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* Merge commit d989ffd10 from llvm git (by Dimitry Andric):Dimitry Andric2020-12-031-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement computeHostNumHardwareThreads() for FreeBSD This retrieves CPU affinity via FreeBSD's cpuset(2) API, and makes LLVM respect affinity settings configured by the user via the cpuset(1) command. In particular, this allows to reduce the number of threads used on machines with high core counts, which can interact badly with parallelized build systems. This is particularly noticable with lld, which spawns lots of threads even for linking e.g. hello_world! This fix is related to PR48193, but does not adress the more fundamental problem, which is that LLVM by default grabs as many CPUs and/or threads as possible. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D92271 Originally by: mjg MFC after: 1 week Notes: svn path=/head/; revision=368309
* Revert r367815, so we can apply the slightly different version thatDimitry Andric2020-12-031-11/+0
| | | | | | | | | | | | | | | | | | landed upstream: For llvm's internal function which retrieves the number of available "hardware threads", use cpuset_getaffinity(2) on FreeBSD, so it will honor processor sets configured by the cpuset(1) command. This should make it possible to avoid e.g. lld creating a huge number of threads on a machine with many cores, even for linking simple programs. This will also be submitted upstream. Submitted by: mjg Notes: svn path=/head/; revision=368308
* For llvm's internal function which retrieves the number of availableDimitry Andric2020-11-181-0/+11
| | | | | | | | | | | | | | | | "hardware threads", use cpuset_getaffinity(2) on FreeBSD, so it will honor processor sets configured by the cpuset(1) command. This should make it possible to avoid e.g. lld creating a huge number of threads on a machine with many cores, even for linking simple programs. This will also be submitted upstream. Submitted by: mjg MFC after: 1 week Notes: svn path=/head/; revision=367815
* Merge commit 354d3106c from llvm git (by Kai Luo):Dimitry Andric2020-11-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [PowerPC] Skip combining (uint_to_fp x) if x is not simple type Current powerpc64le backend hits ``` Combining: t7: f64 = uint_to_fp t6 llc: llvm-project/llvm/include/llvm/CodeGen/ValueTypes.h:291: llvm::MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed. ``` This patch fixes it by skipping combination if `t6` is not simple type. Fixed https://bugs.llvm.org/show_bug.cgi?id=47660. Reviewed By: #powerpc, steven.zhang Differential Revision: https://reviews.llvm.org/D88388 This should fix the llvm assertion mentioned above when building the following ports for powerpc64le: * audio/traverso * databases/percona57-pam-for-mysql * databases/percona57-server * emulators/citra * emulators/citra-qt5 * games/7kaa * graphics/dia * graphics/mandelbulber * graphics/pcl-pointclouds * net-p2p/libtorrent-rasterbar * textproc/htmldoc Requested by: pkubaj MFC after: 3 days Notes: svn path=/head/; revision=367485
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-10-122-3/+9
| | | | | | | | | | release/11.x llvmorg-11.0.0-0-g176249bd673 (aka 11.0.0 release). MFC after: 4 weeks X-MFC-With: r364284 Notes: svn path=/head/; revision=366655
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-10-0111-68/+95
| | | | | | | | | | release/11.x llvmorg-11.0.0-rc5-0-g60a25202a7d. MFC after: 4 weeks X-MFC-With: r364284 Notes: svn path=/head/; revision=366339
* Merge commit 46673763f from llvm git (by Craig Topper):Dimitry Andric2020-09-171-0/+1
| | | | | | | | | | | | | | | | | | | | | [X86] Place new constant node in topological order in X86DAGToDAGISel::matchBitExtract Fixes PR47482 This should fix 'Assertion failed: (Op->getNodeId() != -1 && "Node has already selected predecessor node"), function DoInstructionSelection, file /usr/src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp, line 1149' when compiling part of the project_painter project, while targeting the bdver2 (or higher) CPU. Reported by: jkim MFC after: 6 weeks X-MFC-With: r364284 Notes: svn path=/head/; revision=365849
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-09-1622-328/+363
| | | | | | | | | | release/11.x llvmorg-11.0.0-rc2-91-g6e042866c30. MFC after: 6 weeks X-MFC-With: r364284 Notes: svn path=/head/; revision=365807
* Merge commit e6bb4c8e7 from llvm git (by Craig Topper):Dimitry Andric2020-09-091-1/+1
| | | | | | | | | | | | | | | | | | | | [X86] SSE4_A should only imply SSE3 not SSSE3 in the frontend. SSE4_1 and SSE4_2 due imply SSSE3. So I guess I got confused when switching the code to being table based in D83273. Fixes PR47464 This should fix builds with -march=amdfam10 emitting SSSE3 instructions such as pshufb, which lead to programs crashing with SIGILL on such processors. Reported by: avg MFC after: 6 weeks X-MFC-With: r364284 Notes: svn path=/head/; revision=365507
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-08-2416-61/+264
| | | | | | | | | | release/11.x llvmorg-11.0.0-rc2-0-g414f32a9e86. MFC after: 6 weeks X-MFC-With: r364284 Notes: svn path=/head/; revision=364718
* Merge commit 95e18b2d9d5f from llvm git (by Kang Zhang):Dimitry Andric2020-08-211-2/+2
| | | | | | | | | | | | | | [PowerPC] Fix a typo for InstAlias of mfsprg D77531 has a type for mfsprg, it should be mtsprg. This patch is to fix this typo. This should fix booting powerpc64 kernels, after LLVM 11 was imported. PR: 248763 Notes: svn path=/head/; revision=364455
* Merge commit 4d52ebb9b9c7 from llvm git (by Chen Zheng):Dimitry Andric2020-08-172-20/+35
| | | | | | | | | | | | | | [PowerPC] Make StartMI ignore COPY like instructions. Reviewed By: lkail Differential Revision: https://reviews.llvm.org/D85659 This fixes an assertion failure when building world for powerpc. It was reported upstream as <https://bugs.llvm.org/show_bug.cgi?id=47041>. Notes: svn path=/head/; revision=364314
* Revert r364275, for reapplying the final upstream fix:Dimitry Andric2020-08-172-28/+19
| | | | | | | | | Tentatively apply https://reviews.llvm.org/D85659, which fixes an assertion failure when building world for powerpc. This has been reported upstream as <https://bugs.llvm.org/show_bug.cgi?id=47041>. Notes: svn path=/head/; revision=364313
* Tentatively apply https://reviews.llvm.org/D85659, which fixes anDimitry Andric2020-08-162-19/+28
| | | | | | | | assertion failure when building world for powerpc. This has been reported upstream as <https://bugs.llvm.org/show_bug.cgi?id=47041>. Notes: svn path=/projects/clang1100-import/; revision=364275
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-08-158-52/+110
| | | | | | | release/11.x llvmorg-11.0.0-rc1-47-gff47911ddfc. Notes: svn path=/projects/clang1100-import/; revision=364253
* Reapply r311165:Dimitry Andric2020-08-021-0/+6
| | | | | | | | Disable PDB support in LLVMSymbolizer for now, to avoid llvm-objdump pulling in all the PDB handling code. Notes: svn path=/projects/clang1100-import/; revision=363776
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-07-3125-218/+1221
| | | | | | | release/11.x llvmorg-11.0.0-rc1-25-g903c872b169. Notes: svn path=/projects/clang1100-import/; revision=363746
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-07-3126-379/+409
| | | | | | | release/11.x llvmorg-11-init-20933-g3c1fca803bc. Notes: svn path=/projects/clang1100-import/; revision=363743
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-07-312087-97234/+253298
| | | | | | | | | | | | master 2e10b7a39b9, the last commit before the llvmorg-12-init tag, from which release/11.x was branched. Note that for now, I rolled back all our local changes to make merging easier, and I will reapply the still-relevant ones after updating to 11.0.0-rc1. Notes: svn path=/projects/clang1100-import/; revision=363742
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-06-286-59/+127
| | | | | | | | | | | | | | | | llvmorg-10.0.1-rc2-0-g77d76b71d7d. Also add a few more llvm utilities under WITH_CLANG_EXTRAS: * llvm-dwp, a utility for merging DWARF 5 Split DWARF .dwo files into .dwp (DWARF package files) * llvm-size, a size(1) replacement * llvm-strings, a strings(1) replacement MFC after: 3 weeks Notes: svn path=/head/; revision=362719
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-06-2542-1752/+2135
| | | | | | | | | llvmorg-10.0.0-129-gd24d5c8e308. Getting closer to 10.0.1-rc2. MFC after: 3 weeks Notes: svn path=/head/; revision=362609
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-06-2021-67/+2200
| | | | | | | | | | llvmorg-10.0.0-97-g6f71678ecd2 (not quite 10.0.1 rc2, as more fixes are still pending). MFC after: 3 weeks Notes: svn path=/head/; revision=362445
* Merge commit 0cecafd647cc from llvm git (by Alina Sbirlea):Dimitry Andric2020-06-181-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [BasicAA] Make BasicAA a cfg pass. Summary: Part of the changes in D44564 made BasicAA not CFG only due to it using PhiAnalysisValues which may have values invalidated. Subsequent patches (rL340613) appear to have addressed this limitation. BasicAA should not be invalidated by non-CFG-altering passes. A concrete example is MemCpyOpt which preserves CFG, but we are testing it invalidates BasicAA. llvm-dev RFC: https://groups.google.com/forum/#!topic/llvm-dev/eSPXuWnNfzM Reviewers: john.brawn, sebpop, hfinkel, brzycki Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74353 This fixes an issue with clang's -fintegrated-cc1 feature, which could make it output slightly different assembly code, depending on the way it was invoked. In r361755 we attempted to work around it by disabling the integrated cc1 stage, but it did not solve the root cause for all situations. Extensive testing and bisecting showed that the above change finally makes the output deterministic, even if -fintegrated-cc1 is on. Reported by: Fabian Keil <fk@fabiankeil.de> PR: 246630 MFC after: 3 days Notes: svn path=/head/; revision=362341
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-05-2319-99/+287
| | | | | | | | | llvmorg-10.0.1-rc1-0-gf79cd71e145 (aka 10.0.1 rc1). MFC after: 3 weeks Notes: svn path=/head/; revision=361410
* Merge commit 21e5e1724b75 from llvm git:Ed Maste2020-05-071-7/+2
| | | | | | | | | | | | | | | | | | | | | getMainExecutable: Fix hand-rolled AT_EXECPATH for older FreeBSD Once we hit AT_NULL, we need to bail out of the loop; not just the enclosing switch. This fixes basic usage (e.g. `cc --version`) when AT_EXECPATH isn't present on older branches (e.g. under emu-user-static, at the moment), where we would previously run off the end of ::environ. Patch By: kevans Reviewed By: arichardson Differential Revision: https://reviews.llvm.org/D79239 MFC after: 3 days Notes: svn path=/head/; revision=360801
* In r358396 I merged llvm upstream commit 2e24219d3, which fixed "error:Dimitry Andric2020-05-061-12/+8
| | | | | | | | | | | | | | | unsupported relocation on symbol" when assembling arm 'adr' pseudo instructions. However, the upstream commit did not take big-endian arm into account. Applying the same changes to the big-endian handling is straightforward, thanks to Andrew Turner and Peter Smith for the hint. This will also be submitted upstream. MFC after: immediately, since this fix is meant for stable/11 Notes: svn path=/head/; revision=360697
* Tentatively apply https://reviews.llvm.org/D78877 (by Dave Green):Dimitry Andric2020-04-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | [ARM] Only produce qadd8b under hasV6Ops When compiling for a arm5te cpu from clang, the +dsp attribute is set. This meant we could try and generate qadd8 instructions where we would end up having no pattern. I've changed the condition here to be hasV6Ops && hasDSP, which is what other parts of ARMISelLowering seem to use for similar instructions. Fixed PR45677. This fixes "fatal error: error in backend: Cannot select: t37: i32 = ARMISD::QADD8b t43, t44" when compiling sys/dev/sound/pcm/feeder_mixer.c for armv5. For some reason we do not encounter this on head, but this error popped up while building universes for stable/12. MFC after: 3 days Notes: svn path=/head/; revision=360350
* Merge commit 64b31d96d from llvm git (by Nemanja Ivanovic):Dimitry Andric2020-04-201-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | [PowerPC] Do not attempt to reuse load for 64-bit FP_TO_UINT without FPCVT We call the function that attempts to reuse the conversion without checking whether the target matches the constraints that the callee expects. This patch adds the check prior to the call. Fixes: https://bugs.llvm.org/show_bug.cgi?id=43976 Differential revision: https://reviews.llvm.org/D77564 This should fix 'Assertion failed: ((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) && "i64 FP_TO_UINT is supported only with FPCVT"), function LowerFP_TO_INTForReuse, file /usr/src/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp, line 7276' when building the devel/libslang2 port (and a few others) for PowerPC64. Requested by: pkubaj MFC after: 6 weeks X-MFC-With: 358851 Notes: svn path=/head/; revision=360134
* Revert commit b6cf400aa fro llvm git (by Nemanja Ivanovic):Dimitry Andric2020-04-151-1/+0
| | | | | | | | | | | | | | | | | | Fix bots after a9ad65a2b34f In the last commit, I neglected to initialize the new subtarget feature I added which caused failures on a few bots. This should fix that. This unbreaks the build after r359981, which reverted upstream commit a9ad65a2b34f. Reported by: jhibbits (and jenkins :) MFC after: 6 weeks X-MFC-With: 358851 Notes: svn path=/head/; revision=359994
* Revert commit a9ad65a2b from llvm git (by Nemanja Ivanovic):Dimitry Andric2020-04-153-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | [PowerPC] Change default for unaligned FP access for older subtargets This is a fix for https://bugs.llvm.org/show_bug.cgi?id=40554 Some CPU's trap to the kernel on unaligned floating point access and there are kernels that do not handle the interrupt. The program then fails with a SIGBUS according to the PR. This just switches the default for unaligned access to only allow it on recent server CPUs that are known to allow this. Differential revision: https://reviews.llvm.org/D71954 This upstream commit causes a compiler hang when building certain ports (e.g. security/nss, multimedia/x264) for powerpc64. The hang has been reported in https://bugs.llvm.org/show_bug.cgi?id=45186, but in the mean time it is more convenient to revert the commit. Requested by: jhibbits MFC after: 6 weeks X-MFC-With: 358851 Notes: svn path=/head/; revision=359981
* Merge commit 459e8e948 from llvm git (by Justin Hibbits):Dimitry Andric2020-03-262-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | [PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32 Summary: The linker is free to relax this (relocation R_PPC_GOT_TPREL16) against R_PPC_TLS, if it sees fit (initial exec to local exec). If r0 is used, this can generate execution-invalid code (converts to 'addi %rX, %r0, FOO, which translates in PPC-lingo to li %rX, FOO). Forbid this instead. This fixes static binaries using locales on FreeBSD/powerpc (tested on FreeBSD/powerpcspe). Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D76662 Requested by: jhibbits MFC after: 6 weeks X-MFC-With: 358851 Notes: svn path=/head/; revision=359334
* Merge commit f0990e104 from llvm git (by Justin Hibbits):Dimitry Andric2020-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | [PowerPC]: e500 target can't use lwsync, use msync instead The e500 core has a silicon bug that triggers an illegal instruction program trap on any sync other than msync. Other cores will typically ignore illegal sync types, and the documentation even implies that the 'illegal' bits are ignored. Address this hardware deficiency by only using msync, like the PPC440. Differential Revision: https://reviews.llvm.org/D76614 Requested by: jhibbits MFC after: 6 weeks X-MFC-With: 358851 Notes: svn path=/head/; revision=359333
* Merge commit b8ebc11f0 from llvm git (by Sanjay Patel):Dimitry Andric2020-03-181-7/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [EarlyCSE] avoid crashing when detecting min/max/abs patterns (PR41083) As discussed in PR41083: https://bugs.llvm.org/show_bug.cgi?id=41083 ...we can assert/crash in EarlyCSE using the current hashing scheme and instructions with flags. ValueTracking's matchSelectPattern() may rely on overflow (nsw, etc) or other flags when detecting patterns such as min/max/abs composed of compare+select. But the value numbering / hashing mechanism used by EarlyCSE intersects those flags to allow more CSE. Several alternatives to solve this are discussed in the bug report. This patch avoids the issue by doing simple matching of min/max/abs patterns that never requires instruction flags. We give up some CSE power because of that, but that is not expected to result in much actual performance difference because InstCombine will canonicalize these patterns when possible. It even has this comment for abs/nabs: /// Canonicalize all these variants to 1 pattern. /// This makes CSE more likely. (And this patch adds PhaseOrdering tests to verify that the expected transforms are still happening in the standard optimization pipelines. I left this code to use ValueTracking's "flavor" enum values, so we don't have to change the callers' code. If we decide to go back to using the ValueTracking call (by changing the hashing algorithm instead), it should be obvious how to replace this chunk. Differential Revision: https://reviews.llvm.org/D74285 This fixes an assertion when building the math/gsl port on PowerPC64. Requested by: pkubja MFC after: 6 weeks X-MFC-With: 358851 Notes: svn path=/head/; revision=359086
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2020-03-181-0/+4
| | | | | | | | | | | llvmorg-10.0.0-rc4-5-g52c365aa9ca. The actual release should follow Real Soon Now. PR: 244251 MFC after: 6 weeks Notes: svn path=/head/; revision=359082
* Merge ^/vendor/llvm-project/release-10.x up to its last change (upstreamDimitry Andric2020-03-0520-324/+49
| | | | | | | commit llvmorg-10.0.0-rc3-1-gc290cb61fdc), and bump versions. Notes: svn path=/projects/clang1000-import/; revision=358682
* Merge ^/vendor/llvm-project/release-10.x up to its last change (upstreamDimitry Andric2020-02-2719-165/+306
| | | | | | | commit llvmorg-10.0.0-rc2-70-ge5cb70267e7), and bump versions. Notes: svn path=/projects/clang1000-import/; revision=358399
* Merge commit 2e24219d3 from llvm git (by Hans Wennborg):Dimitry Andric2020-02-272-14/+14
| | | | | | | | | | | | | | | | | | | | | | | [MC][ARM] Resolve some pcrel fixups at assembly time (PR44929) MC currently does not emit these relocation types, and lld does not handle them. Add FKF_Constant as a work-around of some ARM code after D72197. Eventually we probably should implement these relocation types. By Fangrui Song! Differential revision: https://reviews.llvm.org/D72892 This re-enables using the arm 'adr' pseudo instruction on global symbols again. It was broken as a side-effect of upstream commit 2bfee35cb, which lead to "error: unsupported relocation on symbol" when assembling such constructs, which are used in e.g. sys/arm/arm/locore-v[46].S. PR: 244251 Notes: svn path=/projects/clang1000-import/; revision=358396
* Merge ^/vendor/llvm-project/release-10.x up to its last change (upstreamDimitry Andric2020-02-1581-830/+1706
| | | | | | | | commit llvmorg-10.0.0-rc2-0-g90c78073f73), bump versions, and update build glue. Notes: svn path=/projects/clang1000-import/; revision=357964
* Merge ^/vendor/lvm-project/release-10.x up to its last change (upstreamDimitry Andric2020-01-2417-137/+206
| | | | | | | commit llvmorg-10-init-17538-gd11abddb32f). Notes: svn path=/projects/clang1000-import/; revision=357099
* Merge ^/vendor/lvm-project/master up to its last change (upstream commitDimitry Andric2020-01-241395-31050/+67796
| | | | | | | e26a78e70), and resolve conflicts. Notes: svn path=/projects/clang1000-import/; revision=357095
* Reduce diff between stock DWARFContext.cpp and ours.Dimitry Andric2020-01-221-1/+1
| | | | Notes: svn path=/projects/clang1000-import/; revision=356997
* Merge ^/vendor/llvm/dist up to its last change, and resolve conflicts.Dimitry Andric2020-01-221471-38613/+91086
| | | | Notes: svn path=/projects/clang1000-import/; revision=356992
* Merge commit bc4bc5aa0 from llvm git (by Justin Hibbits):Dimitry Andric2020-01-203-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 8548 CPU definition and attributes 8548 CPU is GCC's name for the e500v2, so accept this in clang. The e500v2 doesn't support lwsync, so define __NO_LWSYNC__ for this as well, as GCC does. Differential Revision: https://reviews.llvm.org/D67787 Merge commit ff0311c4b from llvm git (by Justin Hibbits): [PowerPC]: Add powerpcspe target triple subarch component Summary: This allows the use of '-target powerpcspe-unknown-linux-gnu' or 'powerpcspe-unknown-freebsd' to be used, instead of '-target powerpc-unknown-linux-gnu -mspe'. Reviewed By: dim Differential Revision: https://reviews.llvm.org/D72014 Merge commit ba91dffaf from llvm git (by Fangrui Song): [Driver][PowerPC] Move powerpcspe logic from cc1 to Driver Follow-up of D72014. It is more appropriate to use a target feature instead of a SubTypeArch to express the difference. Reviewed By: #powerpc, jhibbits Differential Revision: https://reviews.llvm.org/D72433 commit 36eedfcb3 from llvm git (by Justin Hibbits): [PowerPC] Fix powerpcspe subtarget enablement in llvm backend Summary: As currently written, -target powerpcspe will enable SPE regardless of disabling the feature later on in the command line. Instead, change this to just set a default CPU to 'e500' instead of a generic CPU. As part of this, add FeatureSPE to the e500 definition. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D72673 These are needed to unbreak the build for powerpcspe. Requested by: jhibbits MFC after: 1 week Notes: svn path=/head/; revision=356929
* Merge commit 894f742acb from llvm git (by me):Alex Richardson2020-01-163-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [MIPS][ELF] Use PC-relative relocations in .eh_frame when possible When compiling position-independent executables, we now use DW_EH_PE_pcrel | DW_EH_PE_sdata4. However, the MIPS ABI does not define a 64-bit PC-relative ELF relocation so we cannot use sdata8 for the large code model case. When using the large code model, we fall back to the previous behaviour of generating absolute relocations. With this change clang-generated .o files can be linked by LLD without having to pass -Wl,-z,notext (which creates text relocations). This is simpler than the approach used by ld.bfd, which rewrites the .eh_frame section to convert absolute relocations into relative references. I saw in D13104 that apparently ld.bfd did not accept pc-relative relocations for MIPS ouput at some point. However, I also checked that recent ld.bfd can process the clang-generated .o files so this no longer seems true. Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D72228 Merge commit 8e8ccf47 from llvm git (by me) [MIPS] Don't emit R_(MICRO)MIPS_JALR relocations against data symbols The R_(MICRO)MIPS_JALR optimization only works when used against functions. Using the relocation against a data symbol (e.g. function pointer) will cause some linkers that don't ignore the hint in this case (e.g. LLD prior to commit 5bab291) to generate a relative branch to the data symbol which crashes at run time. Before this patch, LLVM was erroneously emitting these relocations against local-dynamic TLS function pointers and global function pointers with internal visibility. Reviewers: atanasyan, jrtc27, vstefanovic Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D72571 These two changes should allow using lld for MIPS64 (and maybe also MIPS32) by default. The second commit is not strictly necessary for clang+lld since LLD9 will not perform the R_MIPS_JALR optimization (it was only added for 10) but it is probably required in order to use recent ld.bfd. Reviewed By: dim, emaste MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D23203 Notes: svn path=/head/; revision=356789
* Merge commit f46ba4f07 from llvm git (by Simon Atanasyan):Dimitry Andric2020-01-133-2/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [mips] Use less registers to load address of TargetExternalSymbol There is no pattern matched `add hi, (MipsLo texternalsym)`. As a result, loading an address of 32-bit symbol requires two registers and one more additional instruction: ``` addiu $1, $zero, %lo(foo) lui $2, %hi(foo) addu $25, $2, $1 ``` This patch adds the missed pattern and enables generation more effective set of instructions: ``` lui $1, %hi(foo) addiu $25, $1, %lo(foo) ``` Differential Revision: https://reviews.llvm.org/D66771 llvm-svn: 370196 Merge commit 59bb3609f from llvm git (by Simon Atanasyan): [mips] Fix 64-bit address loading in case of applying 32-bit mask to the result If result of 64-bit address loading combines with 32-bit mask, LLVM tries to optimize the code and remove "redundant" loading of upper 32-bits of the address. It leads to incorrect code on MIPS64 targets. MIPS backend creates the following chain of commands to load 64-bit address in the `MipsTargetLowering::getAddrNonPICSym64` method: ``` (add (shl (add (shl (add %highest(sym), %higher(sym)), 16), %hi(sym)), 16), %lo(%sym)) ``` If the mask presents, LLVM decides to optimize the chain of commands. It really does not make sense to load upper 32-bits because the 0x0fffffff mask anyway clears them. After removing redundant commands we get this chain: ``` (add (shl (%hi(sym), 16), %lo(%sym)) ``` There is no patterns matched `(MipsHi (i64 symbol))`. Due a bug in `SYM_32` predicate definition, backend incorrectly selects a pattern for a 32-bit symbols and uses the `lui` instruction for loading `%hi(sym)`. As a result we get incorrect set of instructions with unnecessary 16-bit left shifting: ``` lui at,0x0 R_MIPS_HI16 foo dsll at,at,0x10 daddiu at,at,0 R_MIPS_LO16 foo ``` This patch resolves two problems: - Fix `SYM_32/SYM_64` predicates to prevent selection of patterns dedicated to 32-bit symbols in case of using N64 ABI. - Add missed patterns for 64-bit symbols for `%hi/%lo`. Fix PR42736. Differential Revision: https://reviews.llvm.org/D66228 llvm-svn: 370268 These two commits fix a miscompilation of the kernel for mips64, and should allow clang to be used as the default compiler for mips64. Requested by: arichards MFC after: 3 days Notes: svn path=/head/; revision=356701
* Merge commit d7be3eab5 from llvm git (by Luís Marques):Dimitry Andric2020-01-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | [RISCV] Handle fcopysign(f32, f64) and fcopysign(f64, f32) Summary: Adds tablegen patterns to explicitly handle fcopysign where the magnitude and sign arguments have different types, due to the sign value casts being removed the by DAGCombiner. Support for RV32IF follows in a separate commit. Adds tests for all relevant scenarios except RV32IF. Reviewers: lenary Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D70678 This is a prerequisite for building and linking hard- and soft-float riscv worlds with clang and lld. Requested by: jhb MFC after: 1 week X-MFC-With: r353358 Notes: svn path=/head/; revision=356332
* Merge commit c6b09bff5 from llvm git (by Luís Marques):Dimitry Andric2020-01-031-40/+0
| | | | | | | | | | | | | | | | | | | | | | | | | [RISCV] Fix wrong CFI directives Summary: Removes CFI CFA directives that could incorrectly propagate beyond the basic block they were inteded for. Specifically it removes the epilogue CFI directives. See the branch_and_tail_call test for an example of the issue. Should fix the stack unwinding issues caused by the incorrect directives. Reviewers: asb, lenary, shiva0217 Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D69723 This is a prerequisite for building and linking hard- and soft-float riscv worlds with clang and lld. Requested by: jhb MFC after: 1 week X-MFC-With: r353358 Notes: svn path=/head/; revision=356331
* Merge commit da7b129b1 from llvm git (by James Clarke):Dimitry Andric2020-01-031-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [RISCV] Don't force Local Exec TLS for non-PIC Summary: Forcing Local Exec TLS requires the use of copy relocations. Copy relocations need special handling in the runtime linker when being used against TLS symbols, which is present in glibc, but not in FreeBSD nor musl, and so cannot be relied upon. Moreover, copy relocations are a hack that embed the size of an object in the ABI when it otherwise wouldn't be, and break protected symbols (which are expected to be DSO local), whilst also wasting space, thus they should be avoided whenever possible. As discussed in D70398, RISC-V should move away from forcing Local Exec, and instead use Initial Exec like other targets, with possible linker relaxation to follow. The RISC-V GCC maintainers also intend to adopt this more-conventional behaviour (see https://github.com/riscv/riscv-elf-psabi-doc/issues/122). Reviewers: asb, MaskRay Reviewed By: MaskRay Subscribers: emaste, krytarowski, hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, llvm-commits, bsdjhb Tags: #llvm Differential Revision: https://reviews.llvm.org/D70649 This is a prerequisite for building and linking hard- and soft-float riscv worlds with clang and lld. Requested by: jhb MFC after: 1 week X-MFC-With: r353358 Notes: svn path=/head/; revision=356330
* Merge commit 41449c58c from llvm git (by Roger Ferrer Ibanez):Dimitry Andric2020-01-031-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [RISCV] Fix evaluation of %pcrel_lo The following testcase function: .Lpcrel_label1: auipc a0, %pcrel_hi(other_function) addi a1, a0, %pcrel_lo(.Lpcrel_label1) .p2align 2 # Causes a new fragment to be emitted .type other_function,@function other_function: ret exposes an odd behaviour in which only the %pcrel_hi relocation is evaluated but not the %pcrel_lo. $ llvm-mc -triple riscv64 -filetype obj t.s | llvm-objdump -d -r - <stdin>: file format ELF64-riscv Disassembly of section .text: 0000000000000000 function: 0: 17 05 00 00 auipc a0, 0 4: 93 05 05 00 mv a1, a0 0000000000000004: R_RISCV_PCREL_LO12_I other_function+4 0000000000000008 other_function: 8: 67 80 00 00 ret The reason seems to be that in RISCVAsmBackend::shouldForceRelocation we only consider the fragment but in RISCVMCExpr::evaluatePCRelLo we consider the section. This usually works but there are cases where the section may still be the same but the fragment may be another one. In that case we end forcing a %pcrel_lo relocation without any %pcrel_hi. This patch makes RISCVAsmBackend::shouldForceRelocation use the section, if any, to determine if the relocation must be forced or not. Differential Revision: https://reviews.llvm.org/D60657 This is a prerequisite for building and linking hard- and soft-float riscv worlds with clang and lld. Requested by: jhb MFC after: 1 week X-MFC-With: r353358 Notes: svn path=/head/; revision=356329
* Merge commit 468a0cb5f from llvm git (by Craig Topper):Dimitry Andric2020-01-012-1/+74
| | | | | | | | | | | | | | | | | | | | | | | | | [X86] Add X87 FCMOV support to X86FlagsCopyLowering. Fixes PR44396 Merge commit 86f48999f from llvm git (by Craig Topper): [X86] Fix typo in getCMovOpcode. The 64-bit HasMemoryOperand line was using CMOV32rm instead of CMOV64rm. Not sure how to test this. We have no test coverage that passes true for HasMemoryOperand. This fixes 'Assertion failed: (MI.findRegisterDefOperand(X86::EFLAGS) && "Expected a def of EFLAGS for this instruction!"), function runOnMachineFunction' when compiling the misc/gpsim port for i386. Reported by: yuri Upstream PR: https://bugs.llvm.org/show_bug.cgi?id=44396 MFC after: 1 week Notes: svn path=/head/; revision=356256
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