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* Move all sources from the llvm project into contrib/llvm-project.Dimitry Andric2019-12-20142-177610/+0
| | | | | | | | | | | | | This uses the new layout of the upstream repository, which was recently migrated to GitHub, and converted into a "monorepo". That is, most of the earlier separate sub-projects with their own branches and tags were consolidated into one top-level directory, and are now branched and tagged together. Updating the vendor area to match this layout is next. Notes: svn path=/head/; revision=355940
* Merge commit 8e34dd941 from llvm git (by Sanjay Patel):Dimitry Andric2019-11-071-3/+5
| | | | | | | | | | | | | | | | | | | [x86] avoid crashing when splitting AVX stores with non-simple type (PR43916) The store splitting transform was assuming a simple type (MVT), but that's not necessarily the case as shown in the test. This should fix 'Assertion failed: (isSimple() && "Expected a SimpleValueType!")' when building the security/openssl111 port targeting a CPU that supports AVX, but not AVX2, such as sandybridge. PR: 241747 MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354429
* Pull in r372606 from upstream llvm trunk (by Sanjay Patel):Dimitry Andric2019-09-232-5/+6
| | | | | | | | | | | | | | | | | [x86] fix assert with horizontal math + broadcast of vector (PR43402) https://bugs.llvm.org/show_bug.cgi?id=43402 This should fix 'Assertion failed: ((HOp.getValueType() == MVT::v2f64 || HOp.getValueType() == MVT::v4f64) && HOp.getValueType() == VT && "Unexpected type for h-op"), function foldShuffleOfHorizOp, file contrib/llvm/lib/Target/X86/X86ISelLowering.cpp, line 33661' when building the devel/llvm90 port with CPUTYPE=haswell. PR: 240759 Notes: svn path=/projects/clang900-import/; revision=352629
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb, and openmpDimitry Andric2019-09-191-12/+17
| | | | | | | release 9.0.0 r372316, and update version numbers. Notes: svn path=/projects/clang900-import/; revision=352536
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb, and openmpDimitry Andric2019-09-071-5/+24
| | | | | | | release_90 branch r371301, and update version numbers. Notes: svn path=/projects/clang900-import/; revision=352010
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb, and openmpDimitry Andric2019-09-023-8/+17
| | | | | | | release_90 branch r370514, and update version numbers. Notes: svn path=/projects/clang900-import/; revision=351722
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb, and openmpDimitry Andric2019-09-023-24/+64
| | | | | | | release_90 branch r369369, and update version numbers. Notes: svn path=/projects/clang900-import/; revision=351708
* Merge llvm trunk r366426, resolve conflicts, and update FREEBSD-Xlist.Dimitry Andric2019-08-21148-14118/+18014
| | | | Notes: svn path=/projects/clang900-import/; revision=351344
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt, libc++,Dimitry Andric2019-06-122-2/+6
| | | | | | | | | | | libunwind and openmp to the upstream release_80 branch r363030 (effectively, 8.0.1 rc2). The 8.0.1 release should follow this within a week or so. MFC after: 2 weeks Notes: svn path=/head/; revision=349004
* Revert r308867 (which was originally committed in the clang390-importDimitry Andric2019-03-121-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | project branch): Work around LLVM PR30879, which is about a bad interaction between X86 Call Frame Optimization on i386 and libunwind, by disallowing the optimization for i386-freebsd12. This should fix some instances of broken exception handling when frame pointers are omitted, in particular some unittests run during the build of editors/libreoffice. This hack will be removed as soon as upstream has implemented a more permanent fix for this problem. And indeed, after r345018 and r345019, which updated LLVM libunwind to the most recent version, the above workaround is no longer needed. The upstream commit which fixed this is: https://llvm.org/viewvc/llvm-project?view=revision&revision=292723 Specifically, 32 bit (i386-freebsd) executables optimized with omitted frame pointers and Call Frame Optimization should now behave correctly when a C++ exception is thrown, and the stack is unwound. Upstream PR: https://llvm.org/bugs/show_bug.cgi?id=30879 PR: 236062 MFC after: 1 month X-MFC-With: r344779 Notes: svn path=/head/; revision=345073
* Merge llvm, clang, compiler-rt, libc++, lld, and lldb release_80 branchDimitry Andric2019-03-041-2/+5
| | | | | | | r355313, resolve conflicts, and bump version numbers. Notes: svn path=/projects/clang800-import/; revision=344774
* Merge llvm, clang, compiler-rt, libc++, lld, and lldb release_80 branchDimitry Andric2019-02-251-2/+11
| | | | | | | r354799, resolve conflicts, and bump version numbers. Notes: svn path=/projects/clang800-import/; revision=344548
* Merge ^/head r344178 through r344512.Dimitry Andric2019-02-251-5/+13
|\ | | | | | | Notes: svn path=/projects/clang800-import/; revision=344513
| * Pull in r354756 from upstream llvm trunk (by Craig Topper):Dimitry Andric2019-02-241-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [X86] Fix tls variable lowering issue with large code model Summary: The problem here is the lowering for tls variable. Below is the DAG for the code. SelectionDAG has 11 nodes: t0: ch = EntryToken t8: i64,ch = load<(load 8 from `i8 addrspace(257)* null`, addrspace 257)> t0, Constant:i64<0>, undef:i64 t10: i64 = X86ISD::WrapperRIP TargetGlobalTLSAddress:i64<i32* @x> 0 [TF=10] t11: i64,ch = load<(load 8 from got)> t0, t10, undef:i64 t12: i64 = add t8, t11 t4: i32,ch = load<(dereferenceable load 4 from @x)> t0, t12, undef:i64 t6: ch = CopyToReg t0, Register:i32 %0, t4 And when mcmodel is large, below instruction can NOT be folded. t10: i64 = X86ISD::WrapperRIP TargetGlobalTLSAddress:i64<i32* @x> 0 [TF=10] t11: i64,ch = load<(load 8 from got)> t0, t10, undef:i64 So "t11: i64,ch = load<(load 8 from got)> t0, t10, undef:i64" is lowered to " Morphed node: t11: i64,ch = MOV64rm<Mem:(load 8 from got)> t10, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i32 $noreg, t0" When llvm start to lower "t10: i64 = X86ISD::WrapperRIP TargetGlobalTLSAddress:i64<i32* @x> 0 [TF=10]", it fails. The patch is to fold the load and X86ISD::WrapperRIP. Fixes PR26906 Patch by LuoYuanke Reviewers: craig.topper, rnk, annita.zhang, wxiao3 Reviewed By: rnk Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58336 This should fix "fatal error: error in backend: Cannot select" messages when compiling <ctype.h> functions using -mcmodel=large. Reported by: phk PR: 233143 MFC after: 3 days Notes: svn path=/head/; revision=344503
| * Pull in r352607 from upstream llvm trunk (by Craig Topper):Dimitry Andric2019-02-084-27/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [X86] Add FPSW as a Def on some FP instructions that were missing it. Pull in r353141 from upstream llvm trunk (by Craig Topper): [X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registers we have defined for them. Summary: We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly. This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that. Reviewers: rnk Reviewed By: rnk Subscribers: eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57641 Pull in r353489 from upstream llvm trunk (by Craig Topper): [X86] Add FPCW as a register and start using it as an implicit use on floating point instructions. Summary: FPCW contains the rounding mode control which we manipulate to implement fp to integer conversion by changing the roudning mode, storing the value to the stack, and then changing the rounding mode back. Because we didn't model FPCW and its dependency chain, other instructions could be scheduled into the middle of the sequence. This patch introduces the register and adds it as an implciit def of FLDCW and implicit use of the FP binary arithmetic instructions and store instructions. There are more instructions that need to be updated, but this is a good start. I believe this fixes at least the reduced test case from PR40529. Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor Subscribers: dim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57735 These should fix a problem in clang 7.0 where it would sometimes emit long double floating point instructions in a slightly wrong order, leading to failures in our libm tests. In particular, the cbrt_test test case 'cbrtl_powl' and the trig_test test case 'reduction'. Also bump __FreeBSD_cc_version, to be able to detect this in our test suite. Reported by: lwhsu PR: 234040 Upstream PR: https://bugs.llvm.org/show_bug.cgi?id=40206 MFC after: 1 week Notes: svn path=/head/; revision=343916
* | Pull in r352607 from upstream llvm trunk (by Craig Topper):Dimitry Andric2019-02-1010-105/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [X86] Add FPSW as a Def on some FP instructions that were missing it. Pull in r352608 from upstream llvm trunk (by Craig Topper): [X86] Remove a couple places where we unnecessarily pass 0 to the EmitPriority of some FP instruction aliases. NFC As far as I can tell we already won't emit these aliases due to an operand count check in the tablegen code. Removing these because I couldn't make sense of the inconsistency between fadd and fmul from reading the code. I checked the AsmMatcher and AsmWriter files before and after this change and there were no differences. Pull in r353015 from upstream llvm trunk (by Craig Topper): [X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction. This is a step back from the change I made in r352985. This appears to be more consistent with gcc and objdump behavior. Pull in r353061 from upstream llvm trunk (by Craig Topper): [X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two arguments where on is %st. All of these instructions consume one encoded register and the other register is %st. They either write the result to %st or the encoded register. Previously we printed both arguments when the encoded register was written. And we printed one argument when the result was written to %st. For the stack popping forms the encoded register is always the destination and we didn't print both operands. This was inconsistent with gcc and objdump and just makes the output assembly code harder to read. This patch changes things to always print both operands making us consistent with gcc and objdump. The parser should still be able to handle the single register forms just as it did before. This also matches the GNU assembler behavior. Pull in r353141 from upstream llvm trunk (by Craig Topper): [X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registers we have defined for them. Summary: We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly. This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that. Reviewers: rnk Reviewed By: rnk Subscribers: eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57641 Pull in r353489 from upstream llvm trunk (by Craig Topper): [X86] Add FPCW as a register and start using it as an implicit use on floating point instructions. Summary: FPCW contains the rounding mode control which we manipulate to implement fp to integer conversion by changing the roudning mode, storing the value to the stack, and then changing the rounding mode back. Because we didn't model FPCW and its dependency chain, other instructions could be scheduled into the middle of the sequence. This patch introduces the register and adds it as an implciit def of FLDCW and implicit use of the FP binary arithmetic instructions and store instructions. There are more instructions that need to be updated, but this is a good start. I believe this fixes at least the reduced test case from PR40529. Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor Subscribers: dim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57735 These should fix a problem in clang 7.0 where it would sometimes emit long double floating point instructions in a slightly wrong order, leading to failures in our libm tests. In particular, the cbrt_test test case 'cbrtl_powl' and the trig_test test case 'reduction'. Reported by: lwhsu PR: 234040 Upstream PR: https://bugs.llvm.org/show_bug.cgi?id=40206 Notes: svn path=/projects/clang800-import/; revision=343955
* | Merge llvm, clang, compiler-rt, libc++, lld, and lldb release_80 branchDimitry Andric2019-02-052-1/+13
| | | | | | | | | | | | | | r353167, resolve conflicts, and bump version numbers. Notes: svn path=/projects/clang800-import/; revision=343806
* | Merge llvm release_80 branch r351543, and resolve conflicts.Dimitry Andric2019-01-226-60/+95
| | | | | | | | Notes: svn path=/projects/clang800-import/; revision=343313
* | Merge llvm trunk r351319, resolve conflicts, and update FREEBSD-Xlist.Dimitry Andric2019-01-2086-9254/+16552
|/ | | | Notes: svn path=/projects/clang800-import/; revision=343210
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branchDimitry Andric2018-11-043-5/+25
| | | | | | | | | | r346007 (effectively 7.0.1 rc2), resolve conflicts, and bump version numbers. PR: 230240, 230355 Notes: svn path=/projects/clang700-import/; revision=340125
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branchDimitry Andric2018-09-111-2/+2
| | | | | | | | | r341916, resolve conflicts, and bump version numbers. PR: 230240, 230355 Notes: svn path=/projects/clang700-import/; revision=338597
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branchDimitry Andric2018-08-292-7/+14
| | | | | | | | | r340910, resolve conflicts, and bump version numbers. PR: 230240, 230355 Notes: svn path=/projects/clang700-import/; revision=338391
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branchDimitry Andric2018-08-181-6/+11
| | | | | | | | | r339999, resolve conflicts, and bump version numbers. PR: 230240,230355 Notes: svn path=/projects/clang700-import/; revision=338014
* Merge llvm release_70 branch r338892, and resolve conflicts.Dimitry Andric2018-08-041-0/+4
| | | | Notes: svn path=/projects/clang700-import/; revision=337309
* Merge llvm trunk r338150 (just before the 7.0.0 branch point), andDimitry Andric2018-08-0228-396/+492
| | | | | | | resolve conflicts. Notes: svn path=/projects/clang700-import/; revision=337149
* Merge llvm trunk r338150, and resolve conflicts.Dimitry Andric2018-07-30115-39654/+37313
| | | | Notes: svn path=/projects/clang700-import/; revision=336916
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-06-294-58/+209
| | | | | | | | | | 6.0.1 release (upstream r335540). Relnotes: yes MFC after: 2 weeks Notes: svn path=/head/; revision=335799
* Pull in r329771 from upstream llvm trunk (by Craig Topper):Dimitry Andric2018-04-231-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | [X86] In X86FlagsCopyLowering, when rewriting a memory setcc we need to emit an explicit MOV8mr instruction. Previously the code only knew how to handle setcc to a register. This should fix a crash in the chromium build. This fixes various assertion failures while building ports targeting i386: * www/firefox: isReg() && "This is not a register operand!" * www/iridium, www/qt5-webengine: (I.atEnd() || std::next(I) == def_instr_end()) && "getVRegDef assumes a single definition or no definition" * devel/powerpc64-gcc: FromReg != ToReg && "Cannot replace a reg with itself" Reported by: jbeich PR: 225330, 227686, 227698, 227699 MFC after: 1 week X-MFC-With: r332833 Notes: svn path=/head/; revision=332898
* Recommit r332501, with an additional upstream fix for "Cannot lowerDimitry Andric2018-04-2014-184/+882
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EFLAGS copy that lives out of a basic block!" errors on i386. Pull in r325446 from upstream clang trunk (by me): [X86] Add 'sahf' CPU feature to frontend Summary: Make clang accept `-msahf` (and `-mno-sahf`) flags to activate the `+sahf` feature for the backend, for bug 36028 (Incorrect use of pushf/popf enables/disables interrupts on amd64 kernels). This was originally submitted in bug 36037 by Jonathan Looney <jonlooney@gmail.com>. As described there, GCC also uses `-msahf` for this feature, and the backend already recognizes the `+sahf` feature. All that is needed is to teach clang to pass this on to the backend. The mapping of feature support onto CPUs may not be complete; rather, it was chosen to match LLVM's idea of which CPUs support this feature (see lib/Target/X86/X86.td). I also updated the affected test case (CodeGen/attr-target-x86.c) to match the emitted output. Reviewers: craig.topper, coby, efriedma, rsmith Reviewed By: craig.topper Subscribers: emaste, cfe-commits Differential Revision: https://reviews.llvm.org/D43394 Pull in r328944 from upstream llvm trunk (by Chandler Carruth): [x86] Expose more of the condition conversion routines in the public API for X86's instruction information. I've now got a second patch under review that needs these same APIs. This bit is nicely orthogonal and obvious, so landing it. NFC. Pull in r329414 from upstream llvm trunk (by Craig Topper): [X86] Merge itineraries for CLC, CMC, and STC. These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation. Pull in r329657 from upstream llvm trunk (by Chandler Carruth): [x86] Introduce a pass to begin more systematically fixing PR36028 and similar issues. The key idea is to lower COPY nodes populating EFLAGS by scanning the uses of EFLAGS and introducing dedicated code to preserve the necessary state in a GPR. In the vast majority of cases, these uses are cmovCC and jCC instructions. For such cases, we can very easily save and restore the necessary information by simply inserting a setCC into a GPR where the original flags are live, and then testing that GPR directly to feed the cmov or conditional branch. However, things are a bit more tricky if arithmetic is using the flags. This patch handles the vast majority of cases that seem to come up in practice: adc, adcx, adox, rcl, and rcr; all without taking advantage of partially preserved EFLAGS as LLVM doesn't currently model that at all. There are a large number of operations that techinaclly observe EFLAGS currently but shouldn't in this case -- they typically are using DF. Currently, they will not be handled by this approach. However, I have never seen this issue come up in practice. It is already pretty rare to have these patterns come up in practical code with LLVM. I had to resort to writing MIR tests to cover most of the logic in this pass already. I suspect even with its current amount of coverage of arithmetic users of EFLAGS it will be a significant improvement over the current use of pushf/popf. It will also produce substantially faster code in most of the common patterns. This patch also removes all of the old lowering for EFLAGS copies, and the hack that forced us to use a frame pointer when EFLAGS copies were found anywhere in a function so that the dynamic stack adjustment wasn't a problem. None of this is needed as we now lower all of these copies directly in MI and without require stack adjustments. Lots of thanks to Reid who came up with several aspects of this approach, and Craig who helped me work out a couple of things tripping me up while working on this. Differential Revision: https://reviews.llvm.org/D45146 Pull in r329673 from upstream llvm trunk (by Chandler Carruth): [x86] Model the direction flag (DF) separately from the rest of EFLAGS. This cleans up a number of operations that only claimed te use EFLAGS due to using DF. But no instructions which we think of us setting EFLAGS actually modify DF (other than things like popf) and so this needlessly creates uses of EFLAGS that aren't really there. In fact, DF is so restrictive it is pretty easy to model. Only STD, CLD, and the whole-flags writes (WRFLAGS and POPF) need to model this. I've also somewhat cleaned up some of the flag management instruction definitions to be in the correct .td file. Adding this extra register also uncovered a failure to use the correct datatype to hold X86 registers, and I've corrected that as necessary here. Differential Revision: https://reviews.llvm.org/D45154 Pull in r330264 from upstream llvm trunk (by Chandler Carruth): [x86] Fix PR37100 by teaching the EFLAGS copy lowering to rewrite uses across basic blocks in the limited cases where it is very straight forward to do so. This will also be useful for other places where we do some limited EFLAGS propagation across CFG edges and need to handle copy rewrites afterward. I think this is rapidly approaching the maximum we can and should be doing here. Everything else begins to require either heroic analysis to prove how to do PHI insertion manually, or somehow managing arbitrary PHI-ing of EFLAGS with general PHI insertion. Neither of these seem at all promising so if those cases come up, we'll almost certainly need to rewrite the parts of LLVM that produce those patterns. We do now require dominator trees in order to reliably diagnose patterns that would require PHI nodes. This is a bit unfortunate but it seems better than the completely mysterious crash we would get otherwise. Differential Revision: https://reviews.llvm.org/D45673 Together, these should ensure clang does not use pushf/popf sequences to save and restore flags, avoiding problems with unrelated flags (such as the interrupt flag) being restored unexpectedly. Requested by: jtl PR: 225330 MFC after: 1 week Notes: svn path=/head/; revision=332833
* Revert r332501 for now, as it can cause build failures on i386.Dimitry Andric2018-04-1414-839/+183
| | | | | | | | | | Reported upstream as <https://bugs.llvm.org/show_bug.cgi?id=37133>. Reported by: emaste, ci.freebsd.org PR: 225330 Notes: svn path=/head/; revision=332503
* Pull in r325446 from upstream clang trunk (by me):Dimitry Andric2018-04-1414-183/+839
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [X86] Add 'sahf' CPU feature to frontend Summary: Make clang accept `-msahf` (and `-mno-sahf`) flags to activate the `+sahf` feature for the backend, for bug 36028 (Incorrect use of pushf/popf enables/disables interrupts on amd64 kernels). This was originally submitted in bug 36037 by Jonathan Looney <jonlooney@gmail.com>. As described there, GCC also uses `-msahf` for this feature, and the backend already recognizes the `+sahf` feature. All that is needed is to teach clang to pass this on to the backend. The mapping of feature support onto CPUs may not be complete; rather, it was chosen to match LLVM's idea of which CPUs support this feature (see lib/Target/X86/X86.td). I also updated the affected test case (CodeGen/attr-target-x86.c) to match the emitted output. Reviewers: craig.topper, coby, efriedma, rsmith Reviewed By: craig.topper Subscribers: emaste, cfe-commits Differential Revision: https://reviews.llvm.org/D43394 Pull in r328944 from upstream llvm trunk (by Chandler Carruth): [x86] Expose more of the condition conversion routines in the public API for X86's instruction information. I've now got a second patch under review that needs these same APIs. This bit is nicely orthogonal and obvious, so landing it. NFC. Pull in r329414 from upstream llvm trunk (by Craig Topper): [X86] Merge itineraries for CLC, CMC, and STC. These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation. Pull in r329657 from upstream llvm trunk (by Chandler Carruth): [x86] Introduce a pass to begin more systematically fixing PR36028 and similar issues. The key idea is to lower COPY nodes populating EFLAGS by scanning the uses of EFLAGS and introducing dedicated code to preserve the necessary state in a GPR. In the vast majority of cases, these uses are cmovCC and jCC instructions. For such cases, we can very easily save and restore the necessary information by simply inserting a setCC into a GPR where the original flags are live, and then testing that GPR directly to feed the cmov or conditional branch. However, things are a bit more tricky if arithmetic is using the flags. This patch handles the vast majority of cases that seem to come up in practice: adc, adcx, adox, rcl, and rcr; all without taking advantage of partially preserved EFLAGS as LLVM doesn't currently model that at all. There are a large number of operations that techinaclly observe EFLAGS currently but shouldn't in this case -- they typically are using DF. Currently, they will not be handled by this approach. However, I have never seen this issue come up in practice. It is already pretty rare to have these patterns come up in practical code with LLVM. I had to resort to writing MIR tests to cover most of the logic in this pass already. I suspect even with its current amount of coverage of arithmetic users of EFLAGS it will be a significant improvement over the current use of pushf/popf. It will also produce substantially faster code in most of the common patterns. This patch also removes all of the old lowering for EFLAGS copies, and the hack that forced us to use a frame pointer when EFLAGS copies were found anywhere in a function so that the dynamic stack adjustment wasn't a problem. None of this is needed as we now lower all of these copies directly in MI and without require stack adjustments. Lots of thanks to Reid who came up with several aspects of this approach, and Craig who helped me work out a couple of things tripping me up while working on this. Differential Revision: https://reviews.llvm.org/D45146 Pull in r329673 from upstream llvm trunk (by Chandler Carruth): [x86] Model the direction flag (DF) separately from the rest of EFLAGS. This cleans up a number of operations that only claimed te use EFLAGS due to using DF. But no instructions which we think of us setting EFLAGS actually modify DF (other than things like popf) and so this needlessly creates uses of EFLAGS that aren't really there. In fact, DF is so restrictive it is pretty easy to model. Only STD, CLD, and the whole-flags writes (WRFLAGS and POPF) need to model this. I've also somewhat cleaned up some of the flag management instruction definitions to be in the correct .td file. Adding this extra register also uncovered a failure to use the correct datatype to hold X86 registers, and I've corrected that as necessary here. Differential Revision: https://reviews.llvm.org/D45154 Together, these should ensure clang does not use pushf/popf sequences to save and restore flags, avoiding problems with unrelated flags (such as the interrupt flag) being restored unexpectedly. Requested by: jtl PR: 225330 MFC after: 1 week Notes: svn path=/head/; revision=332501
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-03-041-1/+1
| | | | | | | | | | | | | | | | | 6.0.0 release (upstream r326565). Release notes for llvm, clang and lld will be available here soon: <http://releases.llvm.org/6.0.0/docs/ReleaseNotes.html> <http://releases.llvm.org/6.0.0/tools/clang/docs/ReleaseNotes.html> <http://releases.llvm.org/6.0.0/tools/lld/docs/ReleaseNotes.html> Relnotes: yes MFC after: 3 months X-MFC-With: r327952 PR: 224669 Notes: svn path=/head/; revision=330384
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-02-251-1/+7
| | | | | | | | | | | 6.0.0 (branches/release_60 r325932). This corresponds to 6.0.0 rc3. MFC after: 3 months X-MFC-With: r327952 PR: 224669 Notes: svn path=/head/; revision=329983
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-02-166-181/+142
| | | | | | | | | | | 6.0.0 (branches/release_60 r325330). MFC after: 3 months X-MFC-With: r327952 PR: 224669 Notes: svn path=/head/; revision=329410
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-02-0216-11/+557
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 6.0.0 (branches/release_60 r324090). This introduces retpoline support, with the -mretpoline flag. The upstream initial commit message (r323155 by Chandler Carruth) contains quite a bit of explanation. Quoting: Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre. Summary: First, we need to explain the core of the vulnerability. Note that this is a very incomplete description, please see the Project Zero blog post for details: https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html The basis for branch target injection is to direct speculative execution of the processor to some "gadget" of executable code by poisoning the prediction of indirect branches with the address of that gadget. The gadget in turn contains an operation that provides a side channel for reading data. Most commonly, this will look like a load of secret data followed by a branch on the loaded value and then a load of some predictable cache line. The attacker then uses timing of the processors cache to determine which direction the branch took *in the speculative execution*, and in turn what one bit of the loaded value was. Due to the nature of these timing side channels and the branch predictor on Intel processors, this allows an attacker to leak data only accessible to a privileged domain (like the kernel) back into an unprivileged domain. The goal is simple: avoid generating code which contains an indirect branch that could have its prediction poisoned by an attacker. In many cases, the compiler can simply use directed conditional branches and a small search tree. LLVM already has support for lowering switches in this way and the first step of this patch is to disable jump-table lowering of switches and introduce a pass to rewrite explicit indirectbr sequences into a switch over integers. However, there is no fully general alternative to indirect calls. We introduce a new construct we call a "retpoline" to implement indirect calls in a non-speculatable way. It can be thought of loosely as a trampoline for indirect calls which uses the RET instruction on x86. Further, we arrange for a specific call->ret sequence which ensures the processor predicts the return to go to a controlled, known location. The retpoline then "smashes" the return address pushed onto the stack by the call with the desired target of the original indirect call. The result is a predicted return to the next instruction after a call (which can be used to trap speculative execution within an infinite loop) and an actual indirect branch to an arbitrary address. On 64-bit x86 ABIs, this is especially easily done in the compiler by using a guaranteed scratch register to pass the target into this device. For 32-bit ABIs there isn't a guaranteed scratch register and so several different retpoline variants are introduced to use a scratch register if one is available in the calling convention and to otherwise use direct stack push/pop sequences to pass the target address. This "retpoline" mitigation is fully described in the following blog post: https://support.google.com/faqs/answer/7625886 We also support a target feature that disables emission of the retpoline thunk by the compiler to allow for custom thunks if users want them. These are particularly useful in environments like kernels that routinely do hot-patching on boot and want to hot-patch their thunk to different code sequences. They can write this custom thunk and use `-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this case, on x86-64 thu thunk names must be: ``` __llvm_external_retpoline_r11 ``` or on 32-bit: ``` __llvm_external_retpoline_eax __llvm_external_retpoline_ecx __llvm_external_retpoline_edx __llvm_external_retpoline_push ``` And the target of the retpoline is passed in the named register, or in the case of the `push` suffix on the top of the stack via a `pushl` instruction. There is one other important source of indirect branches in x86 ELF binaries: the PLT. These patches also include support for LLD to generate PLT entries that perform a retpoline-style indirection. The only other indirect branches remaining that we are aware of are from precompiled runtimes (such as crt0.o and similar). The ones we have found are not really attackable, and so we have not focused on them here, but eventually these runtimes should also be replicated for retpoline-ed configurations for completeness. For kernels or other freestanding or fully static executables, the compiler switch `-mretpoline` is sufficient to fully mitigate this particular attack. For dynamic executables, you must compile *all* libraries with `-mretpoline` and additionally link the dynamic executable and all shared libraries with LLD and pass `-z retpolineplt` (or use similar functionality from some other linker). We strongly recommend also using `-z now` as non-lazy binding allows the retpoline-mitigated PLT to be substantially smaller. When manually apply similar transformations to `-mretpoline` to the Linux kernel we observed very small performance hits to applications running typic al workloads, and relatively minor hits (approximately 2%) even for extremely syscall-heavy applications. This is largely due to the small number of indirect branches that occur in performance sensitive paths of the kernel. When using these patches on statically linked applications, especially C++ applications, you should expect to see a much more dramatic performance hit. For microbenchmarks that are switch, indirect-, or virtual-call heavy we have seen overheads ranging from 10% to 50%. However, real-world workloads exhibit substantially lower performance impact. Notably, techniques such as PGO and ThinLTO dramatically reduce the impact of hot indirect calls (by speculatively promoting them to direct calls) and allow optimized search trees to be used to lower switches. If you need to deploy these techniques in C++ applications, we *strongly* recommend that you ensure all hot call targets are statically linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well tuned servers using all of these techniques saw 5% - 10% overhead from the use of retpoline. We will add detailed documentation covering these components in subsequent patches, but wanted to make the core functionality available as soon as possible. Happy for more code review, but we'd really like to get these patches landed and backported ASAP for obvious reasons. We're planning to backport this to both 6.0 and 5.0 release streams and get a 5.0 release with just this cherry picked ASAP for distros and vendors. This patch is the work of a number of people over the past month: Eric, Reid, Rui, and myself. I'm mailing it out as a single commit due to the time sensitive nature of landing this and the need to backport it. Huge thanks to everyone who helped out here, and everyone at Intel who helped out in discussions about how to craft this. Also, credit goes to Paul Turner (at Google, but not an LLVM contributor) for much of the underlying retpoline design. Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41723 MFC after: 3 months X-MFC-With: r327952 PR: 224669 Notes: svn path=/head/; revision=328817
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-02-012-4/+5
| | | | | | | | | | | 6.0.0 (branches/release_60 r323948). MFC after: 3 months X-MFC-With: r327952 PR: 224669 Notes: svn path=/head/; revision=328753
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-01-241-20/+42
| | | | | | | | | | | 6.0.0 (branches/release_60 r323338). MFC after: 3 months X-MFC-With: r327952 PR: 224669 Notes: svn path=/head/; revision=328381
* Pull in r322106 from upstream llvm trunk (by Alexey Bataev):Dimitry Andric2018-01-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | [COST]Fix PR35865: Fix cost model evaluation for shuffle on X86. Summary: If the vector type is transformed to non-vector single type, the compile may crash trying to get vector information about non-vector type. Reviewers: RKSimon, spatel, mkuper, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41862 This should fix "Not a vector MVT!" errors when building the games/dhewm3 port. Reported by: jbeich PR: 225271 Notes: svn path=/head/; revision=328146
* Pull in r322623 from upstream llvm trunk (by Andrew V. Tischenko):Dimitry Andric2018-01-171-0/+7
| | | | | | | | | | | | | | Allow usage of X86-prefixes as separate instrs. Differential Revision: https://reviews.llvm.org/D42102 This should fix parse errors when x86 prefixes (such as 'lock' and 'rep') are followed by various non-mnemonic tokens, e.g. comments, .byte directives and labels. PR: 224669,225054 Notes: svn path=/head/; revision=328090
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_60 r321788,Dimitry Andric2018-01-067-272/+386
| | | | | | | update build glue and version numbers. Notes: svn path=/projects/clang600-import/; revision=327657
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ trunk r321545,Dimitry Andric2017-12-299-117/+129
| | | | | | | | update build glue and version numbers, add new intrinsics headers, and update OptionalObsoleteFiles.inc. Notes: svn path=/projects/clang600-import/; revision=327330
* Merge llvm trunk r321414 to contrib/llvm.Dimitry Andric2017-12-2414-352/+410
| | | | Notes: svn path=/projects/clang600-import/; revision=327134
* Merge llvm trunk r321017 to contrib/llvm.Dimitry Andric2017-12-20108-12365/+40965
| | | | Notes: svn path=/projects/clang600-import/; revision=327023
* Upgrade our copies of clang, llvm, lldb and libc++ to r319231 from theDimitry Andric2017-12-031-0/+17
| | | | | | | | | upstream release_50 branch. This corresponds to 5.0.1 rc2. MFC after: 2 weeks Notes: svn path=/head/; revision=326496
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2017-09-061-22/+45
| | | | | | | | | | | | | | | | 5.0.0 release (upstream r312559). Release notes for llvm, clang and lld will be available here soon: <http://releases.llvm.org/5.0.0/docs/ReleaseNotes.html> <http://releases.llvm.org/5.0.0/tools/clang/docs/ReleaseNotes.html> <http://releases.llvm.org/5.0.0/tools/lld/docs/ReleaseNotes.html> Relnotes: yes MFC after: 1 month X-MFC-with: r321369 Notes: svn path=/head/; revision=323245
* Upgrade our copies of clang, llvm, lldb and compiler-rt to r311606 fromDimitry Andric2017-08-243-2449/+44
| | | | | | | | | | | | | | the upstream release_50 branch. As of this version, lib/msun's trig test should also work correctly again (see bug 220989 for more information). PR: 220989 MFC after: 2 months X-MFC-with: r321369 Notes: svn path=/head/; revision=322855
* Upgrade our copies of clang, llvm, lld and libc++ to r311219 from theDimitry Andric2017-08-212-19/+80
| | | | | | | | | | upstream release_50 branch. MFC after: 2 months X-MFC-with: r321369 Notes: svn path=/head/; revision=322740
* Upgrade our copies of clang, llvm and libc++ to r310316 from theDimitry Andric2017-08-092-4/+10
| | | | | | | | | | upstream release_50 branch. MFC after: 2 months X-MFC-with: r321369 Notes: svn path=/head/; revision=322320
* Upgrade our copies of clang, llvm, lld and lldb to r309439 from theDimitry Andric2017-07-302-3/+7
| | | | | | | | | | upstream release_50 branch. This is just after upstream's 5.0.0-rc1. MFC after: 2 months X-MFC-with: r321369 Notes: svn path=/head/; revision=321723
* Pull in r308891 from upstream llvm trunk (by Benjamin Kramer):Dimitry Andric2017-07-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [CodeGenPrepare] Cut off FindAllMemoryUses if there are too many uses. This avoids excessive compile time. The case I'm looking at is Function.cpp from an old version of LLVM that still had the giant memcmp string matcher in it. Before r308322 this compiled in about 2 minutes, after it, clang takes infinite* time to compile it. With this patch we're at 5 min, which is still bad but this is a pathological case. The cut off at 20 uses was chosen by looking at other cut-offs in LLVM for user scanning. It's probably too high, but does the job and is very unlikely to regress anything. Fixes PR33900. * I'm impatient and aborted after 15 minutes, on the bug report it was killed after 2h. Pull in r308986 from upstream llvm trunk (by Simon Pilgrim): [X86][CGP] Reduce memcmp() expansion to 2 load pairs (PR33914) D35067/rL308322 attempted to support up to 4 load pairs for memcmp inlining which resulted in regressions for some optimized libc memcmp implementations (PR33914). Until we can match these more optimal cases, this patch reduces the memcmp expansion to a maximum of 2 load pairs (which matches what we do for -Os). This patch should be considered for the 5.0.0 release branch as well Differential Revision: https://reviews.llvm.org/D35830 These fix a hang (or extremely long compile time) when building older LLVM ports. Reported by: antoine PR: 219139 Notes: svn path=/head/; revision=321664
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