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path: root/sys/arm/arm/cpufunc.c
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* Use armv7_drain_writebuf() and armv7_context_switch, instead of the arm11Olivier Houchard2013-01-151-2/+2
* Replace generic ARM11 option with more specificOleksandr Tymoshenko2012-12-201-45/+177
* Don't include arm/xscale/i8134x/i81342reg.h when we're compiling LINT.Marcel Moolenaar2012-11-271-1/+7
* Make it clear the L2 ops are filled for any cpu using a PL310 cache, not justOlivier Houchard2012-11-141-1/+2
* Use the arrmv7 version for flushID too, as it does something different for SMP.Olivier Houchard2012-11-141-1/+1
* Support identification of new PJ4B cores.Grzegorz Bernacki2012-09-141-2/+3
* Add support for ARM11 cpufuncOleksandr Tymoshenko2012-08-261-17/+86
* Merging projects/armv6, part 1Oleksandr Tymoshenko2012-08-151-76/+450
* Final whitespace trim.Warner Losh2012-06-131-17/+17
* Add basic cpu_sleep() support for Marvell SoCs. This drops my SheevaPlug'sAlexander Motin2010-09-181-1/+4
* Add support for FA626TE.Kevin Lo2010-05-041-51/+48
* Show the cpu info for fa526Kevin Lo2010-02-201-1/+2
* Add support for Cavium Econa CNS11XX ARM boards. These boards wereRui Paulo2010-01-041-1/+139
* Remove remaining bits of performance counter support.Rui Paulo2009-10-031-24/+0
* Remove performance counter headers. This code came from NetBSD, but ourRui Paulo2009-10-021-29/+0
* Make dcache_inv_range() point to the proper routines on ARM9 and ARM9E/ARM10.Rafal Jaworowski2009-07-211-2/+2
* - Add support for PXA270 cpu.Stanislav Sedov2009-05-051-0/+1
* Fix confusing naming of Marvell ARM CPU specific routines.Rafal Jaworowski2009-01-091-13/+13
* Merge WIP from p4:Sam Leffler2008-12-131-1/+1
* Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571.Rafal Jaworowski2008-10-131-3/+90
* Fixes for ARM9/ARM10 :Olivier Houchard2007-11-281-1/+4
* Add entries for the L2 cache-related functions for armv5.Olivier Houchard2007-11-081-0/+5
* Don't define get_cachetype() for CPU_ARM9E unless it's going to be used.Kevin Lo2007-10-311-1/+1
* Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. NotWarner Losh2007-10-181-4/+124
* Add cast to silent gcc warnings.Olivier Houchard2007-08-071-24/+24
* Add a new set of functions to handle L2 cache. Make them no-op for everyOlivier Houchard2007-07-271-7/+47
* Use uma_set_align().Olivier Houchard2007-02-111-13/+17
* First bits of Xscale core 3 support (the VM bits are far from being optimalOlivier Houchard2006-11-301-0/+4
* Gateworks Avila board support:Sam Leffler2006-11-191-1/+0
* Identify the xscale 81342.Olivier Houchard2006-11-071-5/+77
* style(9) cleanup.Kevin Lo2006-10-211-3/+0
* Finally bring it support for the i80219 XScale processor.Olivier Houchard2006-08-241-15/+26
* MFp4: Use CPU_CONTROL_ROUNDROBIN for arm9, it seems to give marginallyOlivier Houchard2006-04-091-1/+2
* Remove bits specific to CPUs we won't support (< armv4).Olivier Houchard2005-05-251-328/+10
* MFp4: Setup arm9 to write back by default.Olivier Houchard2005-05-241-13/+17
* Support high vectors for arm9.Olivier Houchard2005-02-181-0/+2
* Start all license statements with /*-Warner Losh2005-01-051-1/+1
* Remove __P here too.Tom Rhodes2004-11-101-3/+3
* Call pmap_pte_init_arm9 instead of pmap_pte_init_generic ifOlivier Houchard2004-11-051-0/+4
* Use the right path for xscale files.Olivier Houchard2004-09-231-7/+6
* Uncomment the vector relocation code.Olivier Houchard2004-07-201-4/+2
* Import FreeBSD/arm kernel bits.Olivier Houchard2004-05-141-0/+2177
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