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* Enable ROUTE_MPATH support in GENERIC kernels.Alexander V. Chernikov2020-12-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Ability to load-balance traffic over multiple path is a must-have thing for routers. It may be used by the servers to balance outgoing traffic over multiple default gateways. The previous implementation, RADIX_MPATH stayed in the shadow for too long. It was not well maintained, which lead us to a vicious circle - people were using non-contiguous mask or firewalls to achieve similar goals. As a result, some routing daemons implementation still don't have multipath support enabled for FreeBSD. Turning on ROUTE_MPATH by default would fix it. It will allow to reduce networking feature gap to other operating systems. Linux and OpenBSD enabled similar support at least 5 years ago. ROUTE_MPATH does not consume memory unless actually used. It enables around ~1k LOC. It does not bring any behaviour changes for userland. Additionally, feature is (temporarily) turned off by the net.route.multipath sysctl defaulting to 0. Differential Revision: https://reviews.freebsd.org/D27428 Notes: svn path=/head/; revision=368648
* [PowerPC] Floating-point exception trap followupBrandon Bergren2020-12-133-16/+13
| | | | | | | | | | | | | | * Fix incorrect operation on 32-bit caused by incorrectly-sized storage for a temporary FPSCR. * Fix several whitespace problems. * Don't try to enable VSX during cleanup_fpscr(). Reviewed by: alfredo, jhibbits (earlier version) Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D27453 Notes: svn path=/head/; revision=368604
* Add CFI start/end proc directives to arm64, i386, and ppcConrad Meyer2020-12-0517-11/+165
| | | | | | | | | | | | | | Follow-up to r353959 and r368070: do the same for other architectures. arm32 already seems to use its own .fnstart/.fnend directives, which appear to be ARM-specific variants of the same thing. Likewise, MIPS uses .frame directives. Reviewed by: arichardson Differential Revision: https://reviews.freebsd.org/D27387 Notes: svn path=/head/; revision=368354
* [PowerPC64LE] Fix LE VSX/fpr interopBrandon Bergren2020-12-032-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | In the PCB struct, we need to match the VSX register file layout correctly, as the VSRs shadow the FPRs. In LE, we need to have a dword of padding before the fprs so they end up on the correct side, as the struct may be manipulated by either the FP routines or the VSX routines. Additionally, when saving and restoring fprs, we need to explicitly target the fpr union member so it gets offset correctly on LE. Fixes weirdness with FP registers in VSX-using programs (A FPR that was saved by the FP routines but restored by the VSX routines was becoming 0 due to being loaded to the wrong side of the VSR.) Original patch by jhibbits. Reviewed by: jhibbits Differential Revision: https://reviews.freebsd.org/D27431 Notes: svn path=/head/; revision=368290
* Make MAXPHYS tunable. Bump MAXPHYS to 1M.Konstantin Belousov2020-11-282-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace MAXPHYS by runtime variable maxphys. It is initialized from MAXPHYS by default, but can be also adjusted with the tunable kern.maxphys. Make b_pages[] array in struct buf flexible. Size b_pages[] for buffer cache buffers exactly to atop(maxbcachebuf) (currently it is sized to atop(MAXPHYS)), and b_pages[] for pbufs is sized to atop(maxphys) + 1. The +1 for pbufs allow several pbuf consumers, among them vmapbuf(), to use unaligned buffers still sized to maxphys, esp. when such buffers come from userspace (*). Overall, we save significant amount of otherwise wasted memory in b_pages[] for buffer cache buffers, while bumping MAXPHYS to desired high value. Eliminate all direct uses of the MAXPHYS constant in kernel and driver sources, except a place which initialize maxphys. Some random (and arguably weird) uses of MAXPHYS, e.g. in linuxolator, are converted straight. Some drivers, which use MAXPHYS to size embeded structures, get private MAXPHYS-like constant; their convertion is out of scope for this work. Changes to cam/, dev/ahci, dev/ata, dev/mpr, dev/mpt, dev/mvs, dev/siis, where either submitted by, or based on changes by mav. Suggested by: mav (*) Reviewed by: imp, mav, imp, mckusick, scottl (intermediate versions) Tested by: pho Sponsored by: The FreeBSD Foundation Differential revision: https://reviews.freebsd.org/D27225 Notes: svn path=/head/; revision=368124
* [POWERPC] print uprintf_signal 'type' field in hexAlfredo Dal'Ava Junior2020-11-201-1/+1
| | | | | | | | | | Print 'type' field in hex to improve readability Reviewed by: jhibbits Differential Revision: https://reviews.freebsd.org/D27294 Notes: svn path=/head/; revision=367908
* vm_phys: Try to clean up NUMA KPIsMark Johnston2020-11-192-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | It can useful for code outside the VM system to look up the NUMA domain of a page backing a virtual or physical address, specifically when creating NUMA-aware data structures. We have _vm_phys_domain() for this, but the leading underscore implies that it's an internal function, and vm_phys.h has dependencies on a number of other headers. Rename vm_phys_domain() to vm_page_domain(), and _vm_phys_domain() to vm_phys_domain(). Make the latter an inline function. Add _vm_phys.h and define struct vm_phys_seg there so that it's easier to use in other headers. Include it from vm_page.h so that vm_page_domain() can be defined there. Include machine/vmparam.h from _vm_phys.h since it depends directly on some constants defined there. Reviewed by: alc Reviewed by: dougm, kib (earlier versions) Differential Revision: https://reviews.freebsd.org/D27207 Notes: svn path=/head/; revision=367828
* [POWERPC] fix signal race conditionAlfredo Dal'Ava Junior2020-11-171-4/+3
| | | | | | | | | | | | | | r367416 should have called save_fpu() before kern_sigprocmask to avoid race condition Thanks jhibbits and bdragon for pointing it out Reviewed by: jhibbits Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D27241 Notes: svn path=/head/; revision=367760
* [PowerPC] Don't overwrite vm.pmap sysctl nodeLeandro Lupori2020-11-174-13/+17
| | | | | | | | | | | | | | | | | | After r367417, both mmu_oea64 and mmu_radix were defining the vm.pmap sysctl node, resulting in the later definition hiding the properties of the previous one. Avoid this issue by defining vm.pmap in a common source file and declaring it where needed. This change also standardizes the tunable name used to enable superpages and change its default to disabled on radix MMU, because it still has some issues with superpages. Reviewed by: bdragon, jhibbits Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D27156 Notes: svn path=/head/; revision=367758
* [PowerPC64LE] Radix MMU fixes for LE.Brandon Bergren2020-11-131-199/+222
| | | | | | | | | | | | | | | | There were many, many endianness fixes needed for Radix MMU. The Radix pagetable is stored in BE (as it is read and written to by the MMU hw), so we need to convert back and forth every time we interact with it when running in LE. With these changes, I can successfully boot with radix enabled on POWER9 hw. Reviewed by: luporl, jhibbits Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D27181 Notes: svn path=/head/; revision=367644
* [PowerPC] Fix powerpc64le boot after HPT superpages additionBrandon Bergren2020-11-081-7/+9
| | | | | | | | | | | | | | | The HPT is always stored in big-endian, as it is accessed directly by the hardware as well as the kernel. As such, it is necessary to convert values to and from native endian when running on LE. Some unconverted accesses snuck in accidentally with r367417. Apply the appropriate conversions to fix boot hanging on powerpc64le. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=367496
* Make powerpc use MAXARGS (defined as 8) instead of hardcoding '10'.Edward Tomasz Napierala2020-11-061-1/+2
| | | | | | | | | | | | This brings its 'struct syscall_args' in sync with other architectures. Reviewed by: bdragon, jhibbits MFC after: 2 weeks Sponsored by: EPSRC Differential Revision: https://reviews.freebsd.org/D26605 Notes: svn path=/head/; revision=367430
* Fix powerpc and LINT buildsLeandro Lupori2020-11-062-1/+4
| | | | | | | | | | | | Fix build errors introduced by r367417 and r367390: - Guard label reached only by powerpc64 - Guard vm_reserv_level_iffullpop call, that is not defined on powerpc variants that don't support superpages - Add missing hwpmc file, for when hwpmc is built into kernel Notes: svn path=/head/; revision=367427
* Implement superpages for PowerPC64 (HPT)Leandro Lupori2020-11-0610-159/+1581
| | | | | | | | | | | | | | | | | | | | | | | | | | This change adds support for transparent superpages for PowerPC64 systems using Hashed Page Tables (HPT). All pmap operations are supported. The changes were inspired by RISC-V implementation of superpages, by @markj (r344106), but heavily adapted to fit PPC64 HPT architecture and existing MMU OEA64 code. While these changes are not better tested, superpages support is disabled by default. To enable it, use vm.pmap.superpages_enabled=1. In this initial implementation, when superpages are disabled, system performance stays at the same level as without these changes. When superpages are enabled, buildworld time increases a bit (~2%). However, for workloads that put a heavy pressure on the TLB the performance boost is much bigger (see HPC Challenge and pgbench on D25237). Reviewed by: jhibbits Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D25237 Notes: svn path=/head/; revision=367417
* [POWERPC] Floating-Point Exception trap supportAlfredo Dal'Ava Junior2020-11-066-15/+119
| | | | | | | | | | | | | | Add support for Floating-Point Exception traps on 32 and 64 bit platforms. Also make sure to clean FPSCR on EXEC and thread exit Author of initial version: Renato Riolino <renato.riolino@eldorad.org.br> Reviewed by: jhibbits Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D23623 Notes: svn path=/head/; revision=367416
* Fix powerpc and powerpcspe buildsLeandro Lupori2020-11-051-7/+7
| | | | | | | | This change fixes 32-bit PowerPC builds, that r367390 broke (shift count >= width of type). Notes: svn path=/head/; revision=367397
* [PowerPC] hwpmc: add support for POWER8/9 PMCsLeandro Lupori2020-11-051-0/+1
| | | | | | | | | | | | | | | This change adds support for POWER8 and POWER9 PMCs (bare metal and pseries). All PowerISA 2.07B non-random events are supported. Implementation was based on that of PPC970. Reviewed by: jhibbits Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D26110 Notes: svn path=/head/; revision=367390
* [PowerPC] Make PPC 970 PMC SPRs the standard onesLeandro Lupori2020-11-052-65/+86
| | | | | | | | | | | | | | And add a _74XX suffix to 74XX SPRs. This is a preparation for adding support to POWER8/9 PMCs, which have most SPRs equal to 970 ones. Reviewed by: jhibbits Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D26532 Notes: svn path=/head/; revision=367383
* Tidy up the #includes. Recent changes, such as the introduction ofAlan Cox2020-11-021-9/+2
| | | | | | | | | | | VM_ALLOC_WAITOK and vm_page_unwire_noq(), have eliminated the need for many of the #includes. Reviewed by: kib, markj Differential Revision: https://reviews.freebsd.org/D27052 Notes: svn path=/head/; revision=367281
* Avoid dump_avail[] redefinition.Konstantin Belousov2020-10-145-2/+7
| | | | | | | | | | | | | Move dump_avail[] extern declaration and inlines into a new header vm/vm_dumpset.h. This fixes default gcc build for mips. Reviewed by: alc, scottph Tested by: kevans (previous version) Sponsored by: The FreeBSD Foundation Differential revision: https://reviews.freebsd.org/D26741 Notes: svn path=/head/; revision=366711
* random(4) FenestrasX: Push root seed version to arc4random(3)Conrad Meyer2020-10-102-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Push the root seed version to userspace through the VDSO page, if the RANDOM_FENESTRASX algorithm is enabled. Otherwise, there is no functional change. The mechanism can be disabled with debug.fxrng_vdso_enable=0. arc4random(3) obtains a pointer to the root seed version published by the kernel in the shared page at allocation time. Like arc4random(9), it maintains its own per-process copy of the seed version corresponding to the root seed version at the time it last rekeyed. On read requests, the process seed version is compared with the version published in the shared page; if they do not match, arc4random(3) reseeds from the kernel before providing generated output. This change does not implement the FenestrasX concept of PCPU userspace generators seeded from a per-process base generator. That change is left for future discussion/work. Reviewed by: kib (previous version) Approved by: csprng (me -- only touching FXRNG here) Differential Revision: https://reviews.freebsd.org/D22839 Notes: svn path=/head/; revision=366622
* Create in-tree LINT filesWarner Losh2020-10-093-5/+14
| | | | | | | | | | | | | | | | | | Now that config(8) has supported include for 19 years, transition to including the NOTES files. include support didn't exist at the time, nor did the envvar stuff recently added. Now that it does, eliminate the building of LINT files by just including everything you need. Note: This may cause conflicts with updating in some cases. find sys -name LINT\* -rm is suggested across this commit to remove the generated LINT files. Reviewed by: kevans Differential Revision: https://reviews.freebsd.org/D26540 Notes: svn path=/head/; revision=366559
* [PowerPC] add machdep.uprintf_signal sysctlAlfredo Dal'Ava Junior2020-10-081-0/+13
| | | | | | | | | | | | Add support for sysctl 'machdep.uprintf_signal' that prints debugging information on trap signal. Reviewed by: jhibbits, luporl, bdragon Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D26004 Notes: svn path=/head/; revision=366548
* Print symbol index for unsupported relocation typesMitchell Horne2020-10-072-13/+13
| | | | | | | | | | | | | | | It is unlikely, but possible, that an unrecognized or unsupported relocation type is encountered while trying to load a kernel module. If this occurs we should offer the symbol index as a hint to the user. While here, fix some small style issues. Reviewed by: markj, kib (amd64 part, in D26701) Sponsored by: NetApp, Inc. Sponsored by: Klara, Inc. Notes: svn path=/head/; revision=366519
* Fix LINT: Add backlight to NOTESEmmanuel Vadot2020-10-021-0/+3
| | | | Notes: svn path=/head/; revision=366382
* Get rid of sa->narg. It serves no purpose; use sa->callp->sy_narg instead.Edward Tomasz Napierala2020-09-272-7/+6
| | | | | | | | | Reviewed by: kib Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D26458 Notes: svn path=/head/; revision=366205
* Add a vmparam.h constant indicating pmap support for large pages.Mark Johnston2020-09-231-0/+5
| | | | | | | | | | | Enable SHM_LARGEPAGE support on arm64. Reviewed by: alc, kib Sponsored by: Juniper Networks, Inc., Klara, Inc. Differential Revision: https://reviews.freebsd.org/D26467 Notes: svn path=/head/; revision=366090
* [PowerPC64LE] Fix RTAS LE calls in pseries.Brandon Bergren2020-09-232-6/+27
| | | | | | | | | | | Similar to OPAL calls, switch to big endian to do calls to RTAS. (Missed this one when I was doing the bulk commit of PowerPC64LE support.) Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366063
* [PowerPC64LE] Fix sleeping on POWER8.Brandon Bergren2020-09-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | Due to enter_idle_powerx fabricating a MSR from scratch, it is necessary for it to care about the endianness, so we don't accidentally switch endian the first time we idle a thread. Took about five seconds to spot after seeing an unmangled backtrace. The hard bit was needing to temporarily set up a mutex to sort out the logjam that happens when every thread simultaneously wakes up in the wrong endian due to the panic IPI and panics, leaving what I can best describe as "alphabet soup" on the console. Luckily, I already had a patch sitting around to do that. This brings POWER8 up to equivilence with POWER9 on PPC64LE. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366057
* [PowerPC64LE] Fix AP spinup on powernv.Brandon Bergren2020-09-232-0/+16
| | | | | | | | | | | | | | | | | | | | OPAL unconditionally enters secondary CPUs with only HV and SF set. I tried writing a secondary entry point instead, but OPAL rejected it and I am unsure why, so I resorted to making the system reset interrupt endian-flexible. This means we take a slight performance hit on wakeup on LE, but it is a good stopgap until we can figure out a reliable way to make OPAL enter where we want it to. It probably makes sense to have it around anyway, because I can imagine scenarios where the cpu resets itself to BE and does a software reset. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366053
* [PowerPC64LE] Endian fix for opal_hmi.cBrandon Bergren2020-09-231-1/+1
| | | | | | | | | Another boring one. We need to endian swap before checking flags. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366051
* [PowerPC64LE] Get XIVE up and running.Brandon Bergren2020-09-232-1/+14
| | | | | | | | | | | | | More endian conversion. * Install TCEs correctly (i.e. in big endian) * Convert to big endian and back when setting up queue pages and IRQs. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366049
* [PowerPC64LE] Endian fix for opal_dev.c.Brandon Bergren2020-09-231-1/+1
| | | | | | | | | | Not much to say here, another missing be64toh() in memory that was written from OPAL. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366048
* [PowerPC64LE] Endian fixes for opal_pci.c.Brandon Bergren2020-09-231-1/+3
| | | | | | | | | | | | | | | Since OPAL runs in big endian, any data being passed back and forth via memory instead of registers needs to be byteswapped. From my notes during development: "A good way to find candidates is to look for vtophys() in opal_call() parameters. The memory being passed will be written into in BE." Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366047
* [PowerPC64LE] Implement endian-independent dword atomic PTE lock.Brandon Bergren2020-09-231-1/+33
| | | | | | | | | | | | | | | It's much easier to implement this in an endian-independent way when we don't also have to worry about masking half of the dword off. Given that this code ran on a machine that ran a poudriere bulk with no kernel oddities, I am relatively certain it is correctly implemented. ;) This should be a minor performance boost on BE as well. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366046
* [PowerPC64LE] Fix endian conversion bugs in moea64.Brandon Bergren2020-09-231-4/+4
| | | | | | | | | | | | For a body of code that had its endian conversion bits written blind without the ability to test, moea64 was VERY close to being correct. There were only four instances where the existing code was getting it wrong. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366045
* [PowerPC64LE] Initial GENERIC64LE kernel config.Brandon Bergren2020-09-231-0/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is slightly stripped down from GENERIC64, as PowerMac G5 machines are incapable of running in LE mode (so we can skip the Mac drivers.) While technically POWER6 and POWER7 have the hardware capability of running in LE mode, they have a tendency to trap excessively when a load/store is misaligned. (an extremely common occurrence in LE code, and one of the main reasons I consider BE to be superior, as it turns potential security issues into immediately obvious mangled numbers.) Additionally, there was no mechanism to control what endian interrupts are delivered in, so supporting LE operation on POWER6 and POWER7 involves some really dirty tricks in the interrupt vectors that I would rather avoid. IBM drew the line in the sand at POWER8 some time around 2013, embracing full support for LE in the platform, and making a push across the board for LE code to target POWER8 as a minimum requirement. As such, usage of LE kernels on POWER6 and POWER7 is practically nil, despite it being technically possible to do. The so-called "TRUELE" feature bit which is the baseline requirement for needed for PowerPC64LE was introduced in POWER8. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366043
* [PowerPC64LE] powernv ILE setup code.Brandon Bergren2020-09-232-0/+5
| | | | | | | | | | | | | | | | | When running without a hypervisor, we need to set the ILE bit in the LPCR ourselves. For the boot processor, handle it in powernv_attach() like we do for other LPCR bits. No change for the APs, as they will use the lpcr global to set up their own LPCR when they do their own cpudep_ap_early_bootstrap() and pick up this automatically. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366041
* [PowerPC64LE] LE opal_call() implementationBrandon Bergren2020-09-232-1/+20
| | | | | | | | | | | OPAL runs in big endian, so we need to rfid into it to switch endian atomically when branching to it, and we need to do the RETURN_TO_NATIVE_ENDIAN dance when it returns to us. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366040
* [PowerPC64LE] Fix endianness issues in phyp_vscsi.Brandon Bergren2020-09-231-31/+40
| | | | | | | | | | | | | Unlike virtio, which in legacy mode is guest endian, the hypervisor vscsi interface operates in big endian, so we must convert back and forth in several places. These changes are enough to attach a rootdisk. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366038
* [PowerPC64LE] Work around qemu TCG bug in mtmsrd emulation.Brandon Bergren2020-09-234-0/+23
| | | | | | | | | | | | | | | | | | | | | | The TCG implementation of mtmsrd in qemu blindly copies the entire register to the MSR, instead of the specific bit positions listed in the ISA. This means that qemu will prematurely switch endian out from under the running code instead of waiting for the rfid, causing an immediate trap as it attempts to interpret the next instruction in the wrong endianness. To work around this, ensure PSL_LE is still set before doing the mtmsrd. In the future, we may wish to just turn off translation and unconditionally use rfid to switch to the ofmsr instead of quasi-switching to the ofmsr. Add a new platform option so this can be disabled. (And so that we can conditonalize additional QEMU-specific hacks in the platform code.) Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366037
* [PowerPC64LE] Fix endianness issues in phyp and opal consoles.Brandon Bergren2020-09-232-4/+16
| | | | | | | | | | This applies to both pseries and powernv, which were tested at different points during the patchset development. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366036
* [PowerPC64LE] Tell the hypervisor to switch interrupts to LE at CHRP attach.Brandon Bergren2020-09-232-0/+28
| | | | | | | | | | Since we will need to be able to take traps relatively early in the process, ensure that the hypervisor changes our ILE for us as soon as we are ready. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366035
* [PowerPC64LE] Fix endian dependence of ofw_real.c.Brandon Bergren2020-09-221-152/+156
| | | | | | | | | | | | Since OFW always runs in big endian in practice, we need to convert several bits back and forth. This is necessary to communicate with SLOF on LE pseries. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366034
* [PowerPC64LE] LE bringup work: locore / machdep / platformBrandon Bergren2020-09-225-3/+38
| | | | | | | | | | This is the initial LE changes required in the machdep code to get as far as platform attachment on qemu pseries. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366033
* [PowerPC64LE] Set up powerpc.powerpc64le architectureBrandon Bergren2020-09-221-0/+4
| | | | | | | | | | | | | | | | | | This is the initial set up for PowerPC64LE. The current plan is for this arch to remain experimental for FreeBSD 13. This started as a weekend learning project for me and kinda snowballed from there. (More to follow momentarily.) Reviewed by: imp (earlier version), emaste Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D26399 Notes: svn path=/head/; revision=366032
* Sparsify the vm_page_dump bitmapD Scott Phillips2020-09-212-1/+14
| | | | | | | | | | | | | | | | | | | On Ampere Altra systems, the sparse population of RAM within the physical address space causes the vm_page_dump bitmap to be much larger than necessary, increasing the size from ~8 Mib to > 2 Gib (and overflowing `int` for the size). Changing the page dump bitmap also changes the minidump file format, so changes are also necessary in libkvm. Reviewed by: jhb Approved by: scottl (implicit) MFC after: 1 week Sponsored by: Ampere Computing, Inc. Differential Revision: https://reviews.freebsd.org/D26131 Notes: svn path=/head/; revision=365978
* Move vm_page_dump bitset array definition to MI codeD Scott Phillips2020-09-213-76/+27
| | | | | | | | | | | | | | | | | | | These definitions were repeated by all architectures, with small variations. Consolidate the common definitons in machine independent code and use bitset(9) macros for manipulation. Many opportunities for deduplication remain in the machine dependent minidump logic. The only intended functional change is increasing the bit index type to vm_pindex_t, allowing the indexing of pages with address of 8 TiB and greater. Reviewed by: kib, markj Approved by: scottl (implicit) MFC after: 1 week Sponsored by: Ampere Computing, Inc. Differential Revision: https://reviews.freebsd.org/D26129 Notes: svn path=/head/; revision=365977
* Add missing assignment forgotten in r365899Michal Meloun2020-09-201-0/+1
| | | | | | | | | Noticed by: mav MFC after: 1 month MFC with: r365899 Notes: svn path=/head/; revision=365926
* Add NetBSD compatible bus_space_peek_N() and bus_space_poke_N() functions.Michal Meloun2020-09-191-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | One problem with the bus_space_read_N() and bus_space_write_N() family of functions is that they provide no protection against exceptions which can occur when no physical hardware or device responds to the read or write cycles. In such a situation, the system typically would panic due to a kernel-mode bus error. The bus_space_peek_N() and bus_space_poke_N() family of functions provide a mechanism to handle these exceptions gracefully without the risk of crashing the system. Typical example is access to PCI(e) configuration space in bus enumeration function on badly implemented PCI(e) root complexes (RK3399 or Neoverse N1 N1SDP and/or access to PCI(e) register when device is in deep sleep state. This commit adds a real implementation for arm64 only. The remaining architectures have bus_space_peek()/bus_space_poke() emulated by using bus_space_read()/bus_space_write() (without exception handling). MFC after: 1 month Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D25371 Notes: svn path=/head/; revision=365899
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