From 4cfbfdd4b37ba16b29a13a924663002c960213c8 Mon Sep 17 00:00:00 2001
From: Adrian Chadd <adrian@FreeBSD.org>
Date: Wed, 9 Oct 2013 00:27:12 +0000
Subject: Add "better" MIPS24k and MIPS74k barriers.

* the mips74k cores only need EHB (which is 'sll $0, $0, 3')
  here; NOPs don't actually work.

* add EHB as the last NOP for the default barriers/hazards;
  that is "better" behaviour and should work on a wider
  variety of processors.

This allows the existing (icky) TLB code to work, allowing
the AR9344 SoC (mips74k) to actually get through kernel startup.

Tested:

* AR9344 SoC - (mips74k)
* AR9331 SoC - (mips24k)

TODO:

* test on mips4k CPUs, just to be sure.

* document that sll $0, $0, 3 is actually "EHB" and that it
  falls back to being a NOP for pre-mips32r1.

* mips24k has an errata that we currently don't correctly explicitly
  state - ie, that after DERET/ERET, the only valid instruction is
  a NOP.

Reviewed by:	imp@
Approved by:	re@ (gjb)
---
 sys/mips/include/asm.h     | 7 +++++--
 sys/mips/include/cpuregs.h | 9 ++++++++-
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/sys/mips/include/asm.h b/sys/mips/include/asm.h
index 790024ff60d4..551d02c1cd51 100644
--- a/sys/mips/include/asm.h
+++ b/sys/mips/include/asm.h
@@ -725,9 +725,12 @@ _C_LABEL(x):
 #elif defined(CPU_RMI)
 #define	HAZARD_DELAY
 #define	ITLBNOPFIX
+#elif defined(CPU_MIPS74KC)
+#define	HAZARD_DELAY	sll $0,$0,3
+#define	ITLBNOPFIX	sll $0,$0,3
 #else
-#define	ITLBNOPFIX	nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
-#define	HAZARD_DELAY	nop;nop;nop;nop;nop;
+#define	ITLBNOPFIX	nop;nop;nop;nop;nop;nop;nop;nop;nop;sll $0,$0,3;
+#define	HAZARD_DELAY	nop;nop;nop;nop;sll $0,$0,3;
 #endif
 
 #endif /* !_MACHINE_ASM_H_ */
diff --git a/sys/mips/include/cpuregs.h b/sys/mips/include/cpuregs.h
index 436a980785c4..be8414f8fc32 100644
--- a/sys/mips/include/cpuregs.h
+++ b/sys/mips/include/cpuregs.h
@@ -149,6 +149,11 @@
 #define	MIPS_CCA_CC	0x05	/* Cacheable Coherent. */
 #endif
 
+#if defined(CPU_MIPS74KC)
+#define	MIPS_CCA_UNCACHED	0x02
+#define	MIPS_CCA_CACHED		0x00
+#endif
+
 #ifndef	MIPS_CCA_UNCACHED
 #define	MIPS_CCA_UNCACHED	MIPS_CCA_UC
 #endif
@@ -204,12 +209,14 @@
 #define	COP0_SYNC	.word 0xc0	/* ehb */
 #elif defined(CPU_SB1)
 #define COP0_SYNC  ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
+#elif defined(CPU_MIPS74KC)
+#define	COP0_SYNC	 .word 0xc0	/* ehb */
 #else
 /*
  * Pick a reasonable default based on the "typical" spacing described in the
  * "CP0 Hazards" chapter of MIPS Architecture Book Vol III.
  */
-#define	COP0_SYNC  ssnop; ssnop; ssnop; ssnop; ssnop
+#define	COP0_SYNC  ssnop; ssnop; ssnop; ssnop; .word 0xc0;
 #endif
 #define	COP0_HAZARD_FPUENABLE	nop; nop; nop; nop;
 
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