From e1f316220bf375804e3bee6a4a7b1e3a68564141 Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Sun, 28 Apr 2013 00:45:58 +0000 Subject: Initial import of the QCA qcamain_open_hal repository. Source: https://github.com/qca/qcamain_open_hal_public Revision: 60390a9f9ac6a20db168fbbc01a4ad4e01c395ce Thankyou to QCA for this release. --- LICENCE.TXT | 13 + NOTICE.TXT | 72 + README | 23 + hal/ar9300/ar9300.h | 1641 + hal/ar9300/ar9300_aic.c | 727 + hal/ar9300/ar9300_ani.c | 1277 + hal/ar9300/ar9300_aphrodite10.ini | 1536 + hal/ar9300/ar9300_attach.c | 3965 ++ hal/ar9300/ar9300_beacon.c | 198 + hal/ar9300/ar9300_eeprom.c | 4522 ++ hal/ar9300/ar9300_gpio.c | 652 + hal/ar9300/ar9300_interrupts.c | 767 + hal/ar9300/ar9300_jupiter10.ini | 1894 + hal/ar9300/ar9300_jupiter20.ini | 2010 + hal/ar9300/ar9300_keycache.c | 421 + hal/ar9300/ar9300_mci.c | 1892 + hal/ar9300/ar9300_misc.c | 3714 ++ hal/ar9300/ar9300_osprey22.ini | 2188 + hal/ar9300/ar9300_osprey22_scoemu.ini | 2147 + hal/ar9300/ar9300_paprd.c | 2443 + hal/ar9300/ar9300_phy.c | 1215 + hal/ar9300/ar9300_power.c | 1559 + hal/ar9300/ar9300_radar.c | 593 + hal/ar9300/ar9300_radio.c | 238 + hal/ar9300/ar9300_raw_adc_capture.c | 47 + hal/ar9300/ar9300_recv.c | 341 + hal/ar9300/ar9300_recv_ds.c | 201 + hal/ar9300/ar9300_reset.c | 6072 +++ hal/ar9300/ar9300_rtt.c | 32 + hal/ar9300/ar9300_sim.c | 18 + hal/ar9300/ar9300_sim.h | 21 + hal/ar9300/ar9300_spectral.c | 588 + hal/ar9300/ar9300_timer.c | 185 + hal/ar9300/ar9300_tx99_tgt.c | 525 + hal/ar9300/ar9300_txbf.c | 30 + hal/ar9300/ar9300_txbf.h | 19 + hal/ar9300/ar9300_txbf_cal.c | 25 + hal/ar9300/ar9300_xmit.c | 910 + hal/ar9300/ar9300_xmit_ds.c | 947 + hal/ar9300/ar9300desc.h | 591 + hal/ar9300/ar9300eep.h | 699 + hal/ar9300/ar9300paprd.h | 54 + hal/ar9300/ar9300phy.h | 1955 + hal/ar9300/ar9300radar.h | 45 + hal/ar9300/ar9300reg.h | 3119 ++ hal/ar9300/ar9300template_ap121.h | 748 + hal/ar9300/ar9300template_aphrodite.h | 749 + hal/ar9300/ar9300template_cus157.h | 737 + hal/ar9300/ar9300template_generic.h | 748 + hal/ar9300/ar9300template_hb112.h | 751 + hal/ar9300/ar9300template_hb116.h | 751 + hal/ar9300/ar9300template_osprey_k31.h | 751 + hal/ar9300/ar9300template_wasp_2.h | 747 + hal/ar9300/ar9300template_wasp_k31.h | 748 + hal/ar9300/ar9300template_xb112.h | 750 + hal/ar9300/ar9300template_xb113.h | 750 + hal/ar9300/ar9330_11.ini | 1356 + hal/ar9300/ar9330_12.ini | 1289 + hal/ar9300/ar9340.ini | 4330 ++ hal/ar9300/ar9485.ini | 1419 + hal/ar9300/ar9485_1_1.ini | 1292 + hal/ar9300/ar955x.ini | 1684 + hal/ar9300/ar9580.ini | 2219 + hal/ar9300/eeprom.diff | 281 + hal/ar9300/osprey_reg_map.h | 3193 ++ hal/ar9300/osprey_reg_map_macro.h | 83644 +++++++++++++++++++++++++++++++ hal/ar9300/poseidon_reg_map_macro.h | 4334 ++ hal/ar9300/scorpion_reg_map.h | 1356 + hal/ar9300/scorpion_reg_map_macro.h | 66519 ++++++++++++++++++++++++ hal/ar9300/sources | 81 + hal/ar9300/wasp_reg_map.h | 71 + 71 files changed, 233429 insertions(+) create mode 100644 LICENCE.TXT create mode 100644 NOTICE.TXT create mode 100644 README create mode 100644 hal/ar9300/ar9300.h create mode 100644 hal/ar9300/ar9300_aic.c create mode 100644 hal/ar9300/ar9300_ani.c create mode 100644 hal/ar9300/ar9300_aphrodite10.ini create mode 100644 hal/ar9300/ar9300_attach.c create mode 100644 hal/ar9300/ar9300_beacon.c create mode 100644 hal/ar9300/ar9300_eeprom.c create mode 100644 hal/ar9300/ar9300_gpio.c create mode 100644 hal/ar9300/ar9300_interrupts.c create mode 100644 hal/ar9300/ar9300_jupiter10.ini create mode 100644 hal/ar9300/ar9300_jupiter20.ini create mode 100644 hal/ar9300/ar9300_keycache.c create mode 100644 hal/ar9300/ar9300_mci.c create mode 100644 hal/ar9300/ar9300_misc.c create mode 100644 hal/ar9300/ar9300_osprey22.ini create mode 100644 hal/ar9300/ar9300_osprey22_scoemu.ini create mode 100644 hal/ar9300/ar9300_paprd.c create mode 100644 hal/ar9300/ar9300_phy.c create mode 100644 hal/ar9300/ar9300_power.c create mode 100644 hal/ar9300/ar9300_radar.c create mode 100644 hal/ar9300/ar9300_radio.c create mode 100644 hal/ar9300/ar9300_raw_adc_capture.c create mode 100644 hal/ar9300/ar9300_recv.c create mode 100644 hal/ar9300/ar9300_recv_ds.c create mode 100644 hal/ar9300/ar9300_reset.c create mode 100644 hal/ar9300/ar9300_rtt.c create mode 100644 hal/ar9300/ar9300_sim.c create mode 100644 hal/ar9300/ar9300_sim.h create mode 100644 hal/ar9300/ar9300_spectral.c create mode 100644 hal/ar9300/ar9300_timer.c create mode 100644 hal/ar9300/ar9300_tx99_tgt.c create mode 100644 hal/ar9300/ar9300_txbf.c create mode 100644 hal/ar9300/ar9300_txbf.h create mode 100644 hal/ar9300/ar9300_txbf_cal.c create mode 100644 hal/ar9300/ar9300_xmit.c create mode 100644 hal/ar9300/ar9300_xmit_ds.c create mode 100644 hal/ar9300/ar9300desc.h create mode 100644 hal/ar9300/ar9300eep.h create mode 100644 hal/ar9300/ar9300paprd.h create mode 100644 hal/ar9300/ar9300phy.h create mode 100644 hal/ar9300/ar9300radar.h create mode 100644 hal/ar9300/ar9300reg.h create mode 100644 hal/ar9300/ar9300template_ap121.h create mode 100644 hal/ar9300/ar9300template_aphrodite.h create mode 100644 hal/ar9300/ar9300template_cus157.h create mode 100644 hal/ar9300/ar9300template_generic.h create mode 100644 hal/ar9300/ar9300template_hb112.h create mode 100644 hal/ar9300/ar9300template_hb116.h create mode 100644 hal/ar9300/ar9300template_osprey_k31.h create mode 100644 hal/ar9300/ar9300template_wasp_2.h create mode 100644 hal/ar9300/ar9300template_wasp_k31.h create mode 100644 hal/ar9300/ar9300template_xb112.h create mode 100644 hal/ar9300/ar9300template_xb113.h create mode 100644 hal/ar9300/ar9330_11.ini create mode 100755 hal/ar9300/ar9330_12.ini create mode 100644 hal/ar9300/ar9340.ini create mode 100644 hal/ar9300/ar9485.ini create mode 100644 hal/ar9300/ar9485_1_1.ini create mode 100644 hal/ar9300/ar955x.ini create mode 100644 hal/ar9300/ar9580.ini create mode 100644 hal/ar9300/eeprom.diff create mode 100644 hal/ar9300/osprey_reg_map.h create mode 100644 hal/ar9300/osprey_reg_map_macro.h create mode 100644 hal/ar9300/poseidon_reg_map_macro.h create mode 100644 hal/ar9300/scorpion_reg_map.h create mode 100644 hal/ar9300/scorpion_reg_map_macro.h create mode 100644 hal/ar9300/sources create mode 100644 hal/ar9300/wasp_reg_map.h diff --git a/LICENCE.TXT b/LICENCE.TXT new file mode 100644 index 000000000000..16d1c6c4b012 --- /dev/null +++ b/LICENCE.TXT @@ -0,0 +1,13 @@ +Copyright (c) 2013 Qualcomm Atheros, Inc. + +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH +REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, +INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM +LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +PERFORMANCE OF THIS SOFTWARE. diff --git a/NOTICE.TXT b/NOTICE.TXT new file mode 100644 index 000000000000..b94d2f3129cc --- /dev/null +++ b/NOTICE.TXT @@ -0,0 +1,72 @@ +This NOTICE.TXT file contains certain notices of software components included +with the software that QUALCOMM ATHEROS Incorporated ('Qualcomm Atheros') is +required to provide you. Notwithstanding anything in the notices in this file, +your use of these software components together with the Qualcomm Atheros +software (Qualcomm Atheros software hereinafter referred to as 'Software') is +subject to the terms of your license from Qualcomm Atheros. Compliance with +all copyright laws and software license agreements included in the notice +section of this file are the responsibility of the user. Except as may be +granted by separate express written agreement, this file provides no license +to any Qualcomm Atheros patents, trademarks, copyrights, or other intellectual +property. + +Copyright (c) 2013 QUALCOMM ATHEROS Incorporated. All rights reserved. + +QUALCOMM ATHEROS® is a registered trademark and registered service mark of +QUALCOMM ATHEROS Incorporated. All other trademarks and service marks are +the property of their respective owners. + +NOTICES: + +/* + * Copyright (c) 2005-2012 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * Copyright (c) 2002-2005 Atheros Communications, Inc. + * Copyright (c) 2008-2010, Atheros Communications Inc. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. The materials contained herein are unmodified and are used + * unmodified. + * 2. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following NO + * ''WARRANTY'' disclaimer below (''Disclaimer''), without + * modification. + * 3. Redistributions in binary form must reproduce at minimum a + * disclaimer similar to the Disclaimer below and any redistribution + * must be conditioned upon including a substantially similar + * Disclaimer requirement for further binary redistribution. + * 4. Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote + * product derived from this software without specific prior written + * permission. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, + * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE + * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. + */ diff --git a/README b/README new file mode 100644 index 000000000000..d822dfd54c6e --- /dev/null +++ b/README @@ -0,0 +1,23 @@ +This is a public version of the AR9300 HAL, suitable for open source +development. + + +What is this? +------------- + +This is a public version of the QCA mainline (10.x) development HAL. +It has a few notable changes: + +* The boolean types have been converted back to the HAL types + (HAL_BOOL, AH_TRUE / AH_FALSE) to aid integration into the existing + open source Atheros HAL drivers; + +* Some features have been removed from this HAL. + +However, this is essentially the same HAL which is used in QCA development +and forms the basis for public releases from the 10.x mainline. + +Subsequent HAL releases will be committed on top of this release in order +to provide developers with a simple change history they can use when +doing branch merging. + diff --git a/hal/ar9300/ar9300.h b/hal/ar9300/ar9300.h new file mode 100644 index 000000000000..c8add05fa4bc --- /dev/null +++ b/hal/ar9300/ar9300.h @@ -0,0 +1,1641 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _ATH_AR9300_H_ +#define _ATH_AR9300_H_ + +#include "ah_internal.h" +#include "ah_eeprom.h" +#include "ah_devid.h" +#include "ar9300eep.h" /* For Eeprom definitions */ +#include "asf_amem.h" + + +#define AR9300_MAGIC 0x19741014 + + +/* MAC register values */ + +#define INIT_CONFIG_STATUS 0x00000000 +#define INIT_RSSI_THR 0x7 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ +#define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */ + +/* + * Various fifo fill before Tx start, in 64-byte units + * i.e. put the frame in the air while still DMAing + */ +#define MIN_TX_FIFO_THRESHOLD 0x1 +#define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1) +#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD + + #define CHANSEL_DIV 15 + #define FCLK 40 + +#define COEFF ((FCLK * 5) / 2) +#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) +#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) +#define CHANSEL_5G_DOT5MHZ 2188 + +/* + * Receive Queue Fifo depth. + */ +enum RX_FIFO_DEPTH { + HAL_HP_RXFIFO_DEPTH = 16, + HAL_LP_RXFIFO_DEPTH = 128, +}; + +/* + * Gain support. + */ +#define NUM_CORNER_FIX_BITS_2133 7 +#define CCK_OFDM_GAIN_DELTA 15 + +enum GAIN_PARAMS { + GP_TXCLIP, + GP_PD90, + GP_PD84, + GP_GSEL +}; + +enum GAIN_PARAMS_2133 { + GP_MIXGAIN_OVR, + GP_PWD_138, + GP_PWD_137, + GP_PWD_136, + GP_PWD_132, + GP_PWD_131, + GP_PWD_130, +}; + +enum { + HAL_RESET_POWER_ON, + HAL_RESET_WARM, + HAL_RESET_COLD, +}; + +typedef struct _gain_opt_step { + int16_t paramVal[NUM_CORNER_FIX_BITS_2133]; + int32_t stepGain; + int8_t stepName[16]; +} GAIN_OPTIMIZATION_STEP; + +typedef struct { + u_int32_t numStepsInLadder; + u_int32_t defaultStepNum; + GAIN_OPTIMIZATION_STEP optStep[10]; +} GAIN_OPTIMIZATION_LADDER; + +typedef struct { + u_int32_t currStepNum; + u_int32_t currGain; + u_int32_t targetGain; + u_int32_t loTrig; + u_int32_t hiTrig; + u_int32_t gainFCorrection; + u_int32_t active; + GAIN_OPTIMIZATION_STEP *curr_step; +} GAIN_VALUES; + +typedef struct { + u_int16_t synth_center; + u_int16_t ctl_center; + u_int16_t ext_center; +} CHAN_CENTERS; + +/* RF HAL structures */ +typedef struct rf_hal_funcs { + HAL_BOOL (*set_channel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *); + HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah, HAL_CHANNEL *chans, + u_int32_t nchancs); +} RF_HAL_FUNCS; + +struct ar9300_ani_default { + u_int16_t m1_thresh_low; + u_int16_t m2_thresh_low; + u_int16_t m1_thresh; + u_int16_t m2_thresh; + u_int16_t m2_count_thr; + u_int16_t m2_count_thr_low; + u_int16_t m1_thresh_low_ext; + u_int16_t m2_thresh_low_ext; + u_int16_t m1_thresh_ext; + u_int16_t m2_thresh_ext; + u_int16_t firstep; + u_int16_t firstep_low; + u_int16_t cycpwr_thr1; + u_int16_t cycpwr_thr1_ext; +}; + +/* + * Per-channel ANI state private to the driver. + */ +struct ar9300_ani_state { + HAL_CHANNEL c; + HAL_BOOL must_restore; + HAL_BOOL ofdms_turn; + u_int8_t ofdm_noise_immunity_level; + u_int8_t cck_noise_immunity_level; + u_int8_t spur_immunity_level; + u_int8_t firstep_level; + u_int8_t ofdm_weak_sig_detect_off; + u_int8_t mrc_cck_off; + + /* Thresholds */ + u_int32_t listen_time; + u_int32_t ofdm_trig_high; + u_int32_t ofdm_trig_low; + int32_t cck_trig_high; + int32_t cck_trig_low; + int32_t rssi_thr_low; + int32_t rssi_thr_high; + + int32_t rssi; /* The current RSSI */ + u_int32_t tx_frame_count; /* Last tx_frame_count */ + u_int32_t rx_frame_count; /* Last rx Frame count */ + u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */ + u_int32_t ofdm_phy_err_count;/* OFDM err count since last reset */ + u_int32_t cck_phy_err_count; /* CCK err count since last reset */ + + struct ar9300_ani_default ini_def; /* INI default values for ANI registers */ + HAL_BOOL phy_noise_spur; /* based on OFDM/CCK Phy errors */ +}; + +#define AR9300_ANI_POLLINTERVAL 1000 /* 1000 milliseconds between ANI poll */ + +#define AR9300_CHANNEL_SWITCH_TIME_USEC 1000 /* 1 millisecond needed to change channels */ + +#define HAL_PROCESS_ANI 0x00000001 /* ANI state setup */ +#define HAL_RADAR_EN 0x80000000 /* Radar detect is capable */ +#define HAL_AR_EN 0x40000000 /* AR detect is capable */ + +#define DO_ANI(ah) \ + ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI)) + +struct ar9300_stats { + u_int32_t ast_ani_niup; /* ANI increased noise immunity */ + u_int32_t ast_ani_nidown; /* ANI decreased noise immunity */ + u_int32_t ast_ani_spurup; /* ANI increased spur immunity */ + u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */ + u_int32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ + u_int32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ + u_int32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ + u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ + u_int32_t ast_ani_stepup; /* ANI increased first step level */ + u_int32_t ast_ani_stepdown;/* ANI decreased first step level */ + u_int32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ + u_int32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ + u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ + u_int32_t ast_ani_lzero; /* ANI listen time forced to zero */ + u_int32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ + HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ + HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ +}; + +struct ar9300_rad_reader { + u_int16_t rd_index; + u_int16_t rd_expSeq; + u_int32_t rd_resetVal; + u_int8_t rd_start; +}; + +struct ar9300_rad_writer { + u_int16_t wr_index; + u_int16_t wr_seq; +}; + +struct ar9300_radar_event { + u_int32_t re_ts; /* 32 bit time stamp */ + u_int8_t re_rssi; /* rssi of radar event */ + u_int8_t re_dur; /* duration of radar pulse */ + u_int8_t re_chanIndex; /* Channel of event */ +}; + +struct ar9300_radar_q_elem { + u_int32_t rq_seqNum; + u_int32_t rq_busy; /* 32 bit to insure atomic read/write */ + struct ar9300_radar_event rq_event; /* Radar event */ +}; + +struct ar9300_radar_q_info { + u_int16_t ri_qsize; /* q size */ + u_int16_t ri_seqSize; /* Size of sequence ring */ + struct ar9300_rad_reader ri_reader; /* State for the q reader */ + struct ar9300_rad_writer ri_writer; /* state for the q writer */ +}; + +#define HAL_MAX_ACK_RADAR_DUR 511 +#define HAL_MAX_NUM_PEAKS 3 +#define HAL_ARQ_SIZE 4096 /* 8K AR events for buffer size */ +#define HAL_ARQ_SEQSIZE 4097 /* Sequence counter wrap for AR */ +#define HAL_RADARQ_SIZE 1024 /* 1K radar events for buffer size */ +#define HAL_RADARQ_SEQSIZE 1025 /* Sequence counter wrap for radar */ +#define HAL_NUMRADAR_STATES 64 /* Number of radar channels we keep state for */ + +struct ar9300_ar_state { + u_int16_t ar_prev_time_stamp; + u_int32_t ar_prev_width; + u_int32_t ar_phy_err_count[HAL_MAX_ACK_RADAR_DUR]; + u_int32_t ar_ack_sum; + u_int16_t ar_peak_list[HAL_MAX_NUM_PEAKS]; + u_int32_t ar_packet_threshold; /* Thresh to determine traffic load */ + u_int32_t ar_par_threshold; /* Thresh to determine peak */ + u_int32_t ar_radar_rssi; /* Rssi threshold for AR event */ +}; + +struct ar9300_radar_state { + HAL_CHANNEL_INTERNAL *rs_chan; /* Channel info */ + u_int8_t rs_chan_index; /* Channel index in radar structure */ + u_int32_t rs_num_radar_events; /* Number of radar events */ + int32_t rs_firpwr; /* Thresh to check radar sig is gone */ + u_int32_t rs_radar_rssi; /* Thresh to start radar det (dB) */ + u_int32_t rs_height; /* Thresh for pulse height (dB)*/ + u_int32_t rs_pulse_rssi; /* Thresh to check if pulse is gone (dB) */ + u_int32_t rs_inband; /* Thresh to check if pusle is inband (0.5 dB) */ +}; +typedef struct { + u_int8_t uc_receiver_errors; + u_int8_t uc_bad_tlp_errors; + u_int8_t uc_bad_dllp_errors; + u_int8_t uc_replay_timeout_errors; + u_int8_t uc_replay_number_rollover_errors; +} ar_pcie_error_moniter_counters; + +#define AR9300_OPFLAGS_11A 0x01 /* if set, allow 11a */ +#define AR9300_OPFLAGS_11G 0x02 /* if set, allow 11g */ +#define AR9300_OPFLAGS_N_5G_HT40 0x04 /* if set, disable 5G HT40 */ +#define AR9300_OPFLAGS_N_2G_HT40 0x08 /* if set, disable 2G HT40 */ +#define AR9300_OPFLAGS_N_5G_HT20 0x10 /* if set, disable 5G HT20 */ +#define AR9300_OPFLAGS_N_2G_HT20 0x20 /* if set, disable 2G HT20 */ + +/* + * For Kite and later chipsets, the following bits are not being programmed in EEPROM + * and so need to be enabled always. + * Bit 0: en_fcc_mid, Bit 1: en_jap_mid, Bit 2: en_fcc_dfs_ht40 + * Bit 3: en_jap_ht40, Bit 4: en_jap_dfs_ht40 + */ +#define AR9300_RDEXT_DEFAULT 0x1F + +#define AR9300_MAX_CHAINS 3 +#define AR9300_NUM_CHAINS(chainmask) \ + (((chainmask >> 2) & 1) + ((chainmask >> 1) & 1) + (chainmask & 1)) +#define AR9300_CHAIN0_MASK 0x1 +#define AR9300_CHAIN1_MASK 0x2 +#define AR9300_CHAIN2_MASK 0x4 + +/* Support for multiple INIs */ +struct ar9300_ini_array { + u_int32_t *ia_array; + u_int32_t ia_rows; + u_int32_t ia_columns; +}; +#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ + (iniarray)->ia_array = (u_int32_t *)(array); \ + (iniarray)->ia_rows = (rows); \ + (iniarray)->ia_columns = (columns); \ +} while (0) +#define INI_RA(iniarray, row, column) (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) + +#define INIT_CAL(_perCal) \ + (_perCal)->cal_state = CAL_WAITING; \ + (_perCal)->cal_next = AH_NULL; + +#define INSERT_CAL(_ahp, _perCal) \ +do { \ + if ((_ahp)->ah_cal_list_last == AH_NULL) { \ + (_ahp)->ah_cal_list = (_ahp)->ah_cal_list_last = (_perCal); \ + ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ + } else { \ + ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ + (_ahp)->ah_cal_list_last = (_perCal); \ + (_perCal)->cal_next = (_ahp)->ah_cal_list; \ + } \ +} while (0) + +typedef enum cal_types { + IQ_MISMATCH_CAL = 0x1, + TEMP_COMP_CAL = 0x2, +} HAL_CAL_TYPES; + +typedef enum cal_state { + CAL_INACTIVE, + CAL_WAITING, + CAL_RUNNING, + CAL_DONE +} HAL_CAL_STATE; /* Calibrate state */ + +#define MIN_CAL_SAMPLES 1 +#define MAX_CAL_SAMPLES 64 +#define INIT_LOG_COUNT 5 +#define PER_MIN_LOG_COUNT 2 +#define PER_MAX_LOG_COUNT 10 + +#define AR9300_NUM_BT_WEIGHTS 4 +#define AR9300_NUM_WLAN_WEIGHTS 4 + +/* Per Calibration data structure */ +typedef struct per_cal_data { + HAL_CAL_TYPES cal_type; // Type of calibration + u_int32_t cal_num_samples; // Number of SW samples to collect + u_int32_t cal_count_max; // Number of HW samples to collect + void (*cal_collect)(struct ath_hal *, u_int8_t); // Accumulator func + void (*cal_post_proc)(struct ath_hal *, u_int8_t); // Post-processing func +} HAL_PERCAL_DATA; + +/* List structure for calibration data */ +typedef struct cal_list { + const HAL_PERCAL_DATA *cal_data; + HAL_CAL_STATE cal_state; + struct cal_list *cal_next; +} HAL_CAL_LIST; + +#define AR9300_NUM_CAL_TYPES 2 +#define AR9300_PAPRD_TABLE_SZ 24 +#define AR9300_PAPRD_GAIN_TABLE_SZ 32 +#define AR9382_MAX_GPIO_PIN_NUM (16) +#define AR9382_GPIO_PIN_8_RESERVED (8) +#define AR9382_GPIO_9_INPUT_ONLY (9) +#define AR9382_MAX_GPIO_INPUT_PIN_NUM (13) +#define AR9382_GPIO_PIN_11_RESERVED (11) +#define AR9382_MAX_JTAG_GPIO_PIN_NUM (3) + +/* Paprd tx power adjust data structure */ +struct ar9300_paprd_pwr_adjust { + u_int32_t target_rate; // rate index + u_int32_t reg_addr; // register offset + u_int32_t reg_mask; // mask of register + u_int32_t reg_mask_offset; // mask offset of register + u_int32_t sub_db; // offset value unit of dB +}; + +#define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) + HTTS(8)*/ +struct ath_hal_9300 { + struct ath_hal_private_tables ah_priv; /* base class */ + + /* + * Information retrieved from EEPROM. + */ + ar9300_eeprom_t ah_eeprom; + + GAIN_VALUES ah_gain_values; + + u_int8_t ah_macaddr[IEEE80211_ADDR_LEN]; + u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; + u_int8_t ah_bssid_mask[IEEE80211_ADDR_LEN]; + u_int16_t ah_assoc_id; + + /* + * Runtime state. + */ + u_int32_t ah_mask_reg; /* copy of AR_IMR */ + u_int32_t ah_mask2Reg; /* copy of AR_IMR_S2 */ + u_int32_t ah_msi_reg; /* copy of AR_PCIE_MSI */ + os_atomic_t ah_ier_ref_count; /* reference count for enabling interrupts */ + struct ar9300_stats ah_stats; /* various statistics */ + RF_HAL_FUNCS ah_rf_hal; + u_int32_t ah_tx_desc_mask; /* mask for TXDESC */ + u_int32_t ah_tx_ok_interrupt_mask; + u_int32_t ah_tx_err_interrupt_mask; + u_int32_t ah_tx_desc_interrupt_mask; + u_int32_t ah_tx_eol_interrupt_mask; + u_int32_t ah_tx_urn_interrupt_mask; + HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; + HAL_SMPS_MODE ah_sm_power_mode; + HAL_BOOL ah_chip_full_sleep; + u_int32_t ah_atim_window; + HAL_ANT_SETTING ah_diversity_control; /* antenna setting */ + u_int16_t ah_antenna_switch_swap; /* Controls mapping of OID request */ + u_int8_t ah_tx_chainmask_cfg; /* chain mask config */ + u_int8_t ah_rx_chainmask_cfg; + u_int32_t ah_beacon_rssi_threshold; /* cache beacon rssi threshold */ + /* Calibration related fields */ + HAL_CAL_TYPES ah_supp_cals; + HAL_CAL_LIST ah_iq_cal_data; /* IQ Cal Data */ + HAL_CAL_LIST ah_temp_comp_cal_data; /* Temperature Compensation Cal Data */ + HAL_CAL_LIST *ah_cal_list; /* ptr to first cal in list */ + HAL_CAL_LIST *ah_cal_list_last; /* ptr to last cal in list */ + HAL_CAL_LIST *ah_cal_list_curr; /* ptr to current cal */ +// IQ Cal aliases +#define ah_total_power_meas_i ah_meas0.unsign +#define ah_total_power_meas_q ah_meas1.unsign +#define ah_total_iq_corr_meas ah_meas2.sign + union { + u_int32_t unsign[AR9300_MAX_CHAINS]; + int32_t sign[AR9300_MAX_CHAINS]; + } ah_meas0; + union { + u_int32_t unsign[AR9300_MAX_CHAINS]; + int32_t sign[AR9300_MAX_CHAINS]; + } ah_meas1; + union { + u_int32_t unsign[AR9300_MAX_CHAINS]; + int32_t sign[AR9300_MAX_CHAINS]; + } ah_meas2; + union { + u_int32_t unsign[AR9300_MAX_CHAINS]; + int32_t sign[AR9300_MAX_CHAINS]; + } ah_meas3; + u_int16_t ah_cal_samples; + /* end - Calibration related fields */ + u_int32_t ah_tx6_power_in_half_dbm; /* power output for 6Mb tx */ + u_int32_t ah_sta_id1_defaults; /* STA_ID1 default settings */ + u_int32_t ah_misc_mode; /* MISC_MODE settings */ + HAL_BOOL ah_get_plcp_hdr; /* setting about MISC_SEL_EVM */ + enum { + AUTO_32KHZ, /* use it if 32kHz crystal present */ + USE_32KHZ, /* do it regardless */ + DONT_USE_32KHZ, /* don't use it regardless */ + } ah_enable32k_hz_clock; /* whether to sleep at 32kHz */ + + u_int32_t ah_ofdm_tx_power; + int16_t ah_tx_power_index_offset; + + u_int ah_slot_time; /* user-specified slot time */ + u_int ah_ack_timeout; /* user-specified ack timeout */ + /* + * XXX + * 11g-specific stuff; belongs in the driver. + */ + u_int8_t ah_g_beacon_rate; /* fixed rate for G beacons */ + u_int32_t ah_gpio_mask; /* copy of enabled GPIO mask */ + u_int32_t ah_gpio_cause; /* copy of GPIO cause (sync and async) */ + /* + * RF Silent handling; setup according to the EEPROM. + */ + u_int32_t ah_gpio_select; /* GPIO pin to use */ + u_int32_t ah_polarity; /* polarity to disable RF */ + u_int32_t ah_gpio_bit; /* after init, prev value */ + HAL_BOOL ah_eep_enabled; /* EEPROM bit for capability */ + +#ifdef ATH_BT_COEX + /* + * Bluetooth coexistence static setup according to the registry + */ + HAL_BT_MODULE ah_bt_module; /* Bluetooth module identifier */ + u_int8_t ah_bt_coex_config_type; /* BT coex configuration */ + u_int8_t ah_bt_active_gpio_select; /* GPIO pin for BT_ACTIVE */ + u_int8_t ah_bt_priority_gpio_select; /* GPIO pin for BT_PRIORITY */ + u_int8_t ah_wlan_active_gpio_select; /* GPIO pin for WLAN_ACTIVE */ + u_int8_t ah_bt_active_polarity; /* Polarity of BT_ACTIVE */ + HAL_BOOL ah_bt_coex_single_ant; /* Single or dual antenna configuration */ + u_int8_t ah_bt_wlan_isolation; /* Isolation between BT and WLAN in dB */ + /* + * Bluetooth coexistence runtime settings + */ + HAL_BOOL ah_bt_coex_enabled; /* If Bluetooth coexistence is enabled */ + u_int32_t ah_bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */ + u_int32_t ah_bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ + u_int32_t ah_bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ + u_int32_t ah_bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */ + u_int32_t ah_bt_coex_flag; /* Special tuning flags for BT coex */ +#endif + + /* + * Generic timer support + */ + u_int32_t ah_avail_gen_timers; /* mask of available timers */ + u_int32_t ah_intr_gen_timer_trigger; /* generic timer trigger interrupt state */ + u_int32_t ah_intr_gen_timer_thresh; /* generic timer trigger interrupt state */ + HAL_BOOL ah_enable_tsf2; /* enable TSF2 for gen timer 8-15. */ + + /* + * ANI & Radar support. + */ + u_int32_t ah_proc_phy_err; /* Process Phy errs */ + u_int32_t ah_ani_period; /* ani update list period */ + struct ar9300_ani_state *ah_curani; /* cached last reference */ + struct ar9300_ani_state ah_ani[255]; /* per-channel state */ + struct ar9300_radar_state ah_radar[HAL_NUMRADAR_STATES]; /* Per-Channel Radar detector state */ + struct ar9300_radar_q_elem *ah_radarq; /* radar event queue */ + struct ar9300_radar_q_info ah_radarq_info; /* radar event q read/write state */ + struct ar9300_ar_state ah_ar; /* AR detector state */ + struct ar9300_radar_q_elem *ah_arq; /* AR event queue */ + struct ar9300_radar_q_info ah_arq_info; /* AR event q read/write state */ + + /* + * Transmit power state. Note these are maintained + * here so they can be retrieved by diagnostic tools. + */ + u_int16_t ah_rates_array[16]; + + /* + * Tx queue interrupt state. + */ + u_int32_t ah_intr_txqs; + + HAL_BOOL ah_intr_mitigation_rx; /* rx Interrupt Mitigation Settings */ + HAL_BOOL ah_intr_mitigation_tx; /* tx Interrupt Mitigation Settings */ + + /* + * Extension Channel Rx Clear State + */ + u_int32_t ah_cycle_count; + u_int32_t ah_ctl_busy; + u_int32_t ah_ext_busy; + + /* HT CWM state */ + HAL_HT_EXTPROTSPACING ah_ext_prot_spacing; + u_int8_t ah_tx_chainmask; /* tx chain mask */ + u_int8_t ah_rx_chainmask; /* rx chain mask */ + + u_int8_t ah_tx_cal_chainmask; /* tx cal chain mask */ + u_int8_t ah_rx_cal_chainmask; /* rx cal chain mask */ + + int ah_hwp; + void *ah_cal_mem; + HAL_BOOL ah_emu_eeprom; + + HAL_ANI_CMD ah_ani_function; + HAL_BOOL ah_rifs_enabled; + u_int32_t ah_rifs_reg[11]; + u_int32_t ah_rifs_sec_cnt; + + /* open-loop power control */ + u_int32_t original_gain[22]; + int32_t init_pdadc; + int32_t pdadc_delta; + + /* cycle counts for beacon stuck diagnostics */ + u_int32_t ah_cycles; + u_int32_t ah_rx_clear; + u_int32_t ah_rx_frame; + u_int32_t ah_tx_frame; + +#define BB_HANG_SIG1 0 +#define BB_HANG_SIG2 1 +#define BB_HANG_SIG3 2 +#define BB_HANG_SIG4 3 +#define MAC_HANG_SIG1 4 +#define MAC_HANG_SIG2 5 + /* bb hang detection */ + int ah_hang[6]; + hal_hw_hangs_t ah_hang_wars; + /* + * Support for ar9300 multiple INIs + */ + struct ar9300_ini_array ah_ini_pcie_serdes; + struct ar9300_ini_array ah_ini_pcie_serdes_low_power; + struct ar9300_ini_array ah_ini_modes_additional; + struct ar9300_ini_array ah_ini_modes_additional_40mhz; + struct ar9300_ini_array ah_ini_modes_rxgain; + struct ar9300_ini_array ah_ini_modes_rxgain_bounds; + struct ar9300_ini_array ah_ini_modes_txgain; + struct ar9300_ini_array ah_ini_japan2484; + struct ar9300_ini_array ah_ini_radio_post_sys2ant; + struct ar9300_ini_array ah_ini_BTCOEX_MAX_TXPWR; + /* + * New INI format starting with Osprey 2.0 INI. + * Pre, core, post arrays for each sub-system (mac, bb, radio, soc) + */ + #define ATH_INI_PRE 0 + #define ATH_INI_CORE 1 + #define ATH_INI_POST 2 + #define ATH_INI_NUM_SPLIT (ATH_INI_POST + 1) + struct ar9300_ini_array ah_ini_mac[ATH_INI_NUM_SPLIT]; /* New INI format */ + struct ar9300_ini_array ah_ini_bb[ATH_INI_NUM_SPLIT]; /* New INI format */ + struct ar9300_ini_array ah_ini_radio[ATH_INI_NUM_SPLIT]; /* New INI format */ + struct ar9300_ini_array ah_ini_soc[ATH_INI_NUM_SPLIT]; /* New INI format */ + + /* + * Added to support DFS postamble array in INI that we need to apply + * in DFS channels + */ + + struct ar9300_ini_array ah_ini_dfs; + +#if ATH_WOW + struct ar9300_ini_array ah_ini_pcie_serdes_wow; /* SerDes values during WOW sleep */ +#endif + + /* To indicate EEPROM mapping used */ + u_int32_t ah_immunity_vals[6]; + HAL_BOOL ah_immunity_on; + /* + * snap shot of counter register for debug purposes + */ +#ifdef AH_DEBUG + u_int32_t last_tf; + u_int32_t last_rf; + u_int32_t last_rc; + u_int32_t last_cc; +#endif + HAL_BOOL ah_dma_stuck; /* Set to AH_TRUE when RX/TX DMA failed to stop. */ + u_int32_t nf_tsf32; /* timestamp for NF calibration duration */ + + u_int32_t reg_dmn; /* Regulatory Domain */ + int16_t twice_antenna_gain; /* Antenna Gain */ + u_int16_t twice_antenna_reduction; /* Antenna Gain Allowed */ + + /* + * Upper limit after factoring in the regulatory max, antenna gain and + * multichain factor. No TxBF, CDD or STBC gain factored + */ + int16_t upper_limit[AR9300_MAX_CHAINS]; + + /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */ + int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; + + + /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with STBC*/ + int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; + + /* Transmit Status ring support */ + struct ar9300_txs *ts_ring; + u_int16_t ts_tail; + u_int16_t ts_size; + u_int32_t ts_paddr_start; + u_int32_t ts_paddr_end; + + /* Receive Buffer size */ +#define HAL_RXBUFSIZE_DEFAULT 0xfff + u_int16_t rx_buf_size; + + u_int32_t ah_wa_reg_val; // Store the permanent value of Reg 0x4004 so we dont have to R/M/W. (We should not be reading this register when in sleep states). + + /* Indicate the PLL source clock rate is 25Mhz or not. + * clk_25mhz = 0 by default. + */ + u_int8_t clk_25mhz; + /* For PAPRD uses */ + u_int16_t small_signal_gain[AH_MAX_CHAINS]; + u_int32_t pa_table[AH_MAX_CHAINS][AR9300_PAPRD_TABLE_SZ]; + u_int32_t paprd_gain_table_entries[AR9300_PAPRD_GAIN_TABLE_SZ]; + u_int32_t paprd_gain_table_index[AR9300_PAPRD_GAIN_TABLE_SZ]; + u_int32_t ah_2g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht20 */ + u_int32_t ah_2g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht40 */ + u_int32_t ah_5g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht20 */ + u_int32_t ah_5g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht40 */ + u_int32_t paprd_training_power; + /* For GreenTx use to store the default tx power */ + u_int8_t ah_default_tx_power[ar9300_rate_size]; + HAL_BOOL ah_paprd_broken; + + /* To store offsets of host interface registers */ + struct { + u_int32_t AR_RC; + u_int32_t AR_WA; + u_int32_t AR_PM_STATE; + u_int32_t AR_H_INFOL; + u_int32_t AR_H_INFOH; + u_int32_t AR_PCIE_PM_CTRL; + u_int32_t AR_HOST_TIMEOUT; + u_int32_t AR_EEPROM; + u_int32_t AR_SREV; + u_int32_t AR_INTR_SYNC_CAUSE; + u_int32_t AR_INTR_SYNC_CAUSE_CLR; + u_int32_t AR_INTR_SYNC_ENABLE; + u_int32_t AR_INTR_ASYNC_MASK; + u_int32_t AR_INTR_SYNC_MASK; + u_int32_t AR_INTR_ASYNC_CAUSE_CLR; + u_int32_t AR_INTR_ASYNC_CAUSE; + u_int32_t AR_INTR_ASYNC_ENABLE; + u_int32_t AR_PCIE_SERDES; + u_int32_t AR_PCIE_SERDES2; + u_int32_t AR_GPIO_OUT; + u_int32_t AR_GPIO_IN; + u_int32_t AR_GPIO_OE_OUT; + u_int32_t AR_GPIO_OE1_OUT; + u_int32_t AR_GPIO_INTR_POL; + u_int32_t AR_GPIO_INPUT_EN_VAL; + u_int32_t AR_GPIO_INPUT_MUX1; + u_int32_t AR_GPIO_INPUT_MUX2; + u_int32_t AR_GPIO_OUTPUT_MUX1; + u_int32_t AR_GPIO_OUTPUT_MUX2; + u_int32_t AR_GPIO_OUTPUT_MUX3; + u_int32_t AR_INPUT_STATE; + u_int32_t AR_SPARE; + u_int32_t AR_PCIE_CORE_RESET_EN; + u_int32_t AR_CLKRUN; + u_int32_t AR_EEPROM_STATUS_DATA; + u_int32_t AR_OBS; + u_int32_t AR_RFSILENT; + u_int32_t AR_GPIO_PDPU; + u_int32_t AR_GPIO_DS; + u_int32_t AR_MISC; + u_int32_t AR_PCIE_MSI; + u_int32_t AR_TSF_SNAPSHOT_BT_ACTIVE; + u_int32_t AR_TSF_SNAPSHOT_BT_PRIORITY; + u_int32_t AR_TSF_SNAPSHOT_BT_CNTL; + u_int32_t AR_PCIE_PHY_LATENCY_NFTS_ADJ; + u_int32_t AR_TDMA_CCA_CNTL; + u_int32_t AR_TXAPSYNC; + u_int32_t AR_TXSYNC_INIT_SYNC_TMR; + u_int32_t AR_INTR_PRIO_SYNC_CAUSE; + u_int32_t AR_INTR_PRIO_SYNC_ENABLE; + u_int32_t AR_INTR_PRIO_ASYNC_MASK; + u_int32_t AR_INTR_PRIO_SYNC_MASK; + u_int32_t AR_INTR_PRIO_ASYNC_CAUSE; + u_int32_t AR_INTR_PRIO_ASYNC_ENABLE; + } ah_hostifregs; + + u_int32_t ah_enterprise_mode; + u_int32_t ah_radar1; + u_int32_t ah_dc_offset; + HAL_BOOL ah_hw_green_tx_enable; /* 1:enalbe H/W Green Tx */ + HAL_BOOL ah_smartantenna_enable; /* 1:enalbe H/W */ + u_int32_t ah_disable_cck; + HAL_BOOL ah_lna_div_use_bt_ant_enable; /* 1:enable Rx(LNA) Diversity */ + + + /* + * Different types of memory where the calibration data might be stored. + * All types are searched in Ar9300EepromRestore() in the order flash, eeprom, otp. + * To disable searching a type, set its parameter to 0. + */ + int try_dram; + int try_flash; + int try_eeprom; + int try_otp; +#ifdef ATH_CAL_NAND_FLASH + int try_nand; +#endif + /* + * This is where we found the calibration data. + */ + int calibration_data_source; + int calibration_data_source_address; + /* + * This is where we look for the calibration data. must be set before ath_attach() is called + */ + int calibration_data_try; + int calibration_data_try_address; + u_int8_t + tx_iq_cal_enable : 1, + tx_iq_cal_during_agc_cal : 1, + tx_cl_cal_enable : 1; + +#if ATH_SUPPORT_MCI + /* For MCI */ + HAL_BOOL ah_mci_ready; + u_int32_t ah_mci_int_raw; + u_int32_t ah_mci_int_rx_msg; + u_int32_t ah_mci_rx_status; + u_int32_t ah_mci_cont_status; + u_int8_t ah_mci_bt_state; + u_int32_t ah_mci_gpm_addr; + u_int8_t *ah_mci_gpm_buf; + u_int32_t ah_mci_gpm_len; + u_int32_t ah_mci_gpm_idx; + u_int32_t ah_mci_sched_addr; + u_int8_t *ah_mci_sched_buf; + u_int8_t ah_mci_coex_major_version_wlan; + u_int8_t ah_mci_coex_minor_version_wlan; + u_int8_t ah_mci_coex_major_version_bt; + u_int8_t ah_mci_coex_minor_version_bt; + HAL_BOOL ah_mci_coex_bt_version_known; + HAL_BOOL ah_mci_coex_wlan_channels_update; + u_int32_t ah_mci_coex_wlan_channels[4]; + HAL_BOOL ah_mci_coex_2g5g_update; + HAL_BOOL ah_mci_coex_is_2g; + HAL_BOOL ah_mci_query_bt; + HAL_BOOL ah_mci_unhalt_bt_gpm; /* need send UNHALT */ + HAL_BOOL ah_mci_halted_bt_gpm; /* HALT sent */ + HAL_BOOL ah_mci_need_flush_btinfo; + HAL_BOOL ah_mci_concur_tx_en; + u_int8_t ah_mci_stomp_low_tx_pri; + u_int8_t ah_mci_stomp_all_tx_pri; + u_int8_t ah_mci_stomp_none_tx_pri; + u_int32_t ah_mci_wlan_cal_seq; + u_int32_t ah_mci_wlan_cal_done; +#if ATH_SUPPORT_AIC + HAL_BOOL ah_aic_enabled; + u_int32_t ah_aic_sram[ATH_AIC_MAX_BT_CHANNEL]; +#endif +#endif /* ATH_SUPPORT_MCI */ + u_int8_t ah_cac_quiet_enabled; +#if ATH_WOW_OFFLOAD + u_int32_t ah_mcast_filter_l32_set; + u_int32_t ah_mcast_filter_u32_set; +#endif + HAL_BOOL ah_reduced_self_gen_mask; +}; + +#define AH9300(_ah) ((struct ath_hal_9300 *)(_ah)) + +#define IS_9300_EMU(ah) \ + (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_EMU_PCIE) + +#define ar9300_eep_data_in_flash(_ah) \ + (!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM)) + +#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ + (IS_CHAN_5GHZ(_c) && \ + ((AH_PRIVATE(_ah))->ah_config.ath_hal_fastClockEnable)) + +#if notyet +// Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have valid eeprom contents. +&& \ + ((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <= AR9300_EEP_MINOR_VER_16) || \ + (ar9300_eeprom_get(AH9300(_ah), EEP_FSTCLK_5G)))) +#endif + +/* + * WAR for bug 6773. OS_DELAY() does a PIO READ on the PCI bus which allows + * other cards' DMA reads to complete in the middle of our reset. + */ +#define WAR_6773(x) do { \ + if ((++(x) % 64) == 0) \ + OS_DELAY(1); \ +} while (0) + +#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ + int r; \ + for (r = 0; r < ((iniarray)->ia_rows); r++) { \ + OS_REG_WRITE(ah, INI_RA((iniarray), (r), 0), INI_RA((iniarray), r, (column)));\ + WAR_6773(regWr); \ + } \ +} while (0) + +#define UPPER_5G_SUB_BANDSTART 5700 +#define MID_5G_SUB_BANDSTART 5400 +#define TRAINPOWER_DB_OFFSET 6 + +#define AH_PAPRD_GET_SCALE_FACTOR(_scale, _eep, _is2G, _channel) do{ if(_is2G) { _scale = (_eep->modal_header_2g.paprd_rate_mask_ht20>>25)&0x7; \ + } else { \ + if(_channel >= UPPER_5G_SUB_BANDSTART){ _scale = (_eep->modal_header_5g.paprd_rate_mask_ht20>>25)&0x7;} \ + else if((UPPER_5G_SUB_BANDSTART < _channel) && (_channel >= MID_5G_SUB_BANDSTART)) \ + { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>28)&0x7;} \ + else { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>25)&0x7;} } }while(0) + +#ifdef AH_ASSERT + #define ar9300FeatureNotSupported(feature, ah, func) \ + ath_hal_printf(ah, # feature \ + " not supported but called from %s\n", (func)), \ + hal_assert(0) +#else + #define ar9300FeatureNotSupported(feature, ah, func) \ + ath_hal_printf(ah, # feature \ + " not supported but called from %s\n", (func)) +#endif /* AH_ASSERT */ + +extern void ar9300_detach(struct ath_hal *ah); +extern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info); + +/* + * Green Tx, Based on different RSSI of Received Beacon thresholds, + * using different tx power by modified register tx power related values. + * The thresholds are decided by system team. + */ +#define WB225_SW_GREEN_TX_THRES1_DB 56 /* in dB */ +#define WB225_SW_GREEN_TX_THRES2_DB 41 /* in dB */ +#define WB225_OB_CALIBRATION_VALUE 5 /* For Green Tx OLPC Delta + Calibration Offset */ +#define WB225_OB_GREEN_TX_SHORT_VALUE 1 /* For Green Tx OB value + in short distance*/ +#define WB225_OB_GREEN_TX_MIDDLE_VALUE 3 /* For Green Tx OB value + in middle distance */ +#define WB225_OB_GREEN_TX_LONG_VALUE 5 /* For Green Tx OB value + in long distance */ +#define WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE 0x06060606 /* For SwGreen Tx + BB_powertx_rate9 reg + value in short + distance */ +#define WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE 0x0E0E0E0E /* For SwGreen Tx + BB_powertx_rate9 reg + value in middle + distance */ + + +/* Tx power for short distacnce in SwGreenTx.*/ +static const u_int8_t wb225_sw_gtx_tp_distance_short[ar9300_rate_size] = { + 6, /*ALL_TARGET_LEGACY_6_24*/ + 6, /*ALL_TARGET_LEGACY_36*/ + 6, /*ALL_TARGET_LEGACY_48*/ + 4, /*ALL_TARGET_LEGACY_54*/ + 6, /*ALL_TARGET_LEGACY_1L_5L*/ + 6, /*ALL_TARGET_LEGACY_5S*/ + 6, /*ALL_TARGET_LEGACY_11L*/ + 6, /*ALL_TARGET_LEGACY_11S*/ + 6, /*ALL_TARGET_HT20_0_8_16*/ + 6, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ + 4, /*ALL_TARGET_HT20_4*/ + 4, /*ALL_TARGET_HT20_5*/ + 4, /*ALL_TARGET_HT20_6*/ + 2, /*ALL_TARGET_HT20_7*/ + 0, /*ALL_TARGET_HT20_12*/ + 0, /*ALL_TARGET_HT20_13*/ + 0, /*ALL_TARGET_HT20_14*/ + 0, /*ALL_TARGET_HT20_15*/ + 0, /*ALL_TARGET_HT20_20*/ + 0, /*ALL_TARGET_HT20_21*/ + 0, /*ALL_TARGET_HT20_22*/ + 0, /*ALL_TARGET_HT20_23*/ + 6, /*ALL_TARGET_HT40_0_8_16*/ + 6, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ + 4, /*ALL_TARGET_HT40_4*/ + 4, /*ALL_TARGET_HT40_5*/ + 4, /*ALL_TARGET_HT40_6*/ + 2, /*ALL_TARGET_HT40_7*/ + 0, /*ALL_TARGET_HT40_12*/ + 0, /*ALL_TARGET_HT40_13*/ + 0, /*ALL_TARGET_HT40_14*/ + 0, /*ALL_TARGET_HT40_15*/ + 0, /*ALL_TARGET_HT40_20*/ + 0, /*ALL_TARGET_HT40_21*/ + 0, /*ALL_TARGET_HT40_22*/ + 0 /*ALL_TARGET_HT40_23*/ +}; + +/* Tx power for middle distacnce in SwGreenTx.*/ +static const u_int8_t wb225_sw_gtx_tp_distance_middle[ar9300_rate_size] = { + 14, /*ALL_TARGET_LEGACY_6_24*/ + 14, /*ALL_TARGET_LEGACY_36*/ + 14, /*ALL_TARGET_LEGACY_48*/ + 12, /*ALL_TARGET_LEGACY_54*/ + 14, /*ALL_TARGET_LEGACY_1L_5L*/ + 14, /*ALL_TARGET_LEGACY_5S*/ + 14, /*ALL_TARGET_LEGACY_11L*/ + 14, /*ALL_TARGET_LEGACY_11S*/ + 14, /*ALL_TARGET_HT20_0_8_16*/ + 14, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ + 14, /*ALL_TARGET_HT20_4*/ + 14, /*ALL_TARGET_HT20_5*/ + 12, /*ALL_TARGET_HT20_6*/ + 10, /*ALL_TARGET_HT20_7*/ + 0, /*ALL_TARGET_HT20_12*/ + 0, /*ALL_TARGET_HT20_13*/ + 0, /*ALL_TARGET_HT20_14*/ + 0, /*ALL_TARGET_HT20_15*/ + 0, /*ALL_TARGET_HT20_20*/ + 0, /*ALL_TARGET_HT20_21*/ + 0, /*ALL_TARGET_HT20_22*/ + 0, /*ALL_TARGET_HT20_23*/ + 14, /*ALL_TARGET_HT40_0_8_16*/ + 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ + 14, /*ALL_TARGET_HT40_4*/ + 14, /*ALL_TARGET_HT40_5*/ + 12, /*ALL_TARGET_HT40_6*/ + 10, /*ALL_TARGET_HT40_7*/ + 0, /*ALL_TARGET_HT40_12*/ + 0, /*ALL_TARGET_HT40_13*/ + 0, /*ALL_TARGET_HT40_14*/ + 0, /*ALL_TARGET_HT40_15*/ + 0, /*ALL_TARGET_HT40_20*/ + 0, /*ALL_TARGET_HT40_21*/ + 0, /*ALL_TARGET_HT40_22*/ + 0 /*ALL_TARGET_HT40_23*/ +}; + +/* OLPC DeltaCalibration Offset unit in half dB.*/ +static const u_int8_t wb225_gtx_olpc_cal_offset[6] = { + 0, /* OB0*/ + 16, /* OB1*/ + 9, /* OB2*/ + 5, /* OB3*/ + 2, /* OB4*/ + 0, /* OB5*/ +}; + +/* + * Definitions for HwGreenTx + */ +#define AR9485_HW_GREEN_TX_THRES1_DB 56 /* in dB */ +#define AR9485_HW_GREEN_TX_THRES2_DB 41 /* in dB */ +#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE 0x0C0C0A0A /* For HwGreen Tx + BB_powertx_rate9 reg + value in short + distance */ +#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE 0x10100E0E /* For HwGreenTx + BB_powertx_rate9 reg + value in middle + distance */ + +/* Tx power for short distacnce in HwGreenTx.*/ +static const u_int8_t ar9485_hw_gtx_tp_distance_short[ar9300_rate_size] = { + 14, /*ALL_TARGET_LEGACY_6_24*/ + 14, /*ALL_TARGET_LEGACY_36*/ + 8, /*ALL_TARGET_LEGACY_48*/ + 2, /*ALL_TARGET_LEGACY_54*/ + 14, /*ALL_TARGET_LEGACY_1L_5L*/ + 14, /*ALL_TARGET_LEGACY_5S*/ + 14, /*ALL_TARGET_LEGACY_11L*/ + 14, /*ALL_TARGET_LEGACY_11S*/ + 12, /*ALL_TARGET_HT20_0_8_16*/ + 12, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ + 12, /*ALL_TARGET_HT20_4*/ + 12, /*ALL_TARGET_HT20_5*/ + 8, /*ALL_TARGET_HT20_6*/ + 2, /*ALL_TARGET_HT20_7*/ + 0, /*ALL_TARGET_HT20_12*/ + 0, /*ALL_TARGET_HT20_13*/ + 0, /*ALL_TARGET_HT20_14*/ + 0, /*ALL_TARGET_HT20_15*/ + 0, /*ALL_TARGET_HT20_20*/ + 0, /*ALL_TARGET_HT20_21*/ + 0, /*ALL_TARGET_HT20_22*/ + 0, /*ALL_TARGET_HT20_23*/ + 10, /*ALL_TARGET_HT40_0_8_16*/ + 10, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ + 10, /*ALL_TARGET_HT40_4*/ + 10, /*ALL_TARGET_HT40_5*/ + 6, /*ALL_TARGET_HT40_6*/ + 2, /*ALL_TARGET_HT40_7*/ + 0, /*ALL_TARGET_HT40_12*/ + 0, /*ALL_TARGET_HT40_13*/ + 0, /*ALL_TARGET_HT40_14*/ + 0, /*ALL_TARGET_HT40_15*/ + 0, /*ALL_TARGET_HT40_20*/ + 0, /*ALL_TARGET_HT40_21*/ + 0, /*ALL_TARGET_HT40_22*/ + 0 /*ALL_TARGET_HT40_23*/ +}; + +/* Tx power for middle distacnce in HwGreenTx.*/ +static const u_int8_t ar9485_hw_gtx_tp_distance_middle[ar9300_rate_size] = { + 18, /*ALL_TARGET_LEGACY_6_24*/ + 18, /*ALL_TARGET_LEGACY_36*/ + 14, /*ALL_TARGET_LEGACY_48*/ + 12, /*ALL_TARGET_LEGACY_54*/ + 18, /*ALL_TARGET_LEGACY_1L_5L*/ + 18, /*ALL_TARGET_LEGACY_5S*/ + 18, /*ALL_TARGET_LEGACY_11L*/ + 18, /*ALL_TARGET_LEGACY_11S*/ + 16, /*ALL_TARGET_HT20_0_8_16*/ + 16, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ + 16, /*ALL_TARGET_HT20_4*/ + 16, /*ALL_TARGET_HT20_5*/ + 14, /*ALL_TARGET_HT20_6*/ + 12, /*ALL_TARGET_HT20_7*/ + 0, /*ALL_TARGET_HT20_12*/ + 0, /*ALL_TARGET_HT20_13*/ + 0, /*ALL_TARGET_HT20_14*/ + 0, /*ALL_TARGET_HT20_15*/ + 0, /*ALL_TARGET_HT20_20*/ + 0, /*ALL_TARGET_HT20_21*/ + 0, /*ALL_TARGET_HT20_22*/ + 0, /*ALL_TARGET_HT20_23*/ + 14, /*ALL_TARGET_HT40_0_8_16*/ + 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ + 14, /*ALL_TARGET_HT40_4*/ + 14, /*ALL_TARGET_HT40_5*/ + 14, /*ALL_TARGET_HT40_6*/ + 12, /*ALL_TARGET_HT40_7*/ + 0, /*ALL_TARGET_HT40_12*/ + 0, /*ALL_TARGET_HT40_13*/ + 0, /*ALL_TARGET_HT40_14*/ + 0, /*ALL_TARGET_HT40_15*/ + 0, /*ALL_TARGET_HT40_20*/ + 0, /*ALL_TARGET_HT40_21*/ + 0, /*ALL_TARGET_HT40_22*/ + 0 /*ALL_TARGET_HT40_23*/ +}; + +/* MIMO Modes used in TPC calculations */ +typedef enum { + AR9300_DEF_MODE = 0, /* Could be CDD or Direct */ + AR9300_TXBF_MODE, + AR9300_STBC_MODE +} AR9300_TXMODES; +typedef enum { + POSEIDON_STORED_REG_OBDB = 0, /* default OB/DB setting from ini */ + POSEIDON_STORED_REG_TPC = 1, /* default txpower value in TPC reg */ + POSEIDON_STORED_REG_BB_PWRTX_RATE9 = 2, /* default txpower value in + * BB_powertx_rate9 reg + */ + POSEIDON_STORED_REG_SZ /* Can not add anymore */ +} POSEIDON_STORED_REGS; + +typedef enum { + POSEIDON_STORED_REG_G2_OLPC_OFFSET = 0,/* default OB/DB setting from ini */ + POSEIDON_STORED_REG_G2_SZ /* should not exceed 3 */ +} POSEIDON_STORED_REGS_G2; + +#if AH_NEED_TX_DATA_SWAP +#if AH_NEED_RX_DATA_SWAP +#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB,0) +#else +#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB,0) +#endif +#elif AH_NEED_RX_DATA_SWAP +#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWRB,0) +#else +#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD,0) +#endif + +extern HAL_BOOL ar9300_rf_attach(struct ath_hal *, HAL_STATUS *); + +struct ath_hal; + +extern struct ath_hal_9300 * ar9300_new_state(u_int16_t devid, + HAL_ADAPTER_HANDLE osdev, HAL_SOFTC sc, + HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_BUS_TYPE bustype, + asf_amem_instance_handle amem_handle, + struct hal_reg_parm *hal_conf_parm, HAL_STATUS *status); +extern struct ath_hal * ar9300_attach(u_int16_t devid, + HAL_ADAPTER_HANDLE osdev, HAL_SOFTC sc, + HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_BUS_TYPE bustype, + asf_amem_instance_handle amem_handle, + struct hal_reg_parm *hal_conf_parm, + HAL_STATUS *status); +extern void ar9300_detach(struct ath_hal *ah); +extern void ar9300_read_revisions(struct ath_hal *ah); +extern HAL_BOOL ar9300_chip_test(struct ath_hal *ah); +extern HAL_BOOL ar9300_get_channel_edges(struct ath_hal *ah, + u_int16_t flags, u_int16_t *low, u_int16_t *high); +extern HAL_BOOL ar9300_fill_capability_info(struct ath_hal *ah); + +extern void ar9300_beacon_init(struct ath_hal *ah, + u_int32_t next_beacon, u_int32_t beacon_period, HAL_OPMODE opmode); +extern void ar9300_set_sta_beacon_timers(struct ath_hal *ah, + const HAL_BEACON_STATE *); + +extern HAL_BOOL ar9300_is_interrupt_pending(struct ath_hal *ah); +extern HAL_BOOL ar9300_get_pending_interrupts(struct ath_hal *ah, HAL_INT *, HAL_INT_TYPE, u_int8_t, HAL_BOOL); +extern HAL_INT ar9300_get_interrupts(struct ath_hal *ah); +extern HAL_INT ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL); +extern void ar9300_set_intr_mitigation_timer(struct ath_hal* ah, + HAL_INT_MITIGATION reg, u_int32_t value); +extern u_int32_t ar9300_get_intr_mitigation_timer(struct ath_hal* ah, + HAL_INT_MITIGATION reg); +extern u_int32_t ar9300_get_key_cache_size(struct ath_hal *); +extern HAL_BOOL ar9300_is_key_cache_entry_valid(struct ath_hal *, u_int16_t entry); +extern HAL_BOOL ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry); +extern HAL_BOOL ar9300_set_key_cache_entry_mac(struct ath_hal *, + u_int16_t entry, const u_int8_t *mac); +extern HAL_BOOL ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry, + const HAL_KEYVAL *k, const u_int8_t *mac, int xor_key); +extern HAL_BOOL ar9300_print_keycache(struct ath_hal *ah); + +extern void ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac); +extern HAL_BOOL ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *); +extern void ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mac); +extern HAL_BOOL ar9300_set_bss_id_mask(struct ath_hal *, const u_int8_t *); +extern HAL_STATUS ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg); +extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz); +extern HAL_BOOL ar9300_set_regulatory_domain(struct ath_hal *ah, + u_int16_t reg_domain, HAL_STATUS *stats); +extern u_int ar9300_get_wireless_modes(struct ath_hal *ah); +extern void ar9300_enable_rf_kill(struct ath_hal *); +extern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_OUTPUT_MUX_TYPE signalType); +extern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_OUTPUT_MUX_TYPE signalType); +extern HAL_BOOL ar9300_gpio_cfg_input(struct ath_hal *, u_int32_t gpio); +extern HAL_BOOL ar9300_gpio_set(struct ath_hal *, u_int32_t gpio, u_int32_t val); +extern u_int32_t ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio); +extern u_int32_t ar9300_gpio_get_intr(struct ath_hal *ah); +extern void ar9300_gpio_set_intr(struct ath_hal *ah, u_int, u_int32_t ilevel); +extern u_int32_t ar9300_gpio_get_polarity(struct ath_hal *ah); +extern void ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t, u_int32_t); +extern u_int32_t ar9300_gpio_get_mask(struct ath_hal *ah); +extern int ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map); +extern void ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state); +extern void ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enable); +extern void ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enable); +extern void ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, + u_int16_t assoc_id); +extern u_int32_t ar9300_ppm_get_rssi_dump(struct ath_hal *); +extern u_int32_t ar9300_ppm_arm_trigger(struct ath_hal *); +extern int ar9300_ppm_get_trigger(struct ath_hal *); +extern u_int32_t ar9300_ppm_force(struct ath_hal *); +extern void ar9300_ppm_un_force(struct ath_hal *); +extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *); +extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *); +extern void ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t); +extern u_int32_t ar9300_get_dcs_mode(struct ath_hal *ah); +extern u_int32_t ar9300_get_tsf32(struct ath_hal *ah); +extern u_int64_t ar9300_get_tsf64(struct ath_hal *ah); +extern u_int32_t ar9300_get_tsf2_32(struct ath_hal *ah); +extern void ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf); +extern void ar9300_reset_tsf(struct ath_hal *ah); +extern void ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *pSet); +extern u_int32_t ar9300_get_random_seed(struct ath_hal *ah); +extern HAL_BOOL ar9300_detect_card_present(struct ath_hal *ah); +extern void ar9300_update_mib_mac_stats(struct ath_hal *ah); +extern void ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats); +extern HAL_BOOL ar9300_is_japan_channel_spread_supported(struct ath_hal *ah); +extern u_int32_t ar9300_get_cur_rssi(struct ath_hal *ah); +extern u_int32_t ar9300_get_rssi_chain0(struct ath_hal *ah); +extern u_int ar9300_get_def_antenna(struct ath_hal *ah); +extern void ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna); +extern HAL_BOOL ar9300_set_antenna_switch(struct ath_hal *ah, + HAL_ANT_SETTING settings, HAL_CHANNEL *chan, u_int8_t *, u_int8_t *, u_int8_t *); +extern HAL_BOOL ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah); +extern HAL_BOOL ar9300_set_slot_time(struct ath_hal *, u_int); +extern HAL_BOOL ar9300_set_ack_timeout(struct ath_hal *, u_int); +extern u_int ar9300_get_ack_timeout(struct ath_hal *); +extern HAL_STATUS ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, + u_int32_t next_start, HAL_QUIET_FLAG flag); +extern void ar9300_set_pcu_config(struct ath_hal *); +extern HAL_STATUS ar9300_get_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, + u_int32_t, u_int32_t *); +extern HAL_BOOL ar9300_set_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, + u_int32_t, u_int32_t, HAL_STATUS *); +extern HAL_BOOL ar9300_get_diag_state(struct ath_hal *ah, int request, + const void *args, u_int32_t argsize, + void **result, u_int32_t *resultsize); +extern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info); +extern int8_t ar9300_get_11n_ext_busy(struct ath_hal *ah); +extern void ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode); +extern HAL_HT_RXCLEAR ar9300_get_11n_rx_clear(struct ath_hal *ah); +extern void ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); +extern HAL_BOOL ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, + int set_chip); +extern HAL_POWER_MODE ar9300_get_power_mode(struct ath_hal *ah); +extern HAL_BOOL ar9300_set_power_mode_awake(struct ath_hal *ah, int set_chip); +extern void ar9300_set_sm_power_mode(struct ath_hal *ah, HAL_SMPS_MODE mode); + +extern void ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off); + +extern void ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, + u_int16_t assoc_id); + + +#if ATH_WOW +extern void ar9300_wow_apply_pattern(struct ath_hal *ah, u_int8_t *p_ath_pattern, + u_int8_t *p_ath_mask, int32_t pattern_count, u_int32_t ath_pattern_len); +//extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah,u_int8_t *chipPatternBytes); +extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnable); +extern HAL_BOOL ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid, + HAL_BOOL offloadEnable); +#if ATH_WOW_OFFLOAD +/* ARP offload */ +#define WOW_OFFLOAD_ARP_INFO_MAX 2 + +struct hal_wow_offload_arp_info { + u_int32_t valid; + u_int32_t id; + + u_int32_t Flags; + union { + u_int8_t u8[4]; + u_int32_t u32; + } RemoteIPv4Address; + union { + u_int8_t u8[4]; + u_int32_t u32; + } HostIPv4Address; + union { + u_int8_t u8[6]; + u_int32_t u32[2]; + } MacAddress; +}; + +/* NS offload */ +#define WOW_OFFLOAD_NS_INFO_MAX 2 + +struct hal_wow_offload_ns_info { + u_int32_t valid; + u_int32_t id; + + u_int32_t Flags; + union { + u_int8_t u8[16]; + u_int32_t u32[4]; + } RemoteIPv6Address; + union { + u_int8_t u8[16]; + u_int32_t u32[4]; + } SolicitedNodeIPv6Address; + union { + u_int8_t u8[6]; + u_int32_t u32[2]; + } MacAddress; + union { + u_int8_t u8[16]; + u_int32_t u32[4]; + } TargetIPv6Addresses[2]; +}; + +extern void ar9300_wowoffload_prep(struct ath_hal *ah); +extern void ar9300_wowoffload_post(struct ath_hal *ah); +extern u_int32_t ar9300_wowoffload_download_rekey_data(struct ath_hal *ah, u_int32_t *data, u_int32_t size); +extern void ar9300_wowoffload_retrieve_data(struct ath_hal *ah, void *buf, u_int32_t param); +extern void ar9300_wowoffload_download_acer_magic(struct ath_hal *ah, HAL_BOOL valid, u_int8_t* datap, u_int32_t bytes); +extern void ar9300_wowoffload_download_acer_swka(struct ath_hal *ah, u_int32_t id, HAL_BOOL valid, u_int32_t period, u_int32_t size, u_int32_t* datap); +extern void ar9300_wowoffload_download_arp_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); +extern void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); +#endif /* ATH_WOW_OFFLOAD */ +#endif + +extern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, + HAL_CHANNEL *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask, + u_int8_t rxchainmask, HAL_HT_EXTPROTSPACING extprotspacing, + HAL_BOOL b_channel_change, HAL_STATUS *status, int is_scan); +extern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, HAL_CHANNEL *chan, + HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask); +extern HAL_BOOL ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type); +extern void ar9300_init_pll(struct ath_hal *ah, HAL_CHANNEL *chan); +extern void ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t rxMask); +extern u_int16_t ar9300_is_single_ant_power_save_possible(struct ath_hal *ah); +extern void ar9300_set_operating_mode(struct ath_hal *ah, int opmode); +extern HAL_BOOL ar9300_phy_disable(struct ath_hal *ah); +extern HAL_BOOL ar9300_disable(struct ath_hal *ah); +extern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, HAL_CHANNEL *); +extern HAL_BOOL ar9300_calibration(struct ath_hal *ah, HAL_CHANNEL *chan, + u_int8_t rxchainmask, HAL_BOOL longcal, HAL_BOOL *isIQdone, int is_scan, u_int32_t *sched_cals); +extern void ar9300_reset_cal_valid(struct ath_hal *ah, HAL_CHANNEL *chan, + HAL_BOOL *isIQdone, u_int32_t cal_type); +extern void ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains); +extern void ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains); +extern void ar9300_temp_comp_cal_collect(struct ath_hal *ah); +extern void ar9300_temp_comp_calibration(struct ath_hal *ah, u_int8_t num_chains); +extern int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah); +extern void ar9300_upload_noise_floor(struct ath_hal *ah, int is2G, int16_t nfarray[]); + +extern HAL_BOOL ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit, + u_int16_t extra_txpow, u_int16_t tpc_in_db); +extern void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf, + HAL_CHANNEL *chan, int is_scan); +extern HAL_BOOL ar9300_load_nf(struct ath_hal *ah, int16_t nf[]); + +extern HAL_RFGAIN ar9300_get_rfgain(struct ath_hal *ah); +extern const HAL_RATE_TABLE *ar9300_get_rate_table(struct ath_hal *, u_int mode); +extern int16_t ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode, + u_int8_t rate_index, u_int8_t chainmask, u_int8_t mimo_mode); +extern void ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode, + HAL_CHANNEL_INTERNAL *chan, + u_int8_t powerPerRate[], + u_int8_t chainmask); +extern void ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah, + u_int8_t powerPerRate[]); +extern void ar9300_reset_tx_status_ring(struct ath_hal *ah); +extern void ar9300_enable_mib_counters(struct ath_hal *); +extern void ar9300_disable_mib_counters(struct ath_hal *); +extern void ar9300_ani_attach(struct ath_hal *); +extern void ar9300_ani_detach(struct ath_hal *); +extern struct ar9300_ani_state *ar9300_ani_get_current_state(struct ath_hal *); +extern struct ar9300_stats *ar9300_ani_get_current_stats(struct ath_hal *); +extern HAL_BOOL ar9300_ani_control(struct ath_hal *, HAL_ANI_CMD cmd, int param); +struct ath_rx_status; + +extern void ar9300_process_mib_intr(struct ath_hal *, const HAL_NODE_STATS *); +extern void ar9300_ani_ar_poll(struct ath_hal *, const HAL_NODE_STATS *, + HAL_CHANNEL *, HAL_ANISTATS *); +extern void ar9300_ani_reset(struct ath_hal *, HAL_BOOL is_scanning); +extern void ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode); +extern void ar9300_enable_tpc(struct ath_hal *); + +extern HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is2GHz); +extern void ar9300_rx_gain_table_apply(struct ath_hal *ah); +extern void ar9300_tx_gain_table_apply(struct ath_hal *ah); +extern void ar9300_mat_enable(struct ath_hal *ah, int enable); +extern void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry); +extern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, HAL_CHANNEL * chan); + +#ifdef AH_SUPPORT_AR9300 +/* BB Panic Watchdog declarations */ +#define HAL_BB_PANIC_WD_TMO 25 /* in ms, 0 to disable */ +#define HAL_BB_PANIC_WD_TMO_HORNET 85 +extern void ar9300_config_bb_panic_watchdog(struct ath_hal *); +extern void ar9300_handle_bb_panic(struct ath_hal *); +extern int ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic); +extern HAL_BOOL ar9300_handle_radar_bb_panic(struct ath_hal *ah); +#endif +extern void ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason); + +/* DFS declarations */ +#ifdef ATH_SUPPORT_DFS +extern void ar9300_check_dfs(struct ath_hal *ah, HAL_CHANNEL *chan); +extern void ar9300_dfs_found(struct ath_hal *ah, HAL_CHANNEL *chan, + u_int64_t nolTime); +extern void ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); +extern void ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); +extern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, HAL_CHANNEL *chan); +extern struct dfs_pulse * ar9300_get_dfs_radars(struct ath_hal *ah, + u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses, + int *numb5radars, HAL_PHYERR_PARAM *pe); +extern void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val); +extern u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable); +extern void ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable); +extern void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start); +#endif + +extern HAL_CHANNEL * ar9300_get_extension_channel(struct ath_hal *ah); +extern HAL_BOOL ar9300_is_fast_clock_enabled(struct ath_hal *ah); + + +extern void ar9300_mark_phy_inactive(struct ath_hal *ah); + +/* Spectral scan declarations */ +extern void ar9300_configure_spectral_scan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); +extern void ar9300_set_cca_threshold(struct ath_hal *ah, u_int8_t thresh62); +extern void ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); +extern HAL_BOOL ar9300_is_spectral_active(struct ath_hal *ah); +extern HAL_BOOL ar9300_is_spectral_enabled(struct ath_hal *ah); +extern void ar9300_start_spectral_scan(struct ath_hal *ah); +extern void ar9300_stop_spectral_scan(struct ath_hal *ah); +extern u_int32_t ar9300_get_spectral_config(struct ath_hal *ah); +extern void ar9300_restore_spectral_config(struct ath_hal *ah, u_int32_t restoreval); +int16_t ar9300_get_ctl_chan_nf(struct ath_hal *ah); +int16_t ar9300_get_ext_chan_nf(struct ath_hal *ah); +/* End spectral scan declarations */ + +/* Raw ADC capture functions */ +extern void ar9300_enable_test_addac_mode(struct ath_hal *ah); +extern void ar9300_disable_test_addac_mode(struct ath_hal *ah); +extern void ar9300_begin_adc_capture(struct ath_hal *ah, int auto_agc_gain); +extern HAL_STATUS ar9300_retrieve_capture_data(struct ath_hal *ah, u_int16_t chain_mask, int disable_dc_filter, void *sample_buf, u_int32_t *max_samples); +extern HAL_STATUS ar9300_calc_adc_ref_powers(struct ath_hal *ah, int freq_mhz, int16_t *sample_min, int16_t *sample_max, int32_t *chain_ref_pwr, int num_chain_ref_pwr); +extern HAL_STATUS ar9300_get_min_agc_gain(struct ath_hal *ah, int freq_mhz, int32_t *chain_gain, int num_chain_gain); + +extern HAL_BOOL ar9300_reset_11n(struct ath_hal *ah, HAL_OPMODE opmode, + HAL_CHANNEL *chan, HAL_BOOL b_channel_change, HAL_STATUS *status); +extern void ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now); + +extern void ar9300_get_channel_centers(struct ath_hal *ah, + HAL_CHANNEL_INTERNAL *chan, + CHAN_CENTERS *centers); +extern u_int16_t ar9300_get_ctl_center(struct ath_hal *ah, + HAL_CHANNEL_INTERNAL *chan); +extern u_int16_t ar9300_get_ext_center(struct ath_hal *ah, + HAL_CHANNEL_INTERNAL *chan); +extern u_int32_t ar9300_get_mib_cycle_counts_pct(struct ath_hal *, u_int32_t*, u_int32_t*, u_int32_t*); + +extern void ar9300_dma_reg_dump(struct ath_hal *); +extern HAL_BOOL ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable); +extern HAL_BOOL ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable); +extern HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable); +extern HAL_BOOL ar9300_detect_bb_hang(struct ath_hal *ah); +extern HAL_BOOL ar9300_detect_mac_hang(struct ath_hal *ah); + +#ifdef ATH_BT_COEX +extern void ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo); +extern void ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf); +extern void ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum); +extern void ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); +extern void ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh); +extern void ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, u_int32_t value); +extern void ar9300_bt_coex_disable(struct ath_hal *ah); +extern int ar9300_bt_coex_enable(struct ath_hal *ah); +extern void ar9300_init_bt_coex(struct ath_hal *ah); +extern u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg); +extern u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn); +#endif +extern int ar9300_alloc_generic_timer(struct ath_hal *ah, HAL_GEN_TIMER_DOMAIN tsf); +extern void ar9300_free_generic_timer(struct ath_hal *ah, int index); +extern void ar9300_start_generic_timer(struct ath_hal *ah, int index, u_int32_t timer_next, + u_int32_t timer_period); +extern void ar9300_stop_generic_timer(struct ath_hal *ah, int index); +extern void ar9300_get_gen_timer_interrupts(struct ath_hal *ah, u_int32_t *trigger, + u_int32_t *thresh); +extern void ar9300_start_tsf2(struct ath_hal *ah); + +extern void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi); +extern HAL_BOOL ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah); +extern void ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah); +extern void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value); +extern void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah); +extern int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah); +extern void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, + u_int32_t rssi_threshold); +extern void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah); +extern void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on); +extern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah); +extern void ar9300_get_vow_stats(struct ath_hal *ah, HAL_VOWSTATS *p_stats, + u_int8_t); + +extern int ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq); +extern int ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq); +extern void ar9300_wow_set_gpio_reset_low(struct ath_hal * ah); +extern void ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_COUNTERS*); +extern void ar9300_clear_mib_counters(struct ath_hal *ah); + +/* EEPROM interface functions */ +/* Common Interface functions */ +extern HAL_STATUS ar9300_eeprom_attach(struct ath_hal *); +extern u_int32_t ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param); + +extern u_int32_t ar9300_ini_fixup(struct ath_hal *ah, + ar9300_eeprom_t *p_eep_data, + u_int32_t reg, + u_int32_t val); + +extern HAL_STATUS ar9300_eeprom_set_transmit_power(struct ath_hal *ah, + ar9300_eeprom_t *p_eep_data, HAL_CHANNEL_INTERNAL *chan, + u_int16_t cfg_ctl, u_int16_t twice_antenna_reduction, + u_int16_t twice_max_regulatory_power, u_int16_t power_limit); +extern void ar9300_eeprom_set_addac(struct ath_hal *, HAL_CHANNEL_INTERNAL *); +extern HAL_BOOL ar9300_eeprom_set_param(struct ath_hal *ah, EEPROM_PARAM param, u_int32_t value); +extern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, HAL_CHANNEL_INTERNAL *); +extern HAL_BOOL ar9300_eeprom_read_word(struct ath_hal *, u_int off, u_int16_t *data); +extern HAL_BOOL ar9300_eeprom_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); +extern HAL_BOOL ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi); + +extern HAL_BOOL ar9300_flash_read(struct ath_hal *, u_int off, u_int16_t *data); +extern HAL_BOOL ar9300_flash_write(struct ath_hal *, u_int off, u_int16_t data); +extern u_int ar9300_eeprom_dump_support(struct ath_hal *ah, void **pp_e); +extern u_int8_t ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp, HAL_FREQ_BAND freq_band); +extern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, HAL_CHANNEL_INTERNAL *chan, + u_int8_t index, u_int16_t *config); +extern u_int8_t* ar9300_eeprom_get_cust_data(struct ath_hal_9300 *ahp); +extern u_int8_t *ar9300_eeprom_get_spur_chans_ptr(struct ath_hal *ah, HAL_BOOL is_2ghz); +extern HAL_BOOL ar9300_interference_is_present(struct ath_hal *ah); +extern HAL_BOOL ar9300_tuning_caps_apply(struct ath_hal *ah); +extern void ar9300_disp_tpc_tables(struct ath_hal *ah); +extern u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah); +extern u_int8_t ar9300_eeprom_set_tx_gain_cap(struct ath_hal *ah, int *tx_gain_max); +extern u_int8_t ar9300_eeprom_tx_gain_table_index_max_apply(struct ath_hal *ah, u_int16_t channel); + +/* Common EEPROM Help function */ +extern void ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable); +extern void ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs); + +extern u_int ar9300_mac_to_clks(struct ath_hal *ah, u_int clks); + +/* tx_bf interface */ +#define ar9300_init_txbf(ah) +#define ar9300_set_11n_txbf_sounding(ah, ds, series, cec, opt) +#define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt) +#define ar9300_txbf_save_cv_from_compress( \ + ah, key_idx, mimo_control, compress_rpt) \ + false +#define ar9300_txbf_save_cv_from_non_compress( \ + ah, key_idx, mimo_control, non_compress_rpt) \ + false +#define ar9300_txbf_rc_update( \ + ah, rx_status, local_h, csi_frame, ness_a, ness_b, bw) \ + false +#define ar9300_fill_csi_frame( \ + ah, rx_status, bandwidth, local_h, csi_frame_body) \ + 0 +#define ar9300_fill_txbf_capabilities(ah) +#define ar9300_get_txbf_capabilities(ah) NULL +#define ar9300_txbf_set_key( \ + ah, entry, rx_staggered_sounding, channel_estimation_cap, mmss) +#define ar9300_read_key_cache_mac(ah, entry, mac) false +#define ar9300_txbf_get_cv_cache_nr(ah, key_idx, nr) +#define ar9300_set_selfgenrate_limit(ah, ts_ratecode) +#define ar9300_reset_lowest_txrate(ah) +#define ar9300_txbf_set_basic_set(ah) + +extern void ar9300_crdc_rx_notify(struct ath_hal *ah, struct ath_rx_status *rxs); +extern void ar9300_chain_rssi_diff_compensation(struct ath_hal *ah); + + + +#if ATH_SUPPORT_MCI +extern void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); +extern void ar9300_mci_bt_coex_disable(struct ath_hal *ah); +extern int ar9300_mci_bt_coex_enable(struct ath_hal *ah); +extern void ar9300_mci_setup (struct ath_hal *ah, u_int32_t gpm_addr, + void *gpm_buf, u_int16_t len, + u_int32_t sched_addr); +extern void ar9300_mci_remote_reset(struct ath_hal *ah, HAL_BOOL wait_done); +extern void ar9300_mci_send_lna_transfer(struct ath_hal *ah, HAL_BOOL wait_done); +extern void ar9300_mci_send_sys_waking(struct ath_hal *ah, HAL_BOOL wait_done); +extern HAL_BOOL ar9300_mci_send_message (struct ath_hal *ah, u_int8_t header, + u_int32_t flag, u_int32_t *payload, u_int8_t len, + HAL_BOOL wait_done, HAL_BOOL check_bt); +extern u_int32_t ar9300_mci_get_interrupt (struct ath_hal *ah, + u_int32_t *mci_int, + u_int32_t *mci_int_rx_msg); +extern u_int32_t ar9300_mci_state (struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data); +extern void ar9300_mci_reset (struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g, HAL_BOOL is_full_sleep); +extern void ar9300_mci_send_coex_halt_bt_gpm(struct ath_hal *ah, HAL_BOOL halt, HAL_BOOL wait_done); +extern void ar9300_mci_mute_bt(struct ath_hal *ah); +extern u_int32_t ar9300_mci_wait_for_gpm(struct ath_hal *ah, u_int8_t gpm_type, u_int8_t gpm_opcode, int32_t time_out); +extern void ar9300_mci_enable_interrupt(struct ath_hal *ah); +extern void ar9300_mci_disable_interrupt(struct ath_hal *ah); +extern void ar9300_mci_detach (struct ath_hal *ah); +extern u_int32_t ar9300_mci_check_int (struct ath_hal *ah, u_int32_t ints); +extern void ar9300_mci_sync_bt_state (struct ath_hal *ah); +extern void ar9300_mci_2g5g_changed(struct ath_hal *ah, HAL_BOOL is_2g); +extern void ar9300_mci_2g5g_switch(struct ath_hal *ah, HAL_BOOL wait_done); +#if ATH_SUPPORT_AIC +extern u_int32_t ar9300_aic_calibration (struct ath_hal *ah); +extern u_int32_t ar9300_aic_start_normal (struct ath_hal *ah); +#endif +#endif + +extern HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable); + +extern HAL_BOOL ar9300_regulatory_domain_override( + struct ath_hal *ah, u_int16_t regdmn); +#if ATH_ANT_DIV_COMB +extern void ar9300_ant_div_comb_get_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); +extern void ar9300_ant_div_comb_set_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); +#endif /* ATH_ANT_DIV_COMB */ +extern void ar9300_disable_phy_restart(struct ath_hal *ah, + int disable_phy_restart); +extern void ar9300_enable_keysearch_always(struct ath_hal *ah, int enable); +extern HAL_BOOL ar9300ForceVCS( struct ath_hal *ah); +extern HAL_BOOL ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val); +extern HAL_BOOL ar9300Get3StreamSignature( struct ath_hal *ah); + +#ifdef ATH_TX99_DIAG +#ifndef ATH_SUPPORT_HTC +extern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, u_int32_t txpower); +extern void ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask); +extern void ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype); +extern void ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data); +extern void ar9300_tx99_stop(struct ath_hal *ah); +#endif /* ATH_SUPPORT_HTC */ +#endif /* ATH_TX99_DIAG */ + +enum { + AR9300_COEFF_TX_TYPE = 0, + AR9300_COEFF_RX_TYPE +}; + +#endif /* _ATH_AR9300_H_ */ diff --git a/hal/ar9300/ar9300_aic.c b/hal/ar9300/ar9300_aic.c new file mode 100644 index 000000000000..e35d76c56fec --- /dev/null +++ b/hal/ar9300/ar9300_aic.c @@ -0,0 +1,727 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300phy.h" + +#if ATH_SUPPORT_AIC + +#define ATH_AIC_TEST_PATTERN 1 + +struct ath_aic_sram_info { + HAL_BOOL valid; + u_int8_t rot_quad_att_db; + HAL_BOOL vga_quad_sign; + u_int8_t rot_dir_att_db; + HAL_BOOL vga_dir_sign; + u_int8_t com_att_6db; + }; + +struct ath_aic_out_info { + int16_t dir_path_gain_lin; + int16_t quad_path_gain_lin; + struct ath_aic_sram_info sram; + }; + +#define ATH_AIC_MAX_COM_ATT_DB_TABLE 6 +#define ATH_AIC_MAX_AIC_LIN_TABLE 69 +#define ATH_AIC_MIN_ROT_DIR_ATT_DB 0 +#define ATH_AIC_MIN_ROT_QUAD_ATT_DB 0 +#define ATH_AIC_MAX_ROT_DIR_ATT_DB 37 +#define ATH_AIC_MAX_ROT_QUAD_ATT_DB 37 +#define ATH_AIC_SRAM_AUTO_INCREMENT 0x80000000 +#define ATH_AIC_SRAM_GAIN_TABLE_OFFSET 0x280 +#define ATH_AIC_SRAM_CAL_OFFSET 0x140 +#define ATH_AIC_MAX_CAL_COUNT 5 +#define ATH_AIC_MEAS_MAG_THRESH 20 +#define ATH_AIC_BT_JUPITER_CTRL 0x66820 +#define ATH_AIC_BT_AIC_ENABLE 0x02 + + +static const u_int8_t com_att_db_table[ATH_AIC_MAX_COM_ATT_DB_TABLE] = { + 0, 3, 9, 15, 21, 27}; + +static const u_int16_t aic_lin_table[ATH_AIC_MAX_AIC_LIN_TABLE] = { + 8191, 7300, 6506, 5799, 5168, 4606, 4105, 3659, + 3261, 2906, 2590, 2309, 2057, 1834, 1634, 1457, + 1298, 1157, 1031, 919, 819, 730, 651, 580, + 517, 461, 411, 366, 326, 291, 259, 231, + 206, 183, 163, 146, 130, 116, 103, 92, + 82, 73, 65, 58, 52, 46, 41, 37, + 33, 29, 26, 23, 21, 18, 16, 15, + 13, 12, 10, 9, 8, 7, 7, 6, + 5, 5, 4, 4, 3}; + +#if ATH_AIC_TEST_PATTERN +static const u_int32_t aic_test_pattern[ATH_AIC_MAX_BT_CHANNEL] = { +0x00000, // 0 +0x00000, +0x00000, +0x00000, +0x00000, +0x00000, +0x00000, +0x00000, +0x00000, +0x1918d, +0x1938d, // 10 +0x00000, +0x1978d, +0x19e8d, +0x00000, +0x00000, +0x00000, +0x00000, +0x00000, +0x00000, +0x00000, // 20 +0x00000, +0x00000, +0x1ce8f, +0x00000, +0x00000, +0x00000, +0x00000, +0x1ca93, +0x1c995, +0x00000, // 30 +0x1c897, +0x1c899, +0x00000, +0x00000, +0x1c79f, +0x00000, +0x1c7a5, +0x1c6ab, +0x00000, +0x00000, // 40 +0x00000, +0x00000, +0x1c63f, +0x00000, +0x1c52b, +0x1c525, +0x1c523, +0x00000, +0x00000, +0x00000, // 50 +0x00000, +0x00000, +0x1c617, +0x00000, +0x1c615, +0x1c613, +0x00000, +0x00000, +0x00000, +0x00000, // 60 +0x1c80f, +0x1c90f, +0x1c90f, +0x1ca0f, +0x1ca0d, +0x1cb0d, +0x00000, +0x00000, +0x00000, +0x00000, // 70 +0x1d00d, +0x00000, +0x00000, +0x00000, +0x00000, +0x00000, +0x00000, +0x00000 +}; +#endif + +static void +ar9300_aic_gain_table(struct ath_hal *ah) +{ + u_int32_t aic_atten_word[19], i; + + /* Program gain table */ + aic_atten_word[0] = (0x1 & 0xf)<<14 | (0x1f & 0x1f)<<9 | (0x0 & 0xf)<<5 | + (0x1f & 0x1f); // -01 dB: 4'd1, 5'd31, 00 dB: 4'd0, 5'd31; + aic_atten_word[1] = (0x3 & 0xf)<<14 | (0x1f & 0x1f)<<9 | (0x2 & 0xf)<<5 | + (0x1f & 0x1f); // -03 dB: 4'd3, 5'd31, -02 dB: 4'd2, 5'd31; + aic_atten_word[2] = (0x5 & 0xf)<<14 | (0x1f & 0x1f)<<9 | (0x4 & 0xf)<<5 | + (0x1f & 0x1f); // -05 dB: 4'd5, 5'd31, -04 dB: 4'd4, 5'd31; + aic_atten_word[3] = (0x1 & 0xf)<<14 | (0x1e & 0x1f)<<9 | (0x0 & 0xf)<<5 | + (0x1e & 0x1f); // -07 dB: 4'd1, 5'd30, -06 dB: 4'd0, 5'd30; + aic_atten_word[4] = (0x3 & 0xf)<<14 | (0x1e & 0x1f)<<9 | (0x2 & 0xf)<<5 | + (0x1e & 0x1f); // -09 dB: 4'd3, 5'd30, -08 dB: 4'd2, 5'd30; + aic_atten_word[5] = (0x5 & 0xf)<<14 | (0x1e & 0x1f)<<9 | (0x4 & 0xf)<<5 | + (0x1e & 0x1f); // -11 dB: 4'd5, 5'd30, -10 dB: 4'd4, 5'd30; + aic_atten_word[6] = (0x1 & 0xf)<<14 | (0xf & 0x1f)<<9 | (0x0 & 0xf)<<5 | + (0xf & 0x1f); // -13 dB: 4'd1, 5'd15, -12 dB: 4'd0, 5'd15; + aic_atten_word[7] = (0x3 & 0xf)<<14 | (0xf & 0x1f)<<9 | (0x2 & 0xf)<<5 | + (0xf & 0x1f); // -15 dB: 4'd3, 5'd15, -14 dB: 4'd2, 5'd15; + aic_atten_word[8] = (0x5 & 0xf)<<14 | (0xf & 0x1f)<<9 | (0x4 & 0xf)<<5 | + (0xf & 0x1f); // -17 dB: 4'd5, 5'd15, -16 dB: 4'd4, 5'd15; + aic_atten_word[9] = (0x1 & 0xf)<<14 | (0x7 & 0x1f)<<9 | (0x0 & 0xf)<<5 | + (0x7 & 0x1f); // -19 dB: 4'd1, 5'd07, -18 dB: 4'd0, 5'd07; + aic_atten_word[10] =(0x3 & 0xf)<<14 | (0x7 & 0x1f)<<9 | (0x2 & 0xf)<<5 | + (0x7 & 0x1f); // -21 dB: 4'd3, 5'd07, -20 dB: 4'd2, 5'd07; + aic_atten_word[11] =(0x5 & 0xf)<<14 | (0x7 & 0x1f)<<9 | (0x4 & 0xf)<<5 | + (0x7 & 0x1f); // -23 dB: 4'd5, 5'd07, -22 dB: 4'd4, 5'd07; + aic_atten_word[12] =(0x7 & 0xf)<<14 | (0x7 & 0x1f)<<9 | (0x6 & 0xf)<<5 | + (0x7 & 0x1f); // -25 dB: 4'd7, 5'd07, -24 dB: 4'd6, 5'd07; + aic_atten_word[13] =(0x3 & 0xf)<<14 | (0x3 & 0x1f)<<9 | (0x2 & 0xf)<<5 | + (0x3 & 0x1f); // -27 dB: 4'd3, 5'd03, -26 dB: 4'd2, 5'd03; + aic_atten_word[14] =(0x5 & 0xf)<<14 | (0x3 & 0x1f)<<9 | (0x4 & 0xf)<<5 | + (0x3 & 0x1f); // -29 dB: 4'd5, 5'd03, -28 dB: 4'd4, 5'd03; + aic_atten_word[15] =(0x1 & 0xf)<<14 | (0x1 & 0x1f)<<9 | (0x0 & 0xf)<<5 | + (0x1 & 0x1f); // -31 dB: 4'd1, 5'd01, -30 dB: 4'd0, 5'd01; + aic_atten_word[16] =(0x3 & 0xf)<<14 | (0x1 & 0x1f)<<9 | (0x2 & 0xf)<<5 | + (0x1 & 0x1f); // -33 dB: 4'd3, 5'd01, -32 dB: 4'd2, 5'd01; + aic_atten_word[17] =(0x5 & 0xf)<<14 | (0x1 & 0x1f)<<9 | (0x4 & 0xf)<<5 | + (0x1 & 0x1f); // -35 dB: 4'd5, 5'd01, -34 dB: 4'd4, 5'd01; + aic_atten_word[18] =(0x7 & 0xf)<<14 | (0x1 & 0x1f)<<9 | (0x6 & 0xf)<<5 | + (0x1 & 0x1f); // -37 dB: 4'd7, 5'd01, -36 dB: 4'd6, 5'd01; + + /* Write to Gain table with auto increment enabled. */ + OS_REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000), + (ATH_AIC_SRAM_AUTO_INCREMENT | + ATH_AIC_SRAM_GAIN_TABLE_OFFSET)); + + for (i = 0; i < 19; i++) { + OS_REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), + aic_atten_word[i]); + } + +} + +static int16_t +ar9300_aic_find_valid (struct ath_aic_sram_info *cal_sram, + HAL_BOOL dir, + u_int8_t index) +{ + int16_t i; + + if (dir) { + /* search forward */ + for (i = index + 1; i < ATH_AIC_MAX_BT_CHANNEL; i++) { + if (cal_sram[i].valid) { + break; + } + } + } + else { + /* search backword */ + for (i = index - 1; i >= 0; i--) { + if (cal_sram[i].valid) { + break; + } + } + } + if ((i >= ATH_AIC_MAX_BT_CHANNEL) || (i < 0)) { + i = -1; + } + + return i; +} + +static int16_t +ar9300_aic_find_index (u_int8_t type, int16_t value) +{ + int16_t i = -1; + + /* + * type 0: aic_lin_table, 1: com_att_db_table + */ + + if (type == 0) { + /* Find in aic_lin_table */ + for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) { + if (aic_lin_table[i] >= value) { + break; + } + } + } + else if (type == 1) { + /* find in com_att_db_table */ + for (i = 0; i < ATH_AIC_MAX_COM_ATT_DB_TABLE; i++) { + if (com_att_db_table[i] > value) { + i--; + break; + } + } + if (i >= ATH_AIC_MAX_COM_ATT_DB_TABLE) { + i = -1; + } + } + + return i; +} + +static HAL_BOOL +ar9300_aic_cal_post_process (struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ath_aic_sram_info cal_sram[ATH_AIC_MAX_BT_CHANNEL]; + struct ath_aic_out_info aic_sram[ATH_AIC_MAX_BT_CHANNEL]; + u_int32_t dir_path_gain_idx, quad_path_gain_idx, value; + u_int32_t fixed_com_att_db; + int8_t dir_path_sign, quad_path_sign; + int16_t i; + HAL_BOOL ret = AH_TRUE; + + /* Read CAL_SRAM and get valid values. */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) CAL_SRAM:\n"); + + for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { + OS_REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1, + (ATH_AIC_SRAM_CAL_OFFSET + i*4)); +#if ATH_AIC_TEST_PATTERN + value = aic_test_pattern[i]; +#else + value = OS_REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1); +#endif + cal_sram[i].valid = MS(value, AR_PHY_AIC_SRAM_VALID); + cal_sram[i].rot_quad_att_db = MS(value, + AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB); + cal_sram[i].vga_quad_sign = MS(value, AR_PHY_AIC_SRAM_VGA_QUAD_SIGN); + cal_sram[i].rot_dir_att_db = MS(value, AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB); + cal_sram[i].vga_dir_sign = MS(value, AR_PHY_AIC_SRAM_VGA_DIR_SIGN); + cal_sram[i].com_att_6db = MS(value, AR_PHY_AIC_SRAM_COM_ATT_6DB); + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(AIC) %2d %2d %2d %2d %2d %2d %2d 0x%05x\n", + i, cal_sram[i].vga_quad_sign, + cal_sram[i].vga_dir_sign, + cal_sram[i].rot_dir_att_db, + cal_sram[i].rot_quad_att_db, + cal_sram[i].com_att_6db, + cal_sram[i].valid, + value); + + if (cal_sram[i].valid) { + dir_path_gain_idx = cal_sram[i].rot_dir_att_db + + com_att_db_table[cal_sram[i].com_att_6db]; + quad_path_gain_idx = cal_sram[i].rot_quad_att_db + + com_att_db_table[cal_sram[i].com_att_6db]; + dir_path_sign = (cal_sram[i].vga_dir_sign) ? 1 : -1; + quad_path_sign = (cal_sram[i].vga_quad_sign) ? 1 : -1; + aic_sram[i].dir_path_gain_lin = dir_path_sign * + aic_lin_table[dir_path_gain_idx]; + aic_sram[i].quad_path_gain_lin = quad_path_sign * + aic_lin_table[quad_path_gain_idx]; + } + } + + for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { + int16_t start_idx, end_idx; + + if (cal_sram[i].valid) { + continue; + } + + start_idx = ar9300_aic_find_valid(cal_sram, 0, i); + end_idx = ar9300_aic_find_valid(cal_sram, 1, i); + + if (start_idx < 0) + { + /* extrapolation */ + start_idx = end_idx; + end_idx = ar9300_aic_find_valid(cal_sram, 1, start_idx); + + if (end_idx < 0) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(AIC) Error (1): i = %d, start_idx = %d \n", + i, start_idx); + ret = AH_FALSE; + break; + } + aic_sram[i].dir_path_gain_lin = + ((aic_sram[start_idx].dir_path_gain_lin - + aic_sram[end_idx].dir_path_gain_lin) * + (start_idx - i) + ((end_idx - i) >> 1)) / + (end_idx - i) + + aic_sram[start_idx].dir_path_gain_lin; + aic_sram[i].quad_path_gain_lin = + ((aic_sram[start_idx].quad_path_gain_lin - + aic_sram[end_idx].quad_path_gain_lin) * + (start_idx - i) + ((end_idx - i) >> 1)) / + (end_idx - i) + + aic_sram[start_idx].quad_path_gain_lin; + } + if (end_idx < 0) + { + /* extrapolation */ + end_idx = ar9300_aic_find_valid(cal_sram, 0, start_idx); + + if (end_idx < 0) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(AIC) Error (2): i = %d, start_idx = %d\n", + i, start_idx); + ret = AH_FALSE; + break; + } + aic_sram[i].dir_path_gain_lin = + ((aic_sram[start_idx].dir_path_gain_lin - + aic_sram[end_idx].dir_path_gain_lin) * + (i - start_idx) + ((start_idx - end_idx) >> 1)) / + (start_idx - end_idx) + + aic_sram[start_idx].dir_path_gain_lin; + aic_sram[i].quad_path_gain_lin = + ((aic_sram[start_idx].quad_path_gain_lin - + aic_sram[end_idx].quad_path_gain_lin) * + (i - start_idx) + ((start_idx - end_idx) >> 1)) / + (start_idx - end_idx) + + aic_sram[start_idx].quad_path_gain_lin; + + } + else { + /* interpolation */ + aic_sram[i].dir_path_gain_lin = + (((end_idx - i) * aic_sram[start_idx].dir_path_gain_lin) + + ((i - start_idx) * aic_sram[end_idx].dir_path_gain_lin) + + ((end_idx - start_idx) >> 1)) / + (end_idx - start_idx); + aic_sram[i].quad_path_gain_lin = + (((end_idx - i) * aic_sram[start_idx].quad_path_gain_lin) + + ((i - start_idx) * aic_sram[end_idx].quad_path_gain_lin) + + ((end_idx - start_idx) >> 1))/ + (end_idx - start_idx); + } + } + + /* From dir/quad_path_gain_lin to sram. */ + i = ar9300_aic_find_valid(cal_sram, 1, 0); + if (i < 0) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(AIC) Error (3): can't find valid. Force it to 0.\n"); + i = 0; + ret = AH_FALSE; + } + fixed_com_att_db = com_att_db_table[cal_sram[i].com_att_6db]; + + for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { + int16_t rot_dir_path_att_db, rot_quad_path_att_db; + + aic_sram[i].sram.vga_dir_sign = (aic_sram[i].dir_path_gain_lin >= 0) + ? 1 : 0; + aic_sram[i].sram.vga_quad_sign= (aic_sram[i].quad_path_gain_lin >= 0) + ? 1 : 0; + + rot_dir_path_att_db = + ar9300_aic_find_index(0, abs(aic_sram[i].dir_path_gain_lin)) - + fixed_com_att_db; + rot_quad_path_att_db = + ar9300_aic_find_index(0, abs(aic_sram[i].quad_path_gain_lin)) - + fixed_com_att_db; + + aic_sram[i].sram.com_att_6db = ar9300_aic_find_index(1, + fixed_com_att_db); + + aic_sram[i].sram.valid = 1; + aic_sram[i].sram.rot_dir_att_db = + MIN(MAX(rot_dir_path_att_db, ATH_AIC_MIN_ROT_DIR_ATT_DB), + ATH_AIC_MAX_ROT_DIR_ATT_DB); + aic_sram[i].sram.rot_quad_att_db = + MIN(MAX(rot_quad_path_att_db, ATH_AIC_MIN_ROT_QUAD_ATT_DB), + ATH_AIC_MAX_ROT_QUAD_ATT_DB); + } + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Post processing results:\n"); + + for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { + ahp->ah_aic_sram[i] = (SM(aic_sram[i].sram.vga_dir_sign, + AR_PHY_AIC_SRAM_VGA_DIR_SIGN) | + SM(aic_sram[i].sram.vga_quad_sign, + AR_PHY_AIC_SRAM_VGA_QUAD_SIGN) | + SM(aic_sram[i].sram.com_att_6db, + AR_PHY_AIC_SRAM_COM_ATT_6DB) | + SM(aic_sram[i].sram.valid, + AR_PHY_AIC_SRAM_VALID) | + SM(aic_sram[i].sram.rot_dir_att_db, + AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB) | + SM(aic_sram[i].sram.rot_quad_att_db, + AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB)); + + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(AIC) ch%02d 0x%05x %2d %2d %2d %2d %2d %2d %d %d\n", + i, + ahp->ah_aic_sram[i], + aic_sram[i].sram.vga_quad_sign, + aic_sram[i].sram.vga_dir_sign, + aic_sram[i].sram.rot_dir_att_db, + aic_sram[i].sram.rot_quad_att_db, + aic_sram[i].sram.com_att_6db, + aic_sram[i].sram.valid, + aic_sram[i].dir_path_gain_lin, + aic_sram[i].quad_path_gain_lin); + } + + return ret; +} + +u_int32_t +ar9300_aic_calibration(struct ath_hal *ah) +{ + u_int32_t aic_ctrl_b0[5], aic_ctrl_b1[5]; + u_int32_t aic_stat_b0[2], aic_stat_b1[2]; + u_int32_t aic_stat, value; + u_int32_t i, cal_count = ATH_AIC_MAX_CAL_COUNT; + struct ath_hal_9300 *ahp = AH9300(ah); + + if (AR_SREV_JUPITER_10(ah)) { + aic_ctrl_b0[0] = AR_PHY_AIC_CTRL_0_B0_10; + aic_ctrl_b0[1] = AR_PHY_AIC_CTRL_1_B0_10; + aic_ctrl_b0[2] = AR_PHY_AIC_CTRL_2_B0_10; + aic_ctrl_b0[3] = AR_PHY_AIC_CTRL_3_B0_10; + aic_ctrl_b1[0] = AR_PHY_AIC_CTRL_0_B1_10; + aic_ctrl_b1[1] = AR_PHY_AIC_CTRL_1_B1_10; + aic_stat_b0[0] = AR_PHY_AIC_STAT_0_B0_10; + aic_stat_b0[1] = AR_PHY_AIC_STAT_1_B0_10; + aic_stat_b1[0] = AR_PHY_AIC_STAT_0_B1_10; + aic_stat_b1[1] = AR_PHY_AIC_STAT_1_B1_10; + } + else { + aic_ctrl_b0[0] = AR_PHY_AIC_CTRL_0_B0_20; + aic_ctrl_b0[1] = AR_PHY_AIC_CTRL_1_B0_20; + aic_ctrl_b0[2] = AR_PHY_AIC_CTRL_2_B0_20; + aic_ctrl_b0[3] = AR_PHY_AIC_CTRL_3_B0_20; + aic_ctrl_b0[4] = AR_PHY_AIC_CTRL_4_B0_20; + aic_ctrl_b1[0] = AR_PHY_AIC_CTRL_0_B1_20; + aic_ctrl_b1[1] = AR_PHY_AIC_CTRL_1_B1_20; + aic_ctrl_b1[4] = AR_PHY_AIC_CTRL_4_B1_20; + aic_stat_b0[0] = AR_PHY_AIC_STAT_0_B0_20; + aic_stat_b0[1] = AR_PHY_AIC_STAT_1_B0_20; + aic_stat_b1[0] = AR_PHY_AIC_STAT_0_B1_20; + aic_stat_b1[1] = AR_PHY_AIC_STAT_1_B1_20; + } + + /* Config LNA gain difference */ + OS_REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x22180600); + OS_REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x52443a2e); + + OS_REG_WRITE(ah, aic_ctrl_b0[0], + (SM(0, AR_PHY_AIC_MON_ENABLE) | + SM(40, AR_PHY_AIC_CAL_MAX_HOP_COUNT) | + SM(1, AR_PHY_AIC_CAL_MIN_VALID_COUNT) | //26 + SM(37, AR_PHY_AIC_F_WLAN) | + SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) | + SM(0, AR_PHY_AIC_CAL_ENABLE) | + SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) | + SM(0, AR_PHY_AIC_ENABLE))); + + OS_REG_WRITE(ah, aic_ctrl_b1[0], + (SM(0, AR_PHY_AIC_MON_ENABLE) | + SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) | + SM(0, AR_PHY_AIC_CAL_ENABLE) | + SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) | + SM(0, AR_PHY_AIC_ENABLE))); + + OS_REG_WRITE(ah, aic_ctrl_b0[1], + (SM(8, AR_PHY_AIC_CAL_BT_REF_DELAY) | + SM(6, AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO) | + SM(3, AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO) | + SM(0, AR_PHY_AIC_BT_IDLE_CFG) | + SM(1, AR_PHY_AIC_STDBY_COND) | + SM(37, AR_PHY_AIC_STDBY_ROT_ATT_DB) | + SM(5, AR_PHY_AIC_STDBY_COM_ATT_DB) | + SM(15, AR_PHY_AIC_RSSI_MAX) | + SM(0, AR_PHY_AIC_RSSI_MIN))); + + OS_REG_WRITE(ah, aic_ctrl_b1[1], + (SM(6, AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO) | + SM(3, AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO) | + SM(15, AR_PHY_AIC_RSSI_MAX) | + SM(0, AR_PHY_AIC_RSSI_MIN))); + + OS_REG_WRITE(ah, aic_ctrl_b0[2], + (SM(44, AR_PHY_AIC_RADIO_DELAY) | + SM(7, AR_PHY_AIC_CAL_STEP_SIZE_CORR) | + SM(12, AR_PHY_AIC_CAL_ROT_IDX_CORR) | + SM(2, AR_PHY_AIC_CAL_CONV_CHECK_FACTOR) | + SM(5, AR_PHY_AIC_ROT_IDX_COUNT_MAX) | + SM(1, AR_PHY_AIC_CAL_SYNTH_TOGGLE) | + SM(1, AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX) | + SM(200, AR_PHY_AIC_CAL_SYNTH_SETTLING))); + + OS_REG_WRITE(ah, aic_ctrl_b0[3], + (SM(20, AR_PHY_AIC_MON_MAX_HOP_COUNT) | + SM(10, AR_PHY_AIC_MON_MIN_STALE_COUNT) | + SM(1, AR_PHY_AIC_MON_PWR_EST_LONG) | + SM(2, AR_PHY_AIC_MON_PD_TALLY_SCALING) | + SM(18, AR_PHY_AIC_MON_PERF_THR) | + SM(1, AR_PHY_AIC_CAL_COM_ATT_DB_FIXED) | + SM(2, AR_PHY_AIC_CAL_TARGET_MAG_SETTING) | + SM(3, AR_PHY_AIC_CAL_PERF_CHECK_FACTOR) | + SM(1, AR_PHY_AIC_CAL_PWR_EST_LONG))); + + ar9300_aic_gain_table(ah); + + /* Need to enable AIC reference signal in BT modem. */ + OS_REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL, + (OS_REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) | + ATH_AIC_BT_AIC_ENABLE)); + + while (cal_count) + { + /* Start calibration */ + OS_REG_CLR_BIT(ah, aic_ctrl_b1[0], AR_PHY_AIC_CAL_ENABLE); + OS_REG_SET_BIT(ah, aic_ctrl_b1[0], AR_PHY_AIC_CAL_CH_VALID_RESET); + OS_REG_SET_BIT(ah, aic_ctrl_b1[0], AR_PHY_AIC_CAL_ENABLE); + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Start calibration #%d\n", + (ATH_AIC_MAX_CAL_COUNT - cal_count)); + + /* Wait until calibration is completed. */ + for (i = 0; i < 10000; i++) { + /* + * Use AR_PHY_AIC_CAL_ENABLE bit instead of AR_PHY_AIC_CAL_DONE. + * Sometimes CAL_DONE bit is not asserted. + */ + if ((OS_REG_READ(ah, aic_ctrl_b1[0]) & AR_PHY_AIC_CAL_ENABLE) == 0) + { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Cal is done at #%d\n", i); + break; + } + OS_DELAY(1); + } + + /* print out status registers */ + aic_stat = OS_REG_READ(ah, aic_stat_b1[0]); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(AIC) CAL_DONE = %d, CAL_ACTIVE = %d, MEAS_COUNT = %d\n", + MS(aic_stat, AR_PHY_AIC_CAL_DONE), + MS(aic_stat, AR_PHY_AIC_CAL_ACTIVE), + MS(aic_stat, AR_PHY_AIC_MEAS_COUNT)); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(AIC) ANT_ISO = %d, HOP_COUNT = %d, VALID_COUNT = %d\n", + MS(aic_stat, AR_PHY_AIC_CAL_ANT_ISO_EST), + MS(aic_stat, AR_PHY_AIC_CAL_HOP_COUNT), + MS(aic_stat, AR_PHY_AIC_CAL_VALID_COUNT)); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(AIC) BT_WEAK = %d, BT_STRONG = %d, , \n", + MS(aic_stat, AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR), + MS(aic_stat, AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR)); + + aic_stat = OS_REG_READ(ah, aic_stat_b1[1]); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(AIC) MEAS_MAG_MIN = %d, CAL_AIC_SM = %d, AIC_SM = %d\n", + MS(aic_stat, AR_PHY_AIC_MEAS_MAG_MIN), + MS(aic_stat, AR_PHY_AIC_CAL_AIC_SM), + MS(aic_stat, AR_PHY_AIC_SM)); + + if (i >= 10000) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Calibration failed.\n"); + break; + } + + /* print out calibration result */ + if (MS(aic_stat, AR_PHY_AIC_MEAS_MAG_MIN) < ATH_AIC_MEAS_MAG_THRESH) { + for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { + OS_REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1, + (ATH_AIC_SRAM_CAL_OFFSET + i*4)); + value = OS_REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1); + if (value & 0x01) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(AIC) BT chan %02d: 0x%08x\n", i, value); + } + } + break; + } + cal_count--; + } + + if (!cal_count) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Calibration failed2.\n"); + } + + /* Disable AIC reference signal in BT modem. */ + OS_REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL, + (OS_REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) & + ~ATH_AIC_BT_AIC_ENABLE)); + + ahp->ah_aic_enabled = ar9300_aic_cal_post_process(ah) ? AH_TRUE : AH_FALSE; + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) ah_aic_enable = %d\n", + ahp->ah_aic_enabled); + return 0; +} + + +u_int32_t +ar9300_aic_start_normal (struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t aic_ctrl0_b1, aic_ctrl1_b0, aic_ctrl1_b1; + int16_t i; + + /* Config LNA gain difference */ + OS_REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x22180600); + OS_REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x52443a2e); + + ar9300_aic_gain_table(ah); + + OS_REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1, ATH_AIC_SRAM_AUTO_INCREMENT); + + for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { + OS_REG_WRITE(ah, AR_PHY_AIC_SRAM_DATA_B1, ahp->ah_aic_sram[i]); + } + + if (AR_SREV_JUPITER_10(ah)) { + aic_ctrl0_b1 = AR_PHY_AIC_CTRL_0_B1_10; + aic_ctrl1_b0 = AR_PHY_AIC_CTRL_1_B0_10; + aic_ctrl1_b1 = AR_PHY_AIC_CTRL_1_B1_10; + } + else { + aic_ctrl0_b1 = AR_PHY_AIC_CTRL_0_B1_20; + aic_ctrl1_b0 = AR_PHY_AIC_CTRL_1_B0_20; + aic_ctrl1_b1 = AR_PHY_AIC_CTRL_1_B1_20; + } + + OS_REG_WRITE(ah, aic_ctrl1_b0, + (SM(0, AR_PHY_AIC_BT_IDLE_CFG) | + SM(1, AR_PHY_AIC_STDBY_COND) | + SM(37, AR_PHY_AIC_STDBY_ROT_ATT_DB) | + SM(5, AR_PHY_AIC_STDBY_COM_ATT_DB) | + SM(15, AR_PHY_AIC_RSSI_MAX) | + SM(0, AR_PHY_AIC_RSSI_MIN))); + + OS_REG_WRITE(ah, aic_ctrl1_b1, + (SM(15, AR_PHY_AIC_RSSI_MAX) | + SM(0, AR_PHY_AIC_RSSI_MIN))); + + OS_REG_WRITE(ah, aic_ctrl0_b1, + (SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) | + SM(1, AR_PHY_AIC_ENABLE))); + + ahp->ah_aic_enabled = AH_TRUE; + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Start normal operation mode.\n"); + return 0; +} +#endif + +#endif + + diff --git a/hal/ar9300/ar9300_ani.c b/hal/ar9300/ar9300_ani.c new file mode 100644 index 000000000000..e23841d54fe4 --- /dev/null +++ b/hal/ar9300/ar9300_ani.c @@ -0,0 +1,1277 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" +#include "ah_desc.h" +#include "ah_pktlog.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300phy.h" + +extern void ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits); +extern u_int32_t ar9300_get_rx_filter(struct ath_hal *ah); + +#define HAL_ANI_DEBUG 0 + +/* + * Anti noise immunity support. We track phy errors and react + * to excessive errors by adjusting the noise immunity parameters. + */ + +/****************************************************************************** + * + * New Ani Algorithm for Station side only + * + *****************************************************************************/ + +#define HAL_ANI_OFDM_TRIG_HIGH 1000 /* units are errors per second */ +#define HAL_ANI_OFDM_TRIG_LOW 400 /* units are errors per second */ +#define HAL_ANI_CCK_TRIG_HIGH 600 /* units are errors per second */ +#define HAL_ANI_CCK_TRIG_LOW 300 /* units are errors per second */ +#define HAL_ANI_USE_OFDM_WEAK_SIG true +#define HAL_ANI_ENABLE_MRC_CCK AH_TRUE /* default is enabled */ +#define HAL_ANI_DEF_SPUR_IMMUNE_LVL 3 +#define HAL_ANI_DEF_FIRSTEP_LVL 2 +#define HAL_ANI_RSSI_THR_HIGH 40 +#define HAL_ANI_RSSI_THR_LOW 7 +#define HAL_ANI_PERIOD 1000 + +#define HAL_NOISE_DETECT_PERIOD 100 +#define HAL_NOISE_RECOVER_PERIOD 5000 + +#define HAL_SIG_FIRSTEP_SETTING_MIN 0 +#define HAL_SIG_FIRSTEP_SETTING_MAX 20 +#define HAL_SIG_SPUR_IMM_SETTING_MIN 0 +#define HAL_SIG_SPUR_IMM_SETTING_MAX 22 + +#define HAL_EP_RND(x, mul) \ + ((((x) % (mul)) >= ((mul) / 2)) ? ((x) + ((mul) - 1)) / (mul) : (x) / (mul)) +#define BEACON_RSSI(ahp) \ + HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \ + HAL_RSSI_EP_MULTIPLIER) + +typedef int TABLE[]; +/* + * level: 0 1 2 3 4 5 6 7 8 + * firstep_table: lvl 0-8, default 2 + */ +static const TABLE firstep_table = { -4, -2, 0, 2, 4, 6, 8, 10, 12}; +/* cycpwr_thr1_table: lvl 0-7, default 3 */ +static const TABLE cycpwr_thr1_table = { -6, -4, -2, 0, 2, 4, 6, 8 }; +/* values here are relative to the INI */ + +typedef struct _HAL_ANI_OFDM_LEVEL_ENTRY { + int spur_immunity_level; + int fir_step_level; + int ofdm_weak_signal_on; +} HAL_ANI_OFDM_LEVEL_ENTRY; +static const HAL_ANI_OFDM_LEVEL_ENTRY ofdm_level_table[] = { +/* SI FS WS */ + { 0, 0, 1 }, /* lvl 0 */ + { 1, 1, 1 }, /* lvl 1 */ + { 2, 2, 1 }, /* lvl 2 */ + { 3, 2, 1 }, /* lvl 3 (default) */ + { 4, 3, 1 }, /* lvl 4 */ + { 5, 4, 1 }, /* lvl 5 */ + { 6, 5, 1 }, /* lvl 6 */ + { 7, 6, 1 }, /* lvl 7 */ + { 7, 7, 1 }, /* lvl 8 */ + { 7, 8, 0 } /* lvl 9 */ +}; +#define HAL_ANI_OFDM_NUM_LEVEL \ + (sizeof(ofdm_level_table) / sizeof(ofdm_level_table[0])) +#define HAL_ANI_OFDM_MAX_LEVEL (HAL_ANI_OFDM_NUM_LEVEL - 1) +#define HAL_ANI_OFDM_DEF_LEVEL 3 /* default level - matches the INI settings */ + +typedef struct _HAL_ANI_CCK_LEVEL_ENTRY { + int fir_step_level; + int mrc_cck_on; +} HAL_ANI_CCK_LEVEL_ENTRY; + +static const HAL_ANI_CCK_LEVEL_ENTRY cck_level_table[] = { +/* FS MRC-CCK */ + { 0, 1 }, /* lvl 0 */ + { 1, 1 }, /* lvl 1 */ + { 2, 1 }, /* lvl 2 (default) */ + { 3, 1 }, /* lvl 3 */ + { 4, 0 }, /* lvl 4 */ + { 5, 0 }, /* lvl 5 */ + { 6, 0 }, /* lvl 6 */ + { 7, 0 }, /* lvl 7 (only for high rssi) */ + { 8, 0 } /* lvl 8 (only for high rssi) */ +}; +#define HAL_ANI_CCK_NUM_LEVEL \ + (sizeof(cck_level_table) / sizeof(cck_level_table[0])) +#define HAL_ANI_CCK_MAX_LEVEL (HAL_ANI_CCK_NUM_LEVEL - 1) +#define HAL_ANI_CCK_MAX_LEVEL_LOW_RSSI (HAL_ANI_CCK_NUM_LEVEL - 3) +#define HAL_ANI_CCK_DEF_LEVEL 2 /* default level - matches the INI settings */ + +/* + * register values to turn OFDM weak signal detection OFF + */ +static const int m1_thresh_low_off = 127; +static const int m2_thresh_low_off = 127; +static const int m1_thresh_off = 127; +static const int m2_thresh_off = 127; +static const int m2_count_thr_off = 31; +static const int m2_count_thr_low_off = 63; +static const int m1_thresh_low_ext_off = 127; +static const int m2_thresh_low_ext_off = 127; +static const int m1_thresh_ext_off = 127; +static const int m2_thresh_ext_off = 127; + +void +ar9300_enable_mib_counters(struct ath_hal *ah) +{ + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Enable MIB counters\n", __func__); + /* Clear the mib counters and save them in the stats */ + ar9300_update_mib_mac_stats(ah); + + OS_REG_WRITE(ah, AR_FILT_OFDM, 0); + OS_REG_WRITE(ah, AR_FILT_CCK, 0); + OS_REG_WRITE(ah, AR_MIBC, + ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) & 0x0f); + OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); + OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); + +} + +void +ar9300_disable_mib_counters(struct ath_hal *ah) +{ + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Disabling MIB counters\n", __func__); + + OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); + + /* Clear the mib counters and save them in the stats */ + ar9300_update_mib_mac_stats(ah); + + OS_REG_WRITE(ah, AR_FILT_OFDM, 0); + OS_REG_WRITE(ah, AR_FILT_CCK, 0); +} + +/* + * This routine returns the index into the ani_state array that + * corresponds to the channel in *chan. If no match is found and the + * array is still not fully utilized, a new entry is created for the + * channel. We assume the attach function has already initialized the + * ah_ani values and only the channel field needs to be set. + */ +static int +ar9300_get_ani_channel_index(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int i; + + for (i = 0; i < ARRAY_LENGTH(ahp->ah_ani); i++) { + if (ahp->ah_ani[i].c.channel == chan->channel) { + return i; + } + if (ahp->ah_ani[i].c.channel == 0) { + ahp->ah_ani[i].c.channel = chan->channel; + ahp->ah_ani[i].c.channel_flags = chan->channel_flags; + return i; + } + } + /* XXX statistic */ + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: No more channel states left. Using channel 0\n", __func__); + return 0; /* XXX gotta return something valid */ +} + +/* + * Return the current ANI state of the channel we're on + */ +struct ar9300_ani_state * +ar9300_ani_get_current_state(struct ath_hal *ah) +{ + return AH9300(ah)->ah_curani; +} + +/* + * Return the current statistics. + */ +struct ar9300_stats * +ar9300_ani_get_current_stats(struct ath_hal *ah) +{ + return &AH9300(ah)->ah_stats; +} + +/* + * Setup ANI handling. Sets all thresholds and levels to default level AND + * resets the channel statistics + */ + +void +ar9300_ani_attach(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int i; + + OS_MEMZERO(ahp->ah_ani, sizeof(ahp->ah_ani)); + for (i = 0; i < ARRAY_LENGTH(ahp->ah_ani); i++) { + ahp->ah_ani[i].ofdm_trig_high = HAL_ANI_OFDM_TRIG_HIGH; + ahp->ah_ani[i].ofdm_trig_low = HAL_ANI_OFDM_TRIG_LOW; + ahp->ah_ani[i].cck_trig_high = HAL_ANI_CCK_TRIG_HIGH; + ahp->ah_ani[i].cck_trig_low = HAL_ANI_CCK_TRIG_LOW; + ahp->ah_ani[i].rssi_thr_high = HAL_ANI_RSSI_THR_HIGH; + ahp->ah_ani[i].rssi_thr_low = HAL_ANI_RSSI_THR_LOW; + ahp->ah_ani[i].ofdm_noise_immunity_level = HAL_ANI_OFDM_DEF_LEVEL; + ahp->ah_ani[i].cck_noise_immunity_level = HAL_ANI_CCK_DEF_LEVEL; + ahp->ah_ani[i].ofdm_weak_sig_detect_off = !HAL_ANI_USE_OFDM_WEAK_SIG; + ahp->ah_ani[i].spur_immunity_level = HAL_ANI_DEF_SPUR_IMMUNE_LVL; + ahp->ah_ani[i].firstep_level = HAL_ANI_DEF_FIRSTEP_LVL; + ahp->ah_ani[i].mrc_cck_off = !HAL_ANI_ENABLE_MRC_CCK; + ahp->ah_ani[i].ofdms_turn = AH_TRUE; + ahp->ah_ani[i].must_restore = AH_FALSE; + } + + /* + * Since we expect some ongoing maintenance on the tables, + * let's sanity check here. + * The default level should not modify INI setting. + */ + HALASSERT(firstep_table[HAL_ANI_DEF_FIRSTEP_LVL] == 0); + HALASSERT(cycpwr_thr1_table[HAL_ANI_DEF_SPUR_IMMUNE_LVL] == 0); + HALASSERT( + ofdm_level_table[HAL_ANI_OFDM_DEF_LEVEL].fir_step_level == + HAL_ANI_DEF_FIRSTEP_LVL); + HALASSERT( + ofdm_level_table[HAL_ANI_OFDM_DEF_LEVEL].spur_immunity_level == + HAL_ANI_DEF_SPUR_IMMUNE_LVL); + HALASSERT( + cck_level_table[HAL_ANI_CCK_DEF_LEVEL].fir_step_level == + HAL_ANI_DEF_FIRSTEP_LVL); + + /* Initialize and enable MIB Counters */ + OS_REG_WRITE(ah, AR_PHY_ERR_1, 0); + OS_REG_WRITE(ah, AR_PHY_ERR_2, 0); + ar9300_enable_mib_counters(ah); + + ahp->ah_ani_period = HAL_ANI_PERIOD; + if (AH_PRIVATE(ah)->ah_config.ath_hal_enable_ani) { + ahp->ah_proc_phy_err |= HAL_PROCESS_ANI; + } +} + +/* + * Cleanup any ANI state setup. + */ +void +ar9300_ani_detach(struct ath_hal *ah) +{ + HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Detaching Ani\n", __func__); + ar9300_disable_mib_counters(ah); + OS_REG_WRITE(ah, AR_PHY_ERR_1, 0); + OS_REG_WRITE(ah, AR_PHY_ERR_2, 0); +} + +/* + * Initialize the ANI register values with default (ini) values. + * This routine is called during a (full) hardware reset after + * all the registers are initialised from the INI. + */ +void +ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state; + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + int index; + u_int32_t val; + + HALASSERT(chan != AH_NULL); + index = ar9300_get_ani_channel_index(ah, chan); + ani_state = &ahp->ah_ani[index]; + ahp->ah_curani = ani_state; + + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: ver %d.%d opmode %u chan %d Mhz/0x%x macmode %d\n", + __func__, AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev, + AH_PRIVATE(ah)->ah_opmode, chan->channel, chan->channel_flags, macmode); + + val = OS_REG_READ(ah, AR_PHY_SFCORR); + ani_state->ini_def.m1_thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); + ani_state->ini_def.m2_thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); + ani_state->ini_def.m2_count_thr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); + + val = OS_REG_READ(ah, AR_PHY_SFCORR_LOW); + ani_state->ini_def.m1_thresh_low = + MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); + ani_state->ini_def.m2_thresh_low = + MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); + ani_state->ini_def.m2_count_thr_low = + MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); + + val = OS_REG_READ(ah, AR_PHY_SFCORR_EXT); + ani_state->ini_def.m1_thresh_ext = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); + ani_state->ini_def.m2_thresh_ext = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); + ani_state->ini_def.m1_thresh_low_ext = + MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); + ani_state->ini_def.m2_thresh_low_ext = + MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); + + ani_state->ini_def.firstep = + OS_REG_READ_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP); + ani_state->ini_def.firstep_low = + OS_REG_READ_FIELD( + ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW); + ani_state->ini_def.cycpwr_thr1 = + OS_REG_READ_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1); + ani_state->ini_def.cycpwr_thr1_ext = + OS_REG_READ_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CYCPWR_THR1); + + /* these levels just got reset to defaults by the INI */ + ani_state->spur_immunity_level = HAL_ANI_DEF_SPUR_IMMUNE_LVL; + ani_state->firstep_level = HAL_ANI_DEF_FIRSTEP_LVL; + ani_state->ofdm_weak_sig_detect_off = !HAL_ANI_USE_OFDM_WEAK_SIG; + ani_state->mrc_cck_off = !HAL_ANI_ENABLE_MRC_CCK; + + ani_state->cycle_count = 0; +} + +/* + * Set the ANI settings to match an OFDM level. + */ +static void +ar9300_ani_set_odfm_noise_immunity_level(struct ath_hal *ah, + u_int8_t ofdm_noise_immunity_level) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state = ahp->ah_curani; + + ani_state->rssi = BEACON_RSSI(ahp); + HALDEBUG(ah, HAL_DEBUG_ANI, + "**** %s: ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", __func__, + ani_state->ofdm_noise_immunity_level, ofdm_noise_immunity_level, + ani_state->rssi, ani_state->rssi_thr_low, ani_state->rssi_thr_high); + + ani_state->ofdm_noise_immunity_level = ofdm_noise_immunity_level; + + if (ani_state->spur_immunity_level != + ofdm_level_table[ofdm_noise_immunity_level].spur_immunity_level) + { + ar9300_ani_control( + ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, + ofdm_level_table[ofdm_noise_immunity_level].spur_immunity_level); + } + + if (ani_state->firstep_level != + ofdm_level_table[ofdm_noise_immunity_level].fir_step_level && + ofdm_level_table[ofdm_noise_immunity_level].fir_step_level >= + cck_level_table[ani_state->cck_noise_immunity_level].fir_step_level) + { + ar9300_ani_control( + ah, HAL_ANI_FIRSTEP_LEVEL, + ofdm_level_table[ofdm_noise_immunity_level].fir_step_level); + } + + if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA || + ani_state->rssi <= ani_state->rssi_thr_high)) + { + if (ani_state->ofdm_weak_sig_detect_off) { + /* + * force on ofdm weak sig detect. + */ + ar9300_ani_control(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, AH_TRUE); + } + } else if (ani_state->ofdm_weak_sig_detect_off == + ofdm_level_table[ofdm_noise_immunity_level].ofdm_weak_signal_on) + { + ar9300_ani_control( + ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, + ofdm_level_table[ofdm_noise_immunity_level].ofdm_weak_signal_on); + } +} + +/* + * Set the ANI settings to match a CCK level. + */ +static void +ar9300_ani_set_cck_noise_immunity_level(struct ath_hal *ah, + u_int8_t cck_noise_immunity_level) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state = ahp->ah_curani; + int level; + + ani_state->rssi = BEACON_RSSI(ahp); + HALDEBUG(ah, HAL_DEBUG_ANI, + "**** %s: ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", + __func__, ani_state->cck_noise_immunity_level, cck_noise_immunity_level, + ani_state->rssi, ani_state->rssi_thr_low, ani_state->rssi_thr_high); + + if (AH_PRIVATE(ah)->ah_opmode == HAL_M_STA && + ani_state->rssi <= ani_state->rssi_thr_low && + cck_noise_immunity_level > HAL_ANI_CCK_MAX_LEVEL_LOW_RSSI) + { + cck_noise_immunity_level = HAL_ANI_CCK_MAX_LEVEL_LOW_RSSI; + } + + ani_state->cck_noise_immunity_level = cck_noise_immunity_level; + + level = ani_state->ofdm_noise_immunity_level; + if (ani_state->firstep_level != + cck_level_table[cck_noise_immunity_level].fir_step_level && + cck_level_table[cck_noise_immunity_level].fir_step_level >= + ofdm_level_table[level].fir_step_level) + { + ar9300_ani_control( + ah, HAL_ANI_FIRSTEP_LEVEL, + cck_level_table[cck_noise_immunity_level].fir_step_level); + } + + if (ani_state->mrc_cck_off == + cck_level_table[cck_noise_immunity_level].mrc_cck_on) + { + ar9300_ani_control( + ah, HAL_ANI_MRC_CCK, + cck_level_table[cck_noise_immunity_level].mrc_cck_on); + } +} + +/* + * Control Adaptive Noise Immunity Parameters + */ +HAL_BOOL +ar9300_ani_control(struct ath_hal *ah, HAL_ANI_CMD cmd, int param) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state = ahp->ah_curani; + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + int32_t value, value2; + u_int level = param; + u_int is_on; + + if (chan == NULL && cmd != HAL_ANI_MODE) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: ignoring cmd 0x%02x - no channel\n", __func__, cmd); + return AH_FALSE; + } + + switch (cmd & ahp->ah_ani_function) { + case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: + { + int m1_thresh_low, m2_thresh_low; + int m1_thresh, m2_thresh; + int m2_count_thr, m2_count_thr_low; + int m1_thresh_low_ext, m2_thresh_low_ext; + int m1_thresh_ext, m2_thresh_ext; + /* + * is_on == 1 means ofdm weak signal detection is ON + * (default, less noise imm) + * is_on == 0 means ofdm weak signal detection is OFF + * (more noise imm) + */ + is_on = param ? 1 : 0; + + /* + * make register setting for default (weak sig detect ON) + * come from INI file + */ + m1_thresh_low = is_on ? + ani_state->ini_def.m1_thresh_low : m1_thresh_low_off; + m2_thresh_low = is_on ? + ani_state->ini_def.m2_thresh_low : m2_thresh_low_off; + m1_thresh = is_on ? + ani_state->ini_def.m1_thresh : m1_thresh_off; + m2_thresh = is_on ? + ani_state->ini_def.m2_thresh : m2_thresh_off; + m2_count_thr = is_on ? + ani_state->ini_def.m2_count_thr : m2_count_thr_off; + m2_count_thr_low = is_on ? + ani_state->ini_def.m2_count_thr_low : m2_count_thr_low_off; + m1_thresh_low_ext = is_on ? + ani_state->ini_def.m1_thresh_low_ext : m1_thresh_low_ext_off; + m2_thresh_low_ext = is_on ? + ani_state->ini_def.m2_thresh_low_ext : m2_thresh_low_ext_off; + m1_thresh_ext = is_on ? + ani_state->ini_def.m1_thresh_ext : m1_thresh_ext_off; + m2_thresh_ext = is_on ? + ani_state->ini_def.m2_thresh_ext : m2_thresh_ext_off; + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M1_THRESH, + m1_thresh); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2_THRESH, + m2_thresh); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2COUNT_THR, + m2_count_thr); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, + AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low_ext); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, + AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low_ext); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH, + m1_thresh_ext); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M2_THRESH, + m2_thresh_ext); + if (is_on) { + OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); + } else { + OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); + } + if (!is_on != ani_state->ofdm_weak_sig_detect_off) { + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: ** ch %d: ofdm weak signal: %s=>%s\n", + __func__, chan->channel, + !ani_state->ofdm_weak_sig_detect_off ? "on" : "off", + is_on ? "on" : "off"); + if (is_on) { + ahp->ah_stats.ast_ani_ofdmon++; + } else { + ahp->ah_stats.ast_ani_ofdmoff++; + } + ani_state->ofdm_weak_sig_detect_off = !is_on; + } + break; + } + case HAL_ANI_FIRSTEP_LEVEL: + if (level >= ARRAY_LENGTH(firstep_table)) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: HAL_ANI_FIRSTEP_LEVEL level out of range (%u > %u)\n", + __func__, level, (unsigned) ARRAY_LENGTH(firstep_table)); + return AH_FALSE; + } + /* + * make register setting relative to default + * from INI file & cap value + */ + value = + firstep_table[level] - + firstep_table[HAL_ANI_DEF_FIRSTEP_LVL] + + ani_state->ini_def.firstep; + if (value < HAL_SIG_FIRSTEP_SETTING_MIN) { + value = HAL_SIG_FIRSTEP_SETTING_MIN; + } + if (value > HAL_SIG_FIRSTEP_SETTING_MAX) { + value = HAL_SIG_FIRSTEP_SETTING_MAX; + } + OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, value); + /* + * we need to set first step low register too + * make register setting relative to default from INI file & cap value + */ + value2 = + firstep_table[level] - + firstep_table[HAL_ANI_DEF_FIRSTEP_LVL] + + ani_state->ini_def.firstep_low; + if (value2 < HAL_SIG_FIRSTEP_SETTING_MIN) { + value2 = HAL_SIG_FIRSTEP_SETTING_MIN; + } + if (value2 > HAL_SIG_FIRSTEP_SETTING_MAX) { + value2 = HAL_SIG_FIRSTEP_SETTING_MAX; + } + OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, + AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); + + if (level != ani_state->firstep_level) { + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: ** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", + __func__, chan->channel, ani_state->firstep_level, level, + HAL_ANI_DEF_FIRSTEP_LVL, value, ani_state->ini_def.firstep); + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: ** ch %d: level %d=>%d[def:%d] " + "firstep_low[level]=%d ini=%d\n", + __func__, chan->channel, ani_state->firstep_level, level, + HAL_ANI_DEF_FIRSTEP_LVL, value2, + ani_state->ini_def.firstep_low); + if (level > ani_state->firstep_level) { + ahp->ah_stats.ast_ani_stepup++; + } else if (level < ani_state->firstep_level) { + ahp->ah_stats.ast_ani_stepdown++; + } + ani_state->firstep_level = level; + } + break; + case HAL_ANI_SPUR_IMMUNITY_LEVEL: + if (level >= ARRAY_LENGTH(cycpwr_thr1_table)) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: HAL_ANI_SPUR_IMMUNITY_LEVEL level " + "out of range (%u > %u)\n", + __func__, level, (unsigned) ARRAY_LENGTH(cycpwr_thr1_table)); + return AH_FALSE; + } + /* + * make register setting relative to default from INI file & cap value + */ + value = + cycpwr_thr1_table[level] - + cycpwr_thr1_table[HAL_ANI_DEF_SPUR_IMMUNE_LVL] + + ani_state->ini_def.cycpwr_thr1; + if (value < HAL_SIG_SPUR_IMM_SETTING_MIN) { + value = HAL_SIG_SPUR_IMM_SETTING_MIN; + } + if (value > HAL_SIG_SPUR_IMM_SETTING_MAX) { + value = HAL_SIG_SPUR_IMM_SETTING_MAX; + } + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, value); + + /* + * set AR_PHY_EXT_CCA for extension channel + * make register setting relative to default from INI file & cap value + */ + value2 = + cycpwr_thr1_table[level] - + cycpwr_thr1_table[HAL_ANI_DEF_SPUR_IMMUNE_LVL] + + ani_state->ini_def.cycpwr_thr1_ext; + if (value2 < HAL_SIG_SPUR_IMM_SETTING_MIN) { + value2 = HAL_SIG_SPUR_IMM_SETTING_MIN; + } + if (value2 > HAL_SIG_SPUR_IMM_SETTING_MAX) { + value2 = HAL_SIG_SPUR_IMM_SETTING_MAX; + } + OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CYCPWR_THR1, value2); + + if (level != ani_state->spur_immunity_level) { + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: ** ch %d: level %d=>%d[def:%d] " + "cycpwr_thr1[level]=%d ini=%d\n", + __func__, chan->channel, ani_state->spur_immunity_level, level, + HAL_ANI_DEF_SPUR_IMMUNE_LVL, value, + ani_state->ini_def.cycpwr_thr1); + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: ** ch %d: level %d=>%d[def:%d] " + "cycpwr_thr1_ext[level]=%d ini=%d\n", + __func__, chan->channel, ani_state->spur_immunity_level, level, + HAL_ANI_DEF_SPUR_IMMUNE_LVL, value2, + ani_state->ini_def.cycpwr_thr1_ext); + if (level > ani_state->spur_immunity_level) { + ahp->ah_stats.ast_ani_spurup++; + } else if (level < ani_state->spur_immunity_level) { + ahp->ah_stats.ast_ani_spurdown++; + } + ani_state->spur_immunity_level = level; + } + break; + case HAL_ANI_MRC_CCK: + /* + * is_on == 1 means MRC CCK ON (default, less noise imm) + * is_on == 0 means MRC CCK is OFF (more noise imm) + */ + is_on = param ? 1 : 0; + if (!AR_SREV_POSEIDON(ah)) { + OS_REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, + AR_PHY_MRC_CCK_ENABLE, is_on); + OS_REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, + AR_PHY_MRC_CCK_MUX_REG, is_on); + } + if (!is_on != ani_state->mrc_cck_off) { + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: ** ch %d: MRC CCK: %s=>%s\n", __func__, chan->channel, + !ani_state->mrc_cck_off ? "on" : "off", is_on ? "on" : "off"); + if (is_on) { + ahp->ah_stats.ast_ani_ccklow++; + } else { + ahp->ah_stats.ast_ani_cckhigh++; + } + ani_state->mrc_cck_off = !is_on; + } + break; + case HAL_ANI_PRESENT: + break; +#ifdef AH_PRIVATE_DIAG + case HAL_ANI_MODE: + if (param == 0) { + ahp->ah_proc_phy_err &= ~HAL_PROCESS_ANI; + /* Turn off HW counters if we have them */ + ar9300_ani_detach(ah); + if (AH_PRIVATE(ah)->ah_curchan == NULL) { + return AH_TRUE; + } + /* if we're turning off ANI, reset regs back to INI settings */ + if (AH_PRIVATE(ah)->ah_config.ath_hal_enable_ani) { + HAL_ANI_CMD savefunc = ahp->ah_ani_function; + /* temporarly allow all functions so we can reset */ + ahp->ah_ani_function = HAL_ANI_ALL; + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: disable all ANI functions\n", __func__); + ar9300_ani_set_odfm_noise_immunity_level( + ah, HAL_ANI_OFDM_DEF_LEVEL); + ar9300_ani_set_cck_noise_immunity_level( + ah, HAL_ANI_CCK_DEF_LEVEL); + ahp->ah_ani_function = savefunc; + } + } else { /* normal/auto mode */ + HALDEBUG(ah, HAL_DEBUG_ANI, "%s: enabled\n", __func__); + ahp->ah_proc_phy_err |= HAL_PROCESS_ANI; + if (AH_PRIVATE(ah)->ah_curchan == NULL) { + return AH_TRUE; + } + ar9300_enable_mib_counters(ah); + ar9300_ani_reset(ah, AH_FALSE); + ani_state = ahp->ah_curani; + } + HALDEBUG(ah, HAL_DEBUG_ANI, "5 ANC: ahp->ah_proc_phy_err %x \n", + ahp->ah_proc_phy_err); + break; + case HAL_ANI_PHYERR_RESET: + ahp->ah_stats.ast_ani_ofdmerrs = 0; + ahp->ah_stats.ast_ani_cckerrs = 0; + break; +#endif /* AH_PRIVATE_DIAG */ + default: +#if HAL_ANI_DEBUG + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: invalid cmd 0x%02x (allowed=0x%02x)\n", + __func__, cmd, ahp->ah_ani_function); +#endif + return AH_FALSE; + } + +#if HAL_ANI_DEBUG + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: ANI parameters: SI=%d, ofdm_ws=%s FS=%d MRCcck=%s listen_time=%d " + "CC=%d listen=%d ofdm_errs=%d cck_errs=%d\n", + __func__, ani_state->spur_immunity_level, + !ani_state->ofdm_weak_sig_detect_off ? "on" : "off", + ani_state->firstep_level, !ani_state->mrc_cck_off ? "on" : "off", + ani_state->listen_time, ani_state->cycle_count, + ani_state->listen_time, ani_state->ofdm_phy_err_count, + ani_state->cck_phy_err_count); +#endif + +#ifndef REMOVE_PKT_LOG + /* do pktlog */ + { + struct log_ani log_data; + + /* Populate the ani log record */ + log_data.phy_stats_disable = DO_ANI(ah); + log_data.noise_immun_lvl = ani_state->ofdm_noise_immunity_level; + log_data.spur_immun_lvl = ani_state->spur_immunity_level; + log_data.ofdm_weak_det = ani_state->ofdm_weak_sig_detect_off; + log_data.cck_weak_thr = ani_state->cck_noise_immunity_level; + log_data.fir_lvl = ani_state->firstep_level; + log_data.listen_time = ani_state->listen_time; + log_data.cycle_count = ani_state->cycle_count; + /* express ofdm_phy_err_count as errors/second */ + log_data.ofdm_phy_err_count = ani_state->listen_time ? + ani_state->ofdm_phy_err_count * 1000 / ani_state->listen_time : 0; + /* express cck_phy_err_count as errors/second */ + log_data.cck_phy_err_count = ani_state->listen_time ? + ani_state->cck_phy_err_count * 1000 / ani_state->listen_time : 0; + log_data.rssi = ani_state->rssi; + + /* clear interrupt context flag */ + ath_hal_log_ani(AH_PRIVATE(ah)->ah_sc, &log_data, 0); + } +#endif + + return AH_TRUE; +} + +static void +ar9300_ani_restart(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state; + + if (!DO_ANI(ah)) { + return; + } + + ani_state = ahp->ah_curani; + + ani_state->listen_time = 0; + + OS_REG_WRITE(ah, AR_PHY_ERR_1, 0); + OS_REG_WRITE(ah, AR_PHY_ERR_2, 0); + OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); + OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); + + /* Clear the mib counters and save them in the stats */ + ar9300_update_mib_mac_stats(ah); + + ani_state->ofdm_phy_err_count = 0; + ani_state->cck_phy_err_count = 0; +} + +static void +ar9300_ani_ofdm_err_trigger(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state; + + if (!DO_ANI(ah)) { + return; + } + + ani_state = ahp->ah_curani; + + if (ani_state->ofdm_noise_immunity_level < HAL_ANI_OFDM_MAX_LEVEL) { + ar9300_ani_set_odfm_noise_immunity_level( + ah, ani_state->ofdm_noise_immunity_level + 1); + } +} + +static void +ar9300_ani_cck_err_trigger(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state; + + if (!DO_ANI(ah)) { + return; + } + + ani_state = ahp->ah_curani; + + if (ani_state->cck_noise_immunity_level < HAL_ANI_CCK_MAX_LEVEL) { + ar9300_ani_set_cck_noise_immunity_level( + ah, ani_state->cck_noise_immunity_level + 1); + } +} + +/* + * Restore the ANI parameters in the HAL and reset the statistics. + * This routine should be called for every hardware reset and for + * every channel change. + */ +void +ar9300_ani_reset(struct ath_hal *ah, HAL_BOOL is_scanning) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state; + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + int index; + + HALASSERT(chan != AH_NULL); + + if (!DO_ANI(ah)) { + return; + } + + /* + * we need to re-point to the correct ANI state since the channel + * may have changed due to a fast channel change + */ + index = ar9300_get_ani_channel_index(ah, chan); + ani_state = &ahp->ah_ani[index]; + HALASSERT(ani_state != AH_NULL); + ahp->ah_curani = ani_state; + + ahp->ah_stats.ast_ani_reset++; + + ani_state->phy_noise_spur = 0; + + /* only allow a subset of functions in AP mode */ + if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) { + if (IS_CHAN_2GHZ(chan)) { + ahp->ah_ani_function = (HAL_ANI_SPUR_IMMUNITY_LEVEL | + HAL_ANI_FIRSTEP_LEVEL | + HAL_ANI_MRC_CCK); + } else { + ahp->ah_ani_function = 0; + } + } + /* always allow mode (on/off) to be controlled */ + ahp->ah_ani_function |= HAL_ANI_MODE; + + if (is_scanning || + (AH_PRIVATE(ah)->ah_opmode != HAL_M_STA && + AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS)) + { + /* + * If we're scanning or in AP mode, the defaults (ini) should be + * in place. + * For an AP we assume the historical levels for this channel are + * probably outdated so start from defaults instead. + */ + if (ani_state->ofdm_noise_immunity_level != HAL_ANI_OFDM_DEF_LEVEL || + ani_state->cck_noise_immunity_level != HAL_ANI_CCK_DEF_LEVEL) + { + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: Restore defaults: opmode %u chan %d Mhz/0x%x " + "is_scanning=%d restore=%d ofdm:%d cck:%d\n", + __func__, AH_PRIVATE(ah)->ah_opmode, chan->channel, + chan->channel_flags, is_scanning, ani_state->must_restore, + ani_state->ofdm_noise_immunity_level, + ani_state->cck_noise_immunity_level); + /* + * for STA/IBSS, we want to restore the historical values later + * (when we're not scanning) + */ + if (AH_PRIVATE(ah)->ah_opmode == HAL_M_STA || + AH_PRIVATE(ah)->ah_opmode == HAL_M_IBSS) + { + ar9300_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, + HAL_ANI_DEF_SPUR_IMMUNE_LVL); + ar9300_ani_control( + ah, HAL_ANI_FIRSTEP_LEVEL, HAL_ANI_DEF_FIRSTEP_LVL); + ar9300_ani_control(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, + HAL_ANI_USE_OFDM_WEAK_SIG); + ar9300_ani_control(ah, HAL_ANI_MRC_CCK, HAL_ANI_ENABLE_MRC_CCK); + ani_state->must_restore = AH_TRUE; + } else { + ar9300_ani_set_odfm_noise_immunity_level( + ah, HAL_ANI_OFDM_DEF_LEVEL); + ar9300_ani_set_cck_noise_immunity_level( + ah, HAL_ANI_CCK_DEF_LEVEL); + } + } + } else { + /* + * restore historical levels for this channel + */ + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d " + "restore=%d ofdm:%d cck:%d\n", + __func__, AH_PRIVATE(ah)->ah_opmode, chan->channel, + chan->channel_flags, is_scanning, ani_state->must_restore, + ani_state->ofdm_noise_immunity_level, + ani_state->cck_noise_immunity_level); + ar9300_ani_set_odfm_noise_immunity_level( + ah, ani_state->ofdm_noise_immunity_level); + ar9300_ani_set_cck_noise_immunity_level( + ah, ani_state->cck_noise_immunity_level); + ani_state->must_restore = AH_FALSE; + } + + /* enable phy counters */ + ar9300_ani_restart(ah); + OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); + OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); +} + +/* + * Process a MIB interrupt. We may potentially be invoked because + * any of the MIB counters overflow/trigger so don't assume we're + * here because a PHY error counter triggered. + */ +void +ar9300_process_mib_intr(struct ath_hal *ah, const HAL_NODE_STATS *stats) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t phy_cnt1, phy_cnt2; + +#if 0 + HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Processing Mib Intr\n", __func__); +#endif + + /* Reset these counters regardless */ + OS_REG_WRITE(ah, AR_FILT_OFDM, 0); + OS_REG_WRITE(ah, AR_FILT_CCK, 0); + if (!(OS_REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING)) { + OS_REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); + } + + /* Clear the mib counters and save them in the stats */ + ar9300_update_mib_mac_stats(ah); + ahp->ah_stats.ast_nodestats = *stats; + + if (!DO_ANI(ah)) { + /* + * We must always clear the interrupt cause by resetting + * the phy error regs. + */ + OS_REG_WRITE(ah, AR_PHY_ERR_1, 0); + OS_REG_WRITE(ah, AR_PHY_ERR_2, 0); + return; + } + + /* NB: these are not reset-on-read */ + phy_cnt1 = OS_REG_READ(ah, AR_PHY_ERR_1); + phy_cnt2 = OS_REG_READ(ah, AR_PHY_ERR_2); +#if HAL_ANI_DEBUG + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: Errors: OFDM=0x%08x-0x0=%d CCK=0x%08x-0x0=%d\n", + __func__, phy_cnt1, phy_cnt1, phy_cnt2, phy_cnt2); +#endif + if (((phy_cnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || + ((phy_cnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { + /* NB: always restart to insure the h/w counters are reset */ + ar9300_ani_restart(ah); + } +} + + +static void +ar9300_ani_lower_immunity(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state = ahp->ah_curani; + + if (ani_state->ofdm_noise_immunity_level > 0 && + (ani_state->ofdms_turn || ani_state->cck_noise_immunity_level == 0)) { + /* + * lower OFDM noise immunity + */ + ar9300_ani_set_odfm_noise_immunity_level( + ah, ani_state->ofdm_noise_immunity_level - 1); + + /* + * only lower either OFDM or CCK errors per turn + * we lower the other one next time + */ + return; + } + + if (ani_state->cck_noise_immunity_level > 0) { + /* + * lower CCK noise immunity + */ + ar9300_ani_set_cck_noise_immunity_level( + ah, ani_state->cck_noise_immunity_level - 1); + } +} + +/* convert HW counter values to ms using mode specifix clock rate */ +#define CLOCK_RATE(_ah) (ath_hal_chan_2_clock_rate_mhz(_ah) * 1000) + +/* + * Return an approximation of the time spent ``listening'' by + * deducting the cycles spent tx'ing and rx'ing from the total + * cycle count since our last call. A return value <0 indicates + * an invalid/inconsistent time. + */ +static int32_t +ar9300_ani_get_listen_time(struct ath_hal *ah, HAL_ANISTATS *ani_stats) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state; + u_int32_t tx_frame_count, rx_frame_count, cycle_count; + int32_t listen_time; + + tx_frame_count = OS_REG_READ(ah, AR_TFCNT); + rx_frame_count = OS_REG_READ(ah, AR_RFCNT); + cycle_count = OS_REG_READ(ah, AR_CCCNT); + + ani_state = ahp->ah_curani; + if (ani_state->cycle_count == 0 || ani_state->cycle_count > cycle_count) { + /* + * Cycle counter wrap (or initial call); it's not possible + * to accurately calculate a value because the registers + * right shift rather than wrap--so punt and return 0. + */ + listen_time = 0; + ahp->ah_stats.ast_ani_lzero++; +#if HAL_ANI_DEBUG + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: 1st call: ani_state->cycle_count=%d\n", + __func__, ani_state->cycle_count); +#endif + } else { + int32_t ccdelta = cycle_count - ani_state->cycle_count; + int32_t rfdelta = rx_frame_count - ani_state->rx_frame_count; + int32_t tfdelta = tx_frame_count - ani_state->tx_frame_count; + listen_time = (ccdelta - rfdelta - tfdelta) / CLOCK_RATE(ah); +#if HAL_ANI_DEBUG + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: cyclecount=%d, rfcount=%d, tfcount=%d, listen_time=%d " + "CLOCK_RATE=%d\n", + __func__, ccdelta, rfdelta, tfdelta, listen_time, CLOCK_RATE(ah)); +#endif + } + ani_state->cycle_count = cycle_count; + ani_state->tx_frame_count = tx_frame_count; + ani_state->rx_frame_count = rx_frame_count; + return listen_time; +} + +/* + * Do periodic processing. This routine is called from a timer + */ +void +ar9300_ani_ar_poll(struct ath_hal *ah, const HAL_NODE_STATS *stats, + HAL_CHANNEL *chan, HAL_ANISTATS *ani_stats) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state; + int32_t listen_time; + u_int32_t ofdm_phy_err_rate, cck_phy_err_rate; + u_int32_t ofdm_phy_err_cnt, cck_phy_err_cnt; + HAL_BOOL old_phy_noise_spur; + + ani_state = ahp->ah_curani; + ahp->ah_stats.ast_nodestats = *stats; /* XXX optimize? */ + + if (ani_state == NULL) { + /* should not happen */ + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: can't poll - no ANI not initialized for this channel\n", + __func__); + return; + } + + /* + * ar9300_ani_ar_poll is never called while scanning but we may have been + * scanning and now just restarted polling. In this case we need to + * restore historical values. + */ + if (ani_state->must_restore) { + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: must restore - calling ar9300_ani_restart\n", __func__); + ar9300_ani_reset(ah, AH_FALSE); + return; + } + + listen_time = ar9300_ani_get_listen_time(ah, ani_stats); + if (listen_time <= 0) { + ahp->ah_stats.ast_ani_lneg++; + /* restart ANI period if listen_time is invalid */ + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: listen_time=%d - calling ar9300_ani_restart\n", + __func__, listen_time); + ar9300_ani_restart(ah); + return; + } + /* XXX beware of overflow? */ + ani_state->listen_time += listen_time; + + /* Clear the mib counters and save them in the stats */ + ar9300_update_mib_mac_stats(ah); + /* NB: these are not reset-on-read */ + ofdm_phy_err_cnt = OS_REG_READ(ah, AR_PHY_ERR_1); + cck_phy_err_cnt = OS_REG_READ(ah, AR_PHY_ERR_2); + + + + /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ + ahp->ah_stats.ast_ani_ofdmerrs += + ofdm_phy_err_cnt - ani_state->ofdm_phy_err_count; + ani_state->ofdm_phy_err_count = ofdm_phy_err_cnt; + + ahp->ah_stats.ast_ani_cckerrs += + cck_phy_err_cnt - ani_state->cck_phy_err_count; + ani_state->cck_phy_err_count = cck_phy_err_cnt; + +#if HAL_ANI_DEBUG + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: Errors: OFDM=0x%08x-0x0=%d CCK=0x%08x-0x0=%d\n", + __func__, ofdm_phy_err_cnt, ofdm_phy_err_cnt, + cck_phy_err_cnt, cck_phy_err_cnt); +#endif + + /* + * If ani is not enabled, return after we've collected + * statistics + */ + if (!DO_ANI(ah)) { + return; + } + + ofdm_phy_err_rate = + ani_state->ofdm_phy_err_count * 1000 / ani_state->listen_time; + cck_phy_err_rate = + ani_state->cck_phy_err_count * 1000 / ani_state->listen_time; + + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: listen_time=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n", + __func__, listen_time, + ani_state->ofdm_noise_immunity_level, ofdm_phy_err_rate, + ani_state->cck_noise_immunity_level, cck_phy_err_rate, + ani_state->ofdms_turn); + + if (ani_state->listen_time >= HAL_NOISE_DETECT_PERIOD) { + old_phy_noise_spur = ani_state->phy_noise_spur; + if (ofdm_phy_err_rate <= ani_state->ofdm_trig_low && + cck_phy_err_rate <= ani_state->cck_trig_low) { + if (ani_state->listen_time >= HAL_NOISE_RECOVER_PERIOD) { + ani_state->phy_noise_spur = 0; + } + } else { + ani_state->phy_noise_spur = 1; + } + if (old_phy_noise_spur != ani_state->phy_noise_spur) { + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: enviroment change from %d to %d\n", + __func__, old_phy_noise_spur, ani_state->phy_noise_spur); + } + } + + if (ani_state->listen_time > 5 * ahp->ah_ani_period) { + /* + * Check to see if need to lower immunity if + * 5 ani_periods have passed + */ + if (ofdm_phy_err_rate <= ani_state->ofdm_trig_low && + cck_phy_err_rate <= ani_state->cck_trig_low) + { + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: 1. listen_time=%d OFDM:%d errs=%d/s(<%d) " + "CCK:%d errs=%d/s(<%d) -> ar9300_ani_lower_immunity\n", + __func__, ani_state->listen_time, + ani_state->ofdm_noise_immunity_level, ofdm_phy_err_rate, + ani_state->ofdm_trig_low, ani_state->cck_noise_immunity_level, + cck_phy_err_rate, ani_state->cck_trig_low); + ar9300_ani_lower_immunity(ah); + ani_state->ofdms_turn = !ani_state->ofdms_turn; + } + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: 1 listen_time=%d ofdm=%d/s cck=%d/s - " + "calling ar9300_ani_restart\n", + __func__, ani_state->listen_time, + ofdm_phy_err_rate, cck_phy_err_rate); + ar9300_ani_restart(ah); + } else if (ani_state->listen_time > ahp->ah_ani_period) { + /* check to see if need to raise immunity */ + if (ofdm_phy_err_rate > ani_state->ofdm_trig_high && + (cck_phy_err_rate <= ani_state->cck_trig_high || + ani_state->ofdms_turn)) + { + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: 2 listen_time=%d OFDM:%d errs=%d/s(>%d) -> " + "ar9300_ani_ofdm_err_trigger\n", + __func__, ani_state->listen_time, + ani_state->ofdm_noise_immunity_level, ofdm_phy_err_rate, + ani_state->ofdm_trig_high); + ar9300_ani_ofdm_err_trigger(ah); + ar9300_ani_restart(ah); + ani_state->ofdms_turn = AH_FALSE; + } else if (cck_phy_err_rate > ani_state->cck_trig_high) { + HALDEBUG(ah, HAL_DEBUG_ANI, + "%s: 3 listen_time=%d CCK:%d errs=%d/s(>%d) -> " + "ar9300_ani_cck_err_trigger\n", + __func__, ani_state->listen_time, + ani_state->cck_noise_immunity_level, cck_phy_err_rate, + ani_state->cck_trig_high); + ar9300_ani_cck_err_trigger(ah); + ar9300_ani_restart(ah); + ani_state->ofdms_turn = AH_TRUE; + } + } +} + +/* + * The poll function above calculates short noise spurs, caused by non-80211 + * devices, based on OFDM/CCK Phy errs. + * If the noise is short enough, we don't want our ratectrl Algo to stop probing + * higher rates, due to bad PER. + */ +HAL_BOOL +ar9300_is_ani_noise_spur(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_ani_state *ani_state; + + ani_state = ahp->ah_curani; + + return ani_state->phy_noise_spur; +} + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_aphrodite10.ini b/hal/ar9300/ar9300_aphrodite10.ini new file mode 100644 index 000000000000..da2dc7d3f71d --- /dev/null +++ b/hal/ar9300/ar9300_aphrodite10.ini @@ -0,0 +1,1536 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +static const u_int32_t ar956X_aphrodite_1p0_tx_gain_table_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000000d5 , 0x000000d5 , 0x000000d5 , 0x000000d5 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x00004002 , 0x00004002 , 0x00004002 , 0x00004002 }, + { 0x0000a508 , 0x00008004 , 0x00008004 , 0x00008004 , 0x00008004 }, + { 0x0000a510 , 0x0001000c , 0x0001000c , 0x0001000c , 0x0001000c }, + { 0x0000a514 , 0x0001420b , 0x0001420b , 0x0001420b , 0x0001420b }, + { 0x0000a518 , 0x0001824a , 0x0001824a , 0x0001824a , 0x0001824a }, + { 0x0000a51c , 0x0001c44a , 0x0001c44a , 0x0001c44a , 0x0001c44a }, + { 0x0000a520 , 0x0002064a , 0x0002064a , 0x0002064a , 0x0002064a }, + { 0x0000a524 , 0x0002484a , 0x0002484a , 0x0002484a , 0x0002484a }, + { 0x0000a528 , 0x00028a4a , 0x00028a4a , 0x00028a4a , 0x00028a4a }, + { 0x0000a52c , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a }, + { 0x0000a530 , 0x00030e4a , 0x00030e4a , 0x00030e4a , 0x00030e4a }, + { 0x0000a534 , 0x00034e8a , 0x00034e8a , 0x00034e8a , 0x00034e8a }, +}; + +static const u_int32_t ar956X_aphrodite_1p0_baseband_core[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009804 , 0xfd14e000 }, + { 0x00009808 , 0x9c0a8f6b }, + { 0x0000980c , 0x04800000 }, + { 0x00009814 , 0x9280c00a }, + { 0x00009818 , 0x00000000 }, + { 0x0000981c , 0x00020028 }, + { 0x00009834 , 0x5f3ca3de }, + { 0x00009838 , 0x0108ecff }, + { 0x0000983c , 0x14750600 }, + { 0x00009880 , 0x201fff00 }, + { 0x00009884 , 0x00001042 }, + { 0x000098a4 , 0x00200400 }, + { 0x000098b0 , 0x52440bbe }, + { 0x000098d0 , 0x004b6a8e }, + { 0x000098d4 , 0x00000820 }, + { 0x000098dc , 0x00000000 }, + { 0x000098f0 , 0x00000000 }, + { 0x000098f4 , 0x00000000 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009c0c , 0x00000000 }, + { 0x00009c10 , 0x00000000 }, + { 0x00009c14 , 0x00046384 }, + { 0x00009c18 , 0x05b6b440 }, + { 0x00009c1c , 0x00b6b440 }, + { 0x00009d00 , 0xc080a333 }, + { 0x00009d04 , 0x40206c10 }, + { 0x00009d08 , 0x009c4060 }, + { 0x00009d0c , 0x1883800a }, + { 0x00009d10 , 0x01834061 }, + { 0x00009d14 , 0x00c00400 }, + { 0x00009d18 , 0x00000000 }, + { 0x00009e08 , 0x0038233c }, + { 0x00009e24 , 0x990bb515 }, + { 0x00009e28 , 0x126f0000 }, + { 0x00009e30 , 0x06336f77 }, + { 0x00009e34 , 0x6af6532f }, + { 0x00009e38 , 0x0cc80c00 }, + { 0x00009e3c , 0xcf946222 }, + { 0x00009e40 , 0x0d261820 }, + { 0x00009e4c , 0x00001004 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009fc0 , 0x80be4788 }, + { 0x00009fc4 , 0x0001efb5 }, + { 0x00009fcc , 0x40000014 }, + { 0x0000a20c , 0x00000000 }, + { 0x0000a220 , 0x00000000 }, + { 0x0000a224 , 0x00000000 }, + { 0x0000a228 , 0x10002310 }, + { 0x0000a22c , 0x0103702f }, + { 0x0000a234 , 0x10000fff }, + { 0x0000a23c , 0x00000000 }, + { 0x0000a244 , 0x0c000000 }, + { 0x0000a2a0 , 0x00000001 }, + { 0x0000a2c0 , 0x00000001 }, + { 0x0000a2c8 , 0x00000000 }, + { 0x0000a2cc , 0x18c43433 }, + { 0x0000a2d4 , 0x00000000 }, + { 0x0000a2dc , 0x00000000 }, + { 0x0000a2e0 , 0x00000000 }, + { 0x0000a2e4 , 0x00000000 }, + { 0x0000a2e8 , 0x00000000 }, + { 0x0000a2ec , 0x00000000 }, + { 0x0000a2f0 , 0x00000000 }, + { 0x0000a2f4 , 0x00000000 }, + { 0x0000a2f8 , 0x00000000 }, + { 0x0000a344 , 0x00000000 }, + { 0x0000a34c , 0x00000000 }, + { 0x0000a350 , 0x0000a000 }, + { 0x0000a364 , 0x00000000 }, + { 0x0000a370 , 0x00000000 }, + { 0x0000a390 , 0x00000001 }, + { 0x0000a394 , 0x00000444 }, + { 0x0000a398 , 0x001f0e0f }, + { 0x0000a39c , 0x0075393f }, + { 0x0000a3a0 , 0xb79f6427 }, + { 0x0000a3a4 , 0x00000000 }, + { 0x0000a3a8 , 0xaaaaaaaa }, + { 0x0000a3ac , 0x3c466478 }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a3c8 , 0x20200020 }, + { 0x0000a3cc , 0x20202020 }, + { 0x0000a3d0 , 0x20202020 }, + { 0x0000a3d4 , 0x20202020 }, + { 0x0000a3d8 , 0x20202020 }, + { 0x0000a3dc , 0x20202020 }, + { 0x0000a3e0 , 0x20202020 }, + { 0x0000a3e4 , 0x20202020 }, + { 0x0000a3e8 , 0x20202020 }, + { 0x0000a3ec , 0x20202020 }, + { 0x0000a3f0 , 0x00000000 }, + { 0x0000a3f4 , 0x00000006 }, + { 0x0000a3f8 , 0x0cdbd380 }, + { 0x0000a3fc , 0x000f0f01 }, + { 0x0000a400 , 0x8fa91f01 }, + { 0x0000a404 , 0x00000000 }, + { 0x0000a408 , 0x0e79e5c6 }, + { 0x0000a40c , 0x00820820 }, + { 0x0000a414 , 0x1ce739ce }, + { 0x0000a418 , 0x2d001dce }, + { 0x0000a41c , 0x1ce739ce }, + { 0x0000a420 , 0x000001ce }, + { 0x0000a424 , 0x1ce739ce }, + { 0x0000a428 , 0x000001ce }, + { 0x0000a42c , 0x1ce739ce }, + { 0x0000a430 , 0x1ce739ce }, + { 0x0000a434 , 0x00000000 }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a43c , 0x00000000 }, + { 0x0000a440 , 0x00000000 }, + { 0x0000a444 , 0x00000000 }, + { 0x0000a448 , 0x07000000 }, + { 0x0000a44c , 0x00000001 }, + { 0x0000a450 , 0x00010000 }, + { 0x0000a458 , 0x00000000 }, + { 0x0000a600 , 0x00000000 }, + { 0x0000a604 , 0x00000000 }, + { 0x0000a608 , 0x00000000 }, + { 0x0000a60c , 0x00000000 }, + { 0x0000a610 , 0x00000000 }, + { 0x0000a614 , 0x00000000 }, + { 0x0000a618 , 0x00000000 }, + { 0x0000a61c , 0x00000000 }, + { 0x0000a620 , 0x00000000 }, + { 0x0000a624 , 0x00000000 }, + { 0x0000a628 , 0x00000000 }, + { 0x0000a62c , 0x00000000 }, + { 0x0000a630 , 0x00000000 }, + { 0x0000a634 , 0x00000000 }, + { 0x0000a638 , 0x00000000 }, + { 0x0000a63c , 0x00000000 }, + { 0x0000a644 , 0x3ffd9d74 }, + { 0x0000a648 , 0x0048060a }, + { 0x0000a64c , 0x00000637 }, + { 0x0000a670 , 0x03020100 }, + { 0x0000a674 , 0x09080504 }, + { 0x0000a678 , 0x0d0c0b0a }, + { 0x0000a67c , 0x13121110 }, + { 0x0000a680 , 0x31301514 }, + { 0x0000a684 , 0x35343332 }, + { 0x0000a688 , 0x00000036 }, + { 0x0000a690 , 0x00000838 }, + { 0x0000a7c0 , 0x00000000 }, + { 0x0000a7c4 , 0xfffffffc }, + { 0x0000a7c8 , 0x00000000 }, + { 0x0000a7cc , 0x00000000 }, + { 0x0000a7d0 , 0x00000000 }, + { 0x0000a7d4 , 0x00000004 }, + { 0x0000a7dc , 0x00000001 }, +}; + +static const u_int32_t ar956XModes_fast_clock_aphrodite_1p0[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00001030 , 0x00000268 , 0x000004d0 }, + { 0x00001070 , 0x0000018c , 0x00000318 }, + { 0x000010b0 , 0x00000fd0 , 0x00001fa0 }, + { 0x00008014 , 0x044c044c , 0x08980898 }, + { 0x0000801c , 0x148ec02b , 0x148ec057 }, + { 0x00008318 , 0x000044c0 , 0x00008980 }, + { 0x00009e00 , 0x03721821 , 0x03721821 }, + { 0x0000a230 , 0x0000000b , 0x00000016 }, + { 0x0000a254 , 0x00000898 , 0x00001130 }, +}; + +static const u_int32_t ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x03820190 }, + { 0x0000a030 , 0x03840383 }, + { 0x0000a034 , 0x03880385 }, + { 0x0000a038 , 0x038a0389 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x29292929 }, + { 0x0000a084 , 0x29292929 }, + { 0x0000a088 , 0x29292929 }, + { 0x0000a08c , 0x29292929 }, + { 0x0000a090 , 0x22292929 }, + { 0x0000a094 , 0x1d1d2222 }, + { 0x0000a098 , 0x0c111117 }, + { 0x0000a09c , 0x00030303 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x32323232 }, + { 0x0000b084 , 0x2f2f3232 }, + { 0x0000b088 , 0x23282a2d }, + { 0x0000b08c , 0x1c1e2123 }, + { 0x0000b090 , 0x14171919 }, + { 0x0000b094 , 0x0e0e1214 }, + { 0x0000b098 , 0x03050707 }, + { 0x0000b09c , 0x00030303 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar956X_aphrodite_1p0_mac_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00000030 , 0x000a0085 }, + { 0x00000044 , 0x00000008 }, + { 0x0000805c , 0xffffc7ff }, + { 0x00008344 , 0xaa4a105b }, +}; + +static const u_int32_t ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x21020220 , 0x21020220 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x27020223 , 0x27020223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5c04286b , 0x5c04286b , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x61042a6c , 0x61042a6c , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x66062a6c , 0x66062a6c , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x6b062e6c , 0x6b062e6c , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x7006308c , 0x7006308c , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x730a308a , 0x730a308a , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, +}; + +static const u_int32_t ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x21020220 , 0x21020220 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x27020223 , 0x27020223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5c04286b , 0x5c04286b , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x61042a6c , 0x61042a6c , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x66062a6c , 0x66062a6c , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x6b062e6c , 0x6b062e6c , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x7006308c , 0x7006308c , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x730a308a , 0x730a308a , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, +}; + +static const u_int32_t ar956X_aphrodite_1p0_mac_core[][2] = { +/* Addr allmodes */ + { 0x00000008 , 0x00000000 }, + { 0x00000030 , 0x000a0085 }, + { 0x00000034 , 0x00000005 }, + { 0x00000040 , 0x00000000 }, + { 0x00000044 , 0x00000000 }, + { 0x00000048 , 0x00000008 }, + { 0x0000004c , 0x00000010 }, + { 0x00000050 , 0x00000000 }, + { 0x00001040 , 0x002ffc0f }, + { 0x00001044 , 0x002ffc0f }, + { 0x00001048 , 0x002ffc0f }, + { 0x0000104c , 0x002ffc0f }, + { 0x00001050 , 0x002ffc0f }, + { 0x00001054 , 0x002ffc0f }, + { 0x00001058 , 0x002ffc0f }, + { 0x0000105c , 0x002ffc0f }, + { 0x00001060 , 0x002ffc0f }, + { 0x00001064 , 0x002ffc0f }, + { 0x000010f0 , 0x00000100 }, + { 0x00001270 , 0x00000000 }, + { 0x000012b0 , 0x00000000 }, + { 0x000012f0 , 0x00000000 }, + { 0x0000143c , 0x00000000 }, + { 0x0000147c , 0x00000000 }, + { 0x00008000 , 0x00000000 }, + { 0x00008004 , 0x00000000 }, + { 0x00008008 , 0x00000000 }, + { 0x0000800c , 0x00000000 }, + { 0x00008018 , 0x00000000 }, + { 0x00008020 , 0x00000000 }, + { 0x00008038 , 0x00000000 }, + { 0x0000803c , 0x00000000 }, + { 0x00008040 , 0x00000000 }, + { 0x00008044 , 0x00000000 }, + { 0x00008048 , 0x00000000 }, + { 0x0000804c , 0xffffffff }, + { 0x00008050 , 0xffffffff }, + { 0x00008054 , 0x00000000 }, + { 0x00008058 , 0x00000000 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008060 , 0x0000000f }, + { 0x00008064 , 0x00000000 }, + { 0x00008070 , 0x00000310 }, + { 0x00008074 , 0x00000020 }, + { 0x00008078 , 0x00000000 }, + { 0x0000809c , 0x0000000f }, + { 0x000080a0 , 0x00000000 }, + { 0x000080a4 , 0x02ff0000 }, + { 0x000080a8 , 0x0e070605 }, + { 0x000080ac , 0x0000000d }, + { 0x000080b0 , 0x00000000 }, + { 0x000080b4 , 0x00000000 }, + { 0x000080b8 , 0x00000000 }, + { 0x000080bc , 0x00000000 }, + { 0x000080c0 , 0x2a800000 }, + { 0x000080c4 , 0x06900168 }, + { 0x000080c8 , 0x13881c20 }, + { 0x000080cc , 0x01f40000 }, + { 0x000080d0 , 0x00252500 }, + { 0x000080d4 , 0x00b00005 }, + { 0x000080d8 , 0x00400002 }, + { 0x000080dc , 0x00000000 }, + { 0x000080e0 , 0xffffffff }, + { 0x000080e4 , 0x0000ffff }, + { 0x000080e8 , 0x3f3f3f3f }, + { 0x000080ec , 0x00000000 }, + { 0x000080f0 , 0x00000000 }, + { 0x000080f4 , 0x00000000 }, + { 0x000080fc , 0x00020000 }, + { 0x00008100 , 0x00000000 }, + { 0x00008108 , 0x00000052 }, + { 0x0000810c , 0x00000000 }, + { 0x00008110 , 0x00000000 }, + { 0x00008114 , 0x000007ff }, + { 0x00008118 , 0x000000aa }, + { 0x0000811c , 0x00003210 }, + { 0x00008124 , 0x00000000 }, + { 0x00008128 , 0x00000000 }, + { 0x0000812c , 0x00000000 }, + { 0x00008130 , 0x00000000 }, + { 0x00008134 , 0x00000000 }, + { 0x00008138 , 0x00000000 }, + { 0x0000813c , 0x0000ffff }, + { 0x00008144 , 0xffffffff }, + { 0x00008168 , 0x00000000 }, + { 0x0000816c , 0x00000000 }, +#ifdef AR956X_EMULATION + //This is workaround in emulation.Because it cause tx dma stop. We must find out soluction. + { 0x00008170 , 0x18486E00 }, +#else + { 0x00008170 , 0x18486200 }, +#endif + { 0x00008174 , 0x33332210 }, + { 0x00008178 , 0x00000000 }, + { 0x0000817c , 0x00020000 }, + { 0x000081c4 , 0x33332210 }, + { 0x000081c8 , 0x00000000 }, + { 0x000081cc , 0x00000000 }, + { 0x000081d4 , 0x00000000 }, + { 0x000081ec , 0x00000000 }, + { 0x000081f0 , 0x00000000 }, + { 0x000081f4 , 0x00000000 }, + { 0x000081f8 , 0x00000000 }, + { 0x000081fc , 0x00000000 }, + { 0x00008240 , 0x00100000 }, + { 0x00008244 , 0x0010f424 }, + { 0x00008248 , 0x00000800 }, + { 0x0000824c , 0x0001e848 }, + { 0x00008250 , 0x00000000 }, + { 0x00008254 , 0x00000000 }, + { 0x00008258 , 0x00000000 }, + { 0x0000825c , 0x40000000 }, + { 0x00008260 , 0x00080922 }, + { 0x00008264 , 0x98a00010 }, + { 0x00008268 , 0xffffffff }, + { 0x0000826c , 0x0000ffff }, + { 0x00008270 , 0x00000000 }, + { 0x00008274 , 0x40000000 }, + { 0x00008278 , 0x003e4180 }, + { 0x0000827c , 0x00000004 }, + { 0x00008284 , 0x0000002c }, + { 0x00008288 , 0x0000002c }, + { 0x0000828c , 0x000000ff }, + { 0x00008294 , 0x00000000 }, + { 0x00008298 , 0x00000000 }, + { 0x0000829c , 0x00000000 }, + { 0x00008300 , 0x00000140 }, + { 0x00008314 , 0x00000000 }, + { 0x0000831c , 0x0000010d }, + { 0x00008328 , 0x00000000 }, + { 0x0000832c , 0x0000001f }, + { 0x00008330 , 0x00000302 }, + { 0x00008334 , 0x00000700 }, + { 0x00008338 , 0xffff0000 }, + { 0x0000833c , 0x02400000 }, + { 0x00008340 , 0x000107ff }, + { 0x00008344 , 0xaa48105b }, + { 0x00008348 , 0x008f0000 }, + { 0x0000835c , 0x00000000 }, + { 0x00008360 , 0xffffffff }, + { 0x00008364 , 0xffffffff }, + { 0x00008368 , 0x00000000 }, + { 0x00008370 , 0x00000000 }, + { 0x00008374 , 0x000000ff }, + { 0x00008378 , 0x00000000 }, + { 0x0000837c , 0x00000000 }, + { 0x00008380 , 0xffffffff }, + { 0x00008384 , 0xffffffff }, + { 0x00008390 , 0xffffffff }, + { 0x00008394 , 0xffffffff }, + { 0x00008398 , 0x00000000 }, + { 0x0000839c , 0x00000000 }, + { 0x000083a4 , 0x0000fa14 }, + { 0x000083a8 , 0x000f0c00 }, + { 0x000083ac , 0x33332210 }, + { 0x000083b0 , 0x33332210 }, + { 0x000083b4 , 0x33332210 }, + { 0x000083b8 , 0x33332210 }, + { 0x000083bc , 0x00000000 }, + { 0x000083c0 , 0x00000000 }, + { 0x000083c4 , 0x00000000 }, + { 0x000083c8 , 0x00000000 }, + { 0x000083cc , 0x00000200 }, + { 0x000083d0 , 0x800301ff }, +}; + +static const u_int32_t ar956X_aphrodite_1p0_mac_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 }, + { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 }, +}; + +static const u_int32_t ar956XModes_high_power_tx_gain_table_aphrodite_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06002223 , 0x06002223 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a022220 , 0x0a022220 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x0f022223 , 0x0f022223 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x14022620 , 0x14022620 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x18022622 , 0x18022622 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x1b022822 , 0x1b022822 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x20022842 , 0x20022842 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x22022c41 , 0x22022c41 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x28023042 , 0x28023042 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x2c023044 , 0x2c023044 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x2f023644 , 0x2f023644 , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x34025643 , 0x34025643 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x38025a44 , 0x38025a44 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x3b025e45 , 0x3b025e45 , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x41025e4a , 0x41025e4a , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x48025e6c , 0x48025e6c , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x4e025e8e , 0x4e025e8e , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x53025eb2 , 0x53025eb2 , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x59025eb5 , 0x59025eb5 , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x5f025ef6 , 0x5f025ef6 , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x62025f56 , 0x62025f56 , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x66027f56 , 0x66027f56 , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x6a029f56 , 0x6a029f56 , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x70049f56 , 0x70049f56 , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, +}; + +static const u_int32_t ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06002223 , 0x06002223 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a022220 , 0x0a022220 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x0f022223 , 0x0f022223 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x14022620 , 0x14022620 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x18022622 , 0x18022622 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x1b022822 , 0x1b022822 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x20022842 , 0x20022842 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x22022c41 , 0x22022c41 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x28023042 , 0x28023042 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x2c023044 , 0x2c023044 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x2f023644 , 0x2f023644 , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x34025643 , 0x34025643 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x38025a44 , 0x38025a44 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x3b025e45 , 0x3b025e45 , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x41025e4a , 0x41025e4a , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x48025e6c , 0x48025e6c , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x4e025e8e , 0x4e025e8e , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x53025eb2 , 0x53025eb2 , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x59025eb5 , 0x59025eb5 , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x5f025ef6 , 0x5f025ef6 , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x62025f56 , 0x62025f56 , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x66027f56 , 0x66027f56 , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x6a029f56 , 0x6a029f56 , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x70049f56 , 0x70049f56 , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, +}; + +static const u_int32_t ar9200_merlin_2p0_aphrodite_radio_core[][2] = { +/* Addr common */ + { 0x00007800 , 0x00040000 }, + { 0x00007804 , 0xdb005012 }, + { 0x00007808 , 0x04924914 }, + { 0x0000780c , 0x21084210 }, + { 0x00007810 , 0x6d801300 }, + { 0x00007814 , 0x0019beff }, + { 0x00007818 , 0x07e41000 }, + { 0x0000781c , 0x00392000 }, + { 0x00007820 , 0x92592480 }, + { 0x00007824 , 0x00040000 }, + { 0x00007828 , 0xdb005012 }, + { 0x0000782c , 0x04924914 }, + { 0x00007830 , 0x21084210 }, + { 0x00007834 , 0x6d801300 }, + { 0x00007838 , 0x0019beff }, + { 0x0000783c , 0x07e40000 }, + { 0x00007840 , 0x00392000 }, + { 0x00007844 , 0x92592480 }, + { 0x00007848 , 0x00100000 }, + { 0x0000784c , 0x773f0567 }, + { 0x00007850 , 0x54214514 }, + { 0x00007854 , 0x12035828 }, + { 0x00007858 , 0x92592692 }, + { 0x0000785c , 0x00000000 }, + { 0x00007860 , 0x56400000 }, + { 0x00007864 , 0x0a8e370e }, + { 0x00007868 , 0xc0102850 }, + { 0x0000786c , 0x812d4000 }, + { 0x00007870 , 0x807ec400 }, + { 0x00007874 , 0x001b6db0 }, + { 0x00007878 , 0x00376b63 }, + { 0x0000787c , 0x06db6db6 }, + { 0x00007880 , 0x006d8000 }, + { 0x00007884 , 0xffeffffe }, + { 0x00007888 , 0xffeffffe }, + { 0x0000788c , 0x00010000 }, + { 0x00007890 , 0x02060aeb }, + { 0x00007894 , 0x5a108000 }, +}; + +static const u_int32_t ar956XCommon_rx_gain_table_merlin_2p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x02000101 }, + { 0x0000a004 , 0x02000102 }, + { 0x0000a008 , 0x02000103 }, + { 0x0000a00c , 0x02000104 }, + { 0x0000a010 , 0x02000200 }, + { 0x0000a014 , 0x02000201 }, + { 0x0000a018 , 0x02000202 }, + { 0x0000a01c , 0x02000203 }, + { 0x0000a020 , 0x02000204 }, + { 0x0000a024 , 0x02000205 }, + { 0x0000a028 , 0x02000208 }, + { 0x0000a02c , 0x02000302 }, + { 0x0000a030 , 0x02000303 }, + { 0x0000a034 , 0x02000304 }, + { 0x0000a038 , 0x02000400 }, + { 0x0000a03c , 0x02010300 }, + { 0x0000a040 , 0x02010301 }, + { 0x0000a044 , 0x02010302 }, + { 0x0000a048 , 0x02000500 }, + { 0x0000a04c , 0x02010400 }, + { 0x0000a050 , 0x02020300 }, + { 0x0000a054 , 0x02020301 }, + { 0x0000a058 , 0x02020302 }, + { 0x0000a05c , 0x02020303 }, + { 0x0000a060 , 0x02020400 }, + { 0x0000a064 , 0x02030300 }, + { 0x0000a068 , 0x02030301 }, + { 0x0000a06c , 0x02030302 }, + { 0x0000a070 , 0x02030303 }, + { 0x0000a074 , 0x02030400 }, + { 0x0000a078 , 0x02040300 }, + { 0x0000a07c , 0x02040301 }, + { 0x0000a080 , 0x02040302 }, + { 0x0000a084 , 0x02040303 }, + { 0x0000a088 , 0x02030500 }, + { 0x0000a08c , 0x02040400 }, + { 0x0000a090 , 0x02050203 }, + { 0x0000a094 , 0x02050204 }, + { 0x0000a098 , 0x02050205 }, + { 0x0000a09c , 0x02040500 }, + { 0x0000a0a0 , 0x02050301 }, + { 0x0000a0a4 , 0x02050302 }, + { 0x0000a0a8 , 0x02050303 }, + { 0x0000a0ac , 0x02050400 }, + { 0x0000a0b0 , 0x02050401 }, + { 0x0000a0b4 , 0x02050402 }, + { 0x0000a0b8 , 0x02050403 }, + { 0x0000a0bc , 0x02050500 }, + { 0x0000a0c0 , 0x02050501 }, + { 0x0000a0c4 , 0x02050502 }, + { 0x0000a0c8 , 0x02050503 }, + { 0x0000a0cc , 0x02050504 }, + { 0x0000a0d0 , 0x02050600 }, + { 0x0000a0d4 , 0x02050601 }, + { 0x0000a0d8 , 0x02050602 }, + { 0x0000a0dc , 0x02050603 }, + { 0x0000a0e0 , 0x02050604 }, + { 0x0000a0e4 , 0x02050700 }, + { 0x0000a0e8 , 0x02050701 }, + { 0x0000a0ec , 0x02050702 }, + { 0x0000a0f0 , 0x02050703 }, + { 0x0000a0f4 , 0x02050704 }, + { 0x0000a0f8 , 0x02050705 }, + { 0x0000a0fc , 0x02050708 }, + { 0x0000a100 , 0x02050709 }, + { 0x0000a104 , 0x0205070a }, + { 0x0000a108 , 0x0205070b }, + { 0x0000a10c , 0x0205070c }, + { 0x0000a110 , 0x0205070d }, + { 0x0000a114 , 0x02050710 }, + { 0x0000a118 , 0x02050711 }, + { 0x0000a11c , 0x02050712 }, + { 0x0000a120 , 0x02050713 }, + { 0x0000a124 , 0x02050714 }, + { 0x0000a128 , 0x02050715 }, + { 0x0000a12c , 0x02050730 }, + { 0x0000a130 , 0x02050731 }, + { 0x0000a134 , 0x02050732 }, + { 0x0000a138 , 0x02050733 }, + { 0x0000a13c , 0x02050734 }, + { 0x0000a140 , 0x02050735 }, + { 0x0000a144 , 0x02050750 }, + { 0x0000a148 , 0x02050751 }, + { 0x0000a14c , 0x02050752 }, + { 0x0000a150 , 0x02050753 }, + { 0x0000a154 , 0x02050754 }, + { 0x0000a158 , 0x02050755 }, + { 0x0000a15c , 0x02050770 }, + { 0x0000a160 , 0x02050771 }, + { 0x0000a164 , 0x02050772 }, + { 0x0000a168 , 0x02050773 }, + { 0x0000a16c , 0x02050774 }, + { 0x0000a170 , 0x02050775 }, + { 0x0000a174 , 0x00000776 }, + { 0x0000a178 , 0x00000776 }, + { 0x0000a17c , 0x00000776 }, + { 0x0000a180 , 0x00000776 }, + { 0x0000a184 , 0x00000776 }, + { 0x0000a188 , 0x00000776 }, + { 0x0000a18c , 0x00000776 }, + { 0x0000a190 , 0x00000776 }, + { 0x0000a194 , 0x00000776 }, + { 0x0000a198 , 0x00000776 }, + { 0x0000a19c , 0x00000776 }, + { 0x0000a1a0 , 0x00000776 }, + { 0x0000a1a4 , 0x00000776 }, + { 0x0000a1a8 , 0x00000776 }, + { 0x0000a1ac , 0x00000776 }, + { 0x0000a1b0 , 0x00000776 }, + { 0x0000a1b4 , 0x00000776 }, + { 0x0000a1b8 , 0x00000776 }, + { 0x0000a1bc , 0x00000776 }, + { 0x0000a1c0 , 0x00000776 }, + { 0x0000a1c4 , 0x00000776 }, + { 0x0000a1c8 , 0x00000776 }, + { 0x0000a1cc , 0x00000776 }, + { 0x0000a1d0 , 0x00000776 }, + { 0x0000a1d4 , 0x00000776 }, + { 0x0000a1d8 , 0x00000776 }, + { 0x0000a1dc , 0x00000776 }, + { 0x0000a1e0 , 0x00000776 }, + { 0x0000a1e4 , 0x00000776 }, + { 0x0000a1e8 , 0x00000776 }, + { 0x0000a1ec , 0x00000776 }, + { 0x0000a1f0 , 0x00000776 }, + { 0x0000a1f4 , 0x00000776 }, + { 0x0000a1f8 , 0x00000776 }, + { 0x0000a1fc , 0x00000776 }, + { 0x0000b000 , 0x02000101 }, + { 0x0000b004 , 0x02000102 }, + { 0x0000b008 , 0x02000103 }, + { 0x0000b00c , 0x02000104 }, + { 0x0000b010 , 0x02000200 }, + { 0x0000b014 , 0x02000201 }, + { 0x0000b018 , 0x02000202 }, + { 0x0000b01c , 0x02000203 }, + { 0x0000b020 , 0x02000204 }, + { 0x0000b024 , 0x02000205 }, + { 0x0000b028 , 0x02000208 }, + { 0x0000b02c , 0x02000302 }, + { 0x0000b030 , 0x02000303 }, + { 0x0000b034 , 0x02000304 }, + { 0x0000b038 , 0x02000400 }, + { 0x0000b03c , 0x02010300 }, + { 0x0000b040 , 0x02010301 }, + { 0x0000b044 , 0x02010302 }, + { 0x0000b048 , 0x02000500 }, + { 0x0000b04c , 0x02010400 }, + { 0x0000b050 , 0x02020300 }, + { 0x0000b054 , 0x02020301 }, + { 0x0000b058 , 0x02020302 }, + { 0x0000b05c , 0x02020303 }, + { 0x0000b060 , 0x02020400 }, + { 0x0000b064 , 0x02030300 }, + { 0x0000b068 , 0x02030301 }, + { 0x0000b06c , 0x02030302 }, + { 0x0000b070 , 0x02030303 }, + { 0x0000b074 , 0x02030400 }, + { 0x0000b078 , 0x02040300 }, + { 0x0000b07c , 0x02040301 }, + { 0x0000b080 , 0x02040302 }, + { 0x0000b084 , 0x02040303 }, + { 0x0000b088 , 0x02030500 }, + { 0x0000b08c , 0x02040400 }, + { 0x0000b090 , 0x02050203 }, + { 0x0000b094 , 0x02050204 }, + { 0x0000b098 , 0x02050205 }, + { 0x0000b09c , 0x02040500 }, + { 0x0000b0a0 , 0x02050301 }, + { 0x0000b0a4 , 0x02050302 }, + { 0x0000b0a8 , 0x02050303 }, + { 0x0000b0ac , 0x02050400 }, + { 0x0000b0b0 , 0x02050401 }, + { 0x0000b0b4 , 0x02050402 }, + { 0x0000b0b8 , 0x02050403 }, + { 0x0000b0bc , 0x02050500 }, + { 0x0000b0c0 , 0x02050501 }, + { 0x0000b0c4 , 0x02050502 }, + { 0x0000b0c8 , 0x02050503 }, + { 0x0000b0cc , 0x02050504 }, + { 0x0000b0d0 , 0x02050600 }, + { 0x0000b0d4 , 0x02050601 }, + { 0x0000b0d8 , 0x02050602 }, + { 0x0000b0dc , 0x02050603 }, + { 0x0000b0e0 , 0x02050604 }, + { 0x0000b0e4 , 0x02050700 }, + { 0x0000b0e8 , 0x02050701 }, + { 0x0000b0ec , 0x02050702 }, + { 0x0000b0f0 , 0x02050703 }, + { 0x0000b0f4 , 0x02050704 }, + { 0x0000b0f8 , 0x02050705 }, + { 0x0000b0fc , 0x02050708 }, + { 0x0000b100 , 0x02050709 }, + { 0x0000b104 , 0x0205070a }, + { 0x0000b108 , 0x0205070b }, + { 0x0000b10c , 0x0205070c }, + { 0x0000b110 , 0x0205070d }, + { 0x0000b114 , 0x02050710 }, + { 0x0000b118 , 0x02050711 }, + { 0x0000b11c , 0x02050712 }, + { 0x0000b120 , 0x02050713 }, + { 0x0000b124 , 0x02050714 }, + { 0x0000b128 , 0x02050715 }, + { 0x0000b12c , 0x02050730 }, + { 0x0000b130 , 0x02050731 }, + { 0x0000b134 , 0x02050732 }, + { 0x0000b138 , 0x02050733 }, + { 0x0000b13c , 0x02050734 }, + { 0x0000b140 , 0x02050735 }, + { 0x0000b144 , 0x02050750 }, + { 0x0000b148 , 0x02050751 }, + { 0x0000b14c , 0x02050752 }, + { 0x0000b150 , 0x02050753 }, + { 0x0000b154 , 0x02050754 }, + { 0x0000b158 , 0x02050755 }, + { 0x0000b15c , 0x02050770 }, + { 0x0000b160 , 0x02050771 }, + { 0x0000b164 , 0x02050772 }, + { 0x0000b168 , 0x02050773 }, + { 0x0000b16c , 0x02050774 }, + { 0x0000b170 , 0x02050775 }, + { 0x0000b174 , 0x00000776 }, + { 0x0000b178 , 0x00000776 }, + { 0x0000b17c , 0x00000776 }, + { 0x0000b180 , 0x00000776 }, + { 0x0000b184 , 0x00000776 }, + { 0x0000b188 , 0x00000776 }, + { 0x0000b18c , 0x00000776 }, + { 0x0000b190 , 0x00000776 }, + { 0x0000b194 , 0x00000776 }, + { 0x0000b198 , 0x00000776 }, + { 0x0000b19c , 0x00000776 }, + { 0x0000b1a0 , 0x00000776 }, + { 0x0000b1a4 , 0x00000776 }, + { 0x0000b1a8 , 0x00000776 }, + { 0x0000b1ac , 0x00000776 }, + { 0x0000b1b0 , 0x00000776 }, + { 0x0000b1b4 , 0x00000776 }, + { 0x0000b1b8 , 0x00000776 }, + { 0x0000b1bc , 0x00000776 }, + { 0x0000b1c0 , 0x00000776 }, + { 0x0000b1c4 , 0x00000776 }, + { 0x0000b1c8 , 0x00000776 }, + { 0x0000b1cc , 0x00000776 }, + { 0x0000b1d0 , 0x00000776 }, + { 0x0000b1d4 , 0x00000776 }, + { 0x0000b1d8 , 0x00000776 }, + { 0x0000b1dc , 0x00000776 }, + { 0x0000b1e0 , 0x00000776 }, + { 0x0000b1e4 , 0x00000776 }, + { 0x0000b1e8 , 0x00000776 }, + { 0x0000b1ec , 0x00000776 }, + { 0x0000b1f0 , 0x00000776 }, + { 0x0000b1f4 , 0x00000776 }, + { 0x0000b1f8 , 0x00000776 }, + { 0x0000b1fc , 0x00000776 }, +}; + +static const u_int32_t ar956X_aphrodite_1p0_baseband_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009884 , 0x00001042 }, + { 0x00009c04 , 0x00000000 }, + { 0x00009c08 , 0x03200000 }, + { 0x00009e3c , 0xcf946221 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009fcc , 0x40000014 }, + { 0x0000a344 , 0x00000010 }, + { 0x0000a398 , 0x001f0e0f }, + { 0x0000a39c , 0x0075393f }, + { 0x0000a3a0 , 0xb79f6427 }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a404 , 0x00418a11 }, + { 0x0000a418 , 0x7d001dce }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a458 , 0x00404442 }, + { 0x0000a690 , 0x00000838 }, +}; + +static const u_int32_t ar956X_aphrodite_1p0_soc_preamble[][2] = { +/* Addr allmodes */ + { 0x00004014 , 0xba280400 }, + { 0x00004078 , 0x00000002 }, + { 0x000040a4 , 0x00a0c9c9 }, + { 0x00007010 , 0x00000022 }, + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000004c2 }, + { 0x00007048 , 0x00000002 }, +}; + +static const u_int32_t ar956X_aphrodite_1p0_soc_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00007010 , 0x00002233 , 0x00002233 , 0x00002233 , 0x00002233 }, +}; + +static const u_int32_t ar956X_aphrodite_1p0_mac_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, +}; + +static const u_int32_t ar956XCommon_rx_gain_table_aphrodite_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x01910190 }, + { 0x0000a030 , 0x01930192 }, + { 0x0000a034 , 0x01950194 }, + { 0x0000a038 , 0x038a0196 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x22222229 }, + { 0x0000a084 , 0x1d1d1d1d }, + { 0x0000a088 , 0x1d1d1d1d }, + { 0x0000a08c , 0x1d1d1d1d }, + { 0x0000a090 , 0x171d1d1d }, + { 0x0000a094 , 0x11111717 }, + { 0x0000a098 , 0x00030311 }, + { 0x0000a09c , 0x00000000 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x32323232 }, + { 0x0000b084 , 0x2f2f3232 }, + { 0x0000b088 , 0x23282a2d }, + { 0x0000b08c , 0x1c1e2123 }, + { 0x0000b090 , 0x14171919 }, + { 0x0000b094 , 0x0e0e1214 }, + { 0x0000b098 , 0x03050707 }, + { 0x0000b09c , 0x00030303 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar956X_aphrodite_1p0_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e44 , 0xfc500000 , 0xfc500000 , 0xfc500000 , 0xfc500000 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a28c , 0x00022222 , 0x00022222 , 0x00022222 , 0x00022222 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2d8 , 0x7999a800 , 0x7999a800 , 0x7999a80c , 0x7999a80c }, + { 0x0000a50c , 0x0000c00a , 0x0000c00a , 0x0000c00a , 0x0000c00a }, + { 0x0000a538 , 0x00038e8c , 0x00038e8c , 0x00038e8c , 0x00038e8c }, + { 0x0000a53c , 0x0003cecc , 0x0003cecc , 0x0003cecc , 0x0003cecc }, + { 0x0000a540 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 }, + { 0x0000a544 , 0x00044edc , 0x00044edc , 0x00044edc , 0x00044edc }, + { 0x0000a548 , 0x00048ede , 0x00048ede , 0x00048ede , 0x00048ede }, + { 0x0000a54c , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e }, + { 0x0000a550 , 0x00050f5e , 0x00050f5e , 0x00050f5e , 0x00050f5e }, + { 0x0000a554 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +}; + +static const u_int32_t ar956X_aphrodite_1p0_baseband_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 }, + { 0x00009820 , 0x206a022e , 0x206a022e , 0x206a012e , 0x206a012e }, + { 0x00009824 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 }, + { 0x00009828 , 0x06903081 , 0x06903081 , 0x06903881 , 0x06903881 }, + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000059c , 0x0000059c }, + { 0x00009c00 , 0x00000044 , 0x000000c4 , 0x000000c4 , 0x00000044 }, + { 0x00009e00 , 0x0372161e , 0x0372161e , 0x037216a0 , 0x037216a0 }, + { 0x00009e04 , 0x00802020 , 0x00802020 , 0x00802020 , 0x00802020 }, + { 0x00009e0c , 0x6c4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + { 0x00009e10 , 0x7ec88d2e , 0x7ec88d2e , 0x7ec84d2e , 0x7ec84d2e }, + { 0x00009e14 , 0x31395d5e , 0x3139605e , 0x3139605e , 0x31395d5e }, + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + { 0x00009e2c , 0x0000001c , 0x0000001c , 0x00000021 , 0x00000021 }, + { 0x00009e44 , 0xfe321e27 , 0xfe321e27 , 0xfe291e27 , 0xfe291e27 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302010 , 0x50302010 }, + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, + { 0x0000a204 , 0x033007c0 , 0x033007c4 , 0x033007c4 , 0x033007c0 }, + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + { 0x0000a230 , 0x0000400a , 0x00004014 , 0x00004016 , 0x0000400b }, + { 0x0000a238 , 0xffb81018 , 0xffb81018 , 0xffb81018 , 0xffb81018 }, + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a260 , 0x0a021501 , 0x0a021501 , 0x3a021501 , 0x3a021501 }, + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, + { 0x0000a288 , 0x00000110 , 0x00000110 , 0x00000110 , 0x00000110 }, + { 0x0000a28c , 0x00022222 , 0x00022222 , 0x00022222 , 0x00022222 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2d0 , 0x00071981 , 0x00071981 , 0x00071981 , 0x00071981 }, + { 0x0000a2d8 , 0xf999a83a , 0xf999a83a , 0xf999a83a , 0xf999a83a }, + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000ae04 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +}; + diff --git a/hal/ar9300/ar9300_attach.c b/hal/ar9300/ar9300_attach.c new file mode 100644 index 000000000000..9de27610c088 --- /dev/null +++ b/hal/ar9300/ar9300_attach.c @@ -0,0 +1,3965 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" +#include "ah_devid.h" + +#include "ar9300/ar9300desc.h" +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300phy.h" +#include "ar9300/ar9300paprd.h" + + +/* Add static register initialization vectors */ +#include "ar9300/ar9300_osprey22.ini" +#include "ar9300/ar9330_11.ini" +#include "ar9300/ar9330_12.ini" +#include "ar9300/ar9340.ini" +#include "ar9300/ar9485.ini" +#include "ar9300/ar9485_1_1.ini" +#include "ar9300/ar9300_jupiter10.ini" +#include "ar9300/ar9300_jupiter20.ini" +#include "ar9300/ar9580.ini" +#include "ar9300/ar955x.ini" +#include "ar9300/ar9300_aphrodite10.ini" + + +static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, + HAL_CHANNEL *chans, u_int32_t nchans); + +static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah); +static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah); +static inline void ar9300_hw_detach(struct ath_hal *ah); +static int16_t ar9300_get_nf_adjust(struct ath_hal *ah, + const HAL_CHANNEL_INTERNAL *c); +int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, + HAL_CAL_QUERY query); +#if ATH_TRAFFIC_FAST_RECOVER +unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah); +#endif +static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid); + + +static void +ar9300_disable_pcie_phy(struct ath_hal *ah); + +static const HAL_PERCAL_DATA iq_cal_single_sample = + {IQ_MISMATCH_CAL, + MIN_CAL_SAMPLES, + PER_MAX_LOG_COUNT, + ar9300_iq_cal_collect, + ar9300_iq_calibration}; + +static HAL_CALIBRATION_TIMER ar9300_cals[] = + { {IQ_MISMATCH_CAL, /* Cal type */ + 1200000, /* Cal interval */ + 0 /* Cal timestamp */ + }, + {TEMP_COMP_CAL, + 5000, + 0 + }, + }; + +#if ATH_PCIE_ERROR_MONITOR + +int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop) +{ + u_int32_t val; + + /* Clear the counters */ + OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0); + OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0); + + /* Read the previous value */ + val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); + + /* Set auto_stop */ + if (b_auto_stop) { + val |= + RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | + BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | + RPLY_NUM_RO_ERR_CTR_AUTO_STOP; + } else { + val &= ~( + RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | + BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | + RPLY_NUM_RO_ERR_CTR_AUTO_STOP); + } + OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); + + /* + * Start to run. + * This has to be done separately from the above auto_stop flag setting, + * to avoid a HW race condition. + */ + val |= + RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN | + RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN; + OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val); + + return 0; +} + +int ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters) +{ + u_int32_t val; + ar_pcie_error_moniter_counters *p_counters = + (ar_pcie_error_moniter_counters*) p_read_counters; + + val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0); + + p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK); + p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK); + p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK); + + val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1); + + p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK); + p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK); + + return 0; +} + +int ar9300_stop_pcie_error_monitor(struct ath_hal *ah) +{ + u_int32_t val; + + /* Read the previous value */ + val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); + + val &= ~( + RCVD_ERR_CTR_RUN | + BAD_TLP_ERR_CTR_RUN | + BAD_DLLP_ERR_CTR_RUN | + RPLY_TO_ERR_CTR_RUN | + RPLY_NUM_RO_ERR_CTR_RUN); + + /* Start to stop */ + OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); + + return 0; +} + +#endif /* ATH_PCIE_ERROR_MONITOR */ + +/* WIN32 does not support C99 */ +static const struct ath_hal_private ar9300hal = { + { + ar9300_get_rate_table, /* ah_get_rate_table */ + ar9300_detach, /* ah_detach */ + + /* Reset Functions */ + ar9300_reset, /* ah_reset */ + ar9300_phy_disable, /* ah_phy_disable */ + ar9300_disable, /* ah_disable */ + ar9300_config_pci_power_save, /* ah_config_pci_power_save */ + ar9300_set_pcu_config, /* ah_set_pcu_config */ + ar9300_calibration, /* ah_per_calibration */ + ar9300_reset_cal_valid, /* ah_reset_cal_valid */ + ar9300_set_tx_power_limit, /* ah_set_tx_power_limit */ + +#if ATH_ANT_DIV_COMB + ar9300_ant_ctrl_set_lna_div_use_bt_ant, /* ah_ant_ctrl_set_lna_div_use_bt_ant */ +#endif /* ATH_ANT_DIV_COMB */ +#ifdef ATH_SUPPORT_DFS + ar9300_radar_wait, /* ah_radar_wait */ + + /* New DFS functions */ + ar9300_check_dfs, /* ah_ar_check_dfs */ + ar9300_dfs_found, /* ah_ar_dfs_found */ + ar9300_enable_dfs, /* ah_ar_enable_dfs */ + ar9300_get_dfs_thresh, /* ah_ar_get_dfs_thresh */ + ar9300_get_dfs_radars, /* ah_ar_get_dfs_radars */ + ar9300_adjust_difs, /* ah_adjust_difs */ + ar9300_dfs_config_fft, /* ah_dfs_config_fft */ + ar9300_dfs_cac_war, /* ah_dfs_cac_war */ + ar9300_cac_tx_quiet, /* ah_cac_tx_quiet */ +#endif + ar9300_get_extension_channel, /* ah_get_extension_channel */ + ar9300_is_fast_clock_enabled, /* ah_is_fast_clock_enabled */ + + /* Transmit functions */ + ar9300_update_tx_trig_level, /* ah_update_tx_trig_level */ + ar9300_get_tx_trig_level, /* ah_get_tx_trig_level */ + ar9300_setup_tx_queue, /* ah_setup_tx_queue */ + ar9300_set_tx_queue_props, /* ah_set_tx_queue_props */ + ar9300_get_tx_queue_props, /* ah_get_tx_queue_props */ + ar9300_release_tx_queue, /* ah_release_tx_queue */ + ar9300_reset_tx_queue, /* ah_reset_tx_queue */ + ar9300_get_tx_dp, /* ah_get_tx_dp */ + ar9300_set_tx_dp, /* ah_set_tx_dp */ + ar9300_num_tx_pending, /* ah_num_tx_pending */ + ar9300_start_tx_dma, /* ah_start_tx_dma */ + ar9300_stop_tx_dma, /* ah_stop_tx_dma */ + ar9300_stop_tx_dma_indv_que, /* ah_stop_tx_dma_indv_que */ + ar9300_abort_tx_dma, /* ah_abort_tx_dma */ + ar9300_fill_tx_desc, /* ah_fill_tx_desc */ + ar9300_set_desc_link, /* ah_set_desc_link */ + ar9300_get_desc_link_ptr, /* ah_get_desc_link_ptr */ + ar9300_clear_tx_desc_status, /* ah_clear_tx_desc_status */ +#ifdef ATH_SWRETRY + ar9300_clear_dest_mask, /* ah_clear_dest_mask */ +#endif + ar9300_proc_tx_desc, /* ah_proc_tx_desc */ + ar9300_get_raw_tx_desc, /* ah_get_raw_tx_desc */ + ar9300_get_tx_rate_code, /* ah_get_tx_rate_code */ + AH_NULL, /* ah_get_tx_intr_queue */ + ar9300_tx_req_intr_desc, /* ah_req_tx_intr_desc */ + ar9300_calc_tx_airtime, /* ah_calc_tx_airtime */ + ar9300_setup_tx_status_ring, /* ah_setup_tx_status_ring */ + + /* RX Functions */ + ar9300_get_rx_dp, /* ah_get_rx_dp */ + ar9300_set_rx_dp, /* ah_set_rx_dp */ + ar9300_enable_receive, /* ah_enable_receive */ + ar9300_stop_dma_receive, /* ah_stop_dma_receive */ + ar9300_start_pcu_receive, /* ah_start_pcu_receive */ + ar9300_stop_pcu_receive, /* ah_stop_pcu_receive */ + ar9300_set_multicast_filter, /* ah_set_multicast_filter */ + ar9300_get_rx_filter, /* ah_get_rx_filter */ + ar9300_set_rx_filter, /* ah_set_rx_filter */ + ar9300_set_rx_sel_evm, /* ah_set_rx_sel_evm */ + ar9300_set_rx_abort, /* ah_set_rx_abort */ + AH_NULL, /* ah_setup_rx_desc */ + ar9300_proc_rx_desc, /* ah_proc_rx_desc */ + ar9300_get_rx_key_idx, /* ah_get_rx_key_idx */ + ar9300_proc_rx_desc_fast, /* ah_proc_rx_desc_fast */ + ar9300_ani_ar_poll, /* ah_rx_monitor */ + ar9300_process_mib_intr, /* ah_proc_mib_event */ + + /* Misc Functions */ + ar9300_get_capability, /* ah_get_capability */ + ar9300_set_capability, /* ah_set_capability */ + ar9300_get_diag_state, /* ah_get_diag_state */ + ar9300_get_mac_address, /* ah_get_mac_address */ + ar9300_set_mac_address, /* ah_set_mac_address */ + ar9300_get_bss_id_mask, /* ah_get_bss_id_mask */ + ar9300_set_bss_id_mask, /* ah_set_bss_id_mask */ + ar9300_set_regulatory_domain, /* ah_set_regulatory_domain */ + ar9300_set_led_state, /* ah_set_led_state */ + ar9300_set_power_led_state, /* ah_setpowerledstate */ + ar9300_set_network_led_state, /* ah_setnetworkledstate */ + ar9300_write_associd, /* ah_write_associd */ + ar9300_force_tsf_sync, /* ah_force_tsf_sync */ + ar9300_gpio_cfg_input, /* ah_gpio_cfg_input */ + ar9300_gpio_cfg_output, /* ah_gpio_cfg_output */ + ar9300_gpio_cfg_output_led_off, /* ah_gpio_cfg_output_led_off */ + ar9300_gpio_get, /* ah_gpio_get */ + ar9300_gpio_set, /* ah_gpio_set */ + ar9300_gpio_get_intr, /* ah_gpio_get_intr */ + ar9300_gpio_set_intr, /* ah_gpio_set_intr */ + ar9300_gpio_get_polarity, /* ah_gpio_get_polarity */ + ar9300_gpio_set_polarity, /* ah_gpio_set_polarity */ + ar9300_gpio_get_mask, /* ah_gpio_get_mask */ + ar9300_gpio_set_mask, /* ah_gpio_set_mask */ + ar9300_get_tsf32, /* ah_get_tsf32 */ + ar9300_get_tsf64, /* ah_get_tsf64 */ + ar9300_get_tsf2_32, /* ah_get_tsf2_32 */ + ar9300_reset_tsf, /* ah_reset_tsf */ + ar9300_detect_card_present, /* ah_detect_card_present */ + ar9300_update_mib_mac_stats, /* ah_update_mib_mac_stats */ + ar9300_get_mib_mac_stats, /* ah_get_mib_mac_stats */ + ar9300_get_rfgain, /* ah_get_rf_gain */ + ar9300_get_def_antenna, /* ah_get_def_antenna */ + ar9300_set_def_antenna, /* ah_set_def_antenna */ + ar9300_set_slot_time, /* ah_set_slot_time */ + ar9300_set_ack_timeout, /* ah_set_ack_timeout */ + ar9300_get_ack_timeout, /* ah_get_ack_timeout */ + ar9300_set_coverage_class, /* ah_set_coverage_class */ + ar9300_set_quiet, /* ah_set_quiet */ + ar9300_set_antenna_switch, /* ah_set_antenna_switch */ + ar9300_get_desc_info, /* ah_get_desc_info */ + ar9300_select_ant_config, /* ah_select_ant_config */ + ar9300_ant_ctrl_common_get, /* ah_ant_ctrl_common_get */ + ar9300_enable_tpc, /* ah_enable_tpc */ + AH_NULL, /* ah_olpc_temp_compensation */ +#if ATH_SUPPORT_CRDC + ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/ +#endif + ar9300_disable_phy_restart, /* ah_disable_phy_restart */ + ar9300_enable_keysearch_always, + ar9300_interference_is_present, /* ah_interference_is_present */ + ar9300_disp_tpc_tables, /* ah_disp_tpc_tables */ + ar9300_get_tpc_tables, /* ah_get_tpc_tables */ + /* Key Cache Functions */ + ar9300_get_key_cache_size, /* ah_get_key_cache_size */ + ar9300_reset_key_cache_entry, /* ah_reset_key_cache_entry */ + ar9300_is_key_cache_entry_valid, /* ah_is_key_cache_entry_valid */ + ar9300_set_key_cache_entry, /* ah_set_key_cache_entry */ + ar9300_set_key_cache_entry_mac, /* ah_set_key_cache_entry_mac */ + ar9300_print_keycache, /* ah_print_key_cache */ + + /* Power Management Functions */ + ar9300_set_power_mode, /* ah_set_power_mode */ + ar9300_set_sm_power_mode, /* ah_set_sm_ps_mode */ +#if ATH_WOW + ar9300_wow_apply_pattern, /* ah_wow_apply_pattern */ + ar9300_wow_enable, /* ah_wow_enable */ + ar9300_wow_wake_up, /* ah_wow_wake_up */ +#if ATH_WOW_OFFLOAD + ar9300_wowoffload_prep, /* ah_wow_offload_prep */ + ar9300_wowoffload_post, /* ah_wow_offload_post */ + ar9300_wowoffload_download_rekey_data, /* ah_wow_offload_download_rekey_data */ + ar9300_wowoffload_retrieve_data, /* ah_wow_offload_retrieve_data */ + ar9300_wowoffload_download_acer_magic, /* ah_wow_offload_download_acer_magic */ + ar9300_wowoffload_download_acer_swka, /* ah_wow_offload_download_acer_swka */ + ar9300_wowoffload_download_arp_info, /* ah_wow_offload_download_arp_info */ + ar9300_wowoffload_download_ns_info, /* ah_wow_offload_download_ns_info */ +#endif /* ATH_WOW_OFFLOAD */ +#endif + + /* Get Channel Noise */ + ath_hal_get_chan_noise, /* ah_get_chan_noise */ + ar9300_chain_noise_floor, /* ah_get_chain_noise_floor */ + + /* Beacon Functions */ + ar9300_beacon_init, /* ah_beacon_init */ + ar9300_set_sta_beacon_timers, /* ah_set_station_beacon_timers */ + + /* Interrupt Functions */ + ar9300_is_interrupt_pending, /* ah_is_interrupt_pending */ + ar9300_get_pending_interrupts, /* ah_get_pending_interrupts */ + ar9300_get_interrupts, /* ah_get_interrupts */ + ar9300_set_interrupts, /* ah_set_interrupts */ + ar9300_set_intr_mitigation_timer, /* ah_set_intr_mitigation_timer */ + ar9300_get_intr_mitigation_timer, /* ah_get_intr_mitigation_timer */ + ar9300ForceVCS, + ar9300SetDfs3StreamFix, + ar9300Get3StreamSignature, + + /* 11n specific functions (NOT applicable to ar9300) */ + ar9300_set_11n_tx_desc, /* ah_set_11n_tx_desc */ + /* Update rxchain */ + ar9300_set_rx_chainmask, /*ah_set_rx_chainmask*/ + /*Updating locationing register */ + ar9300_update_loc_ctl_reg, /*ah_update_loc_ctl_reg*/ + /* Start PAPRD functions */ + ar9300_set_paprd_tx_desc, /* ah_set_paprd_tx_desc */ + ar9300_paprd_init_table, /* ah_paprd_init_table */ + ar9300_paprd_setup_gain_table, /* ah_paprd_setup_gain_table */ + ar9300_paprd_create_curve, /* ah_paprd_create_curve */ + ar9300_paprd_is_done, /* ah_paprd_is_done */ + ar9300_enable_paprd, /* ah_PAPRDEnable */ + ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */ + ar9300_is_tx_done, /* ah_is_tx_done */ + ar9300_paprd_dec_tx_pwr, /* ah_paprd_dec_tx_pwr*/ + ar9300_paprd_thermal_send, /* ah_paprd_thermal_send */ + /* End PAPRD functions */ + ar9300_set_11n_rate_scenario, /* ah_set_11n_rate_scenario */ + ar9300_set_11n_aggr_first, /* ah_set_11n_aggr_first */ + ar9300_set_11n_aggr_middle, /* ah_set_11n_aggr_middle */ + ar9300_set_11n_aggr_last, /* ah_set_11n_aggr_last */ + ar9300_clr_11n_aggr, /* ah_clr_11n_aggr */ + ar9300_set_11n_rifs_burst_middle, /* ah_set_11n_rifs_burst_middle */ + ar9300_set_11n_rifs_burst_last, /* ah_set_11n_rifs_burst_last */ + ar9300_clr_11n_rifs_burst, /* ah_clr_11n_rifs_burst */ + ar9300_set_11n_aggr_rifs_burst, /* ah_set_11n_aggr_rifs_burst */ + ar9300_set_11n_rx_rifs, /* ah_set_11n_rx_rifs */ + ar9300_set_smart_antenna, /* ah_setSmartAntenna */ + ar9300_detect_bb_hang, /* ah_detect_bb_hang */ + ar9300_detect_mac_hang, /* ah_detect_mac_hang */ + ar9300_set_immunity, /* ah_immunity */ + ar9300_get_hw_hangs, /* ah_get_hang_types */ + ar9300_set_11n_burst_duration, /* ah_set_11n_burst_duration */ + ar9300_set_11n_virtual_more_frag, /* ah_set_11n_virtual_more_frag */ + ar9300_get_11n_ext_busy, /* ah_get_11n_ext_busy */ + ar9300_set_11n_mac2040, /* ah_set_11n_mac2040 */ + ar9300_get_11n_rx_clear, /* ah_get_11n_rx_clear */ + ar9300_set_11n_rx_clear, /* ah_set_11n_rx_clear */ + ar9300_get_mib_cycle_counts_pct, /* ah_get_mib_cycle_counts_pct */ + ar9300_dma_reg_dump, /* ah_dma_reg_dump */ + + /* force_ppm specific functions */ + ar9300_ppm_get_rssi_dump, /* ah_ppm_get_rssi_dump */ + ar9300_ppm_arm_trigger, /* ah_ppm_arm_trigger */ + ar9300_ppm_get_trigger, /* ah_ppm_get_trigger */ + ar9300_ppm_force, /* ah_ppm_force */ + ar9300_ppm_un_force, /* ah_ppm_un_force */ + ar9300_ppm_get_force_state, /* ah_ppm_get_force_state */ + + ar9300_get_spur_info, /* ah_get_spur_info */ + ar9300_set_spur_info, /* ah_get_spur_info */ + + ar9300_get_min_cca_pwr, /* ah_ar_get_noise_floor_val */ + + ar9300_green_ap_ps_on_off, /* ah_set_rx_green_ap_ps_on_off */ + ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */ + + /* radio measurement specific functions */ + ar9300_get_mib_cycle_counts, /* ah_get_mib_cycle_counts */ + ar9300_get_vow_stats, /* ah_get_vow_stats */ + ar9300_clear_mib_counters, /* ah_clear_mib_counters */ +#if ATH_GEN_RANDOMNESS + ar9300_get_rssi_chain0, /* ah_get_rssi_chain0 */ +#endif +#ifdef ATH_BT_COEX + /* Bluetooth Coexistence functions */ + ar9300_set_bt_coex_info, /* ah_set_bt_coex_info */ + ar9300_bt_coex_config, /* ah_bt_coex_config */ + ar9300_bt_coex_set_qcu_thresh, /* ah_bt_coex_set_qcu_thresh */ + ar9300_bt_coex_set_weights, /* ah_bt_coex_set_weights */ + ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */ + ar9300_bt_coex_set_parameter, /* ah_bt_coex_set_parameter */ + ar9300_bt_coex_disable, /* ah_bt_coex_disable */ + ar9300_bt_coex_enable, /* ah_bt_coex_enable */ + ar9300_get_bt_active_gpio, /* ah_bt_coex_info*/ + ar9300_get_wlan_active_gpio, /* ah__coex_wlan_info*/ +#endif + /* Generic Timer functions */ + ar9300_alloc_generic_timer, /* ah_gentimer_alloc */ + ar9300_free_generic_timer, /* ah_gentimer_free */ + ar9300_start_generic_timer, /* ah_gentimer_start */ + ar9300_stop_generic_timer, /* ah_gentimer_stop */ + ar9300_get_gen_timer_interrupts, /* ah_gentimer_get_intr */ + + ar9300_set_dcs_mode, /* ah_set_dcs_mode */ + ar9300_get_dcs_mode, /* ah_get_dcs_mode */ + +#if ATH_ANT_DIV_COMB + ar9300_ant_div_comb_get_config, /* ah_get_ant_dvi_comb_conf */ + ar9300_ant_div_comb_set_config, /* ah_set_ant_dvi_comb_conf */ +#endif + + ar9300_get_bb_panic_info, /* ah_get_bb_panic_info */ + ar9300_handle_radar_bb_panic, /* ah_handle_radar_bb_panic */ + ar9300_set_hal_reset_reason, /* ah_set_hal_reset_reason */ + +#if ATH_PCIE_ERROR_MONITOR + ar9300_start_pcie_error_monitor, /* ah_start_pcie_error_monitor */ + ar9300_read_pcie_error_monitor, /* ah_read_pcie_error_monitor*/ + ar9300_stop_pcie_error_monitor, /* ah_stop_pcie_error_monitor*/ +#endif /* ATH_PCIE_ERROR_MONITOR */ + +#if ATH_SUPPORT_SPECTRAL + /* Spectral scan */ + ar9300_configure_spectral_scan, /* ah_ar_configure_spectral */ + ar9300_get_spectral_params, /* ah_ar_get_spectral_config */ + ar9300_start_spectral_scan, /* ah_ar_start_spectral_scan */ + ar9300_stop_spectral_scan, /* ah_ar_stop_spectral_scan */ + ar9300_is_spectral_enabled, /* ah_ar_is_spectral_enabled */ + ar9300_is_spectral_active, /* ah_ar_is_spectral_active */ + ar9300_get_ctl_chan_nf, /* ah_ar_get_ctl_nf */ + ar9300_get_ext_chan_nf, /* ah_ar_get_ext_nf */ +#endif /* ATH_SUPPORT_SPECTRAL */ + + + ar9300_promisc_mode, /* ah_promisc_mode */ + ar9300_read_pktlog_reg, /* ah_read_pktlog_reg */ + ar9300_write_pktlog_reg, /* ah_write_pktlog_reg */ + ar9300_set_proxy_sta, /* ah_set_proxy_sta */ + ar9300_get_cal_intervals, /* ah_get_cal_intervals */ +#if ATH_TRAFFIC_FAST_RECOVER + ar9300_get_pll3_sqsum_dvc, /* ah_get_pll3_sqsum_dvc */ +#endif +#ifdef ATH_SUPPORT_HTC + AH_NULL, +#endif + +#ifdef ATH_TX99_DIAG + /* Tx99 functions */ +#ifdef ATH_SUPPORT_HTC + AH_NULL, + AH_NULL, + AH_NULL, + AH_NULL, + AH_NULL, + AH_NULL, + AH_NULL, +#else + AH_NULL, + AH_NULL, + ar9300TX99TgtChannelPwrUpdate, /* ah_tx99channelpwrupdate */ + ar9300TX99TgtStart, /* ah_tx99start */ + ar9300TX99TgtStop, /* ah_tx99stop */ + ar9300TX99TgtChainmskSetup, /* ah_tx99_chainmsk_setup */ + ar9300TX99SetSingleCarrier, /* ah_tx99_set_single_carrier */ +#endif +#endif + ar9300_chk_rssi_update_tx_pwr, + ar9300_is_skip_paprd_by_greentx, /* ah_is_skip_paprd_by_greentx */ + ar9300_hwgreentx_set_pal_spare, /* ah_hwgreentx_set_pal_spare */ +#if ATH_SUPPORT_MCI + /* MCI Coexistence Functions */ + ar9300_mci_setup, /* ah_mci_setup */ + ar9300_mci_send_message, /* ah_mci_send_message */ + ar9300_mci_get_interrupt, /* ah_mci_get_interrupt */ + ar9300_mci_state, /* ah_mci_state */ + ar9300_mci_detach, /* ah_mci_detach */ +#endif + ar9300_reset_hw_beacon_proc_crc, /* ah_reset_hw_beacon_proc_crc */ + ar9300_get_hw_beacon_rssi, /* ah_get_hw_beacon_rssi */ + ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/ + ar9300_reset_hw_beacon_rssi, /* ah_reset_hw_beacon_rssi */ + ar9300_mat_enable, /* ah_mat_enable */ + ar9300_dump_keycache, /* ah_dump_keycache */ + ar9300_is_ani_noise_spur, /* ah_is_ani_noise_spur */ + ar9300_set_hw_beacon_proc, /* ah_set_hw_beacon_proc */ + }, + + ar9300_get_channel_edges, /* ah_get_channel_edges */ + ar9300_get_wireless_modes, /* ah_get_wireless_modes */ + ar9300_eeprom_read_word, /* ah_eeprom_read */ + AH_NULL, + ar9300_eeprom_dump_support, /* ah_eeprom_dump */ + ar9300_get_chip_power_limits, /* ah_get_chip_power_limits */ + + ar9300_get_nf_adjust, /* ah_get_nf_adjust */ + /* rest is zero'd by compiler */ +}; + +/* + * Read MAC version/revision information from Chip registers and initialize + * local data structures. + */ +void +ar9300_read_revisions(struct ath_hal *ah) +{ + u_int32_t val; + + /* XXX verify if this is the correct way to read revision on Osprey */ + /* new SREV format for Sowl and later */ + val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); + + if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { + /* XXX: AR_SREV register in Wasp reads 0 */ + AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; + } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR955X) { + /* XXX: AR_SREV register in Scorpion reads 0 */ + AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; + } else { + /* + * Include 6-bit Chip Type (masked to 0) + * to differentiate from pre-Sowl versions + */ + AH_PRIVATE(ah)->ah_macVersion = + (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; + } + + + + + +#ifdef AH_SUPPORT_HORNET + /* + * EV74984, due to Hornet 1.1 didn't update WMAC revision, + * so that have to read SoC's revision ID instead + */ + if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) { +#define AR_SOC_RST_REVISION_ID 0xB8060090 +#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) + if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK) + == AR_SREV_REVISION_HORNET_11) + { + AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11; + } else { + AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); + } +#undef REG_READ +#undef AR_SOC_RST_REVISION_ID + } else +#endif + if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP) + { +#define AR_SOC_RST_REVISION_ID 0xB8060090 +#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) + + AH_PRIVATE(ah)->ah_macRev = + REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK; +#undef REG_READ +#undef AR_SOC_RST_REVISION_ID + } + else + AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); + + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + AH_PRIVATE(ah)->ah_is_pci_express = AH_TRUE; + } + else { + AH_PRIVATE(ah)->ah_is_pci_express = + (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; + } + +} + +/* + * Attach for an AR9300 part. + */ +struct ath_hal * +ar9300_attach(u_int16_t devid, HAL_ADAPTER_HANDLE osdev, HAL_SOFTC sc, + HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_BUS_TYPE bustype, + asf_amem_instance_handle amem_handle, + struct hal_reg_parm *hal_conf_parm, HAL_STATUS *status) +{ + struct ath_hal_9300 *ahp; + struct ath_hal *ah; + struct ath_hal_private *ahpriv; + HAL_STATUS ecode; + + HAL_NO_INTERSPERSED_READS; + + /* NB: memory is returned zero'd */ + ahp = ar9300_new_state( + devid, osdev, sc, st, sh, bustype, amem_handle, hal_conf_parm, status); + if (ahp == AH_NULL) { + return AH_NULL; + } + ah = &ahp->ah_priv.priv.h; + ar9300_init_offsets(ah, devid); + ahpriv = AH_PRIVATE(ah); + AH_PRIVATE(ah)->ah_bustype = bustype; + + + /* interrupt mitigation */ +#ifdef AR5416_INT_MITIGATION + if (ahpriv->ah_config.ath_hal_intr_mitigation_rx != 0) { + ahp->ah_intr_mitigation_rx = AH_TRUE; + } +#else + /* Enable Rx mitigation (default) */ + ahp->ah_intr_mitigation_rx = AH_TRUE; + ahpriv->ah_config.ath_hal_intr_mitigation_rx = 1; + +#endif +#ifdef HOST_OFFLOAD + /* Reset default Rx mitigation values for Hornet */ + if (AR_SREV_HORNET(ah)) { + ahp->ah_intr_mitigation_rx = AH_FALSE; +#ifdef AR5416_INT_MITIGATION + ahpriv->ah_config.ath_hal_intr_mitigation_rx = 0; +#endif + } +#endif + + if (ahpriv->ah_config.ath_hal_intr_mitigation_tx != 0) { + ahp->ah_intr_mitigation_tx = AH_TRUE; + } + + /* + * Read back AR_WA into a permanent copy and set bits 14 and 17. + * We need to do this to avoid RMW of this register. + * Do this before calling ar9300_set_reset_reg. + * If not, the AR_WA register which was inited via EEPROM + * will get wiped out. + */ + ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); + /* Set Bits 14 and 17 in the AR_WA register. */ + ahp->ah_wa_reg_val |= + AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE; + + if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */ + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__); + ecode = HAL_EIO; + goto bad; + } + + if (AR_SREV_JUPITER(ah) +#if ATH_WOW_OFFLOAD + && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14) +#endif + ) + { + /* Jupiter doesn't need bit 14 to be set. */ + ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE; + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); + } + +#if ATH_SUPPORT_MCI + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + ah->ah_bt_coex_set_weights = ar9300_mci_bt_coex_set_weights; + ah->ah_bt_coex_disable = ar9300_mci_bt_coex_disable; + ah->ah_bt_coex_enable = ar9300_mci_bt_coex_enable; + ahp->ah_mci_ready = AH_FALSE; + ahp->ah_mci_bt_state = MCI_BT_SLEEP; + ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN; + ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN; + ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT; + ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT; + ahp->ah_mci_coex_bt_version_known = AH_FALSE; + ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */ + /* will be updated before boot up sequence */ + ahp->ah_mci_coex_is_2g = AH_TRUE; + ahp->ah_mci_coex_wlan_channels_update = AH_FALSE; + ahp->ah_mci_coex_wlan_channels[0] = 0x00000000; + ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff; + ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff; + ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff; + ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */ + ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */ + ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */ + ahp->ah_mci_need_flush_btinfo = AH_FALSE; + ahp->ah_mci_wlan_cal_seq = 0; + ahp->ah_mci_wlan_cal_done = 0; + } +#endif /* ATH_SUPPORT_MCI */ + +#if ATH_WOW_OFFLOAD + ahp->ah_mcast_filter_l32_set = 0; + ahp->ah_mcast_filter_u32_set = 0; +#endif + + if (AR_SREV_HORNET(ah)) { +#ifdef AH_SUPPORT_HORNET + if (!AR_SREV_HORNET_11(ah)) { + /* + * Do not check bootstrap register, which cannot be trusted + * due to s26 switch issue on CUS164/AP121. + */ + ahp->clk_25mhz = 1; + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); + } else { + /* check bootstrap clock setting */ +#define AR_SOC_SEL_25M_40M 0xB80600AC +#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); +#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) + if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) { + ahp->clk_25mhz = 0; + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "Bootstrap clock 40MHz\n"); + } else { + ahp->clk_25mhz = 1; + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "Bootstrap clock 25MHz\n"); + } +#undef REG_READ +#undef REG_WRITE +#undef AR_SOC_SEL_25M_40M + } +#endif /* AH_SUPPORT_HORNET */ + } + + if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + /* check bootstrap clock setting */ +#define AR9340_SOC_SEL_25M_40M 0xB80600B0 +#define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ +#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) + if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) { + ahp->clk_25mhz = 0; + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n"); + } else { + ahp->clk_25mhz = 1; + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); + } +#undef REG_READ +#undef AR9340_SOC_SEL_25M_40M +#undef AR9340_REF_CLK_40 + } + ar9300_init_pll(ah, AH_NULL); + + if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__); + ecode = HAL_EIO; + goto bad; + } + + /* No serialization of Register Accesses needed. */ + ahpriv->ah_config.ath_hal_serialize_reg_mode = SER_REG_MODE_OFF; + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ath_hal_serialize_reg_mode is %d\n", + __func__, ahpriv->ah_config.ath_hal_serialize_reg_mode); + + /* + * Add mac revision check when needed. + * - Osprey 1.0 and 2.0 no longer supported. + */ + if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) && + (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) || + (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY && + ahpriv->ah_macVersion != AR_SREV_VERSION_WASP && + ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET && + ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON && + ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION && + ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER && + ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) { + HALDEBUG(ah, HAL_DEBUG_RESET, + "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n", + __func__, + ahpriv->ah_macVersion, + ahpriv->ah_macRev); + ecode = HAL_ENOTSUPP; + goto bad; + } + + ahpriv->ah_phy_rev = OS_REG_READ(ah, AR_PHY_CHIP_ID); + + /* Setup supported calibrations */ + ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample; + ahp->ah_supp_cals = IQ_MISMATCH_CAL; + + /* Enable ANI */ + ahp->ah_ani_function = HAL_ANI_ALL; + + /* Enable RIFS */ + ahp->ah_rifs_enabled = AH_TRUE; + + HALDEBUG(ah, HAL_DEBUG_RESET, + "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, + ahpriv->ah_macVersion, + ahpriv->ah_macRev); + + if (AR_SREV_HORNET_12(ah)) { + /* mac */ + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar9331_hornet1_2_mac_core, + ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], + ar9331_hornet1_2_mac_postamble, + ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5); + + /* bb */ + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], + ar9331_hornet1_2_baseband_core, + ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar9331_hornet1_2_baseband_postamble, + ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5); + + /* radio */ + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], + ar9331_hornet1_2_radio_core, + ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); + + /* soc */ + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar9331_hornet1_2_soc_preamble, + ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], + ar9331_hornet1_2_soc_postamble, + ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2); + + /* rx/tx gain */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9331_common_rx_gain_hornet1_2, + ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, + ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); + + ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0; + + /* Japan 2484Mhz CCK settings */ + INIT_INI_ARRAY(&ahp->ah_ini_japan2484, + ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484, + ARRAY_LENGTH( + ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2); + +#if 0 /* ATH_WOW */ + /* SerDes values during WOW sleep */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, + ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); +#endif + + /* additional clock settings */ + if (AH9300(ah)->clk_25mhz) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, + ar9331_hornet1_2_xtal_25M, + ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, + ar9331_hornet1_2_xtal_40M, + ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2); + } + + } else if (AR_SREV_HORNET_11(ah)) { + /* mac */ + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar9331_hornet1_1_mac_core, + ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], + ar9331_hornet1_1_mac_postamble, + ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5); + + /* bb */ + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], + ar9331_hornet1_1_baseband_core, + ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar9331_hornet1_1_baseband_postamble, + ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5); + + /* radio */ + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], + ar9331_hornet1_1_radio_core, + ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); + + /* soc */ + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar9331_hornet1_1_soc_preamble, + ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], + ar9331_hornet1_1_soc_postamble, + ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2); + + /* rx/tx gain */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9331_common_rx_gain_hornet1_1, + ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, + ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); + + ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0; + + /* Japan 2484Mhz CCK settings */ + INIT_INI_ARRAY(&ahp->ah_ini_japan2484, + ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484, + ARRAY_LENGTH( + ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2); + +#if 0 /* ATH_WOW */ + /* SerDes values during WOW sleep */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, + N(ar9300_pcie_phy_awow), 2); +#endif + + /* additional clock settings */ + if (AH9300(ah)->clk_25mhz) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, + ar9331_hornet1_1_xtal_25M, + ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, + ar9331_hornet1_1_xtal_40M, + ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2); + } + + } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { + /* mac */ + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar9485_poseidon1_1_mac_core, + ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], + ar9485_poseidon1_1_mac_postamble, + ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5); + + /* bb */ + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], + ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], + ar9485_poseidon1_1_baseband_core, + ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar9485_poseidon1_1_baseband_postamble, + ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5); + + /* radio */ + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], + ar9485_poseidon1_1_radio_core, + ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], + ar9485_poseidon1_1_radio_postamble, + ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2); + + /* soc */ + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar9485_poseidon1_1_soc_preamble, + ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2); + + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); + + /* rx/tx gain */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9485_common_wo_xlna_rx_gain_poseidon1_1, + ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, + ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); + + /* Japan 2484Mhz CCK settings */ + INIT_INI_ARRAY(&ahp->ah_ini_japan2484, + ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484, + ARRAY_LENGTH( + ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2); + + /* Load PCIE SERDES settings from INI */ + if (ahpriv->ah_config.ath_hal_pcie_clock_req) { + /* Pci-e Clock Request = 1 */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save + & AR_PCIE_PLL_PWRSAVE_CONTROL) + { + /* Sleep Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D3) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), + 2); + } + /* Awake Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D0) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), + 2); + } + + } else { + /*Use driver default setting*/ + /* Sleep Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, + ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), + 2); + /* Awake Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, + ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), + 2); + } + } else { + /* Pci-e Clock Request = 0 */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save + & AR_PCIE_PLL_PWRSAVE_CONTROL) + { + /* Sleep Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D3) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), + 2); + } + /* Awake Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D0) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), + 2); + } + + } else { + /*Use driver default setting*/ + /* Sleep Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, + ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), + 2); + /* Awake Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, + ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), + 2); + } + } + /* pcie ps setting will honor registry setting, default is 0 */ + //ahpriv->ah_config.ath_hal_pciePowerSaveEnable = 0; + } else if (AR_SREV_POSEIDON(ah)) { + /* mac */ + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar9485_poseidon1_0_mac_core, + ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], + ar9485_poseidon1_0_mac_postamble, + ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5); + + /* bb */ + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], + ar9485_poseidon1_0, + ARRAY_LENGTH(ar9485_poseidon1_0), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], + ar9485_poseidon1_0_baseband_core, + ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar9485_poseidon1_0_baseband_postamble, + ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5); + + /* radio */ + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], + ar9485_poseidon1_0_radio_core, + ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], + ar9485_poseidon1_0_radio_postamble, + ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2); + + /* soc */ + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar9485_poseidon1_0_soc_preamble, + ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); + + /* rx/tx gain */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9485Common_wo_xlna_rx_gain_poseidon1_0, + ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, + ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); + + /* Japan 2484Mhz CCK settings */ + INIT_INI_ARRAY(&ahp->ah_ini_japan2484, + ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484, + ARRAY_LENGTH( + ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2); + + /* Load PCIE SERDES settings from INI */ + if (ahpriv->ah_config.ath_hal_pcie_clock_req) { + /* Pci-e Clock Request = 1 */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save + & AR_PCIE_PLL_PWRSAVE_CONTROL) + { + /* Sleep Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D3) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), + 2); + } + /* Awake Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D0) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), + 2); + } + + } else { + /*Use driver default setting*/ + /* Sleep Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), + 2); + /* Awake Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), + 2); + } + } else { + /* Pci-e Clock Request = 0 */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save + & AR_PCIE_PLL_PWRSAVE_CONTROL) + { + /* Sleep Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D3) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), + 2); + } + /* Awake Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D0) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), + 2); + } + + } else { + /*Use driver default setting*/ + /* Sleep Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), + 2); + /* Awake Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, + ARRAY_LENGTH( + ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), + 2); + } + } + /* pcie ps setting will honor registry setting, default is 0 */ + /*ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0;*/ + +#if 0 /* ATH_WOW */ + /* SerDes values during WOW sleep */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, + ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); +#endif + + } else if (AR_SREV_WASP(ah)) { + /* mac */ + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar9340_wasp_1p0_mac_core, + ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], + ar9340_wasp_1p0_mac_postamble, + ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5); + + /* bb */ + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], + ar9340_wasp_1p0_baseband_core, + ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar9340_wasp_1p0_baseband_postamble, + ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5); + + /* radio */ + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], + ar9340_wasp_1p0_radio_core, + ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], + ar9340_wasp_1p0_radio_postamble, + ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5); + + /* soc */ + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar9340_wasp_1p0_soc_preamble, + ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], + ar9340_wasp_1p0_soc_postamble, + ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5); + + /* rx/tx gain */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, + ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, + ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); + + ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0; + + /* Fast clock modal settings */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, + ar9340Modes_fast_clock_wasp_1p0, + ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3); + + /* Additional setttings for 40Mhz */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz, + ar9340_wasp_1p0_radio_core_40M, + ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2); + + /* DFS */ + INIT_INI_ARRAY(&ahp->ah_ini_dfs, + ar9340_wasp_1p0_baseband_postamble_dfs_channel, + ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3); + } else if (AR_SREV_SCORPION(ah)) { + /* mac */ + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar955x_scorpion_1p0_mac_core, + ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], + ar955x_scorpion_1p0_mac_postamble, + ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5); + + /* bb */ + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], + ar955x_scorpion_1p0_baseband_core, + ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar955x_scorpion_1p0_baseband_postamble, + ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5); + + /* radio */ + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], + ar955x_scorpion_1p0_radio_core, + ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], + ar955x_scorpion_1p0_radio_postamble, + ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5); + + /* soc */ + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar955x_scorpion_1p0_soc_preamble, + ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], + ar955x_scorpion_1p0_soc_postamble, + ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5); + + /* rx/tx gain */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, + ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, + ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, + ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, + ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5); + + /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ + ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0; + + /* Fast clock modal settings */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, + ar955xModes_fast_clock_scorpion_1p0, + ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3); + + /* Additional setttings for 40Mhz */ + //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, + // ar955x_scorpion_1p0_radio_core_40M, + // ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2); + } else if (AR_SREV_JUPITER_10(ah)) { + /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ + + /* mac */ + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar9300_jupiter_1p0_mac_core, + ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], + ar9300_jupiter_1p0_mac_postamble, + ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5); + + /* bb */ + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], + ar9300_jupiter_1p0_baseband_core, + ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar9300_jupiter_1p0_baseband_postamble, + ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5); + + /* radio */ + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], + ar9300_jupiter_1p0_radio_core, + ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], + ar9300_jupiter_1p0_radio_postamble, + ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5); + + /* soc */ + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar9300_jupiter_1p0_soc_preamble, + ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], + ar9300_jupiter_1p0_soc_postamble, + ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5); + + /* rx/tx gain */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300_common_rx_gain_table_jupiter_1p0, + ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); + + /* Load PCIE SERDES settings from INI */ + if (ahpriv->ah_config.ath_hal_pcie_clock_req) { + /* Pci-e Clock Request = 1 */ + /* + * PLL ON + clkreq enable is not a valid combination, + * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. + */ + { + /*Use driver default setting*/ + /* Awake -> Sleep Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, + ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), + 2); + /* Sleep -> Awake Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, + ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), + 2); + } + } + else { + /* + * Since Jupiter 1.0 and 2.0 share the same device id and will be + * installed with same INF, but Jupiter 1.0 has issue with PLL OFF. + * + * Force Jupiter 1.0 to use ON/ON setting. + */ + ahpriv->ah_config.ath_hal_pll_pwr_save = 0; + /* Pci-e Clock Request = 0 */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_CONTROL) + { + /* Awake -> Sleep Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D3) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, + ARRAY_LENGTH( + ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), + 2); + } + else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, + ARRAY_LENGTH( + ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), + 2); + } + /* Sleep -> Awake Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D0) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, + ARRAY_LENGTH( + ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), + 2); + } + else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, + ARRAY_LENGTH( + ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), + 2); + } + + } + else { + /*Use driver default setting*/ + /* Awake -> Sleep Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, + ARRAY_LENGTH( + ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), + 2); + /* Sleep -> Awake Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, + ARRAY_LENGTH( + ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), + 2); + } + } + /* + * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and + * 0 for merlin + */ + ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0; + +#if 0 // ATH_WOW + /* SerDes values during WOW sleep */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, + ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); +#endif + + /* Fast clock modal settings */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, + ar9300_modes_fast_clock_jupiter_1p0, + ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3); + INIT_INI_ARRAY(&ahp->ah_ini_japan2484, + ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484, + ARRAY_LENGTH( + ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2); + + } + else if (AR_SREV_JUPITER_20(ah)) { + /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ + + /* mac */ + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar9300_jupiter_2p0_mac_core, + ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], + ar9300_jupiter_2p0_mac_postamble, + ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5); + + /* bb */ + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], + ar9300_jupiter_2p0_baseband_core, + ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar9300_jupiter_2p0_baseband_postamble, + ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5); + + /* radio */ + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], + ar9300_jupiter_2p0_radio_core, + ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], + ar9300_jupiter_2p0_radio_postamble, + ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5); + INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant, + ar9300_jupiter_2p0_radio_postamble_sys2ant, + ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5); + + /* soc */ + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar9300_jupiter_2p0_soc_preamble, + ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], + ar9300_jupiter_2p0_soc_postamble, + ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5); + + /* rx/tx gain */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300Common_rx_gain_table_jupiter_2p0, + ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); + + /* BTCOEX */ + INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR, + ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table, + ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2); + + /* Load PCIE SERDES settings from INI */ + if (ahpriv->ah_config.ath_hal_pcie_clock_req) { + /* Pci-e Clock Request = 1 */ + /* + * PLL ON + clkreq enable is not a valid combination, + * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. + */ + { + /*Use driver default setting*/ + /* Awake -> Sleep Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, + ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), + 2); + /* Sleep -> Awake Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, + ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), + 2); + } + } + else { + /* Pci-e Clock Request = 0 */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_CONTROL) + { + /* Awake -> Sleep Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D3) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, + ARRAY_LENGTH( + ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), + 2); + } + else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, + ARRAY_LENGTH( + ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), + 2); + } + /* Sleep -> Awake Setting */ + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D0) + { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, + ARRAY_LENGTH( + ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), + 2); + } + else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, + ARRAY_LENGTH( + ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), + 2); + } + + } + else { + /*Use driver default setting*/ + /* Awake -> Sleep Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, + ARRAY_LENGTH( + ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), + 2); + /* Sleep -> Awake Setting */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, + ARRAY_LENGTH( + ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), + 2); + } + } + + /* + * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and + * 0 for merlin + */ + ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0; + +#if 0 // ATH_WOW + /* SerDes values during WOW sleep */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, + ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); +#endif + + /* Fast clock modal settings */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, + ar9300Modes_fast_clock_jupiter_2p0, + ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3); + INIT_INI_ARRAY(&ahp->ah_ini_japan2484, + ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484, + ARRAY_LENGTH( + ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2); + + } else if (AR_SREV_APHRODITE(ah)) { + /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */ + + /* mac */ + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar956X_aphrodite_1p0_mac_core, + ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], + ar956X_aphrodite_1p0_mac_postamble, + ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5); + + /* bb */ + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], + ar956X_aphrodite_1p0_baseband_core, + ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar956X_aphrodite_1p0_baseband_postamble, + ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5); + +//mark jupiter have but aphrodite don't have +// /* radio */ +// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); +// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], +// ar9300_aphrodite_1p0_radio_core, +// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2); +// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], +// ar9300_aphrodite_1p0_radio_postamble, +// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5); + + /* soc */ + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar956X_aphrodite_1p0_soc_preamble, + ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], + ar956X_aphrodite_1p0_soc_postamble, + ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5); + + /* rx/tx gain */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar956XCommon_rx_gain_table_aphrodite_1p0, + ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2); + //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + // ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0, + // ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0), + // 5); + + + /* + * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and + * 0 for merlin + */ + ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0; + +#if 0 // ATH_WOW + /* SerDes values during WOW sleep */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, + ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); +#endif + /* Fast clock modal settings */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, + ar956XModes_fast_clock_aphrodite_1p0, + ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3); + + } else if (AR_SREV_AR9580(ah)) { + /* + * AR9580/Peacock - + * new INI format (pre, core, post arrays per subsystem) + */ + + /* mac */ + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar9300_ar9580_1p0_mac_core, + ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], + ar9300_ar9580_1p0_mac_postamble, + ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5); + + /* bb */ + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], + ar9300_ar9580_1p0_baseband_core, + ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar9300_ar9580_1p0_baseband_postamble, + ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5); + + /* radio */ + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], + ar9300_ar9580_1p0_radio_core, + ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], + ar9300_ar9580_1p0_radio_postamble, + ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5); + + /* soc */ + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar9300_ar9580_1p0_soc_preamble, + ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], + ar9300_ar9580_1p0_soc_postamble, + ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5); + + /* rx/tx gain */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300_common_rx_gain_table_ar9580_1p0, + ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, + ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5); + + /* DFS */ + INIT_INI_ARRAY(&ahp->ah_ini_dfs, + ar9300_ar9580_1p0_baseband_postamble_dfs_channel, + ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3); + + + /* Load PCIE SERDES settings from INI */ + + /*D3 Setting */ + if (ahpriv->ah_config.ath_hal_pcie_clock_req) { + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_CONTROL) + { //registry control + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D3) + { //bit1, in to D3 + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, + ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), + 2); + } + } else {//no registry control, default is pll on + INIT_INI_ARRAY( + &ahp->ah_ini_pcie_serdes, + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), + 2); + } + } else { + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_CONTROL) + { //registry control + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D3) + { //bit1, in to D3 + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, + ARRAY_LENGTH( + ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), + 2); + } + } else {//no registry control, default is pll on + INIT_INI_ARRAY( + &ahp->ah_ini_pcie_serdes, + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), + 2); + } + } + + /*D0 Setting */ + if (ahpriv->ah_config.ath_hal_pcie_clock_req) { + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_CONTROL) + { //registry control + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D0) + { //bit2, out of D3 + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, + ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), + 2); + + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), + 2); + } + } else { //no registry control, default is pll on + INIT_INI_ARRAY( + &ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), + 2); + } + } else { + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_CONTROL) + {//registry control + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D0) + {//bit2, out of D3 + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, + ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), + 2); + } + } else { //no registry control, default is pll on + INIT_INI_ARRAY( + &ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), + 2); + } + } + + ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0; + +#if 0 /* ATH_WOW */ + /* SerDes values during WOW sleep */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, + ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); +#endif + + /* Fast clock modal settings */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, + ar9300Modes_fast_clock_ar9580_1p0, + ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3); + INIT_INI_ARRAY(&ahp->ah_ini_japan2484, + ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484, + ARRAY_LENGTH( + ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2); + + } else { + /* + * Osprey 2.2 - new INI format (pre, core, post arrays per subsystem) + */ + + /* mac */ + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], + ar9300_osprey_2p2_mac_core, + ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], + ar9300_osprey_2p2_mac_postamble, + ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5); + + /* bb */ + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], + ar9300_osprey_2p2_baseband_core, + ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], + ar9300_osprey_2p2_baseband_postamble, + ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5); + + /* radio */ + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], + ar9300_osprey_2p2_radio_core, + ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2); + INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], + ar9300_osprey_2p2_radio_postamble, + ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5); + + /* soc */ + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], + ar9300_osprey_2p2_soc_preamble, + ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); + INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], + ar9300_osprey_2p2_soc_postamble, + ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5); + + /* rx/tx gain */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300_common_rx_gain_table_osprey_2p2, + ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, + ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5); + + /* DFS */ + INIT_INI_ARRAY(&ahp->ah_ini_dfs, + ar9300_osprey_2p2_baseband_postamble_dfs_channel, + ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3); + + /* Load PCIE SERDES settings from INI */ + + /*D3 Setting */ + if (ahpriv->ah_config.ath_hal_pcie_clock_req) { + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_CONTROL) + { //registry control + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D3) + { //bit1, in to D3 + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300PciePhy_clkreq_enable_L1_osprey_2p2, + ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), + 2); + } + } else {//no registry control, default is pll on +#ifndef ATH_BUS_PM + INIT_INI_ARRAY( + &ahp->ah_ini_pcie_serdes, + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), + 2); +#else + //no registry control, default is pll off + INIT_INI_ARRAY( + &ahp->ah_ini_pcie_serdes, + ar9300PciePhy_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH( + ar9300PciePhy_clkreq_disable_L1_osprey_2p2), + 2); +#endif + + } + } else { + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_CONTROL) + { //registry control + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D3) + { //bit1, in to D3 + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300PciePhy_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH( + ar9300PciePhy_clkreq_disable_L1_osprey_2p2), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), + 2); + } + } else { +#ifndef ATH_BUS_PM + //no registry control, default is pll on + INIT_INI_ARRAY( + &ahp->ah_ini_pcie_serdes, + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), + 2); +#else + //no registry control, default is pll off + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); +#endif + } + } + + /*D0 Setting */ + if (ahpriv->ah_config.ath_hal_pcie_clock_req) { + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_CONTROL) + { //registry control + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D0) + { //bit2, out of D3 + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_clkreq_enable_L1_osprey_2p2, + ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), + 2); + + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), + 2); + } + } else { //no registry control, default is pll on + INIT_INI_ARRAY( + &ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), + 2); + } + } else { + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_CONTROL) + {//registry control + if (ahpriv->ah_config.ath_hal_pll_pwr_save & + AR_PCIE_PLL_PWRSAVE_ON_D0) + {//bit2, out of D3 + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), + 2); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), + 2); + } + } else { //no registry control, default is pll on + INIT_INI_ARRAY( + &ahp->ah_ini_pcie_serdes_low_power, + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, + ARRAY_LENGTH( + ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), + 2); + } + } + + ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0; + +#ifdef ATH_BUS_PM + /*Use HAL to config PCI powersave by writing into the SerDes Registers */ + ahpriv->ah_config.ath_hal_pcie_ser_des_write = 1; +#endif + +#if 0 /* ATH_WOW */ + /* SerDes values during WOW sleep */ + INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, + ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); +#endif + + /* Fast clock modal settings */ + INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, + ar9300Modes_fast_clock_osprey_2p2, + ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3); + INIT_INI_ARRAY(&ahp->ah_ini_japan2484, + ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484, + ARRAY_LENGTH( + ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2); + + } + + if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) + { +#define AR_SOC_RST_OTP_INTF 0xB80600B4 +#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) + + ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF); + if (AR_SREV_SCORPION(ah)) { + ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12; + } + ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode); +#undef REG_READ +#undef AR_SOC_RST_OTP_INTF + } else { + ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP); + } + + + if (ahpriv->ah_is_pci_express) { + ar9300_config_pci_power_save(ah, 0, 0); + } else { + ar9300_disable_pcie_phy(ah); + } + ecode = ar9300_hw_attach(ah); + if (ecode != HAL_OK) { + goto bad; + } + + /* set gain table pointers according to values read from the eeprom */ + ar9300_tx_gain_table_apply(ah); + ar9300_rx_gain_table_apply(ah); + + /* + ** + ** Got everything we need now to setup the capabilities. + */ + + if (!ar9300_fill_capability_info(ah)) { + HALDEBUG(ah, HAL_DEBUG_RESET, + "%s:failed ar9300_fill_capability_info\n", __func__); + ecode = HAL_EEREAD; + goto bad; + } + ecode = ar9300_init_mac_addr(ah); + if (ecode != HAL_OK) { + HALDEBUG(ah, HAL_DEBUG_RESET, + "%s: failed initializing mac address\n", __func__); + goto bad; + } + + /* + * Initialize receive buffer size to MAC default + */ + ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT; + +#if ATH_WOW +#if 0 + /* + * Needs to be removed once we stop using XB92 XXX + * FIXME: Check with latest boards too - SriniK + */ + ar9300_wow_set_gpio_reset_low(ah); +#endif + + /* + * Clear the Wow Status. + */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) | + AR_PMCTRL_WOW_PME_CLR); + OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, + AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG))); +#endif + + /* + * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n + * with aggregation enabled or disabled. + */ + ahpriv->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); + + if (AR_SREV_HORNET(ah)) { + ahpriv->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ; + ahpriv->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; + ahpriv->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; + ahpriv->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; + ahpriv->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; + ahpriv->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; + ahpriv->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; + } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ + ahpriv->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ; + ahpriv->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; + ahpriv->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ; + ahpriv->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ; + ahpriv->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; + ahpriv->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ; + ahpriv->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; + } else { + ahpriv->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ; + ahpriv->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; + ahpriv->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; + if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + ahpriv->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ; + } else { + ahpriv->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; + } + ahpriv->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; + ahpriv->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; + ahpriv->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; + } + + + + + /* init BB Panic Watchdog timeout */ + if (AR_SREV_HORNET(ah)) { + ahpriv->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET; + } else { + ahpriv->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO; + } + + + /* + * Determine whether tx IQ calibration HW should be enabled, + * and whether tx IQ calibration should be performed during + * AGC calibration, or separately. + */ + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + /* + * Register not initialized yet. This flag will be re-initialized + * after INI loading following each reset. + */ + ahp->tx_iq_cal_enable = 1; + /* if tx IQ cal is enabled, do it together with AGC cal */ + ahp->tx_iq_cal_during_agc_cal = 1; + } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) { + ahp->tx_iq_cal_enable = 1; + ahp->tx_iq_cal_during_agc_cal = 1; + } else { + /* osprey, hornet, wasp */ + ahp->tx_iq_cal_enable = 1; + ahp->tx_iq_cal_during_agc_cal = 0; + } + return ah; + +bad: + if (ahp) { + ar9300_detach((struct ath_hal *) ahp); + } + if (status) { + *status = ecode; + } + return AH_NULL; +} + +void +ar9300_detach(struct ath_hal *ah) +{ + HALASSERT(ah != AH_NULL); + HALASSERT(AH_PRIVATE(ah)->ah_magic == AR9300_MAGIC); + + /* Make sure that chip is awake before writing to it */ + if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: failed to wake up chip\n", + __func__); + } + + ar9300_hw_detach(ah); + ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); + + ath_hal_hdprintf_deregister(ah); + ath_hal_free(ah, ah); +} + +struct ath_hal_9300 * +ar9300_new_state(u_int16_t devid, HAL_ADAPTER_HANDLE osdev, HAL_SOFTC sc, + HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_BUS_TYPE bustype, + asf_amem_instance_handle amem_handle, + struct hal_reg_parm *hal_conf_parm, HAL_STATUS *status) +{ + static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] = + { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + struct ath_hal_9300 *ahp; + struct ath_hal *ah; + + /* NB: memory is returned zero'd */ + ahp = amalloc_adv( + amem_handle, sizeof(struct ath_hal_9300), adf_os_mem_zero_outline); + if (ahp == AH_NULL) { + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "%s: cannot allocate memory for state block\n", + __func__); + *status = HAL_ENOMEM; + return AH_NULL; + } + + ah = &ahp->ah_priv.priv.h; + /* set initial values */ + + /* Attach Osprey structure as default hal structure */ + OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv)); + + AH_PRIVATE(ah)->amem_handle = amem_handle; + AH_PRIVATE(ah)->ah_osdev = osdev; + AH_PRIVATE(ah)->ah_sc = sc; + AH_PRIVATE(ah)->ah_st = st; + AH_PRIVATE(ah)->ah_sh = sh; + + AH_PRIVATE(ah)->ah_magic = AR9300_MAGIC; + AH_PRIVATE(ah)->ah_devid = devid; + + AH_PRIVATE(ah)->ah_flags = 0; + + /* + ** Initialize factory defaults in the private space + */ + ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm); + + if (!hal_conf_parm->calInFlash) { + AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; + } + +#if 0 + if (ar9300_eep_data_in_flash(ah)) { + ahp->ah_priv.priv.ah_eeprom_read = ar9300_flash_read; + ahp->ah_priv.priv.ah_eeprom_dump = AH_NULL; + } else { + ahp->ah_priv.priv.ah_eeprom_read = ar9300_eeprom_read_word; + } +#endif + + AH_PRIVATE(ah)->ah_power_limit = MAX_RATE_POWER; + AH_PRIVATE(ah)->ah_tp_scale = HAL_TP_SCALE_MAX; /* no scaling */ + + ahp->ah_atim_window = 0; /* [0..1000] */ + ahp->ah_diversity_control = + AH_PRIVATE(ah)->ah_config.ath_hal_diversity_control; + ahp->ah_antenna_switch_swap = + AH_PRIVATE(ah)->ah_config.ath_hal_antenna_switch_swap; + + /* + * Enable MIC handling. + */ + ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; + ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */ + ahp->ah_slot_time = (u_int) -1; + ahp->ah_ack_timeout = (u_int) -1; + OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN); + + /* + * 11g-specific stuff + */ + ahp->ah_g_beacon_rate = 0; /* adhoc beacon fixed rate */ + + /* SM power mode: Attach time, disable any setting */ + ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT; + + return ahp; +} + +HAL_BOOL +ar9300_chip_test(struct ath_hal *ah) +{ + /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/ + u_int32_t reg_addr[2] = { AR_STA_ID0 }; + u_int32_t reg_hold[2]; + u_int32_t pattern_data[4] = + { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; + int i, j; + + + /* Test PHY & MAC registers */ + for (i = 0; i < 1; i++) { + u_int32_t addr = reg_addr[i]; + u_int32_t wr_data, rd_data; + + reg_hold[i] = OS_REG_READ(ah, addr); + for (j = 0; j < 0x100; j++) { + wr_data = (j << 16) | j; + OS_REG_WRITE(ah, addr, wr_data); + rd_data = OS_REG_READ(ah, addr); + if (rd_data != wr_data) { + HALDEBUG(ah, HAL_DEBUG_REG_IO, + "%s: address test failed addr: " + "0x%08x - wr:0x%08x != rd:0x%08x\n", + __func__, addr, wr_data, rd_data); + return AH_FALSE; + } + } + for (j = 0; j < 4; j++) { + wr_data = pattern_data[j]; + OS_REG_WRITE(ah, addr, wr_data); + rd_data = OS_REG_READ(ah, addr); + if (wr_data != rd_data) { + HALDEBUG(ah, HAL_DEBUG_REG_IO, + "%s: address test failed addr: " + "0x%08x - wr:0x%08x != rd:0x%08x\n", + __func__, addr, wr_data, rd_data); + return AH_FALSE; + } + } + OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]); + } + OS_DELAY(100); + return AH_TRUE; +} + +/* + * Store the channel edges for the requested operational mode + */ +HAL_BOOL +ar9300_get_channel_edges(struct ath_hal *ah, + u_int16_t flags, u_int16_t *low, u_int16_t *high) +{ + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; + + if (flags & CHANNEL_5GHZ) { + *low = p_cap->hal_low_5ghz_chan; + *high = p_cap->hal_high_5ghz_chan; + return AH_TRUE; + } + if ((flags & CHANNEL_2GHZ)) { + *low = p_cap->hal_low_2ghz_chan; + *high = p_cap->hal_high_2ghz_chan; + + return AH_TRUE; + } + return AH_FALSE; +} + +HAL_BOOL +ar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn) +{ + AH_PRIVATE(ah)->ah_current_rd = regdmn; + return AH_TRUE; +} + +/* + * Fill all software cached or static hardware state information. + * Return failure if capabilities are to come from EEPROM and + * cannot be read. + */ +HAL_BOOL +ar9300_fill_capability_info(struct ath_hal *ah) +{ +#define AR_KEYTABLE_SIZE 128 + struct ath_hal_9300 *ahp = AH9300(ah); + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; + u_int16_t cap_field = 0, eeval; + + ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE); + eeval = ar9300_eeprom_get(ahp, EEP_REG_0); + + /* XXX record serial number */ + AH_PRIVATE(ah)->ah_current_rd = eeval; + + p_cap->halintr_mitigation = AH_TRUE; + eeval = ar9300_eeprom_get(ahp, EEP_REG_1); + AH_PRIVATE(ah)->ah_current_rd_ext = eeval | AR9300_RDEXT_DEFAULT; + + /* Read the capability EEPROM location */ + cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP); + + /* Construct wireless mode from EEPROM */ + p_cap->hal_wireless_modes = 0; + eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE); + + if (eeval & AR9300_OPFLAGS_11A) { + p_cap->hal_wireless_modes |= HAL_MODE_11A | + ((!ahpriv->ah_config.ath_hal_ht_enable || + (eeval & AR9300_OPFLAGS_N_5G_HT20)) ? 0 : + (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 : + (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)))); + } + if (eeval & AR9300_OPFLAGS_11G) { + p_cap->hal_wireless_modes |= HAL_MODE_11B | HAL_MODE_11G | + ((!ahpriv->ah_config.ath_hal_ht_enable || + (eeval & AR9300_OPFLAGS_N_2G_HT20)) ? 0 : + (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 : + (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS)))); + } + + /* Get chainamsks from eeprom */ + p_cap->hal_tx_chain_mask = ar9300_eeprom_get(ahp, EEP_TX_MASK); + p_cap->hal_rx_chain_mask = ar9300_eeprom_get(ahp, EEP_RX_MASK); + + + /* + * This being a newer chip supports TKIP non-splitmic mode. + * + */ + ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; + + + p_cap->hal_low_2ghz_chan = 2312; + p_cap->hal_high_2ghz_chan = 2732; + + p_cap->hal_low_5ghz_chan = 4920; + p_cap->hal_high_5ghz_chan = 6100; + + p_cap->hal_cipher_ckip_support = AH_FALSE; + p_cap->hal_cipher_tkip_support = AH_TRUE; + p_cap->hal_cipher_aes_ccm_support = AH_TRUE; + + p_cap->hal_mic_ckip_support = AH_FALSE; + p_cap->hal_mic_tkip_support = AH_TRUE; + p_cap->hal_mic_aes_ccm_support = AH_TRUE; + + p_cap->hal_chan_spread_support = AH_TRUE; + p_cap->hal_sleep_after_beacon_broken = AH_TRUE; + + p_cap->hal_burst_support = AH_TRUE; + p_cap->hal_chap_tuning_support = AH_TRUE; + p_cap->hal_turbo_prime_support = AH_TRUE; + p_cap->hal_fast_frames_support = AH_FALSE; + + p_cap->hal_turbo_g_support = p_cap->hal_wireless_modes & HAL_MODE_108G; + + p_cap->hal_xr_support = AH_FALSE; + + p_cap->hal_ht_support = + ahpriv->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE; + p_cap->hal_gtt_support = AH_TRUE; + p_cap->hal_ps_poll_broken = AH_TRUE; /* XXX fixed in later revs? */ + p_cap->hal_ht20_sgi_support = AH_TRUE; + p_cap->hal_veol_support = AH_TRUE; + p_cap->hal_bss_id_mask_support = AH_TRUE; + /* Bug 26802, fixed in later revs? */ + p_cap->hal_mcast_key_srch_support = AH_TRUE; + p_cap->hal_tsf_add_support = AH_TRUE; + + if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) { + p_cap->hal_total_queues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU); + } else { + p_cap->hal_total_queues = HAL_NUM_TX_QUEUES; + } + + if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) { + p_cap->hal_key_cache_size = + 1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES); + } else { + p_cap->hal_key_cache_size = AR_KEYTABLE_SIZE; + } + p_cap->hal_fast_cc_support = AH_TRUE; + p_cap->hal_num_mr_retries = 4; + p_cap->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD; + + p_cap->hal_num_gpio_pins = AR9382_MAX_GPIO_PIN_NUM; + +#if 0 + /* XXX Verify support in Osprey */ + if (AR_SREV_MERLIN_10_OR_LATER(ah)) { + p_cap->hal_wow_support = AH_TRUE; + p_cap->hal_wow_match_pattern_exact = AH_TRUE; + if (AR_SREV_MERLIN(ah)) { + p_cap->hal_wow_pattern_match_dword = AH_TRUE; + } + } else { + p_cap->hal_wow_support = AH_FALSE; + p_cap->hal_wow_match_pattern_exact = AH_FALSE; + } +#endif + p_cap->hal_wow_support = AH_TRUE; + p_cap->hal_wow_match_pattern_exact = AH_TRUE; + if (AR_SREV_POSEIDON(ah)) { + p_cap->hal_wow_match_pattern_exact = AH_TRUE; + } + + p_cap->hal_cst_support = AH_TRUE; + + p_cap->hal_rifs_rx_support = AH_TRUE; + p_cap->hal_rifs_tx_support = AH_TRUE; + + p_cap->hal_rts_aggr_limit = IEEE80211_AMPDU_LIMIT_MAX; + + p_cap->hal_mfp_support = ahpriv->ah_config.ath_hal_mfp_support; + + p_cap->halforce_ppm_support = AH_TRUE; + p_cap->hal_hw_beacon_proc_support = AH_TRUE; + + /* ar9300 - has the HW UAPSD trigger support, + * but it has the following limitations + * The power state change from the following + * frames are not put in High priority queue. + * i) Mgmt frames + * ii) NoN QoS frames + * iii) QoS frames form the access categories for which + * UAPSD is not enabled. + * so we can not enable this feature currently. + * could be enabled, if these limitations are fixed + * in later versions of ar9300 chips + */ + p_cap->hal_hw_uapsd_trig = AH_FALSE; + + /* Number of buffers that can be help in a single TxD */ + p_cap->hal_num_tx_maps = 4; + + p_cap->hal_tx_desc_len = sizeof(struct ar9300_txc); + p_cap->hal_tx_status_len = sizeof(struct ar9300_txs); + p_cap->hal_rx_status_len = sizeof(struct ar9300_rxs); + + p_cap->hal_rx_hp_depth = HAL_HP_RXFIFO_DEPTH; + p_cap->hal_rx_lp_depth = HAL_LP_RXFIFO_DEPTH; + + /* Enable extension channel DFS support */ + p_cap->hal_use_combined_radar_rssi = AH_TRUE; + p_cap->hal_ext_chan_dfs_support = AH_TRUE; +#if ATH_SUPPORT_SPECTRAL + p_cap->hal_spectral_scan = AH_TRUE; +#endif + + ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT); + if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) { + ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); + ahp->ah_polarity = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY); + + ath_hal_enable_rfkill(ah, AH_TRUE); + p_cap->hal_rf_silent_support = AH_TRUE; + } + + /* XXX */ + p_cap->hal_wps_push_button = AH_FALSE; + +#ifdef ATH_BT_COEX + p_cap->hal_bt_coex_support = AH_TRUE; + p_cap->hal_bt_coex_aspm_war = AH_FALSE; +#endif + + p_cap->hal_gen_timer_support = AH_TRUE; + ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1); + ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1; + /* + * According to Kyungwan, generic timer 0 and 8 are special + * timers. Remove timer 8 from the available gen timer list. + * Jupiter testing shows timer won't trigger with timer 8. + */ + ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED); + + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { +#if ATH_SUPPORT_MCI + if (ahpriv->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI) + { + p_cap->hal_mci_support = AH_FALSE; + } + else +#endif + { + p_cap->hal_mci_support = (ahp->ah_enterprise_mode & + AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE : AH_TRUE; + } + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "%s: (MCI) MCI support = %d\n", + __func__, p_cap->hal_mci_support); + } + else { + p_cap->hal_mci_support = AH_FALSE; + } + + if (AR_SREV_JUPITER_20(ah)) { + p_cap->hal_radio_retention_support = AH_TRUE; + } else { + p_cap->hal_radio_retention_support = AH_FALSE; + } + + p_cap->hal_auto_sleep_support = AH_TRUE; + + p_cap->hal_mbssid_aggr_support = AH_TRUE; + p_cap->hal_proxy_sta_support = AH_TRUE; + + /* XXX Mark it AH_TRUE after it is verfied as fixed */ + p_cap->hal4kb_split_trans_support = AH_FALSE; + + /* Read regulatory domain flag */ + if (AH_PRIVATE(ah)->ah_current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { + /* + * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND. + */ + p_cap->hal_reg_cap = + AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | + AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | + AR_EEPROM_EEREGCAP_EN_KK_U2 | + AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; + } else { + p_cap->hal_reg_cap = + AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; + } + + /* For AR9300 and above, midband channels are always supported */ + p_cap->hal_reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; + + p_cap->hal_num_ant_cfg_5ghz = + ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ); + p_cap->hal_num_ant_cfg_2ghz = + ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ); + + /* STBC supported */ + p_cap->hal_rx_stbc_support = 1; /* number of streams for STBC recieve. */ + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { + p_cap->hal_tx_stbc_support = 0; + } else { + p_cap->hal_tx_stbc_support = 1; + } + + p_cap->hal_enhanced_dma_support = AH_TRUE; +#ifdef ATH_SUPPORT_DFS + p_cap->hal_enhanced_dfs_support = AH_TRUE; +#endif + + /* + * EV61133 (missing interrupts due to AR_ISR_RAC). + * Fixed in Osprey 2.0. + */ + p_cap->hal_isr_rac_support = AH_TRUE; + + p_cap->hal_wep_tkip_aggr_support = AH_TRUE; + p_cap->hal_wep_tkip_aggr_num_tx_delim = 10; /* TBD */ + p_cap->hal_wep_tkip_aggr_num_rx_delim = 10; /* TBD */ + p_cap->hal_wep_tkip_max_ht_rate = 15; /* TBD */ + p_cap->hal_cfend_fix_support = AH_FALSE; + p_cap->hal_aggr_extra_delim_war = AH_FALSE; + p_cap->hal_rx_desc_timestamp_bits = 32; + p_cap->hal_rx_tx_abort_support = AH_TRUE; + p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL; + p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC; + + /* Transmit Beamforming supported, fill capabilities */ + p_cap->hal_paprd_enabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED); + p_cap->hal_chan_half_rate = + !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE); + p_cap->hal_chan_quarter_rate = + !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE); + + if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ + /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */ + p_cap->hal49Ghz = 1; + } else { + p_cap->hal49Ghz = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE); + } + + if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) { + /* LDPC supported */ + /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */ + p_cap->hal_ldpc_support = AH_FALSE; + /* PCI_E LCR offset */ + if (AR_SREV_POSEIDON(ah)) { + p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/ + } + /*WAR method for APSM L0s with Poseidon 1.0*/ + if (AR_SREV_POSEIDON_10(ah)) { + p_cap->hal_pcie_lcr_extsync_en = AH_TRUE; + } + } else { + p_cap->hal_ldpc_support = AH_TRUE; + } + + p_cap->hal_enable_apm = ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE); +#if ATH_ANT_DIV_COMB + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { + if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) { + u_int8_t ant_div_control1 = + ar9300_eeprom_get(ahp, EEP_ANTDIV_control); + /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1, + * we enable the diversity-combining algorithm. + */ + if ((ant_div_control1 >> 0x6) == 0x3) { + p_cap->hal_ant_div_comb_support = AH_TRUE; + } + p_cap->hal_ant_div_comb_support_org = p_cap->hal_ant_div_comb_support; + } + } +#endif /* ATH_ANT_DIV_COMB */ + + +#if ATH_WOW_OFFLOAD + if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { + p_cap->hal_wow_gtk_offload_support = AH_TRUE; + p_cap->hal_wow_arp_offload_support = AH_TRUE; + p_cap->hal_wow_ns_offload_support = AH_TRUE; + p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE; + p_cap->hal_wow_acer_magic_support = AH_TRUE; + p_cap->hal_wow_acer_swka_support = AH_TRUE; + } else { + p_cap->hal_wow_gtk_offload_support = AH_FALSE; + p_cap->hal_wow_arp_offload_support = AH_FALSE; + p_cap->hal_wow_ns_offload_support = AH_FALSE; + p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE; + p_cap->hal_wow_acer_magic_support = AH_FALSE; + p_cap->hal_wow_acer_swka_support = AH_FALSE; + } +#endif /* ATH_WOW_OFFLOAD */ + + + return AH_TRUE; +#undef AR_KEYTABLE_SIZE +} + +static HAL_BOOL +ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, + u_int32_t nchans) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans); +} + +/* + * Disable PLL when in L0s as well as receiver clock when in L1. + * This power saving option must be enabled through the Serdes. + * + * Programming the Serdes must go through the same 288 bit serial shift + * register as the other analog registers. Hence the 9 writes. + * + * XXX Clean up the magic numbers. + */ +void +ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int i; + + if (AH_PRIVATE(ah)->ah_is_pci_express != AH_TRUE) { + return; + } + + /* + * Increase L1 Entry Latency. Some WB222 boards don't have + * this change in eeprom/OTP. + */ + if (AR_SREV_JUPITER(ah)) { + u_int32_t val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c; + if ((val & 0xff000000) == 0x17000000) { + val &= 0x00ffffff; + val |= 0x27000000; + OS_REG_WRITE(ah, 0x570c, val); + } + } + + /* Do not touch SERDES registers */ + if (AH_PRIVATE(ah)->ah_config.ath_hal_pcie_power_save_enable == 2) { + return; + } + + /* Nothing to do on restore for 11N */ + if (!restore) { + /* set bit 19 to allow forcing of pcie core into L1 state */ + OS_REG_SET_BIT(ah, + AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA); + + /* + * Set PCIE workaround config only if requested, else use the reset + * value of this register. + */ + if (AH_PRIVATE(ah)->ah_config.ath_hal_pcie_waen) { + OS_REG_WRITE(ah, + AR_HOSTIF_REG(ah, AR_WA), + AH_PRIVATE(ah)->ah_config.ath_hal_pcie_waen); + } else { + /* Set Bits 17 and 14 in the AR_WA register. */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); + } + } + + /* Configure PCIE after Ini init. SERDES values now come from ini file */ + if (AH_PRIVATE(ah)->ah_config.ath_hal_pcie_ser_des_write) { + if (power_off) { + for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) { + OS_REG_WRITE(ah, + INI_RA(&ahp->ah_ini_pcie_serdes, i, 0), + INI_RA(&ahp->ah_ini_pcie_serdes, i, 1)); + } + } else { + for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) { + OS_REG_WRITE(ah, + INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0), + INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1)); + } + } + } + +} + +/* + * Recipe from charles to turn off PCIe PHY in PCI mode for power savings + */ +void +ar9300_disable_pcie_phy(struct ath_hal *ah) +{ + /* Osprey does not support PCI mode */ +} + +static inline HAL_STATUS +ar9300_init_mac_addr(struct ath_hal *ah) +{ + u_int32_t sum; + int i; + u_int16_t eeval; + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; + + sum = 0; + for (i = 0; i < 3; i++) { + eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]); + sum += eeval; + ahp->ah_macaddr[2*i] = eeval >> 8; + ahp->ah_macaddr[2*i + 1] = eeval & 0xff; + } + if (sum == 0 || sum == 0xffff*3) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n", + __func__, ath_hal_ether_sprintf(ahp->ah_macaddr)); + return HAL_EEBADMAC; + } + + return HAL_OK; +} + +/* + * Code for the "real" chip i.e. non-emulation. Review and revisit + * when actual hardware is at hand. + */ +static inline HAL_STATUS +ar9300_hw_attach(struct ath_hal *ah) +{ + HAL_STATUS ecode; + + if (!ar9300_chip_test(ah)) { + HALDEBUG(ah, HAL_DEBUG_REG_IO, + "%s: hardware self-test failed\n", __func__); + return HAL_ESELFTEST; + } + + ecode = ar9300_eeprom_attach(ah); + if (ecode != HAL_OK) { + return ecode; + } + if (!ar9300_rf_attach(ah, &ecode)) { + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n", + __func__, ecode); + } + + if (ecode != HAL_OK) { + return ecode; + } + ar9300_ani_attach(ah); + + return HAL_OK; +} + +static inline void +ar9300_hw_detach(struct ath_hal *ah) +{ + /* XXX EEPROM allocated state */ + ar9300_ani_detach(ah); +} + +static int16_t +ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) +{ + return 0; +} + + +void +ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0], + m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1], + m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2], + m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3], + m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4], + m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5]; + + if (ahp->ah_immunity_on == enable) { + return; + } + + ahp->ah_immunity_on = enable; + + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, + AR_PHY_SFCORR_M1_THRESH, m1_thresh); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, + AR_PHY_SFCORR_M2_THRESH, m2_thresh); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, + AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low); + + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, + AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, + AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, + AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh); + OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, + AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh); + + if (!enable) { + OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); + } else { + OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); + } +} + +int +ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, + HAL_CAL_QUERY query) +{ +#define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \ + ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0) +#define AR9300_IS_RX_IQCAL_DISABLED(_ah) \ + (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \ + AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE)) +/* Avoid comilation warnings. Variables are not used when EMULATION. */ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int8_t rxchainmask = ahp->ah_rx_chainmask, i; + int rx_iqcal_invalid = 0, num_chains = 0; + static const u_int32_t offset_array[3] = { + AR_PHY_RX_IQCAL_CORR_B0, + AR_PHY_RX_IQCAL_CORR_B1, + AR_PHY_RX_IQCAL_CORR_B2}; + + *timerp = ar9300_cals; + + switch (query) { + case HAL_QUERY_CALS: + return AR9300_NUM_CAL_TYPES; + case HAL_QUERY_RERUN_CALS: + for (i = 0; i < AR9300_MAX_CHAINS; i++) { + if (rxchainmask & (1 << i)) { + num_chains++; + } + } + for (i = 0; i < num_chains; i++) { + if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { + HALASSERT(num_chains == 0x1); + } + if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) { + rx_iqcal_invalid = 1; + } + } + if (AR9300_IS_RX_IQCAL_DISABLED(ah)) { + rx_iqcal_invalid = 1; + } + + return rx_iqcal_invalid; + default: + HALASSERT(0); + } + return 0; +} + +#if ATH_TRAFFIC_FAST_RECOVER +#define PLL3 0x16188 +#define PLL3_DO_MEAS_MASK 0x40000000 +#define PLL4 0x1618c +#define PLL4_MEAS_DONE 0x8 +#define SQSUM_DVC_MASK 0x007ffff8 +unsigned long +ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah) +{ + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); + OS_DELAY(100); + OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); + + while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { + OS_DELAY(100); + } + + return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3); + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: unable to get pll3_sqsum_dvc\n", + __func__); + return 0; + } +} +#endif + + +#define RX_GAIN_TABLE_LENGTH 128 +// this will be called if rfGainCAP is enabled and rfGainCAP setting is changed, +// or rxGainTable setting is changed +HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz) +{ + int i, done = 0, i_rx_gain = 32; + u_int32_t rf_gain_cap; + u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped; + static u_int32_t rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2]; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + struct ath_hal_9300 *ahp = AH9300(ah); + + if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) ) + return AH_FALSE; + + if (is_2GHz) + { + rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap; + } + else + { + rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap; + } + + if (rf_gain_cap == 0) + return AH_FALSE; + + for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++) + { + if (AR_SREV_AR9580(ah)) + { + // BB_rx_ocgain2 + i_rx_gain = 128 + 32; + switch (ar9300_rx_gain_index_get(ah)) + { + case 0: + rx_gain_table[i][0] = + ar9300_common_rx_gain_table_ar9580_1p0[i][0]; + rx_gain_table[i][1] = + ar9300_common_rx_gain_table_ar9580_1p0[i][1]; + break; + case 1: + rx_gain_table[i][0] = + ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0]; + rx_gain_table[i][1] = + ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1]; + break; + } + } + else if (AR_SREV_OSPREY_22(ah)) + { + i_rx_gain = 128 + 32; + switch (ar9300_rx_gain_index_get(ah)) + { + case 0: + rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0]; + rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1]; + break; + case 1: + rx_gain_table[i][0] = + ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0]; + rx_gain_table[i][1] = + ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1]; + break; + } + } + else + { + return AH_FALSE; + } + } + + while (1) + { + rx_gain_value = rx_gain_table[i_rx_gain][1]; + rx_gain_value_caped = rx_gain_value; + a_Byte = rx_gain_value & (0x000000FF); + if (a_Byte>rf_gain_cap) + { + rx_gain_value_caped = (rx_gain_value_caped & + (0xFFFFFF00)) + rf_gain_cap; + } + a_Byte = rx_gain_value & (0x0000FF00); + if ( a_Byte > ( rf_gain_cap << 8 ) ) + { + rx_gain_value_caped = (rx_gain_value_caped & + (0xFFFF00FF)) + (rf_gain_cap<<8); + } + a_Byte = rx_gain_value & (0x00FF0000); + if ( a_Byte > ( rf_gain_cap << 16 ) ) + { + rx_gain_value_caped = (rx_gain_value_caped & + (0xFF00FFFF)) + (rf_gain_cap<<16); + } + a_Byte = rx_gain_value & (0xFF000000); + if ( a_Byte > ( rf_gain_cap << 24 ) ) + { + rx_gain_value_caped = (rx_gain_value_caped & + (0x00FFFFFF)) + (rf_gain_cap<<24); + } + else + { + done = 1; + } + HALDEBUG(ah, HAL_DEBUG_RESET, + "%s: rx_gain_address: %x, rx_gain_value: %x rx_gain_value_caped: %x\n", + __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped); + if (rx_gain_value_caped != rx_gain_value) + { + rx_gain_table[i_rx_gain][1] = rx_gain_value_caped; + } + if (done == 1) + break; + i_rx_gain ++; + } + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2); + return AH_TRUE; +} + + +void ar9300_rx_gain_table_apply(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + u_int32_t xlan_gpio_cfg; + u_int8_t i; + + if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah)) + { + // this will be called if rxGainTable setting is changed + if (ar9300_rf_gain_cap_apply(ah, 1)) + return; + } + + switch (ar9300_rx_gain_index_get(ah)) + { + case 2: + if (AR_SREV_JUPITER_10(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300_common_mixed_rx_gain_table_jupiter_1p0, + ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2); + break; + } + else if (AR_SREV_JUPITER_20(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300Common_mixed_rx_gain_table_jupiter_2p0, + ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2); + break; + } + case 0: + default: + if (AR_SREV_HORNET_12(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9331_common_rx_gain_hornet1_2, + ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); + } else if (AR_SREV_HORNET_11(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9331_common_rx_gain_hornet1_1, + ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); + } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9485_common_wo_xlna_rx_gain_poseidon1_1, + ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); + xlan_gpio_cfg = ahpriv->ah_config.ath_hal_ext_lna_ctl_gpio; + if (xlan_gpio_cfg) { + for (i = 0; i < 32; i++) { + if (xlan_gpio_cfg & (1 << i)) { + ath_hal_gpio_cfg_output(ah, i, + HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED); + } + } + } + + } else if (AR_SREV_POSEIDON(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9485Common_wo_xlna_rx_gain_poseidon1_0, + ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); + } else if (AR_SREV_JUPITER_10(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300_common_rx_gain_table_jupiter_1p0, + ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); + } else if (AR_SREV_JUPITER_20(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300Common_rx_gain_table_jupiter_2p0, + ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); + } else if (AR_SREV_AR9580(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300_common_rx_gain_table_ar9580_1p0, + ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); + } else if (AR_SREV_WASP(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9340Common_rx_gain_table_wasp_1p0, + ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2); + } else if (AR_SREV_SCORPION(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar955xCommon_rx_gain_table_scorpion_1p0, + ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2); + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, + ar955xCommon_rx_gain_bounds_scorpion_1p0, + ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300_common_rx_gain_table_osprey_2p2, + ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); + } + break; + case 1: + if (AR_SREV_HORNET_12(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9331_common_wo_xlna_rx_gain_hornet1_2, + ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2); + } else if (AR_SREV_HORNET_11(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9331_common_wo_xlna_rx_gain_hornet1_1, + ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2); + } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9485_common_wo_xlna_rx_gain_poseidon1_1, + ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); + } else if (AR_SREV_POSEIDON(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9485Common_wo_xlna_rx_gain_poseidon1_0, + ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); + } else if (AR_SREV_JUPITER_10(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0, + ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0), + 2); + } else if (AR_SREV_JUPITER_20(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0, + ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0), + 2); + } else if (AR_SREV_APHRODITE(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0, + ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0), + 2); + } else if (AR_SREV_AR9580(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0, + ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2); + } else if (AR_SREV_WASP(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, + ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); + } else if (AR_SREV_SCORPION(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, + ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, + ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, + ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, + ar9300Common_wo_xlna_rx_gain_table_osprey_2p2, + ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2); + } + break; + } +} + +void ar9300_tx_gain_table_apply(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + switch (ar9300_tx_gain_index_get(ah)) + { + case 0: + default: + if (AR_SREV_HORNET_12(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, + ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); + } else if (AR_SREV_HORNET_11(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, + ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); + } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, + ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); + } else if (AR_SREV_POSEIDON(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, + ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); + } else if (AR_SREV_AR9580(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, + ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), + 5); + } else if (AR_SREV_WASP(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0, + ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0), + 5); + } else if (AR_SREV_SCORPION(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar955xModes_xpa_tx_gain_table_scorpion_1p0, + ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0), + 9); + } else if (AR_SREV_JUPITER_10(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0, + ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0), + 5); + } else if (AR_SREV_JUPITER_20(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0, + ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0), + 5); + } else if (AR_SREV_APHRODITE(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, + ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), + 5); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, + ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), + 5); + } + break; + case 1: + if (AR_SREV_HORNET_12(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9331_modes_high_ob_db_tx_gain_hornet1_2, + ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5); + } else if (AR_SREV_HORNET_11(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9331_modes_high_ob_db_tx_gain_hornet1_1, + ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5); + } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485_modes_high_ob_db_tx_gain_poseidon1_1, + ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5); + } else if (AR_SREV_POSEIDON(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485Modes_high_ob_db_tx_gain_poseidon1_0, + ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5); + } else if (AR_SREV_AR9580(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0, + ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0), + 5); + } else if (AR_SREV_WASP(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, + ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); + } else if (AR_SREV_SCORPION(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, + ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9); + } else if (AR_SREV_JUPITER_10(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0, + ARRAY_LENGTH( + ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5); + } else if (AR_SREV_JUPITER_20(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0, + ARRAY_LENGTH( + ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5); + } else if (AR_SREV_APHRODITE(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0, + ARRAY_LENGTH( + ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2, + ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2), + 5); + } + break; + case 2: + if (AR_SREV_HORNET_12(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9331_modes_low_ob_db_tx_gain_hornet1_2, + ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5); + } else if (AR_SREV_HORNET_11(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9331_modes_low_ob_db_tx_gain_hornet1_1, + ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5); + } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485_modes_low_ob_db_tx_gain_poseidon1_1, + ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5); + } else if (AR_SREV_POSEIDON(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485Modes_low_ob_db_tx_gain_poseidon1_0, + ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5); + } else if (AR_SREV_AR9580(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0, + ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0), + 5); + } else if (AR_SREV_WASP(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0, + ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5); + } else if (AR_SREV_APHRODITE(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, + ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2, + ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2), + 5); + } + break; + case 3: + if (AR_SREV_HORNET_12(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9331_modes_high_power_tx_gain_hornet1_2, + ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5); + } else if (AR_SREV_HORNET_11(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9331_modes_high_power_tx_gain_hornet1_1, + ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5); + } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485_modes_high_power_tx_gain_poseidon1_1, + ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5); + } else if (AR_SREV_POSEIDON(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485Modes_high_power_tx_gain_poseidon1_0, + ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5); + } else if (AR_SREV_AR9580(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300Modes_high_power_tx_gain_table_ar9580_1p0, + ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0), + 5); + } else if (AR_SREV_WASP(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9340Modes_high_power_tx_gain_table_wasp_1p0, + ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0), + 5); + } else if (AR_SREV_APHRODITE(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar956XModes_high_power_tx_gain_table_aphrodite_1p0, + ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300Modes_high_power_tx_gain_table_osprey_2p2, + ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2), + 5); + } + break; + case 4: + if (AR_SREV_WASP(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0, + ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0), + 5); + } else if (AR_SREV_AR9580(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0, + ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0), + 5); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2, + ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2), + 5); + } + break; + case 5: + /* HW Green TX */ + if (AR_SREV_POSEIDON(ah)) { + if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485_modes_green_ob_db_tx_gain_poseidon1_1, + sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) / + sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5); + } else { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485_modes_green_ob_db_tx_gain_poseidon1_0, + sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) / + sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5); + } + ahp->ah_hw_green_tx_enable = 1; + } + else if (AR_SREV_WASP(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9340_modes_ub124_tx_gain_table_wasp_1p0, + sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) / + sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5); + } + else if (AR_SREV_AR9580(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300_modes_type5_tx_gain_table_ar9580_1p0, + ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0), + 5); + } + else if (AR_SREV_OSPREY_22(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300_modes_number_5_tx_gain_table_osprey_2p2, + ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2), + 5); + } + break; + case 6: + if (AR_SREV_WASP(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0, + sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) / + sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5); + } + /* HW Green TX */ + else if (AR_SREV_POSEIDON(ah)) { + if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1, + sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) / + sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]), + 5); + } + ahp->ah_hw_green_tx_enable = 1; + } + else if (AR_SREV_AR9580(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9300_modes_type6_tx_gain_table_ar9580_1p0, + ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0), + 5); + } + break; + case 7: + if (AR_SREV_WASP(ah)) { + INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, + ar9340Modes_cus227_tx_gain_table_wasp_1p0, + sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) / + sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5); + } + break; + } +} + +#if ATH_ANT_DIV_COMB +void +ar9300_ant_div_comb_get_config(struct ath_hal *ah, + HAL_ANT_COMB_CONFIG *div_comb_conf) +{ + u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); + div_comb_conf->main_lna_conf = + MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val); + div_comb_conf->alt_lna_conf = + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val); + div_comb_conf->fast_div_bias = + MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val); + if (AR_SREV_HORNET_11(ah)) { + div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1; + } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { + div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2; + } else { + div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP; + } +} + +void +ar9300_ant_div_comb_set_config(struct ath_hal *ah, + HAL_ANT_COMB_CONFIG *div_comb_conf) +{ + u_int32_t reg_val; + struct ath_hal_9300 *ahp = AH9300(ah); + + /* DO NOTHING when set to fixed antenna for manufacturing purpose */ + if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A + || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) { + return; + } + reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); + reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | + MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK ); + reg_val |= + MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE( + div_comb_conf->main_gaintb); + reg_val |= + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE( + div_comb_conf->alt_gaintb); + reg_val |= + MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE( + div_comb_conf->main_lna_conf); + reg_val |= + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE( + div_comb_conf->alt_lna_conf); + reg_val |= + MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE( + div_comb_conf->fast_div_bias); + OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); + +} +#endif /* ATH_ANT_DIV_COMB */ + +static void +ar9300_init_hostif_offsets(struct ath_hal *ah) +{ + AR_HOSTIF_REG(ah, AR_RC) = + AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); + AR_HOSTIF_REG(ah, AR_WA) = + AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); + AR_HOSTIF_REG(ah, AR_PM_STATE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE); + AR_HOSTIF_REG(ah, AR_H_INFOL) = + AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL); + AR_HOSTIF_REG(ah, AR_H_INFOH) = + AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH); + AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = + AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); + AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = + AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); + AR_HOSTIF_REG(ah, AR_EEPROM) = + AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL); + AR_HOSTIF_REG(ah, AR_SREV) = + AR9300_HOSTIF_OFFSET(HOST_INTF_SREV); + AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); + AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); + AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); + AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); + AR_HOSTIF_REG(ah, AR_PCIE_SERDES) = + AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW); + AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) = + AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD); + AR_HOSTIF_REG(ah, AR_GPIO_OUT) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); + AR_HOSTIF_REG(ah, AR_GPIO_IN) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); + AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); + AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); + AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); + AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); + AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); + AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); + AR_HOSTIF_REG(ah, AR_INPUT_STATE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); + AR_HOSTIF_REG(ah, AR_SPARE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE); + AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) = + AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN); + AR_HOSTIF_REG(ah, AR_CLKRUN) = + AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN); + AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = + AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); + AR_HOSTIF_REG(ah, AR_OBS) = + AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); + AR_HOSTIF_REG(ah, AR_RFSILENT) = + AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT); + AR_HOSTIF_REG(ah, AR_GPIO_PDPU) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU); + AR_HOSTIF_REG(ah, AR_GPIO_DS) = + AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS); + AR_HOSTIF_REG(ah, AR_MISC) = + AR9300_HOSTIF_OFFSET(HOST_INTF_MISC); + AR_HOSTIF_REG(ah, AR_PCIE_MSI) = + AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); +#if 0 /* Offsets are not defined in reg_map structure */ + AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE); + AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) = + AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY); + AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) = + AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL); +#endif + AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) = + AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ); + AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = + AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); + AR_HOSTIF_REG(ah, AR_TXAPSYNC) = + AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); + AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = + AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = + AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); +} + +static void +ar9340_init_hostif_offsets(struct ath_hal *ah) +{ + AR_HOSTIF_REG(ah, AR_RC) = + AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); + AR_HOSTIF_REG(ah, AR_WA) = + AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); + AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = + AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); + AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = + AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); + AR_HOSTIF_REG(ah, AR_SREV) = + AR9340_HOSTIF_OFFSET(HOST_INTF_SREV); + AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); + AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); + AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); + AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); + AR_HOSTIF_REG(ah, AR_GPIO_OUT) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); + AR_HOSTIF_REG(ah, AR_GPIO_IN) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); + AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); + AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); + AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); + AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); + AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); + AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); + AR_HOSTIF_REG(ah, AR_INPUT_STATE) = + AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); + AR_HOSTIF_REG(ah, AR_CLKRUN) = + AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN); + AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = + AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); + AR_HOSTIF_REG(ah, AR_OBS) = + AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); + AR_HOSTIF_REG(ah, AR_RFSILENT) = + AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT); + AR_HOSTIF_REG(ah, AR_MISC) = + AR9340_HOSTIF_OFFSET(HOST_INTF_MISC); + AR_HOSTIF_REG(ah, AR_PCIE_MSI) = + AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); + AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = + AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); + AR_HOSTIF_REG(ah, AR_TXAPSYNC) = + AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); + AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = + AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); + AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = + AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); +} + +/* + * Host interface register offsets are different for Osprey and Wasp + * and hence store the offsets in hal structure + */ +static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid) +{ + if (devid == AR9300_DEVID_AR9340) { + ar9340_init_hostif_offsets(ah); + } else { + ar9300_init_hostif_offsets(ah); + } + return 0; +} + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_beacon.c b/hal/ar9300/ar9300_beacon.c new file mode 100644 index 000000000000..66ce172241d1 --- /dev/null +++ b/hal/ar9300/ar9300_beacon.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" + +#define TU_TO_USEC(_tu) ((_tu) << 10) + +extern u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q); + +/* + * Initializes all of the hardware registers used to + * send beacons. Note that for station operation the + * driver calls ar9300_set_sta_beacon_timers instead. + */ +void +ar9300_beacon_init(struct ath_hal *ah, + u_int32_t next_beacon, u_int32_t beacon_period, HAL_OPMODE opmode) +{ + struct ath_hal_private *ap = AH_PRIVATE(ah); + u_int32_t beacon_period_usec; + + HALASSERT(opmode == HAL_M_IBSS || opmode == HAL_M_HOSTAP); + if (opmode == HAL_M_IBSS) { + OS_REG_SET_BIT(ah, AR_TXCFG, AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); + } + OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, ONE_EIGHTH_TU_TO_USEC(next_beacon)); + OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, + (ONE_EIGHTH_TU_TO_USEC(next_beacon) - + ap->ah_config.ath_hal_dma_beacon_response_time)); + OS_REG_WRITE(ah, AR_NEXT_SWBA, + (ONE_EIGHTH_TU_TO_USEC(next_beacon) - + ap->ah_config.ath_hal_sw_beacon_response_time)); + + beacon_period_usec = + ONE_EIGHTH_TU_TO_USEC(beacon_period & HAL_BEACON_PERIOD_TU8); + OS_REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period_usec); + OS_REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period_usec); + OS_REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period_usec); + + /* reset TSF if required */ + if (beacon_period & HAL_BEACON_RESET_TSF) { + ar9300_reset_tsf(ah); + } + + /* enable timers */ + OS_REG_SET_BIT(ah, AR_TIMER_MODE, + AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); +} + +/* + * Set all the beacon related bits on the h/w for stations + * i.e. initializes the corresponding h/w timers; + */ +void +ar9300_set_sta_beacon_timers(struct ath_hal *ah, const HAL_BEACON_STATE *bs) +{ + u_int32_t next_tbtt, beaconintval, dtimperiod, beacontimeout; + HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + + HALASSERT(bs->bs_intval != 0); + + /* no cfp setting since h/w automatically takes care */ + OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); + + /* + * Start the beacon timers by setting the BEACON register + * to the beacon interval; no need to write tim offset since + * h/w parses IEs. + */ + OS_REG_WRITE(ah, AR_BEACON_PERIOD, + TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD)); + OS_REG_WRITE(ah, AR_DMA_BEACON_PERIOD, + TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD)); + /* + * Configure the BMISS interrupt. Note that we + * assume the caller blocks interrupts while enabling + * the threshold. + */ + HALASSERT(bs->bs_bmissthreshold <= + (AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S)); + OS_REG_RMW_FIELD(ah, AR_RSSI_THR, + AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); + + /* + * Program the sleep registers to correlate with the beacon setup. + */ + + /* + * Current implementation assumes sw processing of beacons - + * assuming an interrupt is generated every beacon which + * causes the hardware to become awake until the sw tells + * it to go to sleep again; beacon timeout is to allow for + * beacon jitter; cab timeout is max time to wait for cab + * after seeing the last DTIM or MORE CAB bit + */ +#define CAB_TIMEOUT_VAL 10 /* in TU */ +#define BEACON_TIMEOUT_VAL 10 /* in TU */ +#define MIN_BEACON_TIMEOUT_VAL 1 /* in 1/8 TU */ +#define SLEEP_SLOP 3 /* in TU */ + + /* + * For max powersave mode we may want to sleep for longer than a + * beacon period and not want to receive all beacons; modify the + * timers accordingly; make sure to align the next TIM to the + * next DTIM if we decide to wake for DTIMs only + */ + beaconintval = bs->bs_intval & HAL_BEACON_PERIOD; + HALASSERT(beaconintval != 0); + if (bs->bs_sleepduration > beaconintval) { + HALASSERT(roundup(bs->bs_sleepduration, beaconintval) == + bs->bs_sleepduration); + beaconintval = bs->bs_sleepduration; + } + dtimperiod = bs->bs_dtimperiod; + if (bs->bs_sleepduration > dtimperiod) { + HALASSERT(dtimperiod == 0 || + roundup(bs->bs_sleepduration, dtimperiod) == + bs->bs_sleepduration); + dtimperiod = bs->bs_sleepduration; + } + HALASSERT(beaconintval <= dtimperiod); + if (beaconintval == dtimperiod) { + next_tbtt = bs->bs_nextdtim; + } else { + next_tbtt = bs->bs_nexttbtt; + } + + HALDEBUG(ah, HAL_DEBUG_BEACON, + "%s: next DTIM %d\n", __func__, bs->bs_nextdtim); + HALDEBUG(ah, HAL_DEBUG_BEACON, + "%s: next beacon %d\n", __func__, next_tbtt); + HALDEBUG(ah, HAL_DEBUG_BEACON, + "%s: beacon period %d\n", __func__, beaconintval); + HALDEBUG(ah, HAL_DEBUG_BEACON, + "%s: DTIM period %d\n", __func__, dtimperiod); + + OS_REG_WRITE(ah, AR_NEXT_DTIM, TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); + OS_REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(next_tbtt - SLEEP_SLOP)); + + /* cab timeout is now in 1/8 TU */ + OS_REG_WRITE(ah, AR_SLEEP1, + SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) + | AR_SLEEP1_ASSUME_DTIM); + + /* beacon timeout is now in 1/8 TU */ + if (p_cap->hal_auto_sleep_support) { + beacontimeout = (BEACON_TIMEOUT_VAL << 3); + } else { + /* + * Use a very small value to make sure the timeout occurs before + * the TBTT. In this case the chip will not go back to sleep + * automatically, instead it will wait for the SW to explicitly + * set it to that mode. + */ + beacontimeout = MIN_BEACON_TIMEOUT_VAL; + } + + OS_REG_WRITE(ah, AR_SLEEP2, + SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); + + OS_REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); + OS_REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); + + /* clear HOST AP related timers first */ + OS_REG_CLR_BIT(ah, AR_TIMER_MODE, (AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN)); + + OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN + | AR_DTIM_TIMER_EN); + + /* TSF out of range threshold */ + OS_REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); + +#undef CAB_TIMEOUT_VAL +#undef BEACON_TIMEOUT_VAL +#undef SLEEP_SLOP +} +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_eeprom.c b/hal/ar9300/ar9300_eeprom.c new file mode 100644 index 000000000000..63a5a43acd18 --- /dev/null +++ b/hal/ar9300/ar9300_eeprom.c @@ -0,0 +1,4522 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" +#include "ah_devid.h" +#ifdef AH_DEBUG +#include "ah_desc.h" /* NB: for HAL_PHYERR* */ +#endif +#include "ar9300/ar9300.h" +#include "ar9300/ar9300eep.h" +#include "ar9300/ar9300template_generic.h" +#include "ar9300/ar9300template_xb112.h" +#include "ar9300/ar9300template_hb116.h" +#include "ar9300/ar9300template_xb113.h" +#include "ar9300/ar9300template_hb112.h" +#include "ar9300/ar9300template_ap121.h" +#include "ar9300/ar9300template_osprey_k31.h" +#include "ar9300/ar9300template_wasp_2.h" +#include "ar9300/ar9300template_wasp_k31.h" +#include "ar9300/ar9300template_aphrodite.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300phy.h" + + + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN +void ar9300_swap_eeprom(ar9300_eeprom_t *eep); +void ar9300_eeprom_template_swap(void); +#endif + +static u_int16_t ar9300_eeprom_get_spur_chan(struct ath_hal *ah, + u_int16_t spur_chan, HAL_BOOL is_2ghz); +#ifdef UNUSED +static inline HAL_BOOL ar9300_fill_eeprom(struct ath_hal *ah); +static inline HAL_STATUS ar9300_check_eeprom(struct ath_hal *ah); +#endif + +static ar9300_eeprom_t *default9300[] = +{ + &ar9300_template_generic, + &ar9300_template_xb112, + &ar9300_template_hb116, + &ar9300_template_hb112, + &ar9300_template_xb113, + &ar9300_template_ap121, + &ar9300_template_wasp_2, + &ar9300_template_wasp_k31, + &ar9300_template_osprey_k31, + &ar9300_template_aphrodite, +}; + +/* + * Different types of memory where the calibration data might be stored. + * All types are searched in ar9300_eeprom_restore() + * in the order flash, eeprom, otp. + * To disable searching a type, set its parameter to 0. + */ + +/* + * This is where we look for the calibration data. + * must be set before ath_attach() is called + */ +static int calibration_data_try = calibration_data_none; +static int calibration_data_try_address = 0; + +/* + * Set the type of memory used to store calibration data. + * Used by nart to force reading/writing of a specific type. + * The driver can normally allow autodetection + * by setting source to calibration_data_none=0. + */ +void ar9300_calibration_data_set(struct ath_hal *ah, int32_t source) +{ + if (ah != 0) { + AH9300(ah)->calibration_data_source = source; + } else { + calibration_data_try = source; + } +} + +int32_t ar9300_calibration_data_get(struct ath_hal *ah) +{ + if (ah != 0) { + return AH9300(ah)->calibration_data_source; + } else { + return calibration_data_try; + } +} + +/* + * Set the address of first byte used to store calibration data. + * Used by nart to force reading/writing at a specific address. + * The driver can normally allow autodetection by setting size=0. + */ +void ar9300_calibration_data_address_set(struct ath_hal *ah, int32_t size) +{ + if (ah != 0) { + AH9300(ah)->calibration_data_source_address = size; + } else { + calibration_data_try_address = size; + } +} + +int32_t ar9300_calibration_data_address_get(struct ath_hal *ah) +{ + if (ah != 0) { + return AH9300(ah)->calibration_data_source_address; + } else { + return calibration_data_try_address; + } +} + +/* + * This is the template that is loaded if ar9300_eeprom_restore() + * can't find valid data in the memory. + */ +static int Ar9300_eeprom_template_preference = ar9300_eeprom_template_generic; + +void ar9300_eeprom_template_preference(int32_t value) +{ + Ar9300_eeprom_template_preference = value; +} + +/* + * Install the specified default template. + * Overwrites any existing calibration and configuration information in memory. + */ +int32_t ar9300_eeprom_template_install(struct ath_hal *ah, int32_t value) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + ar9300_eeprom_t *mptr, *dptr; + int mdata_size; + + mptr = &ahp->ah_eeprom; + mdata_size = ar9300_eeprom_struct_size(); + if (mptr != 0) { +#if 0 + calibration_data_source = calibration_data_none; + calibration_data_source_address = 0; +#endif + dptr = ar9300_eeprom_struct_default_find_by_id(value); + if (dptr != 0) { + OS_MEMCPY(mptr, dptr, mdata_size); + return 0; + } + } + return -1; +} + +static int +ar9300_eeprom_restore_something(struct ath_hal *ah, ar9300_eeprom_t *mptr, + int mdata_size) +{ + int it; + ar9300_eeprom_t *dptr; + int nptr; + + nptr = -1; + /* + * if we didn't find any blocks in the memory, + * put the prefered template in place + */ + if (nptr < 0) { + AH9300(ah)->calibration_data_source = calibration_data_none; + AH9300(ah)->calibration_data_source_address = 0; + dptr = ar9300_eeprom_struct_default_find_by_id( + Ar9300_eeprom_template_preference); + if (dptr != 0) { + OS_MEMCPY(mptr, dptr, mdata_size); + nptr = 0; + } + } + /* + * if we didn't find the prefered one, + * put the normal default template in place + */ + if (nptr < 0) { + AH9300(ah)->calibration_data_source = calibration_data_none; + AH9300(ah)->calibration_data_source_address = 0; + dptr = ar9300_eeprom_struct_default_find_by_id( + ar9300_eeprom_template_default); + if (dptr != 0) { + OS_MEMCPY(mptr, dptr, mdata_size); + nptr = 0; + } + } + /* + * if we can't find the best template, put any old template in place + * presume that newer ones are better, so search backwards + */ + if (nptr < 0) { + AH9300(ah)->calibration_data_source = calibration_data_none; + AH9300(ah)->calibration_data_source_address = 0; + for (it = ar9300_eeprom_struct_default_many() - 1; it >= 0; it--) { + dptr = ar9300_eeprom_struct_default(it); + if (dptr != 0) { + OS_MEMCPY(mptr, dptr, mdata_size); + nptr = 0; + break; + } + } + } + return nptr; +} + +/* + * Read 16 bits of data from offset into *data + */ +HAL_BOOL +ar9300_eeprom_read_word(struct ath_hal *ah, u_int off, u_int16_t *data) +{ + if (AR_SREV_OSPREY(ah) || AR_SREV_POSEIDON(ah)) + { + (void) OS_REG_READ(ah, AR9300_EEPROM_OFFSET + (off << AR9300_EEPROM_S)); + if (!ath_hal_wait(ah, + AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA), + AR_EEPROM_STATUS_DATA_BUSY | AR_EEPROM_STATUS_DATA_PROT_ACCESS, + 0, AH_WAIT_TIMEOUT)) + { + return AH_FALSE; + } + *data = MS(OS_REG_READ(ah, + AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA)), AR_EEPROM_STATUS_DATA_VAL); + return AH_TRUE; + } + else + { + *data = 0; + return AH_FALSE; + } +} + + +HAL_BOOL +ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi) +{ + int time_out = 1000; + int status = 0; + u_int32_t addr; + + addr = (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah))? + OTP_MEM_START_ADDRESS_WASP : OTP_MEM_START_ADDRESS; + if (!is_wifi) { + addr = BTOTP_MEM_START_ADDRESS; + } + addr += off * 4; /* OTP is 32 bit addressable */ + (void) OS_REG_READ(ah, addr); + + addr = (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) ? + OTP_STATUS0_OTP_SM_BUSY_WASP : OTP_STATUS0_OTP_SM_BUSY; + if (!is_wifi) { + addr = BTOTP_STATUS0_OTP_SM_BUSY; + } + while ((time_out > 0) && (!status)) { /* wait for access complete */ + /* Read data valid, access not busy, sm not busy */ + status = ((OS_REG_READ(ah, addr) & 0x7) == 0x4) ? 1 : 0; + time_out--; + } + if (time_out == 0) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: Timed out during OTP Status0 validation\n", __func__); + return AH_FALSE; + } + + addr = (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) ? + OTP_STATUS1_EFUSE_READ_DATA_WASP : OTP_STATUS1_EFUSE_READ_DATA; + if (!is_wifi) { + addr = BTOTP_STATUS1_EFUSE_READ_DATA; + } + *data = OS_REG_READ(ah, addr); + return AH_TRUE; +} + + + + +static HAL_STATUS +ar9300_flash_map(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); +#if defined(AR9100) || defined(__NetBSD__) + ahp->ah_cal_mem = OS_REMAP(ah, AR9300_EEPROM_START_ADDR, AR9300_EEPROM_MAX); +#else + ahp->ah_cal_mem = OS_REMAP((uintptr_t)(AH_PRIVATE(ah)->ah_st), + (AR9300_EEPROM_MAX + AR9300_FLASH_CAL_START_OFFSET)); +#endif + if (!ahp->ah_cal_mem) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: cannot remap eeprom region \n", __func__); + return HAL_EIO; + } + return HAL_OK; +} + +HAL_BOOL +ar9300_flash_read(struct ath_hal *ah, u_int off, u_int16_t *data) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + *data = ((u_int16_t *)ahp->ah_cal_mem)[off]; + return AH_TRUE; +} + +HAL_BOOL +ar9300_flash_write(struct ath_hal *ah, u_int off, u_int16_t data) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + ((u_int16_t *)ahp->ah_cal_mem)[off] = data; + return AH_TRUE; +} + +#ifdef UNUSED +#endif + +HAL_STATUS +ar9300_eeprom_attach(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + ahp->try_dram = 1; + ahp->try_eeprom = 1; + ahp->try_otp = 1; +#ifdef ATH_CAL_NAND_FLASH + ahp->try_nand = 1; +#else + ahp->try_flash = 1; +#endif + ahp->calibration_data_source = calibration_data_none; + ahp->calibration_data_source_address = 0; + ahp->calibration_data_try = calibration_data_try; + ahp->calibration_data_try_address = 0; + + /* + * In case flash will be used for EEPROM. Otherwise ahp->ah_cal_mem + * must be set to NULL or the real EEPROM address. + */ + ar9300_flash_map(ah); + /* + * ###### This function always return NO SPUR. + * This is not AH_TRUE for many board designs. + * Does anyone use this? + */ + AH_PRIVATE(ah)->ah_eeprom_get_spur_chan = ar9300_eeprom_get_spur_chan; + +#ifdef OLDCODE + /* XXX Needs to be moved for dynamic selection */ + ahp->ah_eeprom = *(default9300[ar9300_eeprom_template_default]); + + + if (AR_SREV_HORNET(ah)) { + /* Set default values for Hornet. */ + ahp->ah_eeprom.base_eep_header.op_cap_flags.op_flags = + AR9300_OPFLAGS_11G; + ahp->ah_eeprom.base_eep_header.txrx_mask = 0x11; + } else if (AR_SREV_POSEIDON(ah)) { + /* Set default values for Poseidon. */ + ahp->ah_eeprom.base_eep_header.op_cap_flags.op_flags = + AR9300_OPFLAGS_11G; + ahp->ah_eeprom.base_eep_header.txrx_mask = 0x11; + } + + if (AH_PRIVATE(ah)->ah_config.ath_hal_skip_eeprom_read) { + ahp->ah_emu_eeprom = 1; + return HAL_OK; + } + + ahp->ah_emu_eeprom = 1; + +#ifdef UNUSED +#endif + + if (!ar9300_fill_eeprom(ah)) { + return HAL_EIO; + } + + return HAL_OK; + /* return ar9300_check_eeprom(ah); */ +#else + ahp->ah_emu_eeprom = 1; + +#if 0 +/*#ifdef MDK_AP*/ /* MDK_AP is defined only in NART AP build */ + u_int8_t buffer[10]; + int caldata_check = 0; + + ar9300_calibration_data_read_flash( + ah, FLASH_BASE_CALDATA_OFFSET, buffer, 4); + printf("flash caldata:: %x\n", buffer[0]); + if (buffer[0] != 0xff) { + caldata_check = 1; + } + if (!caldata_check) { + ar9300_eeprom_t *mptr; + int mdata_size; + if (AR_SREV_HORNET(ah)) { + /* XXX: For initial testing */ + mptr = &ahp->ah_eeprom; + mdata_size = ar9300_eeprom_struct_size(); + ahp->ah_eeprom = ar9300_template_ap121; + ahp->ah_emu_eeprom = 1; + /* need it to let art save in to flash ????? */ + calibration_data_source = calibration_data_flash; + } else if (AR_SREV_WASP(ah)) { + /* XXX: For initial testing */ + ath_hal_printf(ah, " wasp eep attach\n"); + mptr = &ahp->ah_eeprom; + mdata_size = ar9300_eeprom_struct_size(); + ahp->ah_eeprom = ar9300_template_generic; + ahp->ah_eeprom.mac_addr[0] = 0x00; + ahp->ah_eeprom.mac_addr[1] = 0x03; + ahp->ah_eeprom.mac_addr[2] = 0x7F; + ahp->ah_eeprom.mac_addr[3] = 0xBA; + ahp->ah_eeprom.mac_addr[4] = 0xD0; + ahp->ah_eeprom.mac_addr[5] = 0x00; + ahp->ah_emu_eeprom = 1; + ahp->ah_eeprom.base_eep_header.txrx_mask = 0x33; + ahp->ah_eeprom.base_eep_header.txrxgain = 0x10; + /* need it to let art save in to flash ????? */ + calibration_data_source = calibration_data_flash; + } + return HAL_OK; + } +#endif + if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + ahp->try_eeprom = 0; + } + + if (!ar9300_eeprom_restore(ah)) { + return HAL_EIO; + } + return HAL_OK; +#endif +} + +u_int32_t +ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param) +{ + ar9300_eeprom_t *eep = &ahp->ah_eeprom; + OSPREY_BASE_EEP_HEADER *p_base = &eep->base_eep_header; + OSPREY_BASE_EXTENSION_1 *base_ext1 = &eep->base_ext1; + + switch (param) { +#if NOTYET + case EEP_NFTHRESH_5: + return p_modal[0].noise_floor_thresh_ch[0]; + case EEP_NFTHRESH_2: + return p_modal[1].noise_floor_thresh_ch[0]; +#endif + case EEP_MAC_LSW: + return eep->mac_addr[0] << 8 | eep->mac_addr[1]; + case EEP_MAC_MID: + return eep->mac_addr[2] << 8 | eep->mac_addr[3]; + case EEP_MAC_MSW: + return eep->mac_addr[4] << 8 | eep->mac_addr[5]; + case EEP_REG_0: + return p_base->reg_dmn[0]; + case EEP_REG_1: + return p_base->reg_dmn[1]; + case EEP_OP_CAP: + return p_base->device_cap; + case EEP_OP_MODE: + return p_base->op_cap_flags.op_flags; + case EEP_RF_SILENT: + return p_base->rf_silent; +#if NOTYET + case EEP_OB_5: + return p_modal[0].ob; + case EEP_DB_5: + return p_modal[0].db; + case EEP_OB_2: + return p_modal[1].ob; + case EEP_DB_2: + return p_modal[1].db; + case EEP_MINOR_REV: + return p_base->eeprom_version & AR9300_EEP_VER_MINOR_MASK; +#endif + case EEP_TX_MASK: + return (p_base->txrx_mask >> 4) & 0xf; + case EEP_RX_MASK: + return p_base->txrx_mask & 0xf; +#if NOTYET + case EEP_FSTCLK_5G: + return p_base->fast_clk5g; + case EEP_RXGAIN_TYPE: + return p_base->rx_gain_type; +#endif + case EEP_DRIVE_STRENGTH: +#define AR9300_EEP_BASE_DRIVE_STRENGTH 0x1 + return p_base->misc_configuration & AR9300_EEP_BASE_DRIVE_STRENGTH; + case EEP_INTERNAL_REGULATOR: + /* Bit 4 is internal regulator flag */ + return ((p_base->feature_enable & 0x10) >> 4); + case EEP_SWREG: + return (p_base->swreg); + case EEP_PAPRD_ENABLED: + /* Bit 5 is paprd flag */ + return ((p_base->feature_enable & 0x20) >> 5); + case EEP_ANTDIV_control: + return (u_int32_t)(base_ext1->ant_div_control); + case EEP_CHAIN_MASK_REDUCE: + return ((p_base->misc_configuration >> 3) & 0x1); + case EEP_OL_PWRCTRL: + return 0; + case EEP_DEV_TYPE: + return p_base->device_type; + default: + HALASSERT(0); + return 0; + } +} + + + +/******************************************************************************/ +/*! +** \brief EEPROM fixup code for INI values +** +** This routine provides a place to insert "fixup" code for specific devices +** that need to modify INI values based on EEPROM values, BEFORE the INI values +** are written. +** Certain registers in the INI file can only be written once without +** undesired side effects, and this provides a place for EEPROM overrides +** in these cases. +** +** This is called at attach time once. It should not affect run time +** performance at all +** +** \param ah Pointer to HAL object (this) +** \param p_eep_data Pointer to (filled in) eeprom data structure +** \param reg register being inspected on this call +** \param value value in INI file +** +** \return Updated value for INI file. +*/ +u_int32_t +ar9300_ini_fixup(struct ath_hal *ah, ar9300_eeprom_t *p_eep_data, + u_int32_t reg, u_int32_t value) +{ + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "ar9300_eeprom_def_ini_fixup: FIXME\n"); +#if 0 + BASE_EEPDEF_HEADER *p_base = &(p_eep_data->base_eep_header); + + switch (AH_PRIVATE(ah)->ah_devid) + { + case AR9300_DEVID_AR9300_PCI: + /* + ** Need to set the external/internal regulator bit to the proper value. + ** Can only write this ONCE. + */ + + if ( reg == 0x7894 ) + { + /* + ** Check for an EEPROM data structure of "0x0b" or better + */ + + HALDEBUG(ah, HAL_DEBUG_EEPROM, "ini VAL: %x EEPROM: %x\n", + value, (p_base->version & 0xff)); + + if ( (p_base->version & 0xff) > 0x0a) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "PWDCLKIND: %d\n", p_base->pwdclkind); + value &= ~AR_AN_TOP2_PWDCLKIND; + value |= + AR_AN_TOP2_PWDCLKIND & + (p_base->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); + } else { + HALDEBUG(ah, HAL_DEBUG_EEPROM, "PWDCLKIND Earlier Rev\n"); + } + + HALDEBUG(ah, HAL_DEBUG_EEPROM, "final ini VAL: %x\n", value); + } + break; + + } + + return (value); +#else + return 0; +#endif +} + +/* + * Returns the interpolated y value corresponding to the specified x value + * from the np ordered pairs of data (px,py). + * The pairs do not have to be in any order. + * If the specified x value is less than any of the px, + * the returned y value is equal to the py for the lowest px. + * If the specified x value is greater than any of the px, + * the returned y value is equal to the py for the highest px. + */ +static int +interpolate(int32_t x, int32_t *px, int32_t *py, u_int16_t np) +{ + int ip = 0; + int lx = 0, ly = 0, lhave = 0; + int hx = 0, hy = 0, hhave = 0; + int dx = 0; + int y = 0; + int bf, factor, plus; + + lhave = 0; + hhave = 0; + /* + * identify best lower and higher x calibration measurement + */ + for (ip = 0; ip < np; ip++) { + dx = x - px[ip]; + /* this measurement is higher than our desired x */ + if (dx <= 0) { + if (!hhave || dx > (x - hx)) { + /* new best higher x measurement */ + hx = px[ip]; + hy = py[ip]; + hhave = 1; + } + } + /* this measurement is lower than our desired x */ + if (dx >= 0) { + if (!lhave || dx < (x - lx)) { + /* new best lower x measurement */ + lx = px[ip]; + ly = py[ip]; + lhave = 1; + } + } + } + /* the low x is good */ + if (lhave) { + /* so is the high x */ + if (hhave) { + /* they're the same, so just pick one */ + if (hx == lx) { + y = ly; + } else { + /* interpolate with round off */ + bf = (2 * (hy - ly) * (x - lx)) / (hx - lx); + plus = (bf % 2); + factor = bf / 2; + y = ly + factor + plus; + } + } else { + /* only low is good, use it */ + y = ly; + } + } else if (hhave) { + /* only high is good, use it */ + y = hy; + } else { + /* nothing is good,this should never happen unless np=0, ???? */ + y = -(1 << 30); + } + + return y; +} + +u_int8_t +ar9300_eeprom_get_legacy_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, + u_int16_t freq, HAL_BOOL is_2ghz) +{ + u_int16_t num_piers, i; + int32_t target_power_array[OSPREY_NUM_5G_20_TARGET_POWERS]; + int32_t freq_array[OSPREY_NUM_5G_20_TARGET_POWERS]; + u_int8_t *p_freq_bin; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + CAL_TARGET_POWER_LEG *p_eeprom_target_pwr; + + if (is_2ghz) { + num_piers = OSPREY_NUM_2G_20_TARGET_POWERS; + p_eeprom_target_pwr = eep->cal_target_power_2g; + p_freq_bin = eep->cal_target_freqbin_2g; + } else { + num_piers = OSPREY_NUM_5G_20_TARGET_POWERS; + p_eeprom_target_pwr = eep->cal_target_power_5g; + p_freq_bin = eep->cal_target_freqbin_5g; + } + + /* + * create array of channels and targetpower from + * targetpower piers stored on eeprom + */ + for (i = 0; i < num_piers; i++) { + freq_array[i] = FBIN2FREQ(p_freq_bin[i], is_2ghz); + target_power_array[i] = p_eeprom_target_pwr[i].t_pow2x[rate_index]; + } + + /* interpolate to get target power for given frequency */ + return + ((u_int8_t)interpolate( + (int32_t)freq, freq_array, target_power_array, num_piers)); +} + +u_int8_t +ar9300_eeprom_get_ht20_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, + u_int16_t freq, HAL_BOOL is_2ghz) +{ + u_int16_t num_piers, i; + int32_t target_power_array[OSPREY_NUM_5G_20_TARGET_POWERS]; + int32_t freq_array[OSPREY_NUM_5G_20_TARGET_POWERS]; + u_int8_t *p_freq_bin; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + OSP_CAL_TARGET_POWER_HT *p_eeprom_target_pwr; + + if (is_2ghz) { + num_piers = OSPREY_NUM_2G_20_TARGET_POWERS; + p_eeprom_target_pwr = eep->cal_target_power_2g_ht20; + p_freq_bin = eep->cal_target_freqbin_2g_ht20; + } else { + num_piers = OSPREY_NUM_5G_20_TARGET_POWERS; + p_eeprom_target_pwr = eep->cal_target_power_5g_ht20; + p_freq_bin = eep->cal_target_freqbin_5g_ht20; + } + + /* + * create array of channels and targetpower from + * targetpower piers stored on eeprom + */ + for (i = 0; i < num_piers; i++) { + freq_array[i] = FBIN2FREQ(p_freq_bin[i], is_2ghz); + target_power_array[i] = p_eeprom_target_pwr[i].t_pow2x[rate_index]; + } + + /* interpolate to get target power for given frequency */ + return + ((u_int8_t)interpolate( + (int32_t)freq, freq_array, target_power_array, num_piers)); +} + +u_int8_t +ar9300_eeprom_get_ht40_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, + u_int16_t freq, HAL_BOOL is_2ghz) +{ + u_int16_t num_piers, i; + int32_t target_power_array[OSPREY_NUM_5G_40_TARGET_POWERS]; + int32_t freq_array[OSPREY_NUM_5G_40_TARGET_POWERS]; + u_int8_t *p_freq_bin; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + OSP_CAL_TARGET_POWER_HT *p_eeprom_target_pwr; + + if (is_2ghz) { + num_piers = OSPREY_NUM_2G_40_TARGET_POWERS; + p_eeprom_target_pwr = eep->cal_target_power_2g_ht40; + p_freq_bin = eep->cal_target_freqbin_2g_ht40; + } else { + num_piers = OSPREY_NUM_5G_40_TARGET_POWERS; + p_eeprom_target_pwr = eep->cal_target_power_5g_ht40; + p_freq_bin = eep->cal_target_freqbin_5g_ht40; + } + + /* + * create array of channels and targetpower from + * targetpower piers stored on eeprom + */ + for (i = 0; i < num_piers; i++) { + freq_array[i] = FBIN2FREQ(p_freq_bin[i], is_2ghz); + target_power_array[i] = p_eeprom_target_pwr[i].t_pow2x[rate_index]; + } + + /* interpolate to get target power for given frequency */ + return + ((u_int8_t)interpolate( + (int32_t)freq, freq_array, target_power_array, num_piers)); +} + +u_int8_t +ar9300_eeprom_get_cck_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, + u_int16_t freq) +{ + u_int16_t num_piers = OSPREY_NUM_2G_CCK_TARGET_POWERS, i; + int32_t target_power_array[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + int32_t freq_array[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + u_int8_t *p_freq_bin = eep->cal_target_freqbin_cck; + CAL_TARGET_POWER_LEG *p_eeprom_target_pwr = eep->cal_target_power_cck; + + /* + * create array of channels and targetpower from + * targetpower piers stored on eeprom + */ + for (i = 0; i < num_piers; i++) { + freq_array[i] = FBIN2FREQ(p_freq_bin[i], 1); + target_power_array[i] = p_eeprom_target_pwr[i].t_pow2x[rate_index]; + } + + /* interpolate to get target power for given frequency */ + return + ((u_int8_t)interpolate( + (int32_t)freq, freq_array, target_power_array, num_piers)); +} + +/* + * Set tx power registers to array of values passed in + */ +int +ar9300_transmit_power_reg_write(struct ath_hal *ah, u_int8_t *p_pwr_array) +{ +#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) + /* make sure forced gain is not set */ +#if 0 + field_write("force_dac_gain", 0); + OS_REG_WRITE(ah, 0xa3f8, 0); + field_write("force_tx_gain", 0); +#endif + + OS_REG_WRITE(ah, 0xa458, 0); + + /* Write the OFDM power per rate set */ + /* 6 (LSB), 9, 12, 18 (MSB) */ + OS_REG_WRITE(ah, 0xa3c0, + POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) + ); + /* 24 (LSB), 36, 48, 54 (MSB) */ + OS_REG_WRITE(ah, 0xa3c4, + POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54], 24) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48], 16) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36], 8) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) + ); + + /* Write the CCK power per rate set */ + /* 1L (LSB), reserved, 2L, 2S (MSB) */ + OS_REG_WRITE(ah, 0xa3c8, + POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) +/* | POW_SM(tx_power_times2, 8)*/ /* this is reserved for Osprey */ + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) + ); + /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ + OS_REG_WRITE(ah, 0xa3cc, + POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) + ); + + /* write the power for duplicated frames - HT40 */ + /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */ + OS_REG_WRITE(ah, 0xa3e0, + POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) + | POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) + ); + + /* Write the HT20 power per rate set */ + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ + OS_REG_WRITE(ah, 0xa3d0, + POW_SM(p_pwr_array[ALL_TARGET_HT20_5], 24) + | POW_SM(p_pwr_array[ALL_TARGET_HT20_4], 16) + | POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8) + | POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0) + ); + + /* 6 (LSB), 7, 12, 13 (MSB) */ + OS_REG_WRITE(ah, 0xa3d4, + POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) + | POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) + | POW_SM(p_pwr_array[ALL_TARGET_HT20_7], 8) + | POW_SM(p_pwr_array[ALL_TARGET_HT20_6], 0) + ); + + /* 14 (LSB), 15, 20, 21 */ + OS_REG_WRITE(ah, 0xa3e4, + POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) + | POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) + | POW_SM(p_pwr_array[ALL_TARGET_HT20_15], 8) + | POW_SM(p_pwr_array[ALL_TARGET_HT20_14], 0) + ); + + /* Mixed HT20 and HT40 rates */ + /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ + OS_REG_WRITE(ah, 0xa3e8, + POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) + | POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) + | POW_SM(p_pwr_array[ALL_TARGET_HT20_23], 8) + | POW_SM(p_pwr_array[ALL_TARGET_HT20_22], 0) + ); + + /* Write the HT40 power per rate set */ + /* correct PAR difference between HT40 and HT20/LEGACY */ + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ + OS_REG_WRITE(ah, 0xa3d8, + POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) + | POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) + | POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) + | POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0) + ); + + /* 6 (LSB), 7, 12, 13 (MSB) */ + OS_REG_WRITE(ah, 0xa3dc, + POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) + | POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) + | POW_SM(p_pwr_array[ALL_TARGET_HT40_7], 8) + | POW_SM(p_pwr_array[ALL_TARGET_HT40_6], 0) + ); + + /* 14 (LSB), 15, 20, 21 */ + OS_REG_WRITE(ah, 0xa3ec, + POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) + | POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) + | POW_SM(p_pwr_array[ALL_TARGET_HT40_15], 8) + | POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0) + ); + + return 0; +#undef POW_SM +} + +static void +ar9300_selfgen_tpc_reg_write(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, + u_int8_t *p_pwr_array) +{ + u_int32_t tpc_reg_val; + + /* Set the target power values for self generated frames (ACK,RTS/CTS) to + * be within limits. This is just a safety measure.With per packet TPC mode + * enabled the target power value used with self generated frames will be + * MIN( TPC reg, BB_powertx_rate register) + */ + + if (IS_CHAN_2GHZ(chan)) { + tpc_reg_val = (SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_ACK) | + SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_CTS) | + SM(0x3f, AR_TPC_CHIRP) | + SM(0x3f, AR_TPC_RPT)); + } else { + tpc_reg_val = (SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_ACK) | + SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_CTS) | + SM(0x3f, AR_TPC_CHIRP) | + SM(0x3f, AR_TPC_RPT)); + } + OS_REG_WRITE(ah, AR_TPC, tpc_reg_val); +} + +void +ar9300_set_target_power_from_eeprom(struct ath_hal *ah, u_int16_t freq, + u_int8_t *target_power_val_t2) +{ + /* hard code for now, need to get from eeprom struct */ + u_int8_t ht40_power_inc_for_pdadc = 0; + HAL_BOOL is_2ghz = 0; + + if (freq < 4000) { + is_2ghz = 1; + } + + target_power_val_t2[ALL_TARGET_LEGACY_6_24] = + ar9300_eeprom_get_legacy_trgt_pwr( + ah, LEGACY_TARGET_RATE_6_24, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_LEGACY_36] = + ar9300_eeprom_get_legacy_trgt_pwr( + ah, LEGACY_TARGET_RATE_36, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_LEGACY_48] = + ar9300_eeprom_get_legacy_trgt_pwr( + ah, LEGACY_TARGET_RATE_48, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_LEGACY_54] = + ar9300_eeprom_get_legacy_trgt_pwr( + ah, LEGACY_TARGET_RATE_54, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_LEGACY_1L_5L] = + ar9300_eeprom_get_cck_trgt_pwr( + ah, LEGACY_TARGET_RATE_1L_5L, freq); + target_power_val_t2[ALL_TARGET_LEGACY_5S] = + ar9300_eeprom_get_cck_trgt_pwr( + ah, LEGACY_TARGET_RATE_5S, freq); + target_power_val_t2[ALL_TARGET_LEGACY_11L] = + ar9300_eeprom_get_cck_trgt_pwr( + ah, LEGACY_TARGET_RATE_11L, freq); + target_power_val_t2[ALL_TARGET_LEGACY_11S] = + ar9300_eeprom_get_cck_trgt_pwr( + ah, LEGACY_TARGET_RATE_11S, freq); + target_power_val_t2[ALL_TARGET_HT20_0_8_16] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_0_8_16, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_1_3_9_11_17_19] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_1_3_9_11_17_19, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_4] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_4, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_5] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_5, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_6] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_6, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_7] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_7, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_12] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_12, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_13] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_13, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_14] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_14, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_15] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_15, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_20] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_20, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_21] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_21, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_22] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_22, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT20_23] = + ar9300_eeprom_get_ht20_trgt_pwr( + ah, HT_TARGET_RATE_23, freq, is_2ghz); + target_power_val_t2[ALL_TARGET_HT40_0_8_16] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_0_8_16, freq, is_2ghz) + + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_1_3_9_11_17_19] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_1_3_9_11_17_19, freq, is_2ghz) + + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_4] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_4, freq, is_2ghz) + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_5] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_5, freq, is_2ghz) + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_6] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_6, freq, is_2ghz) + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_7] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_7, freq, is_2ghz) + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_12] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_12, freq, is_2ghz) + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_13] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_13, freq, is_2ghz) + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_14] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_14, freq, is_2ghz) + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_15] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_15, freq, is_2ghz) + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_20] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_20, freq, is_2ghz) + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_21] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_21, freq, is_2ghz) + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_22] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_22, freq, is_2ghz) + ht40_power_inc_for_pdadc; + target_power_val_t2[ALL_TARGET_HT40_23] = + ar9300_eeprom_get_ht40_trgt_pwr( + ah, HT_TARGET_RATE_23, freq, is_2ghz) + ht40_power_inc_for_pdadc; + +#ifdef AH_DEBUG + { + int i = 0; + + HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: APPLYING TARGET POWERS\n", __func__); + while (i < ar9300_rate_size) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: TPC[%02d] 0x%08x ", + __func__, i, target_power_val_t2[i]); + i++; + if (i == ar9300_rate_size) { + break; + } + HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: TPC[%02d] 0x%08x ", + __func__, i, target_power_val_t2[i]); + i++; + if (i == ar9300_rate_size) { + break; + } + HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: TPC[%02d] 0x%08x ", + __func__, i, target_power_val_t2[i]); + i++; + if (i == ar9300_rate_size) { + break; + } + HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: TPC[%02d] 0x%08x \n", + __func__, i, target_power_val_t2[i]); + i++; + } + } +#endif +} + +u_int16_t *ar9300_regulatory_domain_get(struct ath_hal *ah) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + return eep->base_eep_header.reg_dmn; +} + + +int32_t +ar9300_eeprom_write_enable_gpio_get(struct ath_hal *ah) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + return eep->base_eep_header.eeprom_write_enable_gpio; +} + +int32_t +ar9300_wlan_disable_gpio_get(struct ath_hal *ah) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + return eep->base_eep_header.wlan_disable_gpio; +} + +int32_t +ar9300_wlan_led_gpio_get(struct ath_hal *ah) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + return eep->base_eep_header.wlan_led_gpio; +} + +int32_t +ar9300_rx_band_select_gpio_get(struct ath_hal *ah) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + return eep->base_eep_header.rx_band_select_gpio; +} + +/* + * since valid noise floor values are negative, returns 1 on error + */ +int32_t +ar9300_noise_floor_cal_or_power_get(struct ath_hal *ah, int32_t frequency, + int32_t ichain, HAL_BOOL use_cal) +{ + int nf_use = 1; /* start with an error return value */ + int32_t fx[OSPREY_NUM_5G_CAL_PIERS + OSPREY_NUM_2G_CAL_PIERS]; + int32_t nf[OSPREY_NUM_5G_CAL_PIERS + OSPREY_NUM_2G_CAL_PIERS]; + int nnf; + int is_2ghz; + int ipier, npier; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + u_int8_t *p_cal_pier; + OSP_CAL_DATA_PER_FREQ_OP_LOOP *p_cal_pier_struct; + + /* + * check chain value + */ + if (ichain < 0 || ichain >= OSPREY_MAX_CHAINS) { + return 1; + } + + /* figure out which band we're using */ + is_2ghz = (frequency < 4000); + if (is_2ghz) { + npier = OSPREY_NUM_2G_CAL_PIERS; + p_cal_pier = eep->cal_freq_pier_2g; + p_cal_pier_struct = eep->cal_pier_data_2g[ichain]; + } else { + npier = OSPREY_NUM_5G_CAL_PIERS; + p_cal_pier = eep->cal_freq_pier_5g; + p_cal_pier_struct = eep->cal_pier_data_5g[ichain]; + } + /* look for valid noise floor values */ + nnf = 0; + for (ipier = 0; ipier < npier; ipier++) { + fx[nnf] = FBIN2FREQ(p_cal_pier[ipier], is_2ghz); + nf[nnf] = use_cal ? + p_cal_pier_struct[ipier].rx_noisefloor_cal : + p_cal_pier_struct[ipier].rx_noisefloor_power; + if (nf[nnf] < 0) { + nnf++; + } + } + /* + * If we have some valid values, interpolate to find the value + * at the desired frequency. + */ + if (nnf > 0) { + nf_use = interpolate(frequency, fx, nf, nnf); + } + + return nf_use; +} + +int32_t ar9300_rx_gain_index_get(struct ath_hal *ah) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + + return (eep->base_eep_header.txrxgain) & 0xf; /* bits 3:0 */ +} + + +int32_t ar9300_tx_gain_index_get(struct ath_hal *ah) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + + return (eep->base_eep_header.txrxgain >> 4) & 0xf; /* bits 7:4 */ +} + +HAL_BOOL ar9300_internal_regulator_apply(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int internal_regulator = ar9300_eeprom_get(ahp, EEP_INTERNAL_REGULATOR); + int reg_pmu1, reg_pmu2, reg_pmu1_set, reg_pmu2_set; + u_int32_t reg_PMU1, reg_PMU2; + unsigned long eep_addr; + u_int32_t reg_val, reg_usb = 0, reg_pmu = 0; + int usb_valid = 0, pmu_valid = 0; + unsigned char pmu_refv; + + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + reg_PMU1 = AR_PHY_PMU1_JUPITER; + reg_PMU2 = AR_PHY_PMU2_JUPITER; + } + else { + reg_PMU1 = AR_PHY_PMU1; + reg_PMU2 = AR_PHY_PMU2; + } + + if (internal_regulator) { + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah)) { + if (AR_SREV_HORNET(ah)) { + /* Read OTP first */ + for (eep_addr = 0x14; ; eep_addr -= 0x10) { + + ar9300_otp_read(ah, eep_addr / 4, ®_val, 1); + + if ((reg_val & 0x80) == 0x80){ + usb_valid = 1; + reg_usb = reg_val & 0x000000ff; + } + + if ((reg_val & 0x80000000) == 0x80000000){ + pmu_valid = 1; + reg_pmu = (reg_val & 0xff000000) >> 24; + } + + if (eep_addr == 0x4) { + break; + } + } + + if (pmu_valid) { + pmu_refv = reg_pmu & 0xf; + } else { + pmu_refv = 0x8; + } + + /* + * If (valid) { + * Usb_phy_ctrl2_tx_cal_en -> 0 + * Usb_phy_ctrl2_tx_cal_sel -> 0 + * Usb_phy_ctrl2_tx_man_cal -> 0, 1, 3, 7 or 15 from OTP + * } + */ + if (usb_valid) { + OS_REG_RMW_FIELD(ah, 0x16c88, AR_PHY_CTRL2_TX_CAL_EN, 0x0); + OS_REG_RMW_FIELD(ah, 0x16c88, AR_PHY_CTRL2_TX_CAL_SEL, 0x0); + OS_REG_RMW_FIELD(ah, 0x16c88, + AR_PHY_CTRL2_TX_MAN_CAL, (reg_usb & 0xf)); + } + + } else { + pmu_refv = 0x8; + } + /*#ifndef USE_HIF*/ + /* Follow the MDK settings for Hornet PMU. + * my $pwd = 0x0; + * my $Nfdiv = 0x3; # xtal_freq = 25MHz + * my $Nfdiv = 0x4; # xtal_freq = 40MHz + * my $Refv = 0x7; # 0x5:1.22V; 0x8:1.29V + * my $Gm1 = 0x3; #Poseidon $Gm1=1 + * my $classb = 0x0; + * my $Cc = 0x1; #Poseidon $Cc=7 + * my $Rc = 0x6; + * my $ramp_slope = 0x1; + * my $Segm = 0x3; + * my $use_local_osc = 0x0; + * my $force_xosc_stable = 0x0; + * my $Selfb = 0x0; #Poseidon $Selfb=1 + * my $Filterfb = 0x3; #Poseidon $Filterfb=0 + * my $Filtervc = 0x0; + * my $disc = 0x0; + * my $discdel = 0x4; + * my $spare = 0x0; + * $reg_PMU1 = + * $pwd | ($Nfdiv<<1) | ($Refv<<4) | ($Gm1<<8) | + * ($classb<<11) | ($Cc<<14) | ($Rc<<17) | ($ramp_slope<<20) | + * ($Segm<<24) | ($use_local_osc<<26) | + * ($force_xosc_stable<<27) | ($Selfb<<28) | ($Filterfb<<29); + * $reg_PMU2 = $handle->reg_rd("ch0_PMU2"); + * $reg_PMU2 = ($reg_PMU2 & 0xfe3fffff) | ($Filtervc<<22); + * $reg_PMU2 = ($reg_PMU2 & 0xe3ffffff) | ($discdel<<26); + * $reg_PMU2 = ($reg_PMU2 & 0x1fffffff) | ($spare<<29); + */ + if (ahp->clk_25mhz) { + reg_pmu1_set = 0 | + (3 << 1) | (pmu_refv << 4) | (3 << 8) | (0 << 11) | + (1 << 14) | (6 << 17) | (1 << 20) | (3 << 24) | + (0 << 26) | (0 << 27) | (0 << 28) | (0 << 29); + } else { + if (AR_SREV_POSEIDON(ah)) { + reg_pmu1_set = 0 | + (5 << 1) | (7 << 4) | (2 << 8) | (0 << 11) | + (2 << 14) | (6 << 17) | (1 << 20) | (3 << 24) | + (0 << 26) | (0 << 27) | (1 << 28) | (0 << 29) ; + } else { + reg_pmu1_set = 0 | + (4 << 1) | (7 << 4) | (3 << 8) | (0 << 11) | + (1 << 14) | (6 << 17) | (1 << 20) | (3 << 24) | + (0 << 26) | (0 << 27) | (0 << 28) | (0 << 29) ; + } + } + OS_REG_RMW_FIELD(ah, reg_PMU2, AR_PHY_PMU2_PGM, 0x0); + + OS_REG_WRITE(ah, reg_PMU1, reg_pmu1_set); /* 0x638c8376 */ + reg_pmu1 = OS_REG_READ(ah, reg_PMU1); + while (reg_pmu1 != reg_pmu1_set) { + OS_REG_WRITE(ah, reg_PMU1, reg_pmu1_set); /* 0x638c8376 */ + OS_DELAY(10); + reg_pmu1 = OS_REG_READ(ah, reg_PMU1); + } + + reg_pmu2_set = + (OS_REG_READ(ah, reg_PMU2) & (~0xFFC00000)) | (4 << 26); + OS_REG_WRITE(ah, reg_PMU2, reg_pmu2_set); + reg_pmu2 = OS_REG_READ(ah, reg_PMU2); + while (reg_pmu2 != reg_pmu2_set) { + OS_REG_WRITE(ah, reg_PMU2, reg_pmu2_set); + OS_DELAY(10); + reg_pmu2 = OS_REG_READ(ah, reg_PMU2); + } + reg_pmu2_set = + (OS_REG_READ(ah, reg_PMU2) & (~0x00200000)) | (1 << 21); + OS_REG_WRITE(ah, reg_PMU2, reg_pmu2_set); + reg_pmu2 = OS_REG_READ(ah, reg_PMU2); + while (reg_pmu2 != reg_pmu2_set) { + OS_REG_WRITE(ah, reg_PMU2, reg_pmu2_set); + OS_DELAY(10); + reg_pmu2 = OS_REG_READ(ah, reg_PMU2); + } + /*#endif*/ + } else if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + /* Internal regulator is ON. Write swreg register. */ + int swreg = ar9300_eeprom_get(ahp, EEP_SWREG); + OS_REG_WRITE(ah, reg_PMU1, swreg); + } else { + /* Internal regulator is ON. Write swreg register. */ + int swreg = ar9300_eeprom_get(ahp, EEP_SWREG); + OS_REG_WRITE(ah, AR_RTC_REG_CONTROL1, + OS_REG_READ(ah, AR_RTC_REG_CONTROL1) & + (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM)); + OS_REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg); + /* Set REG_CONTROL1.SWREG_PROGRAM */ + OS_REG_WRITE(ah, AR_RTC_REG_CONTROL1, + OS_REG_READ(ah, AR_RTC_REG_CONTROL1) | + AR_RTC_REG_CONTROL1_SWREG_PROGRAM); + } + } else { + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah)) { + OS_REG_RMW_FIELD(ah, reg_PMU2, AR_PHY_PMU2_PGM, 0x0); + reg_pmu2 = OS_REG_READ_FIELD(ah, reg_PMU2, AR_PHY_PMU2_PGM); + while (reg_pmu2) { + OS_DELAY(10); + reg_pmu2 = OS_REG_READ_FIELD(ah, reg_PMU2, AR_PHY_PMU2_PGM); + } + OS_REG_RMW_FIELD(ah, reg_PMU1, AR_PHY_PMU1_PWD, 0x1); + reg_pmu1 = OS_REG_READ_FIELD(ah, reg_PMU1, AR_PHY_PMU1_PWD); + while (!reg_pmu1) { + OS_DELAY(10); + reg_pmu1 = OS_REG_READ_FIELD(ah, reg_PMU1, AR_PHY_PMU1_PWD); + } + OS_REG_RMW_FIELD(ah, reg_PMU2, AR_PHY_PMU2_PGM, 0x1); + reg_pmu2 = OS_REG_READ_FIELD(ah, reg_PMU2, AR_PHY_PMU2_PGM); + while (!reg_pmu2) { + OS_DELAY(10); + reg_pmu2 = OS_REG_READ_FIELD(ah, reg_PMU2, AR_PHY_PMU2_PGM); + } + } else if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_RMW_FIELD(ah, reg_PMU1, AR_PHY_PMU1_PWD, 0x1); + } else { + OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, + (OS_REG_READ(ah, AR_RTC_SLEEP_CLK) | + AR_RTC_FORCE_SWREG_PRD | AR_RTC_PCIE_RST_PWDN_EN)); + } + } + + return 0; +} + +HAL_BOOL ar9300_drive_strength_apply(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int drive_strength; + unsigned long reg; + + drive_strength = ar9300_eeprom_get(ahp, EEP_DRIVE_STRENGTH); + if (drive_strength) { + reg = OS_REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); + reg &= ~0x00ffffc0; + reg |= 0x5 << 21; + reg |= 0x5 << 18; + reg |= 0x5 << 15; + reg |= 0x5 << 12; + reg |= 0x5 << 9; + reg |= 0x5 << 6; + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg); + + reg = OS_REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); + reg &= ~0xffffffe0; + reg |= 0x5 << 29; + reg |= 0x5 << 26; + reg |= 0x5 << 23; + reg |= 0x5 << 20; + reg |= 0x5 << 17; + reg |= 0x5 << 14; + reg |= 0x5 << 11; + reg |= 0x5 << 8; + reg |= 0x5 << 5; + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg); + + reg = OS_REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); + reg &= ~0xff800000; + reg |= 0x5 << 29; + reg |= 0x5 << 26; + reg |= 0x5 << 23; + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); + } + return 0; +} + +int32_t ar9300_xpa_bias_level_get(struct ath_hal *ah, HAL_BOOL is_2ghz) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + if (is_2ghz) { + return eep->modal_header_2g.xpa_bias_lvl; + } else { + return eep->modal_header_5g.xpa_bias_lvl; + } +} + +HAL_BOOL ar9300_xpa_bias_level_apply(struct ath_hal *ah, HAL_BOOL is_2ghz) +{ + /* + * In ar9330 emu, we can't access radio registers, + * merlin is used for radio part. + */ + int bias; + bias = ar9300_xpa_bias_level_get(ah, is_2ghz); + + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah)) { + OS_REG_RMW_FIELD(ah, + AR_HORNET_CH0_TOP2, AR_HORNET_CH0_TOP2_XPABIASLVL, bias); + } else if (AR_SREV_SCORPION(ah)) { + OS_REG_RMW_FIELD(ah, + AR_SCORPION_CH0_TOP, AR_SCORPION_CH0_TOP_XPABIASLVL, bias); + } else if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_TOP_JUPITER, AR_PHY_65NM_CH0_TOP_XPABIASLVL, bias); + } else { + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_TOP, AR_PHY_65NM_CH0_TOP_XPABIASLVL, bias); + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_THERM, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB, + bias >> 2); + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_THERM, AR_PHY_65NM_CH0_THERM_XPASHORT2GND, 1); + } + return 0; +} + +u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + if (is_2ghz) { + return eep->modal_header_2g.ant_ctrl_common; + } else { + return eep->modal_header_5g.ant_ctrl_common; + } +} +static u_int16_t +ar9300_switch_com_spdt_get(struct ath_hal *ah, HAL_BOOL is_2ghz) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + if (is_2ghz) { + return eep->modal_header_2g.switchcomspdt; + } else { + return eep->modal_header_5g.switchcomspdt; + } +} +u_int32_t ar9300_ant_ctrl_common2_get(struct ath_hal *ah, HAL_BOOL is_2ghz) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + if (is_2ghz) { + return eep->modal_header_2g.ant_ctrl_common2; + } else { + return eep->modal_header_5g.ant_ctrl_common2; + } +} + +u_int16_t ar9300_ant_ctrl_chain_get(struct ath_hal *ah, int chain, + HAL_BOOL is_2ghz) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + if (chain >= 0 && chain < OSPREY_MAX_CHAINS) { + if (is_2ghz) { + return eep->modal_header_2g.ant_ctrl_chain[chain]; + } else { + return eep->modal_header_5g.ant_ctrl_chain[chain]; + } + } + return 0; +} + +HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz) +{ + u_int32_t value; + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t regval; + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); +#if ATH_ANT_DIV_COMB + HAL_CAPABILITIES *pcap = &ahpriv->ah_caps; +#endif /* ATH_ANT_DIV_COMB */ + u_int32_t xlan_gpio_cfg; + u_int8_t i; + + if (AR_SREV_POSEIDON(ah)) { + xlan_gpio_cfg = ahpriv->ah_config.ath_hal_ext_lna_ctl_gpio; + if (xlan_gpio_cfg) { + for (i = 0; i < 32; i++) { + if (xlan_gpio_cfg & (1 << i)) { + ath_hal_gpio_cfg_output(ah, i, + HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED); + } + } + } + } +#define AR_SWITCH_TABLE_COM_ALL (0xffff) +#define AR_SWITCH_TABLE_COM_ALL_S (0) +#define AR_SWITCH_TABLE_COM_JUPITER_ALL (0xffffff) +#define AR_SWITCH_TABLE_COM_JUPITER_ALL_S (0) +#define AR_SWITCH_TABLE_COM_SCORPION_ALL (0xffffff) +#define AR_SWITCH_TABLE_COM_SCORPION_ALL_S (0) +#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000) + value = ar9300_ant_ctrl_common_get(ah, is_2ghz); + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + if (AR_SREV_JUPITER_10(ah)) { + /* Force SPDT setting for Jupiter 1.0 chips. */ + value &= ~AR_SWITCH_TABLE_COM_SPDT; + value |= 0x00100000; + } + OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, + AR_SWITCH_TABLE_COM_JUPITER_ALL, value); + } + else if (AR_SREV_SCORPION(ah)) { + OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, + AR_SWITCH_TABLE_COM_SCORPION_ALL, value); + } + else { + OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, + AR_SWITCH_TABLE_COM_ALL, value); + } +/* +* Jupiter2.0 defines new switch table for BT/WLAN, +* here's new field name in WB222.ref for both 2G and 5G. +* Register: [GLB_CONTROL] GLB_CONTROL (@0x20044) +* 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX SWITCH_TABLE_COM_SPDT_WLAN_RX +* 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX SWITCH_TABLE_COM_SPDT_WLAN_TX +* 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE SWITCH_TABLE_COM_SPDT_WLAN_IDLE +*/ +#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0) +#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4) + if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { + value = ar9300_switch_com_spdt_get(ah, is_2ghz); + OS_REG_RMW_FIELD(ah, AR_GLB_CONTROL, + AR_SWITCH_TABLE_COM_SPDT_ALL, value); + + OS_REG_SET_BIT(ah, AR_GLB_CONTROL, + AR_BTCOEX_CTRL_SPDT_ENABLE); + //OS_REG_SET_BIT(ah, AR_GLB_CONTROL, + // AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); + } + +#define AR_SWITCH_TABLE_COM2_ALL (0xffffff) +#define AR_SWITCH_TABLE_COM2_ALL_S (0) + value = ar9300_ant_ctrl_common2_get(ah, is_2ghz); +#if ATH_ANT_DIV_COMB + if ( AR_SREV_POSEIDON(ah) && (ahp->ah_lna_div_use_bt_ant_enable == TRUE) ) { + value &= ~AR_SWITCH_TABLE_COM2_ALL; + value |= ahpriv->ah_config.ath_hal_ant_ctrl_comm2g_switch_enable; + } +#endif /* ATH_ANT_DIV_COMB */ + OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value); + +#define AR_SWITCH_TABLE_ALL (0xfff) +#define AR_SWITCH_TABLE_ALL_S (0) + value = ar9300_ant_ctrl_chain_get(ah, 0, is_2ghz); + OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value); + + if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah) && !AR_SREV_APHRODITE(ah)) { + value = ar9300_ant_ctrl_chain_get(ah, 1, is_2ghz); + OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value); + + if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) { + value = ar9300_ant_ctrl_chain_get(ah, 2, is_2ghz); + OS_REG_RMW_FIELD(ah, + AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value); + } + } + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah)) { + value = ar9300_eeprom_get(ahp, EEP_ANTDIV_control); + /* main_lnaconf, alt_lnaconf, main_tb, alt_tb */ + regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); + regval &= (~ANT_DIV_CONTROL_ALL); /* clear bit 25~30 */ + regval |= (value & 0x3f) << ANT_DIV_CONTROL_ALL_S; + /* enable_lnadiv */ + regval &= (~MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MASK); + regval |= ((value >> 6) & 0x1) << + MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__SHIFT; +#if ATH_ANT_DIV_COMB + if ( AR_SREV_POSEIDON(ah) && (ahp->ah_lna_div_use_bt_ant_enable == TRUE) ) { + regval |= ANT_DIV_ENABLE; + } +#endif /* ATH_ANT_DIV_COMB */ + OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); + + /* enable fast_div */ + regval = OS_REG_READ(ah, AR_PHY_CCK_DETECT); + regval &= (~BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MASK); + regval |= ((value >> 7) & 0x1) << + BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SHIFT; +#if ATH_ANT_DIV_COMB + if ( AR_SREV_POSEIDON(ah) && (ahp->ah_lna_div_use_bt_ant_enable == TRUE) ) { + regval |= FAST_DIV_ENABLE; + } +#endif /* ATH_ANT_DIV_COMB */ + OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); + } + +#if ATH_ANT_DIV_COMB + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { + if (pcap->hal_ant_div_comb_support) { + /* If support DivComb, set MAIN to LNA1, ALT to LNA2 at beginning */ + regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); + /* clear bit 25~30 main_lnaconf, alt_lnaconf, main_tb, alt_tb */ + regval &= (~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK)); + regval |= (HAL_ANT_DIV_COMB_LNA1 << + MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__SHIFT); + regval |= (HAL_ANT_DIV_COMB_LNA2 << + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__SHIFT); + OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); + } + + } +#endif /* ATH_ANT_DIV_COMB */ + if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A + || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) + { + u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); + reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | + MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK ); + + switch (ahp->ah_diversity_control) { + case HAL_ANT_FIXED_A: + /* Enable first antenna only */ + reg_val |= (HAL_ANT_DIV_COMB_LNA1 << + MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__SHIFT); + reg_val |= (HAL_ANT_DIV_COMB_LNA2 << + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__SHIFT); + /* main/alt gain table and Fast Div Bias all set to 0 */ + OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); + regval = OS_REG_READ(ah, AR_PHY_CCK_DETECT); + regval &= (~BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MASK); + OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); + break; + case HAL_ANT_FIXED_B: + /* Enable second antenna only, after checking capability */ + reg_val |= (HAL_ANT_DIV_COMB_LNA2 << + MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__SHIFT); + reg_val |= (HAL_ANT_DIV_COMB_LNA1 << + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__SHIFT); + /* main/alt gain table and Fast Div all set to 0 */ + OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); + regval = OS_REG_READ(ah, AR_PHY_CCK_DETECT); + regval &= (~BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MASK); + OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); + /* For WB225, need to swith ANT2 from BT to Wifi + * This will not affect HB125 LNA diversity feature. + */ + OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, + ahpriv->ah_config.ath_hal_ant_ctrl_comm2g_switch_enable); + break; + default: + break; + } + } + return 0; +} + +static u_int16_t +ar9300_attenuation_chain_get(struct ath_hal *ah, int chain, u_int16_t channel) +{ + int32_t f[3], t[3]; + u_int16_t value; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + if (chain >= 0 && chain < OSPREY_MAX_CHAINS) { + if (channel < 4000) { + return eep->modal_header_2g.xatten1_db[chain]; + } else { + if (eep->base_ext2.xatten1_db_low[chain] != 0) { + t[0] = eep->base_ext2.xatten1_db_low[chain]; + f[0] = 5180; + t[1] = eep->modal_header_5g.xatten1_db[chain]; + f[1] = 5500; + t[2] = eep->base_ext2.xatten1_db_high[chain]; + f[2] = 5785; + value = interpolate(channel, f, t, 3); + return value; + } else { + return eep->modal_header_5g.xatten1_db[chain]; + } + } + } + return 0; +} + +static u_int16_t +ar9300_attenuation_margin_chain_get(struct ath_hal *ah, int chain, + u_int16_t channel) +{ + int32_t f[3], t[3]; + u_int16_t value; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + if (chain >= 0 && chain < OSPREY_MAX_CHAINS) { + if (channel < 4000) { + return eep->modal_header_2g.xatten1_margin[chain]; + } else { + if (eep->base_ext2.xatten1_margin_low[chain] != 0) { + t[0] = eep->base_ext2.xatten1_margin_low[chain]; + f[0] = 5180; + t[1] = eep->modal_header_5g.xatten1_margin[chain]; + f[1] = 5500; + t[2] = eep->base_ext2.xatten1_margin_high[chain]; + f[2] = 5785; + value = interpolate(channel, f, t, 3); + return value; + } else { + return eep->modal_header_5g.xatten1_margin[chain]; + } + } + } + return 0; +} + +HAL_BOOL ar9300_attenuation_apply(struct ath_hal *ah, u_int16_t channel) +{ + u_int32_t value; + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + + /* Test value. if 0 then attenuation is unused. Don't load anything. */ + value = ar9300_attenuation_chain_get(ah, 0, channel); + OS_REG_RMW_FIELD(ah, + AR_PHY_EXT_ATTEN_CTL_0, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value); + value = ar9300_attenuation_margin_chain_get(ah, 0, channel); + if (ar9300_rx_gain_index_get(ah) == 0 + && ahpriv->ah_config.ath_hal_ext_atten_margin_cfg) + { + value = 5; + } + OS_REG_RMW_FIELD(ah, + AR_PHY_EXT_ATTEN_CTL_0, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value); + + if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah)) { + value = ar9300_attenuation_chain_get(ah, 1, channel); + OS_REG_RMW_FIELD(ah, + AR_PHY_EXT_ATTEN_CTL_1, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value); + value = ar9300_attenuation_margin_chain_get(ah, 1, channel); + OS_REG_RMW_FIELD(ah, + AR_PHY_EXT_ATTEN_CTL_1, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, + value); + if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) { + value = ar9300_attenuation_chain_get(ah, 2, channel); + OS_REG_RMW_FIELD(ah, + AR_PHY_EXT_ATTEN_CTL_2, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value); + value = ar9300_attenuation_margin_chain_get(ah, 2, channel); + OS_REG_RMW_FIELD(ah, + AR_PHY_EXT_ATTEN_CTL_2, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, + value); + } + } + return 0; +} + +static u_int16_t ar9300_quick_drop_get(struct ath_hal *ah, + int chain, u_int16_t channel) +{ + int32_t f[3], t[3]; + u_int16_t value; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + + if (channel < 4000) { + return eep->modal_header_2g.quick_drop; + } else { + t[0] = eep->base_ext1.quick_drop_low; + f[0] = 5180; + t[1] = eep->modal_header_5g.quick_drop; + f[1] = 5500; + t[2] = eep->base_ext1.quick_drop_high; + f[2] = 5785; + value = interpolate(channel, f, t, 3); + return value; + } +} + + +static HAL_BOOL ar9300_quick_drop_apply(struct ath_hal *ah, u_int16_t channel) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + u_int32_t value; + // + // Test value. if 0 then quickDrop is unused. Don't load anything. + // + if (eep->base_eep_header.misc_configuration & 0x10) + { + if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah) || AR_SREV_WASP(ah)) + { + value = ar9300_quick_drop_get(ah, 0, channel); + OS_REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, value); + } + } + return 0; +} + +static u_int16_t ar9300_tx_end_to_xpa_off_get(struct ath_hal *ah, u_int16_t channel) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + + if (channel < 4000) { + return eep->modal_header_2g.tx_end_to_xpa_off; + } else { + return eep->modal_header_5g.tx_end_to_xpa_off; + } +} + +static HAL_BOOL ar9300_tx_end_to_xpab_off_apply(struct ath_hal *ah, u_int16_t channel) +{ + u_int32_t value; + + value = ar9300_tx_end_to_xpa_off_get(ah, channel); + /* Apply to both xpaa and xpab */ + if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah) || AR_SREV_WASP(ah)) + { + OS_REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, + AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value); + OS_REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, + AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value); + } + return 0; +} + +static int +ar9300_eeprom_cal_pier_get(struct ath_hal *ah, int mode, int ipier, int ichain, + int *pfrequency, int *pcorrection, int *ptemperature, int *pvoltage) +{ + u_int8_t *p_cal_pier; + OSP_CAL_DATA_PER_FREQ_OP_LOOP *p_cal_pier_struct; + int is_2ghz; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + + if (ichain >= OSPREY_MAX_CHAINS) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: Invalid chain index, must be less than %d\n", + __func__, OSPREY_MAX_CHAINS); + return -1; + } + + if (mode) {/* 5GHz */ + if (ipier >= OSPREY_NUM_5G_CAL_PIERS){ + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: Invalid 5GHz cal pier index, must be less than %d\n", + __func__, OSPREY_NUM_5G_CAL_PIERS); + return -1; + } + p_cal_pier = &(eep->cal_freq_pier_5g[ipier]); + p_cal_pier_struct = &(eep->cal_pier_data_5g[ichain][ipier]); + is_2ghz = 0; + } else { + if (ipier >= OSPREY_NUM_2G_CAL_PIERS){ + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: Invalid 2GHz cal pier index, must be less than %d\n", + __func__, OSPREY_NUM_2G_CAL_PIERS); + return -1; + } + + p_cal_pier = &(eep->cal_freq_pier_2g[ipier]); + p_cal_pier_struct = &(eep->cal_pier_data_2g[ichain][ipier]); + is_2ghz = 1; + } + *pfrequency = FBIN2FREQ(*p_cal_pier, is_2ghz); + *pcorrection = p_cal_pier_struct->ref_power; + *ptemperature = p_cal_pier_struct->temp_meas; + *pvoltage = p_cal_pier_struct->volt_meas; + return 0; +} + +/* + * Apply the recorded correction values. + */ +static int +ar9300_calibration_apply(struct ath_hal *ah, int frequency) +{ + int ichain, ipier, npier; + int mode; + int fdiff; + int pfrequency, pcorrection, ptemperature, pvoltage; + int bf, factor, plus; + + int lfrequency[AR9300_MAX_CHAINS]; + int hfrequency[AR9300_MAX_CHAINS]; + + int lcorrection[AR9300_MAX_CHAINS]; + int hcorrection[AR9300_MAX_CHAINS]; + int correction[AR9300_MAX_CHAINS]; + + int ltemperature[AR9300_MAX_CHAINS]; + int htemperature[AR9300_MAX_CHAINS]; + int temperature[AR9300_MAX_CHAINS]; + + int lvoltage[AR9300_MAX_CHAINS]; + int hvoltage[AR9300_MAX_CHAINS]; + int voltage[AR9300_MAX_CHAINS]; + + mode = (frequency >= 4000); + npier = (mode) ? OSPREY_NUM_5G_CAL_PIERS : OSPREY_NUM_2G_CAL_PIERS; + + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { + lfrequency[ichain] = 0; + hfrequency[ichain] = 100000; + } + /* + * identify best lower and higher frequency calibration measurement + */ + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { + for (ipier = 0; ipier < npier; ipier++) { + if (ar9300_eeprom_cal_pier_get( + ah, mode, ipier, ichain, + &pfrequency, &pcorrection, &ptemperature, &pvoltage) == 0) + { + fdiff = frequency - pfrequency; + /* + * this measurement is higher than our desired frequency + */ + if (fdiff <= 0) { + if (hfrequency[ichain] <= 0 || + hfrequency[ichain] >= 100000 || + fdiff > (frequency - hfrequency[ichain])) + { + /* + * new best higher frequency measurement + */ + hfrequency[ichain] = pfrequency; + hcorrection[ichain] = pcorrection; + htemperature[ichain] = ptemperature; + hvoltage[ichain] = pvoltage; + } + } + if (fdiff >= 0) { + if (lfrequency[ichain] <= 0 || + fdiff < (frequency - lfrequency[ichain])) + { + /* + * new best lower frequency measurement + */ + lfrequency[ichain] = pfrequency; + lcorrection[ichain] = pcorrection; + ltemperature[ichain] = ptemperature; + lvoltage[ichain] = pvoltage; + } + } + } + } + } + /* interpolate */ + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: ch=%d f=%d low=%d %d h=%d %d\n", + __func__, ichain, frequency, + lfrequency[ichain], lcorrection[ichain], + hfrequency[ichain], hcorrection[ichain]); + /* + * they're the same, so just pick one + */ + if (hfrequency[ichain] == lfrequency[ichain]) { + correction[ichain] = lcorrection[ichain]; + voltage[ichain] = lvoltage[ichain]; + temperature[ichain] = ltemperature[ichain]; + } else if (frequency - lfrequency[ichain] < 1000) { + /* the low frequency is good */ + if (hfrequency[ichain] - frequency < 1000) { + /* + * The high frequency is good too - + * interpolate with round off. + */ + int mult, div, diff; + mult = frequency - lfrequency[ichain]; + div = hfrequency[ichain] - lfrequency[ichain]; + + diff = hcorrection[ichain] - lcorrection[ichain]; + bf = 2 * diff * mult / div; + plus = (bf % 2); + factor = bf / 2; + correction[ichain] = lcorrection[ichain] + factor + plus; + + diff = htemperature[ichain] - ltemperature[ichain]; + bf = 2 * diff * mult / div; + plus = (bf % 2); + factor = bf / 2; + temperature[ichain] = ltemperature[ichain] + factor + plus; + + diff = hvoltage[ichain] - lvoltage[ichain]; + bf = 2 * diff * mult / div; + plus = (bf % 2); + factor = bf / 2; + voltage[ichain] = lvoltage[ichain] + factor + plus; + } else { + /* only low is good, use it */ + correction[ichain] = lcorrection[ichain]; + temperature[ichain] = ltemperature[ichain]; + voltage[ichain] = lvoltage[ichain]; + } + } else if (hfrequency[ichain] - frequency < 1000) { + /* only high is good, use it */ + correction[ichain] = hcorrection[ichain]; + temperature[ichain] = htemperature[ichain]; + voltage[ichain] = hvoltage[ichain]; + } else { + /* nothing is good, presume 0???? */ + correction[ichain] = 0; + temperature[ichain] = 0; + voltage[ichain] = 0; + } + } + + /* GreenTx */ + if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable) { + if (AR_SREV_POSEIDON(ah)) { + /* Get calibrated OLPC gain delta value for GreenTx */ + AH_PRIVATE(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET] = + (u_int32_t) correction[0]; + } + } + + ar9300_power_control_override( + ah, frequency, correction, voltage, temperature); + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: for frequency=%d, calibration correction = %d %d %d\n", + __func__, frequency, correction[0], correction[1], correction[2]); + + return 0; +} + +int +ar9300_power_control_override(struct ath_hal *ah, int frequency, + int *correction, int *voltage, int *temperature) +{ + int temp_slope = 0; + int temp_slope_1 = 0; + int temp_slope_2 = 0; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + int32_t f[8], t[8],t1[3], t2[3]; + int i; + + OS_REG_RMW(ah, AR_PHY_TPC_11_B0, + (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), + AR_PHY_TPC_OLPC_GAIN_DELTA); + if (!AR_SREV_POSEIDON(ah)) { + OS_REG_RMW(ah, AR_PHY_TPC_11_B1, + (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), + AR_PHY_TPC_OLPC_GAIN_DELTA); + if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) { + OS_REG_RMW(ah, AR_PHY_TPC_11_B2, + (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), + AR_PHY_TPC_OLPC_GAIN_DELTA); + } + } + /* + * enable open loop power control on chip + */ + OS_REG_RMW(ah, AR_PHY_TPC_6_B0, + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), AR_PHY_TPC_6_ERROR_EST_MODE); + if (!AR_SREV_POSEIDON(ah)) { + OS_REG_RMW(ah, AR_PHY_TPC_6_B1, + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), AR_PHY_TPC_6_ERROR_EST_MODE); + if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) { + OS_REG_RMW(ah, AR_PHY_TPC_6_B2, + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), + AR_PHY_TPC_6_ERROR_EST_MODE); + } + } + + /* + * Enable temperature compensation + * Need to use register names + */ + if (frequency < 4000) { + temp_slope = eep->modal_header_2g.temp_slope; + } else { + if ((eep->base_eep_header.misc_configuration & 0x20) != 0) + { + for(i=0;i<8;i++) + { + t[i]=eep->base_ext1.tempslopextension[i]; + f[i]=FBIN2FREQ(eep->cal_freq_pier_5g[i], 0); + } + temp_slope=interpolate(frequency,f,t,8); + } + else + { + if(!AR_SREV_SCORPION(ah)) { + if (eep->base_ext2.temp_slope_low != 0) { + t[0] = eep->base_ext2.temp_slope_low; + f[0] = 5180; + t[1] = eep->modal_header_5g.temp_slope; + f[1] = 5500; + t[2] = eep->base_ext2.temp_slope_high; + f[2] = 5785; + temp_slope = interpolate(frequency, f, t, 3); + } else { + temp_slope = eep->modal_header_5g.temp_slope; + } + } else { + /* + * Scorpion has individual chain tempslope values + */ + t[0] = eep->base_ext1.tempslopextension[2]; + t1[0]= eep->base_ext1.tempslopextension[3]; + t2[0]= eep->base_ext1.tempslopextension[4]; + f[0] = 5180; + t[1] = eep->modal_header_5g.temp_slope; + t1[1]= eep->base_ext1.tempslopextension[0]; + t2[1]= eep->base_ext1.tempslopextension[1]; + f[1] = 5500; + t[2] = eep->base_ext1.tempslopextension[5]; + t1[2]= eep->base_ext1.tempslopextension[6]; + t2[2]= eep->base_ext1.tempslopextension[7]; + f[2] = 5785; + temp_slope = interpolate(frequency, f, t, 3); + temp_slope_1=interpolate(frequency, f, t1,3); + temp_slope_2=interpolate(frequency, f, t2,3); + } + } + } + + if (!AR_SREV_SCORPION(ah)) { + OS_REG_RMW_FIELD(ah, + AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, temp_slope); + } else { + /*Scorpion has tempSlope register for each chain*/ + /*Check whether temp_compensation feature is enabled or not*/ + if (eep->base_eep_header.feature_enable & 0x1){ + if(frequency < 4000) { + OS_REG_RMW_FIELD(ah, + AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, + eep->base_ext2.temp_slope_low); + OS_REG_RMW_FIELD(ah, + AR_SCORPION_PHY_TPC_19_B1, AR_PHY_TPC_19_ALPHA_THERM, + temp_slope); + OS_REG_RMW_FIELD(ah, + AR_SCORPION_PHY_TPC_19_B2, AR_PHY_TPC_19_ALPHA_THERM, + eep->base_ext2.temp_slope_high); + } else { + OS_REG_RMW_FIELD(ah, + AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, + temp_slope); + OS_REG_RMW_FIELD(ah, + AR_SCORPION_PHY_TPC_19_B1, AR_PHY_TPC_19_ALPHA_THERM, + temp_slope_1); + OS_REG_RMW_FIELD(ah, + AR_SCORPION_PHY_TPC_19_B2, AR_PHY_TPC_19_ALPHA_THERM, + temp_slope_2); + } + }else { + /* If temp compensation is not enabled, set all registers to 0*/ + OS_REG_RMW_FIELD(ah, + AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, 0); + OS_REG_RMW_FIELD(ah, + AR_SCORPION_PHY_TPC_19_B1, AR_PHY_TPC_19_ALPHA_THERM, 0); + OS_REG_RMW_FIELD(ah, + AR_SCORPION_PHY_TPC_19_B2, AR_PHY_TPC_19_ALPHA_THERM, 0); + } + } + OS_REG_RMW_FIELD(ah, + AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, temperature[0]); + + return 0; +} + +/************************************************************** + * ar9300_eep_def_get_max_edge_power + * + * Find the maximum conformance test limit for the given channel and CTL info + */ +static inline u_int16_t +ar9300_eep_def_get_max_edge_power(ar9300_eeprom_t *p_eep_data, u_int16_t freq, + int idx, HAL_BOOL is_2ghz) +{ + u_int16_t twice_max_edge_power = AR9300_MAX_RATE_POWER; + u_int8_t *ctl_freqbin = is_2ghz ? + &p_eep_data->ctl_freqbin_2G[idx][0] : + &p_eep_data->ctl_freqbin_5G[idx][0]; + u_int16_t num_edges = is_2ghz ? + OSPREY_NUM_BAND_EDGES_2G : OSPREY_NUM_BAND_EDGES_5G; + int i; + + /* Get the edge power */ + for (i = 0; (i < num_edges) && (ctl_freqbin[i] != AR9300_BCHAN_UNUSED); i++) + { + /* + * If there's an exact channel match or an inband flag set + * on the lower channel use the given rd_edge_power + */ + if (freq == fbin2freq(ctl_freqbin[i], is_2ghz)) { + if (is_2ghz) { + twice_max_edge_power = + p_eep_data->ctl_power_data_2g[idx].ctl_edges[i].t_power; + } else { + twice_max_edge_power = + p_eep_data->ctl_power_data_5g[idx].ctl_edges[i].t_power; + } + break; + } else if ((i > 0) && (freq < fbin2freq(ctl_freqbin[i], is_2ghz))) { + if (is_2ghz) { + if (fbin2freq(ctl_freqbin[i - 1], 1) < freq && + p_eep_data->ctl_power_data_2g[idx].ctl_edges[i - 1].flag) + { + twice_max_edge_power = + p_eep_data->ctl_power_data_2g[idx]. + ctl_edges[i - 1].t_power; + } + } else { + if (fbin2freq(ctl_freqbin[i - 1], 0) < freq && + p_eep_data->ctl_power_data_5g[idx].ctl_edges[i - 1].flag) + { + twice_max_edge_power = + p_eep_data->ctl_power_data_5g[idx]. + ctl_edges[i - 1].t_power; + } + } + /* + * Leave loop - no more affecting edges possible + * in this monotonic increasing list + */ + break; + } + } + /* + * EV89475: EEPROM might contain 0 txpower in CTL table for certain + * 2.4GHz channels. We workaround it by overwriting 60 (30 dBm) here. + */ + if (is_2ghz && (twice_max_edge_power == 0)) { + twice_max_edge_power = 60; + } + + HALASSERT(twice_max_edge_power > 0); + return twice_max_edge_power; +} + +HAL_BOOL +ar9300_eeprom_set_power_per_rate_table( + struct ath_hal *ah, + ar9300_eeprom_t *p_eep_data, + HAL_CHANNEL_INTERNAL *chan, + u_int8_t *p_pwr_array, + u_int16_t cfg_ctl, + u_int16_t antenna_reduction, + u_int16_t twice_max_regulatory_power, + u_int16_t power_limit, + u_int8_t chainmask) +{ + /* Local defines to distinguish between extension and control CTL's */ +#define EXT_ADDITIVE (0x8000) +#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) +#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) +#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) +#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ +#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ +#define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */ +#define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */ +#define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */ + + static const u_int16_t tp_scale_reduction_table[5] = + { 0, 3, 6, 9, AR9300_MAX_RATE_POWER }; + int i; + int16_t twice_largest_antenna; + u_int16_t twice_antenna_reduction = 2*antenna_reduction ; + int16_t scaled_power = 0, min_ctl_power, max_reg_allowed_power; +#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ +#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ + u_int16_t ctl_modes_for11a[] = + {CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40}; + u_int16_t ctl_modes_for11g[] = + {CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40}; + u_int16_t num_ctl_modes, *p_ctl_mode, ctl_mode, freq; + CHAN_CENTERS centers; + int tx_chainmask; + struct ath_hal_9300 *ahp = AH9300(ah); + u_int8_t *ctl_index; + u_int8_t ctl_num; + u_int16_t twice_min_edge_power; + u_int16_t twice_max_edge_power = AR9300_MAX_RATE_POWER; + + tx_chainmask = chainmask ? chainmask : ahp->ah_tx_chainmask; + + ar9300_get_channel_centers(ah, chan, ¢ers); + + if (IS_CHAN_2GHZ(chan)) { + ahp->twice_antenna_gain = p_eep_data->modal_header_2g.antenna_gain; + } else { + ahp->twice_antenna_gain = p_eep_data->modal_header_5g.antenna_gain; + } + + /* Save max allowed antenna gain to ease future lookups */ + ahp->twice_antenna_reduction = twice_antenna_reduction; + + /* Deduct antenna gain from EIRP to get the upper limit */ + twice_largest_antenna = (int16_t)AH_MIN((twice_antenna_reduction - + ahp->twice_antenna_gain), 0); + max_reg_allowed_power = twice_max_regulatory_power + twice_largest_antenna; + + /* Use ah_tp_scale - see bug 30070. */ + if (AH_PRIVATE(ah)->ah_tp_scale != HAL_TP_SCALE_MAX) { + max_reg_allowed_power -= + (tp_scale_reduction_table[(AH_PRIVATE(ah)->ah_tp_scale)] * 2); + } + + scaled_power = AH_MIN(power_limit, max_reg_allowed_power); + + /* + * Reduce scaled Power by number of chains active to get to + * per chain tx power level + */ + /* TODO: better value than these? */ + switch (ar9300_get_ntxchains(tx_chainmask)) { + case 1: + ahp->upper_limit[0] = AH_MAX(0, scaled_power); + break; + case 2: + scaled_power -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; + ahp->upper_limit[1] = AH_MAX(0, scaled_power); + break; + case 3: + scaled_power -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; + ahp->upper_limit[2] = AH_MAX(0, scaled_power); + break; + default: + HALASSERT(0); /* Unsupported number of chains */ + } + + scaled_power = AH_MAX(0, scaled_power); + + /* Get target powers from EEPROM - our baseline for TX Power */ + if (IS_CHAN_2GHZ(chan)) { + /* Setup for CTL modes */ + /* CTL_11B, CTL_11G, CTL_2GHT20 */ + num_ctl_modes = + ARRAY_LENGTH(ctl_modes_for11g) - SUB_NUM_CTL_MODES_AT_2G_40; + p_ctl_mode = ctl_modes_for11g; + + if (IS_CHAN_HT40(chan)) { + num_ctl_modes = ARRAY_LENGTH(ctl_modes_for11g); /* All 2G CTL's */ + } + } else { + /* Setup for CTL modes */ + /* CTL_11A, CTL_5GHT20 */ + num_ctl_modes = + ARRAY_LENGTH(ctl_modes_for11a) - SUB_NUM_CTL_MODES_AT_5G_40; + p_ctl_mode = ctl_modes_for11a; + + if (IS_CHAN_HT40(chan)) { + num_ctl_modes = ARRAY_LENGTH(ctl_modes_for11a); /* All 5G CTL's */ + } + } + + /* + * For MIMO, need to apply regulatory caps individually across dynamically + * running modes: CCK, OFDM, HT20, HT40 + * + * The outer loop walks through each possible applicable runtime mode. + * The inner loop walks through each ctl_index entry in EEPROM. + * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. + * + */ + for (ctl_mode = 0; ctl_mode < num_ctl_modes; ctl_mode++) { + HAL_BOOL is_ht40_ctl_mode = + (p_ctl_mode[ctl_mode] == CTL_5GHT40) || + (p_ctl_mode[ctl_mode] == CTL_2GHT40); + if (is_ht40_ctl_mode) { + freq = centers.synth_center; + } else if (p_ctl_mode[ctl_mode] & EXT_ADDITIVE) { + freq = centers.ext_center; + } else { + freq = centers.ctl_center; + } + + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, + "LOOP-Mode ctl_mode %d < %d, " + "is_ht40_ctl_mode %d, EXT_ADDITIVE %d\n", + ctl_mode, num_ctl_modes, is_ht40_ctl_mode, + (p_ctl_mode[ctl_mode] & EXT_ADDITIVE)); + /* walk through each CTL index stored in EEPROM */ + if (IS_CHAN_2GHZ(chan)) { + ctl_index = p_eep_data->ctl_index_2g; + ctl_num = OSPREY_NUM_CTLS_2G; + } else { + ctl_index = p_eep_data->ctl_index_5g; + ctl_num = OSPREY_NUM_CTLS_5G; + } + + for (i = 0; (i < ctl_num) && ctl_index[i]; i++) { + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, + " LOOP-Ctlidx %d: cfg_ctl 0x%2.2x p_ctl_mode 0x%2.2x " + "ctl_index 0x%2.2x chan %d chanctl 0x%x\n", + i, cfg_ctl, p_ctl_mode[ctl_mode], ctl_index[i], + chan->channel, chan->conformance_test_limit); + + /* + * compare test group from regulatory channel list + * with test mode from p_ctl_mode list + */ + if ((((cfg_ctl & ~CTL_MODE_M) | + (p_ctl_mode[ctl_mode] & CTL_MODE_M)) == ctl_index[i]) || + (((cfg_ctl & ~CTL_MODE_M) | + (p_ctl_mode[ctl_mode] & CTL_MODE_M)) == + ((ctl_index[i] & CTL_MODE_M) | SD_NO_CTL))) + { + twice_min_edge_power = + ar9300_eep_def_get_max_edge_power( + p_eep_data, freq, i, IS_CHAN_2GHZ(chan)); + + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, + " MATCH-EE_IDX %d: ch %d is2 %d " + "2xMinEdge %d chainmask %d chains %d\n", + i, freq, IS_CHAN_2GHZ(chan), + twice_min_edge_power, tx_chainmask, + ar9300_get_ntxchains(tx_chainmask)); + + if ((cfg_ctl & ~CTL_MODE_M) == SD_NO_CTL) { + /* + * Find the minimum of all CTL edge powers + * that apply to this channel + */ + twice_max_edge_power = + AH_MIN(twice_max_edge_power, twice_min_edge_power); + } else { + /* specific */ + twice_max_edge_power = twice_min_edge_power; + break; + } + } + } + + min_ctl_power = (u_int8_t)AH_MIN(twice_max_edge_power, scaled_power); + + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, + " SEL-Min ctl_mode %d p_ctl_mode %d " + "2xMaxEdge %d sP %d min_ctl_pwr %d\n", + ctl_mode, p_ctl_mode[ctl_mode], + twice_max_edge_power, scaled_power, min_ctl_power); + + /* Apply ctl mode to correct target power set */ + switch (p_ctl_mode[ctl_mode]) { + case CTL_11B: + for (i = ALL_TARGET_LEGACY_1L_5L; i <= ALL_TARGET_LEGACY_11S; i++) { + p_pwr_array[i] = + (u_int8_t)AH_MIN(p_pwr_array[i], min_ctl_power); + } + break; + case CTL_11A: + case CTL_11G: + for (i = ALL_TARGET_LEGACY_6_24; i <= ALL_TARGET_LEGACY_54; i++) { + p_pwr_array[i] = + (u_int8_t)AH_MIN(p_pwr_array[i], min_ctl_power); +#ifdef ATH_BT_COEX + if ((ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) || + (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI)) + { + if ((ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOWER_TX_PWR) + && (ahp->ah_bt_wlan_isolation + < HAL_BT_COEX_ISOLATION_FOR_NO_COEX)) + { + + u_int8_t reduce_pow; + + reduce_pow = (HAL_BT_COEX_ISOLATION_FOR_NO_COEX + - ahp->ah_bt_wlan_isolation) << 1; + + if (reduce_pow <= p_pwr_array[i]) { + p_pwr_array[i] -= reduce_pow; + } + } + if ((ahp->ah_bt_coex_flag & + HAL_BT_COEX_FLAG_LOW_ACK_PWR) && + (i != ALL_TARGET_LEGACY_36) && + (i != ALL_TARGET_LEGACY_48) && + (i != ALL_TARGET_LEGACY_54) && + (p_ctl_mode[ctl_mode] == CTL_11G)) + { + p_pwr_array[i] = 0; + } + } +#endif + } + break; + case CTL_5GHT20: + case CTL_2GHT20: + for (i = ALL_TARGET_HT20_0_8_16; i <= ALL_TARGET_HT20_23; i++) { + p_pwr_array[i] = + (u_int8_t)AH_MIN(p_pwr_array[i], min_ctl_power); +#ifdef ATH_BT_COEX + if (((ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) || + (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI)) && + (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOWER_TX_PWR) && + (ahp->ah_bt_wlan_isolation + < HAL_BT_COEX_ISOLATION_FOR_NO_COEX)) { + + u_int8_t reduce_pow = (HAL_BT_COEX_ISOLATION_FOR_NO_COEX + - ahp->ah_bt_wlan_isolation) << 1; + + if (reduce_pow <= p_pwr_array[i]) { + p_pwr_array[i] -= reduce_pow; + } + } +#if ATH_SUPPORT_MCI + else if ((ahp->ah_bt_coex_flag & + HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR) && + (p_ctl_mode[ctl_mode] == CTL_2GHT20) && + (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI)) + { + u_int8_t max_pwr; + + max_pwr = MS(mci_concur_tx_max_pwr[2][1], + ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK); + if (p_pwr_array[i] > max_pwr) { + p_pwr_array[i] = max_pwr; + } + } +#endif +#endif + } + break; + case CTL_11B_EXT: +#ifdef NOT_YET + target_power_cck_ext.t_pow2x[0] = (u_int8_t) + AH_MIN(target_power_cck_ext.t_pow2x[0], min_ctl_power); +#endif /* NOT_YET */ + break; + case CTL_11A_EXT: + case CTL_11G_EXT: +#ifdef NOT_YET + target_power_ofdm_ext.t_pow2x[0] = (u_int8_t) + AH_MIN(target_power_ofdm_ext.t_pow2x[0], min_ctl_power); +#endif /* NOT_YET */ + break; + case CTL_5GHT40: + case CTL_2GHT40: + for (i = ALL_TARGET_HT40_0_8_16; i <= ALL_TARGET_HT40_23; i++) { + p_pwr_array[i] = (u_int8_t) + AH_MIN(p_pwr_array[i], min_ctl_power); +#ifdef ATH_BT_COEX + if (((ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) || + (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI)) && + (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOWER_TX_PWR) && + (ahp->ah_bt_wlan_isolation + < HAL_BT_COEX_ISOLATION_FOR_NO_COEX)) { + + u_int8_t reduce_pow = (HAL_BT_COEX_ISOLATION_FOR_NO_COEX + - ahp->ah_bt_wlan_isolation) << 1; + + if (reduce_pow <= p_pwr_array[i]) { + p_pwr_array[i] -= reduce_pow; + } + } +#if ATH_SUPPORT_MCI + else if ((ahp->ah_bt_coex_flag & + HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR) && + (p_ctl_mode[ctl_mode] == CTL_2GHT40) && + (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI)) + { + u_int8_t max_pwr; + + max_pwr = MS(mci_concur_tx_max_pwr[3][1], + ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK); + if (p_pwr_array[i] > max_pwr) { + p_pwr_array[i] = max_pwr; + } + } +#endif +#endif + } + break; + default: + HALASSERT(0); + break; + } + } /* end ctl mode checking */ + + return AH_TRUE; +#undef EXT_ADDITIVE +#undef CTL_11A_EXT +#undef CTL_11G_EXT +#undef CTL_11B_EXT +#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN +#undef REDUCE_SCALED_POWER_BY_THREE_CHAIN +} + +/************************************************************** + * ar9300_eeprom_set_transmit_power + * + * Set the transmit power in the baseband for the given + * operating channel and mode. + */ +HAL_STATUS +ar9300_eeprom_set_transmit_power(struct ath_hal *ah, + ar9300_eeprom_t *p_eep_data, HAL_CHANNEL_INTERNAL *chan, u_int16_t cfg_ctl, + u_int16_t antenna_reduction, u_int16_t twice_max_regulatory_power, + u_int16_t power_limit) +{ +#define ABS(_x, _y) ((int)_x > (int)_y ? (int)_x - (int)_y : (int)_y - (int)_x) +#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ +#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ + u_int8_t target_power_val_t2[ar9300_rate_size]; + u_int8_t target_power_val_t2_eep[ar9300_rate_size]; + int16_t twice_array_gain = 0, max_power_level = 0; + struct ath_hal_9300 *ahp = AH9300(ah); + int i = 0; + u_int32_t tmp_paprd_rate_mask = 0, *tmp_ptr = NULL; + int paprd_scale_factor = 5; + + u_int8_t *ptr_mcs_rate2power_table_index; + u_int8_t mcs_rate2power_table_index_ht20[24] = + { + ALL_TARGET_HT20_0_8_16, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_4, + ALL_TARGET_HT20_5, + ALL_TARGET_HT20_6, + ALL_TARGET_HT20_7, + ALL_TARGET_HT20_0_8_16, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_12, + ALL_TARGET_HT20_13, + ALL_TARGET_HT20_14, + ALL_TARGET_HT20_15, + ALL_TARGET_HT20_0_8_16, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_20, + ALL_TARGET_HT20_21, + ALL_TARGET_HT20_22, + ALL_TARGET_HT20_23 + }; + + u_int8_t mcs_rate2power_table_index_ht40[24] = + { + ALL_TARGET_HT40_0_8_16, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_4, + ALL_TARGET_HT40_5, + ALL_TARGET_HT40_6, + ALL_TARGET_HT40_7, + ALL_TARGET_HT40_0_8_16, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_12, + ALL_TARGET_HT40_13, + ALL_TARGET_HT40_14, + ALL_TARGET_HT40_15, + ALL_TARGET_HT40_0_8_16, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_20, + ALL_TARGET_HT40_21, + ALL_TARGET_HT40_22, + ALL_TARGET_HT40_23, + }; + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s[%d] +++chan %d,cfgctl 0x%04x " + "antenna_reduction 0x%04x, twice_max_regulatory_power 0x%04x " + "power_limit 0x%04x\n", + __func__, __LINE__, chan->channel, cfg_ctl, + antenna_reduction, twice_max_regulatory_power, power_limit); + ar9300_set_target_power_from_eeprom(ah, chan->channel, target_power_val_t2); + + if (ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED)) { + if (IS_CHAN_2GHZ(chan)) { + if (IS_CHAN_HT40(chan)) { + tmp_paprd_rate_mask = + p_eep_data->modal_header_2g.paprd_rate_mask_ht40; + tmp_ptr = &AH9300(ah)->ah_2g_paprd_rate_mask_ht40; + } else { + tmp_paprd_rate_mask = + p_eep_data->modal_header_2g.paprd_rate_mask_ht20; + tmp_ptr = &AH9300(ah)->ah_2g_paprd_rate_mask_ht20; + } + } else { + if (IS_CHAN_HT40(chan)) { + tmp_paprd_rate_mask = + p_eep_data->modal_header_5g.paprd_rate_mask_ht40; + tmp_ptr = &AH9300(ah)->ah_5g_paprd_rate_mask_ht40; + } else { + tmp_paprd_rate_mask = + p_eep_data->modal_header_5g.paprd_rate_mask_ht20; + tmp_ptr = &AH9300(ah)->ah_5g_paprd_rate_mask_ht20; + } + } + AH_PAPRD_GET_SCALE_FACTOR( + paprd_scale_factor, p_eep_data, IS_CHAN_2GHZ(chan), chan->channel); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] paprd_scale_factor %d\n", + __func__, __LINE__, paprd_scale_factor); + /* PAPRD is not done yet, Scale down the EEP power */ + if (IS_CHAN_HT40(chan)) { + ptr_mcs_rate2power_table_index = + &mcs_rate2power_table_index_ht40[0]; + } else { + ptr_mcs_rate2power_table_index = + &mcs_rate2power_table_index_ht20[0]; + } + if (!chan->paprd_table_write_done) { + for (i = 0; i < 24; i++) { + /* PAPRD is done yet, so Scale down Power for PAPRD Rates*/ + if (tmp_paprd_rate_mask & (1 << i)) { + target_power_val_t2[ptr_mcs_rate2power_table_index[i]] -= + paprd_scale_factor; + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s[%d]: Chan %d " + "Scale down target_power_val_t2[%d] = 0x%04x\n", + __func__, __LINE__, + chan->channel, i, target_power_val_t2[i]); + } + } + } else { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s[%d]: PAPRD Done No TGT PWR Scaling\n", __func__, __LINE__); + } + } + + /* Save the Target power for future use */ + OS_MEMCPY(target_power_val_t2_eep, target_power_val_t2, + sizeof(target_power_val_t2)); + ar9300_eeprom_set_power_per_rate_table(ah, p_eep_data, chan, + target_power_val_t2, cfg_ctl, + antenna_reduction, + twice_max_regulatory_power, + power_limit, 0); + + /* Save this for quick lookup */ + ahp->reg_dmn = chan->conformance_test_limit; + + /* + * Always use CDD/direct per rate power table for register based approach. + * For FCC, CDD calculations should factor in the array gain, hence + * this adjust call. ETSI and MKK does not have this requirement. + */ + if (is_reg_dmn_fcc(ahp->reg_dmn)) { + ar9300_adjust_reg_txpower_cdd(ah, target_power_val_t2); + } + + if (ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED)) { + for (i = 0; i < ar9300_rate_size; i++) { + /* + * EEPROM TGT PWR is not same as current TGT PWR, + * so Disable PAPRD for this rate. + * Some of APs might ask to reduce Target Power, + * if target power drops significantly, + * disable PAPRD for that rate. + */ + if (tmp_paprd_rate_mask & (1 << i)) { + if (ABS(target_power_val_t2_eep[i], target_power_val_t2[i]) > + paprd_scale_factor) + { + tmp_paprd_rate_mask &= ~(1 << i); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: EEP TPC[%02d] 0x%08x " + "Curr TPC[%02d] 0x%08x mask = 0x%08x\n", + __func__, i, target_power_val_t2_eep[i], i, + target_power_val_t2[i], tmp_paprd_rate_mask); + } + } + + } + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Chan %d After tmp_paprd_rate_mask = 0x%08x\n", + __func__, chan->channel, tmp_paprd_rate_mask); + if (tmp_ptr) { + *tmp_ptr = tmp_paprd_rate_mask; + } + } + + /* Write target power array to registers */ + ar9300_transmit_power_reg_write(ah, target_power_val_t2); + + /* Write target power for self generated frames to the TPC register */ + ar9300_selfgen_tpc_reg_write(ah, chan, target_power_val_t2); + + /* GreenTx or Paprd */ + if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable || + AH_PRIVATE(ah)->ah_caps.hal_paprd_enabled) + { + if (AR_SREV_POSEIDON(ah)) { + /*For HAL_RSSI_TX_POWER_NONE array*/ + OS_MEMCPY(ahp->ah_default_tx_power, + target_power_val_t2, + sizeof(target_power_val_t2)); + /* Get defautl tx related register setting for GreenTx */ + /* Record OB/DB */ + AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB] = + OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2); + /* Record TPC settting */ + AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC] = + OS_REG_READ(ah, AR_TPC); + /* Record BB_powertx_rate9 setting */ + AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9] = + OS_REG_READ(ah, AR_PHY_BB_POWERTX_RATE9); + } + } + + /* + * Return tx power used to iwconfig. + * Since power is rate dependent, use one of the indices from the + * AR9300_Rates enum to select an entry from target_power_val_t2[] + * to report. + * Currently returns the power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps + * as CCK power is less interesting (?). + */ + i = ALL_TARGET_LEGACY_6_24; /* legacy */ + if (IS_CHAN_HT40(chan)) { + i = ALL_TARGET_HT40_0_8_16; /* ht40 */ + } else if (IS_CHAN_HT20(chan)) { + i = ALL_TARGET_HT20_0_8_16; /* ht20 */ + } + max_power_level = target_power_val_t2[i]; + /* Adjusting the ah_max_power_level based on chains and antennaGain*/ + switch (ar9300_get_ntxchains(ahp->ah_tx_chainmask)) + { + case 1: + break; + case 2: + twice_array_gain = (ahp->twice_antenna_gain >= ahp->twice_antenna_reduction)? 0: + ((int16_t)AH_MIN((ahp->twice_antenna_reduction - + (ahp->twice_antenna_gain + INCREASE_MAXPOW_BY_TWO_CHAIN)), 0)); + /* Adjusting maxpower with antennaGain */ + max_power_level -= twice_array_gain; + /* Adjusting maxpower based on chain */ + max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN; + break; + case 3: + twice_array_gain = (ahp->twice_antenna_gain >= ahp->twice_antenna_reduction)? 0: + ((int16_t)AH_MIN((ahp->twice_antenna_reduction - + (ahp->twice_antenna_gain + INCREASE_MAXPOW_BY_THREE_CHAIN)), 0)); + + /* Adjusting maxpower with antennaGain */ + max_power_level -= twice_array_gain; + /* Adjusting maxpower based on chain */ + max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; + break; + default: + HALASSERT(0); /* Unsupported number of chains */ + } + AH_PRIVATE(ah)->ah_max_power_level = (int8_t)max_power_level; + + ar9300_calibration_apply(ah, chan->channel); +#undef ABS + + /* Handle per packet TPC initializations */ + if (AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc) { + /* Transmit Power per-rate per-chain are computed here. A separate + * power table is maintained for different MIMO modes (i.e. TXBF ON, + * STBC) to enable easy lookup during packet transmit. + * The reason for maintaing each of these tables per chain is that + * the transmit power used for different number of chains is different + * depending on whether the power has been limited by the target power, + * the regulatory domain or the CTL limits. + */ + u_int mode = ath_hal_get_curmode(ah, chan); + u_int32_t val = 0; + u_int8_t chainmasks[AR9300_MAX_CHAINS] = + {OSPREY_1_CHAINMASK, OSPREY_2LOHI_CHAINMASK, OSPREY_3_CHAINMASK}; + for (i = 0; i < AR9300_MAX_CHAINS; i++) { + OS_MEMCPY(target_power_val_t2, target_power_val_t2_eep, + sizeof(target_power_val_t2_eep)); + ar9300_eeprom_set_power_per_rate_table(ah, p_eep_data, chan, + target_power_val_t2, cfg_ctl, + antenna_reduction, + twice_max_regulatory_power, + power_limit, chainmasks[i]); + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, + " Channel = %d Chainmask = %d, Upper Limit = [%2d.%1d dBm]\n", + chan->channel, i, ahp->upper_limit[i]/2, + ahp->upper_limit[i]%2 * 5); + ar9300_init_rate_txpower(ah, mode, chan, target_power_val_t2, + chainmasks[i]); + + } + + /* Enable TPC */ + OS_REG_WRITE(ah, AR_PHY_PWRTX_MAX, AR_PHY_PWRTX_MAX_TPC_ENABLE); + /* + * Disable per chain power reduction since we are already + * accounting for this in our calculations + */ + val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB); + if (AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, + val & AR_PHY_POWER_TX_SUB_2_DISABLE); + } else { + OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, + val & AR_PHY_POWER_TX_SUB_3_DISABLE); + } + } + + return HAL_OK; +} + +/************************************************************** + * ar9300_eeprom_set_addac + * + * Set the ADDAC from eeprom. + */ +void +ar9300_eeprom_set_addac(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) +{ + + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "FIXME: ar9300_eeprom_def_set_addac called\n"); +#if 0 + MODAL_EEPDEF_HEADER *p_modal; + struct ath_hal_9300 *ahp = AH9300(ah); + ar9300_eeprom_t *eep = &ahp->ah_eeprom.def; + u_int8_t biaslevel; + + if (AH_PRIVATE(ah)->ah_macVersion != AR_SREV_VERSION_SOWL) { + return; + } + + HALASSERT(owl_get_eepdef_ver(ahp) == AR9300_EEP_VER); + + /* Xpa bias levels in eeprom are valid from rev 14.7 */ + if (owl_get_eepdef_rev(ahp) < AR9300_EEP_MINOR_VER_7) { + return; + } + + if (ahp->ah_emu_eeprom) { + return; + } + + p_modal = &(eep->modal_header[IS_CHAN_2GHZ(chan)]); + + if (p_modal->xpa_bias_lvl != 0xff) { + biaslevel = p_modal->xpa_bias_lvl; + } else { + /* Use freqeuncy specific xpa bias level */ + u_int16_t reset_freq_bin, freq_bin, freq_count = 0; + CHAN_CENTERS centers; + + ar9300_get_channel_centers(ah, chan, ¢ers); + + reset_freq_bin = FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)); + freq_bin = p_modal->xpa_bias_lvl_freq[0] & 0xff; + biaslevel = (u_int8_t)(p_modal->xpa_bias_lvl_freq[0] >> 14); + + freq_count++; + + while (freq_count < 3) { + if (p_modal->xpa_bias_lvl_freq[freq_count] == 0x0) { + break; + } + + freq_bin = p_modal->xpa_bias_lvl_freq[freq_count] & 0xff; + if (reset_freq_bin >= freq_bin) { + biaslevel = + (u_int8_t)(p_modal->xpa_bias_lvl_freq[freq_count] >> 14); + } else { + break; + } + freq_count++; + } + } + + /* Apply bias level to the ADDAC values in the INI array */ + if (IS_CHAN_2GHZ(chan)) { + INI_RA(&ahp->ah_ini_addac, 7, 1) = + (INI_RA(&ahp->ah_ini_addac, 7, 1) & (~0x18)) | biaslevel << 3; + } else { + INI_RA(&ahp->ah_ini_addac, 6, 1) = + (INI_RA(&ahp->ah_ini_addac, 6, 1) & (~0xc0)) | biaslevel << 6; + } +#endif +} + +u_int +ar9300_eeprom_dump_support(struct ath_hal *ah, void **pp_e) +{ + *pp_e = &(AH9300(ah)->ah_eeprom); + return sizeof(ar9300_eeprom_t); +} + +u_int8_t +ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp, + HAL_FREQ_BAND freq_band) +{ +#if 0 + ar9300_eeprom_t *eep = &ahp->ah_eeprom.def; + MODAL_EEPDEF_HEADER *p_modal = + &(eep->modal_header[HAL_FREQ_BAND_2GHZ == freq_band]); + BASE_EEPDEF_HEADER *p_base = &eep->base_eep_header; + u_int8_t num_ant_config; + + num_ant_config = 1; /* default antenna configuration */ + + if (p_base->version >= 0x0E0D) { + if (p_modal->use_ant1) { + num_ant_config += 1; + } + } + + return num_ant_config; +#else + return 1; +#endif +} + +HAL_STATUS +ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, HAL_CHANNEL_INTERNAL *chan, + u_int8_t index, u_int16_t *config) +{ +#if 0 + ar9300_eeprom_t *eep = &ahp->ah_eeprom.def; + MODAL_EEPDEF_HEADER *p_modal = &(eep->modal_header[IS_CHAN_2GHZ(chan)]); + BASE_EEPDEF_HEADER *p_base = &eep->base_eep_header; + + switch (index) { + case 0: + *config = p_modal->ant_ctrl_common & 0xFFFF; + return HAL_OK; + case 1: + if (p_base->version >= 0x0E0D) { + if (p_modal->use_ant1) { + *config = ((p_modal->ant_ctrl_common & 0xFFFF0000) >> 16); + return HAL_OK; + } + } + break; + default: + break; + } +#endif + return HAL_EINVAL; +} + +u_int8_t* +ar9300_eeprom_get_cust_data(struct ath_hal_9300 *ahp) +{ + return (u_int8_t *)ahp; +} + +#ifdef UNUSED +static inline HAL_STATUS +ar9300_check_eeprom(struct ath_hal *ah) +{ +#if 0 + u_int32_t sum = 0, el; + u_int16_t *eepdata; + int i; + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL need_swap = AH_FALSE; + ar9300_eeprom_t *eep = (ar9300_eeprom_t *)&ahp->ah_eeprom.def; + u_int16_t magic, magic2; + int addr; + u_int16_t temp; + + /* + ** We need to check the EEPROM data regardless of if it's in flash or + ** in EEPROM. + */ + + if (!ahp->ah_priv.priv.ah_eeprom_read( + ah, AR9300_EEPROM_MAGIC_OFFSET, &magic)) + { + HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: Reading Magic # failed\n", __func__); + return AH_FALSE; + } + + HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: Read Magic = 0x%04X\n", __func__, magic); + + if (!ar9300_eep_data_in_flash(ah)) { + + if (magic != AR9300_EEPROM_MAGIC) { + magic2 = SWAP16(magic); + + if (magic2 == AR9300_EEPROM_MAGIC) { + need_swap = AH_TRUE; + eepdata = (u_int16_t *)(&ahp->ah_eeprom); + + for (addr = 0; + addr < sizeof(ar9300_eeprom_t) / sizeof(u_int16_t); + addr++) + { + temp = SWAP16(*eepdata); + *eepdata = temp; + eepdata++; + + HALDEBUG(ah, HAL_DEBUG_EEPROM_DUMP, "0x%04X ", *eepdata); + if (((addr + 1) % 6) == 0) { + HALDEBUG(ah, HAL_DEBUG_EEPROM_DUMP, "\n"); + } + } + } else { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "Invalid EEPROM Magic. endianness missmatch.\n"); + return HAL_EEBADSUM; + } + } + } else { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "EEPROM being read from flash @0x%p\n", AH_PRIVATE(ah)->ah_st); + } + + HALDEBUG(ah, HAL_DEBUG_EEPROM, "need_swap = %s.\n", need_swap?"True":"False"); + + if (need_swap) { + el = SWAP16(ahp->ah_eeprom.def.base_eep_header.length); + } else { + el = ahp->ah_eeprom.def.base_eep_header.length; + } + + eepdata = (u_int16_t *)(&ahp->ah_eeprom.def); + for (i = 0; + i < AH_MIN(el, sizeof(ar9300_eeprom_t)) / sizeof(u_int16_t); + i++) { + sum ^= *eepdata++; + } + + if (need_swap) { + /* + * preddy: EEPROM endianness does not match. So change it + * 8bit values in eeprom data structure does not need to be swapped + * Only >8bits (16 & 32) values need to be swapped + * If a new 16 or 32 bit field is added to the EEPROM contents, + * please make sure to swap the field here + */ + u_int32_t integer, j; + u_int16_t word; + + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "EEPROM Endianness is not native.. Changing \n"); + + /* convert Base Eep header */ + word = SWAP16(eep->base_eep_header.length); + eep->base_eep_header.length = word; + + word = SWAP16(eep->base_eep_header.checksum); + eep->base_eep_header.checksum = word; + + word = SWAP16(eep->base_eep_header.version); + eep->base_eep_header.version = word; + + word = SWAP16(eep->base_eep_header.reg_dmn[0]); + eep->base_eep_header.reg_dmn[0] = word; + + word = SWAP16(eep->base_eep_header.reg_dmn[1]); + eep->base_eep_header.reg_dmn[1] = word; + + word = SWAP16(eep->base_eep_header.rf_silent); + eep->base_eep_header.rf_silent = word; + + word = SWAP16(eep->base_eep_header.blue_tooth_options); + eep->base_eep_header.blue_tooth_options = word; + + word = SWAP16(eep->base_eep_header.device_cap); + eep->base_eep_header.device_cap = word; + + /* convert Modal Eep header */ + for (j = 0; j < ARRAY_LENGTH(eep->modal_header); j++) { + MODAL_EEPDEF_HEADER *p_modal = &eep->modal_header[j]; + integer = SWAP32(p_modal->ant_ctrl_common); + p_modal->ant_ctrl_common = integer; + + for (i = 0; i < AR9300_MAX_CHAINS; i++) { + integer = SWAP32(p_modal->ant_ctrl_chain[i]); + p_modal->ant_ctrl_chain[i] = integer; + } + + for (i = 0; i < AR9300_EEPROM_MODAL_SPURS; i++) { + word = SWAP16(p_modal->spur_chans[i].spur_chan); + p_modal->spur_chans[i].spur_chan = word; + } + } + } + + /* Check CRC - Attach should fail on a bad checksum */ + if (sum != 0xffff || owl_get_eepdef_ver(ahp) != AR9300_EEP_VER || + owl_get_eepdef_rev(ahp) < AR9300_EEP_NO_BACK_VER) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "Bad EEPROM checksum 0x%x or revision 0x%04x\n", + sum, owl_get_eepdef_ver(ahp)); + return HAL_EEBADSUM; + } +#ifdef EEPROM_DUMP + ar9300_eeprom_def_dump(ah, eep); +#endif + +#if 0 +#ifdef AH_AR9300_OVRD_TGT_PWR + + /* + * 14.4 EEPROM contains low target powers. + * Hardcode until EEPROM > 14.4 + */ + if (owl_get_eepdef_ver(ahp) == 14 && owl_get_eepdef_rev(ahp) <= 4) { + MODAL_EEPDEF_HEADER *p_modal; + +#ifdef EEPROM_DUMP + HALDEBUG(ah, HAL_DEBUG_POWER_OVERRIDE, "Original Target Powers\n"); + ar9300_eep_def_dump_tgt_power(ah, eep); +#endif + HALDEBUG(ah, HAL_DEBUG_POWER_OVERRIDE, + "Override Target Powers. EEPROM Version is %d.%d, " + "Device Type %d\n", + owl_get_eepdef_ver(ahp), + owl_get_eepdef_rev(ahp), + eep->base_eep_header.device_type); + + + ar9300_eep_def_override_tgt_power(ah, eep); + + if (eep->base_eep_header.device_type == 5) { + /* for xb72 only: improve transmit EVM for interop */ + p_modal = &eep->modal_header[1]; + p_modal->tx_frame_to_data_start = 0x23; + p_modal->tx_frame_to_xpa_on = 0x23; + p_modal->tx_frame_to_pa_on = 0x23; + } + +#ifdef EEPROM_DUMP + HALDEBUG(ah, HAL_DEBUG_POWER_OVERRIDE, "Modified Target Powers\n"); + ar9300_eep_def_dump_tgt_power(ah, eep); +#endif + } +#endif /* AH_AR9300_OVRD_TGT_PWR */ +#endif +#endif + return HAL_OK; +} +#endif + +static u_int16_t +ar9300_eeprom_get_spur_chan(struct ath_hal *ah, u_int16_t i, HAL_BOOL is_2ghz) +{ + u_int16_t spur_val = AR_NO_SPUR; +#if 0 + struct ath_hal_9300 *ahp = AH9300(ah); + ar9300_eeprom_t *eep = (ar9300_eeprom_t *)&ahp->ah_eeprom; + + HALASSERT(i < AR_EEPROM_MODAL_SPURS ); + + HALDEBUG(ah, HAL_DEBUG_ANI, + "Getting spur idx %d is2Ghz. %d val %x\n", + i, is_2ghz, + AH_PRIVATE(ah)->ah_config.ath_hal_spur_chans[i][is_2ghz]); + + switch (AH_PRIVATE(ah)->ah_config.ath_hal_spur_mode) { + case SPUR_DISABLE: + /* returns AR_NO_SPUR */ + break; + case SPUR_ENABLE_IOCTL: + spur_val = AH_PRIVATE(ah)->ah_config.ath_hal_spur_chans[i][is_2ghz]; + HALDEBUG(ah, HAL_DEBUG_ANI, + "Getting spur val from new loc. %d\n", spur_val); + break; + case SPUR_ENABLE_EEPROM: + spur_val = eep->modal_header[is_2ghz].spur_chans[i].spur_chan; + break; + + } +#endif + return spur_val; +} + +#ifdef UNUSED +static inline HAL_BOOL +ar9300_fill_eeprom(struct ath_hal *ah) +{ + return ar9300_eeprom_restore(ah); +} +#endif + +u_int16_t +ar9300_eeprom_struct_size(void) +{ + return sizeof(ar9300_eeprom_t); +} + +int ar9300_eeprom_struct_default_many(void) +{ + return ARRAY_LENGTH(default9300); +} + + +ar9300_eeprom_t * +ar9300_eeprom_struct_default(int default_index) +{ + if (default_index >= 0 && + default_index < ARRAY_LENGTH(default9300)) + { + return default9300[default_index]; + } else { + return 0; + } +} + +ar9300_eeprom_t * +ar9300_eeprom_struct_default_find_by_id(int id) +{ + int it; + + for (it = 0; it < ARRAY_LENGTH(default9300); it++) { + if (default9300[it] != 0 && default9300[it]->template_version == id) { + return default9300[it]; + } + } + return 0; +} + + +HAL_BOOL +ar9300_calibration_data_read_flash(struct ath_hal *ah, long address, + u_int8_t *buffer, int many) +{ + + if (((address) < 0) || ((address + many) > AR9300_EEPROM_SIZE - 1)) { + return AH_FALSE; + } + return AH_FALSE; +} + +HAL_BOOL +ar9300_calibration_data_read_eeprom(struct ath_hal *ah, long address, + u_int8_t *buffer, int many) +{ + int i; + u_int8_t value[2]; + unsigned long eep_addr; + unsigned long byte_addr; + u_int16_t *svalue; + struct ath_hal_9300 *ahp = AH9300(ah); + + if (((address) < 0) || ((address + many) > AR9300_EEPROM_SIZE)) { + return AH_FALSE; + } + + for (i = 0; i < many; i++) { + eep_addr = (u_int16_t) (address + i) / 2; + byte_addr = (u_int16_t) (address + i) % 2; + svalue = (u_int16_t *) value; + if (!ahp->ah_priv.priv.ah_eeprom_read(ah, eep_addr, svalue)) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: Unable to read eeprom region \n", __func__); + return AH_FALSE; + } + buffer[i] = (*svalue >> (8 * byte_addr)) & 0xff; + } + return AH_TRUE; +} + +HAL_BOOL +ar9300_calibration_data_read_otp(struct ath_hal *ah, long address, + u_int8_t *buffer, int many, HAL_BOOL is_wifi) +{ + int i; + unsigned long eep_addr; + unsigned long byte_addr; + u_int32_t svalue; + + if (((address) < 0) || ((address + many) > 0x400)) { + return AH_FALSE; + } + + for (i = 0; i < many; i++) { + eep_addr = (u_int16_t) (address + i) / 4; /* otp is 4 bytes long???? */ + byte_addr = (u_int16_t) (address + i) % 4; + if (!ar9300_otp_read(ah, eep_addr, &svalue, is_wifi)) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: Unable to read otp region \n", __func__); + return AH_FALSE; + } + buffer[i] = (svalue >> (8 * byte_addr)) & 0xff; + } + return AH_TRUE; +} + +#ifdef ATH_CAL_NAND_FLASH +HAL_BOOL +ar9300_calibration_data_read_nand(struct ath_hal *ah, long address, + u_int8_t *buffer, int many) +{ + int ret_len; + int ret_val = 1; + + /* Calling OS based API to read NAND */ + ret_val = OS_NAND_FLASH_READ(ATH_CAL_NAND_PARTITION, address, many, &ret_len, buffer); + + return (ret_val ? AH_FALSE: AH_TRUE); +} +#endif + +HAL_BOOL +ar9300_calibration_data_read(struct ath_hal *ah, long address, + u_int8_t *buffer, int many) +{ + switch (AH9300(ah)->calibration_data_source) { + case calibration_data_flash: + return ar9300_calibration_data_read_flash(ah, address, buffer, many); + case calibration_data_eeprom: + return ar9300_calibration_data_read_eeprom(ah, address, buffer, many); + case calibration_data_otp: + return ar9300_calibration_data_read_otp(ah, address, buffer, many, 1); +#ifdef ATH_CAL_NAND_FLASH + case calibration_data_nand: + return ar9300_calibration_data_read_nand(ah,address,buffer,many); +#endif + + } + return AH_FALSE; +} + + +HAL_BOOL +ar9300_calibration_data_read_array(struct ath_hal *ah, int address, + u_int8_t *buffer, int many) +{ + int it; + + for (it = 0; it < many; it++) { + (void)ar9300_calibration_data_read(ah, address - it, buffer + it, 1); + } + return AH_TRUE; +} + + +/* + * the address where the first configuration block is written + */ +static const int base_address = 0x3ff; /* 1KB */ +static const int base_address_512 = 0x1ff; /* 512Bytes */ + +/* + * the address where the NAND first configuration block is written + */ +#ifdef ATH_CAL_NAND_FLASH +static const int base_address_nand = AR9300_FLASH_CAL_START_OFFSET; +#endif + + +/* + * the lower limit on configuration data + */ +static const int low_limit = 0x040; + +/* + * returns size of the physical eeprom in bytes. + * 1024 and 2048 are normal sizes. + * 0 means there is no eeprom. + */ +int32_t +ar9300_eeprom_size(struct ath_hal *ah) +{ + u_int16_t data; + /* + * first we'll try for 4096 bytes eeprom + */ + if (ar9300_eeprom_read_word(ah, 2047, &data)) { + if (data != 0) { + return 4096; + } + } + /* + * then we'll try for 2048 bytes eeprom + */ + if (ar9300_eeprom_read_word(ah, 1023, &data)) { + if (data != 0) { + return 2048; + } + } + /* + * then we'll try for 1024 bytes eeprom + */ + if (ar9300_eeprom_read_word(ah, 511, &data)) { + if (data != 0) { + return 1024; + } + } + return 0; +} + +/* + * returns size of the physical otp in bytes. + * 1024 and 2048 are normal sizes. + * 0 means there is no eeprom. + */ +int32_t ar9300_otp_size(struct ath_hal *ah); +int32_t +ar9300_otp_size(struct ath_hal *ah) +{ + if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah)) { + return base_address_512+1; + } else { + return base_address+1; + } +} + + +/* + * find top of memory + */ +int +ar9300_eeprom_base_address(struct ath_hal *ah) +{ + int size; + + if (AH9300(ah)->calibration_data_source == calibration_data_otp) { + return ar9300_otp_size(ah)-1; + } + else + { + size = ar9300_eeprom_size(ah); + if (size > 0) { + return size - 1; + } else { + return ar9300_otp_size(ah)-1; + } + } +} + +int +ar9300_eeprom_volatile(struct ath_hal *ah) +{ + if (AH9300(ah)->calibration_data_source == calibration_data_otp) { + return 0; /* no eeprom, use otp */ + } else { + return 1; /* board has eeprom or flash */ + } +} + +/* + * need to change this to look for the pcie data in the low parts of memory + * cal data needs to stop a few locations above + */ +int +ar9300_eeprom_low_limit(struct ath_hal *ah) +{ + return low_limit; +} + +u_int16_t +ar9300_compression_checksum(u_int8_t *data, int dsize) +{ + int it; + int checksum = 0; + + for (it = 0; it < dsize; it++) { + checksum += data[it]; + checksum &= 0xffff; + } + + return checksum; +} + +int +ar9300_compression_header_unpack(u_int8_t *best, int *code, int *reference, + int *length, int *major, int *minor) +{ + unsigned long value[4]; + + value[0] = best[0]; + value[1] = best[1]; + value[2] = best[2]; + value[3] = best[3]; + *code = ((value[0] >> 5) & 0x0007); + *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020); + *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f); + *major = (value[2] & 0x000f); + *minor = (value[3] & 0x00ff); + + return 4; +} + + +static HAL_BOOL +ar9300_uncompress_block(struct ath_hal *ah, u_int8_t *mptr, int mdata_size, + u_int8_t *block, int size) +{ + int it; + int spot; + int offset; + int length; + + spot = 0; + for (it = 0; it < size; it += (length + 2)) { + offset = block[it]; + offset &= 0xff; + spot += offset; + length = block[it + 1]; + length &= 0xff; + if (length > 0 && spot >= 0 && spot + length <= mdata_size) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: Restore at %d: spot=%d offset=%d length=%d\n", + __func__, it, spot, offset, length); + OS_MEMCPY(&mptr[spot], &block[it + 2], length); + spot += length; + } else if (length > 0) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: Bad restore at %d: spot=%d offset=%d length=%d\n", + __func__, it, spot, offset, length); + return AH_FALSE; + } + } + return AH_TRUE; +} + +static int +ar9300_eeprom_restore_internal_address(struct ath_hal *ah, + ar9300_eeprom_t *mptr, int mdata_size, int cptr, u_int8_t blank) +{ + u_int8_t word[MOUTPUT]; + ar9300_eeprom_t *dptr; /* was uint8 */ + int code; + int reference, length, major, minor; + int osize; + int it; + int restored; + u_int16_t checksum, mchecksum; + + restored = 0; + for (it = 0; it < MSTATE; it++) { + (void) ar9300_calibration_data_read_array( + ah, cptr, word, compression_header_length); + if (word[0] == blank && word[1] == blank && word[2] == blank && word[3] == blank) + { + break; + } + ar9300_compression_header_unpack( + word, &code, &reference, &length, &major, &minor); + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: Found block at %x: " + "code=%d ref=%d length=%d major=%d minor=%d\n", + __func__, cptr, code, reference, length, major, minor); +#ifdef DONTUSE + if (length >= 1024) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: Skipping bad header\n", __func__); + cptr -= compression_header_length; + continue; + } +#endif + osize = length; + (void) ar9300_calibration_data_read_array( + ah, cptr, word, + compression_header_length + osize + compression_checksum_length); + checksum = ar9300_compression_checksum( + &word[compression_header_length], length); + mchecksum = + word[compression_header_length + osize] | + (word[compression_header_length + osize + 1] << 8); + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: checksum %x %x\n", __func__, checksum, mchecksum); + if (checksum == mchecksum) { + switch (code) { + case _compress_none: + if (length != mdata_size) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: EEPROM structure size mismatch " + "memory=%d eeprom=%d\n", __func__, mdata_size, length); + return -1; + } + OS_MEMCPY((u_int8_t *)mptr, + (u_int8_t *)(word + compression_header_length), length); + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: restored eeprom %d: uncompressed, length %d\n", + __func__, it, length); + restored = 1; + break; +#ifdef UNUSED + case _compress_lzma: + if (reference == reference_current) { + dptr = mptr; + } else { + dptr = (u_int8_t *)ar9300_eeprom_struct_default_find_by_id( + reference); + if (dptr == 0) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: Can't find reference eeprom struct %d\n", + __func__, reference); + goto done; + } + } + usize = -1; + if (usize != mdata_size) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: uncompressed data is wrong size %d %d\n", + __func__, usize, mdata_size); + goto done; + } + + for (ib = 0; ib < mdata_size; ib++) { + mptr[ib] = dptr[ib] ^ word[ib + overhead]; + } + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: restored eeprom %d: compressed, " + "reference %d, length %d\n", + __func__, it, reference, length); + break; + case _compress_pairs: + if (reference == reference_current) { + dptr = mptr; + } else { + dptr = (u_int8_t *)ar9300_eeprom_struct_default_find_by_id( + reference); + if (dptr == 0) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: Can't find the reference " + "eeprom structure %d\n", + __func__, reference); + goto done; + } + } + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: restored eeprom %d: " + "pairs, reference %d, length %d,\n", + __func__, it, reference, length); + break; +#endif + case _compress_block: + if (reference == reference_current) { + dptr = mptr; + } else { + dptr = ar9300_eeprom_struct_default_find_by_id(reference); + if (dptr == 0) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: cant find reference eeprom struct %d\n", + __func__, reference); + break; + } + OS_MEMCPY(mptr, dptr, mdata_size); + } + + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: restore eeprom %d: block, reference %d, length %d\n", + __func__, it, reference, length); + (void) ar9300_uncompress_block(ah, + (u_int8_t *) mptr, mdata_size, + (u_int8_t *) (word + compression_header_length), length); + restored = 1; + break; + default: + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: unknown compression code %d\n", __func__, code); + break; + } + } else { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: skipping block with bad checksum\n", __func__); + } + cptr -= compression_header_length + osize + compression_checksum_length; + } + + if (!restored) { + cptr = -1; + } + return cptr; +} + +static int +ar9300_eeprom_restore_from_dram(struct ath_hal *ah, ar9300_eeprom_t *mptr, + int mdata_size) +{ + struct ath_hal_9300 *ahp = AH9300(ah); +#if !defined(USE_PLATFORM_FRAMEWORK) + char *cal_ptr; +#endif + + + HALASSERT(mdata_size > 0); + + /* if cal_in_flash is AH_TRUE, the address sent by LMAC to HAL + (i.e. ah->ah_st) is corresponding to Flash. so return from + here if ar9300_eep_data_in_flash(ah) returns AH_TRUE */ + if(ar9300_eep_data_in_flash(ah)) + return -1; + + /* check if LMAC sent DRAM address is valid */ + if (!(uintptr_t)(AH_PRIVATE(ah)->ah_st)) { + return -1; + } + + /* When calibration data is from host, Host will copy the + compressed data to the predefined DRAM location saved at ah->ah_st */ + ath_hal_printf(ah, "Restoring Cal data from DRAM\n"); + ahp->ah_cal_mem = OS_REMAP((uintptr_t)(AH_PRIVATE(ah)->ah_st), + HOST_CALDATA_SIZE); + if (!ahp->ah_cal_mem) + { + HALDEBUG(ah, HAL_DEBUG_EEPROM,"%s: can't remap dram region\n", __func__); + return -1; + } +#if !defined(USE_PLATFORM_FRAMEWORK) + cal_ptr = &((char *)(ahp->ah_cal_mem))[AR9300_FLASH_CAL_START_OFFSET]; + OS_MEMCPY(mptr, cal_ptr, mdata_size); +#else + OS_MEMCPY(mptr, ahp->ah_cal_mem, mdata_size); +#endif + + if (mptr->eeprom_version == 0xff || + mptr->template_version == 0xff || + mptr->eeprom_version == 0 || + mptr->template_version == 0) + { + /* The board is uncalibrated */ + return -1; + } + if (mptr->eeprom_version != 0x2) + { + return -1; + } + + return mdata_size; + +} + +static int +ar9300_eeprom_restore_from_flash(struct ath_hal *ah, ar9300_eeprom_t *mptr, + int mdata_size) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + char *cal_ptr; + + HALASSERT(mdata_size > 0); + + if (!ahp->ah_cal_mem) { + return -1; + } + + ath_hal_printf(ah, "Restoring Cal data from Flash\n"); + /* + * When calibration data is saved in flash, read + * uncompressed eeprom structure from flash and return + */ + cal_ptr = &((char *)(ahp->ah_cal_mem))[AR9300_FLASH_CAL_START_OFFSET]; + OS_MEMCPY(mptr, cal_ptr, mdata_size); +#if 0 + ar9300_swap_eeprom((ar9300_eeprom_t *)mptr); DONE IN ar9300_restore() +#endif + if (mptr->eeprom_version == 0xff || + mptr->template_version == 0xff || + mptr->eeprom_version == 0 || + mptr->template_version == 0) + { + /* The board is uncalibrated */ + return -1; + } + if (mptr->eeprom_version != 0x2) + { + return -1; + } + return mdata_size; +} + +/* + * Read the configuration data from the storage. We try the order with: + * EEPROM, Flash, OTP. If all of above failed, use the default template. + * The data can be put in any specified memory buffer. + * + * Returns -1 on error. + * Returns address of next memory location on success. + */ +int +ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, + int mdata_size) +{ + int nptr; + + nptr = -1; + + if ((AH9300(ah)->calibration_data_try == calibration_data_none || + AH9300(ah)->calibration_data_try == calibration_data_dram) && + AH9300(ah)->try_dram && nptr < 0) + { + AH9300(ah)->calibration_data_source = calibration_data_dram; + AH9300(ah)->calibration_data_source_address = 0; + nptr = ar9300_eeprom_restore_from_dram(ah, mptr, mdata_size); + if (nptr < 0) { + AH9300(ah)->calibration_data_source = calibration_data_none; + AH9300(ah)->calibration_data_source_address = 0; + } + } + + if ((AH9300(ah)->calibration_data_try == calibration_data_none || + AH9300(ah)->calibration_data_try == calibration_data_eeprom) && + AH9300(ah)->try_eeprom && nptr < 0) + { + /* + * need to look at highest eeprom address as well as at + * base_address=0x3ff where we used to write the data + */ + AH9300(ah)->calibration_data_source = calibration_data_eeprom; + if (AH9300(ah)->calibration_data_try_address != 0) { + AH9300(ah)->calibration_data_source_address = + AH9300(ah)->calibration_data_try_address; + nptr = ar9300_eeprom_restore_internal_address( + ah, mptr, mdata_size, + AH9300(ah)->calibration_data_source_address, 0xff); + } else { + AH9300(ah)->calibration_data_source_address = + ar9300_eeprom_base_address(ah); + nptr = ar9300_eeprom_restore_internal_address( + ah, mptr, mdata_size, + AH9300(ah)->calibration_data_source_address, 0xff); + if (nptr < 0 && + AH9300(ah)->calibration_data_source_address != base_address) + { + AH9300(ah)->calibration_data_source_address = base_address; + nptr = ar9300_eeprom_restore_internal_address( + ah, mptr, mdata_size, + AH9300(ah)->calibration_data_source_address, 0xff); + } + } + if (nptr < 0) { + AH9300(ah)->calibration_data_source = calibration_data_none; + AH9300(ah)->calibration_data_source_address = 0; + } + } + + /* + * ##### should be an ifdef test for any AP usage, + * either in driver or in nart + */ + if ((AH9300(ah)->calibration_data_try == calibration_data_none || + AH9300(ah)->calibration_data_try == calibration_data_flash) && + AH9300(ah)->try_flash && nptr < 0) + { + AH9300(ah)->calibration_data_source = calibration_data_flash; + /* how are we supposed to set this for flash? */ + AH9300(ah)->calibration_data_source_address = 0; + nptr = ar9300_eeprom_restore_from_flash(ah, mptr, mdata_size); + if (nptr < 0) { + AH9300(ah)->calibration_data_source = calibration_data_none; + AH9300(ah)->calibration_data_source_address = 0; + } + } + + if ((AH9300(ah)->calibration_data_try == calibration_data_none || + AH9300(ah)->calibration_data_try == calibration_data_otp) && + AH9300(ah)->try_otp && nptr < 0) + { + AH9300(ah)->calibration_data_source = calibration_data_otp; + if (AH9300(ah)->calibration_data_try_address != 0) { + AH9300(ah)->calibration_data_source_address = + AH9300(ah)->calibration_data_try_address; + } else { + AH9300(ah)->calibration_data_source_address = + ar9300_eeprom_base_address(ah); + } + nptr = ar9300_eeprom_restore_internal_address( + ah, mptr, mdata_size, AH9300(ah)->calibration_data_source_address, 0); + if (nptr < 0) { + AH9300(ah)->calibration_data_source = calibration_data_none; + AH9300(ah)->calibration_data_source_address = 0; + } + } + +#ifdef ATH_CAL_NAND_FLASH + if ((AH9300(ah)->calibration_data_try == calibration_data_none || + AH9300(ah)->calibration_data_try == calibration_data_nand) && + AH9300(ah)->try_nand && nptr < 0) + { + AH9300(ah)->calibration_data_source = calibration_data_nand; + AH9300(ah)->calibration_data_source_address = ((unsigned int)(AH_PRIVATE(ah)->ah_st)) + base_address_nand; + if(ar9300_calibration_data_read( + ah, AH9300(ah)->calibration_data_source_address, + (u_int8_t *)mptr, mdata_size) == AH_TRUE) + { + nptr = mdata_size; + } + /*nptr=ar9300EepromRestoreInternalAddress(ah, mptr, mdataSize, CalibrationDataSourceAddress);*/ + if(nptr < 0) + { + AH9300(ah)->calibration_data_source = calibration_data_none; + AH9300(ah)->calibration_data_source_address = 0; + } + } +#endif + if (nptr < 0) { + ath_hal_printf(ah, "%s[%d] No vaid CAL, calling default template\n", + __func__, __LINE__); + nptr = ar9300_eeprom_restore_something(ah, mptr, mdata_size); + } + + return nptr; +} + +/******************************************************************************/ +/*! +** \brief Eeprom Swapping Function +** +** This function will swap the contents of the "longer" EEPROM data items +** to ensure they are consistent with the endian requirements for the platform +** they are being compiled for +** +** \param eh Pointer to the EEPROM data structure +** \return N/A +*/ +#if AH_BYTE_ORDER == AH_BIG_ENDIAN +void +ar9300_swap_eeprom(ar9300_eeprom_t *eep) +{ + u_int32_t dword; + u_int16_t word; + int i; + + word = __bswap16(eep->base_eep_header.reg_dmn[0]); + eep->base_eep_header.reg_dmn[0] = word; + + word = __bswap16(eep->base_eep_header.reg_dmn[1]); + eep->base_eep_header.reg_dmn[1] = word; + + dword = __bswap32(eep->base_eep_header.swreg); + eep->base_eep_header.swreg = dword; + + dword = __bswap32(eep->modal_header_2g.ant_ctrl_common); + eep->modal_header_2g.ant_ctrl_common = dword; + + dword = __bswap32(eep->modal_header_2g.ant_ctrl_common2); + eep->modal_header_2g.ant_ctrl_common2 = dword; + + dword = __bswap32(eep->modal_header_2g.paprd_rate_mask_ht20); + eep->modal_header_2g.paprd_rate_mask_ht20 = dword; + + dword = __bswap32(eep->modal_header_2g.paprd_rate_mask_ht40); + eep->modal_header_2g.paprd_rate_mask_ht40 = dword; + + dword = __bswap32(eep->modal_header_5g.ant_ctrl_common); + eep->modal_header_5g.ant_ctrl_common = dword; + + dword = __bswap32(eep->modal_header_5g.ant_ctrl_common2); + eep->modal_header_5g.ant_ctrl_common2 = dword; + + dword = __bswap32(eep->modal_header_5g.paprd_rate_mask_ht20); + eep->modal_header_5g.paprd_rate_mask_ht20 = dword; + + dword = __bswap32(eep->modal_header_5g.paprd_rate_mask_ht40); + eep->modal_header_5g.paprd_rate_mask_ht40 = dword; + + for (i = 0; i < OSPREY_MAX_CHAINS; i++) { + word = __bswap16(eep->modal_header_2g.ant_ctrl_chain[i]); + eep->modal_header_2g.ant_ctrl_chain[i] = word; + + word = __bswap16(eep->modal_header_5g.ant_ctrl_chain[i]); + eep->modal_header_5g.ant_ctrl_chain[i] = word; + } +} + +void ar9300_eeprom_template_swap(void) +{ + int it; + ar9300_eeprom_t *dptr; + + for (it = 0; it < ARRAY_LENGTH(default9300); it++) { + dptr = ar9300_eeprom_struct_default(it); + if (dptr != 0) { + ar9300_swap_eeprom(dptr); + } + } +} +#endif + + +/* + * Restore the configuration structure by reading the eeprom. + * This function destroys any existing in-memory structure content. + */ +HAL_BOOL +ar9300_eeprom_restore(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + ar9300_eeprom_t *mptr; + int mdata_size; + HAL_BOOL status = AH_FALSE; + + mptr = &ahp->ah_eeprom; + mdata_size = ar9300_eeprom_struct_size(); + + if (mptr != 0 && mdata_size > 0) { +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + ar9300_eeprom_template_swap(); + ar9300_swap_eeprom(mptr); +#endif + /* + * At this point, mptr points to the eeprom data structure + * in it's "default" state. If this is big endian, swap the + * data structures back to "little endian" form. + */ + if (ar9300_eeprom_restore_internal(ah, mptr, mdata_size) >= 0) { + status = AH_TRUE; + } + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + /* Second Swap, back to Big Endian */ + ar9300_eeprom_template_swap(); + ar9300_swap_eeprom(mptr); +#endif + + } + ahp->ah_2g_paprd_rate_mask_ht40 = + mptr->modal_header_2g.paprd_rate_mask_ht40; + ahp->ah_2g_paprd_rate_mask_ht20 = + mptr->modal_header_2g.paprd_rate_mask_ht20; + ahp->ah_5g_paprd_rate_mask_ht40 = + mptr->modal_header_5g.paprd_rate_mask_ht40; + ahp->ah_5g_paprd_rate_mask_ht20 = + mptr->modal_header_5g.paprd_rate_mask_ht20; + return status; +} + +int32_t ar9300_thermometer_get(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int thermometer; + thermometer = + (ahp->ah_eeprom.base_eep_header.misc_configuration >> 1) & 0x3; + thermometer--; + return thermometer; +} + +HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah) +{ + int thermometer = ar9300_thermometer_get(ah); + +/* ch0_RXTX4 */ +/*#define AR_PHY_65NM_CH0_RXTX4 AR_PHY_65NM(ch0_RXTX4)*/ +#define AR_PHY_65NM_CH1_RXTX4 AR_PHY_65NM(ch1_RXTX4) +#define AR_PHY_65NM_CH2_RXTX4 AR_PHY_65NM(ch2_RXTX4) +/*#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000*/ +/*#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28*/ +#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR_S 29 +#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR \ + (0x1<ah_eeprom; + tuning_caps_params = eep->base_eep_header.params_for_tuning_caps[0]; + return tuning_caps_params; +} + +/* + * Read the tuning caps params from eeprom and set to correct register. + * To regulation the frequency accuracy. + */ +HAL_BOOL ar9300_tuning_caps_apply(struct ath_hal *ah) +{ + int tuning_caps_params; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + tuning_caps_params = ar9300_tuning_caps_params_get(ah); + if ((eep->base_eep_header.feature_enable & 0x40) >> 6) { + tuning_caps_params &= 0x7f; + + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah)) { + return AH_TRUE; + } else if (AR_SREV_SCORPION(ah)) { + OS_REG_RMW_FIELD(ah, + AR_SCORPION_CH0_XTAL, AR_OSPREY_CHO_XTAL_CAPINDAC, + tuning_caps_params); + OS_REG_RMW_FIELD(ah, + AR_SCORPION_CH0_XTAL, AR_OSPREY_CHO_XTAL_CAPOUTDAC, + tuning_caps_params); + } else { + OS_REG_RMW_FIELD(ah, + AR_OSPREY_CH0_XTAL, AR_OSPREY_CHO_XTAL_CAPINDAC, + tuning_caps_params); + OS_REG_RMW_FIELD(ah, + AR_OSPREY_CH0_XTAL, AR_OSPREY_CHO_XTAL_CAPOUTDAC, + tuning_caps_params); + } + + } + return AH_TRUE; +} + +/* + * Read the tx_frame_to_xpa_on param from eeprom and apply the value to + * correct register. + */ +HAL_BOOL ar9300_xpa_timing_control_apply(struct ath_hal *ah, HAL_BOOL is_2ghz) +{ + u_int8_t xpa_timing_control; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + if ((eep->base_eep_header.feature_enable & 0x80) >> 7) { + if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah) || AR_SREV_WASP(ah)) { + if (is_2ghz) { + xpa_timing_control = eep->modal_header_2g.tx_frame_to_xpa_on; + OS_REG_RMW_FIELD(ah, + AR_PHY_XPA_TIMING_CTL, AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, + xpa_timing_control); + } else { + xpa_timing_control = eep->modal_header_5g.tx_frame_to_xpa_on; + OS_REG_RMW_FIELD(ah, + AR_PHY_XPA_TIMING_CTL, AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, + xpa_timing_control); + } + } + } + return AH_TRUE; +} + + +/* + * Read the xLNA_bias_strength param from eeprom and apply the value to + * correct register. + */ +HAL_BOOL ar9300_x_lNA_bias_strength_apply(struct ath_hal *ah, HAL_BOOL is_2ghz) +{ + u_int8_t x_lNABias; + u_int32_t value = 0; + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + + if ((eep->base_eep_header.misc_configuration & 0x40) >> 6) { + if (AR_SREV_OSPREY(ah)) { + if (is_2ghz) { + x_lNABias = eep->modal_header_2g.xLNA_bias_strength; + } else { + x_lNABias = eep->modal_header_5g.xLNA_bias_strength; + } + value = x_lNABias & ( 0x03 ); // bit0,1 for chain0 + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, value); + value = (x_lNABias >> 2) & ( 0x03 ); // bit2,3 for chain1 + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, value); + value = (x_lNABias >> 4) & ( 0x03 ); // bit4,5 for chain2 + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, value); + } + } + return AH_TRUE; +} + + +/* + * Read EEPROM header info and program the device for correct operation + * given the channel value. + */ +HAL_BOOL +ar9300_eeprom_set_board_values(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) +{ + ar9300_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan)); + + ar9300_xpa_timing_control_apply(ah, IS_CHAN_2GHZ(chan)); + + ar9300_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan)); + ar9300_drive_strength_apply(ah); + + ar9300_x_lNA_bias_strength_apply(ah, IS_CHAN_2GHZ(chan)); + + /* wait for Poseidon internal regular turnning */ + /* for Hornet we move it before initPLL to avoid an access issue */ + /* Function not used when EMULATION. */ + if (!AR_SREV_HORNET(ah) && !AR_SREV_WASP(ah)) { + ar9300_internal_regulator_apply(ah); + } + + ar9300_attenuation_apply(ah, chan->channel); + ar9300_quick_drop_apply(ah, chan->channel); + ar9300_thermometer_apply(ah); + if(!AR_SREV_WASP(ah)) + { + ar9300_tuning_caps_apply(ah); + } + + ar9300_tx_end_to_xpab_off_apply(ah, chan->channel); + + return AH_TRUE; +} + +u_int8_t * +ar9300_eeprom_get_spur_chans_ptr(struct ath_hal *ah, HAL_BOOL is_2ghz) +{ + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + + if (is_2ghz) { + return &(eep->modal_header_2g.spur_chans[0]); + } else { + return &(eep->modal_header_5g.spur_chans[0]); + } +} + +static u_int8_t ar9300_eeprom_get_tx_gain_table_number_max(struct ath_hal *ah) +{ + unsigned long tx_gain_table_max; + tx_gain_table_max = OS_REG_READ_FIELD(ah, + AR_PHY_TPC_7, AR_PHY_TPC_7_TX_GAIN_TABLE_MAX); + return tx_gain_table_max; +} + +u_int8_t ar9300_eeprom_tx_gain_table_index_max_apply(struct ath_hal *ah, u_int16_t channel) +{ + unsigned int index; + ar9300_eeprom_t *ahp_Eeprom; + struct ath_hal_9300 *ahp = AH9300(ah); + + ahp_Eeprom = &ahp->ah_eeprom; + + if (ahp_Eeprom->base_ext1.misc_enable == 0) + return AH_FALSE; + + if (channel < 4000) + { + index = ahp_Eeprom->modal_header_2g.tx_gain_cap; + } + else + { + index = ahp_Eeprom->modal_header_5g.tx_gain_cap; + } + + OS_REG_RMW_FIELD(ah, + AR_PHY_TPC_7, AR_PHY_TPC_7_TX_GAIN_TABLE_MAX, index); + return AH_TRUE; +} + +static u_int8_t ar9300_eeprom_get_pcdac_tx_gain_table_i(struct ath_hal *ah, + int i, u_int8_t *pcdac) +{ + unsigned long tx_gain; + u_int8_t tx_gain_table_max; + tx_gain_table_max = ar9300_eeprom_get_tx_gain_table_number_max(ah); + if (i <= 0 || i > tx_gain_table_max) { + *pcdac = 0; + return AH_FALSE; + } + + tx_gain = OS_REG_READ(ah, AR_PHY_TXGAIN_TAB(1) + i * 4); + *pcdac = ((tx_gain >> 24) & 0xff); + return AH_TRUE; +} + +u_int8_t ar9300_eeprom_set_tx_gain_cap(struct ath_hal *ah, + int *tx_gain_max) +// pcdac read back from reg, read back value depends on reset 2GHz/5GHz ini +// tx_gain_table, this function will be called twice after each +// band's calibration. +// after 2GHz cal, tx_gain_max[0] has 2GHz, calibration max txgain, +// tx_gain_max[1]=-100 +// after 5GHz cal, tx_gain_max[0],tx_gain_max[1] have calibration +// value for both band +// reset is on 5GHz, reg reading from tx_gain_table is for 5GHz, +// so program can't recalculate 2g.tx_gain_cap at this point. +{ + int i = 0, ig, im = 0; + u_int8_t pcdac = 0; + u_int8_t tx_gain_table_max; + ar9300_eeprom_t *ahp_Eeprom; + struct ath_hal_9300 *ahp = AH9300(ah); + + ahp_Eeprom = &ahp->ah_eeprom; + + if (ahp_Eeprom->base_ext1.misc_enable == 0) + return AH_FALSE; + + tx_gain_table_max = ar9300_eeprom_get_tx_gain_table_number_max(ah); + + for (i = 0; i < 2; i++) { + if (tx_gain_max[i]>-100) { // -100 didn't cal that band. + if ( i== 0) { + if (tx_gain_max[1]>-100) { + continue; + // both band are calibrated, skip 2GHz 2g.tx_gain_cap reset + } + } + for (ig = 1; ig <= tx_gain_table_max; ig++) { + if (ah != 0 && ah->ah_reset != 0) + { + ar9300_eeprom_get_pcdac_tx_gain_table_i(ah, ig, &pcdac); + if (pcdac >= tx_gain_max[i]) + break; + } + } + if (ig+1 <= tx_gain_table_max) { + if (pcdac == tx_gain_max[i]) + im = ig; + else + im = ig + 1; + if (i == 0) { + ahp_Eeprom->modal_header_2g.tx_gain_cap = im; + } else { + ahp_Eeprom->modal_header_5g.tx_gain_cap = im; + } + } else { + if (i == 0) { + ahp_Eeprom->modal_header_2g.tx_gain_cap = ig; + } else { + ahp_Eeprom->modal_header_5g.tx_gain_cap = ig; + } + } + } + } + return AH_TRUE; +} + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_gpio.c b/hal/ar9300/ar9300_gpio.c new file mode 100644 index 000000000000..edbdf1ab5894 --- /dev/null +++ b/hal/ar9300/ar9300_gpio.c @@ -0,0 +1,652 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" +#include "ah_devid.h" +#ifdef AH_DEBUG +#include "ah_desc.h" /* NB: for HAL_PHYERR* */ +#endif + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300phy.h" + +#define AR_GPIO_BIT(_gpio) (1 << (_gpio)) + +/* + * Configure GPIO Output Mux control + */ +#ifdef UMAC_SUPPORT_SMARTANTENNA +static void ar9340_soc_gpio_cfg_output_mux( + struct ath_hal *ah, + u_int32_t gpio, + u_int32_t ah_signal_type) +{ +#define ADDR_READ(addr) (*((volatile u_int32_t *)(addr))) +#define ADDR_WRITE(addr, b) (void)((*(volatile u_int32_t *) (addr)) = (b)) +#define AR9340_SOC_GPIO_FUN0 0xB804002c +#define AR9340_SOC_GPIO_OE 0xB8040000 +#if ATH_SMARTANTENNA_DISABLE_JTAG +#define AR9340_SOC_GPIO_FUNCTION (volatile u_int32_t*) 0xB804006c +#define WASP_DISABLE_JTAG 0x2 +#define MAX_JTAG_GPIO_PIN 1 +#endif + u_int8_t out_func, shift; + u_int32_t flags; + volatile u_int32_t* address; + + if (!ah_signal_type){ + return; + } +#if ATH_SMARTANTENNA_DISABLE_JTAG +/* + * To use GPIO pins 0 and 1 for controling antennas, JTAG needs to disabled. + */ + if (gpio <= MAX_JTAG_GPIO_PIN) { + flags = ADDR_READ(AR9340_SOC_GPIO_FUNCTION); + flags |= WASP_DISABLE_JTAG; + ADDR_WRITE(AR9340_SOC_GPIO_FUNCTION, flags); + } +#endif + out_func = gpio / 4; + shift = (gpio % 4); + address = (volatile u_int32_t *)(AR9340_SOC_GPIO_FUN0 + (out_func*4)); + + flags = ADDR_READ(address); + flags |= ah_signal_type << (8*shift); + ADDR_WRITE(address, flags); + flags = ADDR_READ(AR9340_SOC_GPIO_OE); + flags &= ~(1 << gpio); + ADDR_WRITE(AR9340_SOC_GPIO_OE, flags); + +} +#endif + +static void +ar9300_gpio_cfg_output_mux(struct ath_hal *ah, u_int32_t gpio, u_int32_t type) +{ + int addr; + u_int32_t gpio_shift; + + /* each MUX controls 6 GPIO pins */ + if (gpio > 11) { + addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3); + } else if (gpio > 5) { + addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2); + } else { + addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1); + } + + /* + * 5 bits per GPIO pin. + * Bits 0..4 for 1st pin in that mux, + * bits 5..9 for 2nd pin, etc. + */ + gpio_shift = (gpio % 6) * 5; + + OS_REG_RMW(ah, addr, (type << gpio_shift), (0x1f << gpio_shift)); +} + +/* + * Configure GPIO Output lines + */ +HAL_BOOL +ar9300_gpio_cfg_output( + struct ath_hal *ah, + u_int32_t gpio, + HAL_GPIO_OUTPUT_MUX_TYPE hal_signal_type) +{ + u_int32_t ah_signal_type; + u_int32_t gpio_shift; + u_int8_t smart_ant = 0; + static const u_int32_t mux_signal_conversion_table[] = { + /* HAL_GPIO_OUTPUT_MUX_AS_OUTPUT */ + AR_GPIO_OUTPUT_MUX_AS_OUTPUT, + /* HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED */ + AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED, + /* HAL_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED */ + AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED, + /* HAL_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED */ + AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED, + /* HAL_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED */ + AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED, + /* HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE */ + AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL, + /* HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME */ + AR_GPIO_OUTPUT_MUX_AS_TX_FRAME, + /* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA */ + AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, + /* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK */ + AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, + /* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA */ + AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, + /* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK */ + AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, + /* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX */ + AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX, + /* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX */ + AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX, + /* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX */ + AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX, + /* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX */ + AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX, + /* HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE */ + AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, + /* HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA */ + AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, + /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0 */ + AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, + /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1 */ + AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, + /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 */ + AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2, + /* HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_SWCOM3 */ + AR_GPIO_OUTPUT_MUX_AS_SWCOM3, + }; + + HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins); + if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || + (gpio == AR9382_GPIO_PIN_11_RESERVED) || + (gpio == AR9382_GPIO_9_INPUT_ONLY)) + { + return AH_FALSE; + } + + /* Convert HAL signal type definitions to hardware-specific values. */ + if (hal_signal_type < ARRAY_LENGTH(mux_signal_conversion_table)) + { + ah_signal_type = mux_signal_conversion_table[hal_signal_type]; + } else { + return AH_FALSE; + } + + if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) { + OS_REG_SET_BIT(ah, + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE); + } + +#if UMAC_SUPPORT_SMARTANTENNA + /* Get the pin and func values for smart antenna */ + switch (ah_signal_type) + { + case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0: + gpio = ATH_GPIOPIN_ANTCHAIN0; + ah_signal_type = ATH_GPIOFUNC_ANTCHAIN0; + smart_ant = 1; + break; + case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1: + gpio = ATH_GPIOPIN_ANTCHAIN1; + ah_signal_type = ATH_GPIOFUNC_ANTCHAIN1; + smart_ant = 1; + break; + case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2: + gpio = ATH_GPIOPIN_ANTCHAIN2; + ah_signal_type = ATH_GPIOFUNC_ANTCHAIN2; + smart_ant = 1; + break; +#if ATH_SMARTANTENNA_ROUTE_SWCOM_TO_GPIO + case AR_GPIO_OUTPUT_MUX_AS_SWCOM3: + gpio = ATH_GPIOPIN_ROUTE_SWCOM3; + ah_signal_type = ATH_GPIOFUNC_ROUTE_SWCOM3; + smart_ant = 1; + break; +#endif + default: + break; + } +#endif + + if (smart_ant && (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah))) + { +#ifdef UMAC_SUPPORT_SMARTANTENNA + ar9340_soc_gpio_cfg_output_mux(ah, gpio, ah_signal_type); +#endif + return AH_TRUE; + } else + { + /* Configure the MUX */ + ar9300_gpio_cfg_output_mux(ah, gpio, ah_signal_type); + } + + /* 2 bits per output mode */ + gpio_shift = 2 * gpio; + + OS_REG_RMW(ah, + AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), + (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), + (AR_GPIO_OE_OUT_DRV << gpio_shift)); + return AH_TRUE; +} + +/* + * Configure GPIO Output lines -LED off + */ +HAL_BOOL +ar9300_gpio_cfg_output_led_off( + struct ath_hal *ah, + u_int32_t gpio, + HAL_GPIO_OUTPUT_MUX_TYPE halSignalType) +{ +#define N(a) (sizeof(a) / sizeof(a[0])) + u_int32_t ah_signal_type; + u_int32_t gpio_shift; + u_int8_t smart_ant = 0; + + static const u_int32_t mux_signal_conversion_table[] = { + /* HAL_GPIO_OUTPUT_MUX_AS_OUTPUT */ + AR_GPIO_OUTPUT_MUX_AS_OUTPUT, + /* HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED */ + AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED, + /* HAL_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED */ + AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED, + /* HAL_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED */ + AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED, + /* HAL_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED */ + AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED, + /* HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE */ + AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL, + /* HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME */ + AR_GPIO_OUTPUT_MUX_AS_TX_FRAME, + /* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA */ + AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, + /* HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK */ + AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, + /* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA */ + AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, + /* HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK */ + AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, + /* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX */ + AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX, + /* HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX */ + AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX, + /* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX */ + AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX, + /* HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX */ + AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX, + AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, + AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, + AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, + AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, + AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 + }; + HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins); + + /* Convert HAL signal type definitions to hardware-specific values. */ + if (halSignalType < ARRAY_LENGTH(mux_signal_conversion_table)) + { + ah_signal_type = mux_signal_conversion_table[halSignalType]; + } else { + return AH_FALSE; + } +#if UMAC_SUPPORT_SMARTANTENNA + /* Get the pin and func values for smart antenna */ + switch (halSignalType) + { + case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0: + gpio = ATH_GPIOPIN_ANTCHAIN0; + ah_signal_type = ATH_GPIOFUNC_ANTCHAIN0; + smart_ant = 1; + break; + case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1: + gpio = ATH_GPIOPIN_ANTCHAIN1; + ah_signal_type = ATH_GPIOFUNC_ANTCHAIN1; + smart_ant = 1; + break; + case AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2: + gpio = ATH_GPIOPIN_ANTCHAIN2; + ah_signal_type = ATH_GPIOFUNC_ANTCHAIN2; + smart_ant = 1; + break; + default: + break; + } +#endif + + if (smart_ant && AR_SREV_WASP(ah)) + { + return AH_FALSE; + } + + // Configure the MUX + ar9300_gpio_cfg_output_mux(ah, gpio, ah_signal_type); + + // 2 bits per output mode + gpio_shift = 2*gpio; + + OS_REG_RMW(ah, + AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), + (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), + (AR_GPIO_OE_OUT_DRV << gpio_shift)); + + return AH_TRUE; +#undef N +} + +/* + * Configure GPIO Input lines + */ +HAL_BOOL +ar9300_gpio_cfg_input(struct ath_hal *ah, u_int32_t gpio) +{ + u_int32_t gpio_shift; + + HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins); + if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || + (gpio == AR9382_GPIO_PIN_11_RESERVED) || + (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM)) + { + return AH_FALSE; + } + + if (gpio <= AR9382_MAX_JTAG_GPIO_PIN_NUM) { + OS_REG_SET_BIT(ah, + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE); + } + /* TODO: configure input mux for AR9300 */ + /* If configured as input, set output to tristate */ + gpio_shift = 2 * gpio; + + OS_REG_RMW(ah, + AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), + (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), + (AR_GPIO_OE_OUT_DRV << gpio_shift)); + return AH_TRUE; +} + +/* + * Once configured for I/O - set output lines + * output the level of GPio PIN without care work mode + */ +HAL_BOOL +ar9300_gpio_set(struct ath_hal *ah, u_int32_t gpio, u_int32_t val) +{ + HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins); + if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || + (gpio == AR9382_GPIO_PIN_11_RESERVED) || + (gpio == AR9382_GPIO_9_INPUT_ONLY)) + { + return AH_FALSE; + } + OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT), + ((val & 1) << gpio), AR_GPIO_BIT(gpio)); + + return AH_TRUE; +} + +/* + * Once configured for I/O - get input lines + */ +u_int32_t +ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio) +{ + u_int32_t gpio_in; + HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins); + if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || + (gpio == AR9382_GPIO_PIN_11_RESERVED)) + { + return 0xffffffff; + } + + gpio_in = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN)); + OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN), + (1 << gpio), AR_GPIO_BIT(gpio)); + return (MS(gpio_in, AR_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0; +} + +u_int32_t +ar9300_gpio_get_intr(struct ath_hal *ah) +{ + unsigned int mask = 0; + struct ath_hal_9300 *ahp = AH9300(ah); + + mask = ahp->ah_gpio_cause; + return mask; +} + +/* + * Set the GPIO Interrupt + * Sync and Async interrupts are both set/cleared. + * Async GPIO interrupts may not be raised when the chip is put to sleep. + */ +void +ar9300_gpio_set_intr(struct ath_hal *ah, u_int gpio, u_int32_t ilevel) +{ + + + int i, reg_bit; + u_int32_t reg_val; + u_int32_t regs[2], shifts[2]; + +#ifdef AH_ASSERT + u_int32_t gpio_mask; + u_int32_t old_field_val = 0, field_val = 0; +#endif + +#ifdef ATH_GPIO_USE_ASYNC_CAUSE + regs[0] = AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE); + regs[1] = AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK); + shifts[0] = AR_INTR_ASYNC_ENABLE_GPIO_S; + shifts[1] = AR_INTR_ASYNC_MASK_GPIO_S; +#else + regs[0] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE); + regs[1] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK); + shifts[0] = AR_INTR_SYNC_ENABLE_GPIO_S; + shifts[1] = AR_INTR_SYNC_MASK_GPIO_S; +#endif + + HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins); + + if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || + (gpio == AR9382_GPIO_PIN_11_RESERVED) || + (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM)) + { + return; + } + +#ifdef AH_ASSERT + gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins) - 1; +#endif + + if (ilevel == HAL_GPIO_INTR_DISABLE) { + /* clear this GPIO's bit in the interrupt registers */ + for (i = 0; i < ARRAY_LENGTH(regs); i++) { + reg_val = OS_REG_READ(ah, regs[i]); + reg_bit = shifts[i] + gpio; + reg_val &= ~(1 << reg_bit); + OS_REG_WRITE(ah, regs[i], reg_val); + + /* check that each register has same GPIOs enabled */ +#ifdef AH_ASSERT + field_val = (reg_val >> shifts[i]) & gpio_mask; + HALASSERT(i == 0 || old_field_val == field_val); + old_field_val = field_val; +#endif + } + + } else { + reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL)); + reg_bit = gpio; + if (ilevel == HAL_GPIO_INTR_HIGH) { + /* 0 == interrupt on pin high */ + reg_val &= ~(1 << reg_bit); + } else if (ilevel == HAL_GPIO_INTR_LOW) { + /* 1 == interrupt on pin low */ + reg_val |= (1 << reg_bit); + } + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), reg_val); + + /* set this GPIO's bit in the interrupt registers */ + for (i = 0; i < ARRAY_LENGTH(regs); i++) { + reg_val = OS_REG_READ(ah, regs[i]); + reg_bit = shifts[i] + gpio; + reg_val |= (1 << reg_bit); + OS_REG_WRITE(ah, regs[i], reg_val); + + /* check that each register has same GPIOs enabled */ +#ifdef AH_ASSERT + field_val = (reg_val >> shifts[i]) & gpio_mask; + HALASSERT(i == 0 || old_field_val == field_val); + old_field_val = field_val; +#endif + } + } +} + +u_int32_t +ar9300_gpio_get_polarity(struct ath_hal *ah) +{ + return OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL)); + +} + +void +ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t pol_map, + u_int32_t changed_mask) +{ + u_int32_t gpio_mask; + + gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins) - 1; + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), gpio_mask & pol_map); + +#ifndef ATH_GPIO_USE_ASYNC_CAUSE + /* + * For SYNC_CAUSE type interrupts, we need to clear the cause register + * explicitly. Otherwise an interrupt with the original polarity setting + * will come up immediately (if there is already an interrupt source), + * which is not what we want usually. + */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR), + changed_mask << AR_INTR_SYNC_ENABLE_GPIO_S); + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR)); +#endif +} + +/* + * get the GPIO input pin mask + * gpio0 - gpio13 + * gpio8, gpio11, regard as reserved by the chip ar9382 + */ + +u_int32_t +ar9300_gpio_get_mask(struct ath_hal *ah) +{ + u_int32_t mask = (1 << (AR9382_MAX_GPIO_INPUT_PIN_NUM + 1) ) - 1; + + if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) { + mask = (1 << AR9382_MAX_GPIO_PIN_NUM) - 1; + mask &= ~(1 << AR9382_GPIO_PIN_8_RESERVED | + 1 << AR9382_GPIO_PIN_11_RESERVED); + } + return mask; +} + +int +ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map) +{ + u_int32_t invalid = ~((1 << (AR9382_MAX_GPIO_INPUT_PIN_NUM + 1)) - 1); + + if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) { + invalid = ~((1 << AR9382_MAX_GPIO_PIN_NUM) - 1); + invalid |= 1 << AR9382_GPIO_PIN_8_RESERVED | + 1 << AR9382_GPIO_PIN_11_RESERVED; + } + if (mask & invalid) { + ath_hal_printf(ah, "%s: invalid GPIO mask 0x%x\n", __func__, mask); + return -1; + } + AH9300(ah)->ah_gpio_mask = mask; + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), mask & pol_map); + + return 0; +} + +#ifdef AH_DEBUG +void ar9300_gpio_show(struct ath_hal *ah); +void ar9300_gpio_show(struct ath_hal *ah) +{ + ath_hal_printf(ah, "--- 9382 GPIOs ---(ah=%p)\n", ah ); + ath_hal_printf(ah, + "AH9300(_ah)->ah_hostifregs:%p\r\n", &(AH9300(ah)->ah_hostifregs)); + ath_hal_printf(ah, + "GPIO_OUT: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT))); + ath_hal_printf(ah, + "GPIO_IN: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN))); + ath_hal_printf(ah, + "GPIO_OE: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT))); + ath_hal_printf(ah, + "GPIO_OE1_OUT: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT))); + ath_hal_printf(ah, + "GPIO_INTR_POLAR: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL))); + ath_hal_printf(ah, + "GPIO_INPUT_VALUE: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL))); + ath_hal_printf(ah, + "GPIO_INPUT_MUX1: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1))); + ath_hal_printf(ah, + "GPIO_INPUT_MUX2: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2))); + ath_hal_printf(ah, + "GPIO_OUTPUT_MUX1: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1))); + ath_hal_printf(ah, + "GPIO_OUTPUT_MUX2: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2))); + ath_hal_printf(ah, + "GPIO_OUTPUT_MUX3: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3))); + ath_hal_printf(ah, + "GPIO_INPUT_STATE: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INPUT_STATE))); + ath_hal_printf(ah, + "GPIO_PDPU: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU))); + ath_hal_printf(ah, + "GPIO_DS: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_DS))); + ath_hal_printf(ah, + "AR_INTR_ASYNC_ENABLE: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE))); + ath_hal_printf(ah, + "AR_INTR_ASYNC_MASK: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK))); + ath_hal_printf(ah, + "AR_INTR_SYNC_ENABLE: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE))); + ath_hal_printf(ah, + "AR_INTR_SYNC_MASK: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK))); + ath_hal_printf(ah, + "AR_INTR_ASYNC_CAUSE: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE))); + ath_hal_printf(ah, + "AR_INTR_SYNC_CAUSE: 0x%08X\n", + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE))); + +} +#endif /*AH_DEBUG*/ + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_interrupts.c b/hal/ar9300/ar9300_interrupts.c new file mode 100644 index 000000000000..cbd83c679773 --- /dev/null +++ b/hal/ar9300/ar9300_interrupts.c @@ -0,0 +1,767 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300phy.h" + +/* + * Checks to see if an interrupt is pending on our NIC + * + * Returns: TRUE if an interrupt is pending + * FALSE if not + */ +HAL_BOOL +ar9300_is_interrupt_pending(struct ath_hal *ah) +{ + u_int32_t sync_en_def = AR9300_INTR_SYNC_DEFAULT; + u_int32_t host_isr; + + /* + * Some platforms trigger our ISR before applying power to + * the card, so make sure. + */ + host_isr = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE)); + if ((host_isr & AR_INTR_ASYNC_USED) && (host_isr != AR_INTR_SPURIOUS)) { + return AH_TRUE; + } + + host_isr = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)); + if (AR_SREV_POSEIDON(ah)) { + sync_en_def = AR9300_INTR_SYNC_DEF_NO_HOST1_PERR; + } + else if (AR_SREV_WASP(ah)) { + sync_en_def = AR9340_INTR_SYNC_DEFAULT; + } + + if ((host_isr & (sync_en_def | AR_INTR_SYNC_MASK_GPIO)) && + (host_isr != AR_INTR_SPURIOUS)) { + return AH_TRUE; + } + + return AH_FALSE; +} + +/* + * Reads the Interrupt Status Register value from the NIC, thus deasserting + * the interrupt line, and returns both the masked and unmasked mapped ISR + * values. The value returned is mapped to abstract the hw-specific bit + * locations in the Interrupt Status Register. + * + * Returns: A hardware-abstracted bitmap of all non-masked-out + * interrupts pending, as well as an unmasked value + */ +#define MAP_ISR_S2_HAL_CST 6 /* Carrier sense timeout */ +#define MAP_ISR_S2_HAL_GTT 6 /* Global transmit timeout */ +#define MAP_ISR_S2_HAL_TIM 3 /* TIM */ +#define MAP_ISR_S2_HAL_CABEND 0 /* CABEND */ +#define MAP_ISR_S2_HAL_DTIMSYNC 7 /* DTIMSYNC */ +#define MAP_ISR_S2_HAL_DTIM 7 /* DTIM */ +#define MAP_ISR_S2_HAL_TSFOOR 4 /* Rx TSF out of range */ +#define MAP_ISR_S2_HAL_BBPANIC 6 /* Panic watchdog IRQ from BB */ +HAL_BOOL +ar9300_get_pending_interrupts( + struct ath_hal *ah, + HAL_INT *masked, + HAL_INT_TYPE type, + u_int8_t msi, + HAL_BOOL nortc) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL ret_val = AH_TRUE; + u_int32_t isr = 0; + u_int32_t mask2 = 0; + u_int32_t sync_cause = 0; + u_int32_t async_cause; + u_int32_t msi_pend_addr_mask = 0; + u_int32_t sync_en_def = AR9300_INTR_SYNC_DEFAULT; + HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + + *masked = 0; + + if (!nortc) { + if (HAL_INT_MSI == type) { + if (msi == HAL_MSIVEC_RXHP) { + OS_REG_WRITE(ah, AR_ISR, AR_ISR_HP_RXOK); + *masked = HAL_INT_RXHP; + goto end; + } else if (msi == HAL_MSIVEC_RXLP) { + OS_REG_WRITE(ah, AR_ISR, + (AR_ISR_LP_RXOK | AR_ISR_RXMINTR | AR_ISR_RXINTM)); + *masked = HAL_INT_RXLP; + goto end; + } else if (msi == HAL_MSIVEC_TX) { + OS_REG_WRITE(ah, AR_ISR, AR_ISR_TXOK); + *masked = HAL_INT_TX; + goto end; + } else if (msi == HAL_MSIVEC_MISC) { + /* + * For the misc MSI event fall through and determine the cause. + */ + } + } + } + + /* Make sure mac interrupt is pending in async interrupt cause register */ + async_cause = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE)); + if (async_cause & AR_INTR_ASYNC_USED) { + /* + * RTC may not be on since it runs on a slow 32khz clock + * so check its status to be sure + */ + if (!nortc && + (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == + AR_RTC_STATUS_ON) + { + isr = OS_REG_READ(ah, AR_ISR); + } + } + + if (AR_SREV_POSEIDON(ah)) { + sync_en_def = AR9300_INTR_SYNC_DEF_NO_HOST1_PERR; + } + else if (AR_SREV_WASP(ah)) { + sync_en_def = AR9340_INTR_SYNC_DEFAULT; + } + + sync_cause = + OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)) & + (sync_en_def | AR_INTR_SYNC_MASK_GPIO); + + if (!isr && !sync_cause && !async_cause) { + ret_val = AH_FALSE; + goto end; + } + + if (isr) { + if (isr & AR_ISR_BCNMISC) { + u_int32_t isr2; + isr2 = OS_REG_READ(ah, AR_ISR_S2); + + /* Translate ISR bits to HAL values */ + mask2 |= ((isr2 & AR_ISR_S2_TIM) >> MAP_ISR_S2_HAL_TIM); + mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> MAP_ISR_S2_HAL_DTIM); + mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> MAP_ISR_S2_HAL_DTIMSYNC); + mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> MAP_ISR_S2_HAL_CABEND); + mask2 |= ((isr2 & AR_ISR_S2_GTT) << MAP_ISR_S2_HAL_GTT); + mask2 |= ((isr2 & AR_ISR_S2_CST) << MAP_ISR_S2_HAL_CST); + mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> MAP_ISR_S2_HAL_TSFOOR); + mask2 |= ((isr2 & AR_ISR_S2_BBPANIC) >> MAP_ISR_S2_HAL_BBPANIC); + + if (!p_cap->hal_isr_rac_support) { + /* + * EV61133 (missing interrupts due to ISR_RAC): + * If not using ISR_RAC, clear interrupts by writing to ISR_S2. + * This avoids a race condition where a new BCNMISC interrupt + * could come in between reading the ISR and clearing the + * interrupt via the primary ISR. We therefore clear the + * interrupt via the secondary, which avoids this race. + */ + OS_REG_WRITE(ah, AR_ISR_S2, isr2); + isr &= ~AR_ISR_BCNMISC; + } + } + + /* Use AR_ISR_RAC only if chip supports it. + * See EV61133 (missing interrupts due to ISR_RAC) + */ + if (p_cap->hal_isr_rac_support) { + isr = OS_REG_READ(ah, AR_ISR_RAC); + } + if (isr == 0xffffffff) { + *masked = 0; + ret_val = AH_FALSE; + goto end; + } + + *masked = isr & HAL_INT_COMMON; + + /* + * When interrupt mitigation is switched on, we fake a normal RX or TX + * interrupt when we received a mitigated interrupt. This way, the upper + * layer do not need to know about feature. + */ + if (ahp->ah_intr_mitigation_rx) { + /* Only Rx interrupt mitigation. No Tx intr. mitigation. */ + if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) { + *masked |= HAL_INT_RXLP; + } + } + if (ahp->ah_intr_mitigation_tx) { + if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) { + *masked |= HAL_INT_TX; + } + } + + if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) { + *masked |= HAL_INT_RXLP; + } + if (isr & AR_ISR_HP_RXOK) { + *masked |= HAL_INT_RXHP; + } + if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) { + *masked |= HAL_INT_TX; + + if (!p_cap->hal_isr_rac_support) { + u_int32_t s0, s1; + /* + * EV61133 (missing interrupts due to ISR_RAC): + * If not using ISR_RAC, clear interrupts by writing to + * ISR_S0/S1. + * This avoids a race condition where a new interrupt + * could come in between reading the ISR and clearing the + * interrupt via the primary ISR. We therefore clear the + * interrupt via the secondary, which avoids this race. + */ + s0 = OS_REG_READ(ah, AR_ISR_S0); + OS_REG_WRITE(ah, AR_ISR_S0, s0); + s1 = OS_REG_READ(ah, AR_ISR_S1); + OS_REG_WRITE(ah, AR_ISR_S1, s1); + + isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL); + } + } + + /* + * Do not treat receive overflows as fatal for owl. + */ + if (isr & AR_ISR_RXORN) { +#if __PKT_SERIOUS_ERRORS__ + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s: receive FIFO overrun interrupt\n", __func__); +#endif + } + +#if 0 + /* XXX Verify if this is fixed for Osprey */ + if (!p_cap->hal_auto_sleep_support) { + u_int32_t isr5 = OS_REG_READ(ah, AR_ISR_S5_S); + if (isr5 & AR_ISR_S5_TIM_TIMER) { + *masked |= HAL_INT_TIM_TIMER; + } + } +#endif + if (isr & AR_ISR_GENTMR) { + u_int32_t s5; + + if (p_cap->hal_isr_rac_support) { + /* Use secondary shadow registers if using ISR_RAC */ + s5 = OS_REG_READ(ah, AR_ISR_S5_S); + } else { + s5 = OS_REG_READ(ah, AR_ISR_S5); + } + if (isr & AR_ISR_GENTMR) { + + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s: GENTIMER, ISR_RAC=0x%x ISR_S2_S=0x%x\n", __func__, + isr, s5); + ahp->ah_intr_gen_timer_trigger = + MS(s5, AR_ISR_S5_GENTIMER_TRIG); + ahp->ah_intr_gen_timer_thresh = + MS(s5, AR_ISR_S5_GENTIMER_THRESH); + if (ahp->ah_intr_gen_timer_trigger) { + *masked |= HAL_INT_GENTIMER; + } + } + if (!p_cap->hal_isr_rac_support) { + /* + * EV61133 (missing interrupts due to ISR_RAC): + * If not using ISR_RAC, clear interrupts by writing to ISR_S5. + * This avoids a race condition where a new interrupt + * could come in between reading the ISR and clearing the + * interrupt via the primary ISR. We therefore clear the + * interrupt via the secondary, which avoids this race. + */ + OS_REG_WRITE(ah, AR_ISR_S5, s5); + isr &= ~AR_ISR_GENTMR; + } + } + + *masked |= mask2; + + if (!p_cap->hal_isr_rac_support) { + /* + * EV61133 (missing interrupts due to ISR_RAC): + * If not using ISR_RAC, clear the interrupts we've read by + * writing back ones in these locations to the primary ISR + * (except for interrupts that have a secondary isr register - + * see above). + */ + OS_REG_WRITE(ah, AR_ISR, isr); + + /* Flush prior write */ + (void) OS_REG_READ(ah, AR_ISR); + } + +#ifdef AH_SUPPORT_AR9300 + if (*masked & HAL_INT_BBPANIC) { + ar9300_handle_bb_panic(ah); + } +#endif + } + + if (async_cause) { + if (nortc) { + OS_REG_WRITE(ah, + AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR), async_cause); + /* Flush prior write */ + (void) OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR)); + } else { +#ifdef ATH_GPIO_USE_ASYNC_CAUSE + if (async_cause & AR_INTR_ASYNC_CAUSE_GPIO) { + ahp->ah_gpio_cause = (async_cause & AR_INTR_ASYNC_CAUSE_GPIO) >> + AR_INTR_ASYNC_ENABLE_GPIO_S; + *masked |= HAL_INT_GPIO; + } +#endif + } + +#if ATH_SUPPORT_MCI + if ((async_cause & AR_INTR_ASYNC_CAUSE_MCI) && + p_cap->hal_mci_support) + { + u_int32_t int_raw, int_rx_msg; + + int_rx_msg = OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); + int_raw = OS_REG_READ(ah, AR_MCI_INTERRUPT_RAW); + + if ((int_raw == 0xdeadbeef) || (int_rx_msg == 0xdeadbeef)) + { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Get 0xdeadbeef during MCI int processing" + "new int_raw=0x%08x, new rx_msg_raw=0x%08x, " + "int_raw=0x%08x, rx_msg_raw=0x%08x\n", + int_raw, int_rx_msg, ahp->ah_mci_int_raw, + ahp->ah_mci_int_rx_msg); + } + else { + if (ahp->ah_mci_int_raw || ahp->ah_mci_int_rx_msg) { + ahp->ah_mci_int_rx_msg |= int_rx_msg; + ahp->ah_mci_int_raw |= int_raw; + } + else { + ahp->ah_mci_int_rx_msg = int_rx_msg; + ahp->ah_mci_int_raw = int_raw; + } + + *masked |= HAL_INT_MCI; + ahp->ah_mci_rx_status = OS_REG_READ(ah, AR_MCI_RX_STATUS); + if (int_rx_msg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) { + ahp->ah_mci_cont_status = + OS_REG_READ(ah, AR_MCI_CONT_STATUS); + } + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, + int_rx_msg); + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, int_raw); + + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s:AR_INTR_SYNC_MCI\n", __func__); + } + } +#endif + } + + if (sync_cause) { + int host1_fatal, host1_perr, radm_cpl_timeout, local_timeout; + + host1_fatal = AR_SREV_WASP(ah) ? + AR9340_INTR_SYNC_HOST1_FATAL : AR9300_INTR_SYNC_HOST1_FATAL; + host1_perr = AR_SREV_WASP(ah) ? + AR9340_INTR_SYNC_HOST1_PERR : AR9300_INTR_SYNC_HOST1_PERR; + radm_cpl_timeout = AR_SREV_WASP(ah) ? + 0x0 : AR9300_INTR_SYNC_RADM_CPL_TIMEOUT; + local_timeout = AR_SREV_WASP(ah) ? + AR9340_INTR_SYNC_LOCAL_TIMEOUT : AR9300_INTR_SYNC_LOCAL_TIMEOUT; + + if (sync_cause & host1_fatal) { +#if __PKT_SERIOUS_ERRORS__ + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: received PCI FATAL interrupt\n", __func__); +#endif + *masked |= HAL_INT_FATAL; /* Set FATAL INT flag here;*/ + } + if (sync_cause & host1_perr) { +#if __PKT_SERIOUS_ERRORS__ + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: received PCI PERR interrupt\n", __func__); +#endif + } + + if (sync_cause & radm_cpl_timeout) { + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n", + __func__); + + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), 0); + *masked |= HAL_INT_FATAL; + } + if (sync_cause & local_timeout) { + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n", + __func__); + } + +#ifndef ATH_GPIO_USE_ASYNC_CAUSE + if (sync_cause & AR_INTR_SYNC_MASK_GPIO) { + ahp->ah_gpio_cause = (sync_cause & AR_INTR_SYNC_MASK_GPIO) >> + AR_INTR_SYNC_ENABLE_GPIO_S; + *masked |= HAL_INT_GPIO; + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s: AR_INTR_SYNC_GPIO\n", __func__); + } +#endif + + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR), sync_cause); + /* Flush prior write */ + (void) OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR)); + } + +end: + if (HAL_INT_MSI == type) { + /* + * WAR for Bug EV#75887 + * In normal case, SW read HOST_INTF_PCIE_MSI (0x40A4) and write + * into ah_msi_reg. Then use value of ah_msi_reg to set bit#25 + * when want to enable HW write the cfg_msi_pending. + * Sometimes, driver get MSI interrupt before read 0x40a4 and + * ah_msi_reg is initialization value (0x0). + * We don't know why "MSI interrupt earlier than driver read" now... + */ + if (!ahp->ah_msi_reg) { + ahp->ah_msi_reg = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_MSI)); + } + if (AR_SREV_POSEIDON(ah)) { + msi_pend_addr_mask = AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64; + } else { + msi_pend_addr_mask = AR_PCIE_MSI_HW_INT_PENDING_ADDR; + } + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_MSI), + ((ahp->ah_msi_reg | AR_PCIE_MSI_ENABLE) & msi_pend_addr_mask)); + + } + + return ret_val; +} + +HAL_INT +ar9300_get_interrupts(struct ath_hal *ah) +{ + return AH9300(ah)->ah_mask_reg; +} + +/* + * Atomically enables NIC interrupts. Interrupts are passed in + * via the enumerated bitmask in ints. + */ +HAL_INT +ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL nortc) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t omask = ahp->ah_mask_reg; + u_int32_t mask, mask2, msi_mask = 0; + u_int32_t msi_pend_addr_mask = 0; + u_int32_t sync_en_def = AR9300_INTR_SYNC_DEFAULT; + HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s: 0x%x => 0x%x\n", __func__, omask, ints); + + if (omask & HAL_INT_GLOBAL) { + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__); + + if (AH_PRIVATE(ah)->ah_config.ath_hal_enable_msi) { + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE), 0); + /* flush write to HW */ + (void)OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE)); + } + + if (!nortc) { + OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); + (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */ + } + + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE), 0); + /* flush write to HW */ + (void) OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE)); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE), 0); + /* flush write to HW */ + (void) OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE)); + } + + if (!nortc) { + /* reference count for global IER */ + if (ints & HAL_INT_GLOBAL) { +#ifdef AH_DEBUG + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s: Request HAL_INT_GLOBAL ENABLED\n", __func__); + if (OS_ATOMIC_READ(&ahp->ah_ier_ref_count) == 0) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: WARNING: ah_ier_ref_count is 0 " + "and attempting to enable IER\n", + __func__); + } +#endif + if (OS_ATOMIC_READ(&ahp->ah_ier_ref_count) > 0) { + OS_ATOMIC_DEC(&ahp->ah_ier_ref_count); + } + } else { + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s: Request HAL_INT_GLOBAL DISABLED\n", __func__); + OS_ATOMIC_INC(&ahp->ah_ier_ref_count); + } + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s: ah_ier_ref_count = %d\n", __func__, ahp->ah_ier_ref_count); + + mask = ints & HAL_INT_COMMON; + mask2 = 0; + msi_mask = 0; + + if (ints & HAL_INT_TX) { + if (ahp->ah_intr_mitigation_tx) { + mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM; + } else if (ahp->ah_tx_ok_interrupt_mask) { + mask |= AR_IMR_TXOK; + } + msi_mask |= AR_INTR_PRIO_TX; + if (ahp->ah_tx_err_interrupt_mask) { + mask |= AR_IMR_TXERR; + } + if (ahp->ah_tx_eol_interrupt_mask) { + mask |= AR_IMR_TXEOL; + } + } + if (ints & HAL_INT_RX) { + mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP; + if (ahp->ah_intr_mitigation_rx) { + mask &= ~(AR_IMR_RXOK_LP); + mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; + } else { + mask |= AR_IMR_RXOK_LP; + } + msi_mask |= AR_INTR_PRIO_RXLP | AR_INTR_PRIO_RXHP; + if (! p_cap->hal_auto_sleep_support) { + mask |= AR_IMR_GENTMR; + } + } + + if (ints & (HAL_INT_BMISC)) { + mask |= AR_IMR_BCNMISC; + if (ints & HAL_INT_TIM) { + mask2 |= AR_IMR_S2_TIM; + } + if (ints & HAL_INT_DTIM) { + mask2 |= AR_IMR_S2_DTIM; + } + if (ints & HAL_INT_DTIMSYNC) { + mask2 |= AR_IMR_S2_DTIMSYNC; + } + if (ints & HAL_INT_CABEND) { + mask2 |= (AR_IMR_S2_CABEND); + } + if (ints & HAL_INT_TSFOOR) { + mask2 |= AR_IMR_S2_TSFOOR; + } + } + + if (ints & (HAL_INT_GTT | HAL_INT_CST)) { + mask |= AR_IMR_BCNMISC; + if (ints & HAL_INT_GTT) { + mask2 |= AR_IMR_S2_GTT; + } + if (ints & HAL_INT_CST) { + mask2 |= AR_IMR_S2_CST; + } + } + + if (ints & HAL_INT_BBPANIC) { + /* EV92527 - MAC secondary interrupt must enable AR_IMR_BCNMISC */ + mask |= AR_IMR_BCNMISC; + mask2 |= AR_IMR_S2_BBPANIC; + } + + if (ints & HAL_INT_GENTIMER) { + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s: enabling gen timer\n", __func__); + mask |= AR_IMR_GENTMR; + } + + /* Write the new IMR and store off our SW copy. */ + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); + OS_REG_WRITE(ah, AR_IMR, mask); + ahp->ah_mask2Reg &= ~(AR_IMR_S2_TIM | + AR_IMR_S2_DTIM | + AR_IMR_S2_DTIMSYNC | + AR_IMR_S2_CABEND | + AR_IMR_S2_CABTO | + AR_IMR_S2_TSFOOR | + AR_IMR_S2_GTT | + AR_IMR_S2_CST | + AR_IMR_S2_BBPANIC); + ahp->ah_mask2Reg |= mask2; + OS_REG_WRITE(ah, AR_IMR_S2, ahp->ah_mask2Reg ); + ahp->ah_mask_reg = ints; + + if (! p_cap->hal_auto_sleep_support) { + if (ints & HAL_INT_TIM_TIMER) { + OS_REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); + } + else { + OS_REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); + } + } + } + + /* Re-enable interrupts if they were enabled before. */ +#if HAL_INTR_REFCOUNT_DISABLE + if ((ints & HAL_INT_GLOBAL)) { +#else + if ((ints & HAL_INT_GLOBAL) && (OS_ATOMIC_READ(&ahp->ah_ier_ref_count) == 0)) { +#endif + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); + + if (!nortc) { + OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); + } + + mask = AR_INTR_MAC_IRQ; +#ifdef ATH_GPIO_USE_ASYNC_CAUSE + if (ints & HAL_INT_GPIO) { + if (ahp->ah_gpio_mask) { + mask |= SM(ahp->ah_gpio_mask, AR_INTR_ASYNC_MASK_GPIO); + } + } +#endif + +#if ATH_SUPPORT_MCI + if (ints & HAL_INT_MCI) { + mask |= AR_INTR_ASYNC_MASK_MCI; + } +#endif + + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE), mask); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK), mask); + + if (AH_PRIVATE(ah)->ah_config.ath_hal_enable_msi) { + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE), + msi_mask); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK), + msi_mask); + if (AR_SREV_POSEIDON(ah)) { + msi_pend_addr_mask = AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64; + } else { + msi_pend_addr_mask = AR_PCIE_MSI_HW_INT_PENDING_ADDR; + } + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_MSI), + ((ahp->ah_msi_reg | AR_PCIE_MSI_ENABLE) & msi_pend_addr_mask)); + } + + /* + * debug - enable to see all synchronous interrupts status + * Enable synchronous GPIO interrupts as well, since some async + * GPIO interrupts don't wake the chip up. + */ + mask = 0; +#ifndef ATH_GPIO_USE_ASYNC_CAUSE + if (ints & HAL_INT_GPIO) { + mask |= SM(ahp->ah_gpio_mask, AR_INTR_SYNC_MASK_GPIO); + } +#endif + if (AR_SREV_POSEIDON(ah)) { + sync_en_def = AR9300_INTR_SYNC_DEF_NO_HOST1_PERR; + } + else if (AR_SREV_WASP(ah)) { + sync_en_def = AR9340_INTR_SYNC_DEFAULT; + } + + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE), + (sync_en_def | mask)); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK), + (sync_en_def | mask)); + + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "AR_IMR 0x%x IER 0x%x\n", + OS_REG_READ(ah, AR_IMR), OS_REG_READ(ah, AR_IER)); + } + + return omask; +} + +void +ar9300_set_intr_mitigation_timer( + struct ath_hal* ah, + HAL_INT_MITIGATION reg, + u_int32_t value) +{ +#ifdef AR5416_INT_MITIGATION + switch (reg) { + case HAL_INT_THRESHOLD: + OS_REG_WRITE(ah, AR_MIRT, 0); + break; + case HAL_INT_RX_LASTPKT: + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, value); + break; + case HAL_INT_RX_FIRSTPKT: + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, value); + break; + case HAL_INT_TX_LASTPKT: + OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, value); + break; + case HAL_INT_TX_FIRSTPKT: + OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, value); + break; + default: + break; + } +#endif +} + +u_int32_t +ar9300_get_intr_mitigation_timer(struct ath_hal* ah, HAL_INT_MITIGATION reg) +{ + u_int32_t val = 0; +#ifdef AR5416_INT_MITIGATION + switch (reg) { + case HAL_INT_THRESHOLD: + val = OS_REG_READ(ah, AR_MIRT); + break; + case HAL_INT_RX_LASTPKT: + val = OS_REG_READ(ah, AR_RIMT) & 0xFFFF; + break; + case HAL_INT_RX_FIRSTPKT: + val = OS_REG_READ(ah, AR_RIMT) >> 16; + break; + case HAL_INT_TX_LASTPKT: + val = OS_REG_READ(ah, AR_TIMT) & 0xFFFF; + break; + case HAL_INT_TX_FIRSTPKT: + val = OS_REG_READ(ah, AR_TIMT) >> 16; + break; + default: + break; + } +#endif + return val; +} + +#endif /* AH_SUPPORT_AR9300 */ + diff --git a/hal/ar9300/ar9300_jupiter10.ini b/hal/ar9300/ar9300_jupiter10.ini new file mode 100644 index 000000000000..24b9785ab52e --- /dev/null +++ b/hal/ar9300/ar9300_jupiter10.ini @@ -0,0 +1,1894 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +static const u_int32_t ar9300_jupiter_1p0_mac_core[][2] = { +/* Addr allmodes */ + { 0x00000008 , 0x00000000 }, + { 0x00000030 , 0x00060085 }, + { 0x00000034 , 0x00000005 }, + { 0x00000040 , 0x00000000 }, + { 0x00000044 , 0x00000000 }, + { 0x00000048 , 0x00000008 }, + { 0x0000004c , 0x00000010 }, + { 0x00000050 , 0x00000000 }, + { 0x00001040 , 0x002ffc0f }, + { 0x00001044 , 0x002ffc0f }, + { 0x00001048 , 0x002ffc0f }, + { 0x0000104c , 0x002ffc0f }, + { 0x00001050 , 0x002ffc0f }, + { 0x00001054 , 0x002ffc0f }, + { 0x00001058 , 0x002ffc0f }, + { 0x0000105c , 0x002ffc0f }, + { 0x00001060 , 0x002ffc0f }, + { 0x00001064 , 0x002ffc0f }, + { 0x000010f0 , 0x00000100 }, + { 0x00001270 , 0x00000000 }, + { 0x000012b0 , 0x00000000 }, + { 0x000012f0 , 0x00000000 }, + { 0x0000143c , 0x00000000 }, + { 0x0000147c , 0x00000000 }, + { 0x00001810 , 0x0f000003 }, + { 0x00008000 , 0x00000000 }, + { 0x00008004 , 0x00000000 }, + { 0x00008008 , 0x00000000 }, + { 0x0000800c , 0x00000000 }, + { 0x00008018 , 0x00000000 }, + { 0x00008020 , 0x00000000 }, + { 0x00008038 , 0x00000000 }, + { 0x0000803c , 0x00080000 }, + { 0x00008040 , 0x00000000 }, + { 0x00008044 , 0x00000000 }, + { 0x00008048 , 0x00000000 }, + { 0x0000804c , 0xffffffff }, + { 0x00008050 , 0xffffffff }, + { 0x00008054 , 0x00000000 }, + { 0x00008058 , 0x00000000 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008060 , 0x0000000f }, + { 0x00008064 , 0x00000000 }, + { 0x00008070 , 0x00000310 }, + { 0x00008074 , 0x00000020 }, + { 0x00008078 , 0x00000000 }, + { 0x0000809c , 0x0000000f }, + { 0x000080a0 , 0x00000000 }, + { 0x000080a4 , 0x02ff0000 }, + { 0x000080a8 , 0x0e070605 }, + { 0x000080ac , 0x0000000d }, + { 0x000080b0 , 0x00000000 }, + { 0x000080b4 , 0x00000000 }, + { 0x000080b8 , 0x00000000 }, + { 0x000080bc , 0x00000000 }, + { 0x000080c0 , 0x2a800000 }, + { 0x000080c4 , 0x06900168 }, + { 0x000080c8 , 0x13881c20 }, + { 0x000080cc , 0x01f40000 }, + { 0x000080d0 , 0x00252500 }, + { 0x000080d4 , 0x00a00005 }, + { 0x000080d8 , 0x00400002 }, + { 0x000080dc , 0x00000000 }, + { 0x000080e0 , 0xffffffff }, + { 0x000080e4 , 0x0000ffff }, + { 0x000080e8 , 0x3f3f3f3f }, + { 0x000080ec , 0x00000000 }, + { 0x000080f0 , 0x00000000 }, + { 0x000080f4 , 0x00000000 }, + { 0x000080fc , 0x00020000 }, + { 0x00008100 , 0x00000000 }, + { 0x00008108 , 0x00000052 }, + { 0x0000810c , 0x00000000 }, + { 0x00008110 , 0x00000000 }, + { 0x00008114 , 0x000007ff }, + { 0x00008118 , 0x000000aa }, + { 0x0000811c , 0x00003210 }, + { 0x00008124 , 0x00000000 }, + { 0x00008128 , 0x00000000 }, + { 0x0000812c , 0x00000000 }, + { 0x00008130 , 0x00000000 }, + { 0x00008134 , 0x00000000 }, + { 0x00008138 , 0x00000000 }, + { 0x0000813c , 0x0000ffff }, + { 0x00008144 , 0xffffffff }, + { 0x00008168 , 0x00000000 }, + { 0x0000816c , 0x00000000 }, + { 0x00008170 , 0x18486e00 }, + { 0x00008174 , 0x33332210 }, + { 0x00008178 , 0x00000000 }, + { 0x0000817c , 0x00020000 }, + { 0x000081c4 , 0x33332210 }, + { 0x000081c8 , 0x00000000 }, + { 0x000081cc , 0x00000000 }, + { 0x000081d4 , 0x00000000 }, + { 0x000081ec , 0x00000000 }, + { 0x000081f0 , 0x00000000 }, + { 0x000081f4 , 0x00000000 }, + { 0x000081f8 , 0x00000000 }, + { 0x000081fc , 0x00000000 }, + { 0x00008240 , 0x00100000 }, + { 0x00008244 , 0x0010f400 }, + { 0x00008248 , 0x00000800 }, + { 0x0000824c , 0x0001e800 }, + { 0x00008250 , 0x00000000 }, + { 0x00008254 , 0x00000000 }, + { 0x00008258 , 0x00000000 }, + { 0x0000825c , 0x40000000 }, + { 0x00008260 , 0x00080922 }, + { 0x00008264 , 0x99c00010 }, + { 0x00008268 , 0xffffffff }, + { 0x0000826c , 0x0000ffff }, + { 0x00008270 , 0x00000000 }, + { 0x00008274 , 0x40000000 }, + { 0x00008278 , 0x003e4180 }, + { 0x0000827c , 0x00000004 }, + { 0x00008284 , 0x0000002c }, + { 0x00008288 , 0x0000002c }, + { 0x0000828c , 0x000000ff }, + { 0x00008294 , 0x00000000 }, + { 0x00008298 , 0x00000000 }, + { 0x0000829c , 0x00000000 }, + { 0x00008300 , 0x00000140 }, + { 0x00008314 , 0x00000000 }, + { 0x0000831c , 0x0000010d }, + { 0x00008328 , 0x00000000 }, + { 0x0000832c , 0x0000001f }, + { 0x00008330 , 0x00000302 }, + { 0x00008334 , 0x00000700 }, + { 0x00008338 , 0xffff0000 }, + { 0x0000833c , 0x02400000 }, + { 0x00008340 , 0x000107ff }, + { 0x00008344 , 0xaa48105b }, + { 0x00008348 , 0x008f0000 }, + { 0x0000835c , 0x00000000 }, + { 0x00008360 , 0xffffffff }, + { 0x00008364 , 0xffffffff }, + { 0x00008368 , 0x00000000 }, + { 0x00008370 , 0x00000000 }, + { 0x00008374 , 0x000000ff }, + { 0x00008378 , 0x00000000 }, + { 0x0000837c , 0x00000000 }, + { 0x00008380 , 0xffffffff }, + { 0x00008384 , 0xffffffff }, + { 0x00008390 , 0xffffffff }, + { 0x00008394 , 0xffffffff }, + { 0x00008398 , 0x00000000 }, + { 0x0000839c , 0x00000000 }, + { 0x000083a4 , 0x0000fa14 }, + { 0x000083a8 , 0x000f0c00 }, + { 0x000083ac , 0x33332210 }, + { 0x000083b0 , 0x33332210 }, + { 0x000083b4 , 0x33332210 }, + { 0x000083b8 , 0x33332210 }, + { 0x000083bc , 0x00000000 }, + { 0x000083c0 , 0x00000000 }, + { 0x000083c4 , 0x00000000 }, + { 0x000083c8 , 0x00000000 }, + { 0x000083cc , 0x00000200 }, + { 0x000083d0 , 0x000301ff }, +}; + +static const u_int32_t ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { +/* Addr allmodes */ + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x6f7f0301 }, + { 0x0000a3a0 , 0xca9228ee }, +}; + +static const u_int32_t ar9300_jupiter_1p0_sys3ant[][2] = { +/* Addr allmodes */ + { 0x00063280 , 0x00040807 }, + { 0x00063284 , 0x104ccccc }, +}; + +static const u_int32_t ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x10053e5e }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0000580c }, +}; + +static const u_int32_t ar9300_jupiter_1p0_mac_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00000030 , 0x00060085 }, + { 0x00000044 , 0x00000008 }, + { 0x0000805c , 0xffffc7ff }, + { 0x00008344 , 0xaa4a105b }, +}; + +static const u_int32_t ar9300Common_rx_gain_table_merlin_2p0_jupiter_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x02000101 }, + { 0x0000a004 , 0x02000102 }, + { 0x0000a008 , 0x02000103 }, + { 0x0000a00c , 0x02000104 }, + { 0x0000a010 , 0x02000200 }, + { 0x0000a014 , 0x02000201 }, + { 0x0000a018 , 0x02000202 }, + { 0x0000a01c , 0x02000203 }, + { 0x0000a020 , 0x02000204 }, + { 0x0000a024 , 0x02000205 }, + { 0x0000a028 , 0x02000208 }, + { 0x0000a02c , 0x02000302 }, + { 0x0000a030 , 0x02000303 }, + { 0x0000a034 , 0x02000304 }, + { 0x0000a038 , 0x02000400 }, + { 0x0000a03c , 0x02010300 }, + { 0x0000a040 , 0x02010301 }, + { 0x0000a044 , 0x02010302 }, + { 0x0000a048 , 0x02000500 }, + { 0x0000a04c , 0x02010400 }, + { 0x0000a050 , 0x02020300 }, + { 0x0000a054 , 0x02020301 }, + { 0x0000a058 , 0x02020302 }, + { 0x0000a05c , 0x02020303 }, + { 0x0000a060 , 0x02020400 }, + { 0x0000a064 , 0x02030300 }, + { 0x0000a068 , 0x02030301 }, + { 0x0000a06c , 0x02030302 }, + { 0x0000a070 , 0x02030303 }, + { 0x0000a074 , 0x02030400 }, + { 0x0000a078 , 0x02040300 }, + { 0x0000a07c , 0x02040301 }, + { 0x0000a080 , 0x02040302 }, + { 0x0000a084 , 0x02040303 }, + { 0x0000a088 , 0x02030500 }, + { 0x0000a08c , 0x02040400 }, + { 0x0000a090 , 0x02050203 }, + { 0x0000a094 , 0x02050204 }, + { 0x0000a098 , 0x02050205 }, + { 0x0000a09c , 0x02040500 }, + { 0x0000a0a0 , 0x02050301 }, + { 0x0000a0a4 , 0x02050302 }, + { 0x0000a0a8 , 0x02050303 }, + { 0x0000a0ac , 0x02050400 }, + { 0x0000a0b0 , 0x02050401 }, + { 0x0000a0b4 , 0x02050402 }, + { 0x0000a0b8 , 0x02050403 }, + { 0x0000a0bc , 0x02050500 }, + { 0x0000a0c0 , 0x02050501 }, + { 0x0000a0c4 , 0x02050502 }, + { 0x0000a0c8 , 0x02050503 }, + { 0x0000a0cc , 0x02050504 }, + { 0x0000a0d0 , 0x02050600 }, + { 0x0000a0d4 , 0x02050601 }, + { 0x0000a0d8 , 0x02050602 }, + { 0x0000a0dc , 0x02050603 }, + { 0x0000a0e0 , 0x02050604 }, + { 0x0000a0e4 , 0x02050700 }, + { 0x0000a0e8 , 0x02050701 }, + { 0x0000a0ec , 0x02050702 }, + { 0x0000a0f0 , 0x02050703 }, + { 0x0000a0f4 , 0x02050704 }, + { 0x0000a0f8 , 0x02050705 }, + { 0x0000a0fc , 0x02050708 }, + { 0x0000a100 , 0x02050709 }, + { 0x0000a104 , 0x0205070a }, + { 0x0000a108 , 0x0205070b }, + { 0x0000a10c , 0x0205070c }, + { 0x0000a110 , 0x0205070d }, + { 0x0000a114 , 0x02050710 }, + { 0x0000a118 , 0x02050711 }, + { 0x0000a11c , 0x02050712 }, + { 0x0000a120 , 0x02050713 }, + { 0x0000a124 , 0x02050714 }, + { 0x0000a128 , 0x02050715 }, + { 0x0000a12c , 0x02050730 }, + { 0x0000a130 , 0x02050731 }, + { 0x0000a134 , 0x02050732 }, + { 0x0000a138 , 0x02050733 }, + { 0x0000a13c , 0x02050734 }, + { 0x0000a140 , 0x02050735 }, + { 0x0000a144 , 0x02050750 }, + { 0x0000a148 , 0x02050751 }, + { 0x0000a14c , 0x02050752 }, + { 0x0000a150 , 0x02050753 }, + { 0x0000a154 , 0x02050754 }, + { 0x0000a158 , 0x02050755 }, + { 0x0000a15c , 0x02050770 }, + { 0x0000a160 , 0x02050771 }, + { 0x0000a164 , 0x02050772 }, + { 0x0000a168 , 0x02050773 }, + { 0x0000a16c , 0x02050774 }, + { 0x0000a170 , 0x02050775 }, + { 0x0000a174 , 0x00000776 }, + { 0x0000a178 , 0x00000776 }, + { 0x0000a17c , 0x00000776 }, + { 0x0000a180 , 0x00000776 }, + { 0x0000a184 , 0x00000776 }, + { 0x0000a188 , 0x00000776 }, + { 0x0000a18c , 0x00000776 }, + { 0x0000a190 , 0x00000776 }, + { 0x0000a194 , 0x00000776 }, + { 0x0000a198 , 0x00000776 }, + { 0x0000a19c , 0x00000776 }, + { 0x0000a1a0 , 0x00000776 }, + { 0x0000a1a4 , 0x00000776 }, + { 0x0000a1a8 , 0x00000776 }, + { 0x0000a1ac , 0x00000776 }, + { 0x0000a1b0 , 0x00000776 }, + { 0x0000a1b4 , 0x00000776 }, + { 0x0000a1b8 , 0x00000776 }, + { 0x0000a1bc , 0x00000776 }, + { 0x0000a1c0 , 0x00000776 }, + { 0x0000a1c4 , 0x00000776 }, + { 0x0000a1c8 , 0x00000776 }, + { 0x0000a1cc , 0x00000776 }, + { 0x0000a1d0 , 0x00000776 }, + { 0x0000a1d4 , 0x00000776 }, + { 0x0000a1d8 , 0x00000776 }, + { 0x0000a1dc , 0x00000776 }, + { 0x0000a1e0 , 0x00000776 }, + { 0x0000a1e4 , 0x00000776 }, + { 0x0000a1e8 , 0x00000776 }, + { 0x0000a1ec , 0x00000776 }, + { 0x0000a1f0 , 0x00000776 }, + { 0x0000a1f4 , 0x00000776 }, + { 0x0000a1f8 , 0x00000776 }, + { 0x0000a1fc , 0x00000776 }, + { 0x0000b000 , 0x02000101 }, + { 0x0000b004 , 0x02000102 }, + { 0x0000b008 , 0x02000103 }, + { 0x0000b00c , 0x02000104 }, + { 0x0000b010 , 0x02000200 }, + { 0x0000b014 , 0x02000201 }, + { 0x0000b018 , 0x02000202 }, + { 0x0000b01c , 0x02000203 }, + { 0x0000b020 , 0x02000204 }, + { 0x0000b024 , 0x02000205 }, + { 0x0000b028 , 0x02000208 }, + { 0x0000b02c , 0x02000302 }, + { 0x0000b030 , 0x02000303 }, + { 0x0000b034 , 0x02000304 }, + { 0x0000b038 , 0x02000400 }, + { 0x0000b03c , 0x02010300 }, + { 0x0000b040 , 0x02010301 }, + { 0x0000b044 , 0x02010302 }, + { 0x0000b048 , 0x02000500 }, + { 0x0000b04c , 0x02010400 }, + { 0x0000b050 , 0x02020300 }, + { 0x0000b054 , 0x02020301 }, + { 0x0000b058 , 0x02020302 }, + { 0x0000b05c , 0x02020303 }, + { 0x0000b060 , 0x02020400 }, + { 0x0000b064 , 0x02030300 }, + { 0x0000b068 , 0x02030301 }, + { 0x0000b06c , 0x02030302 }, + { 0x0000b070 , 0x02030303 }, + { 0x0000b074 , 0x02030400 }, + { 0x0000b078 , 0x02040300 }, + { 0x0000b07c , 0x02040301 }, + { 0x0000b080 , 0x02040302 }, + { 0x0000b084 , 0x02040303 }, + { 0x0000b088 , 0x02030500 }, + { 0x0000b08c , 0x02040400 }, + { 0x0000b090 , 0x02050203 }, + { 0x0000b094 , 0x02050204 }, + { 0x0000b098 , 0x02050205 }, + { 0x0000b09c , 0x02040500 }, + { 0x0000b0a0 , 0x02050301 }, + { 0x0000b0a4 , 0x02050302 }, + { 0x0000b0a8 , 0x02050303 }, + { 0x0000b0ac , 0x02050400 }, + { 0x0000b0b0 , 0x02050401 }, + { 0x0000b0b4 , 0x02050402 }, + { 0x0000b0b8 , 0x02050403 }, + { 0x0000b0bc , 0x02050500 }, + { 0x0000b0c0 , 0x02050501 }, + { 0x0000b0c4 , 0x02050502 }, + { 0x0000b0c8 , 0x02050503 }, + { 0x0000b0cc , 0x02050504 }, + { 0x0000b0d0 , 0x02050600 }, + { 0x0000b0d4 , 0x02050601 }, + { 0x0000b0d8 , 0x02050602 }, + { 0x0000b0dc , 0x02050603 }, + { 0x0000b0e0 , 0x02050604 }, + { 0x0000b0e4 , 0x02050700 }, + { 0x0000b0e8 , 0x02050701 }, + { 0x0000b0ec , 0x02050702 }, + { 0x0000b0f0 , 0x02050703 }, + { 0x0000b0f4 , 0x02050704 }, + { 0x0000b0f8 , 0x02050705 }, + { 0x0000b0fc , 0x02050708 }, + { 0x0000b100 , 0x02050709 }, + { 0x0000b104 , 0x0205070a }, + { 0x0000b108 , 0x0205070b }, + { 0x0000b10c , 0x0205070c }, + { 0x0000b110 , 0x0205070d }, + { 0x0000b114 , 0x02050710 }, + { 0x0000b118 , 0x02050711 }, + { 0x0000b11c , 0x02050712 }, + { 0x0000b120 , 0x02050713 }, + { 0x0000b124 , 0x02050714 }, + { 0x0000b128 , 0x02050715 }, + { 0x0000b12c , 0x02050730 }, + { 0x0000b130 , 0x02050731 }, + { 0x0000b134 , 0x02050732 }, + { 0x0000b138 , 0x02050733 }, + { 0x0000b13c , 0x02050734 }, + { 0x0000b140 , 0x02050735 }, + { 0x0000b144 , 0x02050750 }, + { 0x0000b148 , 0x02050751 }, + { 0x0000b14c , 0x02050752 }, + { 0x0000b150 , 0x02050753 }, + { 0x0000b154 , 0x02050754 }, + { 0x0000b158 , 0x02050755 }, + { 0x0000b15c , 0x02050770 }, + { 0x0000b160 , 0x02050771 }, + { 0x0000b164 , 0x02050772 }, + { 0x0000b168 , 0x02050773 }, + { 0x0000b16c , 0x02050774 }, + { 0x0000b170 , 0x02050775 }, + { 0x0000b174 , 0x00000776 }, + { 0x0000b178 , 0x00000776 }, + { 0x0000b17c , 0x00000776 }, + { 0x0000b180 , 0x00000776 }, + { 0x0000b184 , 0x00000776 }, + { 0x0000b188 , 0x00000776 }, + { 0x0000b18c , 0x00000776 }, + { 0x0000b190 , 0x00000776 }, + { 0x0000b194 , 0x00000776 }, + { 0x0000b198 , 0x00000776 }, + { 0x0000b19c , 0x00000776 }, + { 0x0000b1a0 , 0x00000776 }, + { 0x0000b1a4 , 0x00000776 }, + { 0x0000b1a8 , 0x00000776 }, + { 0x0000b1ac , 0x00000776 }, + { 0x0000b1b0 , 0x00000776 }, + { 0x0000b1b4 , 0x00000776 }, + { 0x0000b1b8 , 0x00000776 }, + { 0x0000b1bc , 0x00000776 }, + { 0x0000b1c0 , 0x00000776 }, + { 0x0000b1c4 , 0x00000776 }, + { 0x0000b1c8 , 0x00000776 }, + { 0x0000b1cc , 0x00000776 }, + { 0x0000b1d0 , 0x00000776 }, + { 0x0000b1d4 , 0x00000776 }, + { 0x0000b1d8 , 0x00000776 }, + { 0x0000b1dc , 0x00000776 }, + { 0x0000b1e0 , 0x00000776 }, + { 0x0000b1e4 , 0x00000776 }, + { 0x0000b1e8 , 0x00000776 }, + { 0x0000b1ec , 0x00000776 }, + { 0x0000b1f0 , 0x00000776 }, + { 0x0000b1f4 , 0x00000776 }, + { 0x0000b1f8 , 0x00000776 }, + { 0x0000b1fc , 0x00000776 }, +}; + +static const u_int32_t ar9200_merlin_2p0_radio_core_jupiter_1p0[][2] = { +/* Addr common */ + { 0x00007800 , 0x00040000 }, + { 0x00007804 , 0xdb005012 }, + { 0x00007808 , 0x04924914 }, + { 0x0000780c , 0x21084210 }, + { 0x00007810 , 0x6d801300 }, + { 0x00007814 , 0x0019beff }, + { 0x00007818 , 0x07e41000 }, + { 0x0000781c , 0x00392000 }, + { 0x00007820 , 0x92592480 }, + { 0x00007824 , 0x00040000 }, + { 0x00007828 , 0xdb005012 }, + { 0x0000782c , 0x04924914 }, + { 0x00007830 , 0x21084210 }, + { 0x00007834 , 0x6d801300 }, + { 0x00007838 , 0x0019beff }, + { 0x0000783c , 0x07e40000 }, + { 0x00007840 , 0x00392000 }, + { 0x00007844 , 0x92592480 }, + { 0x00007848 , 0x00100000 }, + { 0x0000784c , 0x773f0567 }, + { 0x00007850 , 0x54214514 }, + { 0x00007854 , 0x12035828 }, + { 0x00007858 , 0x92592692 }, + { 0x0000785c , 0x00000000 }, + { 0x00007860 , 0x56400000 }, + { 0x00007864 , 0x0a8e370e }, + { 0x00007868 , 0xc0102850 }, + { 0x0000786c , 0x812d4000 }, + { 0x00007870 , 0x807ec400 }, + { 0x00007874 , 0x001b6db0 }, + { 0x00007878 , 0x00376b63 }, + { 0x0000787c , 0x06db6db6 }, + { 0x00007880 , 0x006d8000 }, + { 0x00007884 , 0xffeffffe }, + { 0x00007888 , 0xffeffffe }, + { 0x0000788c , 0x00010000 }, + { 0x00007890 , 0x02060aeb }, + { 0x00007894 , 0x5a108000 }, +}; + +static const u_int32_t ar9300_jupiter_1p0_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e3c , 0xcf946221 , 0xcf946221 , 0xcf946221 , 0xcf946221 }, + { 0x00009e44 , 0x005c0000 , 0x005c0000 , 0x005c0000 , 0x005c0000 }, + { 0x0000a258 , 0x02020200 , 0x02020200 , 0x02020200 , 0x02020200 }, + { 0x0000a25c , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a28c , 0x00011111 , 0x00011111 , 0x00011111 , 0x00011111 }, + { 0x0000a2c4 , 0x00148d18 , 0x00148d18 , 0x00148d20 , 0x00148d20 }, + { 0x0000a2d8 , 0xf999a800 , 0xf999a800 , 0xf999a80c , 0xf999a80c }, + { 0x0000a50c , 0x0000c00a , 0x0000c00a , 0x0000c00a , 0x0000c00a }, + { 0x0000a538 , 0x00038e8c , 0x00038e8c , 0x00038e8c , 0x00038e8c }, + { 0x0000a53c , 0x0003cecc , 0x0003cecc , 0x0003cecc , 0x0003cecc }, + { 0x0000a540 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 }, + { 0x0000a544 , 0x00044edc , 0x00044edc , 0x00044edc , 0x00044edc }, + { 0x0000a548 , 0x00048ede , 0x00048ede , 0x00048ede , 0x00048ede }, + { 0x0000a54c , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e }, + { 0x0000a550 , 0x00050f5e , 0x00050f5e , 0x00050f5e , 0x00050f5e }, + { 0x0000a554 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +}; + +static const u_int32_t ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x10012e5e }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0000580c }, +}; + +static const u_int32_t ar9300_common_rx_gain_table_jupiter_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x01910190 }, + { 0x0000a030 , 0x01930192 }, + { 0x0000a034 , 0x01950194 }, + { 0x0000a038 , 0x038a0196 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x22222229 }, + { 0x0000a084 , 0x1d1d1d1d }, + { 0x0000a088 , 0x1d1d1d1d }, + { 0x0000a08c , 0x1d1d1d1d }, + { 0x0000a090 , 0x171d1d1d }, + { 0x0000a094 , 0x11111717 }, + { 0x0000a098 , 0x00030311 }, + { 0x0000a09c , 0x00000000 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x2a2d2f32 }, + { 0x0000b084 , 0x21232328 }, + { 0x0000b088 , 0x19191c1e }, + { 0x0000b08c , 0x12141417 }, + { 0x0000b090 , 0x07070e0e }, + { 0x0000b094 , 0x03030305 }, + { 0x0000b098 , 0x00000003 }, + { 0x0000b09c , 0x00000000 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06002223 , 0x06002223 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a022220 , 0x0a022220 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x0f022223 , 0x0f022223 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x14022620 , 0x14022620 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x18022622 , 0x18022622 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x1b022822 , 0x1b022822 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x20022842 , 0x20022842 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x22022c41 , 0x22022c41 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x28023042 , 0x28023042 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x2c023044 , 0x2c023044 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x2f023644 , 0x2f023644 , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x34025643 , 0x34025643 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x38025a44 , 0x38025a44 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x3b025e45 , 0x3b025e45 , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x41025e4a , 0x41025e4a , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x48025e6c , 0x48025e6c , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x4e025e8e , 0x4e025e8e , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x53025eb2 , 0x53025eb2 , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x59025eb2 , 0x59025eb2 , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x5f025ef6 , 0x5f025ef6 , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x62025f56 , 0x62025f56 , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x66027f56 , 0x66027f56 , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x6a029f56 , 0x6a029f56 , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x70049f56 , 0x70049f56 , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00804000 , 0x00804000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x00804201 , 0x00804201 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x0280c802 , 0x0280c802 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x0280ca03 , 0x0280ca03 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x04c15104 , 0x04c15104 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04c15305 , 0x04c15305 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04c15305 , 0x04c15305 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 }, + { 0x00016048 , 0x8db49060 , 0x8db49060 , 0x8db49060 , 0x8db49060 }, + { 0x00016444 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 }, + { 0x00016448 , 0x8db49000 , 0x8db49000 , 0x8db49000 , 0x8db49000 }, +}; + +static const u_int32_t ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x03820190 }, + { 0x0000a030 , 0x03840383 }, + { 0x0000a034 , 0x03880385 }, + { 0x0000a038 , 0x038a0389 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x29292929 }, + { 0x0000a084 , 0x29292929 }, + { 0x0000a088 , 0x29292929 }, + { 0x0000a08c , 0x29292929 }, + { 0x0000a090 , 0x22292929 }, + { 0x0000a094 , 0x1d1d2222 }, + { 0x0000a098 , 0x0c111117 }, + { 0x0000a09c , 0x00030303 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x32323232 }, + { 0x0000b084 , 0x2f2f3232 }, + { 0x0000b088 , 0x23282a2d }, + { 0x0000b08c , 0x1c1e2123 }, + { 0x0000b090 , 0x14171919 }, + { 0x0000b094 , 0x0e0e1214 }, + { 0x0000b098 , 0x03050707 }, + { 0x0000b09c , 0x00030303 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar9300_jupiter_1p0_mac_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, +}; + +static const u_int32_t ar9300_jupiter_1p0_mac_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 }, + { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 }, +}; + +static const u_int32_t ar9300_jupiter_1p0_tx_gain_table_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000000d5 , 0x000000d5 , 0x000000d5 , 0x000000d5 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x00004002 , 0x00004002 , 0x00004002 , 0x00004002 }, + { 0x0000a508 , 0x00008004 , 0x00008004 , 0x00008004 , 0x00008004 }, + { 0x0000a510 , 0x0001000c , 0x0001000c , 0x0001000c , 0x0001000c }, + { 0x0000a514 , 0x0001420b , 0x0001420b , 0x0001420b , 0x0001420b }, + { 0x0000a518 , 0x0001824a , 0x0001824a , 0x0001824a , 0x0001824a }, + { 0x0000a51c , 0x0001c44a , 0x0001c44a , 0x0001c44a , 0x0001c44a }, + { 0x0000a520 , 0x0002064a , 0x0002064a , 0x0002064a , 0x0002064a }, + { 0x0000a524 , 0x0002484a , 0x0002484a , 0x0002484a , 0x0002484a }, + { 0x0000a528 , 0x00028a4a , 0x00028a4a , 0x00028a4a , 0x00028a4a }, + { 0x0000a52c , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a }, + { 0x0000a530 , 0x00030e4a , 0x00030e4a , 0x00030e4a , 0x00030e4a }, + { 0x0000a534 , 0x00034e8a , 0x00034e8a , 0x00034e8a , 0x00034e8a }, +}; + +static const u_int32_t ar9300_jupiter_1p0_radio_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0001609c , 0x0b8ee524 , 0x0b8ee524 , 0x0b8ee524 , 0x0b8ee524 }, + { 0x000160ac , 0xa4646c08 , 0xa4646c08 , 0x24646c08 , 0x24646c08 }, + { 0x000160b0 , 0x01d67f70 , 0x01d67f70 , 0x01d67f70 , 0x01d67f70 }, + { 0x0001610c , 0x48000000 , 0x40000000 , 0x40000000 , 0x40000000 }, + { 0x00016140 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, + { 0x0001650c , 0x48000000 , 0x40000000 , 0x40000000 , 0x40000000 }, + { 0x00016540 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, +}; + +static const u_int32_t ar9300_jupiter_1p0_soc_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00007010 , 0x00001133 , 0x00001133 , 0x00001133 , 0x00001133 }, +}; + +static const u_int32_t ar9300_jupiter_1p0_baseband_core[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009804 , 0xfd14e000 }, + { 0x00009808 , 0x9c0a9f6b }, + { 0x0000980c , 0x04900000 }, + { 0x00009814 , 0x9280c00a }, + { 0x00009818 , 0x00000000 }, + { 0x0000981c , 0x00020028 }, + { 0x00009834 , 0x6400a290 }, + { 0x00009838 , 0x0108ecff }, + { 0x0000983c , 0x0d000600 }, + { 0x00009880 , 0x201fff00 }, + { 0x00009884 , 0x00001042 }, + { 0x000098a4 , 0x00200400 }, + { 0x000098b0 , 0x32840bbe }, + { 0x000098d0 , 0x004b6a8e }, + { 0x000098d4 , 0x00000820 }, + { 0x000098dc , 0x00000000 }, + { 0x000098e4 , 0x01ffffff }, + { 0x000098e8 , 0x01ffffff }, + { 0x000098ec , 0x01ffffff }, + { 0x000098f0 , 0x00000000 }, + { 0x000098f4 , 0x00000000 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009c0c , 0x00000000 }, + { 0x00009c10 , 0x00000000 }, + { 0x00009c14 , 0x00046384 }, + { 0x00009c18 , 0x05b6b440 }, + { 0x00009c1c , 0x00b6b440 }, + { 0x00009d00 , 0xc080a333 }, + { 0x00009d04 , 0x40206c10 }, + { 0x00009d08 , 0x009c4060 }, + { 0x00009d0c , 0x9883800a }, + { 0x00009d10 , 0x01834061 }, + { 0x00009d14 , 0x00c0040b }, + { 0x00009d18 , 0x00000000 }, + { 0x00009e08 , 0x0038230c }, + { 0x00009e24 , 0x990bb514 }, + { 0x00009e28 , 0x0c6f0000 }, + { 0x00009e30 , 0x06336f77 }, + { 0x00009e34 , 0x6af6532f }, + { 0x00009e38 , 0x0cc80c00 }, + { 0x00009e40 , 0x0d261820 }, + { 0x00009e4c , 0x00001004 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009e54 , 0x64c355c7 }, + { 0x00009e58 , 0xfd897735 }, + { 0x00009e5c , 0xe9198724 }, + { 0x00009fc0 , 0x803e4788 }, + { 0x00009fc4 , 0x0001efb5 }, + { 0x00009fcc , 0x40000014 }, + { 0x00009fd0 , 0x01193b93 }, + { 0x0000a20c , 0x00000000 }, + { 0x0000a220 , 0x00000000 }, + { 0x0000a224 , 0x00000000 }, + { 0x0000a228 , 0x10002310 }, + { 0x0000a23c , 0x00000000 }, + { 0x0000a244 , 0x0c000000 }, + { 0x0000a2a0 , 0x00000001 }, + { 0x0000a2c0 , 0x00000001 }, + { 0x0000a2c8 , 0x00000000 }, + { 0x0000a2cc , 0x18c43433 }, + { 0x0000a2d4 , 0x00000000 }, + { 0x0000a2ec , 0x00000000 }, + { 0x0000a2f0 , 0x00000000 }, + { 0x0000a2f4 , 0x00000000 }, + { 0x0000a2f8 , 0x00000000 }, + { 0x0000a344 , 0x00000000 }, + { 0x0000a34c , 0x00000000 }, + { 0x0000a350 , 0x0000a000 }, + { 0x0000a364 , 0x00000000 }, + { 0x0000a370 , 0x00000000 }, + { 0x0000a390 , 0x00000001 }, + { 0x0000a394 , 0x00000444 }, + { 0x0000a398 , 0x001f0e0f }, + { 0x0000a39c , 0x0075393f }, + { 0x0000a3a0 , 0xb79f6427 }, + { 0x0000a3a4 , 0x00000000 }, + { 0x0000a3a8 , 0xaaaaaaaa }, + { 0x0000a3ac , 0x3c466478 }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a3c8 , 0x20200020 }, + { 0x0000a3cc , 0x20202020 }, + { 0x0000a3d0 , 0x20202020 }, + { 0x0000a3d4 , 0x20202020 }, + { 0x0000a3d8 , 0x20202020 }, + { 0x0000a3dc , 0x20202020 }, + { 0x0000a3e0 , 0x20202020 }, + { 0x0000a3e4 , 0x20202020 }, + { 0x0000a3e8 , 0x20202020 }, + { 0x0000a3ec , 0x20202020 }, + { 0x0000a3f0 , 0x00000000 }, + { 0x0000a3f4 , 0x00000006 }, + { 0x0000a3f8 , 0x0c9bd380 }, + { 0x0000a3fc , 0x000f0f01 }, + { 0x0000a400 , 0x8fa91f01 }, + { 0x0000a404 , 0x00000000 }, + { 0x0000a408 , 0x0e79e5c6 }, + { 0x0000a40c , 0x00820820 }, + { 0x0000a414 , 0x1ce739ce }, + { 0x0000a418 , 0x2d001dce }, + { 0x0000a41c , 0x1ce739ce }, + { 0x0000a420 , 0x000001ce }, + { 0x0000a424 , 0x1ce739ce }, + { 0x0000a428 , 0x000001ce }, + { 0x0000a42c , 0x1ce739ce }, + { 0x0000a430 , 0x1ce739ce }, + { 0x0000a434 , 0x00000000 }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a43c , 0x00100000 }, + { 0x0000a440 , 0x00000000 }, + { 0x0000a444 , 0x00000000 }, + { 0x0000a448 , 0x05000080 }, + { 0x0000a44c , 0x00000001 }, + { 0x0000a450 , 0x00010000 }, + { 0x0000a458 , 0x00000000 }, + { 0x0000a644 , 0xbfad9d74 }, + { 0x0000a648 , 0x0048060a }, + { 0x0000a64c , 0x00003c37 }, + { 0x0000a670 , 0x03020100 }, + { 0x0000a674 , 0x09080504 }, + { 0x0000a678 , 0x0d0c0b0a }, + { 0x0000a67c , 0x13121110 }, + { 0x0000a680 , 0x31301514 }, + { 0x0000a684 , 0x35343332 }, + { 0x0000a688 , 0x00000036 }, + { 0x0000a690 , 0x00000838 }, + { 0x0000a6b0 , 0x0000000a }, + { 0x0000a6b4 , 0x28f12c01 }, + { 0x0000a7c0 , 0x00000000 }, + { 0x0000a7c4 , 0xfffffffc }, + { 0x0000a7c8 , 0x00000000 }, + { 0x0000a7cc , 0x00000000 }, + { 0x0000a7d0 , 0x00000000 }, + { 0x0000a7d4 , 0x00000004 }, + { 0x0000a7dc , 0x00000001 }, + { 0x0000a8d0 , 0x004b6a8e }, + { 0x0000a8d4 , 0x00000820 }, + { 0x0000a8dc , 0x00000000 }, + { 0x0000a8f0 , 0x00000000 }, + { 0x0000a8f4 , 0x00000000 }, + { 0x0000b2d0 , 0x00000080 }, + { 0x0000b2d4 , 0x00000000 }, + { 0x0000b2ec , 0x00000000 }, + { 0x0000b2f0 , 0x00000000 }, + { 0x0000b2f4 , 0x00000000 }, + { 0x0000b2f8 , 0x00000000 }, + { 0x0000b408 , 0x0e79e5c0 }, + { 0x0000b40c , 0x00820820 }, + { 0x0000b420 , 0x00000000 }, + { 0x0000b6b0 , 0x0000000a }, + { 0x0000b6b4 , 0x00c00001 }, +}; + +static const u_int32_t ar9300_jupiter_1p0_baseband_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8011 , 0xd00a8011 }, + { 0x00009820 , 0x206a022e , 0x206a022e , 0x206a012e , 0x206a012e }, + { 0x00009824 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 }, + { 0x00009828 , 0x06903081 , 0x06903081 , 0x06903881 , 0x06903881 }, + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000119c , 0x0000119c }, + { 0x00009c00 , 0x000000c4 , 0x000000c4 , 0x000000c4 , 0x000000c4 }, + { 0x00009e00 , 0x0372111a , 0x0372111a , 0x037216a0 , 0x037216a0 }, + { 0x00009e04 , 0x001c2020 , 0x001c2020 , 0x001c2020 , 0x001c2020 }, + { 0x00009e0c , 0x6c4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + { 0x00009e10 , 0x7ec88d2e , 0x7ec88d2e , 0x7ec84d2e , 0x7ec84d2e }, + { 0x00009e14 , 0x37b95d5e , 0x37b9605e , 0x3379605e , 0x33795d5e }, + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + { 0x00009e2c , 0x0000001c , 0x0000001c , 0x00000021 , 0x00000021 }, + { 0x00009e3c , 0xcf946220 , 0xcf946220 , 0xcfd5c782 , 0xcfd5c782 }, + { 0x00009e44 , 0x02321e27 , 0x02321e27 , 0x02291e27 , 0x02291e27 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302012 , 0x50302012 }, + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, + { 0x0000a204 , 0x0131b7c0 , 0x0131b7c4 , 0x0131b7c4 , 0x0131b7c0 }, + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + { 0x0000a22c , 0x01026a2f , 0x01026a27 , 0x01026a2f , 0x01026a2f }, + { 0x0000a230 , 0x0000400a , 0x00004014 , 0x00004016 , 0x0000400b }, + { 0x0000a234 , 0x00000fff , 0x10000fff , 0x10000fff , 0x00000fff }, + { 0x0000a238 , 0xffb81018 , 0xffb81018 , 0xffb81018 , 0xffb81018 }, + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a260 , 0x0a021501 , 0x0a021501 , 0x3a021501 , 0x3a021501 }, + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, + { 0x0000a288 , 0x00000110 , 0x00000110 , 0x00100110 , 0x00100110 }, + { 0x0000a28c , 0x00022222 , 0x00022222 , 0x00022222 , 0x00022222 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2d0 , 0x00041981 , 0x00041981 , 0x00041981 , 0x00041982 }, + { 0x0000a2d8 , 0x7999a83b , 0x7999a83b , 0x7999a83b , 0x7999a83b }, + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a830 , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae04 , 0x001c0000 , 0x001c0000 , 0x001c0000 , 0x00100000 }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000ae1c , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae20 , 0x000001b5 , 0x000001b5 , 0x000001ce , 0x000001ce }, + { 0x0000b284 , 0x00000000 , 0x00000000 , 0x00000550 , 0x00000550 }, +}; + +static const u_int32_t ar9300_modes_fast_clock_jupiter_1p0[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00001030 , 0x00000268 , 0x000004d0 }, + { 0x00001070 , 0x0000018c , 0x00000318 }, + { 0x000010b0 , 0x00000fd0 , 0x00001fa0 }, + { 0x00008014 , 0x044c044c , 0x08980898 }, + { 0x0000801c , 0x148ec02b , 0x148ec057 }, + { 0x00008318 , 0x000044c0 , 0x00008980 }, + { 0x00009e00 , 0x0372131c , 0x0372131c }, + { 0x0000a230 , 0x0000400b , 0x00004016 }, + { 0x0000a254 , 0x00000898 , 0x00001130 }, +}; + +static const u_int32_t ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x21020220 , 0x21020220 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x27020223 , 0x27020223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5c04286b , 0x5c04286b , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x61042a6c , 0x61042a6c , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x66062a6c , 0x66062a6c , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x6b062e6c , 0x6b062e6c , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x7006308c , 0x7006308c , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x730a308a , 0x730a308a , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0300cc03 , 0x0300cc03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x0300cc03 , 0x0300cc03 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03810c03 , 0x03810c03 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012482d4 , 0x012482d4 , 0x012482d4 , 0x012482d4 }, + { 0x00016048 , 0x64992060 , 0x64992060 , 0x64992060 , 0x64992060 }, + { 0x00016444 , 0x012482d4 , 0x012482d4 , 0x012482d4 , 0x012482d4 }, + { 0x00016448 , 0x64992000 , 0x64992000 , 0x64992000 , 0x64992000 }, +}; + +static const u_int32_t ar9300_jupiter_1p0_soc_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00007010 , 0x00002233 , 0x00002233 , 0x00002233 , 0x00002233 }, +}; + +static const u_int32_t ar9300_common_mixed_rx_gain_table_jupiter_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x03820190 }, + { 0x0000a030 , 0x03840383 }, + { 0x0000a034 , 0x03880385 }, + { 0x0000a038 , 0x038a0389 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x29292929 }, + { 0x0000a084 , 0x29292929 }, + { 0x0000a088 , 0x29292929 }, + { 0x0000a08c , 0x29292929 }, + { 0x0000a090 , 0x22292929 }, + { 0x0000a094 , 0x1d1d2222 }, + { 0x0000a098 , 0x0c111117 }, + { 0x0000a09c , 0x00030303 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x2a2d2f32 }, + { 0x0000b084 , 0x21232328 }, + { 0x0000b088 , 0x19191c1e }, + { 0x0000b08c , 0x12141417 }, + { 0x0000b090 , 0x07070e0e }, + { 0x0000b094 , 0x03030305 }, + { 0x0000b098 , 0x00000003 }, + { 0x0000b09c , 0x00000000 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x10013e5e }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0000580c }, +}; + +static const u_int32_t ar9300_jupiter_1p0_baseband_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafa68e30 }, + { 0x00009884 , 0x00002842 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009e50 , 0x00000000 }, + { 0x00009fcc , 0x00000014 }, + { 0x0000a344 , 0x00000010 }, + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x71733d01 }, + { 0x0000a3a0 , 0xd0ad5c12 }, + { 0x0000a3c0 , 0x22222220 }, + { 0x0000a3c4 , 0x22222222 }, + { 0x0000a404 , 0x00418a11 }, + { 0x0000a418 , 0x050001ce }, + { 0x0000a438 , 0x00001800 }, + { 0x0000a458 , 0x01444452 }, + { 0x0000a644 , 0x3fad9d74 }, + { 0x0000a690 , 0x00000038 }, +}; + +static const u_int32_t ar9300_jupiter_1p0_radio_core[][2] = { +/* Addr allmodes */ + { 0x00016000 , 0x36db6db6 }, + { 0x00016004 , 0x6db6db40 }, + { 0x00016008 , 0x73f00000 }, + { 0x0001600c , 0x00000000 }, + { 0x00016010 , 0x6d820001 }, + { 0x00016040 , 0x7f80fff8 }, + { 0x0001604c , 0x2699e04f }, + { 0x00016050 , 0x6db6db6c }, + { 0x00016054 , 0x6db60000 }, + { 0x00016058 , 0x6c200000 }, + { 0x00016080 , 0x00040000 }, + { 0x00016084 , 0x9a68048c }, + { 0x00016088 , 0x54214514 }, + { 0x0001608c , 0x12030409 }, + { 0x00016090 , 0x24926490 }, + { 0x00016098 , 0xd2888888 }, + { 0x000160a0 , 0x0a108ffe }, + { 0x000160a4 , 0x812fc490 }, + { 0x000160a8 , 0x423c8000 }, + { 0x000160b4 , 0x92000000 }, + { 0x000160b8 , 0x0285dddc }, + { 0x000160bc , 0x02908888 }, + { 0x000160c0 , 0x00adb6d0 }, + { 0x000160c4 , 0x6db6db60 }, + { 0x000160c8 , 0x6db6db6c }, + { 0x000160cc , 0x0de6c1b0 }, + { 0x00016100 , 0x3fffbe04 }, + { 0x00016104 , 0xfff80000 }, + { 0x00016108 , 0x00200400 }, + { 0x00016110 , 0x00000000 }, + { 0x00016144 , 0x02084080 }, + { 0x00016148 , 0x000080c0 }, + { 0x00016280 , 0x050a0001 }, + { 0x00016284 , 0x3d841400 }, + { 0x00016288 , 0x00000000 }, + { 0x0001628c , 0xe3000000 }, + { 0x00016290 , 0xa1005080 }, + { 0x00016294 , 0x00000020 }, + { 0x00016298 , 0x50a02900 }, + { 0x00016340 , 0x121e4276 }, + { 0x00016344 , 0x00300000 }, + { 0x00016400 , 0x36db6db6 }, + { 0x00016404 , 0x6db6db40 }, + { 0x00016408 , 0x73f00000 }, + { 0x0001640c , 0x00000000 }, + { 0x00016410 , 0x6c800001 }, + { 0x00016440 , 0x7f80fff8 }, + { 0x0001644c , 0x4699e04f }, + { 0x00016450 , 0x6db6db6c }, + { 0x00016454 , 0x6db60000 }, + { 0x00016500 , 0x3fffbe04 }, + { 0x00016504 , 0xfff80000 }, + { 0x00016508 , 0x00200400 }, + { 0x00016510 , 0x00000000 }, + { 0x00016544 , 0x02084080 }, + { 0x00016548 , 0x000080c0 }, +}; + +static const u_int32_t ar9300_jupiter_1p0_soc_preamble[][2] = { +/* Addr allmodes */ + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000004c2 }, +}; + +static const u_int32_t ar9300_jupiter_1p0_sys2ant[][2] = { +/* Addr allmodes */ + { 0x00063120 , 0x00801980 }, +}; + diff --git a/hal/ar9300/ar9300_jupiter20.ini b/hal/ar9300/ar9300_jupiter20.ini new file mode 100644 index 000000000000..bc22b4fcd43e --- /dev/null +++ b/hal/ar9300/ar9300_jupiter20.ini @@ -0,0 +1,2010 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +static const u_int32_t ar9300Modes_fast_clock_jupiter_2p0[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00001030 , 0x00000268 , 0x000004d0 }, + { 0x00001070 , 0x0000018c , 0x00000318 }, + { 0x000010b0 , 0x00000fd0 , 0x00001fa0 }, + { 0x00008014 , 0x044c044c , 0x08980898 }, + { 0x0000801c , 0x148ec02b , 0x148ec057 }, + { 0x00008318 , 0x000044c0 , 0x00008980 }, + { 0x00009e00 , 0x0372131c , 0x0372131c }, + { 0x0000a230 , 0x0000400b , 0x00004016 }, + { 0x0000a254 , 0x00000898 , 0x00001130 }, +}; + +static const u_int32_t ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x18253ede }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0003580c }, +}; + +static const u_int32_t ar9300_jupiter_2p0_baseband_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8011 , 0xd00a8011 }, + { 0x00009820 , 0x206a022e , 0x206a022e , 0x206a012e , 0x206a012e }, + { 0x00009824 , 0x5ac640de , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640de }, + { 0x00009828 , 0x0796be89 , 0x0696b081 , 0x0696b881 , 0x0796be89 }, + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000119c , 0x0000119c }, + { 0x00009c00 , 0x000000c4 , 0x000000c4 , 0x000000c4 , 0x000000c4 }, + { 0x00009e00 , 0x0372111a , 0x0372111a , 0x037216a0 , 0x037216a0 }, + { 0x00009e04 , 0x001c2020 , 0x001c2020 , 0x001c2020 , 0x001c2020 }, + { 0x00009e0c , 0x6c4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + { 0x00009e10 , 0x92c88d2e , 0x7ec88d2e , 0x7ec84d2e , 0x92c84d2e }, + { 0x00009e14 , 0x37b95d5e , 0x37b9605e , 0x3379605e , 0x33795d5e }, + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + { 0x00009e2c , 0x0000001c , 0x0000001c , 0x00000021 , 0x00000021 }, + { 0x00009e3c , 0xcf946220 , 0xcf946220 , 0xcfd5c782 , 0xcfd5c782 }, + { 0x00009e44 , 0xfe321e27 , 0xfe321e27 , 0xfe291e27 , 0xfe291e27 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302012 , 0x50302012 }, + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, + { 0x0000a204 , 0x013187c0 , 0x013187c4 , 0x013187c4 , 0x013187c0 }, + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + { 0x0000a22c , 0x01026a2f , 0x01026a27 , 0x01026a2f , 0x01026a2f }, + { 0x0000a230 , 0x0000400a , 0x00004014 , 0x00004016 , 0x0000400b }, + { 0x0000a234 , 0x00000fff , 0x10000fff , 0x10000fff , 0x00000fff }, + { 0x0000a238 , 0xffb81018 , 0xffb81018 , 0xffb81018 , 0xffb81018 }, + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a260 , 0x0a021501 , 0x0a021501 , 0x3a021501 , 0x3a021501 }, + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, + { 0x0000a288 , 0x00000110 , 0x00000110 , 0x00000110 , 0x00000110 }, + { 0x0000a28c , 0x00022222 , 0x00022222 , 0x00022222 , 0x00022222 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2d0 , 0x00041981 , 0x00041981 , 0x00041981 , 0x00041982 }, + { 0x0000a2d8 , 0x7999a83b , 0x7999a83b , 0x7999a83b , 0x7999a83b }, + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a830 , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae04 , 0x001c0000 , 0x001c0000 , 0x001c0000 , 0x00100000 }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000ae1c , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae20 , 0x000001b5 , 0x000001b5 , 0x000001ce , 0x000001ce }, + { 0x0000b284 , 0x00000000 , 0x00000000 , 0x00000550 , 0x00000550 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_mac_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00000030 , 0x000e0085 }, + { 0x00000044 , 0x00000008 }, + { 0x0000805c , 0xffffc7ff }, + { 0x00008344 , 0xaa4a105b }, +}; + +static const u_int32_t ar9300Common_rx_gain_table_jupiter_2p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x01910190 }, + { 0x0000a030 , 0x01930192 }, + { 0x0000a034 , 0x01950194 }, + { 0x0000a038 , 0x038a0196 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x22222229 }, + { 0x0000a084 , 0x1d1d1d1d }, + { 0x0000a088 , 0x1d1d1d1d }, + { 0x0000a08c , 0x1d1d1d1d }, + { 0x0000a090 , 0x171d1d1d }, + { 0x0000a094 , 0x11111717 }, + { 0x0000a098 , 0x00030311 }, + { 0x0000a09c , 0x00000000 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x2a2d2f32 }, + { 0x0000b084 , 0x21232328 }, + { 0x0000b088 , 0x19191c1e }, + { 0x0000b08c , 0x12141417 }, + { 0x0000b090 , 0x07070e0e }, + { 0x0000b094 , 0x03030305 }, + { 0x0000b098 , 0x00000003 }, + { 0x0000b09c , 0x00000000 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x18213ede }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0003580c }, +}; + +static const u_int32_t ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x18212ede }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0003580c }, +}; + +static const u_int32_t ar9300_jupiter_2p0_sys3ant[][2] = { +/* Addr allmodes */ + { 0x00063280 , 0x00040807 }, + { 0x00063284 , 0x104ccccc }, +}; + +static const u_int32_t ar9300Common_rx_gain_table_merlin_2p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x02000101 }, + { 0x0000a004 , 0x02000102 }, + { 0x0000a008 , 0x02000103 }, + { 0x0000a00c , 0x02000104 }, + { 0x0000a010 , 0x02000200 }, + { 0x0000a014 , 0x02000201 }, + { 0x0000a018 , 0x02000202 }, + { 0x0000a01c , 0x02000203 }, + { 0x0000a020 , 0x02000204 }, + { 0x0000a024 , 0x02000205 }, + { 0x0000a028 , 0x02000208 }, + { 0x0000a02c , 0x02000302 }, + { 0x0000a030 , 0x02000303 }, + { 0x0000a034 , 0x02000304 }, + { 0x0000a038 , 0x02000400 }, + { 0x0000a03c , 0x02010300 }, + { 0x0000a040 , 0x02010301 }, + { 0x0000a044 , 0x02010302 }, + { 0x0000a048 , 0x02000500 }, + { 0x0000a04c , 0x02010400 }, + { 0x0000a050 , 0x02020300 }, + { 0x0000a054 , 0x02020301 }, + { 0x0000a058 , 0x02020302 }, + { 0x0000a05c , 0x02020303 }, + { 0x0000a060 , 0x02020400 }, + { 0x0000a064 , 0x02030300 }, + { 0x0000a068 , 0x02030301 }, + { 0x0000a06c , 0x02030302 }, + { 0x0000a070 , 0x02030303 }, + { 0x0000a074 , 0x02030400 }, + { 0x0000a078 , 0x02040300 }, + { 0x0000a07c , 0x02040301 }, + { 0x0000a080 , 0x02040302 }, + { 0x0000a084 , 0x02040303 }, + { 0x0000a088 , 0x02030500 }, + { 0x0000a08c , 0x02040400 }, + { 0x0000a090 , 0x02050203 }, + { 0x0000a094 , 0x02050204 }, + { 0x0000a098 , 0x02050205 }, + { 0x0000a09c , 0x02040500 }, + { 0x0000a0a0 , 0x02050301 }, + { 0x0000a0a4 , 0x02050302 }, + { 0x0000a0a8 , 0x02050303 }, + { 0x0000a0ac , 0x02050400 }, + { 0x0000a0b0 , 0x02050401 }, + { 0x0000a0b4 , 0x02050402 }, + { 0x0000a0b8 , 0x02050403 }, + { 0x0000a0bc , 0x02050500 }, + { 0x0000a0c0 , 0x02050501 }, + { 0x0000a0c4 , 0x02050502 }, + { 0x0000a0c8 , 0x02050503 }, + { 0x0000a0cc , 0x02050504 }, + { 0x0000a0d0 , 0x02050600 }, + { 0x0000a0d4 , 0x02050601 }, + { 0x0000a0d8 , 0x02050602 }, + { 0x0000a0dc , 0x02050603 }, + { 0x0000a0e0 , 0x02050604 }, + { 0x0000a0e4 , 0x02050700 }, + { 0x0000a0e8 , 0x02050701 }, + { 0x0000a0ec , 0x02050702 }, + { 0x0000a0f0 , 0x02050703 }, + { 0x0000a0f4 , 0x02050704 }, + { 0x0000a0f8 , 0x02050705 }, + { 0x0000a0fc , 0x02050708 }, + { 0x0000a100 , 0x02050709 }, + { 0x0000a104 , 0x0205070a }, + { 0x0000a108 , 0x0205070b }, + { 0x0000a10c , 0x0205070c }, + { 0x0000a110 , 0x0205070d }, + { 0x0000a114 , 0x02050710 }, + { 0x0000a118 , 0x02050711 }, + { 0x0000a11c , 0x02050712 }, + { 0x0000a120 , 0x02050713 }, + { 0x0000a124 , 0x02050714 }, + { 0x0000a128 , 0x02050715 }, + { 0x0000a12c , 0x02050730 }, + { 0x0000a130 , 0x02050731 }, + { 0x0000a134 , 0x02050732 }, + { 0x0000a138 , 0x02050733 }, + { 0x0000a13c , 0x02050734 }, + { 0x0000a140 , 0x02050735 }, + { 0x0000a144 , 0x02050750 }, + { 0x0000a148 , 0x02050751 }, + { 0x0000a14c , 0x02050752 }, + { 0x0000a150 , 0x02050753 }, + { 0x0000a154 , 0x02050754 }, + { 0x0000a158 , 0x02050755 }, + { 0x0000a15c , 0x02050770 }, + { 0x0000a160 , 0x02050771 }, + { 0x0000a164 , 0x02050772 }, + { 0x0000a168 , 0x02050773 }, + { 0x0000a16c , 0x02050774 }, + { 0x0000a170 , 0x02050775 }, + { 0x0000a174 , 0x00000776 }, + { 0x0000a178 , 0x00000776 }, + { 0x0000a17c , 0x00000776 }, + { 0x0000a180 , 0x00000776 }, + { 0x0000a184 , 0x00000776 }, + { 0x0000a188 , 0x00000776 }, + { 0x0000a18c , 0x00000776 }, + { 0x0000a190 , 0x00000776 }, + { 0x0000a194 , 0x00000776 }, + { 0x0000a198 , 0x00000776 }, + { 0x0000a19c , 0x00000776 }, + { 0x0000a1a0 , 0x00000776 }, + { 0x0000a1a4 , 0x00000776 }, + { 0x0000a1a8 , 0x00000776 }, + { 0x0000a1ac , 0x00000776 }, + { 0x0000a1b0 , 0x00000776 }, + { 0x0000a1b4 , 0x00000776 }, + { 0x0000a1b8 , 0x00000776 }, + { 0x0000a1bc , 0x00000776 }, + { 0x0000a1c0 , 0x00000776 }, + { 0x0000a1c4 , 0x00000776 }, + { 0x0000a1c8 , 0x00000776 }, + { 0x0000a1cc , 0x00000776 }, + { 0x0000a1d0 , 0x00000776 }, + { 0x0000a1d4 , 0x00000776 }, + { 0x0000a1d8 , 0x00000776 }, + { 0x0000a1dc , 0x00000776 }, + { 0x0000a1e0 , 0x00000776 }, + { 0x0000a1e4 , 0x00000776 }, + { 0x0000a1e8 , 0x00000776 }, + { 0x0000a1ec , 0x00000776 }, + { 0x0000a1f0 , 0x00000776 }, + { 0x0000a1f4 , 0x00000776 }, + { 0x0000a1f8 , 0x00000776 }, + { 0x0000a1fc , 0x00000776 }, + { 0x0000b000 , 0x02000101 }, + { 0x0000b004 , 0x02000102 }, + { 0x0000b008 , 0x02000103 }, + { 0x0000b00c , 0x02000104 }, + { 0x0000b010 , 0x02000200 }, + { 0x0000b014 , 0x02000201 }, + { 0x0000b018 , 0x02000202 }, + { 0x0000b01c , 0x02000203 }, + { 0x0000b020 , 0x02000204 }, + { 0x0000b024 , 0x02000205 }, + { 0x0000b028 , 0x02000208 }, + { 0x0000b02c , 0x02000302 }, + { 0x0000b030 , 0x02000303 }, + { 0x0000b034 , 0x02000304 }, + { 0x0000b038 , 0x02000400 }, + { 0x0000b03c , 0x02010300 }, + { 0x0000b040 , 0x02010301 }, + { 0x0000b044 , 0x02010302 }, + { 0x0000b048 , 0x02000500 }, + { 0x0000b04c , 0x02010400 }, + { 0x0000b050 , 0x02020300 }, + { 0x0000b054 , 0x02020301 }, + { 0x0000b058 , 0x02020302 }, + { 0x0000b05c , 0x02020303 }, + { 0x0000b060 , 0x02020400 }, + { 0x0000b064 , 0x02030300 }, + { 0x0000b068 , 0x02030301 }, + { 0x0000b06c , 0x02030302 }, + { 0x0000b070 , 0x02030303 }, + { 0x0000b074 , 0x02030400 }, + { 0x0000b078 , 0x02040300 }, + { 0x0000b07c , 0x02040301 }, + { 0x0000b080 , 0x02040302 }, + { 0x0000b084 , 0x02040303 }, + { 0x0000b088 , 0x02030500 }, + { 0x0000b08c , 0x02040400 }, + { 0x0000b090 , 0x02050203 }, + { 0x0000b094 , 0x02050204 }, + { 0x0000b098 , 0x02050205 }, + { 0x0000b09c , 0x02040500 }, + { 0x0000b0a0 , 0x02050301 }, + { 0x0000b0a4 , 0x02050302 }, + { 0x0000b0a8 , 0x02050303 }, + { 0x0000b0ac , 0x02050400 }, + { 0x0000b0b0 , 0x02050401 }, + { 0x0000b0b4 , 0x02050402 }, + { 0x0000b0b8 , 0x02050403 }, + { 0x0000b0bc , 0x02050500 }, + { 0x0000b0c0 , 0x02050501 }, + { 0x0000b0c4 , 0x02050502 }, + { 0x0000b0c8 , 0x02050503 }, + { 0x0000b0cc , 0x02050504 }, + { 0x0000b0d0 , 0x02050600 }, + { 0x0000b0d4 , 0x02050601 }, + { 0x0000b0d8 , 0x02050602 }, + { 0x0000b0dc , 0x02050603 }, + { 0x0000b0e0 , 0x02050604 }, + { 0x0000b0e4 , 0x02050700 }, + { 0x0000b0e8 , 0x02050701 }, + { 0x0000b0ec , 0x02050702 }, + { 0x0000b0f0 , 0x02050703 }, + { 0x0000b0f4 , 0x02050704 }, + { 0x0000b0f8 , 0x02050705 }, + { 0x0000b0fc , 0x02050708 }, + { 0x0000b100 , 0x02050709 }, + { 0x0000b104 , 0x0205070a }, + { 0x0000b108 , 0x0205070b }, + { 0x0000b10c , 0x0205070c }, + { 0x0000b110 , 0x0205070d }, + { 0x0000b114 , 0x02050710 }, + { 0x0000b118 , 0x02050711 }, + { 0x0000b11c , 0x02050712 }, + { 0x0000b120 , 0x02050713 }, + { 0x0000b124 , 0x02050714 }, + { 0x0000b128 , 0x02050715 }, + { 0x0000b12c , 0x02050730 }, + { 0x0000b130 , 0x02050731 }, + { 0x0000b134 , 0x02050732 }, + { 0x0000b138 , 0x02050733 }, + { 0x0000b13c , 0x02050734 }, + { 0x0000b140 , 0x02050735 }, + { 0x0000b144 , 0x02050750 }, + { 0x0000b148 , 0x02050751 }, + { 0x0000b14c , 0x02050752 }, + { 0x0000b150 , 0x02050753 }, + { 0x0000b154 , 0x02050754 }, + { 0x0000b158 , 0x02050755 }, + { 0x0000b15c , 0x02050770 }, + { 0x0000b160 , 0x02050771 }, + { 0x0000b164 , 0x02050772 }, + { 0x0000b168 , 0x02050773 }, + { 0x0000b16c , 0x02050774 }, + { 0x0000b170 , 0x02050775 }, + { 0x0000b174 , 0x00000776 }, + { 0x0000b178 , 0x00000776 }, + { 0x0000b17c , 0x00000776 }, + { 0x0000b180 , 0x00000776 }, + { 0x0000b184 , 0x00000776 }, + { 0x0000b188 , 0x00000776 }, + { 0x0000b18c , 0x00000776 }, + { 0x0000b190 , 0x00000776 }, + { 0x0000b194 , 0x00000776 }, + { 0x0000b198 , 0x00000776 }, + { 0x0000b19c , 0x00000776 }, + { 0x0000b1a0 , 0x00000776 }, + { 0x0000b1a4 , 0x00000776 }, + { 0x0000b1a8 , 0x00000776 }, + { 0x0000b1ac , 0x00000776 }, + { 0x0000b1b0 , 0x00000776 }, + { 0x0000b1b4 , 0x00000776 }, + { 0x0000b1b8 , 0x00000776 }, + { 0x0000b1bc , 0x00000776 }, + { 0x0000b1c0 , 0x00000776 }, + { 0x0000b1c4 , 0x00000776 }, + { 0x0000b1c8 , 0x00000776 }, + { 0x0000b1cc , 0x00000776 }, + { 0x0000b1d0 , 0x00000776 }, + { 0x0000b1d4 , 0x00000776 }, + { 0x0000b1d8 , 0x00000776 }, + { 0x0000b1dc , 0x00000776 }, + { 0x0000b1e0 , 0x00000776 }, + { 0x0000b1e4 , 0x00000776 }, + { 0x0000b1e8 , 0x00000776 }, + { 0x0000b1ec , 0x00000776 }, + { 0x0000b1f0 , 0x00000776 }, + { 0x0000b1f4 , 0x00000776 }, + { 0x0000b1f8 , 0x00000776 }, + { 0x0000b1fc , 0x00000776 }, +}; + +static const u_int32_t ar9200_merlin_2p0_radio_core[][2] = { +/* Addr common */ + { 0x00007800 , 0x00040000 }, + { 0x00007804 , 0xdb005012 }, + { 0x00007808 , 0x04924914 }, + { 0x0000780c , 0x21084210 }, + { 0x00007810 , 0x6d801300 }, + { 0x00007814 , 0x0019beff }, + { 0x00007818 , 0x07e41000 }, + { 0x0000781c , 0x00392000 }, + { 0x00007820 , 0x92592480 }, + { 0x00007824 , 0x00040000 }, + { 0x00007828 , 0xdb005012 }, + { 0x0000782c , 0x04924914 }, + { 0x00007830 , 0x21084210 }, + { 0x00007834 , 0x6d801300 }, + { 0x00007838 , 0x0019beff }, + { 0x0000783c , 0x07e40000 }, + { 0x00007840 , 0x00392000 }, + { 0x00007844 , 0x92592480 }, + { 0x00007848 , 0x00100000 }, + { 0x0000784c , 0x773f0567 }, + { 0x00007850 , 0x54214514 }, + { 0x00007854 , 0x12035828 }, + { 0x00007858 , 0x92592692 }, + { 0x0000785c , 0x00000000 }, + { 0x00007860 , 0x56400000 }, + { 0x00007864 , 0x0a8e370e }, + { 0x00007868 , 0xc0102850 }, + { 0x0000786c , 0x812d4000 }, + { 0x00007870 , 0x807ec400 }, + { 0x00007874 , 0x001b6db0 }, + { 0x00007878 , 0x00376b63 }, + { 0x0000787c , 0x06db6db6 }, + { 0x00007880 , 0x006d8000 }, + { 0x00007884 , 0xffeffffe }, + { 0x00007888 , 0xffeffffe }, + { 0x0000788c , 0x00010000 }, + { 0x00007890 , 0x02060aeb }, + { 0x00007894 , 0x5a108000 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_mac_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 }, + { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_radio_postamble_sys3ant[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000160ac , 0xa4646c08 , 0xa4646c08 , 0x24645808 , 0x24645808 }, + { 0x00016140 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, + { 0x00016540 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e3c , 0xcf946221 , 0xcf946221 , 0xcf946221 , 0xcf946221 }, + { 0x00009e44 , 0xfc5c0000 , 0xfc5c0000 , 0xfc5c0000 , 0xfc5c0000 }, + { 0x0000a258 , 0x02020200 , 0x02020200 , 0x02020200 , 0x02020200 }, + { 0x0000a25c , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a28c , 0x00011111 , 0x00011111 , 0x00011111 , 0x00011111 }, + { 0x0000a2c4 , 0x00148d18 , 0x00148d18 , 0x00148d20 , 0x00148d20 }, + { 0x0000a2d8 , 0xf999a800 , 0xf999a800 , 0xf999a80c , 0xf999a80c }, + { 0x0000a50c , 0x0000c00a , 0x0000c00a , 0x0000c00a , 0x0000c00a }, + { 0x0000a538 , 0x00038e8c , 0x00038e8c , 0x00038e8c , 0x00038e8c }, + { 0x0000a53c , 0x0003cecc , 0x0003cecc , 0x0003cecc , 0x0003cecc }, + { 0x0000a540 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 }, + { 0x0000a544 , 0x00044edc , 0x00044edc , 0x00044edc , 0x00044edc }, + { 0x0000a548 , 0x00048ede , 0x00048ede , 0x00048ede , 0x00048ede }, + { 0x0000a54c , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e }, + { 0x0000a550 , 0x00050f5e , 0x00050f5e , 0x00050f5e , 0x00050f5e }, + { 0x0000a554 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_radio_postamble_sys2ant[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000160ac , 0xa4646c08 , 0xa4646c08 , 0x24645808 , 0x24645808 }, + { 0x00016140 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, + { 0x00016540 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, +}; + +static const u_int32_t ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x03820190 }, + { 0x0000a030 , 0x03840383 }, + { 0x0000a034 , 0x03880385 }, + { 0x0000a038 , 0x038a0389 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x29292929 }, + { 0x0000a084 , 0x29292929 }, + { 0x0000a088 , 0x29292929 }, + { 0x0000a08c , 0x29292929 }, + { 0x0000a090 , 0x22292929 }, + { 0x0000a094 , 0x1d1d2222 }, + { 0x0000a098 , 0x0c111117 }, + { 0x0000a09c , 0x00030303 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x32323232 }, + { 0x0000b084 , 0x2f2f3232 }, + { 0x0000b088 , 0x23282a2d }, + { 0x0000b08c , 0x1c1e2123 }, + { 0x0000b090 , 0x14171919 }, + { 0x0000b094 , 0x0e0e1214 }, + { 0x0000b098 , 0x03050707 }, + { 0x0000b09c , 0x00030303 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484[][2] = { +/* Addr allmodes */ + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x6f7f0301 }, + { 0x0000a3a0 , 0xca9228ee }, +}; + +static const u_int32_t ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000002 , 0x00000002 , 0x00000002 , 0x00000002 }, + { 0x0000a2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a458 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x21020220 , 0x21020220 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x27020223 , 0x27020223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5c04286b , 0x5c04286b , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x61042a6c , 0x61042a6c , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x66062a6c , 0x66062a6c , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x6b062e6c , 0x6b062e6c , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x7006308c , 0x7006308c , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x730a308a , 0x730a308a , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0300cc03 , 0x0300cc03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x0300cc03 , 0x0300cc03 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03810c03 , 0x03810c03 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012482d4 , 0x012482d4 , 0x012482d4 , 0x012482d4 }, + { 0x00016048 , 0x64992060 , 0x64992060 , 0x64992060 , 0x64992060 }, + { 0x00016054 , 0x6db60000 , 0x6db60000 , 0x6db60000 , 0x6db60000 }, + { 0x00016444 , 0x012482d4 , 0x012482d4 , 0x012482d4 , 0x012482d4 }, + { 0x00016448 , 0x64992000 , 0x64992000 , 0x64992000 , 0x64992000 }, + { 0x00016454 , 0x6db60000 , 0x6db60000 , 0x6db60000 , 0x6db60000 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_soc_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00007010 , 0x00000033 , 0x00000033 , 0x00000033 , 0x00000033 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_baseband_core[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009804 , 0xfd14e000 }, + { 0x00009808 , 0x9c0a9f6b }, + { 0x0000980c , 0x04900000 }, + { 0x00009814 , 0x9280c00a }, + { 0x00009818 , 0x00000000 }, + { 0x0000981c , 0x00020028 }, + { 0x00009834 , 0x6400a290 }, + { 0x00009838 , 0x0108ecff }, + { 0x0000983c , 0x0d000600 }, + { 0x00009880 , 0x201fff00 }, + { 0x00009884 , 0x00001042 }, + { 0x000098a4 , 0x00200400 }, + { 0x000098b0 , 0x32440bbe }, + { 0x000098d0 , 0x004b6a8e }, + { 0x000098d4 , 0x00000820 }, + { 0x000098dc , 0x00000000 }, + { 0x000098e4 , 0x01ffffff }, + { 0x000098e8 , 0x01ffffff }, + { 0x000098ec , 0x01ffffff }, + { 0x000098f0 , 0x00000000 }, + { 0x000098f4 , 0x00000000 }, + { 0x00009bf0 , 0x80000000 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009c0c , 0x00000000 }, + { 0x00009c10 , 0x00000000 }, + { 0x00009c14 , 0x00046384 }, + { 0x00009c18 , 0x05b6b440 }, + { 0x00009c1c , 0x00b6b440 }, + { 0x00009d00 , 0xc080a333 }, + { 0x00009d04 , 0x40206c10 }, + { 0x00009d08 , 0x009c4060 }, + { 0x00009d0c , 0x9883800a }, + { 0x00009d10 , 0x01834061 }, + { 0x00009d14 , 0x00c0040b }, + { 0x00009d18 , 0x00000000 }, + { 0x00009e08 , 0x0038230c }, + { 0x00009e24 , 0x990bb515 }, + { 0x00009e28 , 0x0c6f0000 }, + { 0x00009e30 , 0x06336f77 }, + { 0x00009e34 , 0x6af6532f }, + { 0x00009e38 , 0x0cc80c00 }, + { 0x00009e40 , 0x0d261820 }, + { 0x00009e4c , 0x00001004 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009e54 , 0xe4c355c7 }, + { 0x00009e58 , 0xfd897735 }, + { 0x00009e5c , 0xe9198724 }, + { 0x00009fc0 , 0x803e4788 }, + { 0x00009fc4 , 0x0001efb5 }, + { 0x00009fcc , 0x40000014 }, + { 0x00009fd0 , 0x01193b93 }, + { 0x0000a20c , 0x00000000 }, + { 0x0000a220 , 0x00000000 }, + { 0x0000a224 , 0x00000000 }, + { 0x0000a228 , 0x10002310 }, + { 0x0000a23c , 0x00000000 }, + { 0x0000a244 , 0x0c000000 }, + { 0x0000a2a0 , 0x00000001 }, + { 0x0000a2c0 , 0x00000001 }, + { 0x0000a2c8 , 0x00000000 }, + { 0x0000a2cc , 0x18c43433 }, + { 0x0000a2d4 , 0x00000000 }, + { 0x0000a2ec , 0x00000000 }, + { 0x0000a2f0 , 0x00000000 }, + { 0x0000a2f4 , 0x00000000 }, + { 0x0000a2f8 , 0x00000000 }, + { 0x0000a344 , 0x00000000 }, + { 0x0000a34c , 0x00000000 }, + { 0x0000a350 , 0x0000a000 }, + { 0x0000a364 , 0x00000000 }, + { 0x0000a370 , 0x00000000 }, + { 0x0000a390 , 0x00000001 }, + { 0x0000a394 , 0x00000444 }, + { 0x0000a398 , 0x001f0e0f }, + { 0x0000a39c , 0x0075393f }, + { 0x0000a3a0 , 0xb79f6427 }, + { 0x0000a3a4 , 0x00000000 }, + { 0x0000a3a8 , 0xaaaaaaaa }, + { 0x0000a3ac , 0x3c466478 }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a3c8 , 0x20200020 }, + { 0x0000a3cc , 0x20202020 }, + { 0x0000a3d0 , 0x20202020 }, + { 0x0000a3d4 , 0x20202020 }, + { 0x0000a3d8 , 0x20202020 }, + { 0x0000a3dc , 0x20202020 }, + { 0x0000a3e0 , 0x20202020 }, + { 0x0000a3e4 , 0x20202020 }, + { 0x0000a3e8 , 0x20202020 }, + { 0x0000a3ec , 0x20202020 }, + { 0x0000a3f0 , 0x00000000 }, + { 0x0000a3f4 , 0x00000006 }, + { 0x0000a3f8 , 0x0c9bd380 }, + { 0x0000a3fc , 0x000f0f01 }, + { 0x0000a400 , 0x8fa91f01 }, + { 0x0000a404 , 0x00000000 }, + { 0x0000a408 , 0x0e79e5c6 }, + { 0x0000a40c , 0x00820820 }, + { 0x0000a414 , 0x1ce739ce }, + { 0x0000a418 , 0x2d001dce }, + { 0x0000a41c , 0x1ce739ce }, + { 0x0000a420 , 0x000001ce }, + { 0x0000a424 , 0x1ce739ce }, + { 0x0000a428 , 0x000001ce }, + { 0x0000a42c , 0x1ce739ce }, + { 0x0000a430 , 0x1ce739ce }, + { 0x0000a434 , 0x00000000 }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a43c , 0x00100000 }, + { 0x0000a444 , 0x00000000 }, + { 0x0000a448 , 0x05000080 }, + { 0x0000a44c , 0x00000001 }, + { 0x0000a450 , 0x00010000 }, + { 0x0000a454 , 0x07000000 }, + { 0x0000a644 , 0xbfad9d74 }, + { 0x0000a648 , 0x0048060a }, + { 0x0000a64c , 0x00002037 }, + { 0x0000a670 , 0x03020100 }, + { 0x0000a674 , 0x09080504 }, + { 0x0000a678 , 0x0d0c0b0a }, + { 0x0000a67c , 0x13121110 }, + { 0x0000a680 , 0x31301514 }, + { 0x0000a684 , 0x35343332 }, + { 0x0000a688 , 0x00000036 }, + { 0x0000a690 , 0x00000838 }, + { 0x0000a6b0 , 0x0000000a }, + { 0x0000a6b4 , 0x00512c01 }, + { 0x0000a7c0 , 0x00000000 }, + { 0x0000a7c4 , 0xfffffffc }, + { 0x0000a7c8 , 0x00000000 }, + { 0x0000a7cc , 0x00000000 }, + { 0x0000a7d0 , 0x00000000 }, + { 0x0000a7d4 , 0x00000004 }, + { 0x0000a7dc , 0x00000001 }, + { 0x0000a7f0 , 0x80000000 }, + { 0x0000a8d0 , 0x004b6a8e }, + { 0x0000a8d4 , 0x00000820 }, + { 0x0000a8dc , 0x00000000 }, + { 0x0000a8f0 , 0x00000000 }, + { 0x0000a8f4 , 0x00000000 }, + { 0x0000abf0 , 0x80000000 }, + { 0x0000b2d0 , 0x00000080 }, + { 0x0000b2d4 , 0x00000000 }, + { 0x0000b2ec , 0x00000000 }, + { 0x0000b2f0 , 0x00000000 }, + { 0x0000b2f4 , 0x00000000 }, + { 0x0000b2f8 , 0x00000000 }, + { 0x0000b408 , 0x0e79e5c0 }, + { 0x0000b40c , 0x00820820 }, + { 0x0000b420 , 0x00000000 }, + { 0x0000b6b0 , 0x0000000a }, + { 0x0000b6b4 , 0x00000001 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_radio_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0001609c , 0x0b8ee524 , 0x0b8ee524 , 0x0b8ee524 , 0x0b8ee524 }, + { 0x000160b0 , 0x01d67f70 , 0x01d67f70 , 0x01d67f70 , 0x01d67f70 }, + { 0x0001610c , 0x48000000 , 0x40000000 , 0x40000000 , 0x40000000 }, + { 0x0001650c , 0x48000000 , 0x40000000 , 0x40000000 , 0x40000000 }, +}; + +static const u_int32_t ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000002 , 0x00000002 , 0x00000002 , 0x00000002 }, + { 0x0000a2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a458 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06002223 , 0x06002223 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a022220 , 0x0a022220 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x0f022223 , 0x0f022223 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x14022620 , 0x14022620 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x18022622 , 0x18022622 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x1b022822 , 0x1b022822 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x20022842 , 0x20022842 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x22022c41 , 0x22022c41 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x28023042 , 0x28023042 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x2c023044 , 0x2c023044 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x2f023644 , 0x2f023644 , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x34025643 , 0x34025643 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x38025a44 , 0x38025a44 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x3b025e45 , 0x3b025e45 , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x41025e4a , 0x41025e4a , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x48025e6c , 0x48025e6c , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x4e025e8e , 0x4e025e8e , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x53025eb2 , 0x53025eb2 , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x59025eb6 , 0x59025eb6 , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x5d025ef6 , 0x5d025ef6 , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x62025f56 , 0x62025f56 , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x66027f56 , 0x66027f56 , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x6a029f56 , 0x6a029f56 , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x70049f56 , 0x70049f56 , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00804000 , 0x00804000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x00804201 , 0x00804201 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x0280c802 , 0x0280c802 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x0280ca03 , 0x0280ca03 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x04c15104 , 0x04c15104 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04c15305 , 0x04c15305 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04c15305 , 0x04c15305 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 }, + { 0x00016048 , 0x8db49060 , 0x8db49060 , 0x8db49060 , 0x8db49060 }, + { 0x00016054 , 0x6db60000 , 0x6db60000 , 0x6db60000 , 0x6db60000 }, + { 0x00016444 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 }, + { 0x00016448 , 0x8db49000 , 0x8db49000 , 0x8db49000 , 0x8db49000 }, + { 0x00016454 , 0x6db60000 , 0x6db60000 , 0x6db60000 , 0x6db60000 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_radio_core[][2] = { +/* Addr allmodes */ + { 0x00016000 , 0x36db6db6 }, + { 0x00016004 , 0x6db6db40 }, + { 0x00016008 , 0x73f00000 }, + { 0x0001600c , 0x00000000 }, + { 0x00016010 , 0x6d820001 }, + { 0x00016040 , 0x7f80fff8 }, + { 0x0001604c , 0x2699e04f }, + { 0x00016050 , 0x6db6db6c }, + { 0x00016058 , 0x6c200000 }, + { 0x00016080 , 0x000c0000 }, + { 0x00016084 , 0x9a68048c }, + { 0x00016088 , 0x54214514 }, + { 0x0001608c , 0x1203040b }, + { 0x00016090 , 0x24926490 }, + { 0x00016098 , 0xd2888888 }, + { 0x000160a0 , 0x0a108ffe }, + { 0x000160a4 , 0x812fc491 }, + { 0x000160a8 , 0x423c8000 }, + { 0x000160b4 , 0x92000000 }, + { 0x000160b8 , 0x0285dddc }, + { 0x000160bc , 0x02908888 }, + { 0x000160c0 , 0x00adb6d0 }, + { 0x000160c4 , 0x6db6db60 }, + { 0x000160c8 , 0x6db6db6c }, + { 0x000160cc , 0x0de6c1b0 }, + { 0x00016100 , 0x3fffbe04 }, + { 0x00016104 , 0xfff80000 }, + { 0x00016108 , 0x00200400 }, + { 0x00016110 , 0x00000000 }, + { 0x00016144 , 0x02084080 }, + { 0x00016148 , 0x000080c0 }, + { 0x00016280 , 0x050a0001 }, + { 0x00016284 , 0x3d841400 }, + { 0x00016288 , 0x00000000 }, + { 0x0001628c , 0xe3000000 }, + { 0x00016290 , 0xa1005080 }, + { 0x00016294 , 0x00000020 }, + { 0x00016298 , 0x54a82900 }, + { 0x00016340 , 0x121e4276 }, + { 0x00016344 , 0x00300000 }, + { 0x00016400 , 0x36db6db6 }, + { 0x00016404 , 0x6db6db40 }, + { 0x00016408 , 0x73f00000 }, + { 0x0001640c , 0x00000000 }, + { 0x00016410 , 0x6c800001 }, + { 0x00016440 , 0x7f80fff8 }, + { 0x0001644c , 0x4699e04f }, + { 0x00016450 , 0x6db6db6c }, + { 0x00016500 , 0x3fffbe04 }, + { 0x00016504 , 0xfff80000 }, + { 0x00016508 , 0x00200400 }, + { 0x00016510 , 0x00000000 }, + { 0x00016544 , 0x02084080 }, + { 0x00016548 , 0x000080c0 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_tx_gain_table_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000000d5 , 0x000000d5 , 0x000000d5 , 0x000000d5 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x00004002 , 0x00004002 , 0x00004002 , 0x00004002 }, + { 0x0000a508 , 0x00008004 , 0x00008004 , 0x00008004 , 0x00008004 }, + { 0x0000a510 , 0x0001000c , 0x0001000c , 0x0001000c , 0x0001000c }, + { 0x0000a514 , 0x0001420b , 0x0001420b , 0x0001420b , 0x0001420b }, + { 0x0000a518 , 0x0001824a , 0x0001824a , 0x0001824a , 0x0001824a }, + { 0x0000a51c , 0x0001c44a , 0x0001c44a , 0x0001c44a , 0x0001c44a }, + { 0x0000a520 , 0x0002064a , 0x0002064a , 0x0002064a , 0x0002064a }, + { 0x0000a524 , 0x0002484a , 0x0002484a , 0x0002484a , 0x0002484a }, + { 0x0000a528 , 0x00028a4a , 0x00028a4a , 0x00028a4a , 0x00028a4a }, + { 0x0000a52c , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a }, + { 0x0000a530 , 0x00030e4a , 0x00030e4a , 0x00030e4a , 0x00030e4a }, + { 0x0000a534 , 0x00034e8a , 0x00034e8a , 0x00034e8a , 0x00034e8a }, +}; + +static const u_int32_t ar9300_jupiter_2p0_soc_preamble[][2] = { +/* Addr allmodes */ + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000004c2 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_sys2ant[][2] = { +/* Addr allmodes */ + { 0x00063120 , 0x00801980 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_mac_core[][2] = { +/* Addr allmodes */ + { 0x00000008 , 0x00000000 }, + { 0x00000030 , 0x000e0085 }, + { 0x00000034 , 0x00000005 }, + { 0x00000040 , 0x00000000 }, + { 0x00000044 , 0x00000000 }, + { 0x00000048 , 0x00000008 }, + { 0x0000004c , 0x00000010 }, + { 0x00000050 , 0x00000000 }, + { 0x00001040 , 0x002ffc0f }, + { 0x00001044 , 0x002ffc0f }, + { 0x00001048 , 0x002ffc0f }, + { 0x0000104c , 0x002ffc0f }, + { 0x00001050 , 0x002ffc0f }, + { 0x00001054 , 0x002ffc0f }, + { 0x00001058 , 0x002ffc0f }, + { 0x0000105c , 0x002ffc0f }, + { 0x00001060 , 0x002ffc0f }, + { 0x00001064 , 0x002ffc0f }, + { 0x000010f0 , 0x00000100 }, + { 0x00001270 , 0x00000000 }, + { 0x000012b0 , 0x00000000 }, + { 0x000012f0 , 0x00000000 }, + { 0x0000143c , 0x00000000 }, + { 0x0000147c , 0x00000000 }, + { 0x00001810 , 0x0f000003 }, + { 0x00008000 , 0x00000000 }, + { 0x00008004 , 0x00000000 }, + { 0x00008008 , 0x00000000 }, + { 0x0000800c , 0x00000000 }, + { 0x00008018 , 0x00000000 }, + { 0x00008020 , 0x00000000 }, + { 0x00008038 , 0x00000000 }, + { 0x0000803c , 0x00080000 }, + { 0x00008040 , 0x00000000 }, + { 0x00008044 , 0x00000000 }, + { 0x00008048 , 0x00000000 }, + { 0x0000804c , 0xffffffff }, + { 0x00008050 , 0xffffffff }, + { 0x00008054 , 0x00000000 }, + { 0x00008058 , 0x00000000 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008060 , 0x0000000f }, + { 0x00008064 , 0x00000000 }, + { 0x00008070 , 0x00000310 }, + { 0x00008074 , 0x00000020 }, + { 0x00008078 , 0x00000000 }, + { 0x0000809c , 0x0000000f }, + { 0x000080a0 , 0x00000000 }, + { 0x000080a4 , 0x02ff0000 }, + { 0x000080a8 , 0x0e070605 }, + { 0x000080ac , 0x0000000d }, + { 0x000080b0 , 0x00000000 }, + { 0x000080b4 , 0x00000000 }, + { 0x000080b8 , 0x00000000 }, + { 0x000080bc , 0x00000000 }, + { 0x000080c0 , 0x2a800000 }, + { 0x000080c4 , 0x06900168 }, + { 0x000080c8 , 0x13881c20 }, + { 0x000080cc , 0x01f40000 }, + { 0x000080d0 , 0x00252500 }, + { 0x000080d4 , 0x00b00005 }, + { 0x000080d8 , 0x00400002 }, + { 0x000080dc , 0x00000000 }, + { 0x000080e0 , 0xffffffff }, + { 0x000080e4 , 0x0000ffff }, + { 0x000080e8 , 0x3f3f3f3f }, + { 0x000080ec , 0x00000000 }, + { 0x000080f0 , 0x00000000 }, + { 0x000080f4 , 0x00000000 }, + { 0x000080fc , 0x00020000 }, + { 0x00008100 , 0x00000000 }, + { 0x00008108 , 0x00000052 }, + { 0x0000810c , 0x00000000 }, + { 0x00008110 , 0x00000000 }, + { 0x00008114 , 0x000007ff }, + { 0x00008118 , 0x000000aa }, + { 0x0000811c , 0x00003210 }, + { 0x00008124 , 0x00000000 }, + { 0x00008128 , 0x00000000 }, + { 0x0000812c , 0x00000000 }, + { 0x00008130 , 0x00000000 }, + { 0x00008134 , 0x00000000 }, + { 0x00008138 , 0x00000000 }, + { 0x0000813c , 0x0000ffff }, + { 0x00008144 , 0xffffffff }, + { 0x00008168 , 0x00000000 }, + { 0x0000816c , 0x00000000 }, + { 0x00008170 , 0x18486e00 }, + { 0x00008174 , 0x33332210 }, + { 0x00008178 , 0x00000000 }, + { 0x0000817c , 0x00020000 }, + { 0x000081c4 , 0x33332210 }, + { 0x000081c8 , 0x00000000 }, + { 0x000081cc , 0x00000000 }, + { 0x000081d4 , 0x00000000 }, + { 0x000081ec , 0x00000000 }, + { 0x000081f0 , 0x00000000 }, + { 0x000081f4 , 0x00000000 }, + { 0x000081f8 , 0x00000000 }, + { 0x000081fc , 0x00000000 }, + { 0x00008240 , 0x00100000 }, + { 0x00008244 , 0x0010f400 }, + { 0x00008248 , 0x00000800 }, + { 0x0000824c , 0x0001e800 }, + { 0x00008250 , 0x00000000 }, + { 0x00008254 , 0x00000000 }, + { 0x00008258 , 0x00000000 }, + { 0x0000825c , 0x40000000 }, + { 0x00008260 , 0x00080922 }, + { 0x00008264 , 0x99c00010 }, + { 0x00008268 , 0xffffffff }, + { 0x0000826c , 0x0000ffff }, + { 0x00008270 , 0x00000000 }, + { 0x00008274 , 0x40000000 }, + { 0x00008278 , 0x003e4180 }, + { 0x0000827c , 0x00000004 }, + { 0x00008284 , 0x0000002c }, + { 0x00008288 , 0x0000002c }, + { 0x0000828c , 0x000000ff }, + { 0x00008294 , 0x00000000 }, + { 0x00008298 , 0x00000000 }, + { 0x0000829c , 0x00000000 }, + { 0x00008300 , 0x00000140 }, + { 0x00008314 , 0x00000000 }, + { 0x0000831c , 0x0000010d }, + { 0x00008328 , 0x00000000 }, + { 0x0000832c , 0x0000001f }, + { 0x00008330 , 0x00000302 }, + { 0x00008334 , 0x00000700 }, + { 0x00008338 , 0xffff0000 }, + { 0x0000833c , 0x02400000 }, + { 0x00008340 , 0x000107ff }, + { 0x00008344 , 0xaa48105b }, + { 0x00008348 , 0x008f0000 }, + { 0x0000835c , 0x00000000 }, + { 0x00008360 , 0xffffffff }, + { 0x00008364 , 0xffffffff }, + { 0x00008368 , 0x00000000 }, + { 0x00008370 , 0x00000000 }, + { 0x00008374 , 0x000000ff }, + { 0x00008378 , 0x00000000 }, + { 0x0000837c , 0x00000000 }, + { 0x00008380 , 0xffffffff }, + { 0x00008384 , 0xffffffff }, + { 0x00008390 , 0xffffffff }, + { 0x00008394 , 0xffffffff }, + { 0x00008398 , 0x00000000 }, + { 0x0000839c , 0x00000000 }, + { 0x000083a4 , 0x0000fa14 }, + { 0x000083a8 , 0x000f0c00 }, + { 0x000083ac , 0x33332210 }, + { 0x000083b0 , 0x33332210 }, + { 0x000083b4 , 0x33332210 }, + { 0x000083b8 , 0x33332210 }, + { 0x000083bc , 0x00000000 }, + { 0x000083c0 , 0x00000000 }, + { 0x000083c4 , 0x00000000 }, + { 0x000083c8 , 0x00000000 }, + { 0x000083cc , 0x00000200 }, + { 0x000083d0 , 0x000301ff }, +}; + +static const u_int32_t ar9300_jupiter_2p0_mac_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, +}; + +static const u_int32_t ar9300Common_mixed_rx_gain_table_jupiter_2p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x03820190 }, + { 0x0000a030 , 0x03840383 }, + { 0x0000a034 , 0x03880385 }, + { 0x0000a038 , 0x038a0389 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x29292929 }, + { 0x0000a084 , 0x29292929 }, + { 0x0000a088 , 0x29292929 }, + { 0x0000a08c , 0x29292929 }, + { 0x0000a090 , 0x22292929 }, + { 0x0000a094 , 0x1d1d2222 }, + { 0x0000a098 , 0x0c111117 }, + { 0x0000a09c , 0x00030303 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x2a2d2f32 }, + { 0x0000b084 , 0x21232328 }, + { 0x0000b088 , 0x19191c1e }, + { 0x0000b08c , 0x12141417 }, + { 0x0000b090 , 0x07070e0e }, + { 0x0000b094 , 0x03030305 }, + { 0x0000b098 , 0x00000003 }, + { 0x0000b09c , 0x00000000 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar9300Modes_green_ob_db_tx_gain_table_jupiter_2p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000003 , 0x00000003 , 0x00000003 , 0x00000003 }, + { 0x0000a2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a458 , 0x80000000 , 0x80000000 , 0x80000000 , 0x80000000 }, + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06002223 , 0x06002223 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a022220 , 0x0a022220 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x0f022223 , 0x0f022223 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x14022620 , 0x14022620 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x18022622 , 0x18022622 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x1b022822 , 0x1b022822 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x20022842 , 0x20022842 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x22022c41 , 0x22022c41 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x28023042 , 0x28023042 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x2c023044 , 0x2c023044 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x2f023644 , 0x2f023644 , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x34025643 , 0x34025643 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x38025a44 , 0x38025a44 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x3b025e45 , 0x3b025e45 , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x41025e4a , 0x41025e4a , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x48025e6c , 0x48025e6c , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x4e025e8e , 0x4e025e8e , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x53025eb2 , 0x53025eb2 , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x59025eb6 , 0x59025eb6 , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x5d025ef6 , 0x5d025ef6 , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x62025f56 , 0x62025f56 , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x66027f56 , 0x66027f56 , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x6a029f56 , 0x6a029f56 , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x70049f56 , 0x70049f56 , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x7504ff56 , 0x7504ff56 , 0x56001eec , 0x56001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00804000 , 0x00804000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x00804201 , 0x00804201 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x0280c802 , 0x0280c802 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x0280ca03 , 0x0280ca03 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x04c15104 , 0x04c15104 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04c15305 , 0x04c15305 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04c15305 , 0x04c15305 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 }, + { 0x00016048 , 0x8db49060 , 0x8db49060 , 0x8db49060 , 0x8db49060 }, + { 0x00016054 , 0x6db60180 , 0x6db60180 , 0x6db60180 , 0x6db60180 }, + { 0x00016444 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 , 0x056d82e4 }, + { 0x00016448 , 0x8db49000 , 0x8db49000 , 0x8db49000 , 0x8db49000 }, + { 0x00016454 , 0x6db60180 , 0x6db60180 , 0x6db60180 , 0x6db60180 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table[][2] = { +/* Addr allmodes */ + { 0x000018c0 , 0x10101010 }, + { 0x000018c4 , 0x10101010 }, + { 0x000018c8 , 0x10101010 }, + { 0x000018cc , 0x10101010 }, + { 0x000018d0 , 0x10101010 }, + { 0x000018d4 , 0x10101010 }, + { 0x000018d8 , 0x10101010 }, + { 0x000018dc , 0x10101010 }, +}; + +static const u_int32_t ar9300_jupiter_2p0_baseband_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafa68e30 }, + { 0x00009884 , 0x00002842 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009e50 , 0x00000000 }, + { 0x00009fcc , 0x00000014 }, + { 0x0000a344 , 0x00000010 }, + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x71733d01 }, + { 0x0000a3a0 , 0xd0ad5c12 }, + { 0x0000a3c0 , 0x22222220 }, + { 0x0000a3c4 , 0x22222222 }, + { 0x0000a404 , 0x00418a11 }, + { 0x0000a418 , 0x050001ce }, + { 0x0000a438 , 0x00001800 }, + { 0x0000a458 , 0x01444452 }, + { 0x0000a644 , 0x3fad9d74 }, + { 0x0000a690 , 0x00000038 }, +}; + diff --git a/hal/ar9300/ar9300_keycache.c b/hal/ar9300/ar9300_keycache.c new file mode 100644 index 000000000000..e4b454f6381c --- /dev/null +++ b/hal/ar9300/ar9300_keycache.c @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" + +/* + * Note: The key cache hardware requires that each double-word + * pair be written in even/odd order (since the destination is + * a 64-bit register). Don't reorder the writes in this code + * w/o considering this! + */ +#define KEY_XOR 0xaa + +#define IS_MIC_ENABLED(ah) \ + (AH9300(ah)->ah_sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE) + +/* + * Return the size of the hardware key cache. + */ +u_int32_t +ar9300_get_key_cache_size(struct ath_hal *ah) +{ + return AH_PRIVATE(ah)->ah_caps.hal_key_cache_size; +} + +/* + * Return AH_TRUE if the specific key cache entry is valid. + */ +HAL_BOOL +ar9300_is_key_cache_entry_valid(struct ath_hal *ah, u_int16_t entry) +{ + if (entry < AH_PRIVATE(ah)->ah_caps.hal_key_cache_size) { + u_int32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); + if (val & AR_KEYTABLE_VALID) { + return AH_TRUE; + } + } + return AH_FALSE; +} + +/* + * Clear the specified key cache entry and any associated MIC entry. + */ +HAL_BOOL +ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry) +{ + u_int32_t key_type; + struct ath_hal_9300 *ahp = AH9300(ah); + + if (entry >= AH_PRIVATE(ah)->ah_caps.hal_key_cache_size) { + HALDEBUG(ah, HAL_DEBUG_KEYCACHE, + "%s: entry %u out of range\n", __func__, entry); + return AH_FALSE; + } + key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); + + /* XXX why not clear key type/valid bit first? */ + OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); + OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); + if (key_type == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) { + u_int16_t micentry = entry + 64; /* MIC goes at slot+64 */ + + HALASSERT(micentry < AH_PRIVATE(ah)->ah_caps.hal_key_cache_size); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); + /* NB: key type and MAC are known to be ok */ + } + + if (AH_PRIVATE(ah)->ah_curchan == AH_NULL) { + return AH_TRUE; + } + + if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) + == HAL_OK) { + if (key_type == AR_KEYTABLE_TYPE_TKIP || + key_type == AR_KEYTABLE_TYPE_40 || + key_type == AR_KEYTABLE_TYPE_104 || + key_type == AR_KEYTABLE_TYPE_128) { + /* SW WAR for Bug 31602 */ + if (--ahp->ah_rifs_sec_cnt == 0) { + HALDEBUG(ah, HAL_DEBUG_KEYCACHE, + "%s: Count = %d, enabling RIFS\n", + __func__, ahp->ah_rifs_sec_cnt); + ar9300_set_rifs_delay(ah, AH_TRUE); + } + } + } + return AH_TRUE; +} + +/* + * Sets the mac part of the specified key cache entry (and any + * associated MIC entry) and mark them valid. + */ +HAL_BOOL +ar9300_set_key_cache_entry_mac( + struct ath_hal *ah, + u_int16_t entry, + const u_int8_t *mac) +{ + u_int32_t mac_hi, mac_lo; + u_int32_t unicast_addr = AR_KEYTABLE_VALID; + + if (entry >= AH_PRIVATE(ah)->ah_caps.hal_key_cache_size) { + HALDEBUG(ah, HAL_DEBUG_KEYCACHE, + "%s: entry %u out of range\n", __func__, entry); + return AH_FALSE; + } + /* + * Set MAC address -- shifted right by 1. mac_lo is + * the 4 MSBs, and mac_hi is the 2 LSBs. + */ + if (mac != AH_NULL) { + /* + * If upper layers have requested mcast MACaddr lookup, then + * signify this to the hw by setting the (poorly named) valid_bit + * to 0. Yes, really 0. The hardware specs, pcu_registers.txt, is + * has incorrectly named valid_bit. It should be called "Unicast". + * When the Key Cache entry is to decrypt Unicast frames, this bit + * should be '1'; for multicast and broadcast frames, this bit is '0'. + */ + if (mac[0] & 0x01) { + unicast_addr = 0; /* Not an unicast address */ + } + + mac_hi = (mac[5] << 8) | mac[4]; + mac_lo = (mac[3] << 24) | (mac[2] << 16) + | (mac[1] << 8) | mac[0]; + mac_lo >>= 1; /* Note that the bit 0 is shifted out. This bit is used to + * indicate that this is a multicast key cache. */ + mac_lo |= (mac_hi & 1) << 31; /* carry */ + mac_hi >>= 1; + } else { + mac_lo = mac_hi = 0; + } + OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), mac_lo); + OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), mac_hi | unicast_addr); + return AH_TRUE; +} + +/* + * Sets the contents of the specified key cache entry + * and any associated MIC entry. + */ +HAL_BOOL +ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry, + const HAL_KEYVAL *k, const u_int8_t *mac, + int xor_key) +{ + const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + u_int32_t key0, key1, key2, key3, key4; + u_int32_t key_type; + u_int32_t xor_mask = xor_key ? + (KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0; + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t pwrmgt, pwrmgt_mic, uapsd_cfg, psta = 0; + int is_proxysta_key = k->kv_type & HAL_KEY_PROXY_STA_MASK; + + + if (entry >= p_cap->hal_key_cache_size) { + HALDEBUG(ah, HAL_DEBUG_KEYCACHE, + "%s: entry %u out of range\n", __func__, entry); + return AH_FALSE; + } + HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s[%d] mac %s proxy %d\n", + __func__, __LINE__, mac ? ath_hal_ether_sprintf(mac) : "null", + is_proxysta_key); + + switch (k->kv_type & AH_KEYTYPE_MASK) { + case HAL_CIPHER_AES_OCB: + key_type = AR_KEYTABLE_TYPE_AES; + break; + case HAL_CIPHER_AES_CCM: + if (!p_cap->hal_cipher_aes_ccm_support) { + HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s: AES-CCM not supported by " + "mac rev 0x%x\n", + __func__, AH_PRIVATE(ah)->ah_macRev); + return AH_FALSE; + } + key_type = AR_KEYTABLE_TYPE_CCM; + break; + case HAL_CIPHER_TKIP: + key_type = AR_KEYTABLE_TYPE_TKIP; + if (IS_MIC_ENABLED(ah) && entry + 64 >= p_cap->hal_key_cache_size) { + HALDEBUG(ah, HAL_DEBUG_KEYCACHE, + "%s: entry %u inappropriate for TKIP\n", + __func__, entry); + return AH_FALSE; + } + break; + case HAL_CIPHER_WEP: + if (k->kv_len < 40 / NBBY) { + HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s: WEP key length %u too small\n", + __func__, k->kv_len); + return AH_FALSE; + } + if (k->kv_len <= 40 / NBBY) { + key_type = AR_KEYTABLE_TYPE_40; + } else if (k->kv_len <= 104 / NBBY) { + key_type = AR_KEYTABLE_TYPE_104; + } else { + key_type = AR_KEYTABLE_TYPE_128; + } + break; + case HAL_CIPHER_CLR: + key_type = AR_KEYTABLE_TYPE_CLR; + break; + default: + HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s: cipher %u not supported\n", + __func__, k->kv_type); + return AH_FALSE; + } + + key0 = LE_READ_4(k->kv_val + 0) ^ xor_mask; + key1 = (LE_READ_2(k->kv_val + 4) ^ xor_mask) & 0xffff; + key2 = LE_READ_4(k->kv_val + 6) ^ xor_mask; + key3 = (LE_READ_2(k->kv_val + 10) ^ xor_mask) & 0xffff; + key4 = LE_READ_4(k->kv_val + 12) ^ xor_mask; + if (k->kv_len <= 104 / NBBY) { + key4 &= 0xff; + } + + /* Extract the UAPSD AC bits and shift it appropriately */ + uapsd_cfg = k->kv_apsd; + uapsd_cfg = (u_int32_t) SM(uapsd_cfg, AR_KEYTABLE_UAPSD); + + /* Need to preserve the power management bit used by MAC */ + pwrmgt = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)) & AR_KEYTABLE_PWRMGT; + + if (is_proxysta_key) { + u_int8_t bcast_mac[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + if (!mac || adf_os_mem_cmp(mac, bcast_mac, 6)) { + psta = AR_KEYTABLE_DIR_ACK_BIT; + } + } + /* + * Note: key cache hardware requires that each double-word + * pair be written in even/odd order (since the destination is + * a 64-bit register). Don't reorder these writes w/o + * considering this! + */ + if (key_type == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) { + u_int16_t micentry = entry + 64; /* MIC goes at slot+64 */ + + /* Need to preserve the power management bit used by MAC */ + pwrmgt_mic = + OS_REG_READ(ah, AR_KEYTABLE_TYPE(micentry)) & AR_KEYTABLE_PWRMGT; + + /* + * Invalidate the encrypt/decrypt key until the MIC + * key is installed so pending rx frames will fail + * with decrypt errors rather than a MIC error. + */ + OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); + OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), + key_type | pwrmgt | uapsd_cfg | psta); + ar9300_set_key_cache_entry_mac(ah, entry, mac); + + /* + * since the AR_MISC_MODE register was written with the contents of + * ah_misc_mode (if any) in ar9300_attach, just check ah_misc_mode and + * save a pci read per key set. + */ + if (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { + u_int32_t mic0, mic1, mic2, mic3, mic4; + /* + * both RX and TX mic values can be combined into + * one cache slot entry. + * 8*N + 800 31:0 RX Michael key 0 + * 8*N + 804 15:0 TX Michael key 0 [31:16] + * 8*N + 808 31:0 RX Michael key 1 + * 8*N + 80C 15:0 TX Michael key 0 [15:0] + * 8*N + 810 31:0 TX Michael key 1 + * 8*N + 814 15:0 reserved + * 8*N + 818 31:0 reserved + * 8*N + 81C 14:0 reserved + * 15 key valid == 0 + */ + /* RX mic */ + mic0 = LE_READ_4(k->kv_mic + 0); + mic2 = LE_READ_4(k->kv_mic + 4); + /* TX mic */ + mic1 = LE_READ_2(k->kv_txmic + 2) & 0xffff; + mic3 = LE_READ_2(k->kv_txmic + 0) & 0xffff; + mic4 = LE_READ_4(k->kv_txmic + 4); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); + OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), + AR_KEYTABLE_TYPE_CLR | pwrmgt_mic | uapsd_cfg); + + } else { + u_int32_t mic0, mic2; + + mic0 = LE_READ_4(k->kv_mic + 0); + mic2 = LE_READ_4(k->kv_mic + 4); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); + OS_REG_WRITE(ah, + AR_KEYTABLE_TYPE(micentry | pwrmgt_mic | uapsd_cfg), + AR_KEYTABLE_TYPE_CLR); + } + /* NB: MIC key is not marked valid and has no MAC address */ + OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); + OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); + + /* correct intentionally corrupted key */ + OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); + } else { + OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); + OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); + OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), + key_type | pwrmgt | uapsd_cfg | psta); + + /* + ath_hal_printf(ah, "%s[%d] mac %s proxy %d\n", + __func__, __LINE__, mac ? ath_hal_ether_sprintf(mac) : "null", + is_proxysta_key); + */ + + ar9300_set_key_cache_entry_mac(ah, entry, mac); + } + + if (AH_PRIVATE(ah)->ah_curchan == AH_NULL) { + return AH_TRUE; + } + + if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) + == HAL_OK) { + if (key_type == AR_KEYTABLE_TYPE_TKIP || + key_type == AR_KEYTABLE_TYPE_40 || + key_type == AR_KEYTABLE_TYPE_104 || + key_type == AR_KEYTABLE_TYPE_128) { + /* SW WAR for Bug 31602 */ + ahp->ah_rifs_sec_cnt++; + HALDEBUG(ah, HAL_DEBUG_KEYCACHE, + "%s: Count = %d, disabling RIFS\n", + __func__, ahp->ah_rifs_sec_cnt); + ar9300_set_rifs_delay(ah, AH_FALSE); + } + } + HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s[%d] mac %s proxy %d\n", + __func__, __LINE__, mac ? ath_hal_ether_sprintf(mac) : "null", + is_proxysta_key); + + return AH_TRUE; +} + +/* + * Enable the Keysearch for every subframe of an aggregate + */ +void +ar9300_enable_keysearch_always(struct ath_hal *ah, int enable) +{ + u_int32_t val; + + if (!ah) { + return; + } + val = OS_REG_READ(ah, AR_PCU_MISC); + if (enable) { + val |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; + } else { + val &= ~AR_PCU_ALWAYS_PERFORM_KEYSEARCH; + } + OS_REG_WRITE(ah, AR_PCU_MISC, val); +} +void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry) +{ +#define AH_KEY_REG_SIZE 8 + int i; + + for (i = 0; i < AH_KEY_REG_SIZE; i++) { + entry[i] = OS_REG_READ(ah, AR_KEYTABLE_KEY0(n) + i * 4); + } +#undef AH_KEY_REG_SIZE +} + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_mci.c b/hal/ar9300/ar9300_mci.c new file mode 100644 index 000000000000..811d701be49f --- /dev/null +++ b/hal/ar9300/ar9300_mci.c @@ -0,0 +1,1892 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300phy.h" + +#if ATH_SUPPORT_MCI + +#define AH_MCI_REMOTE_RESET_INTERVAL_US 500 +#define AH_MCI_DEBUG_PRINT_SCHED 0 + +static void ar9300_mci_print_msg(struct ath_hal *ah, HAL_BOOL send,u_int8_t hdr, + int len, u_int32_t *pl) +{ +#if DBG + char s[128]; + char *p = s; + int i; + u_int8_t *p_data = (u_int8_t *) pl; + + if (send) { + p += snprintf(s, 60, + "(MCI) >>>>> Hdr: %02X, Len: %d, Payload:", hdr, len); + } + else { + p += snprintf(s, 60, + "(MCI) <<<<< Hdr: %02X, Len: %d, Payload:", hdr, len); + } + for ( i=0; iah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_DISABLE_AGGR_THRESH)) + { + thresh = MS(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config, + ATH_MCI_CONFIG_AGGR_THRESH); + OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, + AR_BTCOEX_CTRL_AGGR_THRESH, thresh); + OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, + AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 1); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) SCHED aggr thresh: on, thresh=%d (%d.%d%%)\n", + thresh, (thresh + 1)*125/10, (thresh + 1)*125%10); + + } + else { + OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, + AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 0); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) SCHED aggr thresh: off\n"); + } + OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, + AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN, 1); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) SCHED one step look ahead: on\n"); + } + else { + OS_REG_CLR_BIT(ah, AR_BTCOEX_CTRL, + AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) SCHED one step look ahead: off\n"); + } +} + +static void ar9300_mci_reset_req_wakeup(struct ath_hal *ah) +{ + /* to be tested in emulation */ + if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_RMW_FIELD(ah, AR_MCI_COMMAND2, + AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 1); + OS_DELAY(1); + OS_REG_RMW_FIELD(ah, AR_MCI_COMMAND2, + AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 0); + } +} + +static int32_t ar9300_mci_wait_for_interrupt(struct ath_hal *ah, + u_int32_t address, + u_int32_t bit_position, + int32_t time_out) +{ + int data, loop; + + while (time_out) { + data = OS_REG_READ(ah, address); + + if (data & bit_position) { + OS_REG_WRITE(ah, address, bit_position); + if (address == AR_MCI_INTERRUPT_RX_MSG_RAW) { + if (bit_position & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) { + ar9300_mci_reset_req_wakeup(ah); + } + if (bit_position & (AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | + AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING)) + { + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, + AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE); + } + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG); + } + break; + } + + OS_DELAY(10); + time_out -= 10; + if (time_out < 0) { + break; + } + } + + if (time_out <= 0) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Wait for Reg0x%08x = 0x%08x timeout.\n", + __func__, address, bit_position); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) INT_RAW = 0x%08x, RX_MSG_RAW = 0x%08x", + OS_REG_READ(ah, AR_MCI_INTERRUPT_RAW), + OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); + time_out = 0; + } + return time_out; +} + +void ar9300_mci_remote_reset(struct ath_hal *ah, HAL_BOOL wait_done) +{ + u_int32_t payload[4] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffff00}; + + ar9300_mci_send_message(ah, MCI_REMOTE_RESET, 0, payload, 16, + wait_done, AH_FALSE); + + OS_DELAY(5); +} + +void ar9300_mci_send_lna_transfer(struct ath_hal *ah, HAL_BOOL wait_done) +{ + u_int32_t payload = 0x00000000; + + ar9300_mci_send_message(ah, MCI_LNA_TRANS, 0, &payload, 1, + wait_done, AH_FALSE); +} + +static void ar9300_mci_send_req_wake(struct ath_hal *ah, HAL_BOOL wait_done) +{ + ar9300_mci_send_message(ah, MCI_REQ_WAKE, + HAL_MCI_FLAG_DISABLE_TIMESTAMP, AH_NULL, 0, wait_done, AH_FALSE); + + OS_DELAY(5); +} + +void ar9300_mci_send_sys_waking(struct ath_hal *ah, HAL_BOOL wait_done) +{ + ar9300_mci_send_message(ah, MCI_SYS_WAKING, + HAL_MCI_FLAG_DISABLE_TIMESTAMP, AH_NULL, 0, wait_done, AH_FALSE); +} + +static void ar9300_mci_send_lna_take(struct ath_hal *ah, HAL_BOOL wait_done) +{ + u_int32_t payload = 0x70000000; + + /* LNA gain index is set to 7. */ + ar9300_mci_send_message(ah, MCI_LNA_TAKE, + HAL_MCI_FLAG_DISABLE_TIMESTAMP, &payload, 1, wait_done, AH_FALSE); +} + +static void ar9300_mci_send_sys_sleeping(struct ath_hal *ah, HAL_BOOL wait_done) +{ + ar9300_mci_send_message(ah, MCI_SYS_SLEEPING, + HAL_MCI_FLAG_DISABLE_TIMESTAMP, AH_NULL, 0, wait_done, AH_FALSE); +} + +static void +ar9300_mci_send_coex_version_query(struct ath_hal *ah, HAL_BOOL wait_done) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t payload[4] = {0, 0, 0, 0}; + + if ((ahp->ah_mci_coex_bt_version_known == AH_FALSE) && + (ahp->ah_mci_bt_state != MCI_BT_SLEEP)) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send Coex version query.\n"); + MCI_GPM_SET_TYPE_OPCODE(payload, + MCI_GPM_COEX_AGENT, MCI_GPM_COEX_VERSION_QUERY); + ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE); + } +} + +static void +ar9300_mci_send_coex_version_response(struct ath_hal *ah, HAL_BOOL wait_done) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t payload[4] = {0, 0, 0, 0}; + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send Coex version response.\n"); + MCI_GPM_SET_TYPE_OPCODE(payload, + MCI_GPM_COEX_AGENT, MCI_GPM_COEX_VERSION_RESPONSE); + *(((u_int8_t *)payload) + MCI_GPM_COEX_B_MAJOR_VERSION) = + ahp->ah_mci_coex_major_version_wlan; + *(((u_int8_t *)payload) + MCI_GPM_COEX_B_MINOR_VERSION) = + ahp->ah_mci_coex_minor_version_wlan; + ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE); +} + +static void +ar9300_mci_send_coex_wlan_channels(struct ath_hal *ah, HAL_BOOL wait_done) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t *payload = &ahp->ah_mci_coex_wlan_channels[0]; + + if ((ahp->ah_mci_coex_wlan_channels_update == AH_TRUE) && + (ahp->ah_mci_bt_state != MCI_BT_SLEEP)) + { + MCI_GPM_SET_TYPE_OPCODE(payload, + MCI_GPM_COEX_AGENT, MCI_GPM_COEX_WLAN_CHANNELS); + ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE); + MCI_GPM_SET_TYPE_OPCODE(payload, 0xff, 0xff); + } +} + +static void ar9300_mci_send_coex_bt_status_query(struct ath_hal *ah, + HAL_BOOL wait_done, u_int8_t query_type) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t pld[4] = {0, 0, 0, 0}; + HAL_BOOL query_btinfo = query_type & + (MCI_GPM_COEX_QUERY_BT_ALL_INFO | MCI_GPM_COEX_QUERY_BT_TOPOLOGY); + + if (ahp->ah_mci_bt_state != MCI_BT_SLEEP) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Send Coex BT Status Query 0x%02X\n", query_type); + MCI_GPM_SET_TYPE_OPCODE(pld, + MCI_GPM_COEX_AGENT, MCI_GPM_COEX_STATUS_QUERY); + *(((u_int8_t *)pld) + MCI_GPM_COEX_B_BT_BITMAP) = query_type; + /* + * If bt_status_query message is thought not sent successfully, + * then ah_mci_need_flush_btinfo should be set again. + */ + if (!ar9300_mci_send_message(ah, MCI_GPM, 0, pld, 16, wait_done, AH_TRUE)) + { + if (query_btinfo) { + ahp->ah_mci_need_flush_btinfo = AH_TRUE; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) send bt_status_query fail, set flush flag again\n"); + } + } + if (query_btinfo) { + ahp->ah_mci_query_bt = AH_FALSE; + } + } +} + +void ar9300_mci_send_coex_halt_bt_gpm(struct ath_hal *ah, + HAL_BOOL halt, HAL_BOOL wait_done) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t payload[4] = {0, 0, 0, 0}; + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Send Coex %s BT GPM.\n", (halt == AH_TRUE)?"HALT":"UNHALT"); + + MCI_GPM_SET_TYPE_OPCODE(payload, + MCI_GPM_COEX_AGENT, MCI_GPM_COEX_HALT_BT_GPM); + if (halt == AH_TRUE) { + ahp->ah_mci_query_bt = AH_TRUE; + /* Send next UNHALT no matter HALT sent or not */ + ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; + ahp->ah_mci_need_flush_btinfo = AH_TRUE; + *(((u_int8_t *)payload) + MCI_GPM_COEX_B_HALT_STATE) = + MCI_GPM_COEX_BT_GPM_HALT; + } + else { + *(((u_int8_t *)payload) + MCI_GPM_COEX_B_HALT_STATE) = + MCI_GPM_COEX_BT_GPM_UNHALT; + } + ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE); +} + +static HAL_BOOL ar9300_mci_send_coex_bt_flags(struct ath_hal *ah, HAL_BOOL wait_done, + u_int8_t opcode, u_int32_t bt_flags) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t pld[4] = {0, 0, 0, 0}; + + MCI_GPM_SET_TYPE_OPCODE(pld, + MCI_GPM_COEX_AGENT, MCI_GPM_COEX_BT_UPDATE_FLAGS); + + *(((u_int8_t *)pld) + MCI_GPM_COEX_B_BT_FLAGS_OP) = opcode; + *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 0) = bt_flags & 0xFF; + *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 1) = + (bt_flags >> 8) & 0xFF; + *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 2) = + (bt_flags >> 16) & 0xFF; + *(((u_int8_t *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 3) = + (bt_flags >> 24) & 0xFF; + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) BT_MCI_FLAGS: Send Coex BT Update Flags %s 0x%08x\n", + (opcode == MCI_GPM_COEX_BT_FLAGS_READ)?"READ": + ((opcode == MCI_GPM_COEX_BT_FLAGS_SET)?"SET":"CLEAR"), + bt_flags); + + return ar9300_mci_send_message(ah, MCI_GPM, 0, pld, 16, wait_done, AH_TRUE); +} + +void ar9300_mci_2g5g_changed(struct ath_hal *ah, HAL_BOOL is_2g) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + if (ahp->ah_mci_coex_2g5g_update == AH_FALSE) { + if (ahp->ah_mci_coex_is_2g == is_2g) { + //HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) BT_MCI_FLAGS: not changed\n"); + } else { + ahp->ah_mci_coex_2g5g_update = AH_TRUE; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) BT_MCI_FLAGS: changed\n"); + } + } else { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) BT_MCI_FLAGS: force send\n"); + } + ahp->ah_mci_coex_is_2g = is_2g; +} + +static void ar9300_mci_send_2g5g_status(struct ath_hal *ah, HAL_BOOL wait_done) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t new_flags, to_set, to_clear; + + if ((AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) && + (ahp->ah_mci_coex_2g5g_update == AH_TRUE) && + (ahp->ah_mci_bt_state != MCI_BT_SLEEP)) + { + if (ahp->ah_mci_coex_is_2g) { + new_flags = HAL_MCI_2G_FLAGS; + to_clear = HAL_MCI_2G_FLAGS_CLEAR_MASK; + to_set = HAL_MCI_2G_FLAGS_SET_MASK; + } else { + new_flags = HAL_MCI_5G_FLAGS; + to_clear = HAL_MCI_5G_FLAGS_CLEAR_MASK; + to_set = HAL_MCI_5G_FLAGS_SET_MASK; + } + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) BT_MCI_FLAGS: %s (0x%08x) clr=0x%08x, set=0x%08x\n", + ahp->ah_mci_coex_is_2g?"2G":"5G", new_flags, to_clear, to_set); + if (to_clear) { + ar9300_mci_send_coex_bt_flags(ah, wait_done, + MCI_GPM_COEX_BT_FLAGS_CLEAR, to_clear); + } + if (to_set) { + ar9300_mci_send_coex_bt_flags(ah, wait_done, + MCI_GPM_COEX_BT_FLAGS_SET, to_set); + } + } + if (AR_SREV_JUPITER_10(ah) && (ahp->ah_mci_bt_state != MCI_BT_SLEEP)) { + ahp->ah_mci_coex_2g5g_update = AH_FALSE; + } +} + +void ar9300_mci_2g5g_switch(struct ath_hal *ah, HAL_BOOL wait_done) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + if (ahp->ah_mci_coex_2g5g_update) + { + if (ahp->ah_mci_coex_is_2g) { + ar9300_mci_send_2g5g_status(ah, AH_TRUE); + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send LNA trans\n"); + ar9300_mci_send_lna_transfer(ah, AH_TRUE); + OS_DELAY(5); + + OS_REG_CLR_BIT(ah, AR_MCI_TX_CTRL, + AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); + if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_CLR_BIT(ah, AR_GLB_CONTROL, + AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); + if (!(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_DISABLE_OSLA)) + { + ar9300_mci_osla_setup(ah, AH_TRUE); + } + } + } else { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send LNA take\n"); + ar9300_mci_send_lna_take(ah, AH_TRUE); + OS_DELAY(5); + + OS_REG_SET_BIT(ah, AR_MCI_TX_CTRL, + AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); + if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_SET_BIT(ah, AR_GLB_CONTROL, + AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); + ar9300_mci_osla_setup(ah, AH_FALSE); + } + + ar9300_mci_send_2g5g_status(ah, AH_TRUE); + } + } + + /* + * Update self gen chain mask. Also set basic set for + * txbf. + */ + if (AR_SREV_JUPITER(ah)) { + if (ahp->ah_mci_coex_is_2g) { + ahp->ah_reduced_self_gen_mask = AH_TRUE; + OS_REG_WRITE(ah, AR_SELFGEN_MASK, 0x02); + ar9300_txbf_set_basic_set(ah); + } + else { + ahp->ah_reduced_self_gen_mask = AH_FALSE; + ar9300_txbf_set_basic_set(ah); + } + } +} + +void ar9300_mci_mute_bt(struct ath_hal *ah) +{ + /* disable all MCI messages */ + OS_REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xFFFF0000); + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xFFFFFFFF); + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xFFFFFFFF); + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xFFFFFFFF); + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xFFFFFFFF); + OS_REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); + /* wait pending HW messages to flush out */ + OS_DELAY(10); + + /* + * Send LNA_TAKE and SYS_SLEEPING when + * 1. reset not after resuming from full sleep + * 2. before reset MCI RX, to quiet BT and avoid MCI RX misalignment + */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send LNA take\n"); + ar9300_mci_send_lna_take(ah, AH_TRUE); + OS_DELAY(5); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send sys sleeping\n"); + ar9300_mci_send_sys_sleeping(ah, AH_TRUE); +} + +static void ar9300_mci_observation_set_up(struct ath_hal *ah) +{ + /* + * Set up the observation bus in order to monitor MCI bus + * through GPIOs (0, 1, 2, and 3). + */ + /* + OS_REG_WRITE(ah, AR_GPIO_INTR_POL, 0x00420000); + OS_REG_WRITE(ah, AR_GPIO_OE_OUT, 0x000000ff); // 4050 + OS_REG_WRITE(ah, AR_GPIO_OUTPUT_MUX1, 0x000bdab4); // 4068 + OS_REG_WRITE(ah, AR_OBS, 0x0000004b); // 4088 + OS_REG_WRITE(ah, AR_DIAG_SW, 0x080c0000); + OS_REG_WRITE(ah, AR_MACMISC, 0x0001a000); + OS_REG_WRITE(ah, AR_PHY_TEST, 0x00080000); // a360 + OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, 0xe0000000); // a364 + */ + + if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_MCI_OBS_MCI) + { + ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA); + ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK); + ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA); + ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK); + } + else if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_MCI_OBS_TXRX) + { + ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX); + ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX); + ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX); + ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX); + ar9300_gpio_cfg_output(ah, 5, HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); + } + else if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_MCI_OBS_BT) + { + ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX); + ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX); + ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA); + ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK); + } + else { + return; + } + + OS_REG_SET_BIT(ah, + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE); + + if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_RMW_FIELD(ah, AR_GLB_CONTROL, AR_GLB_DS_JTAG_DISABLE, 1); + OS_REG_RMW_FIELD(ah, AR_GLB_CONTROL, AR_GLB_WLAN_UART_INTF_EN, 0); + OS_REG_WRITE(ah, AR_GLB_GPIO_CONTROL, + (OS_REG_READ(ah, AR_GLB_GPIO_CONTROL) | + ATH_MCI_CONFIG_MCI_OBS_GPIO)); + } + + OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_GPIO_OBS_SEL, 0); + OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL, 1); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 0x4b); + OS_REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL1, 0x03); + OS_REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL2, 0x01); + OS_REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_LSB, 0x02); + OS_REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_MSB, 0x03); + //OS_REG_RMW_FIELD(ah, AR_PHY_TEST, AR_PHY_TEST_BBB_OBS_SEL, 0x01); + OS_REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS, + AR_PHY_TEST_CTL_DEBUGPORT_SEL, 0x07); +} + +static void ar9300_mci_process_gpm_extra(struct ath_hal *ah, + u_int8_t gpm_type, u_int8_t gpm_opcode, u_int32_t *p_gpm) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int8_t *p_data = (u_int8_t *) p_gpm; + + switch (gpm_type) + { + case MCI_GPM_COEX_AGENT: + switch (gpm_opcode) + { + case MCI_GPM_COEX_VERSION_QUERY: + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Recv GPM COEX Version Query.\n"); + ar9300_mci_send_coex_version_response(ah, AH_TRUE); + break; + + case MCI_GPM_COEX_VERSION_RESPONSE: + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Recv GPM COEX Version Response.\n"); + ahp->ah_mci_coex_major_version_bt = + *(p_data + MCI_GPM_COEX_B_MAJOR_VERSION); + ahp->ah_mci_coex_minor_version_bt = + *(p_data + MCI_GPM_COEX_B_MINOR_VERSION); + ahp->ah_mci_coex_bt_version_known = AH_TRUE; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) BT Coex version: %d.%d\n", + ahp->ah_mci_coex_major_version_bt, + ahp->ah_mci_coex_minor_version_bt); + break; + + case MCI_GPM_COEX_STATUS_QUERY: + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Recv GPM COEX Status Query = 0x%02X.\n", + *(p_data + MCI_GPM_COEX_B_WLAN_BITMAP)); + //if ((*(p_data + MCI_GPM_COEX_B_WLAN_BITMAP)) & + // MCI_GPM_COEX_QUERY_WLAN_ALL_INFO) + { + ahp->ah_mci_coex_wlan_channels_update = AH_TRUE; + ar9300_mci_send_coex_wlan_channels(ah, AH_TRUE); + } + break; + + case MCI_GPM_COEX_BT_PROFILE_INFO: + ahp->ah_mci_query_bt = AH_TRUE; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Recv GPM COEX BT_Profile_Info (drop&query)\n"); + break; + + case MCI_GPM_COEX_BT_STATUS_UPDATE: + ahp->ah_mci_query_bt = AH_TRUE; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Recv GPM COEX BT_Status_Update " + "SEQ=%d (drop&query)\n", + *(p_gpm + 3)); + break; + + default: + break; + } + default: + break; + } +} + +u_int32_t ar9300_mci_wait_for_gpm(struct ath_hal *ah, u_int8_t gpm_type, + u_int8_t gpm_opcode, int32_t time_out) +{ + u_int32_t *p_gpm = NULL, mismatch = 0, more_data = HAL_MCI_GPM_NOMORE; + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL b_is_bt_cal_done = (gpm_type == MCI_GPM_BT_CAL_DONE); + u_int32_t offset; + u_int8_t recv_type = 0, recv_opcode = 0; + + if (time_out == 0) { + more_data = HAL_MCI_GPM_MORE; + } + + while (time_out > 0) + { + if (p_gpm != NULL) { + MCI_GPM_RECYCLE(p_gpm); + p_gpm = NULL; + } + + if (more_data != HAL_MCI_GPM_MORE) { + time_out = ar9300_mci_wait_for_interrupt(ah, + AR_MCI_INTERRUPT_RX_MSG_RAW, + AR_MCI_INTERRUPT_RX_MSG_GPM, + time_out); + } + + if (time_out) { + offset = ar9300_mci_state(ah, + HAL_MCI_STATE_NEXT_GPM_OFFSET, &more_data); + + if (offset == HAL_MCI_GPM_INVALID) { + continue; + } + p_gpm = (u_int32_t *) (ahp->ah_mci_gpm_buf + offset); + ar9300_mci_print_msg(ah, AH_FALSE, MCI_GPM, 16, p_gpm); + + recv_type = MCI_GPM_TYPE(p_gpm); + recv_opcode = MCI_GPM_OPCODE(p_gpm); + + if (MCI_GPM_IS_CAL_TYPE(recv_type)) { + if (recv_type == gpm_type) { + if ((gpm_type == MCI_GPM_BT_CAL_DONE) && !b_is_bt_cal_done) + { + gpm_type = MCI_GPM_BT_CAL_GRANT; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Rcv BT_CAL_DONE. Now Wait BT_CAL_GRANT\n"); + continue; + } + if (gpm_type == MCI_GPM_BT_CAL_GRANT) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) BT_CAL_GRANT seq=%d, req_count=%d\n", + *(p_gpm + 2), *(p_gpm + 3)); + } + break; + } + } + else { + if ((recv_type == gpm_type) && (recv_opcode == gpm_opcode)) { + break; + } + } + + /* not expected message */ + + /* + * Check if it's cal_grant + * + * When we're waiting for cal_grant in reset routine, it's + * possible that BT sends out cal_request at the same time. + * Since BT's calibration doesn't happen that often, we'll + * let BT completes calibration then we continue to wait + * for cal_grant from BT. + * Orginal: Wait BT_CAL_GRANT. + * New: Receive BT_CAL_REQ -> send WLAN_CAL_GRANT -> wait + * BT_CAL_DONE -> Wait BT_CAL_GRANT. + */ + if ((gpm_type == MCI_GPM_BT_CAL_GRANT) && + (recv_type == MCI_GPM_BT_CAL_REQ)) + { + u_int32_t payload[4] = {0, 0, 0, 0}; + + gpm_type = MCI_GPM_BT_CAL_DONE; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Rcv BT_CAL_REQ. Send WLAN_CAL_GRANT.\n"); + + MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT); + ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, + AH_FALSE, AH_FALSE); + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Now wait for BT_CAL_DONE.\n"); + continue; + } + else { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) GPM subtype not match 0x%x\n", *(p_gpm + 1)); + mismatch++; + ar9300_mci_process_gpm_extra(ah, recv_type, recv_opcode, p_gpm); + } + } + } + if (p_gpm != NULL) { + MCI_GPM_RECYCLE(p_gpm); + p_gpm = NULL; + } + + if (time_out <= 0) { + time_out = 0; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) GPM receiving timeout, mismatch = %d\n", mismatch); + } else { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Receive GPM type=0x%x, code=0x%x\n", gpm_type, gpm_opcode); + } + + while (more_data == HAL_MCI_GPM_MORE) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) discard remaining GPM\n"); + offset = ar9300_mci_state(ah, + HAL_MCI_STATE_NEXT_GPM_OFFSET, &more_data); + + if (offset == HAL_MCI_GPM_INVALID) { + break; + } + p_gpm = (u_int32_t *) (ahp->ah_mci_gpm_buf + offset); + ar9300_mci_print_msg(ah, AH_FALSE, MCI_GPM, 16, p_gpm); + recv_type = MCI_GPM_TYPE(p_gpm); + recv_opcode = MCI_GPM_OPCODE(p_gpm); + if (!MCI_GPM_IS_CAL_TYPE(recv_type)) { + ar9300_mci_process_gpm_extra(ah, recv_type, recv_opcode, p_gpm); + } + MCI_GPM_RECYCLE(p_gpm); + } + + return time_out; +} + +static void ar9300_mci_prep_interface(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t saved_mci_int_en; + u_int32_t mci_timeout = 150; + + ahp->ah_mci_bt_state = MCI_BT_SLEEP; + + saved_mci_int_en = OS_REG_READ(ah, AR_MCI_INTERRUPT_EN); + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); + + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, + OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, + OS_REG_READ(ah, AR_MCI_INTERRUPT_RAW)); + + /* Remote Reset */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Reset sequence start\n", __func__); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) send REMOTE_RESET\n"); + ar9300_mci_remote_reset(ah, AH_TRUE); + + /* + * This delay is required for the reset delay worst case value 255 in + * MCI_COMMAND2 register + */ + if (AR_SREV_JUPITER_10(ah)) { + OS_DELAY(252); + } + + /* Send REQ_WAKE to BT */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send REQ_WAKE to remote(BT)\n", + __func__); + + ar9300_mci_send_req_wake(ah, AH_TRUE); + + if (ar9300_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, + AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING, 500)) + { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Saw SYS_WAKING from remote(BT)\n", __func__); + ahp->ah_mci_bt_state = MCI_BT_AWAKE; + + if (AR_SREV_JUPITER_10(ah)) { + OS_DELAY(10); + } + /* + * We don't need to send more remote_reset at this moment. + * + * If BT receive first remote_reset, then BT HW will be cleaned up and + * will be able to receive req_wake and BT HW will respond sys_waking. + * In this case, WLAN will receive BT's HW sys_waking. + * + * Otherwise, if BT SW missed initial remote_reset, that remote_reset + * will still clean up BT MCI RX, and the req_wake will wake BT up, + * and BT SW will respond this req_wake with a remote_reset and + * sys_waking. In this case, WLAN will receive BT's SW sys_waking. + * + * In either case, BT's RX is cleaned up. So we don't need to reply + * BT's remote_reset now, if any. + * + * Similarly, if in any case, WLAN can receive BT's sys_waking, that + * means WLAN's RX is also fine. + */ + + /* Send SYS_WAKING to BT */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Send SW SYS_WAKING to remot(BT)\n", __func__); + ar9300_mci_send_sys_waking(ah, AH_TRUE); + + OS_DELAY(10); + + /* + * Set BT priority interrupt value to be 0xff to + * avoid having too many BT PRIORITY interrupts. + */ + + OS_REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF); + OS_REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF); + OS_REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF); + OS_REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF); + OS_REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF); + + /* + * A contention reset will be received after send out sys_waking. + * Also BT priority interrupt bits will be set. Clear those bits + * before the next step. + */ + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, + AR_MCI_INTERRUPT_RX_MSG_CONT_RST); + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_BT_PRI); + + if (AR_SREV_JUPITER_10(ah) || ahp->ah_mci_coex_is_2g) { + /* Send LNA_TRANS */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send LNA_TRANS to BT\n", + __func__); + ar9300_mci_send_lna_transfer(ah, AH_TRUE); + + OS_DELAY(5); + } + + if (AR_SREV_JUPITER_10(ah) || + (ahp->ah_mci_coex_is_2g && !ahp->ah_mci_coex_2g5g_update)) + { + if (ar9300_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, + AR_MCI_INTERRUPT_RX_MSG_LNA_INFO, mci_timeout)) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: WLAN has control over the LNA & BT obeys it\n", + __func__); + } else { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: BT did not respond to LNA_TRANS!\n", __func__); + //ahp->ah_mci_bt_state = MCI_BT_SLEEP; + } + } + + if (AR_SREV_JUPITER_10(ah)) { + /* Send another remote_reset to deassert BT clk_req. */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Another remote_reset to deassert clk_req.\n", + __func__); + ar9300_mci_remote_reset(ah, AH_TRUE); + OS_DELAY(252); + } + } + + /* Clear the extra redundant SYS_WAKING from BT */ + if ((ahp->ah_mci_bt_state == MCI_BT_AWAKE) && + (OS_REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, + AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING)) && + (OS_REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, + AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) == 0)) + { + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, + AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING); + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, + AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE); + } + + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en); +} + +void ar9300_mci_setup(struct ath_hal *ah, u_int32_t gpm_addr, + void *gpm_buf, u_int16_t len, + u_int32_t sched_addr) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + void *sched_buf = (void *)((char *) gpm_buf + (sched_addr - gpm_addr)); + + ahp->ah_mci_gpm_addr = gpm_addr; + ahp->ah_mci_gpm_buf = gpm_buf; + ahp->ah_mci_gpm_len = len; + ahp->ah_mci_sched_addr = sched_addr; + ahp->ah_mci_sched_buf = sched_buf; + + ar9300_mci_reset(ah, AH_TRUE, AH_TRUE, AH_TRUE); +} + +void ar9300_mci_disable_interrupt(struct ath_hal *ah) +{ + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); +} + +void ar9300_mci_enable_interrupt(struct ath_hal *ah) +{ + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT); + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, + AR_MCI_INTERRUPT_RX_MSG_DEFAULT); +} + +void ar9300_mci_reset(struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g, + HAL_BOOL is_full_sleep) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + u_int32_t regval; + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: full_sleep = %d, is_2g = %d\n", + __func__, is_full_sleep, is_2g); + + if (!ahp->ah_mci_gpm_addr && !ahp->ah_mci_sched_addr) { + /* GPM buffer and scheduling message buffer are not allocated */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) GPM and SCHEDULE buffers not allocated\n"); + return; + } + + if (OS_REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: ### It's deadbeef, quit mcireset()\n", __func__); + return; + } + + /* Program MCI DMA related registers */ + OS_REG_WRITE(ah, AR_MCI_GPM_0, ahp->ah_mci_gpm_addr); + OS_REG_WRITE(ah, AR_MCI_GPM_1, ahp->ah_mci_gpm_len); + OS_REG_WRITE(ah, AR_MCI_SCHD_TABLE_0, ahp->ah_mci_sched_addr); + + /* + * To avoid MCI state machine be affected by incoming remote MCI messages, + * MCI mode will be enabled later, right before reset the MCI TX and RX. + */ + regval = SM(1, AR_BTCOEX_CTRL_JUPITER_MODE) | + SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | + SM(1, AR_BTCOEX_CTRL_PA_SHARED) | + SM(1, AR_BTCOEX_CTRL_LNA_SHARED) | + SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) | + SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK) | + SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) | + SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) | + SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); + + if (AR_SREV_JUPITER_10(ah)) { + regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10); + } + + OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval); + + if (is_2g && (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) && + !(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_DISABLE_OSLA)) + { + ar9300_mci_osla_setup(ah, AH_TRUE); + } + else { + ar9300_mci_osla_setup(ah, AH_FALSE); + } + + if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_SET_BIT(ah, AR_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE); + + OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3, + AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT, 20); + } + + OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 0); + + OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); + + if (ahpriv->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_CONCUR_TX) { + u_int8_t i; + u_int32_t const *pmax_tx_pwr; + + if ((ahpriv->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN) + { + ahp->ah_mci_concur_tx_en = (ahp->ah_bt_coex_flag & + HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR) ? AH_TRUE : AH_FALSE; + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n", + ahp->ah_mci_concur_tx_en); + /* + * We're not relying on HW to reduce WLAN tx power. + * Set the max tx power table to 0x7f for all. + */ +#if 0 + if (AH_PRIVATE(ah)->ah_curchan) { + chan_flags = AH_PRIVATE(ah)->ah_curchan->channel_flags; + } + if (chan_flags == CHANNEL_G_HT20) { + pmax_tx_pwr = &mci_concur_tx_max_pwr[2][0]; + } + else if (chan_flags == CHANNEL_G) { + pmax_tx_pwr = &mci_concur_tx_max_pwr[1][0]; + } + else if ((chan_flags == CHANNEL_G_HT40PLUS) || + (chan_flags == CHANNEL_G_HT40MINUS)) + { + pmax_tx_pwr = &mci_concur_tx_max_pwr[3][0]; + } + else { + pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0]; + } + + if (ahp->ah_mci_concur_tx_en) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) chan flags = 0x%x, max_tx_pwr = %d dBm\n", + chan_flags, + (MS(pmax_tx_pwr[2], + ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK) >> 1)); + } +#else + pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0]; +#endif + } + else if ((ahpriv->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_UNSHARED_CHN) + { + pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0]; + ahp->ah_mci_concur_tx_en = AH_TRUE; + } + else { + pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0]; + ahp->ah_mci_concur_tx_en = AH_TRUE; + } + + /* Default is using rate based TPC. */ + OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, + AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE, 0); + OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, + AR_BTCOEX_CTRL2_TXPWR_THRESH, 0x7f); + OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, + AR_BTCOEX_CTRL_REDUCE_TXPWR, 0); + for (i = 0; i < 8; i++) { + OS_REG_WRITE(ah, AR_BTCOEX_MAX_TXPWR(i), pmax_tx_pwr[i]); + } + } + + regval = MS(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config, + ATH_MCI_CONFIG_CLK_DIV); + OS_REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval); + + OS_REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN); + + /* Resetting the Rx and Tx paths of MCI */ + regval = OS_REG_READ(ah, AR_MCI_COMMAND2); + regval |= SM(1, AR_MCI_COMMAND2_RESET_TX); + OS_REG_WRITE(ah, AR_MCI_COMMAND2, regval); + OS_DELAY(1); + regval &= ~SM(1, AR_MCI_COMMAND2_RESET_TX); + OS_REG_WRITE(ah, AR_MCI_COMMAND2, regval); + + if (is_full_sleep) { + ar9300_mci_mute_bt(ah); + OS_DELAY(100); + } + + regval |= SM(1, AR_MCI_COMMAND2_RESET_RX); + OS_REG_WRITE(ah, AR_MCI_COMMAND2, regval); + OS_DELAY(1); + regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX); + OS_REG_WRITE(ah, AR_MCI_COMMAND2, regval); + + ar9300_mci_state(ah, HAL_MCI_STATE_INIT_GPM_OFFSET, NULL); + OS_REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, + (SM(0xe801, AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR) | + SM(0x0000, AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM))); + OS_REG_CLR_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); + + if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { + ar9300_mci_observation_set_up(ah); + } + + ahp->ah_mci_ready = AH_TRUE; + ar9300_mci_prep_interface(ah); + + if (en_int) { + ar9300_mci_enable_interrupt(ah); + } + +#if ATH_SUPPORT_AIC + if (ahp->ah_aic_enabled) { + ar9300_aic_start_normal(ah); + } +#endif +} + +static void ar9300_mci_queue_unsent_gpm(struct ath_hal *ah, u_int8_t header, + u_int32_t *payload, HAL_BOOL queue) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int8_t type, opcode; + + if (queue == AH_TRUE) { + if (payload != NULL) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) ERROR: Send fail: %02x: %02x %02x %02x\n", + header, + *(((u_int8_t *)payload) + 4), + *(((u_int8_t *)payload) + 5), + *(((u_int8_t *)payload) + 6)); + } else { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) ERROR: Send fail: %02x\n", header); + } + } + /* check if the message is to be queued */ + if (header == MCI_GPM) { + type = MCI_GPM_TYPE(payload); + opcode = MCI_GPM_OPCODE(payload); + + if (type == MCI_GPM_COEX_AGENT) { + switch (opcode) + { + case MCI_GPM_COEX_BT_UPDATE_FLAGS: + if (AR_SREV_JUPITER_10(ah)) { + break; + } + if (*(((u_int8_t *)payload) + MCI_GPM_COEX_B_BT_FLAGS_OP) == + MCI_GPM_COEX_BT_FLAGS_READ) + { + break; + } + ahp->ah_mci_coex_2g5g_update = queue; + if (queue == AH_TRUE) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) BT_MCI_FLAGS: 2G5G status %s.\n", + ahp->ah_mci_coex_is_2g?"2G":"5G"); + } + else { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) BT_MCI_FLAGS: 2G5G status %s.\n", + ahp->ah_mci_coex_is_2g?"2G":"5G"); + } + break; + + case MCI_GPM_COEX_WLAN_CHANNELS: + ahp->ah_mci_coex_wlan_channels_update = queue; + if (queue == AH_TRUE) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) WLAN channel map .\n"); + } + else { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) WLAN channel map .\n"); + } + break; + + case MCI_GPM_COEX_HALT_BT_GPM: + if (*(((u_int8_t *)payload) + MCI_GPM_COEX_B_HALT_STATE) == + MCI_GPM_COEX_BT_GPM_UNHALT) + { + ahp->ah_mci_unhalt_bt_gpm = queue; + if (queue == AH_TRUE) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) UNHALT BT GPM .\n"); + } + else { + ahp->ah_mci_halted_bt_gpm = AH_FALSE; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) UNHALT BT GPM .\n"); + } + } + if (*(((u_int8_t *)payload) + MCI_GPM_COEX_B_HALT_STATE) == + MCI_GPM_COEX_BT_GPM_HALT) + { + ahp->ah_mci_halted_bt_gpm = !queue; + if (queue == AH_TRUE) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) HALT BT GPM .\n"); + } + else { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) HALT BT GPM .\n"); + } + } + break; + + default: + break; + } + } + } +} + +HAL_BOOL ar9300_mci_send_message(struct ath_hal *ah, u_int8_t header, + u_int32_t flag, u_int32_t *payload, + u_int8_t len, HAL_BOOL wait_done, HAL_BOOL check_bt) +{ + int i; + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL msg_sent = AH_FALSE; + u_int32_t regval; + u_int32_t saved_mci_int_en = OS_REG_READ(ah, AR_MCI_INTERRUPT_EN); + + regval = OS_REG_READ(ah, AR_BTCOEX_CTRL); + if ((regval == 0xdeadbeef) || !(regval & AR_BTCOEX_CTRL_MCI_MODE_EN)) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Not send 0x%x. MCI is not enabled. full_sleep = %d\n", + __func__, header, ahp->ah_chip_full_sleep); + ar9300_mci_queue_unsent_gpm(ah, header, payload, AH_TRUE); + return AH_FALSE; + } + else if (check_bt && (ahp->ah_mci_bt_state == MCI_BT_SLEEP)) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Don't send message(0x%x). BT is in sleep state\n", + __func__, header); + ar9300_mci_queue_unsent_gpm(ah, header, payload, AH_TRUE); + return AH_FALSE; + } + + if (wait_done) { + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); + } + + /* Need to clear SW_MSG_DONE raw bit before wait */ + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, + AR_MCI_INTERRUPT_SW_MSG_DONE | AR_MCI_INTERRUPT_MSG_FAIL_MASK); + + if (payload != AH_NULL) { + for (i = 0; (i*4) < len; i++) { + OS_REG_WRITE(ah, (AR_MCI_TX_PAYLOAD0 + i*4), *(payload + i)); + } + } + ar9300_mci_print_msg(ah, AH_TRUE, header, len, payload); + + OS_REG_WRITE(ah, AR_MCI_COMMAND0, + (SM((flag & HAL_MCI_FLAG_DISABLE_TIMESTAMP), + AR_MCI_COMMAND0_DISABLE_TIMESTAMP) | + SM(len, AR_MCI_COMMAND0_LEN) | + SM(header, AR_MCI_COMMAND0_HEADER))); + + if (wait_done && + ar9300_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RAW, + AR_MCI_INTERRUPT_SW_MSG_DONE, 500) == 0) + { + ar9300_mci_queue_unsent_gpm(ah, header, payload, AH_TRUE); + } + else { + ar9300_mci_queue_unsent_gpm(ah, header, payload, AH_FALSE); + msg_sent = AH_TRUE; + } + + if (wait_done) { + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en); + } + + return msg_sent; +} + +u_int32_t ar9300_mci_get_interrupt(struct ath_hal *ah, u_int32_t *mci_int, + u_int32_t *mci_int_rx_msg) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + *mci_int = ahp->ah_mci_int_raw; + *mci_int_rx_msg = ahp->ah_mci_int_rx_msg; + + /* Clean int bits after the values are read. */ + ahp->ah_mci_int_raw = 0; + ahp->ah_mci_int_rx_msg = 0; + + return 0; +} + +u_int32_t ar9300_mci_check_int(struct ath_hal *ah, u_int32_t ints) +{ + u_int32_t reg; + + reg = OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); + return ((reg & ints) == ints); +} + +void ar9300_mci_sync_bt_state(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t cur_bt_state; + + cur_bt_state = ar9300_mci_state(ah, HAL_MCI_STATE_REMOTE_SLEEP, NULL); + if (ahp->ah_mci_bt_state != cur_bt_state) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: BT state mismatches. old: %d, new: %d\n", + __func__, ahp->ah_mci_bt_state, cur_bt_state); + ahp->ah_mci_bt_state = cur_bt_state; + } + if (ahp->ah_mci_bt_state != MCI_BT_SLEEP) { +#if MCI_QUERY_BT_VERSION_VERBOSE + ar9300_mci_send_coex_version_query(ah, AH_TRUE); +#endif + ar9300_mci_send_coex_wlan_channels(ah, AH_TRUE); + if (ahp->ah_mci_unhalt_bt_gpm == AH_TRUE) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: UNHALT BT GPM\n", __func__); + ar9300_mci_send_coex_halt_bt_gpm(ah, AH_FALSE, AH_TRUE); + } + } +} + +static HAL_BOOL ar9300_mci_is_gpm_valid(struct ath_hal *ah, u_int32_t msg_index) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t *payload; + u_int32_t recv_type, offset = msg_index << 4; + + if (msg_index == HAL_MCI_GPM_INVALID) { + return AH_FALSE; + } + + payload = (u_int32_t *) (ahp->ah_mci_gpm_buf + offset); + recv_type = MCI_GPM_TYPE(payload); + + if (recv_type == MCI_GPM_RSVD_PATTERN) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Skip RSVD GPM\n"); + return AH_FALSE; + } + + return AH_TRUE; +} + +u_int32_t +ar9300_mci_state(struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data) +{ + u_int32_t value = 0, more_gpm = 0, gpm_ptr; + struct ath_hal_9300 *ahp = AH9300(ah); + + switch (state_type) { + case HAL_MCI_STATE_ENABLE: + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && ahp->ah_mci_ready) { + value = OS_REG_READ(ah, AR_BTCOEX_CTRL); + if ((value == 0xdeadbeef) || (value == 0xffffffff)) { + // HALDEBUG(ah, HAL_DEBUG_BT_COEX, + // "(MCI) BTCOEX_CTRL = 0xdeadbeef\n"); + value = 0; + } + } + value &= AR_BTCOEX_CTRL_MCI_MODE_EN; + break; + + case HAL_MCI_STATE_INIT_GPM_OFFSET: + value = MS(OS_REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: GPM initial WRITE_PTR=%d.\n", __func__, value); + ahp->ah_mci_gpm_idx = value; + break; + + case HAL_MCI_STATE_NEXT_GPM_OFFSET: + case HAL_MCI_STATE_LAST_GPM_OFFSET: + /* + * This could be useful to avoid new GPM message interrupt which + * may lead to spurious interrupt after power sleep, or multiple + * entry of ath_coex_mci_intr(). + * Adding empty GPM check by returning HAL_MCI_GPM_INVALID can + * alleviate this effect, but clearing GPM RX interrupt bit is + * safe, because whether this is called from HAL or LMAC, there + * must be an interrupt bit set/triggered initially. + */ + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, + AR_MCI_INTERRUPT_RX_MSG_GPM); + + gpm_ptr = MS(OS_REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); + value = gpm_ptr; + + if (value == 0) { + value = ahp->ah_mci_gpm_len - 1; + } + else if (value >= ahp->ah_mci_gpm_len) { + if (value != 0xFFFF) { + value = 0; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: GPM offset out of range.\n", __func__); + } + } + else { + value--; + } + + if (value == 0xFFFF) { + value = HAL_MCI_GPM_INVALID; + more_gpm = HAL_MCI_GPM_NOMORE; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: GPM ptr invalid " + "@ptr=%d, @offset=%d, more=NOMORE.\n", + __func__, gpm_ptr, value); + } + else if (state_type == HAL_MCI_STATE_NEXT_GPM_OFFSET) { + if (gpm_ptr == ahp->ah_mci_gpm_idx) { + value = HAL_MCI_GPM_INVALID; + more_gpm = HAL_MCI_GPM_NOMORE; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: GPM message not available " + "@ptr=%d, @offset=%d, more=NOMORE.\n", + __func__, gpm_ptr, value); + } + else { + while (1) { + u_int32_t temp_index; + + /* skip reserved GPM if any */ + if (value != ahp->ah_mci_gpm_idx) { + more_gpm = HAL_MCI_GPM_MORE; + } + else { + more_gpm = HAL_MCI_GPM_NOMORE; + } + temp_index = ahp->ah_mci_gpm_idx; + ahp->ah_mci_gpm_idx++; + if (ahp->ah_mci_gpm_idx >= ahp->ah_mci_gpm_len) { + ahp->ah_mci_gpm_idx = 0; + } + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: GPM message got " + "@ptr=%d, @offset=%d, more=%s.\n", + __func__, gpm_ptr, temp_index, + (more_gpm == HAL_MCI_GPM_MORE)?"MORE":"NOMORE"); + if (ar9300_mci_is_gpm_valid(ah, temp_index)) { + value = temp_index; + break; + } + if (more_gpm == HAL_MCI_GPM_NOMORE) { + value = HAL_MCI_GPM_INVALID; + break; + } + } + } + if (p_data != NULL) { + *p_data = more_gpm; + } + } + if (value != HAL_MCI_GPM_INVALID) { + value <<= 4; + } + break; + + case HAL_MCI_STATE_LAST_SCHD_MSG_OFFSET: + value = MS(OS_REG_READ(ah, AR_MCI_RX_STATUS), + AR_MCI_RX_LAST_SCHD_MSG_INDEX); + +#if AH_MCI_DEBUG_PRINT_SCHED + { + u_int32_t index = value; + u_int32_t prev_index, sched_idx; + u_int32_t *pld; + u_int8_t *pld8; + u_int32_t wbtimer = OS_REG_READ(ah, AR_BTCOEX_WBTIMER); + u_int32_t schd_ctl = OS_REG_READ(ah, AR_MCI_HW_SCHD_TBL_CTL); + + if (index > 0) { + prev_index = index - 1; + } else { + prev_index = index; + } + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) SCHED\n"); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) SCHED SCHD_TBL_CTRL=0x%08x, WBTIMER=0x%08x (%d)\n", + schd_ctl, wbtimer, wbtimer); + for (sched_idx = prev_index; sched_idx <= index; sched_idx++) { + pld = (u_int32_t *) (ahp->ah_mci_sched_buf + (sched_idx << 4)); + pld8 = (u_int8_t *) pld; + + ar9300_mci_print_msg(ah, AH_FALSE, MCI_SCHD_INFO, 16, pld); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) SCHED idx=%d, T1=0x%08x (%d), T2=0x%08x (%d)\n", + sched_idx, + pld[0], pld[0], pld[1], pld[1]); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) SCHED addr=%d %s pwr=%d prio=%d %s link=%d\n", + pld8[11] >> 4, + (pld8[11] & 0x08)?"TX":"RX", + (int8_t) (((pld8[11] & 0x07) << 5) | (pld8[10] >> 3)), + (((pld8[10] & 0x07) << 5) | (pld8[9] >> 3)), + (pld8[9] & 0x04)?"LE":"BR/EDR", + (((pld8[9] & 0x03) << 2) | (pld8[8] >> 6))); + } + } +#endif /* AH_MCI_DEBUG_PRINT_SCHED */ + + /* Make it in bytes */ + value <<= 4; + break; + + case HAL_MCI_STATE_REMOTE_SLEEP: + value = MS(OS_REG_READ(ah, AR_MCI_RX_STATUS), + AR_MCI_RX_REMOTE_SLEEP) ? MCI_BT_SLEEP : MCI_BT_AWAKE; + break; + + case HAL_MCI_STATE_CONT_RSSI_POWER: + value = MS(ahp->ah_mci_cont_status, + AR_MCI_CONT_RSSI_POWER); + break; + + case HAL_MCI_STATE_CONT_PRIORITY: + value = MS(ahp->ah_mci_cont_status, + AR_MCI_CONT_RRIORITY); + break; + + case HAL_MCI_STATE_CONT_TXRX: + value = MS(ahp->ah_mci_cont_status, + AR_MCI_CONT_TXRX); + break; + + case HAL_MCI_STATE_BT: + value = ahp->ah_mci_bt_state; + break; + + case HAL_MCI_STATE_SET_BT_SLEEP: + ahp->ah_mci_bt_state = MCI_BT_SLEEP; + break; + + case HAL_MCI_STATE_SET_BT_AWAKE: + ahp->ah_mci_bt_state = MCI_BT_AWAKE; + ar9300_mci_send_coex_version_query(ah, AH_TRUE); + ar9300_mci_send_coex_wlan_channels(ah, AH_TRUE); + if (ahp->ah_mci_unhalt_bt_gpm == AH_TRUE) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: UNHALT BT GPM\n", __func__); + ar9300_mci_send_coex_halt_bt_gpm(ah, AH_FALSE, AH_TRUE); + } + ar9300_mci_2g5g_switch(ah, AH_TRUE); + break; + + case HAL_MCI_STATE_SET_BT_CAL_START: + ahp->ah_mci_bt_state = MCI_BT_CAL_START; + break; + + case HAL_MCI_STATE_SET_BT_CAL: + ahp->ah_mci_bt_state = MCI_BT_CAL; + break; + + case HAL_MCI_STATE_RESET_REQ_WAKE: + ar9300_mci_reset_req_wakeup(ah); + ahp->ah_mci_coex_2g5g_update = AH_TRUE; + + if ((AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) && + (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_MCI_OBS_MASK)) + { + /* Check if we still have control of the GPIOs */ + if ((OS_REG_READ(ah, AR_GLB_GPIO_CONTROL) & + ATH_MCI_CONFIG_MCI_OBS_GPIO) != + ATH_MCI_CONFIG_MCI_OBS_GPIO) + { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Reconfigure observation\n"); + ar9300_mci_observation_set_up(ah); + } + } + + break; + + case HAL_MCI_STATE_SEND_WLAN_COEX_VERSION: + ar9300_mci_send_coex_version_response(ah, AH_TRUE); + break; + + case HAL_MCI_STATE_SET_BT_COEX_VERSION: + if (p_data == NULL) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Error: Set BT Coex version with NULL data !!!\n"); + } + else { + ahp->ah_mci_coex_major_version_bt = (*p_data >> 8) & 0xff; + ahp->ah_mci_coex_minor_version_bt = (*p_data) & 0xff; + ahp->ah_mci_coex_bt_version_known = AH_TRUE; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) BT version set: %d.%d\n", + ahp->ah_mci_coex_major_version_bt, + ahp->ah_mci_coex_minor_version_bt); + } + break; + + case HAL_MCI_STATE_SEND_WLAN_CHANNELS: + if (p_data != NULL) + { + if (((ahp->ah_mci_coex_wlan_channels[1] & 0xffff0000) == + (*(p_data + 1) & 0xffff0000)) && + (ahp->ah_mci_coex_wlan_channels[2] == *(p_data + 2)) && + (ahp->ah_mci_coex_wlan_channels[3] == *(p_data + 3))) + { + break; + } + ahp->ah_mci_coex_wlan_channels[0] = *p_data++; + ahp->ah_mci_coex_wlan_channels[1] = *p_data++; + ahp->ah_mci_coex_wlan_channels[2] = *p_data++; + ahp->ah_mci_coex_wlan_channels[3] = *p_data++; + } + ahp->ah_mci_coex_wlan_channels_update = AH_TRUE; + ar9300_mci_send_coex_wlan_channels(ah, AH_TRUE); + break; + + case HAL_MCI_STATE_SEND_VERSION_QUERY: + ar9300_mci_send_coex_version_query(ah, AH_TRUE); + break; + + case HAL_MCI_STATE_SEND_STATUS_QUERY: + if (AR_SREV_JUPITER_10(ah)) { + ar9300_mci_send_coex_bt_status_query(ah, AH_TRUE, + MCI_GPM_COEX_QUERY_BT_ALL_INFO); + } else { + ar9300_mci_send_coex_bt_status_query(ah, AH_TRUE, + MCI_GPM_COEX_QUERY_BT_TOPOLOGY); + } + break; + + case HAL_MCI_STATE_NEED_FLUSH_BT_INFO: + /* + * ah_mci_unhalt_bt_gpm means whether it's needed to send + * UNHALT message. It's set whenever there's a request to send HALT + * message. ah_mci_halted_bt_gpm means whether HALT message is sent + * out successfully. + * + * Checking (ah_mci_unhalt_bt_gpm == AH_FALSE) instead of checking + * (ahp->ah_mci_halted_bt_gpm == AH_FALSE) will make sure currently is + * in UNHALT-ed mode and BT can respond to status query. + */ + if ((ahp->ah_mci_unhalt_bt_gpm == AH_FALSE) && + (ahp->ah_mci_need_flush_btinfo == AH_TRUE)) + { + value = 1; + } + else { + value = 0; + } + if (p_data != NULL) { + ahp->ah_mci_need_flush_btinfo = (*p_data != 0)?true:false; + } + break; + + case HAL_MCI_STATE_SET_CONCUR_TX_PRI: + if (p_data) { + ahp->ah_mci_stomp_none_tx_pri = *p_data & 0xff; + ahp->ah_mci_stomp_low_tx_pri = (*p_data >> 8) & 0xff; + ahp->ah_mci_stomp_all_tx_pri = (*p_data >> 16) & 0xff; + } + break; + + case HAL_MCI_STATE_RECOVER_RX: + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) hal RECOVER_RX\n"); + ar9300_mci_prep_interface(ah); + ahp->ah_mci_query_bt = AH_TRUE; + ahp->ah_mci_need_flush_btinfo = AH_TRUE; + ar9300_mci_send_coex_wlan_channels(ah, AH_TRUE); + ar9300_mci_2g5g_switch(ah, AH_TRUE); + break; + + case HAL_MCI_STATE_DEBUG: + if (p_data != NULL) { + if (*p_data == HAL_MCI_STATE_DEBUG_REQ_BT_DEBUG) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) QUERY_BT_DEBUG\n"); + ar9300_mci_send_coex_bt_status_query(ah, AH_TRUE, + MCI_GPM_COEX_QUERY_BT_DEBUG); + OS_DELAY(10); + if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) { + ar9300_mci_send_coex_bt_flags(ah, AH_TRUE, + MCI_GPM_COEX_BT_FLAGS_READ, 0); + } + } + } + break; + + case HAL_MCI_STATE_NEED_FTP_STOMP: + value = (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_DISABLE_FTP_STOMP) ? 0 : 1; + break; + + case HAL_MCI_STATE_NEED_TUNING: + value = (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_DISABLE_TUNING) ? 0 : 1; + break; + + case HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX: + value = ((AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_CONCUR_TX) == + ATH_MCI_CONCUR_TX_SHARED_CHN)? 1 : 0; + break; + + default: + break; + } + return value; +} + +void ar9300_mci_detach(struct ath_hal *ah) +{ + /* Turn off MCI and Jupiter mode. */ + OS_REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) ar9300_mci_detach\n"); + ar9300_mci_disable_interrupt(ah); +} + +/* + * Low priority BT: 0 - 59(0x3b) + * High priority BT: 60 - 125(0x7d) + * Critical BT: 126 - 255 + + BTCOEX_WL_WEIGHTS0_VALUE0 ; // wl_idle + BTCOEX_WL_WEIGHTS0_VALUE1 ; // sw_ctrl[3] - all_stomp + BTCOEX_WL_WEIGHTS0_VALUE2 ; // sw_ctrl[2] - all_not_stomp + BTCOEX_WL_WEIGHTS0_VALUE3 ; // sw_ctrl[1] - pa_pre_distortion + BTCOEX_WL_WEIGHTS1_VALUE0 ; // sw_ctrl[0] - general purpose + BTCOEX_WL_WEIGHTS1_VALUE1 ; // tm_wl_wait_beacon + BTCOEX_WL_WEIGHTS1_VALUE2 ; // ts_state_wait_ack_cts + BTCOEX_WL_WEIGHTS1_VALUE3 ; // self_gen + BTCOEX_WL_WEIGHTS2_VALUE0 ; // idle + BTCOEX_WL_WEIGHTS2_VALUE1 ; // rx + BTCOEX_WL_WEIGHTS2_VALUE2 ; // tx + BTCOEX_WL_WEIGHTS2_VALUE3 ; // rx + tx + BTCOEX_WL_WEIGHTS3_VALUE0 ; // tx + BTCOEX_WL_WEIGHTS3_VALUE1 ; // rx + BTCOEX_WL_WEIGHTS3_VALUE2 ; // tx + BTCOEX_WL_WEIGHTS3_VALUE3 ; // rx + tx + + Stomp all: + ah_bt_coex_wlan_weight[0] = 0x00007d00 + ah_bt_coex_wlan_weight[1] = 0x7d7d7d00 + ah_bt_coex_wlan_weight[2] = 0x7d7d7d00 + ah_bt_coex_wlan_weight[3] = 0x7d7d7d7d + Stomp low: + ah_bt_coex_wlan_weight[0] = 0x00007d00 + ah_bt_coex_wlan_weight[1] = 0x7d3b3b00 + ah_bt_coex_wlan_weight[2] = 0x3b3b3b00 + ah_bt_coex_wlan_weight[3] = 0x3b3b3b3b + Stomp none: + ah_bt_coex_wlan_weight[0] = 0x00007d00 + ah_bt_coex_wlan_weight[1] = 0x7d000000 + ah_bt_coex_wlan_weight[2] = 0x00000000 + ah_bt_coex_wlan_weight[3] = 0x00000000 +*/ + +void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + u_int32_t tx_priority = 0; + + switch (stomp_type) { + case HAL_BT_COEX_STOMP_ALL: + ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_ALL_WLAN_WGHT0; + ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_ALL_WLAN_WGHT1; + ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_ALL_WLAN_WGHT2; + ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_ALL_WLAN_WGHT3; + if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_all_tx_pri) { + tx_priority = ahp->ah_mci_stomp_all_tx_pri; + } + break; + case HAL_BT_COEX_STOMP_LOW: + if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX) { + ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_LOW_FTP_WLAN_WGHT0; + ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_LOW_FTP_WLAN_WGHT1; + ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_LOW_FTP_WLAN_WGHT2; + ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_LOW_FTP_WLAN_WGHT3; + } + else { + ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_LOW_WLAN_WGHT0; + ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_LOW_WLAN_WGHT1; + ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_LOW_WLAN_WGHT2; + ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_LOW_WLAN_WGHT3; + } + if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_low_tx_pri) { + tx_priority = ahp->ah_mci_stomp_low_tx_pri; + } + if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_MCI_OBS_TXRX) + { + ar9300_gpio_set(ah, 5, 1); + } + break; + case HAL_BT_COEX_STOMP_ALL_FORCE: + ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0; + ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1; + ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT2; + ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_ALL_FORCE_WLAN_WGHT3; + break; + case HAL_BT_COEX_STOMP_LOW_FORCE: + ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_LOW_FORCE_WLAN_WGHT0; + ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_LOW_FORCE_WLAN_WGHT1; + ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_LOW_FORCE_WLAN_WGHT2; + ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_LOW_FORCE_WLAN_WGHT3; + if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_low_tx_pri) { + tx_priority = ahp->ah_mci_stomp_low_tx_pri; + } + break; + case HAL_BT_COEX_STOMP_NONE: + case HAL_BT_COEX_NO_STOMP: + ahp->ah_bt_coex_wlan_weight[0] = JUPITER_STOMP_NONE_WLAN_WGHT0; + ahp->ah_bt_coex_wlan_weight[1] = JUPITER_STOMP_NONE_WLAN_WGHT1; + ahp->ah_bt_coex_wlan_weight[2] = JUPITER_STOMP_NONE_WLAN_WGHT2; + ahp->ah_bt_coex_wlan_weight[3] = JUPITER_STOMP_NONE_WLAN_WGHT3; + if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_none_tx_pri) { + tx_priority = ahp->ah_mci_stomp_none_tx_pri; + } + if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_MCI_OBS_TXRX) + { + ar9300_gpio_set(ah, 5, 0); + } + break; + default: + /* There is a forceWeight from registry */ + ahp->ah_bt_coex_wlan_weight[0] = stomp_type; + ahp->ah_bt_coex_wlan_weight[1] = stomp_type; + break; + } + + if (ahp->ah_mci_concur_tx_en && tx_priority) { + ahp->ah_bt_coex_wlan_weight[1] &= ~MCI_CONCUR_TX_WLAN_WGHT1_MASK; + ahp->ah_bt_coex_wlan_weight[1] |= + SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT1_MASK); + ahp->ah_bt_coex_wlan_weight[2] &= ~MCI_CONCUR_TX_WLAN_WGHT2_MASK; + ahp->ah_bt_coex_wlan_weight[2] |= + SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT2_MASK); + ahp->ah_bt_coex_wlan_weight[3] &= ~MCI_CONCUR_TX_WLAN_WGHT3_MASK; + ahp->ah_bt_coex_wlan_weight[3] |= + SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT3_MASK); + ahp->ah_bt_coex_wlan_weight[3] &= ~MCI_CONCUR_TX_WLAN_WGHT3_MASK2; + ahp->ah_bt_coex_wlan_weight[3] |= + SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT3_MASK2); + } + if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_MCI_WEIGHT_DBG) + { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) Set weights: 0x%08x 0x%08x 0x%08x 0x%08x\n", + ahp->ah_bt_coex_wlan_weight[0], + ahp->ah_bt_coex_wlan_weight[1], + ahp->ah_bt_coex_wlan_weight[2], + ahp->ah_bt_coex_wlan_weight[3]); + } +} + +void ar9300_mci_bt_coex_disable(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Set weight to stomp none.\n", __func__); + + ar9300_mci_bt_coex_set_weights(ah, HAL_BT_COEX_STOMP_NONE); + + /* + * In Jupiter, when coex is disabled, we just set weight + * table to be in favor of WLAN. + */ + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, ahp->ah_bt_coex_wlan_weight[2]); + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, ahp->ah_bt_coex_wlan_weight[3]); + + ahp->ah_bt_coex_enabled = AH_FALSE; +} + +int ar9300_mci_bt_coex_enable(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + /* Mainly change the WLAN weight table */ + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, ahp->ah_bt_coex_wlan_weight[2]); + OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, ahp->ah_bt_coex_wlan_weight[3]); + + /* Send ACK even when BT has higher priority. */ + OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); + + if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) { + OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); + } + else { + OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); + } + + ahp->ah_bt_coex_enabled = AH_TRUE; + + return 0; +} + +#endif /* ATH_SUPPORT_MCI */ +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_misc.c b/hal/ar9300/ar9300_misc.c new file mode 100644 index 000000000000..1b21239d9eb7 --- /dev/null +++ b/hal/ar9300/ar9300_misc.c @@ -0,0 +1,3714 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" +#include "ah_devid.h" +#ifdef AH_DEBUG +#include "ah_desc.h" /* NB: for HAL_PHYERR* */ +#endif + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300phy.h" + + +void +ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + *hangs = 0; + + if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { + *hangs |= HAL_RIFS_BB_HANG_WAR; + } + if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { + *hangs |= HAL_DFS_BB_HANG_WAR; + } + if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) + == HAL_OK) + { + *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR; + } + if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { + *hangs |= HAL_MAC_HANG_WAR; + } + if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) + == HAL_OK) + { + *hangs |= HAL_PHYRESTART_CLR_WAR; + } + + ahp->ah_hang_wars = *hangs; +} + +static u_int +ar9300_mac_to_usec(struct ath_hal *ah, u_int clks) +{ + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + + if (chan && IS_CHAN_HT40(chan)) { + return (ath_hal_mac_usec(ah, clks) / 2); + } else { + return (ath_hal_mac_usec(ah, clks)); + } +} + +u_int +ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs) +{ + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + + if (chan && IS_CHAN_HT40(chan)) { + return (ath_hal_mac_clks(ah, usecs) * 2); + } else { + return (ath_hal_mac_clks(ah, usecs)); + } +} + +void +ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); +} + +HAL_BOOL +ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); + return AH_TRUE; +} + +void +ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN); +} + +HAL_BOOL +ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + /* save it since it must be rewritten on reset */ + OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN); + + OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask)); + OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4)); + return AH_TRUE; +} + +/* + * Attempt to change the cards operating regulatory domain to the given value + * Returns: A_EINVAL for an unsupported regulatory domain. + * A_HARDWARE for an unwritable EEPROM or bad EEPROM version + */ +HAL_BOOL +ar9300_set_regulatory_domain(struct ath_hal *ah, + u_int16_t reg_domain, HAL_STATUS *status) +{ + HAL_STATUS ecode; + + if (AH_PRIVATE(ah)->ah_current_rd == 0) { + AH_PRIVATE(ah)->ah_current_rd = reg_domain; + return AH_TRUE; + } + ecode = HAL_EIO; + +#if tbd +bad: +#endif + if (status) { + *status = ecode; + } + return AH_FALSE; +} + +/* + * Return the wireless modes (a,b,g,t) supported by hardware. + * + * This value is what is actually supported by the hardware + * and is unaffected by regulatory/country code settings. + * + */ +u_int +ar9300_get_wireless_modes(struct ath_hal *ah) +{ + return AH_PRIVATE(ah)->ah_caps.hal_wireless_modes; +} + +/* + * Set the interrupt and GPIO values so the ISR can disable RF + * on a switch signal. Assumes GPIO port and interrupt polarity + * are set prior to call. + */ +void +ar9300_enable_rf_kill(struct ath_hal *ah) +{ + /* TODO - can this really be above the hal on the GPIO interface for + * TODO - the client only? + */ + struct ath_hal_9300 *ahp = AH9300(ah); + + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + /* Check RF kill GPIO before set/clear RFSILENT bits. */ + if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) { + OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), + AR_RFSILENT_FORCE); + OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); + } + else { + OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), + AR_RFSILENT_FORCE); + OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB); + } + } + else { + /* Connect rfsilent_bb_l to baseband */ + OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), + AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); + + /* Set input mux for rfsilent_bb_l to GPIO #0 */ + OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), + AR_GPIO_INPUT_MUX2_RFSILENT); + OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), + (ahp->ah_gpio_select & 0x0f) << 4); + + /* + * Configure the desired GPIO port for input and + * enable baseband rf silence + */ + ath_hal_gpio_cfg_input(ah, ahp->ah_gpio_select); + OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); + } + + /* + * If radio disable switch connection to GPIO bit x is enabled + * program GPIO interrupt. + * If rfkill bit on eeprom is 1, setupeeprommap routine has already + * verified that it is a later version of eeprom, it has a place for + * rfkill bit and it is set to 1, indicating that GPIO bit x hardware + * connection is present. + */ + /* + * RFKill uses polling not interrupt, + * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue + */ + if (ath_hal_hasrfkill_int(ah)) { + if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) { + /* switch already closed, set to interrupt upon open */ + ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit); + } else { + ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit); + } + } +} + +/* + * Change the LED blinking pattern to correspond to the connectivity + */ +void +ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state) +{ + static const u_int32_t ledbits[8] = { + AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */ + AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */ + AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */ + AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */ + AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */ + AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */ + AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ + AR_CFG_LED_ASSOC_NONE, + }; + + OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]); +} + +/* + * Sets the Power LED on the cardbus without affecting the Network LED. + */ +void +ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled) +{ + u_int32_t val; + + val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF; + OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val); +} + +/* + * Sets the Network LED on the cardbus without affecting the Power LED. + */ +void +ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled) +{ + u_int32_t val; + + val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF; + OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val); +} + +/* + * Change association related fields programmed into the hardware. + * Writing a valid BSSID to the hardware effectively enables the hardware + * to synchronize its TSF to the correct beacons and receive frames coming + * from that BSSID. It is called by the SME JOIN operation. + */ +void +ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, + u_int16_t assoc_id) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + /* save bssid and assoc_id for restore on reset */ + OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); + ahp->ah_assoc_id = assoc_id; + + OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); + OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | + ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S)); +} + +/* + * Get the current hardware tsf for stamlme + */ +u_int64_t +ar9300_get_tsf64(struct ath_hal *ah) +{ + u_int64_t tsf; + + /* XXX sync multi-word read? */ + tsf = OS_REG_READ(ah, AR_TSF_U32); + tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); + return tsf; +} + +void +ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf) +{ + OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff)); + OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff)); +} + +/* + * Get the current hardware tsf for stamlme + */ +u_int32_t +ar9300_get_tsf32(struct ath_hal *ah) +{ + return OS_REG_READ(ah, AR_TSF_L32); +} + +u_int32_t +ar9300_get_tsf2_32(struct ath_hal *ah) +{ + return OS_REG_READ(ah, AR_TSF2_L32); +} + +/* + * Reset the current hardware tsf for stamlme. + */ +void +ar9300_reset_tsf(struct ath_hal *ah) +{ + int count; + + count = 0; + while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { + count++; + if (count > 10) { + HALDEBUG(ah, HAL_DEBUG_RESET, + "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__); + break; + } + OS_DELAY(10); + } + OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); +} + +/* + * Set or clear hardware basic rate bit + * Set hardware basic rate set if basic rate is found + * and basic rate is equal or less than 2Mbps + */ +void +ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs) +{ + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + u_int32_t reg; + u_int8_t xset; + int i; + + if (chan == AH_NULL || !IS_CHAN_CCK(chan)) { + return; + } + xset = 0; + for (i = 0; i < rs->rs_count; i++) { + u_int8_t rset = rs->rs_rates[i]; + /* Basic rate defined? */ + if ((rset & 0x80) && (rset &= 0x7f) >= xset) { + xset = rset; + } + } + /* + * Set the h/w bit to reflect whether or not the basic + * rate is found to be equal or less than 2Mbps. + */ + reg = OS_REG_READ(ah, AR_STA_ID1); + if (xset && xset / 2 <= 2) { + OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); + } else { + OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); + } +} + +/* + * Grab a semi-random value from hardware registers - may not + * change often + */ +u_int32_t +ar9300_get_random_seed(struct ath_hal *ah) +{ + u_int32_t nf; + + nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; + if (nf & 0x100) { + nf = 0 - ((nf ^ 0x1ff) + 1); + } + return (OS_REG_READ(ah, AR_TSF_U32) ^ + OS_REG_READ(ah, AR_TSF_L32) ^ nf); +} + +/* + * Detect if our card is present + */ +HAL_BOOL +ar9300_detect_card_present(struct ath_hal *ah) +{ + u_int16_t mac_version, mac_rev; + u_int32_t v; + + /* + * Read the Silicon Revision register and compare that + * to what we read at attach time. If the same, we say + * a card/device is present. + */ + v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID; + if (v == 0xFF) { + /* new SREV format */ + v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); + /* + * Include 6-bit Chip Type (masked to 0) to differentiate + * from pre-Sowl versions + */ + mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; + mac_rev = MS(v, AR_SREV_REVISION2); + } else { + mac_version = MS(v, AR_SREV_VERSION); + mac_rev = v & AR_SREV_REVISION; + } + return (AH_PRIVATE(ah)->ah_macVersion == mac_version && + AH_PRIVATE(ah)->ah_macRev == mac_rev); +} + +/* + * Update MIB Counters + */ +void +ar9300_update_mib_mac_stats(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats; + + stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); + stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); + stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); + stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); + stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); +} + +void +ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats; + + stats->ackrcv_bad = istats->ackrcv_bad; + stats->rts_bad = istats->rts_bad; + stats->fcs_bad = istats->fcs_bad; + stats->rts_good = istats->rts_good; + stats->beacons = istats->beacons; +} + +/* + * Detect if the HW supports spreading a CCK signal on channel 14 + */ +HAL_BOOL +ar9300_is_japan_channel_spread_supported(struct ath_hal *ah) +{ + return AH_TRUE; +} + +/* + * Get the rssi of frame curently being received. + */ +u_int32_t +ar9300_get_cur_rssi(struct ath_hal *ah) +{ + /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */ + /* get combined RSSI */ + return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff); +} + +#if ATH_GEN_RANDOMNESS +/* + * Get the rssi value from BB on ctl chain0. + */ +u_int32_t +ar9300_get_rssi_chain0(struct ath_hal *ah) +{ + /* get ctl chain0 RSSI */ + return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff; +} +#endif + +u_int +ar9300_get_def_antenna(struct ath_hal *ah) +{ + return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); +} + +/* Setup coverage class */ +void +ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now) +{ +} + +void +ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna) +{ + OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); +} + +HAL_BOOL +ar9300_set_antenna_switch(struct ath_hal *ah, + HAL_ANT_SETTING settings, HAL_CHANNEL *chan, u_int8_t *tx_chainmask, + u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + /* + * Owl does not support diversity or changing antennas. + * + * Instead this API and function are defined differently for AR9300. + * To support Tablet PC's, this interface allows the system + * to dramatically reduce the TX power on a particular chain. + * + * Based on the value of (redefined) diversity_control, the + * reset code will decrease power on chain 0 or chain 1/2. + * + * Based on the value of bit 0 of antenna_switch_swap, + * the mapping between OID call and chain is defined as: + * 0: map A -> 0, B -> 1; + * 1: map A -> 1, B -> 0; + * + * NOTE: + * The devices that use this OID should use a tx_chain_mask and + * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is + * used in order to ensure an active transmit antenna. This + * API will allow the host to turn off the only transmitting + * antenna to ensure the antenna closest to the user's body is + * powered-down. + */ + /* + * Set antenna control for use during reset sequence by + * ar9300_decrease_chain_power() + */ + ahp->ah_diversity_control = settings; + + return AH_TRUE; +} + +HAL_BOOL +ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah) +{ + return AH_TRUE; +} + +HAL_BOOL +ar9300_set_slot_time(struct ath_hal *ah, u_int us) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) { + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us); + ahp->ah_slot_time = (u_int) -1; /* restore default handling */ + return AH_FALSE; + } else { + /* convert to system clocks */ + OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us)); + ahp->ah_slot_time = us; + return AH_TRUE; + } +} + +HAL_BOOL +ar9300_set_ack_timeout(struct ath_hal *ah, u_int us) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us); + ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */ + return AH_FALSE; + } else { + /* convert to system clocks */ + OS_REG_RMW_FIELD(ah, + AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us)); + ahp->ah_ack_timeout = us; + return AH_TRUE; + } +} + +u_int +ar9300_get_ack_timeout(struct ath_hal *ah) +{ + u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); + return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */ +} + +HAL_STATUS +ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, + u_int32_t next_start, HAL_QUIET_FLAG flag) +{ + HAL_STATUS status = HAL_EIO; + u_int32_t tsf = 0, j, next_start_us = 0; + if (flag & HAL_QUIET_ENABLE) { + for (j = 0; j < 2; j++) { + next_start_us = TU_TO_USEC(next_start); + tsf = OS_REG_READ(ah, AR_TSF_L32); + if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { + next_start_us += tsf; + } + if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { + next_start_us += + AH_PRIVATE(ah)->ah_config.ath_hal_sw_beacon_response_time; + } + OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); + OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); + OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period)); + OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us); + OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); + if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) { + status = HAL_OK; + break; + } + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved " + "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf); + /* TSF shouldn't count twice or reg access is taking forever */ + HALASSERT(j < 1); + } + } else { + OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); + status = HAL_OK; + } + + return status; +} +#ifdef ATH_SUPPORT_DFS +void +ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable) +{ + u32 reg1, reg2; + + reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE)); + reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1)); + AH9300(ah)->ah_cac_quiet_enabled = enable; + + if (enable) { + OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), + reg1 | AR_PCU_FORCE_QUIET_COLL); + OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), + reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE); + } else { + OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), + reg1 & ~AR_PCU_FORCE_QUIET_COLL); + OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), + reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE); + } +} +#endif /* ATH_SUPPORT_DFS */ + +void +ar9300_set_pcu_config(struct ath_hal *ah) +{ + ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode); +} + +HAL_STATUS +ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, + u_int32_t capability, u_int32_t *result) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + + switch (type) { + case HAL_CAP_CIPHER: /* cipher handled in hardware */ + switch (capability) { + case HAL_CIPHER_AES_CCM: + case HAL_CIPHER_AES_OCB: + case HAL_CIPHER_TKIP: + case HAL_CIPHER_WEP: + case HAL_CIPHER_MIC: + case HAL_CIPHER_CLR: + return HAL_OK; + default: + return HAL_ENOTSUPP; + } + case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ + switch (capability) { + case 0: /* hardware capability */ + return HAL_OK; + case 1: + return (ahp->ah_sta_id1_defaults & + AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO; + default: + return HAL_ENOTSUPP; + } + case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ + /* XXX check rev when new parts are available */ + return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? + HAL_ENXIO : HAL_OK; + case HAL_CAP_WME_TKIPMIC: + /* hardware can do TKIP MIC when WMM is turned on */ + return HAL_OK; + case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */ + return HAL_OK; + case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */ + switch (capability) { + case 0: /* hardware capability */ + return HAL_OK; + case 1: /* current setting */ + return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) & + AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? + HAL_OK : HAL_ENXIO; + } + return HAL_EINVAL; + case HAL_CAP_TPC: + switch (capability) { + case 0: /* hardware capability */ + return HAL_OK; + case 1: + return AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc ? + HAL_OK : HAL_ENXIO; + } + return HAL_OK; + case HAL_CAP_PHYDIAG: /* radar pulse detection capability */ + return HAL_OK; + case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ + switch (capability) { + case 0: /* hardware capability */ + return HAL_OK; + case 1: + if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { + /* + * Owl and Merlin have problems in mcast key search. + * Disable this cap. in Ad-hoc mode. see Bug 25776 and + * 26802 + */ + return HAL_ENXIO; + } else { + return (ahp->ah_sta_id1_defaults & + AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO; + } + } + return HAL_EINVAL; + case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ + switch (capability) { + case 0: /* hardware capability */ + return p_cap->hal_tsf_add_support ? HAL_OK : HAL_ENOTSUPP; + case 1: + return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ? + HAL_OK : HAL_ENXIO; + } + return HAL_EINVAL; + case HAL_CAP_RFSILENT: /* rfsilent support */ + if (capability == 3) { /* rfkill interrupt */ + /* + * XXX: Interrupt-based notification of RF Kill state + * changes not working yet. Report that this feature + * is not supported so that polling is used instead. + */ + return (HAL_ENOTSUPP); + } + return ath_hal_getcapability(ah, type, capability, result); + case HAL_CAP_4ADDR_AGGR: + return HAL_OK; + case HAL_CAP_BB_RIFS_HANG: + return HAL_ENOTSUPP; + case HAL_CAP_BB_DFS_HANG: + return HAL_ENOTSUPP; + case HAL_CAP_BB_RX_CLEAR_STUCK_HANG: + /* Track chips that are known to have BB hangs related + * to rx_clear stuck low. + */ + return HAL_ENOTSUPP; + case HAL_CAP_MAC_HANG: + /* Track chips that are known to have MAC hangs. + */ + return HAL_OK; + case HAL_CAP_RIFS_RX_ENABLED: + /* Is RIFS RX currently enabled */ + return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; + case HAL_CAP_ANT_CFG_2GHZ: + *result = p_cap->hal_num_ant_cfg_2ghz; + return HAL_OK; + case HAL_CAP_ANT_CFG_5GHZ: + *result = p_cap->hal_num_ant_cfg_5ghz; + return HAL_OK; + case HAL_CAP_RX_STBC: + *result = p_cap->hal_rx_stbc_support; + return HAL_OK; + case HAL_CAP_TX_STBC: + *result = p_cap->hal_tx_stbc_support; + return HAL_OK; + case HAL_CAP_LDPC: + *result = p_cap->hal_ldpc_support; + return HAL_OK; + case HAL_CAP_DYNAMIC_SMPS: + return HAL_OK; + case HAL_CAP_DS: + return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || + (p_cap->hal_tx_chain_mask & 0x3) != 0x3 || + (p_cap->hal_rx_chain_mask & 0x3) != 0x3) ? + HAL_ENOTSUPP : HAL_OK; + case HAL_CAP_TS: + return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || + (p_cap->hal_tx_chain_mask & 0x7) != 0x7 || + (p_cap->hal_rx_chain_mask & 0x7) != 0x7) ? + HAL_ENOTSUPP : HAL_OK; + case HAL_CAP_OL_PWRCTRL: + return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ? + HAL_OK : HAL_ENOTSUPP; + case HAL_CAP_CRDC: +#if ATH_SUPPORT_CRDC + return (AR_SREV_WASP(ah) && + AH_PRIVATE(ah)->ah_config.ath_hal_crdc_enable) ? + HAL_OK : HAL_ENOTSUPP; +#else + return HAL_ENOTSUPP; +#endif + case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS: + *result = (u_int32_t)(-1); + return HAL_OK; + case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS: + *result = (u_int32_t)(-1); + return HAL_OK; + case HAL_CAP_BB_PANIC_WATCHDOG: + return HAL_OK; + case HAL_CAP_PHYRESTART_CLR_WAR: + if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && + (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10)) + { + return HAL_OK; + } + else + { + return HAL_ENOTSUPP; + } + case HAL_CAP_ENTERPRISE_MODE: + *result = ahp->ah_enterprise_mode >> 16; + /* + * WAR for EV 77658 - Add delimiters to first sub-frame when using + * RTS/CTS with aggregation and non-enterprise Osprey. + * + * Bug fixed in AR9580/Peacock, Wasp1.1 and later + */ + if ((ahp->ah_enterprise_mode && AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) && + !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) || + AR_SREV_WASP_10(ah))) { + *result |= AH_ENT_RTSCTS_DELIM_WAR; + } + return HAL_OK; + case HAL_CAP_LDPCWAR: + /* WAR for RIFS+LDPC issue is required for all chips currently + * supported by ar9300 HAL. + */ + return HAL_OK; + case HAL_CAP_ENABLE_APM: + *result = p_cap->hal_enable_apm; + return HAL_OK; + case HAL_CAP_PCIE_LCR_EXTSYNC_EN: + return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; + case HAL_CAP_PCIE_LCR_OFFSET: + *result = p_cap->hal_pcie_lcr_offset; + return HAL_OK; + case HAL_CAP_SMARTANTENNA: + /* FIXME A request is pending with h/w team to add feature bit in + * caldata to detect if board has smart antenna or not, once added + * we need to fix his piece of code to read and return value without + * any compile flags + */ +#if UMAC_SUPPORT_SMARTANTENNA + /* enable smart antenna for Peacock, Wasp and scorpion + for future chips need to modify */ + if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) { + return HAL_OK; + } else { + return HAL_ENOTSUPP; + } +#else + return HAL_ENOTSUPP; +#endif + +#ifdef ATH_TRAFFIC_FAST_RECOVER + case HAL_CAP_TRAFFIC_FAST_RECOVER: + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) { + return HAL_OK; + } else { + return HAL_ENOTSUPP; + } +#endif + default: + return ath_hal_getcapability(ah, type, capability, result); + } +} + +HAL_BOOL +ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, + u_int32_t capability, u_int32_t setting, HAL_STATUS *status) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + u_int32_t v; + + switch (type) { + case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ + if (setting) { + ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; + } else { + ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; + } + return AH_TRUE; + case HAL_CAP_DIVERSITY: + v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); + if (setting) { + v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; + } else { + v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; + } + OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); + return AH_TRUE; + case HAL_CAP_DIAG: /* hardware diagnostic support */ + /* + * NB: could split this up into virtual capabilities, + * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly + * seems worth the additional complexity. + */ +#ifdef AH_DEBUG + AH_PRIVATE(ah)->ah_diagreg = setting; +#else + AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ +#endif + OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); + return AH_TRUE; + case HAL_CAP_TPC: + AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = (setting != 0); + return AH_TRUE; + case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ + if (setting) { + ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; + } else { + ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; + } + return AH_TRUE; + case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ + if (p_cap->hal_tsf_add_support) { + if (setting) { + ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF; + } else { + ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF; + } + return AH_TRUE; + } + return AH_FALSE; + case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */ + ahp->rx_buf_size = setting & AR_DATABUF_MASK; + OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size); + return AH_TRUE; + + /* fall thru... */ + default: + return ath_hal_setcapability(ah, type, capability, setting, status); + } +} + +#ifdef AH_DEBUG +static void +ar9300_print_reg(struct ath_hal *ah, u_int32_t args) +{ + u_int32_t i = 0; + + /* Read 0x80d0 to trigger pcie analyzer */ + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0)); + + if (args & HAL_DIAG_PRINT_REG_COUNTER) { + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t tf, rf, rc, cc; + + tf = OS_REG_READ(ah, AR_TFCNT); + rf = OS_REG_READ(ah, AR_RFCNT); + rc = OS_REG_READ(ah, AR_RCCNT); + cc = OS_REG_READ(ah, AR_CCCNT); + + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf); + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf); + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc); + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc); + + ahp->last_tf = tf; + ahp->last_rf = rf; + ahp->last_rc = rc; + ahp->last_cc = cc; + + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0)); + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1)); + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2)); + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3)); + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4)); + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5)); + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6)); + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7)); + } + + if (args & HAL_DIAG_PRINT_REG_ALL) { + for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i)); + + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, + "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i)); + + for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + + for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) { + HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", + i, OS_REG_READ(ah, i)); + } + } +} +#endif + +HAL_BOOL +ar9300_get_diag_state(struct ath_hal *ah, int request, + const void *args, u_int32_t argsize, + void **result, u_int32_t *resultsize) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + (void) ahp; + if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) { + return AH_TRUE; + } + switch (request) { +#ifdef AH_PRIVATE_DIAG + case HAL_DIAG_EEPROM: + *result = &ahp->ah_eeprom; + *resultsize = sizeof(HAL_EEPROM); + return AH_TRUE; + +#if 0 /* XXX - TODO */ + case HAL_DIAG_EEPROM_EXP_11A: + case HAL_DIAG_EEPROM_EXP_11B: + case HAL_DIAG_EEPROM_EXP_11G: + pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A]; + *result = pe->p_channels; + *resultsize = (*result == AH_NULL) ? 0 : + roundup(sizeof(u_int16_t) * pe->num_channels, + sizeof(u_int32_t)) + + sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels; + return AH_TRUE; +#endif + case HAL_DIAG_RFGAIN: + *result = &ahp->ah_gain_values; + *resultsize = sizeof(GAIN_VALUES); + return AH_TRUE; + case HAL_DIAG_RFGAIN_CURSTEP: + *result = (void *) ahp->ah_gain_values.curr_step; + *resultsize = (*result == AH_NULL) ? + 0 : sizeof(GAIN_OPTIMIZATION_STEP); + return AH_TRUE; +#if 0 /* XXX - TODO */ + case HAL_DIAG_PCDAC: + *result = ahp->ah_pcdac_table; + *resultsize = ahp->ah_pcdac_table_size; + return AH_TRUE; +#endif + case HAL_DIAG_ANI_CURRENT: + *result = ar9300_ani_get_current_state(ah); + *resultsize = (*result == AH_NULL) ? + 0 : sizeof(struct ar9300_ani_state); + return AH_TRUE; + case HAL_DIAG_ANI_STATS: + *result = ar9300_ani_get_current_stats(ah); + *resultsize = (*result == AH_NULL) ? + 0 : sizeof(struct ar9300_stats); + return AH_TRUE; + case HAL_DIAG_ANI_CMD: + if (argsize != 2*sizeof(u_int32_t)) { + return AH_FALSE; + } + ar9300_ani_control( + ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]); + return AH_TRUE; + case HAL_DIAG_TXCONT: + /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/ + return AH_TRUE; +#endif /* AH_PRIVATE_DIAG */ + case HAL_DIAG_CHANNELS: + *result = &(ahp->ah_priv.ah_channels[0]); + *resultsize = + sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan; + return AH_TRUE; +#ifdef AH_DEBUG + case HAL_DIAG_PRINT_REG: + ar9300_print_reg(ah, *((const u_int32_t *)args)); + return AH_TRUE; +#endif + default: + break; + } + + return AH_FALSE; +} + +void +ar9300_dma_reg_dump(struct ath_hal *ah) +{ +#ifdef AH_DEBUG +#define NUM_DMA_DEBUG_REGS 8 +#define NUM_QUEUES 10 + + u_int32_t val[NUM_DMA_DEBUG_REGS]; + int qcu_offset = 0, dcu_offset = 0; + u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; + int i, j, k; + int16_t nfarray[NUM_NF_READINGS]; + HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah); + + /* selecting DMA OBS 8 */ + OS_REG_WRITE(ah, AR_MACMISC, + ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | + (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); + + ath_hal_printf(ah, "Raw DMA Debug values:\n"); + for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) { + if (i % 4 == 0) { + ath_hal_printf(ah, "\n"); + } + + val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t))); + ath_hal_printf(ah, "%d: %08x ", i, val[i]); + } + + ath_hal_printf(ah, "\n\n"); + ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); + + for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) { + if (i == 8) { + /* only 8 QCU entries in val[0] */ + qcu_offset = 0; + qcu_base++; + } + + if (i == 6) { + /* only 6 DCU entries in val[4] */ + dcu_offset = 0; + dcu_base++; + } + + ath_hal_printf(ah, + "%2d %2x %1x %2x %2x\n", + i, + (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset, + (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3), + val[2] & (0x7 << (i * 3)) >> (i * 3), + (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset); + } + + ath_hal_printf(ah, "\n"); + ath_hal_printf(ah, + "qcu_stitch state: %2x qcu_fetch state: %2x\n", + (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); + ath_hal_printf(ah, + "qcu_complete state: %2x dcu_complete state: %2x\n", + (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); + ath_hal_printf(ah, + "dcu_arb state: %2x dcu_fp state: %2x\n", + (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); + ath_hal_printf(ah, + "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", + (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); + ath_hal_printf(ah, + "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", + (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); + ath_hal_printf(ah, + "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", + (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); + ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1)); + ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); + + ar9300_upload_noise_floor(ah, 1, nfarray); + ath_hal_printf(ah, "2G:\n"); + ath_hal_printf(ah, "Min CCA Out:\n"); + ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); + ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", + nfarray[0], nfarray[1], nfarray[2]); + ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", + nfarray[3], nfarray[4], nfarray[5]); + + ar9300_upload_noise_floor(ah, 0, nfarray); + ath_hal_printf(ah, "5G:\n"); + ath_hal_printf(ah, "Min CCA Out:\n"); + ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); + ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", + nfarray[0], nfarray[1], nfarray[2]); + ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", + nfarray[3], nfarray[4], nfarray[5]); + + for (i = 0; i < NUM_NF_READINGS; i++) { + ath_hal_printf(ah, "%s Chain %d NF History:\n", + ((i < 3) ? "Control " : "Extension "), i%3); + for (j = 0, k = h->base.curr_index; + j < HAL_NF_CAL_HIST_LEN_FULL; + j++, k++) { + ath_hal_printf(ah, "Element %d: %d\n", + j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]); + } + ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]); + } + + reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW); + ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n", + MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW), + MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW)); + reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ); + ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n", + MS(reg, AR_PHY_DESIRED_SZ_TOT_DES), + MS(reg, AR_PHY_DESIRED_SZ_TOT_DES)); + ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n", + MS(reg, AR_PHY_DESIRED_SZ_ADC), + MS(reg, AR_PHY_DESIRED_SZ_ADC)); + reg = OS_REG_READ(ah, AR_PHY_FIND_SIG); + ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n", + MS(reg, AR_PHY_FIND_SIG_FIRSTEP), + MS(reg, AR_PHY_FIND_SIG_FIRSTEP)); + reg = OS_REG_READ(ah, AR_PHY_AGC); + ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n", + MS(reg, AR_PHY_AGC_COARSE_HIGH), + MS(reg, AR_PHY_AGC_COARSE_HIGH)); + ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n", + MS(reg, AR_PHY_AGC_COARSE_LOW), + MS(reg, AR_PHY_AGC_COARSE_LOW)); + ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n", + MS(reg, AR_PHY_AGC_COARSE_PWR_CONST), + MS(reg, AR_PHY_AGC_COARSE_PWR_CONST)); + reg = OS_REG_READ(ah, AR_PHY_TIMING5); + ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n", + MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE)); + ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n", + MS(reg, AR_PHY_TIMING5_CYCPWR_THR1), + MS(reg, AR_PHY_TIMING5_CYCPWR_THR1)); + ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n", + MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A), + MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A)); + reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK); + ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n", + MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR)); + ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n", + MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR), + MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR)); + + + /* Step 1a: Set bit 23 of register 0xa360 to 0 */ + reg = OS_REG_READ(ah, 0xa360); + reg &= ~0x00800000; + OS_REG_WRITE(ah, 0xa360, reg); + + /* Step 2a: Set register 0xa364 to 0x1000 */ + reg = 0x1000; + OS_REG_WRITE(ah, 0xa364, reg); + + /* Step 3a: Read bits 17:0 of register 0x9c20 */ + reg = OS_REG_READ(ah, 0x9c20); + reg &= 0x0003ffff; + ath_hal_printf(ah, + "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", + __func__, reg); + + /* Step 1b: Set bit 23 of register 0xa360 to 0 */ + reg = OS_REG_READ(ah, 0xa360); + reg &= ~0x00800000; + OS_REG_WRITE(ah, 0xa360, reg); + + /* Step 2b: Set register 0xa364 to 0x1400 */ + reg = 0x1400; + OS_REG_WRITE(ah, 0xa364, reg); + + /* Step 3b: Read bits 17:0 of register 0x9c20 */ + reg = OS_REG_READ(ah, 0x9c20); + reg &= 0x0003ffff; + ath_hal_printf(ah, + "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", + __func__, reg); + + /* Step 1c: Set bit 23 of register 0xa360 to 0 */ + reg = OS_REG_READ(ah, 0xa360); + reg &= ~0x00800000; + OS_REG_WRITE(ah, 0xa360, reg); + + /* Step 2c: Set register 0xa364 to 0x3C00 */ + reg = 0x3c00; + OS_REG_WRITE(ah, 0xa364, reg); + + /* Step 3c: Read bits 17:0 of register 0x9c20 */ + reg = OS_REG_READ(ah, 0x9c20); + reg &= 0x0003ffff; + ath_hal_printf(ah, + "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", + __func__, reg); + + /* Step 1d: Set bit 24 of register 0xa360 to 0 */ + reg = OS_REG_READ(ah, 0xa360); + reg &= ~0x001040000; + OS_REG_WRITE(ah, 0xa360, reg); + + /* Step 2d: Set register 0xa364 to 0x5005D */ + reg = 0x5005D; + OS_REG_WRITE(ah, 0xa364, reg); + + /* Step 3d: Read bits 17:0 of register 0xa368 */ + reg = OS_REG_READ(ah, 0xa368); + reg &= 0x0003ffff; + ath_hal_printf(ah, + "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", + __func__, reg); + + /* Step 1e: Set bit 24 of register 0xa360 to 0 */ + reg = OS_REG_READ(ah, 0xa360); + reg &= ~0x001040000; + OS_REG_WRITE(ah, 0xa360, reg); + + /* Step 2e: Set register 0xa364 to 0x7005D */ + reg = 0x7005D; + OS_REG_WRITE(ah, 0xa364, reg); + + /* Step 3e: Read bits 17:0 of register 0xa368 */ + reg = OS_REG_READ(ah, 0xa368); + reg &= 0x0003ffff; + ath_hal_printf(ah, + "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", + __func__, reg); + + /* Step 1f: Set bit 24 of register 0xa360 to 0 */ + reg = OS_REG_READ(ah, 0xa360); + reg &= ~0x001000000; + reg |= 0x40000; + OS_REG_WRITE(ah, 0xa360, reg); + + /* Step 2f: Set register 0xa364 to 0x3005D */ + reg = 0x3005D; + OS_REG_WRITE(ah, 0xa364, reg); + + /* Step 3f: Read bits 17:0 of register 0xa368 */ + reg = OS_REG_READ(ah, 0xa368); + reg &= 0x0003ffff; + ath_hal_printf(ah, + "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", + __func__, reg); + + /* Step 1g: Set bit 24 of register 0xa360 to 0 */ + reg = OS_REG_READ(ah, 0xa360); + reg &= ~0x001000000; + reg |= 0x40000; + OS_REG_WRITE(ah, 0xa360, reg); + + /* Step 2g: Set register 0xa364 to 0x6005D */ + reg = 0x6005D; + OS_REG_WRITE(ah, 0xa364, reg); + + /* Step 3g: Read bits 17:0 of register 0xa368 */ + reg = OS_REG_READ(ah, 0xa368); + reg &= 0x0003ffff; + ath_hal_printf(ah, + "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", + __func__, reg); +#endif /* AH_DEBUG */ +} + +/* + * Return the busy for rx_frame, rx_clear, and tx_frame + */ +u_int32_t +ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt, + u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t good = 1; + + u_int32_t rc = OS_REG_READ(ah, AR_RCCNT); + u_int32_t rf = OS_REG_READ(ah, AR_RFCNT); + u_int32_t tf = OS_REG_READ(ah, AR_TFCNT); + u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ + + if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) { + /* + * Cycle counter wrap (or initial call); it's not possible + * to accurately calculate a value because the registers + * right shift rather than wrap--so punt and return 0. + */ + HALDEBUG(ah, HAL_DEBUG_CHANNEL, + "%s: cycle counter wrap. ExtBusy = 0\n", __func__); + good = 0; + } else { + u_int32_t cc_d = cc - ahp->ah_cycles; + u_int32_t rc_d = rc - ahp->ah_rx_clear; + u_int32_t rf_d = rf - ahp->ah_rx_frame; + u_int32_t tf_d = tf - ahp->ah_tx_frame; + + if (cc_d != 0) { + *rxc_pcnt = rc_d * 100 / cc_d; + *rxf_pcnt = rf_d * 100 / cc_d; + *txf_pcnt = tf_d * 100 / cc_d; + } else { + good = 0; + } + } + + ahp->ah_cycles = cc; + ahp->ah_rx_frame = rf; + ahp->ah_rx_clear = rc; + ahp->ah_tx_frame = tf; + + return good; +} + +/* + * Return approximation of extension channel busy over an time interval + * 0% (clear) -> 100% (busy) + * -1 for invalid estimate + */ +int8_t +ar9300_get_11n_ext_busy(struct ath_hal *ah) +{ + /* + * Overflow condition to check before multiplying to get % + * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28) + */ +#define OVERFLOW_LIMIT 0x28F5C28 +#define ERROR_CODE -1 + + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t busy = 0; /* percentage */ + int8_t busyper = 0; + u_int32_t cycle_count, ctl_busy, ext_busy; + + /* cycle_count will always be the first to wrap; therefore, read it last + * This sequence of reads is not atomic, and MIB counter wrap + * could happen during it ? + */ + ctl_busy = OS_REG_READ(ah, AR_RCCNT); + ext_busy = OS_REG_READ(ah, AR_EXTRCCNT); + cycle_count = OS_REG_READ(ah, AR_CCCNT); + + if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) || + (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy)) + { + /* + * Cycle counter wrap (or initial call); it's not possible + * to accurately calculate a value because the registers + * right shift rather than wrap--so punt and return 0. + */ + busyper = ERROR_CODE; + HALDEBUG(ah, HAL_DEBUG_CHANNEL, + "%s: cycle counter wrap. ExtBusy = 0\n", __func__); + } else { + u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count; + u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy; + + /* + * Compute extension channel busy percentage + * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100 + * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0 + * Will never happen, since (ext_busy_delta < cycle_delta) always, + * and shift necessitated by large ext_busy_delta. + * Due to timing difference to read the registers and counter overflow, + * it may still happen that cycle_delta >> 7 = 0. + * + */ + if (cycle_delta) { + if (ext_busy_delta > OVERFLOW_LIMIT) { + if (cycle_delta >> 7) { + busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7); + } else { + busyper = ERROR_CODE; + } + } else { + busy = (ext_busy_delta * 100) / cycle_delta; + } + } else { + busyper = ERROR_CODE; + } + + if (busy > 100) { + busy = 100; + } + if ( busyper != ERROR_CODE ) { + busyper = busy; + } + } + + ahp->ah_cycle_count = cycle_count; + ahp->ah_ctl_busy = ctl_busy; + ahp->ah_ext_busy = ext_busy; + + return busyper; +#undef OVERFLOW_LIMIT +#undef ERROR_CODE +} + +/* BB Panic Watchdog declarations */ +#define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */ +#define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */ + +void +ar9300_config_bb_panic_watchdog(struct ath_hal *ah) +{ +#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000 + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + u_int32_t idle_tmo_ms = AH_PRIVATE(ah)->ah_bb_panic_timeout_ms; + u_int32_t val, idle_count; + + if (idle_tmo_ms != 0) { + /* enable IRQ, disable chip-reset for BB panic */ + val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & + AR_PHY_BB_PANIC_CNTL2_MASK; + OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, + (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE); + /* bound limit to 10 secs */ + if (idle_tmo_ms > 10000) { + idle_tmo_ms = 10000; + } + if (chan != AH_NULL && IS_CHAN_HT40(chan)) { + idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR; + } else { + idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR; + } + /* + * enable panic in non-IDLE mode, + * disable in IDLE mode, + * set idle time-out + */ + + // EV92527 : Enable IDLE mode panic + + OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, + AR_PHY_BB_PANIC_NON_IDLE_ENABLE | + AR_PHY_BB_PANIC_IDLE_ENABLE | + (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) | + (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2))); + } else { + /* disable IRQ, disable chip-reset for BB panic */ + OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, + OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & + ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE)); + /* disable panic in non-IDLE mode, disable in IDLE mode */ + OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, + OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) & + ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE)); + } + + HALDEBUG(ah, HAL_DEBUG_RF_PARAM, "%s: %s BB Panic Watchdog tmo=%ums\n", + __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms); +#undef HAL_BB_PANIC_IDLE_TIME_OUT +} + + +void +ar9300_handle_bb_panic(struct ath_hal *ah) +{ + u_int32_t status; + /* + * we want to avoid printing in ISR context so we save + * panic watchdog status to be printed later in DPC context + */ + AH_PRIVATE(ah)->ah_bb_panic_last_status = status = + OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS); + /* + * panic watchdog timer should reset on status read + * but to make sure we write 0 to the watchdog status bit + */ + OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR); +} + +int +ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic) +{ + bb_panic->status = AH_PRIVATE(ah)->ah_bb_panic_last_status; + + /* + * For signature 04000539 do not print anything. + * This is a very common occurence as a compromise between + * BB Panic and AH_FALSE detects (EV71009). It indicates + * radar hang, which can be cleared by reprogramming + * radar related register and does not requre a chip reset + */ + + /* Suppress BB Status mesg following signature */ + switch (bb_panic->status) { + case 0x04000539: + case 0x04008009: + case 0x04000b09: + case 0x1300000a: + return -1; + } + + bb_panic->tsf = ar9300_get_tsf32(ah); + bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); + bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); + bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); + bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); + bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM); + bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM); + bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM); + bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM); + bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM); + bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1); + bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2); + bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL); + bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0; + bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah, + &bb_panic->rxc_pcnt, + &bb_panic->rxf_pcnt, + &bb_panic->txf_pcnt); + + if (AH_PRIVATE(ah)->ah_config.ath_hal_show_bb_panic) { + ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, " + "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf); + ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " + "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", + bb_panic->wd, bb_panic->det, bb_panic->rdar, + bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm, + bb_panic->t_cck, bb_panic->agc, bb_panic->src); + ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", + bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2); + ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n", + bb_panic->phy_gen_ctrl); + if (bb_panic->cycles) { + ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, " + "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt, + bb_panic->rxf_pcnt, bb_panic->txf_pcnt); + } + ath_hal_printf(ah, "==== BB update: done ====\n\n"); + } + + return 0; //The returned data will be stored for athstats to retrieve it +} + +/* set the reason for HAL reset */ +void +ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason) +{ + AH_PRIVATE(ah)->ah_reset_reason = resetreason; +} + +/* + * Configure 20/40 operation + * + * 20/40 = joint rx clear (control and extension) + * 20 = rx clear (control) + * + * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz + * when changing from 20/40 => 20 only + */ +void +ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) +{ + u_int32_t macmode; + + /* Configure MAC for 20/40 operation */ + if (mode == HAL_HT_MACMODE_2040 && + !AH_PRIVATE(ah)->ah_config.ath_hal_cwm_ignore_ext_cca) { + macmode = AR_2040_JOINED_RX_CLEAR; + } else { + macmode = 0; + } + OS_REG_WRITE(ah, AR_2040_MODE, macmode); +} + +/* + * Get Rx clear (control/extension channel) + * + * Returns active low (busy) for ctrl/ext channel + * Owl 2.0 + */ +HAL_HT_RXCLEAR +ar9300_get_11n_rx_clear(struct ath_hal *ah) +{ + HAL_HT_RXCLEAR rxclear = 0; + u_int32_t val; + + val = OS_REG_READ(ah, AR_DIAG_SW); + + /* control channel */ + if (val & AR_DIAG_RX_CLEAR_CTL_LOW) { + rxclear |= HAL_RX_CLEAR_CTL_LOW; + } + /* extension channel */ + if (val & AR_DIAG_RX_CLEAR_EXT_LOW) { + rxclear |= HAL_RX_CLEAR_EXT_LOW; + } + return rxclear; +} + +/* + * Set Rx clear (control/extension channel) + * + * Useful for forcing the channel to appear busy for + * debugging/diagnostics + * Owl 2.0 + */ +void +ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) +{ + /* control channel */ + if (rxclear & HAL_RX_CLEAR_CTL_LOW) { + OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); + } else { + OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); + } + /* extension channel */ + if (rxclear & HAL_RX_CLEAR_EXT_LOW) { + OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); + } else { + OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); + } +} + + +/* + * HAL support code for force ppm tracking workaround. + */ + +u_int32_t +ar9300_ppm_get_rssi_dump(struct ath_hal *ah) +{ + u_int32_t retval; + u_int32_t off1; + u_int32_t off2; + + if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { + off1 = 0x2000; + off2 = 0x1000; + } else { + off1 = 0x1000; + off2 = 0x2000; + } + + retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) | + ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) | + ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16); + + return retval; +} + +u_int32_t +ar9300_ppm_force(struct ath_hal *ah) +{ + u_int32_t data_fine; + u_int32_t data4; + //u_int32_t off1; + //u_int32_t off2; + HAL_BOOL signed_val = AH_FALSE; + +// if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { +// off1 = 0x2000; +// off2 = 0x1000; +// } else { +// off1 = 0x1000; +// off2 = 0x2000; +// } + data_fine = + AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK & + OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF); + + /* + * bit [11-0] is new ppm value. bit 11 is the signed bit. + * So check value from bit[10:0]. + * Now get the abs val of the ppm value read in bit[0:11]. + * After that do bound check on abs value. + * if value is off limit, CAP the value and and restore signed bit. + */ + if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT) + { + /* get the positive value */ + data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; + signed_val = AH_TRUE; + } + if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT) + { + HALDEBUG(ah, HAL_DEBUG_REG_IO, + "%s Correcting ppm out of range %x\n", + __func__, (data_fine & 0x7ff)); + data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT; + } + /* + * Restore signed value if changed above. + * Use typecast to avoid compilation errors + */ + if (signed_val) { + data_fine = (-(int32_t)data_fine) & + AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; + } + + /* write value */ + data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & + ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); + OS_REG_WRITE(ah, AR_PHY_TIMING2, + data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM); + + return data_fine; +} + +void +ar9300_ppm_un_force(struct ath_hal *ah) +{ + u_int32_t data4; + + data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM; + OS_REG_WRITE(ah, AR_PHY_TIMING2, data4); +} + +u_int32_t +ar9300_ppm_arm_trigger(struct ath_hal *ah) +{ + u_int32_t val; + u_int32_t ret; + + val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY); + ret = OS_REG_READ(ah, AR_TSF_L32); + OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY, + val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK); + + /* return low word of TSF at arm time */ + return ret; +} + +int +ar9300_ppm_get_trigger(struct ath_hal *ah) +{ + if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) & + AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK) + { + /* has not triggered yet, return AH_FALSE */ + return 0; + } + + /* else triggered, return AH_TRUE */ + return 1; +} + +void +ar9300_mark_phy_inactive(struct ath_hal *ah) +{ + OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); +} + +/* DEBUG */ +u_int32_t +ar9300_ppm_get_force_state(struct ath_hal *ah) +{ + return + OS_REG_READ(ah, AR_PHY_TIMING2) & + (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); +} + +/* + * Return the Cycle counts for rx_frame, rx_clear, and tx_frame + */ +void +ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_COUNTERS* p_cnts) +{ + p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); + p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); + p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); + p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT); + p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) == + p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE; + p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) == + p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE; +} + +void +ar9300_clear_mib_counters(struct ath_hal *ah) +{ + u_int32_t reg_val; + + reg_val = OS_REG_READ(ah, AR_MIBC); + OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); + OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); +} + + +/* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */ +HAL_BOOL +ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(AH_PRIVATE(ah)->ah_curchan); + u_int32_t tmp = 0; + + if (enable) { + if (ahp->ah_rifs_enabled == AH_TRUE) { + return AH_TRUE; + } + + OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]); + OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, + ahp->ah_rifs_reg[1]); + + ahp->ah_rifs_enabled = AH_TRUE; + OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg)); + } else { + if (ahp->ah_rifs_enabled == AH_TRUE) { + ahp->ah_rifs_reg[0] = OS_REG_READ(ah, + AR_PHY_SEARCH_START_DELAY); + ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH); + } + /* Change rifs init delay to 0 */ + OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, + (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY))); + tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY); + if (is_chan_2g) { + if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { + OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500); + } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */ + OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250); + } + } else { + if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { + OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370); + } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */ + OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8); + } + } + + ahp->ah_rifs_enabled = AH_FALSE; + } + return AH_TRUE; + +} /* ar9300_set_rifs_delay () */ + +/* Set the current RIFS Rx setting */ +HAL_BOOL +ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable) +{ + /* Non-Owl 11n chips */ + if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) { + if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) { + return ar9300_set_rifs_delay(ah, enable); + } + return AH_FALSE; + } + + return AH_TRUE; +} /* ar9300_set_11n_rx_rifs () */ + +static hal_mac_hangs_t +ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg, + hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain) +{ + int i = 0; + hal_mac_hangs_t found_hangs = 0; + + if (hangs & dcu_chain_state) { + for (i = 0; i < 6; i++) { + if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) == + hang_check.dcu_chain_state) + { + found_hangs |= dcu_chain_state; + *dcu_chain = i; + } + } + for (i = 0; i < 4; i++) { + if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) == + hang_check.dcu_chain_state) + { + found_hangs |= dcu_chain_state; + *dcu_chain = i + 6; + } + } + } + + if (hangs & dcu_complete_state) { + if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) { + found_hangs |= dcu_complete_state; + } + } + + return found_hangs; + +} /* end - ar9300_compare_dbg_hang */ + +#define NUM_STATUS_READS 50 +HAL_BOOL +ar9300_detect_mac_hang(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + mac_dbg_regs_t mac_dbg; + hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0}; + hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state); + int i = 0; + u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val; + + if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) { + return AH_FALSE; + } + + OS_MEMZERO(&mac_dbg, sizeof(mac_dbg)); + + mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); + mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); + mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); + + HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n", + mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, + mac_dbg.dma_dbg_6); + + if (hang_sig1 != + ar9300_compare_dbg_hang(ah, mac_dbg, + hang_sig1_val, hang_sig1, &dcu_chain)) + { + HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n"); + return AH_FALSE; + } + + shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain); + shift_val *= 5; + + for (i = 1; i <= NUM_STATUS_READS; i++) { + if (dcu_chain < 6) { + mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); + current_dcu_chain_state = + ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f); + } else { + mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); + current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f); + } + mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); + + if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state) + || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) { + return AH_FALSE; + } + } + HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__, + ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]); + ahp->ah_hang[MAC_HANG_SIG1]++; + return AH_TRUE; + +} /* end - ar9300_detect_mac_hang */ + +/* Determine if the baseband is hung by reading the Observation Bus Register */ +HAL_BOOL +ar9300_detect_bb_hang(struct ath_hal *ah) +{ +#define N(a) (sizeof(a) / sizeof(a[0])) + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t hang_sig = 0; + int i = 0; + /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times + * + * 4 known BB hang signatures - + * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E + * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52 + * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18 + * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, + * Rx State (bits 20-24) is 0x7. + */ + hal_hw_hang_check_t hang_list [] = + { + /* Offset Reg Value Reg Mask Hang Offset */ + {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1}, + {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2}, + {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3}, + {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4} + }; + + if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR | + HAL_DFS_BB_HANG_WAR | + HAL_RX_STUCK_LOW_BB_HANG_WAR))) { + return AH_FALSE; + } + + hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1); + for (i = 1; i <= NUM_STATUS_READS; i++) { + if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) { + return AH_FALSE; + } + } + + for (i = 0; i < N(hang_list); i++) { + if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) { + ahp->ah_hang[hang_list[i].hang_offset]++; + HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d " + "sig3count=%d sig4count=%d\n", __func__, + ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2], + ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]); + return AH_TRUE; + } + } + + HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! " + "<0x806c>=0x%x\n", __func__, hang_sig); + + return AH_FALSE; + +#undef N +} /* end - ar9300_detect_bb_hang () */ + +#undef NUM_STATUS_READS + +HAL_STATUS +ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + u_int16_t ant_config; + u_int32_t hal_num_ant_config; + + hal_num_ant_config = IS_CHAN_2GHZ(chan) ? + p_cap->hal_num_ant_cfg_2ghz : p_cap->hal_num_ant_cfg_5ghz; + + if (cfg < hal_num_ant_config) { + if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) { + OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); + return HAL_OK; + } + } + + return HAL_EINVAL; +} + +/* + * Functions to get/set DCS mode + */ +void +ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode) +{ + AH_PRIVATE(ah)->ah_dcs_enable = mode; +} + +u_int32_t +ar9300_get_dcs_mode(struct ath_hal *ah) +{ + return AH_PRIVATE(ah)->ah_dcs_enable; +} + +#ifdef ATH_BT_COEX +void +ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + ahp->ah_bt_module = btinfo->bt_module; + ahp->ah_bt_coex_config_type = btinfo->bt_coex_config; + ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active; + ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority; + ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active; + ahp->ah_bt_active_polarity = btinfo->bt_active_polarity; + ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant; + ahp->ah_bt_wlan_isolation = btinfo->bt_isolation; +} + +void +ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL rx_clear_polarity; + + /* + * For Kiwi and Osprey, the polarity of rx_clear is active high. + * The bt_rxclear_polarity flag from ath_dev needs to be inverted. + */ + rx_clear_polarity = !btconf->bt_rxclear_polarity; + + ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) | + SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | + SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | + SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | + SM(btconf->bt_mode, AR_BT_MODE) | + SM(btconf->bt_quiet_collision, AR_BT_QUIET) | + SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) | + SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | + SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); + + ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR); + + if (ahp->ah_bt_coex_single_ant == AH_FALSE) { + /* Enable ACK to go out even though BT has higher priority. */ + ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; + } +} + +void +ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + /* clear the old value, then set the new value */ + ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH; + ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH); +} + +void +ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT; + ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT; + ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT; + ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT; + + switch (stomp_type) { + case HAL_BT_COEX_STOMP_ALL: + ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0; + ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1; + break; + case HAL_BT_COEX_STOMP_LOW: + ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0; + ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1; + break; + case HAL_BT_COEX_STOMP_ALL_FORCE: + ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0; + ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1; + break; + case HAL_BT_COEX_STOMP_LOW_FORCE: + ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0; + ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1; + break; + case HAL_BT_COEX_STOMP_NONE: + case HAL_BT_COEX_NO_STOMP: + ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0; + ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1; + break; + default: + /* There is a force_weight from registry */ + ahp->ah_bt_coex_wlan_weight[0] = stomp_type; + ahp->ah_bt_coex_wlan_weight[1] = stomp_type; + break; + } +} + +void +ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + /* clear the old value, then set the new value */ + ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH; + ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH); +} + +static void +ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value) +{ + struct ath_hal_9300 *ahp = AH9300(ah); +#if ATH_ANT_DIV_COMB + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + HAL_CHANNEL *chan = (HAL_CHANNEL *) ahpriv->ah_curchan; +#endif + + if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW) + { + if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) + { + /* Config antenna diversity */ +#if ATH_ANT_DIV_COMB + ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan); +#endif + } + } +} + + +void +ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, + u_int32_t value) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + + switch (type) { + case HAL_BT_COEX_SET_ACK_PWR: + if (value) { + ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR; + } else { + ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR; + } + ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit, + ahpriv->ah_extra_txpow, 0); + break; + + case HAL_BT_COEX_ANTENNA_DIVERSITY: + if (AR_SREV_POSEIDON(ah)) { + ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW; + if (value) { + ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; + } + else { + ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; + } + ar9300_bt_coex_antenna_diversity(ah, value); + } + break; + case HAL_BT_COEX_LOWER_TX_PWR: + if (value) { + ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR; + } + else { + ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR; + } + ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit, + ahpriv->ah_extra_txpow, 0); + break; +#if ATH_SUPPORT_MCI + case HAL_BT_COEX_MCI_MAX_TX_PWR: + if ((ahpriv->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN) + { + if (value) { + ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; + ahp->ah_mci_concur_tx_en = AH_TRUE; + } + else { + ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; + ahp->ah_mci_concur_tx_en = AH_FALSE; + } + ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit, + ahpriv->ah_extra_txpow, 0); + } + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n", + ahp->ah_mci_concur_tx_en); + break; + case HAL_BT_COEX_MCI_FTP_STOMP_RX: + if (value) { + ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; + } + else { + ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; + } + break; +#endif + default: + break; + } +} + +void +ar9300_bt_coex_disable(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + /* Always drive rx_clear_external output as 0 */ + ath_hal_gpio_cfg_output(ah, ahp->ah_wlan_active_gpio_select, + HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); + + if (ahp->ah_bt_coex_single_ant == AH_TRUE) { + OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); + OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); + } + + OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); + OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0); + OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); + OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); + OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0); + OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0); + OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0); + OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0); + + ahp->ah_bt_coex_enabled = AH_FALSE; +} + +int +ar9300_bt_coex_enable(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + /* Program coex mode and weight registers to actually enable coex */ + OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode); + OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2); + OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); + OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); + OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]); + OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]); + OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]); + OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]); + + if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) { + OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); + } else { + OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); + } + + OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); + if (ahp->ah_bt_coex_single_ant == AH_TRUE) { + OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1); + } else { + OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); + } + + if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { + /* For 3-wire, configure the desired GPIO port for rx_clear */ + ath_hal_gpio_cfg_output(ah, + ahp->ah_wlan_active_gpio_select, + HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE); + } + else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && + (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) + { + /* For 2-wire, configure the desired GPIO port for TX_FRAME output */ + ath_hal_gpio_cfg_output(ah, + ahp->ah_wlan_active_gpio_select, + HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME); + } + + /* + * Enable a weak pull down on BT_ACTIVE. + * When BT device is disabled, BT_ACTIVE might be floating. + */ + OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), + (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)), + (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2))); + + ahp->ah_bt_coex_enabled = AH_TRUE; + + return 0; +} + +u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) +{ + return 0; +} + +u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) +{ + return bOn; +} + +void +ar9300_init_bt_coex(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { + OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), + (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | + AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); + + /* + * Set input mux for bt_prority_async and + * bt_active_async to GPIO pins + */ + OS_REG_RMW_FIELD(ah, + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), + AR_GPIO_INPUT_MUX1_BT_ACTIVE, + ahp->ah_bt_active_gpio_select); + OS_REG_RMW_FIELD(ah, + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), + AR_GPIO_INPUT_MUX1_BT_PRIORITY, + ahp->ah_bt_priority_gpio_select); + + /* Configure the desired GPIO ports for input */ + ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select); + ath_hal_gpio_cfg_input(ah, ahp->ah_bt_priority_gpio_select); + + if (ahp->ah_bt_coex_enabled) { + ar9300_bt_coex_enable(ah); + } else { + ar9300_bt_coex_disable(ah); + } + } + else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && + (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) + { + /* 2-wire */ + if (ahp->ah_bt_coex_enabled) { + /* Connect bt_active_async to baseband */ + OS_REG_CLR_BIT(ah, + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), + (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | + AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); + OS_REG_SET_BIT(ah, + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), + AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); + + /* + * Set input mux for bt_prority_async and + * bt_active_async to GPIO pins + */ + OS_REG_RMW_FIELD(ah, + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), + AR_GPIO_INPUT_MUX1_BT_ACTIVE, + ahp->ah_bt_active_gpio_select); + + /* Configure the desired GPIO ports for input */ + ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select); + + /* Enable coexistence on initialization */ + ar9300_bt_coex_enable(ah); + } + } +#if ATH_SUPPORT_MCI + else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) { + if (ahp->ah_bt_coex_enabled) { + ar9300_mci_bt_coex_enable(ah); + } + else { + ar9300_mci_bt_coex_disable(ah); + } + } +#endif /* ATH_SUPPORT_MCI */ +} + +#endif /* ATH_BT_COEX */ + +HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable) +{ + u_int32_t val; + int wasp_mm_rev; + +#define AR_SOC_RST_REVISION_ID 0xB8060090 +#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) + wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) & + AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >> + AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT; +#undef AR_SOC_RST_REVISION_ID +#undef REG_READ + + /* + * Azimuth (ProxySTA) Mode is only supported correctly by + * Peacock or WASP 1.3.0.1 or later (hopefully) chips. + * + * Enable this feature for Scorpion at this time. The silicon + * still needs to be validated. + */ + if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && + !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) && + !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) && + ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) || + (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 && + wasp_mm_rev >= 0 /* 1 */)))) + { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, " + "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n", + __func__, AH_PRIVATE((ah))->ah_macVersion, + AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev); + return HAL_ENOTSUPP; + } + + OS_REG_WRITE(ah, + AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996); + + /* turn on mode bit[24] for proxy sta */ + OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, + OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA); + + val = OS_REG_READ(ah, AR_AZIMUTH_MODE); + if (enable) { + val |= AR_AZIMUTH_KEY_SEARCH_AD1 | + AR_AZIMUTH_CTS_MATCH_TX_AD2 | + AR_AZIMUTH_BA_USES_AD1; + /* turn off filter pass hold (bit 9) */ + val &= ~AR_AZIMUTH_FILTER_PASS_HOLD; + } else { + val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 | + AR_AZIMUTH_CTS_MATCH_TX_AD2 | + AR_AZIMUTH_BA_USES_AD1); + } + OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val); + + /* enable promiscous mode */ + OS_REG_WRITE(ah, AR_RX_FILTER, + OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM); + /* enable promiscous in azimuth mode */ + OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE); + OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE); + + /* turn on filter pass hold (bit 9) */ + OS_REG_WRITE(ah, AR_AZIMUTH_MODE, + OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD); + + return HAL_OK; +} + +void ar9300_mat_enable(struct ath_hal *ah, int enable) +{ + /* + * MAT (s/w ProxySTA) implementation requires to turn off interrupt + * mitigation and turn on key search always for better performance. + */ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ath_hal_private *ap = AH_PRIVATE(ah); + + ahp->ah_intr_mitigation_rx = !enable; + if (ahp->ah_intr_mitigation_rx) { + /* + * Enable Interrupt Mitigation for Rx. + * If no build-specific limits for the rx interrupt mitigation + * timer have been specified, use conservative defaults. + */ + #ifndef AH_RIMT_VAL_LAST + #define AH_RIMT_LAST_MICROSEC 500 + #endif + #ifndef AH_RIMT_VAL_FIRST + #define AH_RIMT_FIRST_MICROSEC 2000 + #endif + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC); + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC); + } else { + OS_REG_WRITE(ah, AR_RIMT, 0); + } + + ap->ah_enable_keysearch_always = !!enable; + ar9300_enable_keysearch_always(ah, ap->ah_enable_keysearch_always); +} + + +void ar9300_enable_tpc(struct ath_hal *ah) +{ + u_int32_t val = 0; + + AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = 1; + + /* Enable TPC */ + OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1); + + /* + * Disable per chain power reduction since we are already + * accounting for this in our calculations + */ + val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB); + if (AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, + val & AR_PHY_POWER_TX_SUB_2_DISABLE); + } else { + OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, + val & AR_PHY_POWER_TX_SUB_3_DISABLE); + } +} + + +/* + * ar9300_force_tsf_sync + * This function forces the TSF sync to the given bssid, this is implemented + * as a temp hack to get the AoW demo, and is primarily used in the WDS client + * mode of operation, where we sync the TSF to RootAP TSF values + */ +void +ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, + u_int16_t assoc_id) +{ + ar9300_set_operating_mode(ah, HAL_M_STA); + ar9300_write_associd(ah, bssid, assoc_id); +} + +void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val; + u_int32_t temp_powertx_rate9_reg_val; + int8_t olpc_power_offset = 0; + int8_t tmp_olpc_val = 0; + HAL_RSSI_TX_POWER old_greentx_status; + u_int8_t target_power_val_t[ar9300_rate_size]; + int8_t tmp_rss1_thr1, tmp_rss1_thr2; + + if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) || + !AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable) { + return; + } + + old_greentx_status = AH_PRIVATE(ah)->green_tx_status; + if (ahp->ah_hw_green_tx_enable) { + tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB; + tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB; + } else { + tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB; + tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB; + } + + if ((AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S1) + && (rssi > tmp_rss1_thr1)) + { + if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) { + AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT; + } + } else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S2 + && (rssi > tmp_rss1_thr2)) + { + if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) { + AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE; + } + } else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) { + if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) { + AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG; + } + } + + /* If status is not change, don't do anything */ + if (old_greentx_status == AH_PRIVATE(ah)->green_tx_status) { + return; + } + + /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */ + if ((AH_PRIVATE(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE) + && AR_SREV_POSEIDON(ah)) + { + if (ahp->ah_hw_green_tx_enable) { + switch (AH_PRIVATE(ah)->green_tx_status) { + case HAL_RSSI_TX_POWER_SHORT: + /* 1. TxPower Config */ + OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short, + sizeof(target_power_val_t)); + /* 1.1 Store OLPC Delta Calibration Offset*/ + olpc_power_offset = 0; + /* 2. Store OB/DB */ + /* 3. Store TPC settting */ + temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | + SM(14, AR_TPC_CTS) | + SM(14, AR_TPC_CHIRP) | + SM(14, AR_TPC_RPT)); + /* 4. Store BB_powertx_rate9 value */ + temp_powertx_rate9_reg_val = + AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE; + break; + case HAL_RSSI_TX_POWER_MIDDLE: + /* 1. TxPower Config */ + OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle, + sizeof(target_power_val_t)); + /* 1.1 Store OLPC Delta Calibration Offset*/ + olpc_power_offset = 0; + /* 2. Store OB/DB */ + /* 3. Store TPC settting */ + temp_tcp_reg_val = (SM(18, AR_TPC_ACK) | + SM(18, AR_TPC_CTS) | + SM(18, AR_TPC_CHIRP) | + SM(18, AR_TPC_RPT)); + /* 4. Store BB_powertx_rate9 value */ + temp_powertx_rate9_reg_val = + AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE; + break; + case HAL_RSSI_TX_POWER_LONG: + default: + /* 1. TxPower Config */ + OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, + sizeof(target_power_val_t)); + /* 1.1 Store OLPC Delta Calibration Offset*/ + olpc_power_offset = 0; + /* 2. Store OB/DB1/DB2 */ + /* 3. Store TPC settting */ + temp_tcp_reg_val = + AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; + /* 4. Store BB_powertx_rate9 value */ + temp_powertx_rate9_reg_val = + AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; + break; + } + } else { + switch (AH_PRIVATE(ah)->green_tx_status) { + case HAL_RSSI_TX_POWER_SHORT: + /* 1. TxPower Config */ + OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short, + sizeof(target_power_val_t)); + /* 1.1 Store OLPC Delta Calibration Offset*/ + olpc_power_offset = + wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] - + wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; + /* 2. Store OB/DB */ + temp_obdb_reg_val = + AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; + temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | + AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | + AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | + AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); + temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | + SM(WB225_OB_GREEN_TX_SHORT_VALUE, + AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | + SM(WB225_OB_GREEN_TX_SHORT_VALUE, + AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | + SM(WB225_OB_GREEN_TX_SHORT_VALUE, + AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); + /* 3. Store TPC settting */ + temp_tcp_reg_val = (SM(6, AR_TPC_ACK) | + SM(6, AR_TPC_CTS) | + SM(6, AR_TPC_CHIRP) | + SM(6, AR_TPC_RPT)); + /* 4. Store BB_powertx_rate9 value */ + temp_powertx_rate9_reg_val = + WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE; + break; + case HAL_RSSI_TX_POWER_MIDDLE: + /* 1. TxPower Config */ + OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle, + sizeof(target_power_val_t)); + /* 1.1 Store OLPC Delta Calibration Offset*/ + olpc_power_offset = + wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] - + wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; + /* 2. Store OB/DB */ + temp_obdb_reg_val = + AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; + temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | + AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | + AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | + AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); + temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | + SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, + AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | + SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, + AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | + SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, + AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); + /* 3. Store TPC settting */ + temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | + SM(14, AR_TPC_CTS) | + SM(14, AR_TPC_CHIRP) | + SM(14, AR_TPC_RPT)); + /* 4. Store BB_powertx_rate9 value */ + temp_powertx_rate9_reg_val = + WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE; + break; + case HAL_RSSI_TX_POWER_LONG: + default: + /* 1. TxPower Config */ + OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, + sizeof(target_power_val_t)); + /* 1.1 Store OLPC Delta Calibration Offset*/ + olpc_power_offset = + wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] - + wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; + /* 2. Store OB/DB1/DB2 */ + temp_obdb_reg_val = + AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; + /* 3. Store TPC settting */ + temp_tcp_reg_val = + AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; + /* 4. Store BB_powertx_rate9 value */ + temp_powertx_rate9_reg_val = + AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; + break; + } + } + /* 1.1 Do OLPC Delta Calibration Offset */ + tmp_olpc_val = + (int8_t) AH_PRIVATE(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET]; + tmp_olpc_val += olpc_power_offset; + OS_REG_RMW(ah, AR_PHY_TPC_11_B0, + (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S), + AR_PHY_TPC_OLPC_GAIN_DELTA); + + /* 1.2 TxPower Config */ + ar9300_transmit_power_reg_write(ah, target_power_val_t); + /* 2. Config OB/DB */ + if (!ahp->ah_hw_green_tx_enable) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val); + } + /* 3. config TPC settting */ + OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val); + /* 4. config BB_powertx_rate9 value */ + OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val); + } +} + +void +ar9300_get_vow_stats( + struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags) +{ + if (vow_reg_flags & AR_REG_TX_FRM_CNT) { + p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); + } + if (vow_reg_flags & AR_REG_RX_FRM_CNT) { + p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); + } + if (vow_reg_flags & AR_REG_RX_CLR_CNT) { + p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); + } + if (vow_reg_flags & AR_REG_CYCLE_CNT) { + p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT); + } + if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) { + p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT); + } +} +/* + * ar9300_is_skip_paprd_by_greentx + * + * This function check if we need to skip PAPRD tuning + * when GreenTx in specific state. + */ +HAL_BOOL +ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah) +{ + if (AR_SREV_POSEIDON(ah) && + AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable && + ((AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) || + (AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE))) + { + return AH_TRUE; + } + return AH_FALSE; +} + +void +ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah) +{ + unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3] + unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3] + unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3] + unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3] + unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3] + struct ath_hal_9300 *ahp = AH9300(ah); + + if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, + AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, + AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, + AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, + AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, + AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0); + } +} + +void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { + if ((value == 0) || (value == 1)) { + OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, + AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value); + } + } +} + +void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah) +{ + OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC); +} + +int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah) +{ + int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL); + + /* RSSI format is 8.4. Ignore lowest four bits */ + val = val >> 4; + return val; +} + +void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, + u_int32_t rssi_threshold) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold); + + /* save value for restoring after chip reset */ + ahp->ah_beacon_rssi_threshold = rssi_threshold; +} + +void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah) +{ + OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST); +} + +void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on) +{ + if (on) { + OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | + AR_HWBCNPROC1_EXCLUDE_TIM_ELM); + } + else { + OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | + AR_HWBCNPROC1_EXCLUDE_TIM_ELM); + } +} +/* + * Gets the contents of the specified key cache entry. + */ +HAL_BOOL +ar9300_print_keycache(struct ath_hal *ah) +{ + + const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + u_int32_t key0, key1, key2, key3, key4; + u_int32_t mac_hi, mac_lo; + u_int16_t entry = 0; + u_int32_t valid = 0; + u_int32_t key_type; + + ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n"); + + for (entry = 0 ; entry < p_cap->hal_key_cache_size; entry++) { + key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry)); + key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry)); + key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry)); + key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry)); + key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry)); + + key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); + + mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry)); + mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); + + if (mac_hi & AR_KEYTABLE_VALID) { + valid = 1; + } else { + valid = 0; + } + + if ((mac_hi != 0) && (mac_lo != 0)) { + mac_hi &= ~0x8000; + mac_hi <<= 1; + mac_hi |= ((mac_lo & (1 << 31) )) >> 31; + mac_lo <<= 1; + } + + ath_hal_printf(ah, + "%03d " + "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" + " %02d %02d " + "%02x:%02x:%02x:%02x:%02x:%02x \n", + entry, + (key0 << 24) >> 24, (key0 << 16) >> 24, + (key0 << 8) >> 24, key0 >> 24, + (key1 << 24) >> 24, (key1 << 16) >> 24, + //(key1 << 8) >> 24, key1 >> 24, + (key2 << 24) >> 24, (key2 << 16) >> 24, + (key2 << 8) >> 24, key2 >> 24, + (key3 << 24) >> 24, (key3 << 16) >> 24, + //(key3 << 8) >> 24, key3 >> 24, + (key4 << 24) >> 24, (key4 << 16) >> 24, + (key4 << 8) >> 24, key4 >> 24, + valid, key_type, + (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24, + (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 ); + } + + return AH_TRUE; +} + +/* enable/disable smart antenna mode */ +HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + if (enable) { + OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); + } else { + OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); + } + + /* if scropion and smart antenna is enabled, write swcom1 with 0x440 + * and swcom2 with 0 + * FIXME Ideally these registers need to be made read from caldata. + * Until the calibration team gets them, keep them along with board + * configuration. + */ + if (enable && AR_SREV_SCORPION(ah) && + (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) { + + OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440); + OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0); + } + + ahp->ah_smartantenna_enable = enable; + return 1; +} + +#ifdef ATH_TX99_DIAG +#ifndef ATH_SUPPORT_HTC +void +ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, + u_int32_t txpower) +{ +#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) + static int16_t p_pwr_array[ar9300_rate_size] = { 0 }; + int32_t i; + + /* The max power is limited to 63 */ + if (txpower <= AR9300_MAX_RATE_POWER) { + for (i = 0; i < ar9300_rate_size; i++) { + p_pwr_array[i] = txpower; + } + } else { + for (i = 0; i < ar9300_rate_size; i++) { + p_pwr_array[i] = AR9300_MAX_RATE_POWER; + } + } + + OS_REG_WRITE(ah, 0xa458, 0); + + /* Write the OFDM power per rate set */ + /* 6 (LSB), 9, 12, 18 (MSB) */ + OS_REG_WRITE(ah, 0xa3c0, + PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) + | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) + | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) + | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) + ); + /* 24 (LSB), 36, 48, 54 (MSB) */ + OS_REG_WRITE(ah, 0xa3c4, + PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24) + | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16) + | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8) + | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) + ); + + /* Write the CCK power per rate set */ + /* 1L (LSB), reserved, 2L, 2S (MSB) */ + OS_REG_WRITE(ah, 0xa3c8, + PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) + | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) + /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */ + | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) + ); + /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ + OS_REG_WRITE(ah, 0xa3cc, + PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) + | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) + | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) + | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) + ); + + /* Write the HT20 power per rate set */ + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ + OS_REG_WRITE(ah, 0xa3d0, + PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0) + ); + + /* 6 (LSB), 7, 12, 13 (MSB) */ + OS_REG_WRITE(ah, 0xa3d4, + PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0) + ); + + /* 14 (LSB), 15, 20, 21 */ + OS_REG_WRITE(ah, 0xa3e4, + PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0) + ); + + /* Mixed HT20 and HT40 rates */ + /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ + OS_REG_WRITE(ah, 0xa3e8, + PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0) + ); + + /* Write the HT40 power per rate set */ + /* correct PAR difference between HT40 and HT20/LEGACY */ + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ + OS_REG_WRITE(ah, 0xa3d8, + PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0) + ); + + /* 6 (LSB), 7, 12, 13 (MSB) */ + OS_REG_WRITE(ah, 0xa3dc, + PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0) + ); + + /* 14 (LSB), 15, 20, 21 */ + OS_REG_WRITE(ah, 0xa3ec, + PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8) + | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0) + ); +#undef PWR_MAS +} + +void +ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) +{ + if (tx_chainmask == 0x5) { + OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, + OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); + } + OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); + OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); + + OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); + if (tx_chainmask == 0x5) { + OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, + OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); + } +} + +void +ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, + int chtype) +{ + OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff); + OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1)); + OS_REG_WRITE(ah, 0xa350, + (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13)); + + /* 11G mode */ + if (!chtype) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, + OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2)); + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, + OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24)) + & ~(0x1 << 22)); + } else { + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, + OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, + (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24)) + & ~(0x1 << 22)); + } + + /* chain zero */ + if ((tx_chain_mask & 0x01) == 0x01) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) + | (0x1 << 31) | (0x5 << 15) + | (0x3 << 9)) & ~(0x1 << 27) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7)) & ~(0x1 << 11)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, + OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, + OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); + } + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + /* chain one */ + if ((tx_chain_mask & 0x02) == 0x02 ) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, + (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) + | (0x1 << 31) | (0x5 << 15) + | (0x3 << 9)) & ~(0x1 << 27) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7)) & ~(0x1 << 11)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, + (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, + (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, + OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, + OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); + } + } + if (AR_SREV_OSPREY(ah)) { + /* chain two */ + if ((tx_chain_mask & 0x04) == 0x04 ) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, + (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) + | (0x1 << 31) | (0x5 << 15) + | (0x3 << 9)) & ~(0x1 << 27) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7)) & ~(0x1 << 11)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, + (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, + (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, + OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, + OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); + } + } + + OS_REG_WRITE(ah, 0xa28c, 0x11111); + OS_REG_WRITE(ah, 0xa288, 0x111); + } else { + /* chain zero */ + if ((tx_chain_mask & 0x01) == 0x01) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) + | (0x1 << 31) | (0x1 << 27) + | (0x3 << 23) | (0x1 << 19) + | (0x1 << 15) | (0x3 << 9)) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7) | (0x1 << 3) + | (0x1 << 2) | (0x1 << 1)) + & ~(0x1 << 11)& ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, + OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) + | (0x3 << 3) | (0x3 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) + | (0x3 << 29) | (0x3 << 26) + | (0x2 << 23) | (0x2 << 20) + | (0x2 << 17))& ~(0x1 << 14)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, + OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, + OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, + OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, + OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } else { + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, + OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, + OS_REG_READ(ah, AR_HORNET_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } + + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, + OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, + OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); + } + if (AR_SREV_OSPREY(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, + OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, + OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); + } + } + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + /* chain one */ + if ((tx_chain_mask & 0x02) == 0x02 ) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, + OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, + OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, + OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, + OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } else { + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, + OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, + OS_REG_READ(ah, AR_HORNET_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } + + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, + (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) + | (0x1 << 31) | (0x1 << 27) + | (0x3 << 23) | (0x1 << 19) + | (0x1 << 15) | (0x3 << 9)) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7) | (0x1 << 3) + | (0x1 << 2) | (0x1 << 1)) + & ~(0x1 << 11)& ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, + (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, + (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, + OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) + | (0x3 << 3) | (0x3 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, + (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) + | (0x3 << 29) | (0x3 << 26) + | (0x2 << 23) | (0x2 << 20) + | (0x2 << 17))& ~(0x1 << 14)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, + OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, + OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); + + if (AR_SREV_OSPREY(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, + OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, + OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); + } + } + } + if (AR_SREV_OSPREY(ah)) { + /* chain two */ + if ((tx_chain_mask & 0x04) == 0x04 ) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, + OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, + OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, + OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, + OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } else { + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, + OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, + OS_REG_READ(ah, AR_HORNET_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } + + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, + OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, + OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); + + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, + (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) + | (0x1 << 31) | (0x1 << 27) + | (0x3 << 23) | (0x1 << 19) + | (0x1 << 15) | (0x3 << 9)) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, + (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7) | (0x1 << 3) + | (0x1 << 2) | (0x1 << 1)) + & ~(0x1 << 11)& ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, + (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, + (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, + OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) + | (0x3 << 3) | (0x3 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, + (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) + | (0x3 << 29) | (0x3 << 26) + | (0x2 << 23) | (0x2 << 20) + | (0x2 << 17))& ~(0x1 << 14)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, + OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, + OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); + } + } + + OS_REG_WRITE(ah, 0xa28c, 0x22222); + OS_REG_WRITE(ah, 0xa288, 0x222); + } +} + +void +ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) +{ + u_int32_t val; + u_int32_t qnum = (u_int32_t)data; + + /* Disable AGC to A2 */ + OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); + OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000); + OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe); + OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); + + OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ + /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ + OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); + OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ + OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); + /* 200 ok for HT20, 400 ok for HT40 */ + OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); + OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); + + /* set QCU modes to early termination */ + val = OS_REG_READ(ah, AR_QMISC(qnum)); + OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); +} + +void +ar9300_tx99_stop(struct ath_hal *ah) +{ + /* this should follow the setting of start */ + OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); + OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); +} +#endif /* ATH_TX99_DIAG */ +#endif /* ATH_SUPPORT_HTC */ + +HAL_BOOL +ar9300Get3StreamSignature(struct ath_hal *ah) +{ + return AH_FALSE; +} + +HAL_BOOL +ar9300ForceVCS(struct ath_hal *ah) +{ + return AH_FALSE; +} + +HAL_BOOL +ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) +{ + return AH_FALSE; +} + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_osprey22.ini b/hal/ar9300/ar9300_osprey22.ini new file mode 100644 index 000000000000..9814dab95b4e --- /dev/null +++ b/hal/ar9300/ar9300_osprey22.ini @@ -0,0 +1,2188 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +static const u_int32_t ar9300_osprey_2p2_mac_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 }, + { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 }, +}; + +static const u_int32_t ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x52022470 , 0x52022470 , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x55022490 , 0x55022490 , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x59022492 , 0x59022492 , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x5d022692 , 0x5d022692 , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x61022892 , 0x61022892 , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x65024890 , 0x65024890 , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x69024892 , 0x69024892 , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x6e024c92 , 0x6e024c92 , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x12800400 , 0x12800400 }, + { 0x0000a598 , 0x21802220 , 0x21802220 , 0x16800402 , 0x16800402 }, + { 0x0000a59c , 0x27802223 , 0x27802223 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1c800603 , 0x1c800603 }, + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x21800a02 , 0x21800a02 }, + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x25800a04 , 0x25800a04 }, + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x28800a20 , 0x28800a20 }, + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2c800e20 , 0x2c800e20 }, + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x30800e22 , 0x30800e22 }, + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x34800e24 , 0x34800e24 }, + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x38801640 , 0x38801640 }, + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x3c801660 , 0x3c801660 }, + { 0x0000a5c4 , 0x52822470 , 0x52822470 , 0x3f801861 , 0x3f801861 }, + { 0x0000a5c8 , 0x55822490 , 0x55822490 , 0x43801a81 , 0x43801a81 }, + { 0x0000a5cc , 0x59822492 , 0x59822492 , 0x47801a83 , 0x47801a83 }, + { 0x0000a5d0 , 0x5d822692 , 0x5d822692 , 0x4a801c84 , 0x4a801c84 }, + { 0x0000a5d4 , 0x61822892 , 0x61822892 , 0x4e801ce3 , 0x4e801ce3 }, + { 0x0000a5d8 , 0x65824890 , 0x65824890 , 0x52801ce5 , 0x52801ce5 }, + { 0x0000a5dc , 0x69824892 , 0x69824892 , 0x56801ce9 , 0x56801ce9 }, + { 0x0000a5e0 , 0x6e824c92 , 0x6e824c92 , 0x5a801ceb , 0x5a801ceb }, + { 0x0000a5e4 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5e8 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5ec , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f0 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f4 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f8 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5fc , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x02004000 , 0x02004000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x02004801 , 0x02004801 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02808a02 , 0x02808a02 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0380ce03 , 0x0380ce03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04411104 , 0x04411104 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04411104 , 0x04411104 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x66480001 , 0x66480001 , 0x66480001 , 0x66480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x66480001 , 0x66480001 , 0x66480001 , 0x66480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x66480001 , 0x66480001 , 0x66480001 , 0x66480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300_osprey_2p2_baseband_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafa68e30 }, + { 0x00009884 , 0x00002842 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009e50 , 0x00000000 }, + { 0x00009fcc , 0x00000014 }, + { 0x0000a344 , 0x00000010 }, + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x71733d01 }, + { 0x0000a3a0 , 0xd0ad5c12 }, + { 0x0000a3c0 , 0x22222220 }, + { 0x0000a3c4 , 0x22222222 }, + { 0x0000a404 , 0x00418a11 }, + { 0x0000a418 , 0x050001ce }, + { 0x0000a438 , 0x00001800 }, + { 0x0000a458 , 0x01444452 }, + { 0x0000a690 , 0x00000038 }, + { 0x0000b8dc , 0x00400000 }, +}; + +static const u_int32_t ar9300_osprey_2p2_radio_core[][2] = { +/* Addr allmodes */ + { 0x00016000 , 0x36db6db6 }, + { 0x00016004 , 0x6db6db40 }, + { 0x00016008 , 0x73f00000 }, + { 0x0001600c , 0x00000000 }, + { 0x00016040 , 0x7f80fff8 }, + { 0x0001604c , 0x76d005b5 }, + { 0x00016050 , 0x556cf031 }, + { 0x00016054 , 0x13449440 }, + { 0x00016058 , 0x0c51c92c }, + { 0x0001605c , 0x3db7fffc }, + { 0x00016060 , 0xfffffffc }, + { 0x00016064 , 0x000f0278 }, + { 0x0001606c , 0x6db60000 }, + { 0x00016080 , 0x00000000 }, + { 0x00016084 , 0x0e48048c }, + { 0x00016088 , 0x54214514 }, + { 0x0001608c , 0x119f481e }, + { 0x00016090 , 0x24926490 }, + { 0x00016098 , 0xd2888888 }, + { 0x000160a0 , 0x0a108ffe }, + { 0x000160a4 , 0x812fc370 }, + { 0x000160a8 , 0x423c8000 }, + { 0x000160b4 , 0x92480080 }, + { 0x000160c0 , 0x00adb6d0 }, + { 0x000160c4 , 0x6db6db60 }, + { 0x000160c8 , 0x6db6db6c }, + { 0x000160cc , 0x01e6c000 }, + { 0x00016100 , 0x3fffbe01 }, + { 0x00016104 , 0xfff80000 }, + { 0x00016108 , 0x00080010 }, + { 0x00016144 , 0x02084080 }, + { 0x00016148 , 0x00000000 }, + { 0x00016280 , 0x058a0001 }, + { 0x00016284 , 0x3d840208 }, + { 0x00016288 , 0x05a20408 }, + { 0x0001628c , 0x00038c07 }, + { 0x00016290 , 0x00000004 }, + { 0x00016294 , 0x458a214f }, + { 0x00016380 , 0x00000000 }, + { 0x00016384 , 0x00000000 }, + { 0x00016388 , 0x00800700 }, + { 0x0001638c , 0x00800700 }, + { 0x00016390 , 0x00800700 }, + { 0x00016394 , 0x00000000 }, + { 0x00016398 , 0x00000000 }, + { 0x0001639c , 0x00000000 }, + { 0x000163a0 , 0x00000001 }, + { 0x000163a4 , 0x00000001 }, + { 0x000163a8 , 0x00000000 }, + { 0x000163ac , 0x00000000 }, + { 0x000163b0 , 0x00000000 }, + { 0x000163b4 , 0x00000000 }, + { 0x000163b8 , 0x00000000 }, + { 0x000163bc , 0x00000000 }, + { 0x000163c0 , 0x000000a0 }, + { 0x000163c4 , 0x000c0000 }, + { 0x000163c8 , 0x14021402 }, + { 0x000163cc , 0x00001402 }, + { 0x000163d0 , 0x00000000 }, + { 0x000163d4 , 0x00000000 }, + { 0x00016400 , 0x36db6db6 }, + { 0x00016404 , 0x6db6db40 }, + { 0x00016408 , 0x73f00000 }, + { 0x0001640c , 0x00000000 }, + { 0x00016440 , 0x7f80fff8 }, + { 0x0001644c , 0x76d005b5 }, + { 0x00016450 , 0x556cf031 }, + { 0x00016454 , 0x13449440 }, + { 0x00016458 , 0x0c51c92c }, + { 0x0001645c , 0x3db7fffc }, + { 0x00016460 , 0xfffffffc }, + { 0x00016464 , 0x000f0278 }, + { 0x0001646c , 0x6db60000 }, + { 0x00016500 , 0x3fffbe01 }, + { 0x00016504 , 0xfff80000 }, + { 0x00016508 , 0x00080010 }, + { 0x00016544 , 0x02084080 }, + { 0x00016548 , 0x00000000 }, + { 0x00016780 , 0x00000000 }, + { 0x00016784 , 0x00000000 }, + { 0x00016788 , 0x00800700 }, + { 0x0001678c , 0x00800700 }, + { 0x00016790 , 0x00800700 }, + { 0x00016794 , 0x00000000 }, + { 0x00016798 , 0x00000000 }, + { 0x0001679c , 0x00000000 }, + { 0x000167a0 , 0x00000001 }, + { 0x000167a4 , 0x00000001 }, + { 0x000167a8 , 0x00000000 }, + { 0x000167ac , 0x00000000 }, + { 0x000167b0 , 0x00000000 }, + { 0x000167b4 , 0x00000000 }, + { 0x000167b8 , 0x00000000 }, + { 0x000167bc , 0x00000000 }, + { 0x000167c0 , 0x000000a0 }, + { 0x000167c4 , 0x000c0000 }, + { 0x000167c8 , 0x14021402 }, + { 0x000167cc , 0x00001402 }, + { 0x000167d0 , 0x00000000 }, + { 0x000167d4 , 0x00000000 }, + { 0x00016800 , 0x36db6db6 }, + { 0x00016804 , 0x6db6db40 }, + { 0x00016808 , 0x73f00000 }, + { 0x0001680c , 0x00000000 }, + { 0x00016840 , 0x7f80fff8 }, + { 0x0001684c , 0x76d005b5 }, + { 0x00016850 , 0x556cf031 }, + { 0x00016854 , 0x13449440 }, + { 0x00016858 , 0x0c51c92c }, + { 0x0001685c , 0x3db7fffc }, + { 0x00016860 , 0xfffffffc }, + { 0x00016864 , 0x000f0278 }, + { 0x0001686c , 0x6db60000 }, + { 0x00016900 , 0x3fffbe01 }, + { 0x00016904 , 0xfff80000 }, + { 0x00016908 , 0x00080010 }, + { 0x00016944 , 0x02084080 }, + { 0x00016948 , 0x00000000 }, + { 0x00016b80 , 0x00000000 }, + { 0x00016b84 , 0x00000000 }, + { 0x00016b88 , 0x00800700 }, + { 0x00016b8c , 0x00800700 }, + { 0x00016b90 , 0x00800700 }, + { 0x00016b94 , 0x00000000 }, + { 0x00016b98 , 0x00000000 }, + { 0x00016b9c , 0x00000000 }, + { 0x00016ba0 , 0x00000001 }, + { 0x00016ba4 , 0x00000001 }, + { 0x00016ba8 , 0x00000000 }, + { 0x00016bac , 0x00000000 }, + { 0x00016bb0 , 0x00000000 }, + { 0x00016bb4 , 0x00000000 }, + { 0x00016bb8 , 0x00000000 }, + { 0x00016bbc , 0x00000000 }, + { 0x00016bc0 , 0x000000a0 }, + { 0x00016bc4 , 0x000c0000 }, + { 0x00016bc8 , 0x14021402 }, + { 0x00016bcc , 0x00001402 }, + { 0x00016bd0 , 0x00000000 }, + { 0x00016bd4 , 0x00000000 }, +}; + +static const u_int32_t ar9300_osprey_2p2_tx_gain_table_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000000d5 , 0x000000d5 , 0x000000d5 , 0x000000d5 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x00004002 , 0x00004002 , 0x00004002 , 0x00004002 }, + { 0x0000a508 , 0x00008004 , 0x00008004 , 0x00008004 , 0x00008004 }, + { 0x0000a510 , 0x0001000c , 0x0001000c , 0x0001000c , 0x0001000c }, + { 0x0000a514 , 0x0001420b , 0x0001420b , 0x0001420b , 0x0001420b }, + { 0x0000a518 , 0x0001824a , 0x0001824a , 0x0001824a , 0x0001824a }, + { 0x0000a51c , 0x0001c44a , 0x0001c44a , 0x0001c44a , 0x0001c44a }, + { 0x0000a520 , 0x0002064a , 0x0002064a , 0x0002064a , 0x0002064a }, + { 0x0000a524 , 0x0002484a , 0x0002484a , 0x0002484a , 0x0002484a }, + { 0x0000a528 , 0x00028a4a , 0x00028a4a , 0x00028a4a , 0x00028a4a }, + { 0x0000a52c , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a }, + { 0x0000a530 , 0x00030e4a , 0x00030e4a , 0x00030e4a , 0x00030e4a }, + { 0x0000a534 , 0x00034e8a , 0x00034e8a , 0x00034e8a , 0x00034e8a }, +}; + +static const u_int32_t ar9300_osprey_2p2_baseband_postamble_dfs_channel[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00009824 , 0x5ac668d0 , 0x5ac668d0 }, + { 0x00009e0c , 0x6d4000e2 , 0x6d4000e2 }, + { 0x00009e14 , 0x37b9625e , 0x37b9625e }, +}; + +static const u_int32_t ar9300Modes_fast_clock_osprey_2p2[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00001030 , 0x00000268 , 0x000004d0 }, + { 0x00001070 , 0x0000018c , 0x00000318 }, + { 0x000010b0 , 0x00000fd0 , 0x00001fa0 }, + { 0x00008014 , 0x044c044c , 0x08980898 }, + { 0x0000801c , 0x148ec02b , 0x148ec057 }, + { 0x00008318 , 0x000044c0 , 0x00008980 }, + { 0x00009e00 , 0x0372131c , 0x0372131c }, + { 0x0000a230 , 0x0000000b , 0x00000016 }, + { 0x0000a254 , 0x00000898 , 0x00001130 }, +}; + +static const u_int32_t ar9300_osprey_2p2_radio_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0001609c , 0x0dd08f29 , 0x0dd08f29 , 0x0b283f31 , 0x0b283f31 }, + { 0x000160ac , 0xa4653c00 , 0xa4653c00 , 0x24652800 , 0x24652800 }, + { 0x000160b0 , 0x03284f3e , 0x03284f3e , 0x05d08f20 , 0x05d08f20 }, + { 0x0001610c , 0xc8000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016140 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, + { 0x0001650c , 0xc8000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016540 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, + { 0x0001690c , 0xc8000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016940 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, +}; + +static const u_int32_t ar9300_modes_number_5_tx_gain_table_osprey_2p2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x15000028 , 0x15000028 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1b00002b , 0x1b00002b , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x1f020028 , 0x1f020028 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x2502002b , 0x2502002b , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2a04002a , 0x2a04002a , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2e06002a , 0x2e06002a , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x3302202d , 0x3302202d , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3804202c , 0x3804202c , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3c06202c , 0x3c06202c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4108202d , 0x4108202d , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4506402d , 0x4506402d , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4906222d , 0x4906222d , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4d062231 , 0x4d062231 , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x50082231 , 0x50082231 , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5608422e , 0x5608422e , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5e08442e , 0x5e08442e , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x620a4431 , 0x620a4431 , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x640a4432 , 0x640a4432 , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x680a4434 , 0x680a4434 , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x6c0a6434 , 0x6c0a6434 , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x6f0a6633 , 0x6f0a6633 , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01804601 , 0x01804601 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01804601 , 0x01804601 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x01804601 , 0x01804601 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x03408d02 , 0x03408d02 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x03410d04 , 0x03410d04 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x65240001 , 0x65240001 , 0x66480001 , 0x66480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x65240001 , 0x65240001 , 0x66480001 , 0x66480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x65240001 , 0x65240001 , 0x66480001 , 0x66480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300_osprey_2p2_mac_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00000030 , 0x00020085 }, + { 0x00000044 , 0x00000008 }, + { 0x0000805c , 0xffffc7ff }, + { 0x00008344 , 0xaa4a105b }, +}; + +static const u_int32_t ar9300_osprey_2p2_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e3c , 0xcf946221 , 0xcf946221 , 0xcf946221 , 0xcf946221 }, + { 0x00009e44 , 0x005c0000 , 0x005c0000 , 0x005c0000 , 0x005c0000 }, + { 0x0000a258 , 0x02020200 , 0x02020200 , 0x02020200 , 0x02020200 }, + { 0x0000a25c , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a28c , 0x00011111 , 0x00011111 , 0x00011111 , 0x00011111 }, + { 0x0000a2c4 , 0x00148d18 , 0x00148d18 , 0x00148d20 , 0x00148d20 }, + { 0x0000a2d8 , 0xf999a801 , 0xf999a801 , 0xf999a80d , 0xf999a80d }, + { 0x0000a50c , 0x0000c00a , 0x0000c00a , 0x0000c00a , 0x0000c00a }, + { 0x0000a538 , 0x00038e8c , 0x00038e8c , 0x00038e8c , 0x00038e8c }, + { 0x0000a53c , 0x0003cecc , 0x0003cecc , 0x0003cecc , 0x0003cecc }, + { 0x0000a540 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 }, + { 0x0000a544 , 0x00044edc , 0x00044edc , 0x00044edc , 0x00044edc }, + { 0x0000a548 , 0x00048ede , 0x00048ede , 0x00048ede , 0x00048ede }, + { 0x0000a54c , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e }, + { 0x0000a550 , 0x00050f5e , 0x00050f5e , 0x00050f5e , 0x00050f5e }, + { 0x0000a554 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000be18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +}; + +static const u_int32_t ar9300_osprey_2p2_baseband_core[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009804 , 0xfd14e000 }, + { 0x00009808 , 0x9c0a9f6b }, + { 0x0000980c , 0x04900000 }, + { 0x00009814 , 0x9280c00a }, + { 0x00009818 , 0x00000000 }, + { 0x0000981c , 0x00020028 }, + { 0x00009834 , 0x6400a190 }, + { 0x00009838 , 0x0108ecff }, + { 0x0000983c , 0x14000600 }, + { 0x00009880 , 0x201fff00 }, + { 0x00009884 , 0x00001042 }, + { 0x000098a4 , 0x00200400 }, + { 0x000098b0 , 0x32840bbe }, + { 0x000098d0 , 0x004b6a8e }, + { 0x000098d4 , 0x00000820 }, + { 0x000098dc , 0x00000000 }, + { 0x000098f0 , 0x00000000 }, + { 0x000098f4 , 0x00000000 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009c0c , 0x00000000 }, + { 0x00009c10 , 0x00000000 }, + { 0x00009c14 , 0x00046384 }, + { 0x00009c18 , 0x05b6b440 }, + { 0x00009c1c , 0x00b6b440 }, + { 0x00009d00 , 0xc080a333 }, + { 0x00009d04 , 0x40206c10 }, + { 0x00009d08 , 0x009c4060 }, + { 0x00009d0c , 0x9883800a }, + { 0x00009d10 , 0x01834061 }, + { 0x00009d14 , 0x00c0040b }, + { 0x00009d18 , 0x00000000 }, + { 0x00009e08 , 0x0038230c }, + { 0x00009e24 , 0x990bb515 }, + { 0x00009e28 , 0x0c6f0000 }, + { 0x00009e30 , 0x06336f77 }, + { 0x00009e34 , 0x6af6532f }, + { 0x00009e38 , 0x0cc80c00 }, + { 0x00009e40 , 0x0d261820 }, + { 0x00009e4c , 0x00001004 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009e54 , 0x00000000 }, + { 0x00009fc0 , 0x803e4788 }, + { 0x00009fc4 , 0x0001efb5 }, + { 0x00009fcc , 0x40000014 }, + { 0x00009fd0 , 0x01193b93 }, + { 0x0000a20c , 0x00000000 }, + { 0x0000a220 , 0x00000000 }, + { 0x0000a224 , 0x00000000 }, + { 0x0000a228 , 0x10002310 }, + { 0x0000a23c , 0x00000000 }, + { 0x0000a244 , 0x0c000000 }, + { 0x0000a2a0 , 0x00000001 }, + { 0x0000a2c0 , 0x00000001 }, + { 0x0000a2c8 , 0x00000000 }, + { 0x0000a2cc , 0x18c43433 }, + { 0x0000a2d4 , 0x00000000 }, + { 0x0000a2ec , 0x00000000 }, + { 0x0000a2f0 , 0x00000000 }, + { 0x0000a2f4 , 0x00000000 }, + { 0x0000a2f8 , 0x00000000 }, + { 0x0000a344 , 0x00000000 }, + { 0x0000a34c , 0x00000000 }, + { 0x0000a350 , 0x0000a000 }, + { 0x0000a364 , 0x00000000 }, + { 0x0000a370 , 0x00000000 }, + { 0x0000a390 , 0x00000001 }, + { 0x0000a394 , 0x00000444 }, + { 0x0000a398 , 0x001f0e0f }, + { 0x0000a39c , 0x0075393f }, + { 0x0000a3a0 , 0xb79f6427 }, + { 0x0000a3a4 , 0x00000000 }, + { 0x0000a3a8 , 0xaaaaaaaa }, + { 0x0000a3ac , 0x3c466478 }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a3c8 , 0x20200020 }, + { 0x0000a3cc , 0x20202020 }, + { 0x0000a3d0 , 0x20202020 }, + { 0x0000a3d4 , 0x20202020 }, + { 0x0000a3d8 , 0x20202020 }, + { 0x0000a3dc , 0x20202020 }, + { 0x0000a3e0 , 0x20202020 }, + { 0x0000a3e4 , 0x20202020 }, + { 0x0000a3e8 , 0x20202020 }, + { 0x0000a3ec , 0x20202020 }, + { 0x0000a3f0 , 0x00000000 }, + { 0x0000a3f4 , 0x00000000 }, + { 0x0000a3f8 , 0x0c9bd380 }, + { 0x0000a3fc , 0x000f0f01 }, + { 0x0000a400 , 0x8fa91f01 }, + { 0x0000a404 , 0x00000000 }, + { 0x0000a408 , 0x0e79e5c6 }, + { 0x0000a40c , 0x00820820 }, + { 0x0000a414 , 0x1ce739ce }, + { 0x0000a418 , 0x2d001dce }, + { 0x0000a41c , 0x1ce739ce }, + { 0x0000a420 , 0x000001ce }, + { 0x0000a424 , 0x1ce739ce }, + { 0x0000a428 , 0x000001ce }, + { 0x0000a42c , 0x1ce739ce }, + { 0x0000a430 , 0x1ce739ce }, + { 0x0000a434 , 0x00000000 }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a43c , 0x00100000 }, + { 0x0000a440 , 0x00000000 }, + { 0x0000a444 , 0x00000000 }, + { 0x0000a448 , 0x05000080 }, + { 0x0000a44c , 0x00000001 }, + { 0x0000a450 , 0x00010000 }, + { 0x0000a458 , 0x00000000 }, + { 0x0000a640 , 0x00000000 }, + { 0x0000a644 , 0x3fad9d74 }, + { 0x0000a648 , 0x0048060a }, + { 0x0000a64c , 0x00003c37 }, + { 0x0000a670 , 0x03020100 }, + { 0x0000a674 , 0x09080504 }, + { 0x0000a678 , 0x0d0c0b0a }, + { 0x0000a67c , 0x13121110 }, + { 0x0000a680 , 0x31301514 }, + { 0x0000a684 , 0x35343332 }, + { 0x0000a688 , 0x00000036 }, + { 0x0000a690 , 0x00000838 }, + { 0x0000a7c0 , 0x00000000 }, + { 0x0000a7c4 , 0xfffffffc }, + { 0x0000a7c8 , 0x00000000 }, + { 0x0000a7cc , 0x00000000 }, + { 0x0000a7d0 , 0x00000000 }, + { 0x0000a7d4 , 0x00000004 }, + { 0x0000a7dc , 0x00000001 }, + { 0x0000a8d0 , 0x004b6a8e }, + { 0x0000a8d4 , 0x00000820 }, + { 0x0000a8dc , 0x00000000 }, + { 0x0000a8f0 , 0x00000000 }, + { 0x0000a8f4 , 0x00000000 }, + { 0x0000b2d0 , 0x00000080 }, + { 0x0000b2d4 , 0x00000000 }, + { 0x0000b2ec , 0x00000000 }, + { 0x0000b2f0 , 0x00000000 }, + { 0x0000b2f4 , 0x00000000 }, + { 0x0000b2f8 , 0x00000000 }, + { 0x0000b408 , 0x0e79e5c0 }, + { 0x0000b40c , 0x00820820 }, + { 0x0000b420 , 0x00000000 }, + { 0x0000b8d0 , 0x004b6a8e }, + { 0x0000b8d4 , 0x00000820 }, + { 0x0000b8dc , 0x00000000 }, + { 0x0000b8f0 , 0x00000000 }, + { 0x0000b8f4 , 0x00000000 }, + { 0x0000c2d0 , 0x00000080 }, + { 0x0000c2d4 , 0x00000000 }, + { 0x0000c2ec , 0x00000000 }, + { 0x0000c2f0 , 0x00000000 }, + { 0x0000c2f4 , 0x00000000 }, + { 0x0000c2f8 , 0x00000000 }, + { 0x0000c408 , 0x0e79e5c0 }, + { 0x0000c40c , 0x00820820 }, + { 0x0000c420 , 0x00000000 }, +}; + +static const u_int32_t ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d4 , 0x000050d4 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x04002222 , 0x04002222 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x09002421 , 0x09002421 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x0d002621 , 0x0d002621 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x13004620 , 0x13004620 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x19004a20 , 0x19004a20 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x1d004e20 , 0x1d004e20 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x21005420 , 0x21005420 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x26005e20 , 0x26005e20 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x2b005e40 , 0x2b005e40 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x2f005e42 , 0x2f005e42 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x33005e44 , 0x33005e44 , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x38005e65 , 0x38005e65 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x3c005e69 , 0x3c005e69 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x40005e6b , 0x40005e6b , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x44005e6d , 0x44005e6d , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x49005e72 , 0x49005e72 , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x4e005eb2 , 0x4e005eb2 , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x53005f12 , 0x53005f12 , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x59025eb2 , 0x59025eb2 , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x5e025f12 , 0x5e025f12 , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x61027f12 , 0x61027f12 , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x6702bf12 , 0x6702bf12 , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x6b02bf14 , 0x6b02bf14 , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x6f02bf16 , 0x6f02bf16 , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a580 , 0x00802220 , 0x00802220 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x04802222 , 0x04802222 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x09802421 , 0x09802421 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x0d802621 , 0x0d802621 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x13804620 , 0x13804620 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x19804a20 , 0x19804a20 , 0x11800400 , 0x11800400 }, + { 0x0000a598 , 0x1d804e20 , 0x1d804e20 , 0x15800402 , 0x15800402 }, + { 0x0000a59c , 0x21805420 , 0x21805420 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x26805e20 , 0x26805e20 , 0x1b800603 , 0x1b800603 }, + { 0x0000a5a4 , 0x2b805e40 , 0x2b805e40 , 0x1f800a02 , 0x1f800a02 }, + { 0x0000a5a8 , 0x2f805e42 , 0x2f805e42 , 0x23800a04 , 0x23800a04 }, + { 0x0000a5ac , 0x33805e44 , 0x33805e44 , 0x26800a20 , 0x26800a20 }, + { 0x0000a5b0 , 0x38805e65 , 0x38805e65 , 0x2a800e20 , 0x2a800e20 }, + { 0x0000a5b4 , 0x3c805e69 , 0x3c805e69 , 0x2e800e22 , 0x2e800e22 }, + { 0x0000a5b8 , 0x40805e6b , 0x40805e6b , 0x31800e24 , 0x31800e24 }, + { 0x0000a5bc , 0x44805e6d , 0x44805e6d , 0x34801640 , 0x34801640 }, + { 0x0000a5c0 , 0x49805e72 , 0x49805e72 , 0x38801660 , 0x38801660 }, + { 0x0000a5c4 , 0x4e805eb2 , 0x4e805eb2 , 0x3b801861 , 0x3b801861 }, + { 0x0000a5c8 , 0x53805f12 , 0x53805f12 , 0x3e801a81 , 0x3e801a81 }, + { 0x0000a5cc , 0x59825eb2 , 0x59825eb2 , 0x42801a83 , 0x42801a83 }, + { 0x0000a5d0 , 0x5e825f12 , 0x5e825f12 , 0x44801c84 , 0x44801c84 }, + { 0x0000a5d4 , 0x61827f12 , 0x61827f12 , 0x48801ce3 , 0x48801ce3 }, + { 0x0000a5d8 , 0x6782bf12 , 0x6782bf12 , 0x4c801ce5 , 0x4c801ce5 }, + { 0x0000a5dc , 0x6b82bf14 , 0x6b82bf14 , 0x50801ce9 , 0x50801ce9 }, + { 0x0000a5e0 , 0x6f82bf16 , 0x6f82bf16 , 0x54801ceb , 0x54801ceb }, + { 0x0000a5e4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5e8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5ec , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5f0 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5f4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5f8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5fc , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00804000 , 0x00804000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x00804201 , 0x00804201 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x0280c802 , 0x0280c802 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x0280ca03 , 0x0280ca03 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x04c15104 , 0x04c15104 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04c15305 , 0x04c15305 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04c15305 , 0x04c15305 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016048 , 0x8e480001 , 0x8e480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016448 , 0x8e480001 , 0x8e480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016848 , 0x8e480001 , 0x8e480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300_osprey_2p2_mac_core[][2] = { +/* Addr allmodes */ + { 0x00000008 , 0x00000000 }, + { 0x00000030 , 0x00020085 }, + { 0x00000034 , 0x00000005 }, + { 0x00000040 , 0x00000000 }, + { 0x00000044 , 0x00000000 }, + { 0x00000048 , 0x00000008 }, + { 0x0000004c , 0x00000010 }, + { 0x00000050 , 0x00000000 }, + { 0x00001040 , 0x002ffc0f }, + { 0x00001044 , 0x002ffc0f }, + { 0x00001048 , 0x002ffc0f }, + { 0x0000104c , 0x002ffc0f }, + { 0x00001050 , 0x002ffc0f }, + { 0x00001054 , 0x002ffc0f }, + { 0x00001058 , 0x002ffc0f }, + { 0x0000105c , 0x002ffc0f }, + { 0x00001060 , 0x002ffc0f }, + { 0x00001064 , 0x002ffc0f }, + { 0x000010f0 , 0x00000100 }, + { 0x00001270 , 0x00000000 }, + { 0x000012b0 , 0x00000000 }, + { 0x000012f0 , 0x00000000 }, + { 0x0000143c , 0x00000000 }, + { 0x0000147c , 0x00000000 }, + { 0x00008000 , 0x00000000 }, + { 0x00008004 , 0x00000000 }, + { 0x00008008 , 0x00000000 }, + { 0x0000800c , 0x00000000 }, + { 0x00008018 , 0x00000000 }, + { 0x00008020 , 0x00000000 }, + { 0x00008038 , 0x00000000 }, + { 0x0000803c , 0x00000000 }, + { 0x00008040 , 0x00000000 }, + { 0x00008044 , 0x00000000 }, + { 0x00008048 , 0x00000000 }, + { 0x0000804c , 0xffffffff }, + { 0x00008054 , 0x00000000 }, + { 0x00008058 , 0x00000000 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008060 , 0x0000000f }, + { 0x00008064 , 0x00000000 }, + { 0x00008070 , 0x00000310 }, + { 0x00008074 , 0x00000020 }, + { 0x00008078 , 0x00000000 }, + { 0x0000809c , 0x0000000f }, + { 0x000080a0 , 0x00000000 }, + { 0x000080a4 , 0x02ff0000 }, + { 0x000080a8 , 0x0e070605 }, + { 0x000080ac , 0x0000000d }, + { 0x000080b0 , 0x00000000 }, + { 0x000080b4 , 0x00000000 }, + { 0x000080b8 , 0x00000000 }, + { 0x000080bc , 0x00000000 }, + { 0x000080c0 , 0x2a800000 }, + { 0x000080c4 , 0x06900168 }, + { 0x000080c8 , 0x13881c20 }, + { 0x000080cc , 0x01f40000 }, + { 0x000080d0 , 0x00252500 }, + { 0x000080d4 , 0x00a00000 }, + { 0x000080d8 , 0x00400000 }, + { 0x000080dc , 0x00000000 }, + { 0x000080e0 , 0xffffffff }, + { 0x000080e4 , 0x0000ffff }, + { 0x000080e8 , 0x3f3f3f3f }, + { 0x000080ec , 0x00000000 }, + { 0x000080f0 , 0x00000000 }, + { 0x000080f4 , 0x00000000 }, + { 0x000080fc , 0x00020000 }, + { 0x00008100 , 0x00000000 }, + { 0x00008108 , 0x00000052 }, + { 0x0000810c , 0x00000000 }, + { 0x00008110 , 0x00000000 }, + { 0x00008114 , 0x000007ff }, + { 0x00008118 , 0x000000aa }, + { 0x0000811c , 0x00003210 }, + { 0x00008124 , 0x00000000 }, + { 0x00008128 , 0x00000000 }, + { 0x0000812c , 0x00000000 }, + { 0x00008130 , 0x00000000 }, + { 0x00008134 , 0x00000000 }, + { 0x00008138 , 0x00000000 }, + { 0x0000813c , 0x0000ffff }, + { 0x00008144 , 0xffffffff }, + { 0x00008168 , 0x00000000 }, + { 0x0000816c , 0x00000000 }, + { 0x000081c0 , 0x00000000 }, + { 0x000081c4 , 0x33332210 }, + { 0x000081ec , 0x00000000 }, + { 0x000081f0 , 0x00000000 }, + { 0x000081f4 , 0x00000000 }, + { 0x000081f8 , 0x00000000 }, + { 0x000081fc , 0x00000000 }, + { 0x00008240 , 0x00100000 }, + { 0x00008244 , 0x0010f400 }, + { 0x00008248 , 0x00000800 }, + { 0x0000824c , 0x0001e800 }, + { 0x00008250 , 0x00000000 }, + { 0x00008254 , 0x00000000 }, + { 0x00008258 , 0x00000000 }, + { 0x0000825c , 0x40000000 }, + { 0x00008260 , 0x00080922 }, + { 0x00008264 , 0x9bc00010 }, + { 0x00008268 , 0xffffffff }, + { 0x0000826c , 0x0000ffff }, + { 0x00008270 , 0x00000000 }, + { 0x00008274 , 0x40000000 }, + { 0x00008278 , 0x003e4180 }, + { 0x0000827c , 0x00000004 }, + { 0x00008284 , 0x0000002c }, + { 0x00008288 , 0x0000002c }, + { 0x0000828c , 0x000000ff }, + { 0x00008294 , 0x00000000 }, + { 0x00008298 , 0x00000000 }, + { 0x0000829c , 0x00000000 }, + { 0x00008300 , 0x00000140 }, + { 0x00008314 , 0x00000000 }, + { 0x0000831c , 0x0000010d }, + { 0x00008328 , 0x00000000 }, + { 0x0000832c , 0x00000007 }, + { 0x00008330 , 0x00000302 }, + { 0x00008334 , 0x00000700 }, + { 0x00008338 , 0x00ff0000 }, + { 0x0000833c , 0x02400000 }, + { 0x00008340 , 0x000107ff }, + { 0x00008344 , 0xaa48105b }, + { 0x00008348 , 0x008f0000 }, + { 0x0000835c , 0x00000000 }, + { 0x00008360 , 0xffffffff }, + { 0x00008364 , 0xffffffff }, + { 0x00008368 , 0x00000000 }, + { 0x00008370 , 0x00000000 }, + { 0x00008374 , 0x000000ff }, + { 0x00008378 , 0x00000000 }, + { 0x0000837c , 0x00000000 }, + { 0x00008380 , 0xffffffff }, + { 0x00008384 , 0xffffffff }, + { 0x00008390 , 0xffffffff }, + { 0x00008394 , 0xffffffff }, + { 0x00008398 , 0x00000000 }, + { 0x0000839c , 0x00000000 }, + { 0x000083a0 , 0x00000000 }, + { 0x000083a4 , 0x0000fa14 }, + { 0x000083a8 , 0x000f0c00 }, + { 0x000083ac , 0x33332210 }, + { 0x000083b0 , 0x33332210 }, + { 0x000083b4 , 0x33332210 }, + { 0x000083b8 , 0x33332210 }, + { 0x000083bc , 0x00000000 }, + { 0x000083c0 , 0x00000000 }, + { 0x000083c4 , 0x00000000 }, + { 0x000083c8 , 0x00000000 }, + { 0x000083cc , 0x00000200 }, + { 0x000083d0 , 0x000301ff }, +}; + +static const u_int32_t ar9300_osprey_2p2_soc_preamble[][2] = { +/* Addr allmodes */ + { 0x000040a4 , 0x00a0c1c9 }, + { 0x00007008 , 0x00000000 }, + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000004c2 }, + { 0x00007048 , 0x00000008 }, +}; + +static const u_int32_t ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x52022470 , 0x52022470 , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x55022490 , 0x55022490 , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x59022492 , 0x59022492 , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x5d022692 , 0x5d022692 , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x61022892 , 0x61022892 , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x65024890 , 0x65024890 , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x69024892 , 0x69024892 , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x6e024c92 , 0x6e024c92 , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x12800400 , 0x12800400 }, + { 0x0000a598 , 0x21802220 , 0x21802220 , 0x16800402 , 0x16800402 }, + { 0x0000a59c , 0x27802223 , 0x27802223 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1c800603 , 0x1c800603 }, + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x21800a02 , 0x21800a02 }, + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x25800a04 , 0x25800a04 }, + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x28800a20 , 0x28800a20 }, + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2c800e20 , 0x2c800e20 }, + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x30800e22 , 0x30800e22 }, + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x34800e24 , 0x34800e24 }, + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x38801640 , 0x38801640 }, + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x3c801660 , 0x3c801660 }, + { 0x0000a5c4 , 0x52822470 , 0x52822470 , 0x3f801861 , 0x3f801861 }, + { 0x0000a5c8 , 0x55822490 , 0x55822490 , 0x43801a81 , 0x43801a81 }, + { 0x0000a5cc , 0x59822492 , 0x59822492 , 0x47801a83 , 0x47801a83 }, + { 0x0000a5d0 , 0x5d822692 , 0x5d822692 , 0x4a801c84 , 0x4a801c84 }, + { 0x0000a5d4 , 0x61822892 , 0x61822892 , 0x4e801ce3 , 0x4e801ce3 }, + { 0x0000a5d8 , 0x65824890 , 0x65824890 , 0x52801ce5 , 0x52801ce5 }, + { 0x0000a5dc , 0x69824892 , 0x69824892 , 0x56801ce9 , 0x56801ce9 }, + { 0x0000a5e0 , 0x6e824c92 , 0x6e824c92 , 0x5a801ceb , 0x5a801ceb }, + { 0x0000a5e4 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5e8 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5ec , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f0 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f4 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f8 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5fc , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x02004000 , 0x02004000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x02004801 , 0x02004801 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02808a02 , 0x02808a02 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0380ce03 , 0x0380ce03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04411104 , 0x04411104 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04411104 , 0x04411104 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x62480001 , 0x62480001 , 0x62480001 , 0x62480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x62480001 , 0x62480001 , 0x62480001 , 0x62480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x62480001 , 0x62480001 , 0x62480001 , 0x62480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x52022470 , 0x52022470 , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x55022490 , 0x55022490 , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x59022492 , 0x59022492 , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x5d022692 , 0x5d022692 , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x61022892 , 0x61022892 , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x65024890 , 0x65024890 , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x69024892 , 0x69024892 , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x6e024c92 , 0x6e024c92 , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x11800400 , 0x11800400 }, + { 0x0000a598 , 0x21802220 , 0x21802220 , 0x15800402 , 0x15800402 }, + { 0x0000a59c , 0x27802223 , 0x27802223 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1b800603 , 0x1b800603 }, + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x1f800a02 , 0x1f800a02 }, + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x23800a04 , 0x23800a04 }, + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x26800a20 , 0x26800a20 }, + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2a800e20 , 0x2a800e20 }, + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x2e800e22 , 0x2e800e22 }, + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x31800e24 , 0x31800e24 }, + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x34801640 , 0x34801640 }, + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x38801660 , 0x38801660 }, + { 0x0000a5c4 , 0x52822470 , 0x52822470 , 0x3b801861 , 0x3b801861 }, + { 0x0000a5c8 , 0x55822490 , 0x55822490 , 0x3e801a81 , 0x3e801a81 }, + { 0x0000a5cc , 0x59822492 , 0x59822492 , 0x42801a83 , 0x42801a83 }, + { 0x0000a5d0 , 0x5d822692 , 0x5d822692 , 0x44801c84 , 0x44801c84 }, + { 0x0000a5d4 , 0x61822892 , 0x61822892 , 0x48801ce3 , 0x48801ce3 }, + { 0x0000a5d8 , 0x65824890 , 0x65824890 , 0x4c801ce5 , 0x4c801ce5 }, + { 0x0000a5dc , 0x69824892 , 0x69824892 , 0x50801ce9 , 0x50801ce9 }, + { 0x0000a5e0 , 0x6e824c92 , 0x6e824c92 , 0x54801ceb , 0x54801ceb }, + { 0x0000a5e4 , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5e8 , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5ec , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5f0 , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5f4 , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5f8 , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5fc , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x02004000 , 0x02004000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x02004801 , 0x02004801 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02808a02 , 0x02808a02 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0380ce03 , 0x0380ce03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04411104 , 0x04411104 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04411104 , 0x04411104 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016048 , 0x66480001 , 0x66480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016448 , 0x66480001 , 0x66480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016848 , 0x66480001 , 0x66480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484[][2] = { +/* Addr allmodes */ + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x6f7f0301 }, + { 0x0000a3a0 , 0xca9228ee }, +}; + +static const u_int32_t ar9300_osprey_2p2_mac_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, +}; + +static const u_int32_t ar9300Modes_high_power_tx_gain_table_osprey_2p2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x15000028 , 0x15000028 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1b00002b , 0x1b00002b , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x1f020028 , 0x1f020028 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x2502002b , 0x2502002b , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2a04002a , 0x2a04002a , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2e06002a , 0x2e06002a , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x3302202d , 0x3302202d , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3804202c , 0x3804202c , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3c06202c , 0x3c06202c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4108202d , 0x4108202d , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4506402d , 0x4506402d , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4906222d , 0x4906222d , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4d062231 , 0x4d062231 , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x50082231 , 0x50082231 , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5608422e , 0x5608422e , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5e08442e , 0x5e08442e , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x620a4431 , 0x620a4431 , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x640a4432 , 0x640a4432 , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x680a4434 , 0x680a4434 , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x6c0a6434 , 0x6c0a6434 , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x6f0a6633 , 0x6f0a6633 , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x15800028 , 0x15800028 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1b80002b , 0x1b80002b , 0x12800400 , 0x12800400 }, + { 0x0000a598 , 0x1f820028 , 0x1f820028 , 0x16800402 , 0x16800402 }, + { 0x0000a59c , 0x2582002b , 0x2582002b , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2a84002a , 0x2a84002a , 0x1c800603 , 0x1c800603 }, + { 0x0000a5a4 , 0x2e86002a , 0x2e86002a , 0x21800a02 , 0x21800a02 }, + { 0x0000a5a8 , 0x3382202d , 0x3382202d , 0x25800a04 , 0x25800a04 }, + { 0x0000a5ac , 0x3884202c , 0x3884202c , 0x28800a20 , 0x28800a20 }, + { 0x0000a5b0 , 0x3c86202c , 0x3c86202c , 0x2c800e20 , 0x2c800e20 }, + { 0x0000a5b4 , 0x4188202d , 0x4188202d , 0x30800e22 , 0x30800e22 }, + { 0x0000a5b8 , 0x4586402d , 0x4586402d , 0x34800e24 , 0x34800e24 }, + { 0x0000a5bc , 0x4986222d , 0x4986222d , 0x38801640 , 0x38801640 }, + { 0x0000a5c0 , 0x4d862231 , 0x4d862231 , 0x3c801660 , 0x3c801660 }, + { 0x0000a5c4 , 0x50882231 , 0x50882231 , 0x3f801861 , 0x3f801861 }, + { 0x0000a5c8 , 0x5688422e , 0x5688422e , 0x43801a81 , 0x43801a81 }, + { 0x0000a5cc , 0x5e88442e , 0x5e88442e , 0x47801a83 , 0x47801a83 }, + { 0x0000a5d0 , 0x628a4431 , 0x628a4431 , 0x4a801c84 , 0x4a801c84 }, + { 0x0000a5d4 , 0x648a4432 , 0x648a4432 , 0x4e801ce3 , 0x4e801ce3 }, + { 0x0000a5d8 , 0x688a4434 , 0x688a4434 , 0x52801ce5 , 0x52801ce5 }, + { 0x0000a5dc , 0x6c8a6434 , 0x6c8a6434 , 0x56801ce9 , 0x56801ce9 }, + { 0x0000a5e0 , 0x6f8a6633 , 0x6f8a6633 , 0x5a801ceb , 0x5a801ceb }, + { 0x0000a5e4 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5e8 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5ec , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f0 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f4 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f8 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5fc , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01804601 , 0x01804601 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01804601 , 0x01804601 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x01804601 , 0x01804601 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x03408d02 , 0x03408d02 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x03410d04 , 0x03410d04 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x61200001 , 0x61200001 , 0x66480001 , 0x66480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x61200001 , 0x61200001 , 0x66480001 , 0x66480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x61200001 , 0x61200001 , 0x66480001 , 0x66480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9200_merlin_2p2_radio_core[][2] = { +/* Addr common */ + { 0x00007800 , 0x00040000 }, + { 0x00007804 , 0xdb005012 }, + { 0x00007808 , 0x04924914 }, + { 0x0000780c , 0x21084210 }, + { 0x00007810 , 0x6d801300 }, + { 0x00007814 , 0x0019beff }, + { 0x00007818 , 0x07e41000 }, + { 0x0000781c , 0x00392000 }, + { 0x00007820 , 0x92592480 }, + { 0x00007824 , 0x00040000 }, + { 0x00007828 , 0xdb005012 }, + { 0x0000782c , 0x04924914 }, + { 0x00007830 , 0x21084210 }, + { 0x00007834 , 0x6d801300 }, + { 0x00007838 , 0x0019beff }, + { 0x0000783c , 0x07e40000 }, + { 0x00007840 , 0x00392000 }, + { 0x00007844 , 0x92592480 }, + { 0x00007848 , 0x00100000 }, + { 0x0000784c , 0x773f0567 }, + { 0x00007850 , 0x54214514 }, + { 0x00007854 , 0x12035828 }, + { 0x00007858 , 0x92592692 }, + { 0x0000785c , 0x00000000 }, + { 0x00007860 , 0x56400000 }, + { 0x00007864 , 0x0a8e370e }, + { 0x00007868 , 0xc0102850 }, + { 0x0000786c , 0x812d4000 }, + { 0x00007870 , 0x807ec400 }, + { 0x00007874 , 0x001b6db0 }, + { 0x00007878 , 0x00376b63 }, + { 0x0000787c , 0x06db6db6 }, + { 0x00007880 , 0x006d8000 }, + { 0x00007884 , 0xffeffffe }, + { 0x00007888 , 0xffeffffe }, + { 0x0000788c , 0x00010000 }, + { 0x00007890 , 0x02060aeb }, + { 0x00007894 , 0x5a108000 }, +}; + +static const u_int32_t ar9300_osprey_2p2_baseband_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8011 , 0xd00a8011 }, + { 0x00009820 , 0x206a022e , 0x206a022e , 0x206a012e , 0x206a012e }, + { 0x00009824 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 }, + { 0x00009828 , 0x06903081 , 0x06903081 , 0x06903881 , 0x06903881 }, + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000119c , 0x0000119c }, + { 0x00009c00 , 0x000000c4 , 0x000000c4 , 0x000000c4 , 0x000000c4 }, + { 0x00009e00 , 0x0372111a , 0x0372111a , 0x037216a0 , 0x037216a0 }, + { 0x00009e04 , 0x001c2020 , 0x001c2020 , 0x001c2020 , 0x001c2020 }, + { 0x00009e0c , 0x6c4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + { 0x00009e10 , 0x7ec88d2e , 0x7ec88d2e , 0x7ec84d2e , 0x7ec84d2e }, + { 0x00009e14 , 0x37b95d5e , 0x37b9605e , 0x3379605e , 0x33795d5e }, + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + { 0x00009e2c , 0x0000001c , 0x0000001c , 0x00000021 , 0x00000021 }, + { 0x00009e3c , 0xcf946220 , 0xcf946220 , 0xcf946222 , 0xcf946222 }, + { 0x00009e44 , 0x02321e27 , 0x02321e27 , 0x02291e27 , 0x02291e27 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302012 , 0x50302012 }, + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, + { 0x0000a204 , 0x000036c0 , 0x000036c4 , 0x000036c4 , 0x000036c0 }, + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + { 0x0000a22c , 0x01026a2f , 0x01026a2f , 0x01026a2f , 0x01026a2f }, + { 0x0000a230 , 0x0000000a , 0x00000014 , 0x00000016 , 0x0000000b }, + { 0x0000a234 , 0x00000fff , 0x10000fff , 0x10000fff , 0x00000fff }, + { 0x0000a238 , 0xffb81018 , 0xffb81018 , 0xffb81018 , 0xffb81018 }, + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a260 , 0x0a021501 , 0x0a021501 , 0x3a021501 , 0x3a021501 }, + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, + { 0x0000a288 , 0x00000110 , 0x00000110 , 0x00000110 , 0x00000110 }, + { 0x0000a28c , 0x00022222 , 0x00022222 , 0x00022222 , 0x00022222 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2d0 , 0x00041983 , 0x00041983 , 0x00041981 , 0x00041982 }, + { 0x0000a2d8 , 0x7999a83b , 0x7999a83b , 0x7999a83b , 0x7999a83b }, + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a830 , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae04 , 0x001c0000 , 0x001c0000 , 0x001c0000 , 0x001c0000 }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000ae1c , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae20 , 0x000001b5 , 0x000001b5 , 0x000001ce , 0x000001ce }, + { 0x0000b284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, + { 0x0000b830 , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000be04 , 0x001c0000 , 0x001c0000 , 0x001c0000 , 0x001c0000 }, + { 0x0000be18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000be1c , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000be20 , 0x000001b5 , 0x000001b5 , 0x000001ce , 0x000001ce }, + { 0x0000c284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, +}; + +static const u_int32_t ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x03820190 }, + { 0x0000a030 , 0x03840383 }, + { 0x0000a034 , 0x03880385 }, + { 0x0000a038 , 0x038a0389 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x29292929 }, + { 0x0000a084 , 0x29292929 }, + { 0x0000a088 , 0x29292929 }, + { 0x0000a08c , 0x29292929 }, + { 0x0000a090 , 0x22292929 }, + { 0x0000a094 , 0x1d1d2222 }, + { 0x0000a098 , 0x0c111117 }, + { 0x0000a09c , 0x00030303 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x32323232 }, + { 0x0000b084 , 0x2f2f3232 }, + { 0x0000b088 , 0x23282a2d }, + { 0x0000b08c , 0x1c1e2123 }, + { 0x0000b090 , 0x14171919 }, + { 0x0000b094 , 0x0e0e1214 }, + { 0x0000b098 , 0x03050707 }, + { 0x0000b09c , 0x00030303 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar9300_osprey_2p2_soc_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00007010 , 0x00000023 , 0x00000023 , 0x00000023 , 0x00000023 }, +}; + +static const u_int32_t ar9300Common_rx_gain_table_merlin_2p2[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x02000101 }, + { 0x0000a004 , 0x02000102 }, + { 0x0000a008 , 0x02000103 }, + { 0x0000a00c , 0x02000104 }, + { 0x0000a010 , 0x02000200 }, + { 0x0000a014 , 0x02000201 }, + { 0x0000a018 , 0x02000202 }, + { 0x0000a01c , 0x02000203 }, + { 0x0000a020 , 0x02000204 }, + { 0x0000a024 , 0x02000205 }, + { 0x0000a028 , 0x02000208 }, + { 0x0000a02c , 0x02000302 }, + { 0x0000a030 , 0x02000303 }, + { 0x0000a034 , 0x02000304 }, + { 0x0000a038 , 0x02000400 }, + { 0x0000a03c , 0x02010300 }, + { 0x0000a040 , 0x02010301 }, + { 0x0000a044 , 0x02010302 }, + { 0x0000a048 , 0x02000500 }, + { 0x0000a04c , 0x02010400 }, + { 0x0000a050 , 0x02020300 }, + { 0x0000a054 , 0x02020301 }, + { 0x0000a058 , 0x02020302 }, + { 0x0000a05c , 0x02020303 }, + { 0x0000a060 , 0x02020400 }, + { 0x0000a064 , 0x02030300 }, + { 0x0000a068 , 0x02030301 }, + { 0x0000a06c , 0x02030302 }, + { 0x0000a070 , 0x02030303 }, + { 0x0000a074 , 0x02030400 }, + { 0x0000a078 , 0x02040300 }, + { 0x0000a07c , 0x02040301 }, + { 0x0000a080 , 0x02040302 }, + { 0x0000a084 , 0x02040303 }, + { 0x0000a088 , 0x02030500 }, + { 0x0000a08c , 0x02040400 }, + { 0x0000a090 , 0x02050203 }, + { 0x0000a094 , 0x02050204 }, + { 0x0000a098 , 0x02050205 }, + { 0x0000a09c , 0x02040500 }, + { 0x0000a0a0 , 0x02050301 }, + { 0x0000a0a4 , 0x02050302 }, + { 0x0000a0a8 , 0x02050303 }, + { 0x0000a0ac , 0x02050400 }, + { 0x0000a0b0 , 0x02050401 }, + { 0x0000a0b4 , 0x02050402 }, + { 0x0000a0b8 , 0x02050403 }, + { 0x0000a0bc , 0x02050500 }, + { 0x0000a0c0 , 0x02050501 }, + { 0x0000a0c4 , 0x02050502 }, + { 0x0000a0c8 , 0x02050503 }, + { 0x0000a0cc , 0x02050504 }, + { 0x0000a0d0 , 0x02050600 }, + { 0x0000a0d4 , 0x02050601 }, + { 0x0000a0d8 , 0x02050602 }, + { 0x0000a0dc , 0x02050603 }, + { 0x0000a0e0 , 0x02050604 }, + { 0x0000a0e4 , 0x02050700 }, + { 0x0000a0e8 , 0x02050701 }, + { 0x0000a0ec , 0x02050702 }, + { 0x0000a0f0 , 0x02050703 }, + { 0x0000a0f4 , 0x02050704 }, + { 0x0000a0f8 , 0x02050705 }, + { 0x0000a0fc , 0x02050708 }, + { 0x0000a100 , 0x02050709 }, + { 0x0000a104 , 0x0205070a }, + { 0x0000a108 , 0x0205070b }, + { 0x0000a10c , 0x0205070c }, + { 0x0000a110 , 0x0205070d }, + { 0x0000a114 , 0x02050710 }, + { 0x0000a118 , 0x02050711 }, + { 0x0000a11c , 0x02050712 }, + { 0x0000a120 , 0x02050713 }, + { 0x0000a124 , 0x02050714 }, + { 0x0000a128 , 0x02050715 }, + { 0x0000a12c , 0x02050730 }, + { 0x0000a130 , 0x02050731 }, + { 0x0000a134 , 0x02050732 }, + { 0x0000a138 , 0x02050733 }, + { 0x0000a13c , 0x02050734 }, + { 0x0000a140 , 0x02050735 }, + { 0x0000a144 , 0x02050750 }, + { 0x0000a148 , 0x02050751 }, + { 0x0000a14c , 0x02050752 }, + { 0x0000a150 , 0x02050753 }, + { 0x0000a154 , 0x02050754 }, + { 0x0000a158 , 0x02050755 }, + { 0x0000a15c , 0x02050770 }, + { 0x0000a160 , 0x02050771 }, + { 0x0000a164 , 0x02050772 }, + { 0x0000a168 , 0x02050773 }, + { 0x0000a16c , 0x02050774 }, + { 0x0000a170 , 0x02050775 }, + { 0x0000a174 , 0x00000776 }, + { 0x0000a178 , 0x00000776 }, + { 0x0000a17c , 0x00000776 }, + { 0x0000a180 , 0x00000776 }, + { 0x0000a184 , 0x00000776 }, + { 0x0000a188 , 0x00000776 }, + { 0x0000a18c , 0x00000776 }, + { 0x0000a190 , 0x00000776 }, + { 0x0000a194 , 0x00000776 }, + { 0x0000a198 , 0x00000776 }, + { 0x0000a19c , 0x00000776 }, + { 0x0000a1a0 , 0x00000776 }, + { 0x0000a1a4 , 0x00000776 }, + { 0x0000a1a8 , 0x00000776 }, + { 0x0000a1ac , 0x00000776 }, + { 0x0000a1b0 , 0x00000776 }, + { 0x0000a1b4 , 0x00000776 }, + { 0x0000a1b8 , 0x00000776 }, + { 0x0000a1bc , 0x00000776 }, + { 0x0000a1c0 , 0x00000776 }, + { 0x0000a1c4 , 0x00000776 }, + { 0x0000a1c8 , 0x00000776 }, + { 0x0000a1cc , 0x00000776 }, + { 0x0000a1d0 , 0x00000776 }, + { 0x0000a1d4 , 0x00000776 }, + { 0x0000a1d8 , 0x00000776 }, + { 0x0000a1dc , 0x00000776 }, + { 0x0000a1e0 , 0x00000776 }, + { 0x0000a1e4 , 0x00000776 }, + { 0x0000a1e8 , 0x00000776 }, + { 0x0000a1ec , 0x00000776 }, + { 0x0000a1f0 , 0x00000776 }, + { 0x0000a1f4 , 0x00000776 }, + { 0x0000a1f8 , 0x00000776 }, + { 0x0000a1fc , 0x00000776 }, + { 0x0000b000 , 0x02000101 }, + { 0x0000b004 , 0x02000102 }, + { 0x0000b008 , 0x02000103 }, + { 0x0000b00c , 0x02000104 }, + { 0x0000b010 , 0x02000200 }, + { 0x0000b014 , 0x02000201 }, + { 0x0000b018 , 0x02000202 }, + { 0x0000b01c , 0x02000203 }, + { 0x0000b020 , 0x02000204 }, + { 0x0000b024 , 0x02000205 }, + { 0x0000b028 , 0x02000208 }, + { 0x0000b02c , 0x02000302 }, + { 0x0000b030 , 0x02000303 }, + { 0x0000b034 , 0x02000304 }, + { 0x0000b038 , 0x02000400 }, + { 0x0000b03c , 0x02010300 }, + { 0x0000b040 , 0x02010301 }, + { 0x0000b044 , 0x02010302 }, + { 0x0000b048 , 0x02000500 }, + { 0x0000b04c , 0x02010400 }, + { 0x0000b050 , 0x02020300 }, + { 0x0000b054 , 0x02020301 }, + { 0x0000b058 , 0x02020302 }, + { 0x0000b05c , 0x02020303 }, + { 0x0000b060 , 0x02020400 }, + { 0x0000b064 , 0x02030300 }, + { 0x0000b068 , 0x02030301 }, + { 0x0000b06c , 0x02030302 }, + { 0x0000b070 , 0x02030303 }, + { 0x0000b074 , 0x02030400 }, + { 0x0000b078 , 0x02040300 }, + { 0x0000b07c , 0x02040301 }, + { 0x0000b080 , 0x02040302 }, + { 0x0000b084 , 0x02040303 }, + { 0x0000b088 , 0x02030500 }, + { 0x0000b08c , 0x02040400 }, + { 0x0000b090 , 0x02050203 }, + { 0x0000b094 , 0x02050204 }, + { 0x0000b098 , 0x02050205 }, + { 0x0000b09c , 0x02040500 }, + { 0x0000b0a0 , 0x02050301 }, + { 0x0000b0a4 , 0x02050302 }, + { 0x0000b0a8 , 0x02050303 }, + { 0x0000b0ac , 0x02050400 }, + { 0x0000b0b0 , 0x02050401 }, + { 0x0000b0b4 , 0x02050402 }, + { 0x0000b0b8 , 0x02050403 }, + { 0x0000b0bc , 0x02050500 }, + { 0x0000b0c0 , 0x02050501 }, + { 0x0000b0c4 , 0x02050502 }, + { 0x0000b0c8 , 0x02050503 }, + { 0x0000b0cc , 0x02050504 }, + { 0x0000b0d0 , 0x02050600 }, + { 0x0000b0d4 , 0x02050601 }, + { 0x0000b0d8 , 0x02050602 }, + { 0x0000b0dc , 0x02050603 }, + { 0x0000b0e0 , 0x02050604 }, + { 0x0000b0e4 , 0x02050700 }, + { 0x0000b0e8 , 0x02050701 }, + { 0x0000b0ec , 0x02050702 }, + { 0x0000b0f0 , 0x02050703 }, + { 0x0000b0f4 , 0x02050704 }, + { 0x0000b0f8 , 0x02050705 }, + { 0x0000b0fc , 0x02050708 }, + { 0x0000b100 , 0x02050709 }, + { 0x0000b104 , 0x0205070a }, + { 0x0000b108 , 0x0205070b }, + { 0x0000b10c , 0x0205070c }, + { 0x0000b110 , 0x0205070d }, + { 0x0000b114 , 0x02050710 }, + { 0x0000b118 , 0x02050711 }, + { 0x0000b11c , 0x02050712 }, + { 0x0000b120 , 0x02050713 }, + { 0x0000b124 , 0x02050714 }, + { 0x0000b128 , 0x02050715 }, + { 0x0000b12c , 0x02050730 }, + { 0x0000b130 , 0x02050731 }, + { 0x0000b134 , 0x02050732 }, + { 0x0000b138 , 0x02050733 }, + { 0x0000b13c , 0x02050734 }, + { 0x0000b140 , 0x02050735 }, + { 0x0000b144 , 0x02050750 }, + { 0x0000b148 , 0x02050751 }, + { 0x0000b14c , 0x02050752 }, + { 0x0000b150 , 0x02050753 }, + { 0x0000b154 , 0x02050754 }, + { 0x0000b158 , 0x02050755 }, + { 0x0000b15c , 0x02050770 }, + { 0x0000b160 , 0x02050771 }, + { 0x0000b164 , 0x02050772 }, + { 0x0000b168 , 0x02050773 }, + { 0x0000b16c , 0x02050774 }, + { 0x0000b170 , 0x02050775 }, + { 0x0000b174 , 0x00000776 }, + { 0x0000b178 , 0x00000776 }, + { 0x0000b17c , 0x00000776 }, + { 0x0000b180 , 0x00000776 }, + { 0x0000b184 , 0x00000776 }, + { 0x0000b188 , 0x00000776 }, + { 0x0000b18c , 0x00000776 }, + { 0x0000b190 , 0x00000776 }, + { 0x0000b194 , 0x00000776 }, + { 0x0000b198 , 0x00000776 }, + { 0x0000b19c , 0x00000776 }, + { 0x0000b1a0 , 0x00000776 }, + { 0x0000b1a4 , 0x00000776 }, + { 0x0000b1a8 , 0x00000776 }, + { 0x0000b1ac , 0x00000776 }, + { 0x0000b1b0 , 0x00000776 }, + { 0x0000b1b4 , 0x00000776 }, + { 0x0000b1b8 , 0x00000776 }, + { 0x0000b1bc , 0x00000776 }, + { 0x0000b1c0 , 0x00000776 }, + { 0x0000b1c4 , 0x00000776 }, + { 0x0000b1c8 , 0x00000776 }, + { 0x0000b1cc , 0x00000776 }, + { 0x0000b1d0 , 0x00000776 }, + { 0x0000b1d4 , 0x00000776 }, + { 0x0000b1d8 , 0x00000776 }, + { 0x0000b1dc , 0x00000776 }, + { 0x0000b1e0 , 0x00000776 }, + { 0x0000b1e4 , 0x00000776 }, + { 0x0000b1e8 , 0x00000776 }, + { 0x0000b1ec , 0x00000776 }, + { 0x0000b1f0 , 0x00000776 }, + { 0x0000b1f4 , 0x00000776 }, + { 0x0000b1f8 , 0x00000776 }, + { 0x0000b1fc , 0x00000776 }, +}; + +static const u_int32_t ar9300_common_rx_gain_table_osprey_2p2[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x01910190 }, + { 0x0000a030 , 0x01930192 }, + { 0x0000a034 , 0x01950194 }, + { 0x0000a038 , 0x038a0196 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x22222229 }, + { 0x0000a084 , 0x1d1d1d1d }, + { 0x0000a088 , 0x1d1d1d1d }, + { 0x0000a08c , 0x1d1d1d1d }, + { 0x0000a090 , 0x171d1d1d }, + { 0x0000a094 , 0x11111717 }, + { 0x0000a098 , 0x00030311 }, + { 0x0000a09c , 0x00000000 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x23232323 }, + { 0x0000b084 , 0x21232323 }, + { 0x0000b088 , 0x19191c1e }, + { 0x0000b08c , 0x12141417 }, + { 0x0000b090 , 0x07070e0e }, + { 0x0000b094 , 0x03030305 }, + { 0x0000b098 , 0x00000003 }, + { 0x0000b09c , 0x00000000 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +/* PCIE-PHY programming array */ +static const u_int32_t ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2[][2] = { +{0x00004040, 0x0821265e}, +{0x00004040, 0x0008003b}, +{0x00004044, 0x00000000}, +}; + +/* PCIE-PHY programming array */ +static const u_int32_t ar9300PciePhy_clkreq_enable_L1_osprey_2p2[][2] = { +{0x00004040, 0x0825365e}, +{0x00004040, 0x0008003b}, +{0x00004044, 0x00000000}, +}; + +/* PCIE-PHY programming array */ +static const u_int32_t ar9300PciePhy_clkreq_disable_L1_osprey_2p2[][2] = { +{0x00004040, 0x0821365e}, +{0x00004040, 0x0008003b}, +{0x00004044, 0x00000000}, +}; + diff --git a/hal/ar9300/ar9300_osprey22_scoemu.ini b/hal/ar9300/ar9300_osprey22_scoemu.ini new file mode 100644 index 000000000000..134740e7f5a9 --- /dev/null +++ b/hal/ar9300/ar9300_osprey22_scoemu.ini @@ -0,0 +1,2147 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +>>>> ORIGINAL //depot/sw/branches/AquilaStaging/drivers/wlan/hal/ar9300/ar9300_osprey22.ini#11 + +==== THEIRS //depot/sw/branches/scorpion_dev/drivers/wlan/hal/ar9300/ar9300_osprey22.ini#3 + +==== YOURS //sco9.5/drivers/wlan/hal/ar9300/ar9300_osprey22.ini + +<<<< + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>>>> ORIGINAL //depot/sw/branches/AquilaStaging/drivers/wlan/hal/ar9300/ar9300_osprey22.ini#11 + +==== THEIRS //depot/sw/branches/scorpion_dev/drivers/wlan/hal/ar9300/ar9300_osprey22.ini#3 + +==== YOURS //sco9.5/drivers/wlan/hal/ar9300/ar9300_osprey22.ini + +<<<< + + + + + + + + + + +static const u_int32_t ar9300_osprey_2p2_mac_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 }, +#ifdef AR9340_EMULATION + { 0x0000801c , 0x0e8d8013 , 0x0e8d8013 , 0x0e8d8013 , 0x0e8d8013 }, +#else + { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 }, +#endif +}; + +static const u_int32_t ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x52022470 , 0x52022470 , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x55022490 , 0x55022490 , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x59022492 , 0x59022492 , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x5d022692 , 0x5d022692 , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x61022892 , 0x61022892 , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x65024890 , 0x65024890 , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x69024892 , 0x69024892 , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x6e024c92 , 0x6e024c92 , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x12800400 , 0x12800400 }, + { 0x0000a598 , 0x21802220 , 0x21802220 , 0x16800402 , 0x16800402 }, + { 0x0000a59c , 0x27802223 , 0x27802223 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1c800603 , 0x1c800603 }, + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x21800a02 , 0x21800a02 }, + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x25800a04 , 0x25800a04 }, + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x28800a20 , 0x28800a20 }, + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2c800e20 , 0x2c800e20 }, + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x30800e22 , 0x30800e22 }, + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x34800e24 , 0x34800e24 }, + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x38801640 , 0x38801640 }, + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x3c801660 , 0x3c801660 }, + { 0x0000a5c4 , 0x52822470 , 0x52822470 , 0x3f801861 , 0x3f801861 }, + { 0x0000a5c8 , 0x55822490 , 0x55822490 , 0x43801a81 , 0x43801a81 }, + { 0x0000a5cc , 0x59822492 , 0x59822492 , 0x47801a83 , 0x47801a83 }, + { 0x0000a5d0 , 0x5d822692 , 0x5d822692 , 0x4a801c84 , 0x4a801c84 }, + { 0x0000a5d4 , 0x61822892 , 0x61822892 , 0x4e801ce3 , 0x4e801ce3 }, + { 0x0000a5d8 , 0x65824890 , 0x65824890 , 0x52801ce5 , 0x52801ce5 }, + { 0x0000a5dc , 0x69824892 , 0x69824892 , 0x56801ce9 , 0x56801ce9 }, + { 0x0000a5e0 , 0x6e824c92 , 0x6e824c92 , 0x5a801ceb , 0x5a801ceb }, + { 0x0000a5e4 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5e8 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5ec , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f0 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f4 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f8 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5fc , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x02004000 , 0x02004000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x02004801 , 0x02004801 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02808a02 , 0x02808a02 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0380ce03 , 0x0380ce03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04411104 , 0x04411104 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04411104 , 0x04411104 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, +#ifndef AR9340_EMULATION + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x66480001 , 0x66480001 , 0x66480001 , 0x66480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x66480001 , 0x66480001 , 0x66480001 , 0x66480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x66480001 , 0x66480001 , 0x66480001 , 0x66480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +#endif +}; + +static const u_int32_t ar9300_osprey_2p2_baseband_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafa68e30 }, + { 0x00009884 , 0x00002842 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009e50 , 0x00000000 }, + { 0x00009fcc , 0x00000014 }, + { 0x0000a344 , 0x00000010 }, + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x71733d01 }, + { 0x0000a3a0 , 0xd0ad5c12 }, + { 0x0000a3c0 , 0x22222220 }, + { 0x0000a3c4 , 0x22222222 }, + { 0x0000a404 , 0x00418a11 }, + { 0x0000a418 , 0x050001ce }, + { 0x0000a438 , 0x00001800 }, + { 0x0000a458 , 0x01444452 }, + { 0x0000a690 , 0x00000038 }, + { 0x0000b8dc , 0x00400000 }, +}; + +static const u_int32_t ar9300_osprey_2p2_radio_core[][2] = { +/* Addr allmodes */ +#ifndef AR9340_EMULATION + { 0x00016000 , 0x36db6db6 }, + { 0x00016004 , 0x6db6db40 }, + { 0x00016008 , 0x73f00000 }, + { 0x0001600c , 0x00000000 }, + { 0x00016040 , 0x7f80fff8 }, + { 0x0001604c , 0x76d005b5 }, + { 0x00016050 , 0x556cf031 }, + { 0x00016054 , 0x13449440 }, + { 0x00016058 , 0x0c51c92c }, + { 0x0001605c , 0x3db7fffc }, + { 0x00016060 , 0xfffffffc }, + { 0x00016064 , 0x000f0278 }, + { 0x0001606c , 0x6db60000 }, + { 0x00016080 , 0x00000000 }, + { 0x00016084 , 0x0e48048c }, + { 0x00016088 , 0x54214514 }, + { 0x0001608c , 0x119f481e }, + { 0x00016090 , 0x24926490 }, + { 0x00016098 , 0xd2888888 }, + { 0x000160a0 , 0x0a108ffe }, + { 0x000160a4 , 0x812fc370 }, + { 0x000160a8 , 0x423c8000 }, + { 0x000160b4 , 0x92480080 }, + { 0x000160c0 , 0x00adb6d0 }, + { 0x000160c4 , 0x6db6db60 }, + { 0x000160c8 , 0x6db6db6c }, + { 0x000160cc , 0x01e6c000 }, + { 0x00016100 , 0x3fffbe01 }, + { 0x00016104 , 0xfff80000 }, + { 0x00016108 , 0x00080010 }, + { 0x00016144 , 0x02084080 }, + { 0x00016148 , 0x00000000 }, + { 0x00016280 , 0x058a0001 }, + { 0x00016284 , 0x3d840208 }, + { 0x00016288 , 0x05a20408 }, + { 0x0001628c , 0x00038c07 }, + { 0x00016290 , 0x00000004 }, + { 0x00016294 , 0x458a214f }, + { 0x00016380 , 0x00000000 }, + { 0x00016384 , 0x00000000 }, + { 0x00016388 , 0x00800700 }, + { 0x0001638c , 0x00800700 }, + { 0x00016390 , 0x00800700 }, + { 0x00016394 , 0x00000000 }, + { 0x00016398 , 0x00000000 }, + { 0x0001639c , 0x00000000 }, + { 0x000163a0 , 0x00000001 }, + { 0x000163a4 , 0x00000001 }, + { 0x000163a8 , 0x00000000 }, + { 0x000163ac , 0x00000000 }, + { 0x000163b0 , 0x00000000 }, + { 0x000163b4 , 0x00000000 }, + { 0x000163b8 , 0x00000000 }, + { 0x000163bc , 0x00000000 }, + { 0x000163c0 , 0x000000a0 }, + { 0x000163c4 , 0x000c0000 }, + { 0x000163c8 , 0x14021402 }, + { 0x000163cc , 0x00001402 }, + { 0x000163d0 , 0x00000000 }, + { 0x000163d4 , 0x00000000 }, + { 0x00016400 , 0x36db6db6 }, + { 0x00016404 , 0x6db6db40 }, + { 0x00016408 , 0x73f00000 }, + { 0x0001640c , 0x00000000 }, + { 0x00016440 , 0x7f80fff8 }, + { 0x0001644c , 0x76d005b5 }, + { 0x00016450 , 0x556cf031 }, + { 0x00016454 , 0x13449440 }, + { 0x00016458 , 0x0c51c92c }, + { 0x0001645c , 0x3db7fffc }, + { 0x00016460 , 0xfffffffc }, + { 0x00016464 , 0x000f0278 }, + { 0x0001646c , 0x6db60000 }, + { 0x00016500 , 0x3fffbe01 }, + { 0x00016504 , 0xfff80000 }, + { 0x00016508 , 0x00080010 }, + { 0x00016544 , 0x02084080 }, + { 0x00016548 , 0x00000000 }, + { 0x00016780 , 0x00000000 }, + { 0x00016784 , 0x00000000 }, + { 0x00016788 , 0x00800700 }, + { 0x0001678c , 0x00800700 }, + { 0x00016790 , 0x00800700 }, + { 0x00016794 , 0x00000000 }, + { 0x00016798 , 0x00000000 }, + { 0x0001679c , 0x00000000 }, + { 0x000167a0 , 0x00000001 }, + { 0x000167a4 , 0x00000001 }, + { 0x000167a8 , 0x00000000 }, + { 0x000167ac , 0x00000000 }, + { 0x000167b0 , 0x00000000 }, + { 0x000167b4 , 0x00000000 }, + { 0x000167b8 , 0x00000000 }, + { 0x000167bc , 0x00000000 }, + { 0x000167c0 , 0x000000a0 }, + { 0x000167c4 , 0x000c0000 }, + { 0x000167c8 , 0x14021402 }, + { 0x000167cc , 0x00001402 }, + { 0x000167d0 , 0x00000000 }, + { 0x000167d4 , 0x00000000 }, + { 0x00016800 , 0x36db6db6 }, + { 0x00016804 , 0x6db6db40 }, + { 0x00016808 , 0x73f00000 }, + { 0x0001680c , 0x00000000 }, + { 0x00016840 , 0x7f80fff8 }, + { 0x0001684c , 0x76d005b5 }, + { 0x00016850 , 0x556cf031 }, + { 0x00016854 , 0x13449440 }, + { 0x00016858 , 0x0c51c92c }, + { 0x0001685c , 0x3db7fffc }, + { 0x00016860 , 0xfffffffc }, + { 0x00016864 , 0x000f0278 }, + { 0x0001686c , 0x6db60000 }, + { 0x00016900 , 0x3fffbe01 }, + { 0x00016904 , 0xfff80000 }, + { 0x00016908 , 0x00080010 }, + { 0x00016944 , 0x02084080 }, + { 0x00016948 , 0x00000000 }, + { 0x00016b80 , 0x00000000 }, + { 0x00016b84 , 0x00000000 }, + { 0x00016b88 , 0x00800700 }, + { 0x00016b8c , 0x00800700 }, + { 0x00016b90 , 0x00800700 }, + { 0x00016b94 , 0x00000000 }, + { 0x00016b98 , 0x00000000 }, + { 0x00016b9c , 0x00000000 }, + { 0x00016ba0 , 0x00000001 }, + { 0x00016ba4 , 0x00000001 }, + { 0x00016ba8 , 0x00000000 }, + { 0x00016bac , 0x00000000 }, + { 0x00016bb0 , 0x00000000 }, + { 0x00016bb4 , 0x00000000 }, + { 0x00016bb8 , 0x00000000 }, + { 0x00016bbc , 0x00000000 }, + { 0x00016bc0 , 0x000000a0 }, + { 0x00016bc4 , 0x000c0000 }, + { 0x00016bc8 , 0x14021402 }, + { 0x00016bcc , 0x00001402 }, + { 0x00016bd0 , 0x00000000 }, + { 0x00016bd4 , 0x00000000 }, +#endif +}; + +static const u_int32_t ar9300_osprey_2p2_tx_gain_table_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000000d5 , 0x000000d5 , 0x000000d5 , 0x000000d5 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x00004002 , 0x00004002 , 0x00004002 , 0x00004002 }, + { 0x0000a508 , 0x00008004 , 0x00008004 , 0x00008004 , 0x00008004 }, + { 0x0000a510 , 0x0001000c , 0x0001000c , 0x0001000c , 0x0001000c }, + { 0x0000a514 , 0x0001420b , 0x0001420b , 0x0001420b , 0x0001420b }, + { 0x0000a518 , 0x0001824a , 0x0001824a , 0x0001824a , 0x0001824a }, + { 0x0000a51c , 0x0001c44a , 0x0001c44a , 0x0001c44a , 0x0001c44a }, + { 0x0000a520 , 0x0002064a , 0x0002064a , 0x0002064a , 0x0002064a }, + { 0x0000a524 , 0x0002484a , 0x0002484a , 0x0002484a , 0x0002484a }, + { 0x0000a528 , 0x00028a4a , 0x00028a4a , 0x00028a4a , 0x00028a4a }, + { 0x0000a52c , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a }, + { 0x0000a530 , 0x00030e4a , 0x00030e4a , 0x00030e4a , 0x00030e4a }, + { 0x0000a534 , 0x00034e8a , 0x00034e8a , 0x00034e8a , 0x00034e8a }, +}; + +static const u_int32_t ar9300Modes_fast_clock_osprey_2p2[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00001030 , 0x00000268 , 0x000004d0 }, + { 0x00001070 , 0x0000018c , 0x00000318 }, + { 0x000010b0 , 0x00000fd0 , 0x00001fa0 }, + { 0x00008014 , 0x044c044c , 0x08980898 }, + { 0x0000801c , 0x148ec02b , 0x148ec057 }, + { 0x00008318 , 0x000044c0 , 0x00008980 }, + { 0x00009e00 , 0x0372131c , 0x0372131c }, + { 0x0000a230 , 0x0000000b , 0x00000016 }, + { 0x0000a254 , 0x00000898 , 0x00001130 }, +}; + +static const u_int32_t ar9300_osprey_2p2_radio_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ +#ifndef AR9340_EMULATION + { 0x0001609c , 0x0dd08f29 , 0x0dd08f29 , 0x0b283f31 , 0x0b283f31 }, + { 0x000160ac , 0xa4653c00 , 0xa4653c00 , 0x24652800 , 0x24652800 }, + { 0x000160b0 , 0x03284f3e , 0x03284f3e , 0x05d08f20 , 0x05d08f20 }, + { 0x0001610c , 0xc8000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016140 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, + { 0x0001650c , 0xc8000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016540 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, + { 0x0001690c , 0xc8000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016940 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, +#endif +}; + +static const u_int32_t ar9300_osprey_2p2_mac_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00000030 , 0x00020085 }, + { 0x00000044 , 0x00000008 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008344 , 0xaa4a105b }, +}; + +static const u_int32_t ar9300_osprey_2p2_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e3c , 0xcf946221 , 0xcf946221 , 0xcf946221 , 0xcf946221 }, + { 0x00009e44 , 0x005c0000 , 0x005c0000 , 0x005c0000 , 0x005c0000 }, + { 0x0000a258 , 0x02020200 , 0x02020200 , 0x02020200 , 0x02020200 }, + { 0x0000a25c , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a28c , 0x00011111 , 0x00011111 , 0x00011111 , 0x00011111 }, + { 0x0000a2c4 , 0x00148d18 , 0x00148d18 , 0x00148d20 , 0x00148d20 }, + { 0x0000a2d8 , 0xf999a801 , 0xf999a801 , 0xf999a80d , 0xf999a80d }, + { 0x0000a50c , 0x0000c00a , 0x0000c00a , 0x0000c00a , 0x0000c00a }, + { 0x0000a538 , 0x00038e8c , 0x00038e8c , 0x00038e8c , 0x00038e8c }, + { 0x0000a53c , 0x0003cecc , 0x0003cecc , 0x0003cecc , 0x0003cecc }, + { 0x0000a540 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 }, + { 0x0000a544 , 0x00044edc , 0x00044edc , 0x00044edc , 0x00044edc }, + { 0x0000a548 , 0x00048ede , 0x00048ede , 0x00048ede , 0x00048ede }, + { 0x0000a54c , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e }, + { 0x0000a550 , 0x00050f5e , 0x00050f5e , 0x00050f5e , 0x00050f5e }, + { 0x0000a554 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000be18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +#ifdef AR9340_EMULATION + { 0x0000b830 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000be04 , 0x00001000 , 0x00001000 , 0x00001000 , 0x00001000 }, + { 0x0000be1c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000c284 , 0x00000010 , 0x00000010 , 0x00000010 , 0x00000010 }, +#endif +}; + +static const u_int32_t ar9300_osprey_2p2_baseband_core[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009804 , 0xfd14e000 }, + { 0x00009808 , 0x9c0a9f6b }, + { 0x0000980c , 0x04900000 }, + { 0x00009814 , 0x9280c00a }, + { 0x00009818 , 0x00000000 }, + { 0x0000981c , 0x00020028 }, + { 0x00009834 , 0x6400a290 }, + { 0x00009838 , 0x0108ecff }, + { 0x0000983c , 0x14000600 }, + { 0x00009880 , 0x201fff00 }, + { 0x00009884 , 0x00001042 }, + { 0x000098a4 , 0x00200400 }, + { 0x000098b0 , 0x32840bbe }, + { 0x000098d0 , 0x004b6a8e }, + { 0x000098d4 , 0x00000820 }, + { 0x000098dc , 0x00000000 }, + { 0x000098f0 , 0x00000000 }, + { 0x000098f4 , 0x00000000 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009c0c , 0x00000000 }, + { 0x00009c10 , 0x00000000 }, + { 0x00009c14 , 0x00046384 }, + { 0x00009c18 , 0x05b6b440 }, + { 0x00009c1c , 0x00b6b440 }, + { 0x00009d00 , 0xc080a333 }, + { 0x00009d04 , 0x40206c10 }, + { 0x00009d08 , 0x009c4060 }, + { 0x00009d0c , 0x9883800a }, + { 0x00009d10 , 0x01834061 }, + { 0x00009d14 , 0x00c0040b }, + { 0x00009d18 , 0x00000000 }, + { 0x00009e08 , 0x0038230c }, + { 0x00009e24 , 0x990bb515 }, + { 0x00009e28 , 0x0c6f0000 }, + { 0x00009e30 , 0x06336f77 }, + { 0x00009e34 , 0x6af6532f }, + { 0x00009e38 , 0x0cc80c00 }, + { 0x00009e40 , 0x0d261820 }, + { 0x00009e4c , 0x00001004 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009e54 , 0x00000000 }, + { 0x00009fc0 , 0x803e4788 }, + { 0x00009fc4 , 0x0001efb5 }, + { 0x00009fcc , 0x40000014 }, + { 0x00009fd0 , 0x01193b93 }, + { 0x0000a20c , 0x00000000 }, + { 0x0000a220 , 0x00000000 }, + { 0x0000a224 , 0x00000000 }, + { 0x0000a228 , 0x10002310 }, + { 0x0000a23c , 0x00000000 }, + { 0x0000a244 , 0x0c000000 }, + { 0x0000a2a0 , 0x00000001 }, + { 0x0000a2c0 , 0x00000001 }, + { 0x0000a2c8 , 0x00000000 }, + { 0x0000a2cc , 0x18c43433 }, + { 0x0000a2d4 , 0x00000000 }, + { 0x0000a2ec , 0x00000000 }, + { 0x0000a2f0 , 0x00000000 }, + { 0x0000a2f4 , 0x00000000 }, + { 0x0000a2f8 , 0x00000000 }, + { 0x0000a344 , 0x00000000 }, + { 0x0000a34c , 0x00000000 }, + { 0x0000a350 , 0x0000a000 }, + { 0x0000a364 , 0x00000000 }, + { 0x0000a370 , 0x00000000 }, + { 0x0000a390 , 0x00000001 }, + { 0x0000a394 , 0x00000444 }, + { 0x0000a398 , 0x001f0e0f }, + { 0x0000a39c , 0x0075393f }, + { 0x0000a3a0 , 0xb79f6427 }, + { 0x0000a3a4 , 0x00000000 }, + { 0x0000a3a8 , 0xaaaaaaaa }, + { 0x0000a3ac , 0x3c466478 }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a3c8 , 0x20200020 }, + { 0x0000a3cc , 0x20202020 }, + { 0x0000a3d0 , 0x20202020 }, + { 0x0000a3d4 , 0x20202020 }, + { 0x0000a3d8 , 0x20202020 }, + { 0x0000a3dc , 0x20202020 }, + { 0x0000a3e0 , 0x20202020 }, + { 0x0000a3e4 , 0x20202020 }, + { 0x0000a3e8 , 0x20202020 }, + { 0x0000a3ec , 0x20202020 }, + { 0x0000a3f0 , 0x00000000 }, + { 0x0000a3f4 , 0x00000000 }, + { 0x0000a3f8 , 0x0c9bd380 }, + { 0x0000a3fc , 0x000f0f01 }, + { 0x0000a400 , 0x8fa91f01 }, + { 0x0000a404 , 0x00000000 }, + { 0x0000a408 , 0x0e79e5c6 }, + { 0x0000a40c , 0x00820820 }, + { 0x0000a414 , 0x1ce739ce }, + { 0x0000a418 , 0x2d001dce }, + { 0x0000a41c , 0x1ce739ce }, + { 0x0000a420 , 0x000001ce }, + { 0x0000a424 , 0x1ce739ce }, + { 0x0000a428 , 0x000001ce }, + { 0x0000a42c , 0x1ce739ce }, + { 0x0000a430 , 0x1ce739ce }, + { 0x0000a434 , 0x00000000 }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a43c , 0x00100000 }, + { 0x0000a440 , 0x00000000 }, + { 0x0000a444 , 0x00000000 }, + { 0x0000a448 , 0x05000080 }, + { 0x0000a44c , 0x00000001 }, + { 0x0000a450 , 0x00010000 }, + { 0x0000a458 , 0x00000000 }, + { 0x0000a640 , 0x00000000 }, + { 0x0000a644 , 0x3fad9d74 }, + { 0x0000a648 , 0x0048060a }, + { 0x0000a64c , 0x00003c37 }, + { 0x0000a670 , 0x03020100 }, + { 0x0000a674 , 0x09080504 }, + { 0x0000a678 , 0x0d0c0b0a }, + { 0x0000a67c , 0x13121110 }, + { 0x0000a680 , 0x31301514 }, + { 0x0000a684 , 0x35343332 }, + { 0x0000a688 , 0x00000036 }, + { 0x0000a690 , 0x00000838 }, + { 0x0000a7c0 , 0x00000000 }, + { 0x0000a7c4 , 0xfffffffc }, + { 0x0000a7c8 , 0x00000000 }, + { 0x0000a7cc , 0x00000000 }, + { 0x0000a7d0 , 0x00000000 }, + { 0x0000a7d4 , 0x00000004 }, + { 0x0000a7dc , 0x00000001 }, + { 0x0000a8d0 , 0x004b6a8e }, + { 0x0000a8d4 , 0x00000820 }, + { 0x0000a8dc , 0x00000000 }, + { 0x0000a8f0 , 0x00000000 }, + { 0x0000a8f4 , 0x00000000 }, + { 0x0000b2d0 , 0x00000080 }, + { 0x0000b2d4 , 0x00000000 }, + { 0x0000b2ec , 0x00000000 }, + { 0x0000b2f0 , 0x00000000 }, + { 0x0000b2f4 , 0x00000000 }, + { 0x0000b2f8 , 0x00000000 }, + { 0x0000b408 , 0x0e79e5c0 }, + { 0x0000b40c , 0x00820820 }, + { 0x0000b420 , 0x00000000 }, + { 0x0000b8d0 , 0x004b6a8e }, + { 0x0000b8d4 , 0x00000820 }, + { 0x0000b8dc , 0x00000000 }, + { 0x0000b8f0 , 0x00000000 }, + { 0x0000b8f4 , 0x00000000 }, + { 0x0000c2d0 , 0x00000080 }, + { 0x0000c2d4 , 0x00000000 }, + { 0x0000c2ec , 0x00000000 }, + { 0x0000c2f0 , 0x00000000 }, + { 0x0000c2f4 , 0x00000000 }, + { 0x0000c2f8 , 0x00000000 }, + { 0x0000c408 , 0x0e79e5c0 }, + { 0x0000c40c , 0x00820820 }, + { 0x0000c420 , 0x00000000 }, +}; + +static const u_int32_t ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d8 , 0x000050d8 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x04002222 , 0x04002222 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x09002421 , 0x09002421 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x0d002621 , 0x0d002621 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x13004620 , 0x13004620 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x19004a20 , 0x19004a20 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x1d004e20 , 0x1d004e20 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x21005420 , 0x21005420 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x26005e20 , 0x26005e20 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x2b005e40 , 0x2b005e40 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x2f005e42 , 0x2f005e42 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x33005e44 , 0x33005e44 , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x38005e65 , 0x38005e65 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x3c005e69 , 0x3c005e69 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x40005e6b , 0x40005e6b , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x44005e6d , 0x44005e6d , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x49005e72 , 0x49005e72 , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x4e005eb2 , 0x4e005eb2 , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x53005f12 , 0x53005f12 , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x59025eb2 , 0x59025eb2 , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x5e025f12 , 0x5e025f12 , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x61027f12 , 0x61027f12 , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x6702bf12 , 0x6702bf12 , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x6b02bf14 , 0x6b02bf14 , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x6f02bf16 , 0x6f02bf16 , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a580 , 0x00802220 , 0x00802220 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x04802222 , 0x04802222 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x09802421 , 0x09802421 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x0d802621 , 0x0d802621 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x13804620 , 0x13804620 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x19804a20 , 0x19804a20 , 0x11800400 , 0x11800400 }, + { 0x0000a598 , 0x1d804e20 , 0x1d804e20 , 0x15800402 , 0x15800402 }, + { 0x0000a59c , 0x21805420 , 0x21805420 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x26805e20 , 0x26805e20 , 0x1b800603 , 0x1b800603 }, + { 0x0000a5a4 , 0x2b805e40 , 0x2b805e40 , 0x1f800a02 , 0x1f800a02 }, + { 0x0000a5a8 , 0x2f805e42 , 0x2f805e42 , 0x23800a04 , 0x23800a04 }, + { 0x0000a5ac , 0x33805e44 , 0x33805e44 , 0x26800a20 , 0x26800a20 }, + { 0x0000a5b0 , 0x38805e65 , 0x38805e65 , 0x2a800e20 , 0x2a800e20 }, + { 0x0000a5b4 , 0x3c805e69 , 0x3c805e69 , 0x2e800e22 , 0x2e800e22 }, + { 0x0000a5b8 , 0x40805e6b , 0x40805e6b , 0x31800e24 , 0x31800e24 }, + { 0x0000a5bc , 0x44805e6d , 0x44805e6d , 0x34801640 , 0x34801640 }, + { 0x0000a5c0 , 0x49805e72 , 0x49805e72 , 0x38801660 , 0x38801660 }, + { 0x0000a5c4 , 0x4e805eb2 , 0x4e805eb2 , 0x3b801861 , 0x3b801861 }, + { 0x0000a5c8 , 0x53805f12 , 0x53805f12 , 0x3e801a81 , 0x3e801a81 }, + { 0x0000a5cc , 0x59825eb2 , 0x59825eb2 , 0x42801a83 , 0x42801a83 }, + { 0x0000a5d0 , 0x5e825f12 , 0x5e825f12 , 0x44801c84 , 0x44801c84 }, + { 0x0000a5d4 , 0x61827f12 , 0x61827f12 , 0x48801ce3 , 0x48801ce3 }, + { 0x0000a5d8 , 0x6782bf12 , 0x6782bf12 , 0x4c801ce5 , 0x4c801ce5 }, + { 0x0000a5dc , 0x6b82bf14 , 0x6b82bf14 , 0x50801ce9 , 0x50801ce9 }, + { 0x0000a5e0 , 0x6f82bf16 , 0x6f82bf16 , 0x54801ceb , 0x54801ceb }, + { 0x0000a5e4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5e8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5ec , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5f0 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5f4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5f8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5fc , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00804000 , 0x00804000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x00804201 , 0x00804201 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x0280c802 , 0x0280c802 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x0280ca03 , 0x0280ca03 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x04c15104 , 0x04c15104 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04c15305 , 0x04c15305 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04c15305 , 0x04c15305 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, +#ifndef AR9340_EMULATION + { 0x00016044 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016048 , 0x8e480001 , 0x8e480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016448 , 0x8e480001 , 0x8e480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016848 , 0x8e480001 , 0x8e480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +#endif +}; + +static const u_int32_t ar9300_osprey_2p2_mac_core[][2] = { +/* Addr allmodes */ + { 0x00000008 , 0x00000000 }, + { 0x00000030 , 0x00020085 }, + { 0x00000034 , 0x00000005 }, + { 0x00000040 , 0x00000000 }, + { 0x00000044 , 0x00000000 }, + { 0x00000048 , 0x00000008 }, + { 0x0000004c , 0x00000010 }, + { 0x00000050 , 0x00000000 }, + { 0x00001040 , 0x002ffc0f }, + { 0x00001044 , 0x002ffc0f }, + { 0x00001048 , 0x002ffc0f }, + { 0x0000104c , 0x002ffc0f }, + { 0x00001050 , 0x002ffc0f }, + { 0x00001054 , 0x002ffc0f }, + { 0x00001058 , 0x002ffc0f }, + { 0x0000105c , 0x002ffc0f }, + { 0x00001060 , 0x002ffc0f }, + { 0x00001064 , 0x002ffc0f }, + { 0x000010f0 , 0x00000100 }, + { 0x00001270 , 0x00000000 }, + { 0x000012b0 , 0x00000000 }, + { 0x000012f0 , 0x00000000 }, + { 0x0000143c , 0x00000000 }, + { 0x0000147c , 0x00000000 }, + { 0x00008000 , 0x00000000 }, + { 0x00008004 , 0x00000000 }, + { 0x00008008 , 0x00000000 }, + { 0x0000800c , 0x00000000 }, + { 0x00008018 , 0x00000000 }, + { 0x00008020 , 0x00000000 }, + { 0x00008038 , 0x00000000 }, + { 0x0000803c , 0x00000000 }, + { 0x00008040 , 0x00000000 }, + { 0x00008044 , 0x00000000 }, + { 0x00008048 , 0x00000000 }, + { 0x0000804c , 0xffffffff }, + { 0x00008054 , 0x00000000 }, + { 0x00008058 , 0x00000000 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008060 , 0x0000000f }, + { 0x00008064 , 0x00000000 }, + { 0x00008070 , 0x00000310 }, + { 0x00008074 , 0x00000020 }, + { 0x00008078 , 0x00000000 }, + { 0x0000809c , 0x0000000f }, + { 0x000080a0 , 0x00000000 }, + { 0x000080a4 , 0x02ff0000 }, + { 0x000080a8 , 0x0e070605 }, + { 0x000080ac , 0x0000000d }, + { 0x000080b0 , 0x00000000 }, + { 0x000080b4 , 0x00000000 }, + { 0x000080b8 , 0x00000000 }, + { 0x000080bc , 0x00000000 }, + { 0x000080c0 , 0x2a800000 }, + { 0x000080c4 , 0x06900168 }, + { 0x000080c8 , 0x13881c20 }, + { 0x000080cc , 0x01f40000 }, + { 0x000080d0 , 0x00252500 }, + { 0x000080d4 , 0x00a00000 }, + { 0x000080d8 , 0x00400000 }, + { 0x000080dc , 0x00000000 }, + { 0x000080e0 , 0xffffffff }, + { 0x000080e4 , 0x0000ffff }, + { 0x000080e8 , 0x3f3f3f3f }, + { 0x000080ec , 0x00000000 }, + { 0x000080f0 , 0x00000000 }, + { 0x000080f4 , 0x00000000 }, + { 0x000080fc , 0x00020000 }, + { 0x00008100 , 0x00000000 }, + { 0x00008108 , 0x00000052 }, + { 0x0000810c , 0x00000000 }, + { 0x00008110 , 0x00000000 }, + { 0x00008114 , 0x000007ff }, + { 0x00008118 , 0x000000aa }, + { 0x0000811c , 0x00003210 }, + { 0x00008124 , 0x00000000 }, + { 0x00008128 , 0x00000000 }, + { 0x0000812c , 0x00000000 }, + { 0x00008130 , 0x00000000 }, + { 0x00008134 , 0x00000000 }, + { 0x00008138 , 0x00000000 }, + { 0x0000813c , 0x0000ffff }, + { 0x00008144 , 0xffffffff }, + { 0x00008168 , 0x00000000 }, + { 0x0000816c , 0x00000000 }, + { 0x000081c0 , 0x00000000 }, + { 0x000081c4 , 0x33332210 }, + { 0x000081ec , 0x00000000 }, + { 0x000081f0 , 0x00000000 }, + { 0x000081f4 , 0x00000000 }, + { 0x000081f8 , 0x00000000 }, + { 0x000081fc , 0x00000000 }, + { 0x00008240 , 0x00100000 }, + { 0x00008244 , 0x0010f400 }, + { 0x00008248 , 0x00000800 }, + { 0x0000824c , 0x0001e800 }, + { 0x00008250 , 0x00000000 }, + { 0x00008254 , 0x00000000 }, + { 0x00008258 , 0x00000000 }, + { 0x0000825c , 0x40000000 }, + { 0x00008260 , 0x00080922 }, +#ifdef AR9340_EMULATION + { 0x00008264 , 0x9d400010 }, +#else + { 0x00008264 , 0x9bc00010 }, +#endif + { 0x00008268 , 0xffffffff }, + { 0x0000826c , 0x0000ffff }, + { 0x00008270 , 0x00000000 }, + { 0x00008274 , 0x40000000 }, + { 0x00008278 , 0x003e4180 }, + { 0x0000827c , 0x00000004 }, + { 0x00008284 , 0x0000002c }, + { 0x00008288 , 0x0000002c }, + { 0x0000828c , 0x000000ff }, + { 0x00008294 , 0x00000000 }, + { 0x00008298 , 0x00000000 }, + { 0x0000829c , 0x00000000 }, + { 0x00008300 , 0x00000140 }, + { 0x00008314 , 0x00000000 }, + { 0x0000831c , 0x0000010d }, + { 0x00008328 , 0x00000000 }, + { 0x0000832c , 0x00000007 }, + { 0x00008330 , 0x00000302 }, + { 0x00008334 , 0x00000700 }, + { 0x00008338 , 0x00ff0000 }, + { 0x0000833c , 0x02400000 }, + { 0x00008340 , 0x000107ff }, + { 0x00008344 , 0xaa48105b }, + { 0x00008348 , 0x008f0000 }, + { 0x0000835c , 0x00000000 }, + { 0x00008360 , 0xffffffff }, + { 0x00008364 , 0xffffffff }, + { 0x00008368 , 0x00000000 }, + { 0x00008370 , 0x00000000 }, + { 0x00008374 , 0x000000ff }, + { 0x00008378 , 0x00000000 }, + { 0x0000837c , 0x00000000 }, + { 0x00008380 , 0xffffffff }, + { 0x00008384 , 0xffffffff }, + { 0x00008390 , 0xffffffff }, + { 0x00008394 , 0xffffffff }, + { 0x00008398 , 0x00000000 }, + { 0x0000839c , 0x00000000 }, + { 0x000083a0 , 0x00000000 }, + { 0x000083a4 , 0x0000fa14 }, + { 0x000083a8 , 0x000f0c00 }, + { 0x000083ac , 0x33332210 }, + { 0x000083b0 , 0x33332210 }, + { 0x000083b4 , 0x33332210 }, + { 0x000083b8 , 0x33332210 }, + { 0x000083bc , 0x00000000 }, + { 0x000083c0 , 0x00000000 }, + { 0x000083c4 , 0x00000000 }, + { 0x000083c8 , 0x00000000 }, + { 0x000083cc , 0x00000200 }, + { 0x000083d0 , 0x000301ff }, +}; + +static const u_int32_t ar9300_osprey_2p2_soc_preamble[][2] = { +/* Addr allmodes */ + { 0x000040a4 , 0x00a0c1c9 }, + { 0x00007008 , 0x00000000 }, + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000004c2 }, + { 0x00007048 , 0x00000008 }, +}; + +static const u_int32_t ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x52022470 , 0x52022470 , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x55022490 , 0x55022490 , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x59022492 , 0x59022492 , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x5d022692 , 0x5d022692 , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x61022892 , 0x61022892 , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x65024890 , 0x65024890 , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x69024892 , 0x69024892 , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x6e024c92 , 0x6e024c92 , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x74026e92 , 0x74026e92 , 0x5d001eec , 0x5d001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x12800400 , 0x12800400 }, + { 0x0000a598 , 0x21802220 , 0x21802220 , 0x16800402 , 0x16800402 }, + { 0x0000a59c , 0x27802223 , 0x27802223 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1c800603 , 0x1c800603 }, + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x21800a02 , 0x21800a02 }, + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x25800a04 , 0x25800a04 }, + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x28800a20 , 0x28800a20 }, + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2c800e20 , 0x2c800e20 }, + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x30800e22 , 0x30800e22 }, + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x34800e24 , 0x34800e24 }, + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x38801640 , 0x38801640 }, + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x3c801660 , 0x3c801660 }, + { 0x0000a5c4 , 0x52822470 , 0x52822470 , 0x3f801861 , 0x3f801861 }, + { 0x0000a5c8 , 0x55822490 , 0x55822490 , 0x43801a81 , 0x43801a81 }, + { 0x0000a5cc , 0x59822492 , 0x59822492 , 0x47801a83 , 0x47801a83 }, + { 0x0000a5d0 , 0x5d822692 , 0x5d822692 , 0x4a801c84 , 0x4a801c84 }, + { 0x0000a5d4 , 0x61822892 , 0x61822892 , 0x4e801ce3 , 0x4e801ce3 }, + { 0x0000a5d8 , 0x65824890 , 0x65824890 , 0x52801ce5 , 0x52801ce5 }, + { 0x0000a5dc , 0x69824892 , 0x69824892 , 0x56801ce9 , 0x56801ce9 }, + { 0x0000a5e0 , 0x6e824c92 , 0x6e824c92 , 0x5a801ceb , 0x5a801ceb }, + { 0x0000a5e4 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5e8 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5ec , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f0 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f4 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f8 , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5fc , 0x74826e92 , 0x74826e92 , 0x5d801eec , 0x5d801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x02004000 , 0x02004000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x02004801 , 0x02004801 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02808a02 , 0x02808a02 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0380ce03 , 0x0380ce03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04411104 , 0x04411104 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04411104 , 0x04411104 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, +#ifndef AR9340_EMULATION + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x62480001 , 0x62480001 , 0x62480001 , 0x62480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x62480001 , 0x62480001 , 0x62480001 , 0x62480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x62480001 , 0x62480001 , 0x62480001 , 0x62480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +#endif +}; + +static const u_int32_t ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x52022470 , 0x52022470 , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x55022490 , 0x55022490 , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x59022492 , 0x59022492 , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x5d022692 , 0x5d022692 , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x61022892 , 0x61022892 , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x65024890 , 0x65024890 , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x69024892 , 0x69024892 , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x6e024c92 , 0x6e024c92 , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x74026e92 , 0x74026e92 , 0x56001eec , 0x56001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x11800400 , 0x11800400 }, + { 0x0000a598 , 0x21802220 , 0x21802220 , 0x15800402 , 0x15800402 }, + { 0x0000a59c , 0x27802223 , 0x27802223 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1b800603 , 0x1b800603 }, + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x1f800a02 , 0x1f800a02 }, + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x23800a04 , 0x23800a04 }, + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x26800a20 , 0x26800a20 }, + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2a800e20 , 0x2a800e20 }, + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x2e800e22 , 0x2e800e22 }, + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x31800e24 , 0x31800e24 }, + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x34801640 , 0x34801640 }, + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x38801660 , 0x38801660 }, + { 0x0000a5c4 , 0x52822470 , 0x52822470 , 0x3b801861 , 0x3b801861 }, + { 0x0000a5c8 , 0x55822490 , 0x55822490 , 0x3e801a81 , 0x3e801a81 }, + { 0x0000a5cc , 0x59822492 , 0x59822492 , 0x42801a83 , 0x42801a83 }, + { 0x0000a5d0 , 0x5d822692 , 0x5d822692 , 0x44801c84 , 0x44801c84 }, + { 0x0000a5d4 , 0x61822892 , 0x61822892 , 0x48801ce3 , 0x48801ce3 }, + { 0x0000a5d8 , 0x65824890 , 0x65824890 , 0x4c801ce5 , 0x4c801ce5 }, + { 0x0000a5dc , 0x69824892 , 0x69824892 , 0x50801ce9 , 0x50801ce9 }, + { 0x0000a5e0 , 0x6e824c92 , 0x6e824c92 , 0x54801ceb , 0x54801ceb }, + { 0x0000a5e4 , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5e8 , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5ec , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5f0 , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5f4 , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5f8 , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a5fc , 0x74826e92 , 0x74826e92 , 0x56801eec , 0x56801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x02004000 , 0x02004000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x02004801 , 0x02004801 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02808a02 , 0x02808a02 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0380ce03 , 0x0380ce03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04411104 , 0x04411104 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04411104 , 0x04411104 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04411104 , 0x04411104 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x00033800 , 0x00033800 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0003c000 , 0x0003c000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03fc0000 , 0x03fc0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016048 , 0x66480001 , 0x66480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016448 , 0x66480001 , 0x66480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016848 , 0x66480001 , 0x66480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484[][2] = { +/* Addr allmodes */ + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x6f7f0301 }, + { 0x0000a3a0 , 0xca9228ee }, +}; + +static const u_int32_t ar9300_osprey_2p2_mac_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, +}; + +static const u_int32_t ar9300Modes_high_power_tx_gain_table_osprey_2p2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x15000028 , 0x15000028 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1b00002b , 0x1b00002b , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x1f020028 , 0x1f020028 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x2502002b , 0x2502002b , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2a04002a , 0x2a04002a , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2e06002a , 0x2e06002a , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x3302202d , 0x3302202d , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3804202c , 0x3804202c , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3c06202c , 0x3c06202c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4108202d , 0x4108202d , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4506402d , 0x4506402d , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4906222d , 0x4906222d , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4d062231 , 0x4d062231 , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x50082231 , 0x50082231 , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5608422e , 0x5608422e , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5a08442e , 0x5a08442e , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x5e0a4431 , 0x5e0a4431 , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x640a4432 , 0x640a4432 , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x680a4434 , 0x680a4434 , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x6c0a6434 , 0x6c0a6434 , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x6f0a6633 , 0x6f0a6633 , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x15800028 , 0x15800028 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1b80002b , 0x1b80002b , 0x12800400 , 0x12800400 }, + { 0x0000a598 , 0x1f820028 , 0x1f820028 , 0x16800402 , 0x16800402 }, + { 0x0000a59c , 0x2582002b , 0x2582002b , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2a84002a , 0x2a84002a , 0x1c800603 , 0x1c800603 }, + { 0x0000a5a4 , 0x2e86002a , 0x2e86002a , 0x21800a02 , 0x21800a02 }, + { 0x0000a5a8 , 0x3382202d , 0x3382202d , 0x25800a04 , 0x25800a04 }, + { 0x0000a5ac , 0x3884202c , 0x3884202c , 0x28800a20 , 0x28800a20 }, + { 0x0000a5b0 , 0x3c86202c , 0x3c86202c , 0x2c800e20 , 0x2c800e20 }, + { 0x0000a5b4 , 0x4188202d , 0x4188202d , 0x30800e22 , 0x30800e22 }, + { 0x0000a5b8 , 0x4586402d , 0x4586402d , 0x34800e24 , 0x34800e24 }, + { 0x0000a5bc , 0x4986222d , 0x4986222d , 0x38801640 , 0x38801640 }, + { 0x0000a5c0 , 0x4d862231 , 0x4d862231 , 0x3c801660 , 0x3c801660 }, + { 0x0000a5c4 , 0x50882231 , 0x50882231 , 0x3f801861 , 0x3f801861 }, + { 0x0000a5c8 , 0x5688422e , 0x5688422e , 0x43801a81 , 0x43801a81 }, + { 0x0000a5cc , 0x5a88442e , 0x5a88442e , 0x47801a83 , 0x47801a83 }, + { 0x0000a5d0 , 0x5e8a4431 , 0x5e8a4431 , 0x4a801c84 , 0x4a801c84 }, + { 0x0000a5d4 , 0x648a4432 , 0x648a4432 , 0x4e801ce3 , 0x4e801ce3 }, + { 0x0000a5d8 , 0x688a4434 , 0x688a4434 , 0x52801ce5 , 0x52801ce5 }, + { 0x0000a5dc , 0x6c8a6434 , 0x6c8a6434 , 0x56801ce9 , 0x56801ce9 }, + { 0x0000a5e0 , 0x6f8a6633 , 0x6f8a6633 , 0x5a801ceb , 0x5a801ceb }, + { 0x0000a5e4 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5e8 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5ec , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f0 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f4 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f8 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5fc , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01804601 , 0x01804601 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01804601 , 0x01804601 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x01804601 , 0x01804601 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x03408d02 , 0x03408d02 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x03410d04 , 0x03410d04 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x61200001 , 0x61200001 , 0x66480001 , 0x66480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x61200001 , 0x61200001 , 0x66480001 , 0x66480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x61200001 , 0x61200001 , 0x66480001 , 0x66480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9200_merlin_2p2_radio_core[][2] = { +/* Addr common */ + { 0x00007800 , 0x00040000 }, + { 0x00007804 , 0xdb005012 }, + { 0x00007808 , 0x04924914 }, + { 0x0000780c , 0x21084210 }, + { 0x00007810 , 0x6d801300 }, + { 0x00007814 , 0x0019beff }, + { 0x00007818 , 0x07e41000 }, + { 0x0000781c , 0x00392000 }, + { 0x00007820 , 0x92592480 }, + { 0x00007824 , 0x00040000 }, + { 0x00007828 , 0xdb005012 }, + { 0x0000782c , 0x04924914 }, + { 0x00007830 , 0x21084210 }, + { 0x00007834 , 0x6d801300 }, + { 0x00007838 , 0x0019beff }, + { 0x0000783c , 0x07e40000 }, + { 0x00007840 , 0x00392000 }, + { 0x00007844 , 0x92592480 }, + { 0x00007848 , 0x00100000 }, + { 0x0000784c , 0x773f0567 }, + { 0x00007850 , 0x54214514 }, + { 0x00007854 , 0x12035828 }, + { 0x00007858 , 0x92592692 }, + { 0x0000785c , 0x00000000 }, + { 0x00007860 , 0x56400000 }, + { 0x00007864 , 0x0a8e370e }, + { 0x00007868 , 0xc0102850 }, + { 0x0000786c , 0x812d4000 }, + { 0x00007870 , 0x807ec400 }, + { 0x00007874 , 0x001b6db0 }, + { 0x00007878 , 0x00376b63 }, + { 0x0000787c , 0x06db6db6 }, + { 0x00007880 , 0x006d8000 }, + { 0x00007884 , 0xffeffffe }, + { 0x00007888 , 0xffeffffe }, + { 0x0000788c , 0x00010000 }, + { 0x00007890 , 0x02060aeb }, + { 0x00007894 , 0x5a108000 }, +}; + +static const u_int32_t ar9300_osprey_2p2_baseband_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8011 , 0xd00a8011 }, + { 0x00009820 , 0x206a022e , 0x206a022e , 0x206a012e , 0x206a012e }, + { 0x00009824 , 0x5ac668d0 , 0x5ac668d0 , 0x5ac640d0 , 0x5ac640d0 }, + { 0x00009828 , 0x06903081 , 0x06903081 , 0x06903881 , 0x06903881 }, + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000119c , 0x0000119c }, + { 0x00009c00 , 0x000000c4 , 0x000000c4 , 0x000000c4 , 0x000000c4 }, + { 0x00009e00 , 0x0372111a , 0x0372111a , 0x037216a0 , 0x037216a0 }, + { 0x00009e04 , 0x001c2020 , 0x001c2020 , 0x001c2020 , 0x001c2020 }, + { 0x00009e0c , 0x6d4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + { 0x00009e10 , 0x7ec88d2e , 0x7ec88d2e , 0x7ec84d2e , 0x7ec84d2e }, + { 0x00009e14 , 0x37b9625e , 0x37b9625e , 0x3379605e , 0x33795d5e }, + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + { 0x00009e2c , 0x0000001c , 0x0000001c , 0x00000021 , 0x00000021 }, + { 0x00009e3c , 0xcf946222 , 0xcf946222 , 0xcf946222 , 0xcf946222 }, + { 0x00009e44 , 0x02321e27 , 0x02321e27 , 0x02291e27 , 0x02291e27 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302012 , 0x50302012 }, + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, +#ifdef AR9340_EMULATION + { 0x0000a204 , 0x013037c0 , 0x013037c4 , 0x013037c4 , 0x013037c0 }, +#else + { 0x0000a204 , 0x000036c0 , 0x000036c4 , 0x000036c4 , 0x000036c0 }, +#endif + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + { 0x0000a22c , 0x01026a2f , 0x01026a2f , 0x01026a2f , 0x01026a2f }, + { 0x0000a230 , 0x0000000a , 0x00000014 , 0x00000016 , 0x0000000b }, + { 0x0000a234 , 0x00000fff , 0x10000fff , 0x10000fff , 0x00000fff }, + { 0x0000a238 , 0xffb81018 , 0xffb81018 , 0xffb81018 , 0xffb81018 }, + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a260 , 0x0a021501 , 0x0a021501 , 0x3a021501 , 0x3a021501 }, + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, + { 0x0000a288 , 0x00000110 , 0x00000110 , 0x00000110 , 0x00000110 }, + { 0x0000a28c , 0x00022222 , 0x00022222 , 0x00022222 , 0x00022222 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2d0 , 0x00041981 , 0x00041981 , 0x00041981 , 0x00041982 }, + { 0x0000a2d8 , 0x7999a83b , 0x7999a83b , 0x7999a83b , 0x7999a83b }, + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a830 , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae04 , 0x001c0000 , 0x001c0000 , 0x001c0000 , 0x001c0000 }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000ae1c , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae20 , 0x000001b5 , 0x000001b5 , 0x000001ce , 0x000001ce }, + { 0x0000b284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, + { 0x0000b830 , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000be04 , 0x001c0000 , 0x001c0000 , 0x001c0000 , 0x001c0000 }, + { 0x0000be18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000be1c , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000be20 , 0x000001b5 , 0x000001b5 , 0x000001ce , 0x000001ce }, + { 0x0000c284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, +}; + +static const u_int32_t ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x03820190 }, + { 0x0000a030 , 0x03840383 }, + { 0x0000a034 , 0x03880385 }, + { 0x0000a038 , 0x038a0389 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x29292929 }, + { 0x0000a084 , 0x29292929 }, + { 0x0000a088 , 0x29292929 }, + { 0x0000a08c , 0x29292929 }, + { 0x0000a090 , 0x22292929 }, + { 0x0000a094 , 0x1d1d2222 }, + { 0x0000a098 , 0x0c111117 }, + { 0x0000a09c , 0x00030303 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x32323232 }, + { 0x0000b084 , 0x2f2f3232 }, + { 0x0000b088 , 0x23282a2d }, + { 0x0000b08c , 0x1c1e2123 }, + { 0x0000b090 , 0x14171919 }, + { 0x0000b094 , 0x0e0e1214 }, + { 0x0000b098 , 0x03050707 }, + { 0x0000b09c , 0x00030303 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar9300_osprey_2p2_soc_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00007010 , 0x00000023 , 0x00000023 , 0x00000023 , 0x00000023 }, +}; + +static const u_int32_t ar9300Common_rx_gain_table_merlin_2p2[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x02000101 }, + { 0x0000a004 , 0x02000102 }, + { 0x0000a008 , 0x02000103 }, + { 0x0000a00c , 0x02000104 }, + { 0x0000a010 , 0x02000200 }, + { 0x0000a014 , 0x02000201 }, + { 0x0000a018 , 0x02000202 }, + { 0x0000a01c , 0x02000203 }, + { 0x0000a020 , 0x02000204 }, + { 0x0000a024 , 0x02000205 }, + { 0x0000a028 , 0x02000208 }, + { 0x0000a02c , 0x02000302 }, + { 0x0000a030 , 0x02000303 }, + { 0x0000a034 , 0x02000304 }, + { 0x0000a038 , 0x02000400 }, + { 0x0000a03c , 0x02010300 }, + { 0x0000a040 , 0x02010301 }, + { 0x0000a044 , 0x02010302 }, + { 0x0000a048 , 0x02000500 }, + { 0x0000a04c , 0x02010400 }, + { 0x0000a050 , 0x02020300 }, + { 0x0000a054 , 0x02020301 }, + { 0x0000a058 , 0x02020302 }, + { 0x0000a05c , 0x02020303 }, + { 0x0000a060 , 0x02020400 }, + { 0x0000a064 , 0x02030300 }, + { 0x0000a068 , 0x02030301 }, + { 0x0000a06c , 0x02030302 }, + { 0x0000a070 , 0x02030303 }, + { 0x0000a074 , 0x02030400 }, + { 0x0000a078 , 0x02040300 }, + { 0x0000a07c , 0x02040301 }, + { 0x0000a080 , 0x02040302 }, + { 0x0000a084 , 0x02040303 }, + { 0x0000a088 , 0x02030500 }, + { 0x0000a08c , 0x02040400 }, + { 0x0000a090 , 0x02050203 }, + { 0x0000a094 , 0x02050204 }, + { 0x0000a098 , 0x02050205 }, + { 0x0000a09c , 0x02040500 }, + { 0x0000a0a0 , 0x02050301 }, + { 0x0000a0a4 , 0x02050302 }, + { 0x0000a0a8 , 0x02050303 }, + { 0x0000a0ac , 0x02050400 }, + { 0x0000a0b0 , 0x02050401 }, + { 0x0000a0b4 , 0x02050402 }, + { 0x0000a0b8 , 0x02050403 }, + { 0x0000a0bc , 0x02050500 }, + { 0x0000a0c0 , 0x02050501 }, + { 0x0000a0c4 , 0x02050502 }, + { 0x0000a0c8 , 0x02050503 }, + { 0x0000a0cc , 0x02050504 }, + { 0x0000a0d0 , 0x02050600 }, + { 0x0000a0d4 , 0x02050601 }, + { 0x0000a0d8 , 0x02050602 }, + { 0x0000a0dc , 0x02050603 }, + { 0x0000a0e0 , 0x02050604 }, + { 0x0000a0e4 , 0x02050700 }, + { 0x0000a0e8 , 0x02050701 }, + { 0x0000a0ec , 0x02050702 }, + { 0x0000a0f0 , 0x02050703 }, + { 0x0000a0f4 , 0x02050704 }, + { 0x0000a0f8 , 0x02050705 }, + { 0x0000a0fc , 0x02050708 }, + { 0x0000a100 , 0x02050709 }, + { 0x0000a104 , 0x0205070a }, + { 0x0000a108 , 0x0205070b }, + { 0x0000a10c , 0x0205070c }, + { 0x0000a110 , 0x0205070d }, + { 0x0000a114 , 0x02050710 }, + { 0x0000a118 , 0x02050711 }, + { 0x0000a11c , 0x02050712 }, + { 0x0000a120 , 0x02050713 }, + { 0x0000a124 , 0x02050714 }, + { 0x0000a128 , 0x02050715 }, + { 0x0000a12c , 0x02050730 }, + { 0x0000a130 , 0x02050731 }, + { 0x0000a134 , 0x02050732 }, + { 0x0000a138 , 0x02050733 }, + { 0x0000a13c , 0x02050734 }, + { 0x0000a140 , 0x02050735 }, + { 0x0000a144 , 0x02050750 }, + { 0x0000a148 , 0x02050751 }, + { 0x0000a14c , 0x02050752 }, + { 0x0000a150 , 0x02050753 }, + { 0x0000a154 , 0x02050754 }, + { 0x0000a158 , 0x02050755 }, + { 0x0000a15c , 0x02050770 }, + { 0x0000a160 , 0x02050771 }, + { 0x0000a164 , 0x02050772 }, + { 0x0000a168 , 0x02050773 }, + { 0x0000a16c , 0x02050774 }, + { 0x0000a170 , 0x02050775 }, + { 0x0000a174 , 0x00000776 }, + { 0x0000a178 , 0x00000776 }, + { 0x0000a17c , 0x00000776 }, + { 0x0000a180 , 0x00000776 }, + { 0x0000a184 , 0x00000776 }, + { 0x0000a188 , 0x00000776 }, + { 0x0000a18c , 0x00000776 }, + { 0x0000a190 , 0x00000776 }, + { 0x0000a194 , 0x00000776 }, + { 0x0000a198 , 0x00000776 }, + { 0x0000a19c , 0x00000776 }, + { 0x0000a1a0 , 0x00000776 }, + { 0x0000a1a4 , 0x00000776 }, + { 0x0000a1a8 , 0x00000776 }, + { 0x0000a1ac , 0x00000776 }, + { 0x0000a1b0 , 0x00000776 }, + { 0x0000a1b4 , 0x00000776 }, + { 0x0000a1b8 , 0x00000776 }, + { 0x0000a1bc , 0x00000776 }, + { 0x0000a1c0 , 0x00000776 }, + { 0x0000a1c4 , 0x00000776 }, + { 0x0000a1c8 , 0x00000776 }, + { 0x0000a1cc , 0x00000776 }, + { 0x0000a1d0 , 0x00000776 }, + { 0x0000a1d4 , 0x00000776 }, + { 0x0000a1d8 , 0x00000776 }, + { 0x0000a1dc , 0x00000776 }, + { 0x0000a1e0 , 0x00000776 }, + { 0x0000a1e4 , 0x00000776 }, + { 0x0000a1e8 , 0x00000776 }, + { 0x0000a1ec , 0x00000776 }, + { 0x0000a1f0 , 0x00000776 }, + { 0x0000a1f4 , 0x00000776 }, + { 0x0000a1f8 , 0x00000776 }, + { 0x0000a1fc , 0x00000776 }, + { 0x0000b000 , 0x02000101 }, + { 0x0000b004 , 0x02000102 }, + { 0x0000b008 , 0x02000103 }, + { 0x0000b00c , 0x02000104 }, + { 0x0000b010 , 0x02000200 }, + { 0x0000b014 , 0x02000201 }, + { 0x0000b018 , 0x02000202 }, + { 0x0000b01c , 0x02000203 }, + { 0x0000b020 , 0x02000204 }, + { 0x0000b024 , 0x02000205 }, + { 0x0000b028 , 0x02000208 }, + { 0x0000b02c , 0x02000302 }, + { 0x0000b030 , 0x02000303 }, + { 0x0000b034 , 0x02000304 }, + { 0x0000b038 , 0x02000400 }, + { 0x0000b03c , 0x02010300 }, + { 0x0000b040 , 0x02010301 }, + { 0x0000b044 , 0x02010302 }, + { 0x0000b048 , 0x02000500 }, + { 0x0000b04c , 0x02010400 }, + { 0x0000b050 , 0x02020300 }, + { 0x0000b054 , 0x02020301 }, + { 0x0000b058 , 0x02020302 }, + { 0x0000b05c , 0x02020303 }, + { 0x0000b060 , 0x02020400 }, + { 0x0000b064 , 0x02030300 }, + { 0x0000b068 , 0x02030301 }, + { 0x0000b06c , 0x02030302 }, + { 0x0000b070 , 0x02030303 }, + { 0x0000b074 , 0x02030400 }, + { 0x0000b078 , 0x02040300 }, + { 0x0000b07c , 0x02040301 }, + { 0x0000b080 , 0x02040302 }, + { 0x0000b084 , 0x02040303 }, + { 0x0000b088 , 0x02030500 }, + { 0x0000b08c , 0x02040400 }, + { 0x0000b090 , 0x02050203 }, + { 0x0000b094 , 0x02050204 }, + { 0x0000b098 , 0x02050205 }, + { 0x0000b09c , 0x02040500 }, + { 0x0000b0a0 , 0x02050301 }, + { 0x0000b0a4 , 0x02050302 }, + { 0x0000b0a8 , 0x02050303 }, + { 0x0000b0ac , 0x02050400 }, + { 0x0000b0b0 , 0x02050401 }, + { 0x0000b0b4 , 0x02050402 }, + { 0x0000b0b8 , 0x02050403 }, + { 0x0000b0bc , 0x02050500 }, + { 0x0000b0c0 , 0x02050501 }, + { 0x0000b0c4 , 0x02050502 }, + { 0x0000b0c8 , 0x02050503 }, + { 0x0000b0cc , 0x02050504 }, + { 0x0000b0d0 , 0x02050600 }, + { 0x0000b0d4 , 0x02050601 }, + { 0x0000b0d8 , 0x02050602 }, + { 0x0000b0dc , 0x02050603 }, + { 0x0000b0e0 , 0x02050604 }, + { 0x0000b0e4 , 0x02050700 }, + { 0x0000b0e8 , 0x02050701 }, + { 0x0000b0ec , 0x02050702 }, + { 0x0000b0f0 , 0x02050703 }, + { 0x0000b0f4 , 0x02050704 }, + { 0x0000b0f8 , 0x02050705 }, + { 0x0000b0fc , 0x02050708 }, + { 0x0000b100 , 0x02050709 }, + { 0x0000b104 , 0x0205070a }, + { 0x0000b108 , 0x0205070b }, + { 0x0000b10c , 0x0205070c }, + { 0x0000b110 , 0x0205070d }, + { 0x0000b114 , 0x02050710 }, + { 0x0000b118 , 0x02050711 }, + { 0x0000b11c , 0x02050712 }, + { 0x0000b120 , 0x02050713 }, + { 0x0000b124 , 0x02050714 }, + { 0x0000b128 , 0x02050715 }, + { 0x0000b12c , 0x02050730 }, + { 0x0000b130 , 0x02050731 }, + { 0x0000b134 , 0x02050732 }, + { 0x0000b138 , 0x02050733 }, + { 0x0000b13c , 0x02050734 }, + { 0x0000b140 , 0x02050735 }, + { 0x0000b144 , 0x02050750 }, + { 0x0000b148 , 0x02050751 }, + { 0x0000b14c , 0x02050752 }, + { 0x0000b150 , 0x02050753 }, + { 0x0000b154 , 0x02050754 }, + { 0x0000b158 , 0x02050755 }, + { 0x0000b15c , 0x02050770 }, + { 0x0000b160 , 0x02050771 }, + { 0x0000b164 , 0x02050772 }, + { 0x0000b168 , 0x02050773 }, + { 0x0000b16c , 0x02050774 }, + { 0x0000b170 , 0x02050775 }, + { 0x0000b174 , 0x00000776 }, + { 0x0000b178 , 0x00000776 }, + { 0x0000b17c , 0x00000776 }, + { 0x0000b180 , 0x00000776 }, + { 0x0000b184 , 0x00000776 }, + { 0x0000b188 , 0x00000776 }, + { 0x0000b18c , 0x00000776 }, + { 0x0000b190 , 0x00000776 }, + { 0x0000b194 , 0x00000776 }, + { 0x0000b198 , 0x00000776 }, + { 0x0000b19c , 0x00000776 }, + { 0x0000b1a0 , 0x00000776 }, + { 0x0000b1a4 , 0x00000776 }, + { 0x0000b1a8 , 0x00000776 }, + { 0x0000b1ac , 0x00000776 }, + { 0x0000b1b0 , 0x00000776 }, + { 0x0000b1b4 , 0x00000776 }, + { 0x0000b1b8 , 0x00000776 }, + { 0x0000b1bc , 0x00000776 }, + { 0x0000b1c0 , 0x00000776 }, + { 0x0000b1c4 , 0x00000776 }, + { 0x0000b1c8 , 0x00000776 }, + { 0x0000b1cc , 0x00000776 }, + { 0x0000b1d0 , 0x00000776 }, + { 0x0000b1d4 , 0x00000776 }, + { 0x0000b1d8 , 0x00000776 }, + { 0x0000b1dc , 0x00000776 }, + { 0x0000b1e0 , 0x00000776 }, + { 0x0000b1e4 , 0x00000776 }, + { 0x0000b1e8 , 0x00000776 }, + { 0x0000b1ec , 0x00000776 }, + { 0x0000b1f0 , 0x00000776 }, + { 0x0000b1f4 , 0x00000776 }, + { 0x0000b1f8 , 0x00000776 }, + { 0x0000b1fc , 0x00000776 }, +}; + +static const u_int32_t ar9300_common_rx_gain_table_osprey_2p2[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x01910190 }, + { 0x0000a030 , 0x01930192 }, + { 0x0000a034 , 0x01950194 }, + { 0x0000a038 , 0x038a0196 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x22222229 }, + { 0x0000a084 , 0x1d1d1d1d }, + { 0x0000a088 , 0x1d1d1d1d }, + { 0x0000a08c , 0x1d1d1d1d }, + { 0x0000a090 , 0x171d1d1d }, + { 0x0000a094 , 0x11111717 }, + { 0x0000a098 , 0x00030311 }, + { 0x0000a09c , 0x00000000 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x2a2d2f32 }, + { 0x0000b084 , 0x21232328 }, + { 0x0000b088 , 0x19191c1e }, + { 0x0000b08c , 0x12141417 }, + { 0x0000b090 , 0x07070e0e }, + { 0x0000b094 , 0x03030305 }, + { 0x0000b098 , 0x00000003 }, + { 0x0000b09c , 0x00000000 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +/* PCIE-PHY programming array */ +static const u_int32_t ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2[][2] = { +{0x00004040, 0x0821265e}, +{0x00004040, 0x0008003b}, +{0x00004044, 0x00000000}, +}; + +/* PCIE-PHY programming array */ +static const u_int32_t ar9300PciePhy_clkreq_enable_L1_osprey_2p2[][2] = { +{0x00004040, 0x0825365e}, +{0x00004040, 0x0008003b}, +{0x00004044, 0x00000000}, +}; + +/* PCIE-PHY programming array */ +static const u_int32_t ar9300PciePhy_clkreq_disable_L1_osprey_2p2[][2] = { +{0x00004040, 0x0821365e}, +{0x00004040, 0x0008003b}, +{0x00004044, 0x00000000}, +}; + diff --git a/hal/ar9300/ar9300_paprd.c b/hal/ar9300/ar9300_paprd.c new file mode 100644 index 000000000000..36ab31af7765 --- /dev/null +++ b/hal/ar9300/ar9300_paprd.c @@ -0,0 +1,2443 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" +#include "ah.h" +#include "ar9300.h" +#include "ah_internal.h" +#include "ar9300paprd.h" +#include "ar9300reg.h" + + +#if ATH_SUPPORT_PAPRD + +static struct ar9300_paprd_pwr_adjust ar9300_paprd_pwr_adj_array[] = { +/* rate index , register offset , mask of register , */ + {ALL_TARGET_HT20_5, AR_PHY_POWERTX_RATE5, AR_PHY_POWERTX_RATE5_POWERTXHT20_3, +/* mask offset of register , offset dB*/ + AR_PHY_POWERTX_RATE5_POWERTXHT20_3_S, 1}, + {ALL_TARGET_HT20_6, AR_PHY_POWERTX_RATE6, AR_PHY_POWERTX_RATE6_POWERTXHT20_4, + AR_PHY_POWERTX_RATE6_POWERTXHT20_4_S, 2}, + {ALL_TARGET_HT20_7, AR_PHY_POWERTX_RATE6, AR_PHY_POWERTX_RATE6_POWERTXHT20_5, + AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S, 2}, + {ALL_TARGET_HT40_5, AR_PHY_POWERTX_RATE7, AR_PHY_POWERTX_RATE7_POWERTXHT40_3, + AR_PHY_POWERTX_RATE7_POWERTXHT40_3_S, 1}, + {ALL_TARGET_HT40_6, AR_PHY_POWERTX_RATE8, AR_PHY_POWERTX_RATE8_POWERTXHT40_4, + AR_PHY_POWERTX_RATE8_POWERTXHT40_4_S, 2}, + {ALL_TARGET_HT40_7, AR_PHY_POWERTX_RATE8, AR_PHY_POWERTX_RATE8_POWERTXHT40_5, + AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S, 2}, + {ALL_TARGET_LEGACY_54, AR_PHY_POWERTX_RATE2, AR_PHY_POWERTX_RATE2_POWERTX54M_7, + AR_PHY_POWERTX_RATE2_POWERTX54M_7_S, 2}, +}; + +HAL_BOOL create_pa_curve(u_int32_t * paprd_train_data_l, + u_int32_t *paprd_train_data_u, u_int32_t *pa_table, u_int32_t *g_fxp_ext, + int * pa_in); + +#define AR9300_IS_CHAN(_c, _f) (((_c)->channel_flags & _f) || 0) + +static int +ar9300_paprd_setup_single_table(struct ath_hal *ah, HAL_CHANNEL * chan) +{ + int is_2g = AR9300_IS_CHAN(chan, CHANNEL_2GHZ); + struct ath_hal_9300 *ahp = AH9300(ah); + int is_ht40 = 0; + u_int32_t am_mask = 0; + u_int32_t val = OS_REG_READ(ah, AR_2040_MODE); + u_int8_t target_power_val_t2[ar9300_rate_size]; + int power_tblindex = 0, power_delta = 0; + int paprd_scale_factor = 5; + + const u_int8_t mask2num[8] = { + 0 /* 000 */, + 1 /* 001 */, + 1 /* 010 */, + 2 /* 011 */, + 1 /* 100 */, + 2 /* 101 */, + 2 /* 110 */, + 3 /* 111 */ + }; + + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + +#define ABS(_x, _y) ((int)_x > (int)_y ? (int)_x - (int)_y : (int)_y - (int)_x) + + ar9300_set_target_power_from_eeprom(ah, chan->channel, target_power_val_t2); + if (val & HAL_HT_MACMODE_2040) { + is_ht40 = 1; + } + + /* + * Note on paprd_scale_factor + * This factor is saved in eeprom as 3 bit fields in following fashion. + * In 5G there are 3 scale factors -- upper, mid and lower band. + * Upper band scale factor is coded in bits 25-27 of + * modal_header_5g.paprd_rate_mask_ht20. + * Mid band scale factor is coded in bits 28-30 of + * modal_header_5g.paprd_rate_mask_ht40. + * Lower band scale factor is coded in bits 25-27 of + * modal_header_5g.paprd_rate_mask_ht40. + * For 2G there is only one scale factor. It is saved in bits 25-27 of + * modal_header_2g.paprd_rate_mask_ht20. + */ + AH_PAPRD_GET_SCALE_FACTOR(paprd_scale_factor, eep, is_2g, chan->channel); + if (is_2g) { + if (is_ht40) { + am_mask = ahp->ah_2g_paprd_rate_mask_ht40 & AH_PAPRD_AM_PM_MASK; + power_tblindex = ALL_TARGET_HT40_0_8_16; + } else { + am_mask = ahp->ah_2g_paprd_rate_mask_ht20 & AH_PAPRD_AM_PM_MASK; + power_tblindex = ALL_TARGET_HT20_0_8_16; + } + if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + if (is_ht40) { + ahp->paprd_training_power = + target_power_val_t2[ALL_TARGET_HT40_7] + 2; + } else { + ahp->paprd_training_power = + target_power_val_t2[ALL_TARGET_HT20_7] + 2; + } + } else if (AR_SREV_POSEIDON(ah)) { + ahp->paprd_training_power = 25; + } else { + ahp->paprd_training_power = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_POWERTX_RATE5, + AR_PHY_POWERTX_RATE5_POWERTXHT20_0); + if (ABS(target_power_val_t2[power_tblindex], + ahp->paprd_training_power) > paprd_scale_factor) + { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s[%d]: Chan %d paprd failing EEP PWR 0x%08x" + "TGT PWR 0x%08x\n", __func__, __LINE__, chan->channel, + target_power_val_t2[power_tblindex], + ahp->paprd_training_power); + goto FAILED; + } + + power_delta = + ABS(ahp->paprd_training_power, + target_power_val_t2[power_tblindex]); + + power_delta = power_delta > 4 ? 0 : 4 - power_delta; + ahp->paprd_training_power = + ahp->paprd_training_power - power_delta; + } + + + } else { + if (is_ht40) { + ahp->paprd_training_power = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_POWERTX_RATE8, + AR_PHY_POWERTX_RATE8_POWERTXHT40_5); + am_mask = ahp->ah_5g_paprd_rate_mask_ht40 & AH_PAPRD_AM_PM_MASK; + switch (mask2num[ahp->ah_tx_chainmask]) + { + case 1: + power_delta = 6; + break; + case 2: + power_delta = 4; + break; + case 3: + power_delta = 2; + break; + default: + goto FAILED; + break; + } + power_tblindex = ALL_TARGET_HT40_7; + } else { + ahp->paprd_training_power = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_POWERTX_RATE6, + AR_PHY_POWERTX_RATE6_POWERTXHT20_5); + am_mask = ahp->ah_5g_paprd_rate_mask_ht20 & AH_PAPRD_AM_PM_MASK; + switch (mask2num[ahp->ah_tx_chainmask]) + { + case 1: + power_delta = 6; + break; + case 2: + power_delta = 4; + break; + case 3: + power_delta = 2; + break; + default: + goto FAILED; + break; + } + power_tblindex = ALL_TARGET_HT20_7; + } + /* Adjust for scale factor */ + ahp->paprd_training_power += paprd_scale_factor; + /* + ath_hal_printf(ah, "%s[%d] paprd_scale_factor %d power_delta %d\n", + __func__, __LINE__, paprd_scale_factor, power_delta); + */ + if (ABS(target_power_val_t2[power_tblindex], ahp->paprd_training_power) + > paprd_scale_factor) + { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s[%d]: Chan %d paprd failing EEP PWR 0x%08x TGT PWR 0x%08x\n", + __func__, __LINE__, chan->channel, + target_power_val_t2[power_tblindex], ahp->paprd_training_power); + goto FAILED; + } + ahp->paprd_training_power = ahp->paprd_training_power + power_delta; + } + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s 2G %d HT40 %d am_mask 0x%08x\n", + __func__, is_2g, is_ht40, am_mask); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK, + am_mask); + if (AR_SREV_HORNET(ah)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, + 0); + } + else { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, + am_mask); + } + + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, + AR_PHY_PAPRD_HT40_MASK); + /* chain0 */ + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN0_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0, + AR_PHY_PAPRD_CTRL0_B0_USE_SINGLE_TABLE_MASK, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2PM_ENABLE_0, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2AM_ENABLE_0, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_PA_GAIN_SCALE_FACT_0_MASK, 181); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_PAPRD_MAG_SCALE_FACT_0, 361); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0, + AR_PHY_PAPRD_CTRL0_B0_PAPRD_MAG_THRSH_0, 3); + } + + /* chain1 */ + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN1_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1, + AR_PHY_PAPRD_CTRL0_B1_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2PM_ENABLE_1, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2AM_ENABLE_1, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_PA_GAIN_SCALE_FACT_1_MASK, 181); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_PAPRD_MAG_SCALE_FACT_1, 361); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1, + AR_PHY_PAPRD_CTRL0_B1_PAPRD_MAG_THRSH_1, 3); + } + + /* chain2 */ + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2, + AR_PHY_PAPRD_CTRL0_B2_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2PM_ENABLE_2, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2AM_ENABLE_2, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_PA_GAIN_SCALE_FACT_2_MASK, 181); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_PAPRD_MAG_SCALE_FACT_2, 361); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2, + AR_PHY_PAPRD_CTRL0_B2_PAPRD_MAG_THRSH_2, 3); + } + + ar9300_enable_paprd(ah, AH_FALSE, chan); + if (AR_SREV_POSEIDON(ah)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP, 0x30); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, 148); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN, 4); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN, 4); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -3); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, -15); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR, 400); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES, 100); + } else { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP, 0x30); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1); + if (is_2g) { + if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2, + AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, 0x91); + }else{ + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2, + AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, 147); + } + } + else if (AR_SREV_WASP(ah) && !is_2g) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2, + AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, 137); + } else { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2, + AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, 147); + } + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN, 4); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN, 4); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1); + if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -3); + } else { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -6); + } + if (is_2g) { + if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, -10); + }else{ + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, -15); + } + } + else { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, -10); + } + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4, + AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4, + AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR, 400); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4, + AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES, 100); + } + + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_0_B0, + AR_PHY_PAPRD_PRE_POST_SCALE_0_B0_PAPRD_PRE_POST_SCALING_0_0, 261376); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_1_B0, + AR_PHY_PAPRD_PRE_POST_SCALE_1_B0_PAPRD_PRE_POST_SCALING_1_0, 248079); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_2_B0, + AR_PHY_PAPRD_PRE_POST_SCALE_2_B0_PAPRD_PRE_POST_SCALING_2_0, 233759); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_3_B0, + AR_PHY_PAPRD_PRE_POST_SCALE_3_B0_PAPRD_PRE_POST_SCALING_3_0, 220464); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_4_B0, + AR_PHY_PAPRD_PRE_POST_SCALE_4_B0_PAPRD_PRE_POST_SCALING_4_0, 208194); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_5_B0, + AR_PHY_PAPRD_PRE_POST_SCALE_5_B0_PAPRD_PRE_POST_SCALING_5_0, 196949); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_6_B0, + AR_PHY_PAPRD_PRE_POST_SCALE_6_B0_PAPRD_PRE_POST_SCALING_6_0, 185706); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_7_B0, + AR_PHY_PAPRD_PRE_POST_SCALE_7_B0_PAPRD_PRE_POST_SCALING_7_0, 175487); + return 0; + +FAILED: + return -1; +#undef ABS +} + +static inline HAL_CHANNEL_INTERNAL* +ar9300_check_chan(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + if ((AR9300_IS_CHAN(chan, CHANNEL_2GHZ) ^ + AR9300_IS_CHAN(chan, CHANNEL_5GHZ)) == 0) + { + HALDEBUG(ah, HAL_DEBUG_CHANNEL, + "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n", + __func__, chan->channel, chan->channel_flags); + return AH_NULL; + } + + if ((AR9300_IS_CHAN(chan, CHANNEL_OFDM) ^ + AR9300_IS_CHAN(chan, CHANNEL_CCK) ^ + AR9300_IS_CHAN(chan, CHANNEL_HT20) ^ + AR9300_IS_CHAN(chan, CHANNEL_HT40PLUS) ^ + AR9300_IS_CHAN(chan, CHANNEL_HT40MINUS)) == 0) + { + HALDEBUG(ah, HAL_DEBUG_CHANNEL, + "%s: invalid channel %u/0x%x; not marked as " + "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n", __func__, + chan->channel, chan->channel_flags); + return AH_NULL; + } + + return (ath_hal_checkchannel(ah, chan)); +} + +void ar9300_enable_paprd(struct ath_hal *ah, HAL_BOOL enable_flag, + HAL_CHANNEL * chan) +{ + HAL_BOOL enable = enable_flag; + u_int32_t am_mask = 0; + u_int32_t val = OS_REG_READ(ah, AR_2040_MODE); + int is_2g = AR9300_IS_CHAN(chan, CHANNEL_2GHZ); + int is_ht40 = 0; + struct ath_hal_9300 *ahp = AH9300(ah); + + if (val & HAL_HT_MACMODE_2040) { + is_ht40 = 1; + } + if (enable_flag == AH_TRUE) { + ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; + + if (!is_2g) { + /* + * 3 bits for modal_header_5g.paprd_rate_mask_ht20 + * is used for sub band disabling of paprd. + * 5G band is divided into 3 sub bands -- upper, mid, lower. + * If bit 30 of modal_header_5g.paprd_rate_mask_ht20 is set + * to one -- disable paprd for upper 5G + * If bit 29 of modal_header_5g.paprd_rate_mask_ht20 is set + * to one -- disable paprd for mid 5G + * If bit 28 of modal_header_5g.paprd_rate_mask_ht20 is set + * to one -- disable paprd for lower 5G + * u_int32_t am_mask = eep->modal_header_5g.paprd_rate_mask_ht20; + */ + if (chan->channel >= UPPER_5G_SUB_BANDSTART) { + if (eep->modal_header_5g.paprd_rate_mask_ht20 & (1 << 30)) { + enable = AH_FALSE; + } + } else if (chan->channel >= MID_5G_SUB_BANDSTART) { + if (eep->modal_header_5g.paprd_rate_mask_ht20 & (1 << 29)) { + enable = AH_FALSE; + } + } else { /* must be in the lower 5G subband */ + if (eep->modal_header_5g.paprd_rate_mask_ht20 & (1 << 28)) { + enable = AH_FALSE; + } + } + } + + if (ahp->ah_paprd_broken) { + ahp->ah_paprd_broken = AH_FALSE; + enable = AH_FALSE; + + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: PAPRD is in bad state. Don't enable PAPRD\n", + __func__); + } + } + if (enable) { + HAL_CHANNEL_INTERNAL *ichan; + if (is_2g) { + if (is_ht40) { + am_mask = ahp->ah_2g_paprd_rate_mask_ht40 & AH_PAPRD_AM_PM_MASK; + } else { + am_mask = ahp->ah_2g_paprd_rate_mask_ht20 & AH_PAPRD_AM_PM_MASK; + } + } else { + if (is_ht40) { + am_mask = ahp->ah_5g_paprd_rate_mask_ht40 & AH_PAPRD_AM_PM_MASK; + } else { + am_mask = ahp->ah_5g_paprd_rate_mask_ht20 & AH_PAPRD_AM_PM_MASK; + } + } + /* Earlier we promgrammed TGT Power with Scaled down value, since + * PAPRD CAL was not done. + * Now we finish PAPRD CAL, so bump up the TGT PWR to original + * EEPROM Power. CTLs calc and Maverickd in + * "ar9300_eeprom_set_transmit_power" + */ + ichan = ar9300_check_chan(ah, chan); + ichan->paprd_table_write_done = 1; + chan->paprd_table_write_done = 1; + /* + ath_hal_printf(ah, "%s[%d] eeprom_set_transmit_power PAPRD\n", + __func__, __LINE__); + */ + if (ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, ichan, + ath_hal_getctl(ah, chan), ath_hal_getantennaallowed(ah, chan), + ath_hal_get_twice_max_regpower(AH_PRIVATE(ah), ichan, chan), + AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_power_limit)) != HAL_OK) { + ichan->paprd_table_write_done = 0; + chan->paprd_table_write_done = 0; + /* Intentional print */ + ath_hal_printf(ah, + "%s[%d] eeprom_set_transmit_power failed ABORT PAPRD\n", + __func__, __LINE__); + + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0, + AR_PHY_PAPRD_CTRL0_B0_PAPRD_ENABLE_0, 0); + if (!AR_SREV_POSEIDON(ah) && !AR_SREV_HORNET(ah)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1, + AR_PHY_PAPRD_CTRL0_B1_PAPRD_ENABLE_1, 0); + if (!AR_SREV_JUPITER(ah) || (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2, + AR_PHY_PAPRD_CTRL0_B2_PAPRD_ENABLE_2, 0); + + } + } + return; + } + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s 2G %d HT40 %d am_mask 0x%08x\n", + __func__, is_2g, is_ht40, am_mask); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK, + am_mask); + if (AR_SREV_HORNET(ah)) { + OS_REG_RMW_FIELD_ALT(ah, + AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, 0); + } else { + OS_REG_RMW_FIELD_ALT(ah, + AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask); + } + + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, + AR_PHY_PAPRD_HT40_MASK); + /* chain0 */ + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN0_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0, + AR_PHY_PAPRD_CTRL0_B0_USE_SINGLE_TABLE_MASK, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2PM_ENABLE_0, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2AM_ENABLE_0, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_PA_GAIN_SCALE_FACT_0_MASK, 181); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_PAPRD_MAG_SCALE_FACT_0, 361); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0, + AR_PHY_PAPRD_CTRL0_B0_PAPRD_MAG_THRSH_0, 3); + } + /* chain1 */ + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN1_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1, + AR_PHY_PAPRD_CTRL0_B1_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2PM_ENABLE_1, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2AM_ENABLE_1, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_PA_GAIN_SCALE_FACT_1_MASK, 181); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_PAPRD_MAG_SCALE_FACT_1, 361); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1, + AR_PHY_PAPRD_CTRL0_B1_PAPRD_MAG_THRSH_1, 3); + } + /* chain2 */ + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2, + AR_PHY_PAPRD_CTRL0_B2_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2PM_ENABLE_2, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2AM_ENABLE_2, 1); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_PA_GAIN_SCALE_FACT_2_MASK, 181); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_PAPRD_MAG_SCALE_FACT_2, 361); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_SCALING_ENA, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2, + AR_PHY_PAPRD_CTRL0_B2_PAPRD_MAG_THRSH_2, 3); + } + + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN0_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0, + AR_PHY_PAPRD_CTRL0_B0_PAPRD_ENABLE_0, 1); + } + + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN1_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1, + AR_PHY_PAPRD_CTRL0_B1_PAPRD_ENABLE_1, 1); + } + + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2, + AR_PHY_PAPRD_CTRL0_B2_PAPRD_ENABLE_2, 1); + } + + } else { + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN0_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0, + AR_PHY_PAPRD_CTRL0_B0_PAPRD_ENABLE_0, 0); + } + + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN1_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1, + AR_PHY_PAPRD_CTRL0_B1_PAPRD_ENABLE_1, 0); + } + + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2, + AR_PHY_PAPRD_CTRL0_B2_PAPRD_ENABLE_2, 0); + } + } +} + +static void ar9300_gain_table_entries(struct ath_hal *ah) +{ + int i; + u_int32_t reg; + u_int32_t *gain_table_entries = AH9300(ah)->paprd_gain_table_entries; + u_int32_t *gain_vs_table_index = AH9300(ah)->paprd_gain_table_index; + + reg = AR_PHY_TXGAIN_TAB(1); + + for (i = 0; i < 32; i++) { + gain_table_entries[i] = OS_REG_READ(ah, reg); + gain_vs_table_index[i] = (gain_table_entries[i] >> 24) & 0xff; + /* + * ath_hal_printf( + * ah, "+++reg 0x%08x gain_table_entries[%d] = 0x%08x \n", + * reg, i, gain_table_entries[i]); + */ + reg = reg + 4; + } +} + +/* Get gain index for Target power */ +static unsigned int ar9300_get_desired_gain_for_chain(struct ath_hal *ah, + int chain_num, int target_power) +{ + int olpc_gain_delta = 0; + int alpha_therm = 0, alpha_volt = 0; + int therm_cal_value = 0, volt_cal_value = 0; + int latest_therm_value = 0, latest_volt_value = 0, olpc_gain_delta_tmp = 0; + int thermal_gain_corr = 0, voltage_gain_corr = 0, desired_scale = 0; + int desired_gain = 0; + int cl_gain_mod = 0; + + /* Clear the training done bit */ + if (AR_SREV_POSEIDON(ah)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE, 0); + } else { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE, 0); + } + /*field_read("BB_tpc_12.desired_scale_ht40_5", &desired_scale);*/ + desired_scale = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_12, + AR_PHY_TPC_12_DESIRED_SCALE_HT40_5); + /*field_read("BB_tpc_19.alpha_therm", &alpha_therm);*/ + alpha_therm = + OS_REG_READ_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM); + /*field_read("BB_tpc_19.alpha_volt", &alpha_volt);*/ + alpha_volt = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALT_ALPHA_VOLT); + + /*field_read("BB_tpc_18.therm_cal_value", &therm_cal_value);*/ + therm_cal_value = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_18, + AR_PHY_TPC_18_ALT_THERM_CAL_VALUE); + /*field_read("BB_tpc_18.volt_cal_value", &volt_cal_value);*/ + volt_cal_value = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_18, + AR_PHY_TPC_18_ALT_VOLT_CAL_VALUE); + + /*field_read("BB_therm_adc_4.latest_therm_value", &latest_therm_value);*/ + latest_therm_value = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_THERM_ADC_4, + AR_PHY_THERM_ADC_4_LATEST_THERM_VALUE); + /*field_read("BB_therm_adc_4.latest_volt_value", &latest_volt_value);*/ + latest_volt_value = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_THERM_ADC_4, + AR_PHY_THERM_ADC_4_LATEST_VOLT_VALUE); + + /* + * sprintf( + * field_name, "%s%d%s%d\0", "BB_tpc_11_b", + * chain_num, ".olpc_gain_delta_", chain_num); + */ + /*field_read(field_name, &olpc_gain_delta_tmp);*/ + + + if (chain_num == 0) { + olpc_gain_delta_tmp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_11_B0, + AR_PHY_TPC_11_B0_OLPC_GAIN_DELTA_0); + cl_gain_mod = OS_REG_READ_FIELD_ALT(ah, AR_PHY_CL_TAB_0, + AR_PHY_CL_TAB_0_CL_GAIN_MOD); + } else if (chain_num == 1) { + if (!AR_SREV_POSEIDON(ah)) { + olpc_gain_delta_tmp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_11_B1, + AR_PHY_TPC_11_B1_OLPC_GAIN_DELTA_1); + cl_gain_mod = OS_REG_READ_FIELD_ALT(ah, AR_PHY_CL_TAB_1, + AR_PHY_CL_TAB_1_CL_GAIN_MOD); + } + } else if (chain_num == 2) { + if (!AR_SREV_POSEIDON(ah)) { + olpc_gain_delta_tmp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_11_B2, + AR_PHY_TPC_11_B2_OLPC_GAIN_DELTA_2); + cl_gain_mod = OS_REG_READ_FIELD_ALT(ah, AR_PHY_CL_TAB_2, + AR_PHY_CL_TAB_2_CL_GAIN_MOD); + } + } else { + /* invalid chain_num */ + } + + if (olpc_gain_delta_tmp < 128) { + olpc_gain_delta = olpc_gain_delta_tmp; + } else { + olpc_gain_delta = olpc_gain_delta_tmp - 256; + } + + thermal_gain_corr = + (int) (alpha_therm * (latest_therm_value - therm_cal_value) + + 128) >> 8; + voltage_gain_corr = + (int) (alpha_volt * (latest_volt_value - volt_cal_value) + 64) >> 7; + desired_gain = + target_power - olpc_gain_delta - thermal_gain_corr - + voltage_gain_corr + desired_scale + cl_gain_mod; + /* + * printf( + * "olpc_gain_delta %d, desired_gain %d\n", + * olpc_gain_delta, desired_gain); + */ +#if 0 + ath_hal_printf(ah, + "+++ target_power %d olpc_gain_delta %d, cl_gain_mod %d," + "thermal_gain_corr %d voltage_gain_corr %d desired_scale %d" + "desired_gain %d\n", + target_power, olpc_gain_delta, cl_gain_mod, thermal_gain_corr, + voltage_gain_corr, + desired_scale, desired_gain); +#endif + return (unsigned int) desired_gain; +} + +static void ar9300_tx_force_gain(struct ath_hal *ah, unsigned int gain_index) +{ + int selected_gain_entry, txbb1dbgain, txbb6dbgain, txmxrgain; + int padrvgn_a, padrvgn_b, padrvgn_c, padrvgn_d; + u_int32_t *gain_table_entries = AH9300(ah)->paprd_gain_table_entries; + + /*u_int32_t *gain_vs_table_index = ah->paprd_gain_table_index;*/ + selected_gain_entry = gain_table_entries[gain_index]; + txbb1dbgain = selected_gain_entry & 0x7; + txbb6dbgain = (selected_gain_entry >> 3) & 0x3; + txmxrgain = (selected_gain_entry >> 5) & 0xf; + padrvgn_a = (selected_gain_entry >> 9) & 0xf; + padrvgn_b = (selected_gain_entry >> 13) & 0xf; + padrvgn_c = (selected_gain_entry >> 17) & 0xf; + padrvgn_d = (selected_gain_entry >> 21) & 0x3; + + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN, txbb1dbgain); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN, txbb6dbgain); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN, txmxrgain); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA, padrvgn_a); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB, padrvgn_b); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC, padrvgn_c); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND, padrvgn_d); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN, 0); + + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCE_DAC_GAIN, 0); +} + +#define HAL_DEBUG_PAPRD HAL_DEBUG_CALIBRATE /* driver: conditionally print */ + +#if defined(ART_PAPRD_DEBUG) || defined(AH_DEBUG) +static void ar9300_paprd_debug_print(struct ath_hal *ah) +{ + int temp; + int txbb1dbgain, txbb6dbgain, txmxrgain; + int padrvgn_a, padrvgn_b, padrvgn_c, padrvgn_d; + + if (AR_SREV_POSEIDON(ah)) { + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_lb_skip", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_lb_skip=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_lb_enable", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_lb_enable=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_tx_gain_force", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_tx_gain_force=0x%x\n", temp); + /* + * field_read( + * "BB_paprd_trainer_cntl1.cf_paprd_rx_bb_gain_force", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_rx_bb_gain_force=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_iqcorr_enable", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_iqcorr_enable=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_agc2_settling", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_agc2_settling=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_train_enable", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_train_enable=0x%x\n", temp); + /* + * field_read("BB_paprd_trainer_cntl2.cf_paprd_init_rx_bb_gain", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl2.cf_paprd_init_rx_bb_gain=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl3.cf_paprd_fine_corr_len", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_fine_corr_len=0x%x\n", temp); + /* + * field_read("BB_paprd_trainer_cntl3.cf_paprd_coarse_corr_len", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_coarse_corr_len=0x%x\n", temp); + /* + * field_read("BB_paprd_trainer_cntl3.cf_paprd_num_corr_stages", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_num_corr_stages=0x%x\n", temp); + /* + * field_read( + * "BB_paprd_trainer_cntl3.cf_paprd_min_loopback_del", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_min_loopback_del=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl3.cf_paprd_quick_drop", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_quick_drop=0x%x\n", temp); + /* + * field_read( + * "BB_paprd_trainer_cntl3.cf_paprd_adc_desired_size", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_adc_desired_size=0x%x\n", temp); + /* + * field_read("BB_paprd_trainer_cntl3.cf_paprd_bbtxmix_disable", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_bbtxmix_disable=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl4.cf_paprd_safety_delta", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl4.cf_paprd_safety_delta=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl4.cf_paprd_min_corr", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl4.cf_paprd_min_corr=0x%x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_agc2_pwr", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_agc2_pwr = 0x%02x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_rx_gain_idx", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_rx_gain_idx = 0x%02x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_train_active", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_train_active = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_corr_err", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_corr_err = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_train_incomplete", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_train_incomplete = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_train_done", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_train_done = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat2.paprd_fine_idx", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_fine_idx = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat2.paprd_coarse_idx", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_coarse_idx = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat2.paprd_fine_val", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_fine_val = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat3.paprd_train_samples_cnt", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT3_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_train_samples_cnt = 0x%08x\n", temp); + } else { + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_lb_skip", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_lb_skip=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_lb_enable", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_lb_enable=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_tx_gain_force", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_tx_gain_force=0x%x\n", temp); + /* + * field_read( + * "BB_paprd_trainer_cntl1.cf_paprd_rx_bb_gain_force", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_rx_bb_gain_force=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_iqcorr_enable", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_iqcorr_enable=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_agc2_settling", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_agc2_settling=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl1.cf_paprd_train_enable", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1, + AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl1.cf_paprd_train_enable=0x%x\n", temp); + /* + * field_read("BB_paprd_trainer_cntl2.cf_paprd_init_rx_bb_gain", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2, + AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl2.cf_paprd_init_rx_bb_gain=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl3.cf_paprd_fine_corr_len", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_fine_corr_len=0x%x\n", temp); + /* + * field_read("BB_paprd_trainer_cntl3.cf_paprd_coarse_corr_len", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_coarse_corr_len=0x%x\n", temp); + /* + * field_read("BB_paprd_trainer_cntl3.cf_paprd_num_corr_stages", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_num_corr_stages=0x%x\n", temp); + /* + * field_read( + * "BB_paprd_trainer_cntl3.cf_paprd_min_loopback_del", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_min_loopback_del=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl3.cf_paprd_quick_drop", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_quick_drop=0x%x\n", temp); + /* + * field_read( + * "BB_paprd_trainer_cntl3.cf_paprd_adc_desired_size", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_adc_desired_size=0x%x\n", temp); + /* + * field_read( + * "BB_paprd_trainer_cntl3.cf_paprd_bbtxmix_disable", &temp); + */ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl3.cf_paprd_bbtxmix_disable=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl4.cf_paprd_safety_delta", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4, + AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl4.cf_paprd_safety_delta=0x%x\n", temp); + /*field_read("BB_paprd_trainer_cntl4.cf_paprd_min_corr", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4, + AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "BB_paprd_trainer_cntl4.cf_paprd_min_corr=0x%x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_agc2_pwr", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_agc2_pwr = 0x%02x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_rx_gain_idx", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_rx_gain_idx = 0x%02x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_train_active", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_train_active = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_corr_err", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_corr_err = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_train_incomplete", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_train_incomplete = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat1.paprd_train_done", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_train_done = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat2.paprd_fine_idx", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2, + AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_fine_idx = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat2.paprd_coarse_idx", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2, + AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_coarse_idx = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat2.paprd_fine_val", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2, + AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_fine_val = 0x%08x\n", temp); + /*field_read("BB_paprd_trainer_stat3.paprd_train_samples_cnt", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT3, + AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " paprd_train_samples_cnt = 0x%08x\n", temp); + } + + /*field_read("BB_tpc_1.force_dac_gain", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCE_DAC_GAIN); + HALDEBUG(ah, HAL_DEBUG_PAPRD, " dac_gain_forced = 0x%08x\n", + temp); + /*field_read("BB_tpc_1.forced_dac_gain", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCED_DAC_GAIN); + HALDEBUG(ah, HAL_DEBUG_PAPRD, " forced_dac_gain = 0x%08x\n", + temp); + + /*field_read("BB_paprd_ctrl0_b0.paprd_enable_0", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0, + AR_PHY_PAPRD_CTRL0_B0_PAPRD_ENABLE_0); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " BB_paprd_ctrl0_b0.paprd_enable_0 = 0x%08x\n", temp); + if (!AR_SREV_POSEIDON(ah)) { + /*field_read("BB_paprd_ctrl0_b1.paprd_enable_1", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1, + AR_PHY_PAPRD_CTRL0_B1_PAPRD_ENABLE_1); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " BB_paprd_ctrl0_b1.paprd_enable_1 = 0x%08x\n", temp); + if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK) { + /*field_read("BB_paprd_ctrl0_b2.paprd_enable_2", &temp);*/ + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2, + AR_PHY_PAPRD_CTRL0_B2_PAPRD_ENABLE_2); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + " BB_paprd_ctrl0_b2.paprd_enable_2 = 0x%08x\n", temp); + } + } + + /*field_read("BB_tx_forced_gain.forced_txbb1dbgain", &txbb1dbgain);*/ + txbb1dbgain = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN); + /*field_read("BB_tx_forced_gain.forced_txbb6dbgain", &txbb6dbgain);*/ + txbb6dbgain = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN); + /*field_read("BB_tx_forced_gain.forced_txmxrgain", &txmxrgain);*/ + txmxrgain = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN); + /*field_read("BB_tx_forced_gain.forced_padrvgn_a", &padrvgn_a);*/ + padrvgn_a = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA); + /*field_read("BB_tx_forced_gain.forced_padrvgn_b", &padrvgn_b);*/ + padrvgn_b = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB); + /*field_read("BB_tx_forced_gain.forced_padrvgn_c", &padrvgn_c);*/ + padrvgn_c = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC); + /*field_read("BB_tx_forced_gain.forced_padrvgn_d", &padrvgn_d);*/ + padrvgn_d = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN, + AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND); + + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "txbb1dbgain=0x%x, txbb6dbgain=0x%x, txmxrgain=0x%x\n", + txbb1dbgain, txbb6dbgain, txmxrgain); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "padrvgn_a=0x%x, padrvgn_b=0x%x\n", padrvgn_a, padrvgn_b); + HALDEBUG(ah, HAL_DEBUG_PAPRD, + "padrvgn_c=0x%x, padrvgn_d=0x%x\n", padrvgn_c, padrvgn_d); +} +#else +#define ar9300_paprd_debug_print(ah) /* dummy macro */ +#endif /* defined(ART_PAPRD_DEBUG) || defined(AH_DEBUG) */ + +static int ar9300_create_pa_curve(struct ath_hal *ah, u_int32_t * pa_table, + u_int32_t * small_signal_gain, int * pa_in) +{ + int i; + int status; + /*char field_name[100];*/ + u_int32_t paprd_train_data_l[48], paprd_train_data_u[48]; + u_int32_t reg; + + ar9300_paprd_debug_print(ah); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_CHAN_INFO_MEMORY, + AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ, 0); + reg = AR_PHY_CHAN_INFO_TAB_0; + + for (i = 0; i < 48; i++) { + /* + * sprintf( + * field_name, "%s%d%s\0", "BB_chan_info_chan_tab_b0[", + * i, "].chaninfo_word"); + */ + /*field_read(field_name, &paprd_train_data_l[i]);*/ + paprd_train_data_l[i] = OS_REG_READ(ah, reg); + reg = reg + 4; + } + + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_CHAN_INFO_MEMORY, + AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ, 1); + reg = AR_PHY_CHAN_INFO_TAB_0; + + for (i = 0; i < 48; i++) { + /* + * sprintf( + * field_name, "%s%d%s\0", "BB_chan_info_chan_tab_b0[", + * i, "].chaninfo_word"); + */ + /*field_read(field_name, &paprd_train_data_u[i]);*/ + paprd_train_data_u[i] = OS_REG_READ(ah, reg); + reg = reg + 4; + } + + /* + * for(i=0; i<48; i++) + * ath_hal_printf( + * ah, "%08x%08x\n", paprd_train_data_u[i], paprd_train_data_l[i]); + */ + status = 0; + if (create_pa_curve( + paprd_train_data_l, paprd_train_data_u, + pa_table, small_signal_gain, pa_in) == + AH_FALSE) + { + status = -2; + } + /* Clear the training done bit */ + if (AR_SREV_POSEIDON(ah)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE, 0); + } else { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE, 0); + } + return status; +} + +static int find_expn(int num) +{ + int tmp, exp; + + exp = 0; + tmp = num >> 1; + + while (tmp != 0) { + tmp = tmp >> 1; + exp++; + } + + return exp; +} + +static int find_proper_scale(int expn, int n) +{ + int q_pw; + + q_pw = (expn > n) ? expn - 10 : 0; + return q_pw; +} + +static int find_max(int *array, int length) +{ + int i, loc_max; + + loc_max = 0; + + for (i = 0; i < length; i++) { + if (array[i] > loc_max) { + loc_max = array[i]; + } + } + + return loc_max; +} + +static int paprd_abs(int num) +{ + if (num < 0) { + return -num; + } + return num; +} + +#define NUM_BIN 23 + +HAL_BOOL create_pa_curve(u_int32_t * paprd_train_data_l, + u_int32_t * paprd_train_data_u, u_int32_t * pa_table, + u_int32_t * g_fxp_ext, int *pa_in) +{ + unsigned int accum_cnt[NUM_BIN + 1]; + unsigned int accum_tx[NUM_BIN + 1]; + unsigned int accum_rx[NUM_BIN + 1]; + unsigned int accum_ang[NUM_BIN + 1]; + unsigned int thresh_accum_cnt; + + int max_index; + int scale_factor; + + int x_est[NUM_BIN + 1]; + int y[NUM_BIN + 1]; + int theta[NUM_BIN + 1]; + int y_sqr[NUM_BIN + 1]; + int y_quad[NUM_BIN + 1]; + int theta_tilde[NUM_BIN + 1]; + int pa_angle[NUM_BIN + 1]; + + int b1_tmp[NUM_BIN + 1]; + int b2_tmp[NUM_BIN + 1]; + int b1_abs[NUM_BIN + 1]; + int b2_abs[NUM_BIN + 1]; + + int y_lin[NUM_BIN + 1]; + int y_est[NUM_BIN + 1]; + int x_est_fxp1_nonlin[NUM_BIN + 1]; + int x_tilde[NUM_BIN + 1]; + int x_tilde_abs[NUM_BIN + 1]; + + int g_fxp; + int y_intercept; + int order_x_by_y; + int m, half_lo, half_hi; + int sum_y_sqr; + int sum_y_quad; + int q_x, q_b1, q_b2; + int beta_raw, alpha_raw, scale_b; + int q_scale_b, q_beta, q_alpha; + int alpha, beta; + int order_1, order_2; + int order1_5x, order2_3x; + int order1_5x_rem, order2_3x_rem; + int y5, y3, tmp; + int bin, idx; + int theta_low_bin = 0; + + /* + * [15:00] u16, accum_cnt[15:00]: number of samples in the bin + * [42:16] u27, accum_tx[26:00]: sum(tx amplitude) of the bin + * [63:43] u21, accum_rx[20:00]: + * sum(rx amplitude distance to lower bin edge) of the bin + * [90:64] s27, accum_ang[26:00]: sum(angles) of the bin + */ + max_index = 0; + /* + * Disregard any bin that contains less than + * or equal to 16 counts of samples + */ + thresh_accum_cnt = 16; + scale_factor = 5; + + for (bin = 0; bin < NUM_BIN; bin++) { + accum_cnt[bin] = paprd_train_data_l[bin] & 0xffff; + /* lower 16 bit OR-ed upper 11 bits */ + accum_tx[bin] = + ((paprd_train_data_l[bin] >> 16) & 0xffff) | + ((paprd_train_data_u[bin] & 0x7ff) << 16); + accum_rx[bin] = + ((paprd_train_data_u[bin] >> 11) & 0x1f) | + ((paprd_train_data_l[bin + 23] & 0xffff) << 5); + accum_ang[bin] = + ((paprd_train_data_l[bin + 23] >> 16) & 0xffff) | + ((paprd_train_data_u[bin + 23] & 0x7ff) << 16); + /* + * printf( + * "%d\t%d\t%d\t%d\n", accum_cnt[bin], accum_tx[bin], + * accum_rx[bin], accum_ang[bin]); + */ + if (accum_cnt[bin] > thresh_accum_cnt) { + /* accum_cnt[i] will be non-zero at this point */ + x_est[bin + 1] = + ((((accum_tx[bin] << scale_factor) + + accum_cnt[bin]) / accum_cnt[bin]) + 32) >> scale_factor; + y[bin + 1] = + (((((accum_rx[bin] << scale_factor) + + accum_cnt[bin]) / accum_cnt[bin]) + 32) >> scale_factor) + + (1 << scale_factor) * max_index + 16; + if (accum_ang[bin] >= (1 << 26)) { + theta[bin + 1] = + ((accum_ang[bin] - (1 << 27)) * (1 << scale_factor) + + accum_cnt[bin]); + theta[bin + 1] = theta[bin + 1] / (int) accum_cnt[bin]; + /* + * theta[i+1] = + * ((accum_ang[i] - (1 << 27)) * + * (1 << scale_factor) + zz) / zz; + */ + } else { + theta[bin + 1] = + ((accum_ang[bin] * (1 << scale_factor)) + + accum_cnt[bin]) / accum_cnt[bin]; + } + max_index++; + } + /* + * printf( + * "i=%d, theta[i+1]=%d\t%d\t%d\t%d\t%d\n", + * i, theta[i+1], accum_cnt[i], + * accum_tx[i], accum_rx[i], accum_ang[i]); + */ + } + + /* + * Find average theta of first 5 bin and all of those to same value. + * Curve is linear at that range. + */ + for (bin = 1; bin < 6; bin++) { + theta_low_bin += theta[bin]; + } + theta_low_bin = theta_low_bin / 5; + for (bin = 1; bin < 6; bin++) { + theta[bin] = theta_low_bin; + } + + /* Set values at origin */ + theta[0] = theta_low_bin; + + for (bin = 0; bin <= max_index; bin++) { + theta[bin] = theta[bin] - theta_low_bin; + /*printf("bin=%d, theta[bin] = %d\n", bin, theta[bin]);*/ + } + + x_est[0] = 0; + y[0] = 0; + scale_factor = 8; + /* low signal gain */ + if (x_est[6] == x_est[3]) { + return AH_FALSE; + } + g_fxp = + (((y[6] - y[3]) * 1 << scale_factor) + (x_est[6] - x_est[3])) / + (x_est[6] - x_est[3]); + if (g_fxp == 0) { + /* + * ath_hal_printf( + * NULL, "%s[%d] Potential divide by zero error\n", + * __func__, __LINE__); + */ + return AH_FALSE; + } + + for (bin = 0; bin <= max_index; bin++) { + y_lin[bin] = + (g_fxp * (x_est[bin] - x_est[3]) + (1 << scale_factor)) / + (1 << scale_factor) + y[3]; + } + y_intercept = y_lin[0]; + + for (bin = 0; bin <= max_index; bin++) { + y_est[bin] = y[bin] - y_intercept; + y_lin[bin] = y_lin[bin] - y_intercept; + } + + for (bin = 0; bin <= 3; bin++) { + y_est[bin] = bin * 32; + /* g_fxp was checked for zero already */ + x_est[bin] = ((y_est[bin] * 1 << scale_factor) + g_fxp) / g_fxp; + } + + /* + * for (bin = 0; bin <= max_index; bin++) { + * printf("y_est[%d] = %d, x_est[%d]=%d\n", + * bin, y_est[bin], bin, x_est[bin]); + * } + */ + for (bin = 0; bin <= max_index; bin++) { + x_est_fxp1_nonlin[bin] = + x_est[bin] - ((1 << scale_factor) * y_est[bin] + g_fxp) / g_fxp; + /*printf("x_est_fxp1_nonlin[%d] = %d\n", bin, x_est_fxp1_nonlin[bin]);*/ + } + + /* Check for divide by 0 */ + if (y_est[max_index] == 0) { + return AH_FALSE; + } + order_x_by_y = + (x_est_fxp1_nonlin[max_index] + y_est[max_index]) / y_est[max_index]; + if (order_x_by_y == 0) { + m = 10; + } else if (order_x_by_y == 1) { + m = 9; + } else { + m = 8; + } + + half_lo = (max_index > 15) ? 7 : max_index >> 1; + half_hi = max_index - half_lo; + scale_factor = 8; + sum_y_sqr = 0; + sum_y_quad = 0; + + for (bin = 0; bin <= half_hi; bin++) { + if (y_est[bin + half_lo] == 0) { + /* + * ath_hal_printf( + * NULL, "%s Potential divide by zero error\n", __func__); + */ + return AH_FALSE; + } + + x_tilde[bin] = + (x_est_fxp1_nonlin[bin + half_lo] * (1 << m) + + y_est[bin + half_lo]) / y_est[bin + half_lo]; + x_tilde[bin] = (x_tilde[bin] * (1 << m) + y_est[bin + half_lo]) / + y_est[bin + half_lo]; + x_tilde[bin] = (x_tilde[bin] * (1 << m) + y_est[bin + half_lo]) / + y_est[bin + half_lo]; + + y_sqr[bin] = + (y_est[bin + half_lo] * y_est[bin + half_lo] + + (scale_factor * scale_factor)) / (scale_factor * scale_factor); + x_tilde_abs[bin] = paprd_abs(x_tilde[bin]); + y_quad[bin] = y_sqr[bin] * y_sqr[bin]; + sum_y_sqr = sum_y_sqr + y_sqr[bin]; + sum_y_quad = sum_y_quad + y_quad[bin]; + } + + /*printf("sum_y_sqr = %d, sum_y_quad=%d\n", sum_y_sqr, sum_y_quad);*/ + + for (bin = 0; bin <= half_hi; bin++) { + b1_tmp[bin] = y_sqr[bin] * (half_hi + 1) - sum_y_sqr; + b2_tmp[bin] = sum_y_quad - sum_y_sqr * y_sqr[bin]; + b1_abs[bin] = paprd_abs(b1_tmp[bin]); + b2_abs[bin] = paprd_abs(b2_tmp[bin]); + + /* + * printf( + * "bin=%d, b1_tmp[bin] = %d, b2_tmp[bin] = %d\n", + * bin, b1_tmp[bin], b2_tmp[bin]); + */ + } + + q_x = find_proper_scale(find_expn(find_max(x_tilde_abs, half_hi + 1)), 10); + q_b1 = find_proper_scale(find_expn(find_max(b1_abs, half_hi + 1)), 10); + q_b2 = find_proper_scale(find_expn(find_max(b2_abs, half_hi + 1)), 10); + + beta_raw = 0; + alpha_raw = 0; + + for (bin = 0; bin <= half_hi; bin++) { + x_tilde[bin] = x_tilde[bin] / (1 << q_x); + b1_tmp[bin] = b1_tmp[bin] / (1 << q_b1); + b2_tmp[bin] = b2_tmp[bin] / (1 << q_b2); + + /* + * printf( + * "bin=%d, b1_tmp[bin]=%d b2_tmp[bin]=%d x_tilde[bin] = %d\n", + * bin, b1_tmp[bin], b2_tmp[bin], x_tilde[bin]); + */ + beta_raw = beta_raw + b1_tmp[bin] * x_tilde[bin]; + alpha_raw = alpha_raw + b2_tmp[bin] * x_tilde[bin]; + } + + scale_b = + ((sum_y_quad / scale_factor) * (half_hi + 1) - + (sum_y_sqr / scale_factor) * sum_y_sqr) * scale_factor; + q_scale_b = find_proper_scale(find_expn(paprd_abs(scale_b)), 10); + scale_b = scale_b / (1 << q_scale_b); + /* Check for divide by 0 */ + if (scale_b == 0) { + return AH_FALSE; + } + q_beta = find_proper_scale(find_expn(paprd_abs(beta_raw)), 10); + q_alpha = find_proper_scale(find_expn(paprd_abs(alpha_raw)), 10); + + beta_raw = beta_raw / (1 << q_beta); + alpha_raw = alpha_raw / (1 << q_alpha); + alpha = (alpha_raw << 10) / scale_b; + beta = (beta_raw << 10) / scale_b; + order_1 = 3 * m - q_x - q_b1 - q_beta + 10 + q_scale_b; + order_2 = 3 * m - q_x - q_b2 - q_alpha + 10 + q_scale_b; + + order1_5x = order_1 / 5; + order2_3x = order_2 / 3; + + order1_5x_rem = order_1 - 5 * order1_5x; + order2_3x_rem = order_2 - 3 * order2_3x; + + for (idx = 0; idx < AR9300_PAPRD_TABLE_SZ; idx++) { + tmp = idx * 32; + y5 = ((beta * tmp) >> 6) >> order1_5x; + y5 = (y5 * tmp) >> order1_5x; + y5 = (y5 * tmp) >> order1_5x; + y5 = (y5 * tmp) >> order1_5x; + y5 = (y5 * tmp) >> order1_5x; + + y5 = y5 >> order1_5x_rem; + y3 = (alpha * tmp) >> order2_3x; + y3 = (y3 * tmp) >> order2_3x; + y3 = (y3 * tmp) >> order2_3x; + + y3 = y3 >> order2_3x_rem; + /* g_fxp was checked for zero already */ + pa_in[idx] = y5 + y3 + (256 * tmp) / g_fxp; + } + + for (idx = 1; idx < 23; idx++) { + tmp = pa_in[idx + 1] - pa_in[idx]; + if (tmp < 0) { + pa_in[idx + 1] = pa_in[idx] + (pa_in[idx] - pa_in[idx - 1]); + } + } + + for (idx = 0; idx < AR9300_PAPRD_TABLE_SZ; idx++) { + pa_in[idx] = (pa_in[idx] < 1400) ? pa_in[idx] : 1400; + /*printf("idx=%d, pa_in[idx]=%d\n", i, pa_in[idx]);*/ + } + + beta_raw = 0; + alpha_raw = 0; + + for (bin = 0; bin <= half_hi; bin++) { + /* + * printf( + * "bin=%d half_lo=%d m=%d theta[bin+half_lo]=%d " + * "y_est[bin+half_lo]=%d\n", + * bin, half_lo, m, theta[bin+half_lo], y_est[bin+half_lo]); + */ + /* y_est[] was already checked for zero */ + theta_tilde[bin] = + ((theta[bin + half_lo] << m) + y_est[bin + half_lo]) / + y_est[bin + half_lo]; + theta_tilde[bin] = ((theta_tilde[bin] << m) + y_est[bin + half_lo]) / + y_est[bin + half_lo]; + theta_tilde[bin] = ((theta_tilde[bin] << m) + y_est[bin + half_lo]) / + y_est[bin + half_lo]; + + /*printf("bin=%d theta_tilde[bin]=%d\n", bin, theta_tilde[bin]);*/ + beta_raw = beta_raw + b1_tmp[bin] * theta_tilde[bin]; + alpha_raw = alpha_raw + b2_tmp[bin] * theta_tilde[bin]; + + /* + printf("bin=%d, alpha_raw=%d, beta_raw=%d\n", bin, alpha_raw, beta_raw); + */ + } + + q_beta = find_proper_scale(find_expn(paprd_abs(beta_raw)), 10); + q_alpha = find_proper_scale(find_expn(paprd_abs(alpha_raw)), 10); + + beta_raw = beta_raw / (1 << q_beta); + alpha_raw = alpha_raw / (1 << q_alpha); + /* scale_b checked for zero previously */ + alpha = (alpha_raw << 10) / scale_b; + beta = (beta_raw << 10) / scale_b; + order_1 = 3 * m - q_x - q_b1 - q_beta + 10 + q_scale_b + 5; + order_2 = 3 * m - q_x - q_b2 - q_alpha + 10 + q_scale_b + 5; + + order1_5x = order_1 / 5; + order2_3x = order_2 / 3; + + order1_5x_rem = order_1 - 5 * order1_5x; + order2_3x_rem = order_2 - 3 * order2_3x; + + for (idx = 0; idx < AR9300_PAPRD_TABLE_SZ; idx++) { + tmp = idx * 32; + + if (beta > 0) { + y5 = (((beta * tmp - 64) >> 6) - + (1 << order1_5x)) / (1 << order1_5x); + } else { + y5 = ((((beta * tmp - 64) >> 6) + + (1 << order1_5x)) / (1 << order1_5x)); + } + + y5 = (y5 * tmp) / (1 << order1_5x); + y5 = (y5 * tmp) / (1 << order1_5x); + y5 = (y5 * tmp) / (1 << order1_5x); + y5 = (y5 * tmp) / (1 << order1_5x); + + y5 = y5 / (1 << order1_5x_rem); + + if (beta > 0) { + y3 = (alpha * tmp - (1 << order2_3x)) / (1 << order2_3x); + } else { + y3 = (alpha * tmp + (1 << order2_3x)) / (1 << order2_3x); + } + + y3 = (y3 * tmp) / (1 << order2_3x); + y3 = (y3 * tmp) / (1 << order2_3x); + + y3 = y3 / (1 << order2_3x_rem); + pa_angle[idx] = y5 + y3; + /*printf("idx=%d, y5 = %d, y3=%d\n", idx, y5, y3);*/ + pa_angle[idx] = + (pa_angle[idx] < -150) ? -150 : ((pa_angle[idx] > + 150) ? 150 : pa_angle[idx]); + } + + pa_angle[0] = 0; + pa_angle[1] = 0; + pa_angle[2] = 0; + pa_angle[3] = 0; + + pa_angle[4] = (pa_angle[5] + 2) >> 1; + + for (idx = 0; idx < AR9300_PAPRD_TABLE_SZ; idx++) { + pa_table[idx] = ((pa_in[idx] & 0x7ff) << 11) + (pa_angle[idx] & 0x7ff); + /* + * HALDEBUG( + * NULL, HAL_DEBUG_UNMASKABLE,"%d\t%d\t0x%x\n", + * pa_in[idx], pa_angle[idx], pa_table[idx]); + */ + } + + /*HALDEBUG(NULL, HAL_DEBUG_UNMASKABLE, "g_fxp = %d\n", g_fxp);*/ + *g_fxp_ext = g_fxp; + return AH_TRUE; +} + +// Due to a hardware bug, when transmitting with just one chain the papd +// data for chain 0 is always used. So when using chain 2 or 4, the +// corresponding data must be copied into the chain 0 area. +void ar9300_swizzle_paprd_entries(struct ath_hal *ah, unsigned int txchain) +{ + int i; + u_int32_t *paprd_table_val = NULL; + u_int32_t small_signal_gain = 0; + u_int32_t reg = 0; + + reg = AR_PHY_PAPRD_MEM_TAB_B0; + switch (txchain) { + case 0x1: + case 0x3: + case 0x7: + paprd_table_val = &AH9300(ah)->pa_table[0][0]; + small_signal_gain = AH9300(ah)->small_signal_gain[0]; + break; + case 0x2: + paprd_table_val = &AH9300(ah)->pa_table[1][0]; + small_signal_gain = AH9300(ah)->small_signal_gain[1]; + break; + case 0x4: + paprd_table_val = &AH9300(ah)->pa_table[2][0]; + small_signal_gain = AH9300(ah)->small_signal_gain[2]; + break; + default: + // Error out. + ath_hal_printf(ah, "YAK! Bad chain mask %x\n", txchain); + return; + } + for (i = 0; i < AR9300_PAPRD_TABLE_SZ; i++) { + OS_REG_WRITE(ah, reg, paprd_table_val[i]); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", __func__, + __LINE__, reg, paprd_table_val[i]); + + reg = reg + 4; + } + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PA_GAIN123_B0,AR_PHY_PA_GAIN123_B0_PA_GAIN1_0, small_signal_gain); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x small_signal_gain 0x%08x\n", __func__, __LINE__, + (unsigned) AR_PHY_PA_GAIN123_B0, OS_REG_READ(ah, AR_PHY_PA_GAIN123_B0)); + + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, AR_PHY_PAPRD_CTRL1_B0_PAPRD_POWER_AT_AM2AM_CAL_0, + AH9300(ah)->paprd_training_power); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", __func__, __LINE__, + (unsigned) AR_PHY_PAPRD_CTRL1_B0, OS_REG_READ(ah, AR_PHY_PAPRD_CTRL1_B0)); + +} + +void ar9300_populate_paprd_single_table(struct ath_hal *ah, HAL_CHANNEL * chan, + int chain_num) +{ + int i, j, bad_read = 0; + u_int32_t *paprd_table_val = &AH9300(ah)->pa_table[chain_num][0]; + u_int32_t small_signal_gain = AH9300(ah)->small_signal_gain[chain_num]; + u_int32_t reg = 0; + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s[%d]: channel %d paprd_done %d write %d\n", __func__, __LINE__, + chan->channel, chan->paprd_done, chan->paprd_table_write_done); + + if (chain_num == 0) { + reg = AR_PHY_PAPRD_MEM_TAB_B0; + } else if (chain_num == 1) { + reg = AR_PHY_PAPRD_MEM_TAB_B1; + } else if (chain_num == 2) { + reg = AR_PHY_PAPRD_MEM_TAB_B2; + } + + for (i = 0; i < AR9300_PAPRD_TABLE_SZ; i++) { + if (AR_SREV_POSEIDON(ah)) { + HALASSERT(chain_num == 0x1); + if ((reg == AR_PHY_PAPRD_MEM_TAB_B1) || + (reg == AR_PHY_PAPRD_MEM_TAB_B2)) { + continue; + } + } + /* + * sprintf( + * field_name, "%s%d[%d]%s\0", "BB_paprd_mem_tab_b", + * chain_num, i, ".paprd_mem"); + */ + OS_REG_WRITE(ah, reg, paprd_table_val[i]); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", __func__, + __LINE__, reg, paprd_table_val[i]); + /* + * printf( + * "%s[%d] reg %08x = 0x%08x\n", + * __func__, __LINE__, reg, paprd_table_val[i]); + */ + if (OS_REG_READ(ah, reg) == 0xdeadbeef) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: Reg0x%x = 0xdeadbeef\n", __func__, reg); + bad_read++; + for (j = AR_PHY_PAPRD_MEM_TAB_B0; j < (AR_PHY_PAPRD_MEM_TAB_B0 + 0x10); j+=4) + { + if (OS_REG_READ(ah, j) == 0xdeadbeef) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: Reg0x%x = 0xdeadbeef\n", __func__, j); + bad_read++; + } + } + for (j = AR_PHY_PAPRD_MEM_TAB_B1; j < (AR_PHY_PAPRD_MEM_TAB_B1 + 0x10); j+=4) + { + if (OS_REG_READ(ah, j) == 0xdeadbeef) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: Reg0x%x = 0xdeadbeef\n", __func__, j); + bad_read++; + } + } + } + + reg = reg + 4; + } + + if (bad_read > 4) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: Get %d 0xdeadbeef. Mark PAPRD as broken.\n", + __func__, bad_read); + AH9300(ah)->ah_paprd_broken = AH_TRUE; + } + + if (chain_num == 0) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PA_GAIN123_B0, + AR_PHY_PA_GAIN123_B0_PA_GAIN1_0, small_signal_gain); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s[%d] reg %08x small_signal_gain 0x%08x\n", __func__, __LINE__, + (unsigned) AR_PHY_PA_GAIN123_B0, + OS_REG_READ(ah, AR_PHY_PA_GAIN123_B0)); + } else if (chain_num == 1) { + if (!AR_SREV_POSEIDON(ah) && !AR_SREV_HORNET(ah) && !AR_SREV_APHRODITE(ah)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PA_GAIN123_B1, + AR_PHY_PA_GAIN123_B1_PA_GAIN1_1, small_signal_gain); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s[%d] reg %08x small_signal_gain 0x%08x\n", + __func__, __LINE__, + (unsigned) AR_PHY_PA_GAIN123_B1, + OS_REG_READ(ah, AR_PHY_PA_GAIN123_B1)); + } + } else if (chain_num == 2) { + if (!AR_SREV_POSEIDON(ah) && !AR_SREV_HORNET(ah) && !AR_SREV_APHRODITE(ah)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PA_GAIN123_B2, + AR_PHY_PA_GAIN123_B2_PA_GAIN1_2, small_signal_gain); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s[%d] reg %08x small_signal_gain 0x%08x\n", + __func__, __LINE__, + (unsigned) AR_PHY_PA_GAIN123_B2, + OS_REG_READ(ah, AR_PHY_PA_GAIN123_B2)); + } + } else { + /* invalid channel number */ + } + + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, + AR_PHY_PAPRD_CTRL1_B0_PAPRD_POWER_AT_AM2AM_CAL_0, + AH9300(ah)->paprd_training_power); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", __func__, + __LINE__, (unsigned) AR_PHY_PAPRD_CTRL1_B0, + OS_REG_READ(ah, AR_PHY_PAPRD_CTRL1_B0)); + if (!AR_SREV_POSEIDON(ah) && !AR_SREV_HORNET(ah) && !AR_SREV_APHRODITE(ah)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1, + AR_PHY_PAPRD_CTRL1_B1_PAPRD_POWER_AT_AM2AM_CAL_1, + AH9300(ah)->paprd_training_power); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", __func__, + __LINE__, (unsigned) AR_PHY_PAPRD_CTRL1_B1, + OS_REG_READ(ah, AR_PHY_PAPRD_CTRL1_B1)); + if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2, + AR_PHY_PAPRD_CTRL1_B2_PAPRD_POWER_AT_AM2AM_CAL_2, + AH9300(ah)->paprd_training_power); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s[%d] reg %08x = 0x%08x\n", __func__, + __LINE__, (unsigned) AR_PHY_PAPRD_CTRL1_B2, + OS_REG_READ(ah, AR_PHY_PAPRD_CTRL1_B2)); + } + } + /*ar9300_enable_paprd(ah, AH_TRUE);*/ +} + +HAL_STATUS ar9300_paprd_setup_gain_table(struct ath_hal *ah, int chain_num) +{ + unsigned int i, desired_gain, gain_index; + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "Run papredistortion single table algorithm:: Training power = %d\n", + AH9300(ah)->paprd_training_power / 2); + + if (AH9300(ah)->ah_tx_chainmask & (1 << chain_num)) { + /* this is an active chain */ + desired_gain = ar9300_get_desired_gain_for_chain( + ah, chain_num, AH9300(ah)->paprd_training_power); + /* find out gain index */ + gain_index = 0; + + for (i = 0; i < 32; i++) { + if (AH9300(ah)->paprd_gain_table_index[i] < desired_gain) { + gain_index = gain_index + 1; + } else { + break; + } + } + + /*printf("gain_index = %d\n", gain_index);*/ + /*ath_hal_printf(ah, "++++ gain_index = %d\n", gain_index);*/ + ar9300_tx_force_gain(ah, gain_index); + if (AR_SREV_POSEIDON(ah)) { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE, 0); + } else { + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE, 0); + } + } + + return HAL_OK; +} + +static HAL_BOOL ar9300_paprd_retrain_pain(struct ath_hal * ah, int * pa_in) +{ + int count = 0, i; + int capdiv_offset = 0, quick_drop_offset; + int capdiv2g, quick_drop; + + capdiv2g = (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) >> 1) & 0xF; + if (!AR_SREV_POSEIDON(ah)) { + quick_drop = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP); + } else { + quick_drop = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP); + } + + if ( quick_drop != 0 ) { + quick_drop -= 0x40; + } + for (i = 0; i < (NUM_BIN + 1); i++) { + if (pa_in[i] == 1400) { + count++; + } + } + + if (AR_SREV_POSEIDON(ah)) { + if ((pa_in[23] < 800) || (pa_in[23] == 1400)) { + if (pa_in[23] < 800) { + capdiv_offset = (int)((1000 - pa_in[23] + 75) / 150); + capdiv2g = capdiv2g + capdiv_offset; + if (capdiv2g > 7) { + capdiv2g = 7; + if (pa_in[23] < 600) { + quick_drop = quick_drop + 1; + if (quick_drop > 0) { + quick_drop = 0; + } + } + } + + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_TXRF3, + AR_PHY_65NM_CH0_TXRF3_CAPDIV2G, + capdiv2g); + + OS_REG_RMW_FIELD_ALT(ah, + AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, + quick_drop); + + return AH_TRUE; + } /* end of if (pa_in[23] < 800) */ + else if (pa_in[23] == 1400) { + quick_drop_offset = (int)(count / 3); + if (quick_drop_offset > 2) { + quick_drop_offset = 2; + } + quick_drop = quick_drop + quick_drop_offset; + capdiv2g = capdiv2g + (int)(quick_drop_offset / 2); + if (capdiv2g > 7) { + capdiv2g = 7; + } + if (quick_drop > 0) { + quick_drop = 0; + capdiv2g = capdiv2g - (int)(quick_drop_offset / 1); + if (capdiv2g < 0) { + capdiv2g = 0; + } + } + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_TXRF3, + AR_PHY_65NM_CH0_TXRF3_CAPDIV2G, + capdiv2g); + + OS_REG_RMW_FIELD_ALT(ah, + AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, + quick_drop); + + return AH_TRUE; + /* sleep(1); */ + } /* end of if (pa_in[23] == 1400)*/ + } /* end of if ((pa_in[23] < 800) || (pa_in[23] == 1400)) */ + }else if (AR_SREV_HORNET(ah)) { + if ((pa_in[23] < 1000) || (pa_in[23] == 1400)) { + if (pa_in[23] < 1000) { + capdiv_offset = ((1000 - pa_in[23]) / 100); + capdiv2g = capdiv2g + capdiv_offset; + if (capdiv_offset > 3) { + quick_drop_offset = 1; + quick_drop = quick_drop - quick_drop_offset; + capdiv2g = capdiv2g + 1; + if (capdiv2g > 6) { + capdiv2g = 6; + } + if (quick_drop < -4) { + quick_drop = -4; + } + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_TXRF3, + AR_PHY_65NM_CH0_TXRF3_CAPDIV2G, + capdiv2g); + OS_REG_RMW_FIELD_ALT(ah, + AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, + quick_drop); + return AH_TRUE; + } else { + capdiv2g = capdiv2g + capdiv_offset; + if (capdiv2g > 6) { + capdiv2g = 6; + } + if (quick_drop < -4) { + quick_drop = -4; + } + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_TXRF3, + AR_PHY_65NM_CH0_TXRF3_CAPDIV2G, + capdiv2g); + OS_REG_RMW_FIELD_ALT(ah, + AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, + quick_drop); + return AH_TRUE; + } + } /* end of if (PA_in[23] < 1000) */ + else if (pa_in[23] == 1400) { + if (count > 3) { + quick_drop_offset = 1; + quick_drop = quick_drop + quick_drop_offset; + capdiv2g = capdiv2g - (count / 4); + if (capdiv2g < 0) { + capdiv2g = 0; + } + if (quick_drop > -2) { + quick_drop = -2; + } + OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, + AR_PHY_65NM_CH0_TXRF3_CAPDIV2G, + capdiv2g); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, + quick_drop); + return AH_TRUE; + } else { + capdiv2g = capdiv2g - 1; + if (capdiv2g < 0) { + capdiv2g = 0; + } + OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, + AR_PHY_65NM_CH0_TXRF3_CAPDIV2G, + capdiv2g); + OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3, + AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, + quick_drop); + return AH_TRUE; + } + } /* end of if (PA_in[23] == 1400)*/ + } /* end of if ((PA_in[23] < 1000) || (PA_in[23] == 1400)) */ + } + + return AH_FALSE; +} + +HAL_STATUS ar9300_paprd_create_curve(struct ath_hal * ah, HAL_CHANNEL * chan, + int chain_num) +{ + int status = 0; + u_int32_t *pa_table, small_signal_gain; + int pa_in[NUM_BIN + 1]; + + if (AH9300(ah)->ah_tx_chainmask & (1 << chain_num)) { + pa_table = &AH9300(ah)->pa_table[chain_num][0]; + /* Compute PA table and gain index */ + status = ar9300_create_pa_curve(ah, &pa_table[0], &small_signal_gain, + &pa_in[0]); + + if (AR_SREV_WASP(ah)) { + OS_DELAY(1000); + } + + if (status != 0) { + ath_hal_printf(ah, "ERROR:: paprd failed with error code = %d\n", + status); + return -1; + } + AH9300(ah)->small_signal_gain[chain_num] = small_signal_gain; + + if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah)) { + if (ar9300_paprd_retrain_pain(ah, pa_in)) { + /* need re-train PAPRD */ + return HAL_EINPROGRESS; + } + } + } + return HAL_OK; +} + +int ar9300_paprd_init_table(struct ath_hal *ah, HAL_CHANNEL * chan) +{ + if ((AR_SREV_WASP(ah) && IS_CHAN_5GHZ(chan)) || + ar9300_paprd_setup_single_table(ah, chan)) { + goto FAIL; + } + OS_MEMZERO(AH9300(ah)->paprd_gain_table_entries, + sizeof(AH9300(ah)->paprd_gain_table_entries)); + OS_MEMZERO(AH9300(ah)->paprd_gain_table_index, + sizeof(AH9300(ah)->paprd_gain_table_index)); + + ar9300_gain_table_entries(ah); + return 0; +FAIL: + return -1; +} + +int ar9300_paprd_is_done(struct ath_hal *ah) +{ + int temp, agc2_pwr; + + /*field_read("BB_paprd_trainer_stat1.paprd_train_done", &temp);*/ + if (!AR_SREV_POSEIDON(ah)) { + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE); + + if (temp == 0x1) { + agc2_pwr = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR); + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s AGC2_PWR=0x%2x Training done=0x%2x\n", + __func__, agc2_pwr, temp); + + /* Retrain if agc2_pwr is not in ideal range */ + if (agc2_pwr <= AH_PAPRD_IDEAL_AGC2_PWR_RANGE) { + temp = 0; + } + } + } else { + temp = + OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON, + AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE); + } + if (!temp) { + /*ath_hal_printf(ah, "%s[%d] PAPRD TEMp Error\n", __func__, __LINE__);*/ + } + + return temp; +} + +/* + * ar9300_paprd_dec_tx_pwr + * + * This function do decrease tx power if Paprd is off or train failed. + */ +void +ar9300_paprd_dec_tx_pwr(struct ath_hal *ah) +{ + u_int32_t pwr_temp, pwr_reg; + int i, loop_cnt; + struct ar9300_paprd_pwr_adjust *p_item; + struct ath_hal_9300 *ahp = AH9300(ah); + + if (AR_SREV_POSEIDON(ah)) { + loop_cnt = + (sizeof(ar9300_paprd_pwr_adj_array) / + sizeof(struct ar9300_paprd_pwr_adjust)); + for (i = 0; i < loop_cnt; i++ ) + { + p_item = &ar9300_paprd_pwr_adj_array[i]; + pwr_reg = OS_REG_READ(ah, p_item->reg_addr); + pwr_temp = ahp->ah_default_tx_power[p_item->target_rate]; + pwr_temp -= (p_item->sub_db * 2); + pwr_temp = pwr_temp << p_item->reg_mask_offset; + pwr_temp |= (pwr_reg&~(p_item->reg_mask <reg_mask_offset)); + + if (pwr_temp != pwr_reg) + { + OS_REG_WRITE(ah, p_item->reg_addr, pwr_temp); + } + } + } + return; +} + +int ar9300_paprd_thermal_send(struct ath_hal *ah) +{ + if (AR_SREV_HORNET(ah)) { + return OS_REG_READ(ah, AR_TFCNT); + } else { + return 1; + } +} + +#if 0 +void ar9300_paprd_test_prints(struct ath_hal *ah) +{ + u_int32_t i, reg = 0; + + HALDEBUG(NULL, HAL_DEBUG_CALIBRATE, "=====ar9300_paprd_test_prints=======\n"); + /*printf("=====ar9300_paprd_test_prints=======\n");*/ + HALDEBUG(NULL, HAL_DEBUG_CALIBRATE, "BB_paprd_ctrl0_b0 = 0x%08x\n", + OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B0)); + /* + * printf( + * "BB_paprd_ctrl0_b0 = 0x%08x\n", + * OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B0)); + */ + if (!AR_SREV_POSEIDON(ah) && !AR_SREV_HORNET(ah)) { + HALDEBUG(NULL, HAL_DEBUG_CALIBRATE, "BB_paprd_ctrl0_b1 = 0x%08x\n", + OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B1)); + /* + * printf( + * "BB_paprd_ctrl0_b1 = 0x%08x\n", + * OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B1)); + */ + HALDEBUG(NULL, HAL_DEBUG_CALIBRATE, "BB_paprd_ctrl0_b2 = 0x%08x\n", + OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B2)); + /* + * printf( + * "BB_paprd_ctrl0_b2 = 0x%08x\n", + * OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B2)); + */ + } + + reg = AR_PHY_PAPRD_MEM_TAB_B0; + HALDEBUG(NULL, HAL_DEBUG_CALIBRATE, + "%s[%d] reg %08lx small_signal_gain ch0 0x%08x\n", __func__, __LINE__, + AR_PHY_PA_GAIN123_B0, OS_REG_READ(ah, AR_PHY_PA_GAIN123_B0)); + /* + * printf( + * "%s[%d] reg %08lx small_signal_gain ch0 0x%08x\n", + * __func__, __LINE__, AR_PHY_PA_GAIN123_B0, + * OS_REG_READ(ah, AR_PHY_PA_GAIN123_B0)); + */ + + for (i = 0; i < 24; i++) { + HALDEBUG(NULL, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", + __func__, __LINE__, reg, OS_REG_READ(ah, reg)); + /* + * printf( + * "%s[%d] reg %08x = 0x%08x\n", __func__, __LINE__, + * reg, OS_REG_READ(ah, reg)); + */ + reg = reg + 4; + } + + ar9300_paprd_debug_print(ah); + HALDEBUG(NULL, HAL_DEBUG_CALIBRATE, + "=====ar9300_paprd_test_prints end=======\n"); + /*printf("=====ar9300_paprd_test_prints end=======\n");*/ + + if (!AR_SREV_POSEIDON(ah)) { + reg = AR_PHY_PAPRD_MEM_TAB_B1; + printf("%s[%d] reg %08lx small_signal_gain ch1 0x%08x\n", + __func__, __LINE__, + AR_PHY_PA_GAIN123_B1, OS_REG_READ(ah, AR_PHY_PA_GAIN123_B1)); + for (i = 0; i < 24; i++) { + OS_REG_WRITE(ah, reg, paprd_table_val[i]); + HALDEBUG(NULL, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", + __func__, __LINE__, reg, OS_REG_READ(ah, reg)); + printf("%s[%d] reg %08x = 0x%08x\n", __func__, __LINE__, reg, + OS_REG_READ(ah, reg)); + reg = reg + 4; + } + + reg = AR_PHY_PAPRD_MEM_TAB_B2; + printf("%s[%d] reg %08lx small_signal_gain ch2 0x%08x\n", + __func__, __LINE__, + AR_PHY_PA_GAIN123_B2, OS_REG_READ(ah, AR_PHY_PA_GAIN123_B2)); + } +} +#endif + +#else +int +ar9300_paprd_init_table(struct ath_hal *ah, HAL_CHANNEL * chan) +{ + return 0; +} + +HAL_STATUS +ar9300_paprd_setup_gain_table(struct ath_hal * ah, int chain_num) +{ + return HAL_OK; +} + +HAL_STATUS +ar9300_paprd_create_curve(struct ath_hal * ah, HAL_CHANNEL * chan, + int chain_num) +{ + return HAL_OK; +} + +int +ar9300_paprd_is_done(struct ath_hal *ah) +{ + return 0; +} + +void +ar9300_enable_paprd(struct ath_hal *ah, HAL_BOOL enable_flag, HAL_CHANNEL * chan) +{ + return; +} + +void +ar9300_populate_paprd_single_table(struct ath_hal *ah, HAL_CHANNEL * chan, + int chain_num) +{ + return; +} + +void +ar9300_paprd_dec_tx_pwr(struct ath_hal *ah) +{ + return; +} + +int ar9300_paprd_thermal_send(struct ath_hal *ah) +{ + return 1; +} +#endif /* ATH_SUPPORT_PAPRD */ diff --git a/hal/ar9300/ar9300_phy.c b/hal/ar9300/ar9300_phy.c new file mode 100644 index 000000000000..5b88806c9a52 --- /dev/null +++ b/hal/ar9300/ar9300_phy.c @@ -0,0 +1,1215 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" + +/* shorthands to compact tables for readability */ +#define OFDM IEEE80211_T_OFDM +#define CCK IEEE80211_T_CCK +#define TURBO IEEE80211_T_TURBO +#define XR ATHEROS_T_XR +#define HT IEEE80211_T_HT + +#define AR9300_NUM_OFDM_RATES 8 +#define AR9300_NUM_HT_SS_RATES 8 +#define AR9300_NUM_HT_DS_RATES 8 +#define AR9300_NUM_HT_TS_RATES 8 + +/* Array Gain defined for TxBF */ +#define AR9300_TXBF_2TX_ARRAY_GAIN 6 /* 2TX/SS 3 */ +#define AR9300_TXBF_3TX_ARRAY_GAIN 10 /* 3TX/SS or 3TX/DS 4.8 */ +#define AR9300_STBC_3TX_ARRAY_GAIN 10 /* 3TX/SS or 3TX/DS 4.8 */ + +/* MCS RATE CODES - first and last */ +#define AR9300_MCS0_RATE_CODE 0x80 +#define AR9300_MCS23_RATE_CODE 0x97 + +static inline void ar9300_init_rate_txpower_cck(struct ath_hal *ah, + const HAL_RATE_TABLE *rt, u_int8_t rates_array[], u_int8_t chainmask); +static inline void ar9300_init_rate_txpower_ofdm(struct ath_hal* ah, + const HAL_RATE_TABLE *rt, u_int8_t rates_array[], int rt_offset, + u_int8_t chainmask); +static inline void ar9300_init_rate_txpower_ht(struct ath_hal *ah, + const HAL_RATE_TABLE *rt, HAL_BOOL is40, u_int8_t rates_array[], + int rt_ss_offset, int rt_ds_offset, + int rt_ts_offset, u_int8_t chainmask); +static inline void ar9300_init_rate_txpower_stbc(struct ath_hal *ah, + const HAL_RATE_TABLE *rt, HAL_BOOL is40, + int rt_ss_offset, int rt_ds_offset, + int rt_ts_offset, u_int8_t chainmask); +static inline void ar9300_adjust_rate_txpower_cdd(struct ath_hal *ah, + const HAL_RATE_TABLE *rt, HAL_BOOL is40, + int rt_ss_offset, int rt_ds_offset, + int rt_ts_offset, u_int8_t chainmask); + +#define AR9300_11A_RT_OFDM_OFFSET 0 +HAL_RATE_TABLE ar9300_11a_table = { + 8, /* number of rates */ + { 0 }, + { +/* short ctrl */ +/* valid rate_code Preamble dot11Rate Rate */ +/* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0 }, +/* 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0 }, +/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2 }, +/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2 }, +/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4 }, +/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 4 }, +/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 4 }, +/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 4 }, + }, +}; + +HAL_RATE_TABLE ar9300_11a_half_table = { + 8, /* number of rates */ + { 0 }, + { +/* short ctrl */ +/* valid rate_code Preamble dot11Rate Rate */ +/* 6 Mb */ { AH_TRUE, OFDM, 3000, 0x0b, 0x00, (0x80 | 6), 0 }, +/* 9 Mb */ { AH_TRUE, OFDM, 4500, 0x0f, 0x00, 9, 0 }, +/* 12 Mb */ { AH_TRUE, OFDM, 6000, 0x0a, 0x00, (0x80 | 12), 2 }, +/* 18 Mb */ { AH_TRUE, OFDM, 9000, 0x0e, 0x00, 18, 2 }, +/* 24 Mb */ { AH_TRUE, OFDM, 12000, 0x09, 0x00, (0x80 | 24), 4 }, +/* 36 Mb */ { AH_TRUE, OFDM, 18000, 0x0d, 0x00, 36, 4 }, +/* 48 Mb */ { AH_TRUE, OFDM, 24000, 0x08, 0x00, 48, 4 }, +/* 54 Mb */ { AH_TRUE, OFDM, 27000, 0x0c, 0x00, 54, 4 }, + }, +}; + +HAL_RATE_TABLE ar9300_11a_quarter_table = { + 8, /* number of rates */ + { 0 }, + { +/* short ctrl */ +/* valid rate_code Preamble dot11Rate Rate */ +/* 6 Mb */ { AH_TRUE, OFDM, 1500, 0x0b, 0x00, (0x80 | 3), 0 }, +/* 9 Mb */ { AH_TRUE, OFDM, 2250, 0x0f, 0x00, 4 , 0 }, +/* 12 Mb */ { AH_TRUE, OFDM, 3000, 0x0a, 0x00, (0x80 | 6), 2 }, +/* 18 Mb */ { AH_TRUE, OFDM, 4500, 0x0e, 0x00, 9, 2 }, +/* 24 Mb */ { AH_TRUE, OFDM, 6000, 0x09, 0x00, (0x80 | 12), 4 }, +/* 36 Mb */ { AH_TRUE, OFDM, 9000, 0x0d, 0x00, 18, 4 }, +/* 48 Mb */ { AH_TRUE, OFDM, 12000, 0x08, 0x00, 24, 4 }, +/* 54 Mb */ { AH_TRUE, OFDM, 13500, 0x0c, 0x00, 27, 4 }, + }, +}; + +HAL_RATE_TABLE ar9300_turbo_table = { + 8, /* number of rates */ + { 0 }, + { +/* short ctrl */ +/* valid rate_code Preamble dot11Rate Rate */ +/* 6 Mb */ { AH_TRUE, TURBO, 6000, 0x0b, 0x00, (0x80 | 12), 0 }, +/* 9 Mb */ { AH_TRUE, TURBO, 9000, 0x0f, 0x00, 18, 0 }, +/* 12 Mb */ { AH_TRUE, TURBO, 12000, 0x0a, 0x00, (0x80 | 24), 2 }, +/* 18 Mb */ { AH_TRUE, TURBO, 18000, 0x0e, 0x00, 36, 2 }, +/* 24 Mb */ { AH_TRUE, TURBO, 24000, 0x09, 0x00, (0x80 | 48), 4 }, +/* 36 Mb */ { AH_TRUE, TURBO, 36000, 0x0d, 0x00, 72, 4 }, +/* 48 Mb */ { AH_TRUE, TURBO, 48000, 0x08, 0x00, 96, 4 }, +/* 54 Mb */ { AH_TRUE, TURBO, 54000, 0x0c, 0x00, 108, 4 }, + }, +}; + +HAL_RATE_TABLE ar9300_11b_table = { + 4, /* number of rates */ + { 0 }, + { +/* short ctrl */ +/* valid rate_code Preamble dot11Rate Rate */ +/* 1 Mb */ { AH_TRUE, CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0 }, +/* 2 Mb */ { AH_TRUE, CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1 }, +/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80 | 11), 1 }, +/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80 | 22), 1 }, + }, +}; + + +/* Venice TODO: round_up_rate() is broken when the rate table does not represent + * rates in increasing order e.g. 5.5, 11, 6, 9. + * An average rate of 6 Mbps will currently map to 11 Mbps. + */ +#define AR9300_11G_RT_OFDM_OFFSET 4 +HAL_RATE_TABLE ar9300_11g_table = { + 12, /* number of rates */ + { 0 }, + { +/* short ctrl */ +/* valid rate_code Preamble dot11Rate Rate */ +/* 1 Mb */ { AH_TRUE, CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0 }, +/* 2 Mb */ { AH_TRUE, CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1 }, +/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80 | 11), 2 }, +/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80 | 22), 3 }, +/* Hardware workaround - remove rates 6, 9 from rate ctrl */ +/* 6 Mb */ { AH_FALSE, OFDM, 6000, 0x0b, 0x00, 12, 4 }, +/* 9 Mb */ { AH_FALSE, OFDM, 9000, 0x0f, 0x00, 18, 4 }, +/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, 24, 6 }, +/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 6 }, +/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, 48, 8 }, +/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 8 }, +/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 8 }, +/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8 }, + }, +}; + +HAL_RATE_TABLE ar9300_xr_table = { + 13, /* number of rates */ + { 0 }, + { +/* short ctrl */ +/* valid rate_code Preamble dot11Rate Rate */ +/* 0.25 Mb */ {AH_TRUE, XR, 250, 0x03, 0x00, (0x80 | 1), 0, 612, 612 }, +/* 0.5 Mb */ {AH_TRUE, XR, 500, 0x07, 0x00, (0x80 | 1), 0, 457, 457 }, +/* 1 Mb */ {AH_TRUE, XR, 1000, 0x02, 0x00, (0x80 | 2), 1, 228, 228 }, +/* 2 Mb */ {AH_TRUE, XR, 2000, 0x06, 0x00, (0x80 | 4), 2, 160, 160 }, +/* 3 Mb */ {AH_TRUE, XR, 3000, 0x01, 0x00, (0x80 | 6), 3, 140, 140 }, +/* 6 Mb */ {AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 4, 60, 60 }, +/* 9 Mb */ {AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 4, 60, 60 }, +/* 12 Mb */ {AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 6, 48, 48 }, +/* 18 Mb */ {AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 6, 48, 48 }, +/* 24 Mb */ {AH_TRUE, OFDM, 24000, 0x09, 0x00, 48, 8, 44, 44 }, +/* 36 Mb */ {AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 8, 44, 44 }, +/* 48 Mb */ {AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 8, 44, 44 }, +/* 54 Mb */ {AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8, 44, 44 }, + }, +}; + +#define AR9300_11NG_RT_OFDM_OFFSET 4 +#define AR9300_11NG_RT_HT_SS_OFFSET 12 +#define AR9300_11NG_RT_HT_DS_OFFSET 20 +#define AR9300_11NG_RT_HT_TS_OFFSET 28 +HAL_RATE_TABLE ar9300_11ng_table = { + + 36, /* number of rates */ + { 0 }, + { +/* short ctrl */ +/* valid rate_code Preamble dot11Rate Rate */ +/* 1 Mb */ { AH_TRUE, CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0 }, +/* 2 Mb */ { AH_TRUE, CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1 }, +/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80 | 11), 2 }, +/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80 | 22), 3 }, +/* Hardware workaround - remove rates 6, 9 from rate ctrl */ +/* 6 Mb */ { AH_FALSE, OFDM, 6000, 0x0b, 0x00, 12, 4 }, +/* 9 Mb */ { AH_FALSE, OFDM, 9000, 0x0f, 0x00, 18, 4 }, +/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, 24, 6 }, +/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 6 }, +/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, 48, 8 }, +/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 8 }, +/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 8 }, +/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8 }, +/*--- HT SS rates ---*/ +/* 6.5 Mb */ { AH_TRUE, HT, 6500, 0x80, 0x00, 0, 4 }, +/* 13 Mb */ { AH_TRUE, HT, 13000, 0x81, 0x00, 1, 6 }, +/*19.5 Mb */ { AH_TRUE, HT, 19500, 0x82, 0x00, 2, 6 }, +/* 26 Mb */ { AH_TRUE, HT, 26000, 0x83, 0x00, 3, 8 }, +/* 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 8 }, +/* 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 8 }, +/*58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 8 }, +/* 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 8 }, +/*--- HT DS rates ---*/ +/* 13 Mb */ { AH_TRUE, HT, 13000, 0x88, 0x00, 8, 4 }, +/* 26 Mb */ { AH_TRUE, HT, 26000, 0x89, 0x00, 9, 6 }, +/* 39 Mb */ { AH_TRUE, HT, 39000, 0x8a, 0x00, 10, 6 }, +/* 52 Mb */ { AH_TRUE, HT, 52000, 0x8b, 0x00, 11, 8 }, +/* 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 8 }, +/* 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 8 }, +/* 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 8 }, +/* 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 8 }, +/*--- HT TS rates ---*/ +/*19.5 Mb */ { AH_TRUE, HT, 19500, 0x90, 0x00, 16, 4 }, +/* 39 Mb */ { AH_TRUE, HT, 39000, 0x91, 0x00, 17, 6 }, +/*58.5 Mb */ { AH_TRUE, HT, 58500, 0x92, 0x00, 18, 6 }, +/* 78 Mb */ { AH_TRUE, HT, 78000, 0x93, 0x00, 19, 8 }, +/* 117 Mb */ { AH_TRUE, HT, 117000, 0x94, 0x00, 20, 8 }, +/* 156 Mb */ { AH_TRUE, HT, 156000, 0x95, 0x00, 21, 8 }, +/*175.5Mb */ { AH_TRUE, HT, 175500, 0x96, 0x00, 22, 8 }, +/* 195 Mb */ { AH_TRUE, HT, 195000, 0x97, 0x00, 23, 8 }, + }, +}; + +#define AR9300_11NA_RT_OFDM_OFFSET 0 +#define AR9300_11NA_RT_HT_SS_OFFSET 8 +#define AR9300_11NA_RT_HT_DS_OFFSET 16 +#define AR9300_11NA_RT_HT_TS_OFFSET 24 +static HAL_RATE_TABLE ar9300_11na_table = { + + 32, /* number of rates */ + { 0 }, + { +/* short ctrl */ +/* valid rate_code Preamble dot11Rate Rate */ +/* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0 }, +/* 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0 }, +/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2 }, +/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2 }, +/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4 }, +/* 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 4 }, +/* 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 4 }, +/* 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 4 }, +/*--- HT SS rates ---*/ +/* 6.5 Mb */ { AH_TRUE, HT, 6500, 0x80, 0x00, 0, 0 }, +/* 13 Mb */ { AH_TRUE, HT, 13000, 0x81, 0x00, 1, 2 }, +/*19.5 Mb */ { AH_TRUE, HT, 19500, 0x82, 0x00, 2, 2 }, +/* 26 Mb */ { AH_TRUE, HT, 26000, 0x83, 0x00, 3, 4 }, +/* 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 4 }, +/* 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 4 }, +/*58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 4 }, +/* 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 4 }, +/*--- HT DS rates ---*/ +/* 13 Mb */ { AH_TRUE, HT, 13000, 0x88, 0x00, 8, 0 }, +/* 26 Mb */ { AH_TRUE, HT, 26000, 0x89, 0x00, 9, 2 }, +/* 39 Mb */ { AH_TRUE, HT, 39000, 0x8a, 0x00, 10, 2 }, +/* 52 Mb */ { AH_TRUE, HT, 52000, 0x8b, 0x00, 11, 4 }, +/* 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 4 }, +/* 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 4 }, +/* 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 4 }, +/* 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 4 }, +/*--- HT TS rates ---*/ +/*19.5 Mb */ { AH_TRUE, HT, 19500, 0x90, 0x00, 16, 0 }, +/* 39 Mb */ { AH_TRUE, HT, 39000, 0x91, 0x00, 17, 2 }, +/*58.5 Mb */ { AH_TRUE, HT, 58500, 0x92, 0x00, 18, 2 }, +/* 78 Mb */ { AH_TRUE, HT, 78000, 0x93, 0x00, 19, 4 }, +/* 117 Mb */ { AH_TRUE, HT, 117000, 0x94, 0x00, 20, 4 }, +/* 156 Mb */ { AH_TRUE, HT, 156000, 0x95, 0x00, 21, 4 }, +/*175.5Mb */ { AH_TRUE, HT, 175500, 0x96, 0x00, 22, 4 }, +/* 195 Mb */ { AH_TRUE, HT, 195000, 0x97, 0x00, 23, 4 }, + }, +}; + +#undef OFDM +#undef CCK +#undef TURBO +#undef XR +#undef HT +#undef HT_HGI + +const HAL_RATE_TABLE * +ar9300_get_rate_table(struct ath_hal *ah, u_int mode) +{ + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; + HAL_RATE_TABLE *rt; + + switch (mode) { + case HAL_MODE_11A: + rt = &ar9300_11a_table; + break; + case HAL_MODE_11A_HALF_RATE: + if (p_cap->hal_chan_half_rate) { + rt = &ar9300_11a_half_table; + break; + } + return AH_NULL; + case HAL_MODE_11A_QUARTER_RATE: + if (p_cap->hal_chan_quarter_rate) { + rt = &ar9300_11a_quarter_table; + break; + } + return AH_NULL; + case HAL_MODE_11B: + rt = &ar9300_11b_table; + break; + case HAL_MODE_11G: + rt = &ar9300_11g_table; + break; + case HAL_MODE_TURBO: + case HAL_MODE_108G: + rt = &ar9300_turbo_table; + break; + case HAL_MODE_XR: + rt = &ar9300_xr_table; + break; + case HAL_MODE_11NG_HT20: + case HAL_MODE_11NG_HT40PLUS: + case HAL_MODE_11NG_HT40MINUS: + rt = &ar9300_11ng_table; + break; + case HAL_MODE_11NA_HT20: + case HAL_MODE_11NA_HT40PLUS: + case HAL_MODE_11NA_HT40MINUS: + rt = &ar9300_11na_table; + break; + default: + HALDEBUG(ah, HAL_DEBUG_CHANNEL, + "%s: invalid mode 0x%x\n", __func__, mode); + return AH_NULL; + } + ath_hal_setupratetable(ah, rt); + return rt; +} + +static HAL_BOOL +ar9300_invalid_stbc_cfg(int tx_chains, u_int8_t rate_code) +{ + switch (tx_chains) { + case 0: /* Single Chain */ + return AH_TRUE; + + case 1: /* 2 Chains */ + if ((rate_code < 0x80) || (rate_code > 0x87)) { + return AH_TRUE; + } else { + return AH_FALSE; + } + + case 2: /* 3 Chains */ + if ((rate_code < 0x80) || (rate_code > 0x87)) { + return AH_TRUE; + } else { + return AH_FALSE; + } + + default: + HALASSERT(0); + break; + } + + return AH_TRUE; +} + + +int16_t +ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode, u_int8_t rate_index, + u_int8_t chainmask, u_int8_t xmit_mode) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int num_chains = ar9300_get_ntxchains(chainmask); + + switch (xmit_mode) { + case AR9300_DEF_MODE: + return ahp->txpower[rate_index][num_chains-1]; + + + case AR9300_STBC_MODE: + return ahp->txpower_stbc[rate_index][num_chains-1]; + + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid mode 0x%x\n", + __func__, xmit_mode); + HALASSERT(0); + break; + } + + return ahp->txpower[rate_index][num_chains-1]; +} + +extern void +ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah, + u_int8_t power_per_rate[]) + +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int16_t twice_array_gain, cdd_power = 0; + int i; + + /* + * Adjust the upper limit for CDD factoring in the array gain . + * The array gain is the same as TxBF, hence reuse the same defines. + */ + switch (ahp->ah_tx_chainmask) { + + case OSPREY_1_CHAINMASK: + cdd_power = ahp->upper_limit[0]; + break; + + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + twice_array_gain = + (ahp->twice_antenna_gain >= ahp->twice_antenna_reduction)? + -(AR9300_TXBF_2TX_ARRAY_GAIN) : + ((int16_t)AH_MIN((ahp->twice_antenna_reduction - + (ahp->twice_antenna_gain + AR9300_TXBF_2TX_ARRAY_GAIN)), 0)); + cdd_power = ahp->upper_limit[1] + twice_array_gain; + /* Adjust OFDM legacy rates as well */ + for (i = ALL_TARGET_LEGACY_6_24; i <= ALL_TARGET_LEGACY_54; i++) { + if (power_per_rate[i] > cdd_power) { + power_per_rate[i] = cdd_power; + } + } + + /* 2Tx/(n-1) stream Adjust rates MCS0 through MCS 7 HT 20*/ + for (i = ALL_TARGET_HT20_0_8_16; i <= ALL_TARGET_HT20_7; i++) { + if (power_per_rate[i] > cdd_power) { + power_per_rate[i] = cdd_power; + } + } + + /* 2Tx/(n-1) stream Adjust rates MCS0 through MCS 7 HT 40*/ + for (i = ALL_TARGET_HT40_0_8_16; i <= ALL_TARGET_HT40_7; i++) { + if (power_per_rate[i] > cdd_power) { + power_per_rate[i] = cdd_power; + } + } + break; + + case OSPREY_3_CHAINMASK: + twice_array_gain = + (ahp->twice_antenna_gain >= ahp->twice_antenna_reduction)? + -(AR9300_TXBF_3TX_ARRAY_GAIN) : + ((int16_t)AH_MIN((ahp->twice_antenna_reduction - + (ahp->twice_antenna_gain + AR9300_TXBF_3TX_ARRAY_GAIN)), 0)); + cdd_power = ahp->upper_limit[2] + twice_array_gain; + /* Adjust OFDM legacy rates as well */ + for (i = ALL_TARGET_LEGACY_6_24; i <= ALL_TARGET_LEGACY_54; i++) { + if (power_per_rate[i] > cdd_power) { + power_per_rate[i] = cdd_power; + } + } + /* 3Tx/(n-1)streams Adjust rates MCS0 through MCS 15 HT20 */ + for (i = ALL_TARGET_HT20_0_8_16; i <= ALL_TARGET_HT20_15; i++) { + if (power_per_rate[i] > cdd_power) { + power_per_rate[i] = cdd_power; + } + } + + /* 3Tx/(n-1)streams Adjust rates MCS0 through MCS 15 HT40 */ + for (i = ALL_TARGET_HT40_0_8_16; i <= ALL_TARGET_HT40_15; i++) { + if (power_per_rate[i] > cdd_power) { + power_per_rate[i] = cdd_power; + } + } + + break; + + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, ahp->ah_tx_chainmask); + break; + } + + return; +} + +extern void +ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode, + HAL_CHANNEL_INTERNAL *chan, + u_int8_t power_per_rate[], u_int8_t chainmask) +{ + const HAL_RATE_TABLE *rt; + HAL_BOOL is40 = IS_CHAN_HT40(chan); + + rt = ar9300_get_rate_table(ah, mode); + HALASSERT(rt != NULL); + + switch (mode) { + case HAL_MODE_11A: + ar9300_init_rate_txpower_ofdm(ah, rt, power_per_rate, + AR9300_11A_RT_OFDM_OFFSET, chainmask); + break; + case HAL_MODE_11NA_HT20: + case HAL_MODE_11NA_HT40PLUS: + case HAL_MODE_11NA_HT40MINUS: + ar9300_init_rate_txpower_ofdm(ah, rt, power_per_rate, + AR9300_11NA_RT_OFDM_OFFSET, chainmask); + ar9300_init_rate_txpower_ht(ah, rt, is40, power_per_rate, + AR9300_11NA_RT_HT_SS_OFFSET, + AR9300_11NA_RT_HT_DS_OFFSET, + AR9300_11NA_RT_HT_TS_OFFSET, chainmask); + ar9300_init_rate_txpower_stbc(ah, rt, is40, + AR9300_11NA_RT_HT_SS_OFFSET, + AR9300_11NA_RT_HT_DS_OFFSET, + AR9300_11NA_RT_HT_TS_OFFSET, chainmask); + /* For FCC the array gain has to be factored for CDD mode */ + if (is_reg_dmn_fcc(chan->conformance_test_limit)) { + ar9300_adjust_rate_txpower_cdd(ah, rt, is40, + AR9300_11NA_RT_HT_SS_OFFSET, + AR9300_11NA_RT_HT_DS_OFFSET, + AR9300_11NA_RT_HT_TS_OFFSET, chainmask); + } + break; + case HAL_MODE_11G: + ar9300_init_rate_txpower_cck(ah, rt, power_per_rate, chainmask); + ar9300_init_rate_txpower_ofdm(ah, rt, power_per_rate, + AR9300_11G_RT_OFDM_OFFSET, chainmask); + break; + case HAL_MODE_11B: + ar9300_init_rate_txpower_cck(ah, rt, power_per_rate, chainmask); + break; + case HAL_MODE_11NG_HT20: + case HAL_MODE_11NG_HT40PLUS: + case HAL_MODE_11NG_HT40MINUS: + ar9300_init_rate_txpower_cck(ah, rt, power_per_rate, chainmask); + ar9300_init_rate_txpower_ofdm(ah, rt, power_per_rate, + AR9300_11NG_RT_OFDM_OFFSET, chainmask); + ar9300_init_rate_txpower_ht(ah, rt, is40, power_per_rate, + AR9300_11NG_RT_HT_SS_OFFSET, + AR9300_11NG_RT_HT_DS_OFFSET, + AR9300_11NG_RT_HT_TS_OFFSET, chainmask); + ar9300_init_rate_txpower_stbc(ah, rt, is40, + AR9300_11NG_RT_HT_SS_OFFSET, + AR9300_11NG_RT_HT_DS_OFFSET, + AR9300_11NG_RT_HT_TS_OFFSET, chainmask); + /* For FCC the array gain needs to be factored for CDD mode */ + if (is_reg_dmn_fcc(chan->conformance_test_limit)) { + ar9300_adjust_rate_txpower_cdd(ah, rt, is40, + AR9300_11NG_RT_HT_SS_OFFSET, + AR9300_11NG_RT_HT_DS_OFFSET, + AR9300_11NG_RT_HT_TS_OFFSET, chainmask); + } + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid mode 0x%x\n", + __func__, mode); + HALASSERT(0); + break; + } + +} + +static inline void +ar9300_init_rate_txpower_cck(struct ath_hal *ah, const HAL_RATE_TABLE *rt, + u_int8_t rates_array[], u_int8_t chainmask) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + /* + * Pick the lower of the long-preamble txpower, and short-preamble tx power. + * Unfortunately, the rate table doesn't have separate entries for these!. + */ + switch (chainmask) { + case OSPREY_1_CHAINMASK: + ahp->txpower[0][0] = rates_array[ALL_TARGET_LEGACY_1L_5L]; + ahp->txpower[1][0] = rates_array[ALL_TARGET_LEGACY_1L_5L]; + ahp->txpower[2][0] = AH_MIN(rates_array[ALL_TARGET_LEGACY_1L_5L], + rates_array[ALL_TARGET_LEGACY_5S]); + ahp->txpower[3][0] = AH_MIN(rates_array[ALL_TARGET_LEGACY_11L], + rates_array[ALL_TARGET_LEGACY_11S]); + break; + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + ahp->txpower[0][1] = rates_array[ALL_TARGET_LEGACY_1L_5L]; + ahp->txpower[1][1] = rates_array[ALL_TARGET_LEGACY_1L_5L]; + ahp->txpower[2][1] = AH_MIN(rates_array[ALL_TARGET_LEGACY_1L_5L], + rates_array[ALL_TARGET_LEGACY_5S]); + ahp->txpower[3][1] = AH_MIN(rates_array[ALL_TARGET_LEGACY_11L], + rates_array[ALL_TARGET_LEGACY_11S]); + break; + case OSPREY_3_CHAINMASK: + ahp->txpower[0][2] = rates_array[ALL_TARGET_LEGACY_1L_5L]; + ahp->txpower[1][2] = rates_array[ALL_TARGET_LEGACY_1L_5L]; + ahp->txpower[2][2] = AH_MIN(rates_array[ALL_TARGET_LEGACY_1L_5L], + rates_array[ALL_TARGET_LEGACY_5S]); + ahp->txpower[3][2] = AH_MIN(rates_array[ALL_TARGET_LEGACY_11L], + rates_array[ALL_TARGET_LEGACY_11S]); + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } +} + +static inline void +ar9300_init_rate_txpower_ofdm(struct ath_hal *ah, const HAL_RATE_TABLE *rt, + u_int8_t rates_array[], int rt_offset, + u_int8_t chainmask) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int16_t twice_array_gain, cdd_power = 0; + int i, j; + u_int8_t ofdm_rt_2_pwr_idx[8] = + { + ALL_TARGET_LEGACY_6_24, + ALL_TARGET_LEGACY_6_24, + ALL_TARGET_LEGACY_6_24, + ALL_TARGET_LEGACY_6_24, + ALL_TARGET_LEGACY_6_24, + ALL_TARGET_LEGACY_36, + ALL_TARGET_LEGACY_48, + ALL_TARGET_LEGACY_54, + }; + + /* + * For FCC adjust the upper limit for CDD factoring in the array gain. + * The array gain is the same as TxBF, hence reuse the same defines. + */ + for (i = rt_offset; i < rt_offset + AR9300_NUM_OFDM_RATES; i++) { + + /* Get the correct OFDM rate to Power table Index */ + j = ofdm_rt_2_pwr_idx[i- rt_offset]; + + switch (chainmask) { + case OSPREY_1_CHAINMASK: + ahp->txpower[i][0] = rates_array[j]; + break; + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + ahp->txpower[i][1] = rates_array[j]; + if (is_reg_dmn_fcc(ahp->reg_dmn)){ + twice_array_gain = (ahp->twice_antenna_gain >= + ahp->twice_antenna_reduction)? + -(AR9300_TXBF_2TX_ARRAY_GAIN) : + ((int16_t)AH_MIN((ahp->twice_antenna_reduction - + (ahp->twice_antenna_gain + AR9300_TXBF_2TX_ARRAY_GAIN)), 0)); + cdd_power = ahp->upper_limit[1] + twice_array_gain; + if (ahp->txpower[i][1] > cdd_power){ + ahp->txpower[i][1] = cdd_power; + } + } + break; + case OSPREY_3_CHAINMASK: + ahp->txpower[i][2] = rates_array[j]; + if (is_reg_dmn_fcc(ahp->reg_dmn)) { + twice_array_gain = + (ahp->twice_antenna_gain >= ahp->twice_antenna_reduction)? + -(AR9300_TXBF_3TX_ARRAY_GAIN): + ((int16_t)AH_MIN((ahp->twice_antenna_reduction - + (ahp->twice_antenna_gain + AR9300_TXBF_3TX_ARRAY_GAIN)), 0)); + cdd_power = ahp->upper_limit[2] + twice_array_gain; + if (ahp->txpower[i][2] > cdd_power){ + ahp->txpower[i][2] = cdd_power; + } + } + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } + } +} + +static u_int8_t mcs_rate_2_pwr_idx_ht20[24] = + { + ALL_TARGET_HT20_0_8_16, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_4, + ALL_TARGET_HT20_5, + ALL_TARGET_HT20_6, + ALL_TARGET_HT20_7, + ALL_TARGET_HT20_0_8_16, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_12, + ALL_TARGET_HT20_13, + ALL_TARGET_HT20_14, + ALL_TARGET_HT20_15, + ALL_TARGET_HT20_0_8_16, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_20, + ALL_TARGET_HT20_21, + ALL_TARGET_HT20_22, + ALL_TARGET_HT20_23 + }; + +static u_int8_t mcs_rate_2_pwr_idx_ht40[24] = + { + ALL_TARGET_HT40_0_8_16, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_4, + ALL_TARGET_HT40_5, + ALL_TARGET_HT40_6, + ALL_TARGET_HT40_7, + ALL_TARGET_HT40_0_8_16, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_12, + ALL_TARGET_HT40_13, + ALL_TARGET_HT40_14, + ALL_TARGET_HT40_15, + ALL_TARGET_HT40_0_8_16, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_20, + ALL_TARGET_HT40_21, + ALL_TARGET_HT40_22, + ALL_TARGET_HT40_23, + }; + +static inline void +ar9300_init_rate_txpower_ht(struct ath_hal *ah, const HAL_RATE_TABLE *rt, + HAL_BOOL is40, + u_int8_t rates_array[], + int rt_ss_offset, int rt_ds_offset, + int rt_ts_offset, u_int8_t chainmask) +{ + + struct ath_hal_9300 *ahp = AH9300(ah); + int i, j; + u_int8_t mcs_index = 0; + + + for (i = rt_ss_offset; i < rt_ss_offset + AR9300_NUM_HT_SS_RATES; i++) { + /* Get the correct MCS rate to Power table Index */ + j = (is40) ? mcs_rate_2_pwr_idx_ht40[mcs_index] : + mcs_rate_2_pwr_idx_ht20[mcs_index]; + switch (chainmask) { + case OSPREY_1_CHAINMASK: + ahp->txpower[i][0] = rates_array[j]; + break; + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + ahp->txpower[i][1] = rates_array[j]; + break; + case OSPREY_3_CHAINMASK: + ahp->txpower[i][2] = rates_array[j]; + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } + mcs_index++; + } + + for (i = rt_ds_offset; i < rt_ds_offset + AR9300_NUM_HT_DS_RATES; i++) { + /* Get the correct MCS rate to Power table Index */ + j = (is40) ? mcs_rate_2_pwr_idx_ht40[mcs_index] : + mcs_rate_2_pwr_idx_ht20[mcs_index]; + switch (chainmask) { + case OSPREY_1_CHAINMASK: + ahp->txpower[i][0] = rates_array[j]; + break; + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + ahp->txpower[i][1] = rates_array[j]; + break; + case OSPREY_3_CHAINMASK: + ahp->txpower[i][2] = rates_array[j]; + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } + mcs_index++; + } + + for (i = rt_ts_offset; i < rt_ts_offset + AR9300_NUM_HT_TS_RATES; i++) { + /* Get the correct MCS rate to Power table Index */ + j = (is40) ? mcs_rate_2_pwr_idx_ht40[mcs_index] : + mcs_rate_2_pwr_idx_ht20[mcs_index]; + switch (chainmask) { + case OSPREY_1_CHAINMASK: + ahp->txpower[i][0] = rates_array[j]; + break; + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + ahp->txpower[i][1] = rates_array[j]; + break; + case OSPREY_3_CHAINMASK: + ahp->txpower[i][2] = rates_array[j]; + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } + mcs_index++; + } +} + + +static inline void +ar9300_init_rate_txpower_stbc(struct ath_hal *ah, const HAL_RATE_TABLE *rt, + HAL_BOOL is40, + int rt_ss_offset, int rt_ds_offset, + int rt_ts_offset, u_int8_t chainmask) +{ + + struct ath_hal_9300 *ahp = AH9300(ah); + int i; + int16_t twice_array_gain, stbc_power = 0; + u_int8_t mcs_index = 0; + + /* Upper Limit with STBC */ + switch (chainmask) { + case OSPREY_1_CHAINMASK: + stbc_power = ahp->upper_limit[0]; + break; + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + stbc_power = ahp->upper_limit[1]; + break; + case OSPREY_3_CHAINMASK: + stbc_power = ahp->upper_limit[2]; + /* Ony FCC requires that we back off with 3 transmit chains */ + if (is_reg_dmn_fcc(ahp->reg_dmn)) { + twice_array_gain = + (ahp->twice_antenna_gain >= ahp->twice_antenna_reduction)? + -(AR9300_STBC_3TX_ARRAY_GAIN) : + ((int16_t)AH_MIN((ahp->twice_antenna_reduction - + (ahp->twice_antenna_gain + AR9300_STBC_3TX_ARRAY_GAIN)), 0)); + stbc_power = ahp->upper_limit[2] + twice_array_gain; + } + break; + + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } + + + for (i = rt_ss_offset; i < rt_ss_offset + AR9300_NUM_HT_SS_RATES; i++) { + switch (chainmask) { + case OSPREY_1_CHAINMASK: + ahp->txpower_stbc[i][0] = ahp->txpower[i][0]; + break; + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + ahp->txpower_stbc[i][1] = ahp->txpower[i][1]; + break; + case OSPREY_3_CHAINMASK: + ahp->txpower_stbc[i][2] = ahp->txpower[i][2]; + /* 3 TX/1 stream STBC gain adjustment */ + if (ahp->txpower_stbc[i][2] > stbc_power){ + ahp->txpower_stbc[i][2] = stbc_power; + } + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } + mcs_index++; + } + + for (i = rt_ds_offset; i < rt_ds_offset + AR9300_NUM_HT_DS_RATES; i++) { + switch (chainmask) { + case OSPREY_1_CHAINMASK: + ahp->txpower_stbc[i][0] = ahp->txpower[i][0]; + break; + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + ahp->txpower_stbc[i][1] = ahp->txpower[i][1]; + break; + case OSPREY_3_CHAINMASK: + ahp->txpower_stbc[i][2] = ahp->txpower[i][2]; + /* 3 TX/2 stream STBC gain adjustment */ + if (ahp->txpower_stbc[i][2] > stbc_power){ + ahp->txpower_stbc[i][2] = stbc_power; + } + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } + mcs_index++; + } + + for (i = rt_ts_offset; i < rt_ts_offset + AR9300_NUM_HT_TS_RATES; i++) { + switch (chainmask) { + case OSPREY_1_CHAINMASK: + ahp->txpower_stbc[i][0] = ahp->txpower[i][0]; + break; + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + ahp->txpower_stbc[i][1] = ahp->txpower[i][1]; + break; + case OSPREY_3_CHAINMASK: + ahp->txpower_stbc[i][2] = ahp->txpower[i][2]; + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } + mcs_index++; + } + + return; +} + +static inline void +ar9300_adjust_rate_txpower_cdd(struct ath_hal *ah, const HAL_RATE_TABLE *rt, + HAL_BOOL is40, + int rt_ss_offset, int rt_ds_offset, + int rt_ts_offset, u_int8_t chainmask) +{ + + struct ath_hal_9300 *ahp = AH9300(ah); + int i; + int16_t twice_array_gain, cdd_power = 0; + u_int8_t mcs_index = 0; + + /* + * Adjust the upper limit for CDD factoring in the array gain . + * The array gain is the same as TxBF, hence reuse the same defines. + */ + switch (chainmask) { + case OSPREY_1_CHAINMASK: + cdd_power = ahp->upper_limit[0]; + break; + + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + twice_array_gain = + (ahp->twice_antenna_gain >= ahp->twice_antenna_reduction)? + -(AR9300_TXBF_2TX_ARRAY_GAIN) : + ((int16_t)AH_MIN((ahp->twice_antenna_reduction - + (ahp->twice_antenna_gain + AR9300_TXBF_2TX_ARRAY_GAIN)), 0)); + cdd_power = ahp->upper_limit[1] + twice_array_gain; + break; + + case OSPREY_3_CHAINMASK: + twice_array_gain = + (ahp->twice_antenna_gain >= ahp->twice_antenna_reduction)? + -(AR9300_TXBF_3TX_ARRAY_GAIN) : + ((int16_t)AH_MIN((ahp->twice_antenna_reduction - + (ahp->twice_antenna_gain + AR9300_TXBF_3TX_ARRAY_GAIN)), 0)); + cdd_power = ahp->upper_limit[2] + twice_array_gain; + break; + + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } + + + for (i = rt_ss_offset; i < rt_ss_offset + AR9300_NUM_HT_SS_RATES; i++) { + switch (chainmask) { + case OSPREY_1_CHAINMASK: + break; + + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + /* 2 TX/1 stream CDD gain adjustment */ + if (ahp->txpower[i][1] > cdd_power){ + ahp->txpower[i][1] = cdd_power; + } + break; + case OSPREY_3_CHAINMASK: + /* 3 TX/1 stream CDD gain adjustment */ + if (ahp->txpower[i][2] > cdd_power){ + ahp->txpower[i][2] = cdd_power; + } + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } + mcs_index++; + } + + for (i = rt_ds_offset; i < rt_ds_offset + AR9300_NUM_HT_DS_RATES; i++) { + switch (chainmask) { + case OSPREY_1_CHAINMASK: + case OSPREY_2LOHI_CHAINMASK: + case OSPREY_2LOMID_CHAINMASK: + break; + case OSPREY_3_CHAINMASK: + /* 3 TX/2 stream TxBF gain adjustment */ + if (ahp->txpower[i][2] > cdd_power){ + ahp->txpower[i][2] = cdd_power; + } + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: invalid chainmask 0x%x\n", + __func__, chainmask); + break; + } + mcs_index++; + } + + return; + +} + +void ar9300_disp_tpc_tables(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + u_int mode = ath_hal_get_curmode(ah, chan); + const HAL_RATE_TABLE *rt; + int i, j; + + /* Check whether TPC is enabled */ + if (!AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc) { + ath_hal_printf(ah, "\n TPC Register method in use\n"); + return; + } + + rt = ar9300_get_rate_table(ah, mode); + HALASSERT(rt != NULL); + + ath_hal_printf(ah, "\n===TARGET POWER TABLE===\n"); + for (j = 0 ; j < ar9300_get_ntxchains(ahp->ah_tx_chainmask) ; j++ ) { + for (i = 0; i < rt->rateCount; i++) { + int16_t txpower[AR9300_MAX_CHAINS]; + txpower[j] = ahp->txpower[i][j]; + ath_hal_printf(ah, " Index[%2d] Rate[0x%02x] %6d kbps " + "Power (%d Chain) [%2d.%1d dBm]\n", + i, rt->info[i].rate_code, rt->info[i].rateKbps, + j + 1, txpower[j] / 2, txpower[j]%2 * 5); + } + } + ath_hal_printf(ah, "\n"); + + + ath_hal_printf(ah, "\n\n===TARGET POWER TABLE with STBC===\n"); + for ( j = 0 ; j < ar9300_get_ntxchains(ahp->ah_tx_chainmask) ; j++ ) { + for (i = 0; i < rt->rateCount; i++) { + int16_t txpower[AR9300_MAX_CHAINS]; + txpower[j] = ahp->txpower_stbc[i][j]; + + /* Do not display invalid configurations */ + if ((rt->info[i].rate_code < AR9300_MCS0_RATE_CODE) || + (rt->info[i].rate_code > AR9300_MCS23_RATE_CODE) || + ar9300_invalid_stbc_cfg(j, rt->info[i].rate_code) == AH_TRUE) { + continue; + } + + ath_hal_printf(ah, " Index[%2d] Rate[0x%02x] %6d kbps " + "Power (%d Chain) [%2d.%1d dBm]\n", + i, rt->info[i].rate_code, rt->info[i].rateKbps, + j + 1, txpower[j] / 2, txpower[j]%2 * 5); + } + } + ath_hal_printf(ah, "\n"); +} + +/* + * The followings are customer specific APIs for querying power limit. + * Power limit is based on regulatory domain, chipset, and transmission rate. + * Here we only consider EEPROM values, no array gain/CTL considered here. + */ + +struct rate_power_tbl { + u_int8_t rateIdx; /* rate index in the rate table */ + u_int32_t rateKbps; /* transfer rate in kbs */ + u_int8_t rateCode; /* rate for h/w descriptors */ + u_int8_t txbf: 1, /* txbf eligible */ + stbc: 1, /* stbc eligible */ + chain1: 1, /* one-chain eligible */ + chain2: 1, /* two-chain eligible */ + chain3: 1; /* three-chain eligible */ + int16_t txpower[AR9300_MAX_CHAINS]; /* txpower for different chainmasks */ + int16_t txpower_stbc[AR9300_MAX_CHAINS]; +}; + +u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + u_int mode = ath_hal_get_curmode(ah, chan); + const HAL_RATE_TABLE *rt; + u_int8_t *data; + struct rate_power_tbl *table; + int i, j; + + /* Check whether TPC is enabled */ + if (!AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc) { + ath_hal_printf(ah, "\n TPC Register method in use\n"); + return NULL; + } + + rt = ar9300_get_rate_table(ah, mode); + HALASSERT(rt != NULL); + + data = (u_int8_t *)ath_hal_malloc(ah, + 1 + rt->rateCount * sizeof(struct rate_power_tbl)); + if (data == NULL) + return NULL; + + OS_MEMZERO(data, 1 + rt->rateCount * sizeof(struct rate_power_tbl)); + /* store the rate count at the beginning */ + *data = rt->rateCount; + table = (struct rate_power_tbl *)&data[1]; + + for (j = 0 ; j < ar9300_get_ntxchains(ahp->ah_tx_chainmask) ; j++ ) { + for (i = 0; i < rt->rateCount; i++) { + table[i].rateIdx = i; + table[i].rateCode = rt->info[i].rate_code; + table[i].rateKbps = rt->info[i].rateKbps; + switch (j) { + case 0: + table[i].chain1 = rt->info[i].rate_code <= 0x87 ? 1 : 0; + break; + case 1: + table[i].chain2 = rt->info[i].rate_code <= 0x8f ? 1 : 0; + break; + case 2: + table[i].chain3 = 1; + break; + default: + break; + } + if ((j == 0 && table[i].chain1) || + (j == 1 && table[i].chain2) || + (j == 2 && table[i].chain3)) + table[i].txpower[j] = ahp->txpower[i][j]; + } + } + + + for ( j = 0 ; j < ar9300_get_ntxchains(ahp->ah_tx_chainmask) ; j++ ) { + for (i = 0; i < rt->rateCount; i++) { + /* Do not display invalid configurations */ + if ((rt->info[i].rate_code < AR9300_MCS0_RATE_CODE) || + (rt->info[i].rate_code > AR9300_MCS23_RATE_CODE) || + ar9300_invalid_stbc_cfg(j, rt->info[i].rate_code) == AH_TRUE) { + continue; + } + + table[i].stbc = 1; + table[i].txpower_stbc[j] = ahp->txpower_stbc[i][j]; + } + } + + return data; + /* the caller is responsible to free data */ +} + +HAL_STATUS +ath_hal_get_rate_power_limit_from_eeprom(struct ath_hal *ah, u_int16_t freq, + int8_t *max_rate_power, int8_t *min_rate_power) +{ + /* + * Used for AR9300 series chip only + */ + if (AH_PRIVATE(ah)->ah_magic == AR9300_MAGIC) { + u_int8_t target_rate_power_limit_val_t2[ar9300_rate_size]; + int i; + + *max_rate_power = 0; + *min_rate_power = AR9300_MAX_RATE_POWER; + + ar9300_set_target_power_from_eeprom(ah, freq, target_rate_power_limit_val_t2); + + for (i=0; i *max_rate_power) + *max_rate_power = target_rate_power_limit_val_t2[i]; + if (target_rate_power_limit_val_t2[i] < *min_rate_power) + *min_rate_power = target_rate_power_limit_val_t2[i]; + } + } else { + *max_rate_power = 0; + *min_rate_power = 0; + } + + return HAL_OK; +} +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_power.c b/hal/ar9300/ar9300_power.c new file mode 100644 index 000000000000..9e3d9c98d004 --- /dev/null +++ b/hal/ar9300/ar9300_power.c @@ -0,0 +1,1559 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" + +#if ATH_WOW_OFFLOAD +void ar9300_wowoffload_prep(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + ahp->ah_mcast_filter_l32_set = 0; + ahp->ah_mcast_filter_u32_set = 0; +} + +void ar9300_wowoffload_post(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t val; + + if (ahp->ah_mcast_filter_l32_set != 0) { + val = OS_REG_READ(ah, AR_MCAST_FIL0); + val &= ~ahp->ah_mcast_filter_l32_set; + OS_REG_WRITE(ah, AR_MCAST_FIL0, val); + } + if (ahp->ah_mcast_filter_u32_set != 0) { + val = OS_REG_READ(ah, AR_MCAST_FIL1); + val &= ~ahp->ah_mcast_filter_u32_set; + OS_REG_WRITE(ah, AR_MCAST_FIL1, val); + } + + ahp->ah_mcast_filter_l32_set = 0; + ahp->ah_mcast_filter_u32_set = 0; +} + +static void ar9300_wowoffload_add_mcast_filter(struct ath_hal *ah, u_int8_t *mc_addr) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t reg, val; + u_int8_t pos, high32; + + memcpy((u_int8_t *) &val, &mc_addr[0], 3); + pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; + memcpy((u_int8_t *) &val, &mc_addr[3], 3); + pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; + high32 = pos & 0x20; + reg = high32 ? AR_MCAST_FIL1 : AR_MCAST_FIL0; + pos &= 0x1F; + + val = OS_REG_READ(ah, reg); + if ((val & (1 << pos)) == 0) { + val |= (1 << pos); + if (high32) { + ahp->ah_mcast_filter_u32_set |= (1 << pos); + } else { + ahp->ah_mcast_filter_l32_set |= (1 << pos); + } + OS_REG_WRITE(ah, reg, val); + } +} + +/* + * DeviceID SWAR - EV91928 + * + * During SW WOW, 0x4004[13] is set to allow BT eCPU to access WLAN MAC + * registers. Setting 00x4004[13] will prevent eeprom state machine to + * load customizable PCIE configuration registers, which lead to the PCIE + * device id stay as default 0xABCD. The SWAR to have BT eCPU to write + * to PCIE registers as soon as it detects PCIE reset is deasserted. + */ +void ar9300_wowoffload_download_devid_swar(struct ath_hal *ah) +{ + u_int32_t addr = AR_WOW_OFFLOAD_WLAN_REGSET_NUM; + + OS_REG_WRITE(ah, addr, 8); + addr += 4; + OS_REG_WRITE(ah, addr, 0x5000); + addr += 4; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) pcie_000 = %08x\n", + AH_PRIVATE(ah)->ah_config.ath_hal_pcie_000); + OS_REG_WRITE(ah, addr, AH_PRIVATE(ah)->ah_config.ath_hal_pcie_000); + addr += 4; + OS_REG_WRITE(ah, addr, 0x5008); + addr += 4; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) pcie_008 = %08x\n", + AH_PRIVATE(ah)->ah_config.ath_hal_pcie_008); + OS_REG_WRITE(ah, addr, AH_PRIVATE(ah)->ah_config.ath_hal_pcie_008); + addr += 4; + OS_REG_WRITE(ah, addr, 0x502c); + addr += 4; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) pcie_02c = %08x\n", + AH_PRIVATE(ah)->ah_config.ath_hal_pcie_02c); + OS_REG_WRITE(ah, addr, AH_PRIVATE(ah)->ah_config.ath_hal_pcie_02c); + addr += 4; + OS_REG_WRITE(ah, addr, 0x18c00); + addr += 4; + OS_REG_WRITE(ah, addr, 0x18212ede); + addr += 4; + OS_REG_WRITE(ah, addr, 0x18c04); + addr += 4; + OS_REG_WRITE(ah, addr, 0x008001d8); + addr += 4; + OS_REG_WRITE(ah, addr, 0x18c08); + addr += 4; + OS_REG_WRITE(ah, addr, 0x0003580c); + addr += 4; + OS_REG_WRITE(ah, addr, 0x570c); + addr += 4; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) pcie_70c = %08x\n", + AH_PRIVATE(ah)->ah_config.ath_hal_pcie_70c); + OS_REG_WRITE(ah, addr, AH_PRIVATE(ah)->ah_config.ath_hal_pcie_70c); + addr += 4; + OS_REG_WRITE(ah, addr, 0x5040); + addr += 4; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) pcie_040 = %08x\n", + AH_PRIVATE(ah)->ah_config.ath_hal_pcie_040); + OS_REG_WRITE(ah, addr, AH_PRIVATE(ah)->ah_config.ath_hal_pcie_040); + addr += 4; +/* + A_SOC_REG_WRITE(0x45000, 0x0034168c); + A_SOC_REG_WRITE(0x45008, 0x02800001); + A_SOC_REG_WRITE(0x4502c, 0x3117168c); + A_SOC_REG_WRITE(0x58c00, 0x18212ede); + A_SOC_REG_WRITE(0x58c04, 0x000801d8); + A_SOC_REG_WRITE(0x58c08, 0x0003580c); + A_SOC_REG_WRITE(0x4570c, 0x275f3f01); + A_SOC_REG_WRITE(0x45040, 0xffc25001); +*/ +} + +/* Retrieve updated information from MAC PCU buffer. + * Embedded CPU would have written the value before exiting WoW + * */ +void ar9300_wowoffload_retrieve_data(struct ath_hal *ah, void *buf, u_int32_t param) +{ + u_int32_t rc_lower, rc_upper; + + if (param == WOW_PARAM_REPLAY_CNTR) { + rc_lower = OS_REG_READ(ah, AR_WOW_TXBUF(0)); + rc_upper = OS_REG_READ(ah, AR_WOW_TXBUF(1)); + *(u_int64_t *)buf = rc_lower + (rc_upper << 32); + } + else if (param == WOW_PARAM_KEY_TSC) { + rc_lower = OS_REG_READ(ah, AR_WOW_TXBUF(2)); + rc_upper = OS_REG_READ(ah, AR_WOW_TXBUF(3)); + *(u_int64_t *)buf = rc_lower + (rc_upper << 32); + } + else if (param == WOW_PARAM_TX_SEQNUM) { + *(u_int32_t *)buf = OS_REG_READ(ah, AR_WOW_TXBUF(4)); + } + +} + +/* Download GTK rekey related information to the embedded CPU */ +u_int32_t ar9300_wowoffload_download_rekey_data(struct ath_hal *ah, u_int32_t *data, u_int32_t bytes) +{ + int i; + int mbox_status = OS_REG_READ(ah, AR_MBOX_CTRL_STATUS); + u_int32_t gtk_data_start; + + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) %s, bytes=%d\n", __func__, bytes); + if (AR_SREV_JUPITER(ah) && + (bytes > (AR_WOW_OFFLOAD_GTK_DATA_WORDS_JUPITER * 4))) + { + bytes = AR_WOW_OFFLOAD_GTK_DATA_WORDS_JUPITER * 4; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) bytes truncated to %d\n", bytes); + } + /* Check if mailbox is busy */ + if (mbox_status != 0) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: Mailbox register busy! Reg = 0x%x", __func__, mbox_status); + return 1; + } + + /* Clear status */ + OS_REG_WRITE(ah, AR_EMB_CPU_WOW_STATUS, 0x0); + OS_REG_WRITE(ah, AR_WLAN_WOW_ENABLE, 0); + OS_REG_WRITE(ah, AR_WLAN_WOW_STATUS, 0xFFFFFFFF); + + if (AR_SREV_JUPITER(ah)) { + gtk_data_start = AR_WOW_OFFLOAD_GTK_DATA_START_JUPITER; + } else { + gtk_data_start = AR_WOW_OFFLOAD_GTK_DATA_START; + } + for (i = 0;i < bytes/4; i++) { + OS_REG_WRITE(ah, gtk_data_start + i * 4, data[i]); + } + + return 0; +} + +void ar9300_wowoffload_download_acer_magic( struct ath_hal *ah, + HAL_BOOL valid, + u_int8_t* datap, + u_int32_t bytes) +{ + u_int32_t *p32 = (u_int32_t *) datap; + u_int32_t l = 0, u = 0; + + if (valid) { + l = *p32; + p32++; + u = *(u_int16_t *) p32; + } + + OS_REG_WRITE(ah, AR_WOW_OFFLOAD_ACER_MAGIC_START, l); + OS_REG_WRITE(ah, AR_WOW_OFFLOAD_ACER_MAGIC_START + 4, u); + + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: Aer Magic: %02x-%02x-%02x-%02x-%02x-%02x\n", __func__, + datap[0], datap[1], datap[2], datap[3], datap[4], datap[5]); +} + +void ar9300_wowoffload_download_acer_swka( struct ath_hal *ah, + u_int32_t id, + HAL_BOOL valid, + u_int32_t period, + u_int32_t size, + u_int32_t* datap) +{ + u_int32_t ka_period[2] = { + AR_WOW_OFFLOAD_ACER_KA0_PERIOD_MS, + AR_WOW_OFFLOAD_ACER_KA1_PERIOD_MS + }; + u_int32_t ka_size[2] = { + AR_WOW_OFFLOAD_ACER_KA0_SIZE, + AR_WOW_OFFLOAD_ACER_KA1_SIZE + }; + u_int32_t ka_data[2] = { + AR_WOW_OFFLOAD_ACER_KA0_DATA, + AR_WOW_OFFLOAD_ACER_KA1_DATA + }; + u_int32_t n_data = AR_WOW_OFFLOAD_ACER_KA0_DATA_WORDS; + int i; + + if (id >= 2) { + return; + } + + if (valid) { + OS_REG_WRITE(ah, ka_period[id], period); + OS_REG_WRITE(ah, ka_size[id], size); + } else { + OS_REG_WRITE(ah, ka_period[id], 0); + OS_REG_WRITE(ah, ka_size[id], 0); + } + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: id=%d, period=%d ms, size=%d bytes\n", + __func__, id, period, size); + + if (size < (n_data * 4)) { + n_data = (size + 3) / 4; + } + for (i=0; ivalid) { + OS_REG_WRITE(ah, addr, 0x1); + addr += 4; + OS_REG_WRITE(ah, addr, p_info->RemoteIPv4Address.u32); + addr += 4; + OS_REG_WRITE(ah, addr, p_info->HostIPv4Address.u32); + addr += 4; + OS_REG_WRITE(ah, addr, p_info->MacAddress.u32[0]); + addr += 4; + OS_REG_WRITE(ah, addr, p_info->MacAddress.u32[1]); + } else { + OS_REG_WRITE(ah, addr, 0x0); + } +} + +#define WOW_WRITE_NS_IPV6_ADDRESS(_ah, _buf_addr, _p_ipv6_addr) \ + { \ + u_int32_t offset = (_buf_addr); \ + u_int32_t *p_ipv6_addr = (u_int32_t *) (_p_ipv6_addr); \ + int i; \ + for (i = 0; i < 4; i++) { \ + OS_REG_WRITE((_ah), offset, *p_ipv6_addr); \ + offset += 4; \ + p_ipv6_addr ++; \ + } \ + } + +void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data) +{ + u_int32_t addr; + struct hal_wow_offload_ns_info *p_info = (struct hal_wow_offload_ns_info *) data; + u_int8_t mc_addr[6]; + + if (id == 0) { + addr = AR_WOW_OFFLOAD_NS0_VALID; + } else if (id == 1) { + addr = AR_WOW_OFFLOAD_NS1_VALID; + } else { + return; + } + + if (p_info->valid) { + OS_REG_WRITE(ah, addr, 0x1); + addr += 4; + WOW_WRITE_NS_IPV6_ADDRESS(ah, addr, &p_info->RemoteIPv6Address.u32[0]); + addr += 4 * 4; + WOW_WRITE_NS_IPV6_ADDRESS(ah, addr, &p_info->SolicitedNodeIPv6Address.u32[0]); + addr += 4 * 4; + OS_REG_WRITE(ah, addr, p_info->MacAddress.u32[0]); + addr += 4; + OS_REG_WRITE(ah, addr, p_info->MacAddress.u32[1]); + addr += 4; + WOW_WRITE_NS_IPV6_ADDRESS(ah, addr, &p_info->TargetIPv6Addresses[0].u32[0]); + addr += 4 * 4; + WOW_WRITE_NS_IPV6_ADDRESS(ah, addr, &p_info->TargetIPv6Addresses[1].u32[0]); + + mc_addr[0] = 0x33; + mc_addr[1] = 0x33; + mc_addr[2] = 0xFF; + mc_addr[3] = p_info->SolicitedNodeIPv6Address.u8[13]; + mc_addr[4] = p_info->SolicitedNodeIPv6Address.u8[14]; + mc_addr[5] = p_info->SolicitedNodeIPv6Address.u8[15]; + ar9300_wowoffload_add_mcast_filter(ah, mc_addr); + } else { + OS_REG_WRITE(ah, addr, 0x0); + } +} + +/* Download transmit parameters for GTK response frame during WoW + * offload */ +u_int32_t ar9300_wow_offload_download_hal_params(struct ath_hal *ah) +{ + u_int32_t tpc = 0x3f; /* Transmit Power Control */ + u_int32_t tx_tries_series = 7; + u_int32_t tx_rate_series, transmit_rate; + u_int32_t gtk_txdesc_param_start; + + if (AH_PRIVATE(ah)->ah_curchan->channel_flags & CHANNEL_CCK) { + transmit_rate = 0x1B; /* CCK_1M */ + } else { + transmit_rate = 0xB; /* OFDM_6M */ + } + + /* Use single rate for now. Change later as need be */ + tx_rate_series = transmit_rate; + tx_tries_series = 7; + + if (AR_SREV_JUPITER(ah)) { + gtk_txdesc_param_start = AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START_JUPITER; + } else { + gtk_txdesc_param_start = AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START; + } +#define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM(x) (gtk_txdesc_param_start + ((x) * 4)) + + /* Do not change the data order unless firmware code on embedded + * CPU is changed correspondingly */ + OS_REG_WRITE(ah, AR_WOW_OFFLOAD_GTK_TXDESC_PARAM(0), tx_rate_series); + OS_REG_WRITE(ah, AR_WOW_OFFLOAD_GTK_TXDESC_PARAM(1), tx_tries_series); + OS_REG_WRITE(ah, AR_WOW_OFFLOAD_GTK_TXDESC_PARAM(2), AH9300(ah)->ah_tx_chainmask); + OS_REG_WRITE(ah, AR_WOW_OFFLOAD_GTK_TXDESC_PARAM(3), tpc); + + return 0; +} + +/* Indicate to the embedded CPU that host is ready to enter WoW mode. + * Embedded CPU will copy relevant information from the MAC PCU buffer + */ +u_int32_t ar9300_wow_offload_handshake(struct ath_hal *ah, u_int32_t pattern_enable) +{ + int val; + int mbox_status = OS_REG_READ(ah, AR_MBOX_CTRL_STATUS); +#if ATH_WOW_OFFLOAD + u_int32_t bt_handshake_timeout_us = HAL_WOW_CTRL_WAIT_BT_TO(ah) * 100000; + +#define AH_DEFAULT_BT_WAIT_TIMEOUT 3000000; /* 3 sec */ + if (bt_handshake_timeout_us == 0) { + bt_handshake_timeout_us = AH_DEFAULT_BT_WAIT_TIMEOUT; + } + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) TIMEOUT: %d us\n", bt_handshake_timeout_us); +#endif /* ATH_WOW_OFFLOAD */ + + if (mbox_status & AR_MBOX_WOW_REQ) { + /* WOW mode request handshake is already in progress. + * Do nothing */ + return 0; + } + + /* Clear status */ + OS_REG_WRITE(ah, AR_MBOX_CTRL_STATUS, 0); + OS_REG_WRITE(ah, AR_EMB_CPU_WOW_STATUS, 0x0); + OS_REG_WRITE(ah, AR_WLAN_WOW_ENABLE, 0); + OS_REG_WRITE(ah, AR_WLAN_WOW_STATUS, 0xFFFFFFFF); + + OS_REG_WRITE(ah, AR_RIMT, 0); + OS_REG_WRITE(ah, AR_TIMT, 0); + + val = 0; + if (pattern_enable & AH_WOW_USER_PATTERN_EN) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - User pattern\n"); + val |= AR_EMB_CPU_WOW_ENABLE_PATTERN_MATCH; + } + else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - User pattern\n"); + } + if ((pattern_enable & AH_WOW_MAGIC_PATTERN_EN) +#if ATH_WOW_OFFLOAD + || (pattern_enable & AH_WOW_ACER_MAGIC_EN) +#endif + ) + { + val |= AR_EMB_CPU_WOW_ENABLE_MAGIC_PATTERN; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Magic pattern\n"); + } + else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Magic pattern\n"); + } + if ((pattern_enable & AH_WOW_LINK_CHANGE) +#if ATH_WOW_OFFLOAD + || HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_KAFAIL_ENABLE) +#endif + ) + { + val |= AR_EMB_CPU_WOW_ENABLE_KEEP_ALIVE_FAIL; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Kepp alive fail\n"); + } + else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Kepp alive fail\n"); + } + if (pattern_enable & AH_WOW_BEACON_MISS) { + val |= AR_EMB_CPU_WOW_ENABLE_BEACON_MISS; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Becon Miss\n"); + } + else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Becon Miss\n"); + } + + OS_REG_WRITE(ah, AR_EMB_CPU_WOW_ENABLE, val); + + OS_REG_CLR_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF); + OS_REG_SET_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_REQ); + OS_REG_SET_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_INT_EMB_CPU); + + if (!ath_hal_wait(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF, AR_MBOX_WOW_CONF, bt_handshake_timeout_us)) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: WoW offload handshake failed", __func__); + return 0; + } + else { + OS_REG_CLR_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF); + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: WoW offload handshake successful",__func__); + } + return 1; +} +#endif /* ATH_WOW_OFFLOAD */ + +/* + * Notify Power Mgt is enabled in self-generated frames. + * If requested, force chip awake. + * + * Returns A_OK if chip is awake or successfully forced awake. + * + * WARNING WARNING WARNING + * There is a problem with the chip where sometimes it will not wake up. + */ +HAL_BOOL +ar9300_set_power_mode_awake(struct ath_hal *ah, int set_chip) +{ + struct ath_hal_9300 *ahp = AH9300(ah); +#define POWER_UP_TIME 10000 + u_int32_t val; + int i; + + /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); + OS_DELAY(10); /* delay to allow the write to take effect. */ + + if (set_chip) { + /* Do a Power-On-Reset if MAC is shutdown */ + if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_SHUTDOWN)) { + if (ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON) != AH_TRUE) { + HALASSERT(0); + return AH_FALSE; + } + } + + OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); + + OS_DELAY(50); + + for (i = POWER_UP_TIME / 50; i > 0; i--) { + val = OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; + if (val == AR_RTC_STATUS_ON) { + break; + } + OS_DELAY(50); + OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); + } + if (i == 0) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: Failed to wakeup in %uus\n", + __func__, POWER_UP_TIME / 20); + return AH_FALSE; + } + + } + + OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); + return AH_TRUE; +#undef POWER_UP_TIME +} + +/* + * Notify Power Mgt is disabled in self-generated frames. + * If requested, force chip to sleep. + */ +static void +ar9300_set_power_mode_sleep(struct ath_hal *ah, int set_chip) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); + if (set_chip ) { + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_WRITE(ah, AR_TIMER_MODE, + OS_REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00); + OS_REG_WRITE(ah, AR_GEN_TIMERS2_MODE, + OS_REG_READ(ah, AR_GEN_TIMERS2_MODE) & 0xFFFFFF00); + OS_REG_WRITE(ah, AR_SLP32_INC, + OS_REG_READ(ah, AR_SLP32_INC) & 0xFFF00000); + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); + OS_DELAY(100); + } + /* Clear the RTC force wake bit to allow the mac to go to sleep */ + OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); + + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + /* + * In Jupiter, after enter sleep mode, hardware will send + * a SYS_SLEEPING message through MCI interface. Add a + * few us delay to make sure the message can reach BT side. + */ + OS_DELAY(100); + } + + if (!AR_SREV_JUPITER_10(ah)) { + /* Shutdown chip. Active low */ + OS_REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); + /* Settle time */ + OS_DELAY(2); + } + } + +#if ATH_WOW_OFFLOAD + if (!AR_SREV_JUPITER(ah) || !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14)) +#endif /* ATH_WOW_OFFLOAD */ + { + /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), + ahp->ah_wa_reg_val & ~AR_WA_D3_TO_L1_DISABLE); + } +} + +/* + * Notify Power Management is enabled in self-generating + * frames. If request, set power mode of chip to + * auto/normal. Duration in units of 128us (1/8 TU). + */ +static void +ar9300_set_power_mode_network_sleep(struct ath_hal *ah, int set_chip) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); + if (set_chip) { + HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + + if (! p_cap->hal_auto_sleep_support) { + /* Set wake_on_interrupt bit; clear force_wake bit */ + OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); + } + else { + /* + * When chip goes into network sleep, it could be waken up by + * MCI_INT interrupt caused by BT's HW messages (LNA_xxx, CONT_xxx) + * which chould be in a very fast rate (~100us). This will cause + * chip to leave and re-enter network sleep mode frequently, which + * in consequence will have WLAN MCI HW to generate lots of + * SYS_WAKING and SYS_SLEEPING messages which will make BT CPU + * to busy to process. + */ + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, + OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & + ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK); + } + + /* Clear the RTC force wake bit to allow the mac to go to sleep */ + OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); + + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + /* + * In Jupiter, after enter sleep mode, hardware will send + * a SYS_SLEEPING message through MCI interface. Add a + * few us delay to make sure the message can reach BT side. + */ + OS_DELAY(30); + } + } + } + +#if ATH_WOW_OFFLOAD + if (!AR_SREV_JUPITER(ah) || !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14)) +#endif /* ATH_WOW_OFFLOAD */ + { + /* Clear Bit 14 of AR_WA after putting chip into Sleep mode. */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), + ahp->ah_wa_reg_val & ~AR_WA_D3_TO_L1_DISABLE); + } +} + +/* + * Set power mgt to the requested mode, and conditionally set + * the chip as well + */ +HAL_BOOL +ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, int set_chip) +{ + struct ath_hal_9300 *ahp = AH9300(ah); +#if AH_DEBUG || AH_PRINT_FILTER + static const char* modes[] = { + "AWAKE", + "FULL-SLEEP", + "NETWORK SLEEP", + "UNDEFINED" + }; +#endif + int status = AH_TRUE; + + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__, + modes[ar9300_get_power_mode(ah)], modes[mode], + set_chip ? "set chip " : ""); + + switch (mode) { + case HAL_PM_AWAKE: + status = ar9300_set_power_mode_awake(ah, set_chip); +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) { + OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); + } +#endif + break; + case HAL_PM_FULL_SLEEP: +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) { + if (ar9300_get_power_mode(ah) == HAL_PM_AWAKE) { + if ((ar9300_mci_state(ah, HAL_MCI_STATE_ENABLE, NULL) != 0) && + (ahp->ah_mci_bt_state != MCI_BT_SLEEP) && + !ahp->ah_mci_halted_bt_gpm) + { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: HALT BT GPM (full_sleep)\n", __func__); + ar9300_mci_send_coex_halt_bt_gpm(ah, AH_TRUE, AH_TRUE); + } + } + ahp->ah_mci_ready = AH_FALSE; + } +#endif +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) { + OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); + } +#endif + ar9300_set_power_mode_sleep(ah, set_chip); + ahp->ah_chip_full_sleep = AH_TRUE; + break; + case HAL_PM_NETWORK_SLEEP: +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) { + OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); + } +#endif + ar9300_set_power_mode_network_sleep(ah, set_chip); + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, + "%s: unknown power mode %u\n", __func__, mode); + return AH_FALSE; + } + return status; +} + +/* + * Return the current sleep mode of the chip + */ +HAL_POWER_MODE +ar9300_get_power_mode(struct ath_hal *ah) +{ + int mode = OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; + + switch (mode) { + case AR_RTC_STATUS_ON: + case AR_RTC_STATUS_WAKEUP: + return HAL_PM_AWAKE; + break; + case AR_RTC_STATUS_SLEEP: + return HAL_PM_NETWORK_SLEEP; + break; + case AR_RTC_STATUS_SHUTDOWN: + return HAL_PM_FULL_SLEEP; + break; + default: + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, + "%s: unknown power mode 0x%x\n", __func__, mode); + return HAL_PM_UNDEFINED; + } +} + +/* + * Set SM power save mode + */ +void +ar9300_set_sm_power_mode(struct ath_hal *ah, HAL_SMPS_MODE mode) +{ + int regval; + struct ath_hal_9300 *ahp = AH9300(ah); + + if (ar9300_get_capability(ah, HAL_CAP_DYNAMIC_SMPS, 0, AH_NULL) != HAL_OK) { + return; + } + + /* Program low & high power chainmask settings and enable MAC control */ + regval = SM(AR_PCU_SMPS_LPWR_CHNMSK_VAL, AR_PCU_SMPS_LPWR_CHNMSK) | + SM(ahp->ah_rx_chainmask, AR_PCU_SMPS_HPWR_CHNMSK) | + AR_PCU_SMPS_MAC_CHAINMASK; + + /* Program registers according to required SM power mode.*/ + switch (mode) { + case HAL_SMPS_SW_CTRL_LOW_PWR: + OS_REG_WRITE(ah, AR_PCU_SMPS, regval); + break; + case HAL_SMPS_SW_CTRL_HIGH_PWR: + OS_REG_WRITE(ah, AR_PCU_SMPS, regval | AR_PCU_SMPS_SW_CTRL_HPWR); + break; + case HAL_SMPS_HW_CTRL: + OS_REG_WRITE(ah, AR_PCU_SMPS, regval | AR_PCU_SMPS_HW_CTRL_EN); + break; + case HAL_SMPS_DEFAULT: + OS_REG_WRITE(ah, AR_PCU_SMPS, 0); + break; + default: + break; + } + ahp->ah_sm_power_mode = mode; +} + +#if ATH_WOW +#if NOT_NEEDED_FOR_OSPREY /* not compiled for darwin */ +/* + * This routine is called to configure the SerDes register for the + * Merlin 2.0 and above chip during WOW sleep. + */ +static void +ar9280_config_ser_des__wow_sleep(struct ath_hal *ah) +{ + int i; + struct ath_hal_9300 *ahp = AH9300(ah); + + /* + * For WOW sleep, we reprogram the SerDes so that the PLL and CHK REQ + * are both enabled. This uses more power but the Maverick team reported + * that otherwise, WOW sleep is unstable and chip may disappears. + */ + for (i = 0; i < ahp->ah_ini_pcie_serdes_wow.ia_rows; i++) { + OS_REG_WRITE(ah, + INI_RA(&ahp->ah_ini_pcie_serdes_wow, i, 0), + INI_RA(&ahp->ah_ini_pcie_serdes_wow, i, 1)); + } + OS_DELAY(1000); +} +#endif /* if NOT_NEEDED_FOR_OSPREY */ +static HAL_BOOL +ar9300_wow_create_keep_alive_pattern(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t frame_len = 28; + u_int32_t tpc = 0x3f; + u_int32_t transmit_rate; + u_int32_t frame_type = 0x2; /* Frame Type -> Data; */ + u_int32_t sub_type = 0x4; /* Subtype -> Null Data */ + u_int32_t to_ds = 1; + u_int32_t duration_id = 0x3d; + u_int8_t *sta_mac_addr, *ap_mac_addr; + u_int8_t *addr1, *addr2, *addr3; + u_int32_t ctl[13] = { 0, }; +#define NUM_KA_DATA_WORDS 6 + u_int32_t data_word[NUM_KA_DATA_WORDS]; + u_int32_t i; + u_int32_t wow_ka_dataword0; + + sta_mac_addr = (u_int8_t *)ahp->ah_macaddr; + ap_mac_addr = (u_int8_t *)ahp->ah_bssid; + addr2 = sta_mac_addr; + addr1 = addr3 = ap_mac_addr; + + if (AH_PRIVATE(ah)->ah_curchan->channel_flags & CHANNEL_CCK) { + transmit_rate = 0x1B; /* CCK_1M */ + } else { + transmit_rate = 0xB; /* OFDM_6M */ + } + + /* Set the Transmit Buffer. */ + ctl[0] = (frame_len | (tpc << 16)); + ctl[1] = 0; + ctl[2] = (0x7 << 16); /* tx_tries0 */ + ctl[3] = transmit_rate; + ctl[4] = 0; + ctl[7] = ahp->ah_tx_chainmask << 2; + + for (i = 0; i < 13; i++) { + OS_REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); + } + + data_word[0] = + (frame_type << 2) | + (sub_type << 4) | + (to_ds << 8) | + (duration_id << 16); + data_word[1] = (((u_int32_t)addr1[3] << 24) | ((u_int32_t)addr1[2] << 16) | + ((u_int32_t)addr1[1]) << 8 | ((u_int32_t)addr1[0])); + data_word[2] = (((u_int32_t)addr2[1] << 24) | ((u_int32_t)addr2[0] << 16) | + ((u_int32_t)addr1[5]) << 8 | ((u_int32_t)addr1[4])); + data_word[3] = (((u_int32_t)addr2[5] << 24) | ((u_int32_t)addr2[4] << 16) | + ((u_int32_t)addr2[3]) << 8 | ((u_int32_t)addr2[2])); + data_word[4] = (((u_int32_t)addr3[3] << 24) | ((u_int32_t)addr3[2] << 16) | + ((u_int32_t)addr3[1]) << 8 | (u_int32_t)addr3[0]); + data_word[5] = (((u_int32_t)addr3[5]) << 8 | ((u_int32_t)addr3[4])); + + if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { + /* Jupiter 2.0 has an extra descriptor word (Time based + * discard) compared to other chips */ + OS_REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + 12 * 4), 0); + wow_ka_dataword0 = AR_WOW_TXBUF(13); + } + else { + wow_ka_dataword0 = AR_WOW_TXBUF(12); + } + + for (i = 0; i < NUM_KA_DATA_WORDS; i++) { + OS_REG_WRITE(ah, (wow_ka_dataword0 + i * 4), data_word[i]); + } + + return AH_TRUE; +} + +/* TBD: Should querying hal for hardware capability */ +#define MAX_PATTERN_SIZE 256 +#define MAX_PATTERN_MASK_SIZE 32 +#define MAX_NUM_USER_PATTERN 6 /* Deducting the disassoc/deauth packets */ + +void +ar9300_wow_apply_pattern( + struct ath_hal *ah, + u_int8_t *p_ath_pattern, + u_int8_t *p_ath_mask, + int32_t pattern_count, + u_int32_t ath_pattern_len) +{ + int i; + u_int32_t reg_pat[] = { + AR_WOW_TB_PATTERN0, + AR_WOW_TB_PATTERN1, + AR_WOW_TB_PATTERN2, + AR_WOW_TB_PATTERN3, + AR_WOW_TB_PATTERN4, + AR_WOW_TB_PATTERN5, + AR_WOW_TB_PATTERN6, + AR_WOW_TB_PATTERN7 + }; + u_int32_t reg_mask[] = { + AR_WOW_TB_MASK0, + AR_WOW_TB_MASK1, + AR_WOW_TB_MASK2, + AR_WOW_TB_MASK3, + AR_WOW_TB_MASK4, + AR_WOW_TB_MASK5, + AR_WOW_TB_MASK6, + AR_WOW_TB_MASK7 + }; + u_int32_t pattern_val; + u_int32_t mask_val; + u_int32_t val; + u_int8_t mask_bit = 0x1; + u_int8_t pattern; + + /* TBD: should check count by querying the hardware capability */ + if (pattern_count >= MAX_NUM_USER_PATTERN) { + return; + } + + pattern = (u_int8_t)OS_REG_READ(ah, AR_WOW_PATTERN_REG); + pattern = pattern | (mask_bit << pattern_count); + OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, pattern); + + /* Set the registers for pattern */ + for (i = 0; i < MAX_PATTERN_SIZE; i += 4) { + pattern_val = (((u_int32_t)p_ath_pattern[i + 0]) | + ((u_int32_t)p_ath_pattern[i + 1] << 8) | + ((u_int32_t)p_ath_pattern[i + 2] << 16) | + ((u_int32_t)p_ath_pattern[i + 3] << 24)); + OS_REG_WRITE(ah, (reg_pat[pattern_count] + i), pattern_val); + } + + /* Set the registers for mask */ + for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) { + mask_val = (((u_int32_t)p_ath_mask[i + 0]) | + ((u_int32_t)p_ath_mask[i + 1] << 8) | + ((u_int32_t)p_ath_mask[i + 2] << 16) | + ((u_int32_t)p_ath_mask[i + 3] << 24)); + OS_REG_WRITE(ah, (reg_mask[pattern_count] + i), mask_val); + } + + /* XXX */ + /* Set the pattern length to be matched */ + if (pattern_count < 4) { + /* Pattern 0-3 uses AR_WOW_LENGTH1_REG register */ + val = OS_REG_READ(ah, AR_WOW_LENGTH1_REG); + val = ((val & (~AR_WOW_LENGTH1_MASK(pattern_count))) | + ((ath_pattern_len & AR_WOW_LENGTH_MAX) << + AR_WOW_LENGTH1_SHIFT(pattern_count))); + OS_REG_WRITE(ah, AR_WOW_LENGTH1_REG, val); + } else { + /* Pattern 4-7 uses AR_WOW_LENGTH2_REG register */ + val = OS_REG_READ(ah, AR_WOW_LENGTH2_REG); + val = ((val & (~AR_WOW_LENGTH2_MASK(pattern_count))) | + ((ath_pattern_len & AR_WOW_LENGTH_MAX) << + AR_WOW_LENGTH2_SHIFT(pattern_count))); + OS_REG_WRITE(ah, AR_WOW_LENGTH2_REG, val); + } + + AH_PRIVATE(ah)->ah_wow_event_mask |= + (1 << (pattern_count + AR_WOW_PATTERN_FOUND_SHIFT)); + + return; +} + +HAL_BOOL +ar9300_set_power_mode_wow_sleep(struct ath_hal *ah) +{ + OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); + + OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ + if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) { + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: dma failed to stop in 10ms\n" + "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", __func__, + OS_REG_READ(ah, AR_CR), OS_REG_READ(ah, AR_DIAG_SW)); + return AH_FALSE; + } else { +#if 0 + OS_REG_WRITE(ah, AR_RXDP, 0x0); +#endif + + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "%s: TODO How to disable RXDP!!\n", __func__); + +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) { + OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); + } +#endif + OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); + + return AH_TRUE; + } +} + + +HAL_BOOL +ar9300_wow_enable( + struct ath_hal *ah, + u_int32_t pattern_enable, + u_int32_t timeout_in_seconds, + int clearbssid, + HAL_BOOL offloadEnable) +{ + uint32_t init_val, val, rval = 0; + const int ka_delay = 4; /* Delay of 4 millisec between two keep_alive's */ + uint32_t wow_event_mask; +#if ATH_WOW_OFFLOAD + uint32_t wow_feature_enable = + //AR_WOW_OFFLOAD_ENA_GTK | + //AR_WOW_OFFLOAD_ENA_ARP_OFFLOAD | + //AR_WOW_OFFLOAD_ENA_NS_OFFLOAD | + //AR_WOW_OFFLOAD_ENA_ACER_MAGIC | + //AR_WOW_OFFLOAD_ENA_STD_MAGIC | + //AR_WOW_OFFLOAD_ENA_4WAY_WAKE | + //AR_WOW_OFFLOAD_ENA_SWKA | + //AR_WOW_OFFLOAD_ENA_BT_SLEEP | + AR_WOW_OFFLOAD_ENA_SW_NULL; +#endif + + /* + * ah_wow_event_mask is a mask to the AR_WOW_PATTERN_REG register to + * indicate which WOW events that we have enabled. The WOW Events are + * from the pattern_enable in this function and pattern_count of + * ar9300_wow_apply_pattern() + */ + wow_event_mask = AH_PRIVATE(ah)->ah_wow_event_mask; + + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "%s: offload: %d, pattern: %08x, event_mask: %08x\n", + __func__, offloadEnable, pattern_enable, wow_event_mask); + + /* + * Untie Power-On-Reset from the PCI-E Reset. When we are in WOW sleep, + * we do not want the Reset from the PCI-E to disturb our hw state. + */ + if (AH_PRIVATE(ah)->ah_is_pci_express == AH_TRUE) { + + u_int32_t wa_reg_val; + /* + * We need to untie the internal POR (power-on-reset) to the external + * PCI-E reset. We also need to tie the PCI-E Phy reset to the PCI-E + * reset. + */ + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "%s: Untie POR and PCIE reset\n", __func__); + wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); + wa_reg_val = wa_reg_val & ~(AR_WA_UNTIE_RESET_EN); + wa_reg_val = wa_reg_val | AR_WA_RESET_EN | AR_WA_POR_SHORT; + /* + * This bit is to bypass the EEPROM/OTP state machine, (by clearing its + * busy state while PCIE_rst is asserted), to allow BT embedded CPU + * be able to access WLAN registers. Otherwise the eCPU access will be + * stalled as eeprom_sm is held in busy state. + * + * EV91928 is that when this bit is set, after host wakeup and PCIE_rst + * deasserted, PCIE configuration registers will be reset and DeviceID + * SubsystemID etc. registers will be different from values before + * entering sleep. This will cause Windows to detect a device removal. + * + * For HW WOW, this bit should keep as cleared. + */ + if (offloadEnable) { + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "%s: Set AR_WA.13 COLD_RESET_OVERRIDE\n", __func__); + wa_reg_val = wa_reg_val | AR_WA_COLD_RESET_OVERRIDE; + +#if ATH_WOW_OFFLOAD + if (AR_SREV_JUPITER(ah)) { + wa_reg_val = wa_reg_val | AR_WA_D3_TO_L1_DISABLE; + } +#endif + } + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), wa_reg_val); + } + + /* + * Set the power states appropriately and enable pme. + */ + val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)); + val |= + AR_PMCTRL_HOST_PME_EN | + AR_PMCTRL_PWR_PM_CTRL_ENA | + AR_PMCTRL_AUX_PWR_DET; + + /* + * Set and clear WOW_PME_CLEAR registers for the chip to generate next + * wow signal. + */ + val |= AR_PMCTRL_WOW_PME_CLR; + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val); + val &= ~AR_PMCTRL_WOW_PME_CLR; + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val); + + /* + * Setup for for: + * - beacon misses + * - magic pattern + * - keep alive timeout + * - pattern matching + */ + + /* + * Program some default values for keep-alives, beacon misses, etc. + */ + init_val = OS_REG_READ(ah, AR_WOW_PATTERN_REG); + val = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF) | init_val; + OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, val); + rval = OS_REG_READ(ah, AR_WOW_PATTERN_REG); + + val = + AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) | + AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) | + AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT); + OS_REG_WRITE(ah, AR_WOW_COUNT_REG, val); + rval = OS_REG_READ(ah, AR_WOW_COUNT_REG); + + if (pattern_enable & AH_WOW_BEACON_MISS) { + val = AR_WOW_BEACON_TIMO; + } else { + /* We are not using the beacon miss. Program a large value. */ + val = AR_WOW_BEACON_TIMO_MAX; + } + OS_REG_WRITE(ah, AR_WOW_BCN_TIMO_REG, val); + rval = OS_REG_READ(ah, AR_WOW_BCN_TIMO_REG); + + /* + * Keep Alive Timo in ms. + */ + if (pattern_enable == 0) { + val = AR_WOW_KEEP_ALIVE_NEVER; + } else { + val = AH_PRIVATE(ah)->ah_config.ath_hal_keep_alive_timeout * 32; + } + OS_REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO_REG, val); + rval = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_TIMO_REG); + + /* + * Keep Alive delay in us. + */ + val = ka_delay * 1000; + OS_REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY_REG, val); + rval = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_DELAY_REG); + + /* + * Create keep_alive Pattern to respond to beacons. + */ + ar9300_wow_create_keep_alive_pattern(ah); + + /* + * Configure Mac Wow Registers. + */ + + val = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_REG); + + /* + * Send keep alive timeouts anyway. + */ + val &= ~AR_WOW_KEEP_ALIVE_AUTO_DIS; + + if (pattern_enable & AH_WOW_LINK_CHANGE) { + val &= ~ AR_WOW_KEEP_ALIVE_FAIL_DIS; + wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL; + } else { + val |= AR_WOW_KEEP_ALIVE_FAIL_DIS; + } +#if ATH_WOW_OFFLOAD + if (offloadEnable) { + /* Don't enable KA frames yet. BT CPU is not + * yet ready. */ + } + else +#endif /* ATH_WOW_OFFLOAD */ + { + OS_REG_WRITE(ah, AR_WOW_KEEP_ALIVE_REG, val); + val = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_REG); + } + + + /* + * We are relying on a bmiss failure. Ensure we have enough + * threshold to prevent AH_FALSE positives. + */ + OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR, + AR_WOW_BMISSTHRESHOLD); + + val = OS_REG_READ(ah, AR_WOW_BCN_EN_REG); + if (pattern_enable & AH_WOW_BEACON_MISS) { + val |= AR_WOW_BEACON_FAIL_EN; + wow_event_mask |= AR_WOW_BEACON_FAIL; + } else { + val &= ~AR_WOW_BEACON_FAIL_EN; + } + OS_REG_WRITE(ah, AR_WOW_BCN_EN_REG, val); + val = OS_REG_READ(ah, AR_WOW_BCN_EN_REG); + + /* + * Enable the magic packet registers. + */ + val = OS_REG_READ(ah, AR_WOW_PATTERN_REG); + if ((pattern_enable & AH_WOW_MAGIC_PATTERN_EN) +#if ATH_WOW_OFFLOAD + || (pattern_enable & AH_WOW_ACER_MAGIC_EN) +#endif + ) + { + val |= AR_WOW_MAGIC_EN; + wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND; + } else { + val &= ~AR_WOW_MAGIC_EN; + } + val |= AR_WOW_MAC_INTR_EN; + OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, val); + val = OS_REG_READ(ah, AR_WOW_PATTERN_REG); + +#if ATH_WOW_OFFLOAD + if (HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_FORCE_BT_SLEEP)) { + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_BT_SLEEP; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - BT SLEEP\n"); + } else { + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_BT_SLEEP; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - BT SLEEP\n"); + } + + if (HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SW_NULL_DISABLE)) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - SW NULL\n"); + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_SW_NULL; + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - SW NULL\n"); + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_SW_NULL; + } + + if (HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_DEVID_SWAR_DISABLE)) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - DevID SWAR\n"); + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_DEVID_SWAR; + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - DevID SWAR\n"); + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_DEVID_SWAR; + } + + if (pattern_enable & AH_WOW_ACER_KEEP_ALIVE_EN) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Acer SWKA\n"); + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_SWKA; + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Acer SWKA\n"); + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_SWKA; + } + + if (pattern_enable & AH_WOW_ACER_MAGIC_EN) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Standard Magic\n"); + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_STD_MAGIC; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Acer Magic\n"); + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_ACER_MAGIC; + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Standard Magic\n"); + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_STD_MAGIC; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Acer Magic\n"); + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_ACER_MAGIC; + } + + if ((pattern_enable & AH_WOW_4WAY_HANDSHAKE_EN) || + HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_FORCE_4WAY_HS_WAKE)) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - 4Way Handshake\n"); + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_4WAY_WAKE; + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - 4Way Handshake\n"); + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_4WAY_WAKE; + } + + if((pattern_enable & AH_WOW_AP_ASSOCIATION_LOST_EN) || + HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_FORCE_AP_LOSS_WAKE)) + { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - AP loss wake\n"); + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_AP_LOSS_WAKE; + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - AP loss wake\n"); + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_AP_LOSS_WAKE; + } + + if((pattern_enable & AH_WOW_GTK_HANDSHAKE_ERROR_EN) || + HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_FORCE_GTK_ERR_WAKE)) + { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - GTK error wake\n"); + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_GTK_ERROR_WAKE; + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - GTK error wake\n"); + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_GTK_ERROR_WAKE; + } + + if (pattern_enable & AH_WOW_GTK_OFFLOAD_EN) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - GTK offload\n"); + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_GTK; + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - GTK offload\n"); + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_GTK; + } + + if (pattern_enable & AH_WOW_ARP_OFFLOAD_EN) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - ARP offload\n"); + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_ARP_OFFLOAD; + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - ARP offload\n"); + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_ARP_OFFLOAD; + } + + if (pattern_enable & AH_WOW_NS_OFFLOAD_EN) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - NS offload\n"); + wow_feature_enable |= AR_WOW_OFFLOAD_ENA_NS_OFFLOAD; + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - NS offload\n"); + wow_feature_enable &= ~AR_WOW_OFFLOAD_ENA_NS_OFFLOAD; + } + +#endif /* ATH_WOW_OFFLOAD */ + + /* For Kite and later version of the chips + * enable wow pattern match for packets less than + * 256 bytes for all patterns. + */ + /* XXX */ + OS_REG_WRITE( + ah, AR_WOW_PATTERN_MATCH_LT_256B_REG, AR_WOW_PATTERN_SUPPORTED); + + /* + * Set the power states appropriately and enable PME. + */ + val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)); + val |= + AR_PMCTRL_PWR_STATE_D1D3 | + AR_PMCTRL_HOST_PME_EN | + AR_PMCTRL_PWR_PM_CTRL_ENA; + val &= ~AR_PCIE_PM_CTRL_ENA; + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val); + + /* Wake on Timer Interrupt. Test mode only. Used in Manufacturing line. */ + if (timeout_in_seconds) { + /* convert Timeout to u_secs */ + OS_REG_WRITE(ah, AR_NEXT_NDP_TIMER, + OS_REG_READ(ah, AR_TSF_L32) + timeout_in_seconds * 1000000 ); + /* timer_period = 30 seconds always */ + OS_REG_WRITE(ah, AR_NDP_PERIOD, 30 * 1000000); + OS_REG_WRITE(ah, AR_TIMER_MODE, OS_REG_READ(ah, AR_TIMER_MODE) | 0x80); + OS_REG_WRITE(ah, AR_IMR_S5, OS_REG_READ(ah, AR_IMR_S5) | 0x80); + OS_REG_WRITE(ah, AR_IMR, OS_REG_READ(ah, AR_IMR) | AR_IMR_GENTMR); + if (clearbssid) { + OS_REG_WRITE(ah, AR_BSS_ID0, 0); + OS_REG_WRITE(ah, AR_BSS_ID1, 0); + } + } + + /* Enable Seq# generation when asleep. */ + OS_REG_WRITE(ah, AR_STA_ID1, + OS_REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_PRESERVE_SEQNUM); + + + AH_PRIVATE(ah)->ah_wow_event_mask = wow_event_mask; + +#if ATH_WOW_OFFLOAD + if (offloadEnable) { + /* Force MAC awake before entering SW WoW mode */ + OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) { + OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); + } +#endif + + OS_REG_WRITE(ah, AR_WOW_OFFLOAD_COMMAND_JUPITER, wow_feature_enable); + OS_REG_WRITE(ah, AR_WOW_OFFLOAD_STATUS_JUPITER, 0x0); + if (wow_feature_enable & AR_WOW_OFFLOAD_ENA_SW_NULL) { + OS_REG_WRITE(ah, AR_WOW_SW_NULL_PARAMETER, + ((1000) | + (4 << AR_WOW_SW_NULL_SHORT_PERIOD_MASK_S))); + } + + if (wow_feature_enable & AR_WOW_OFFLOAD_ENA_DEVID_SWAR) { + ar9300_wowoffload_download_devid_swar(ah); + } + + ar9300_wow_offload_download_hal_params(ah); + ar9300_wow_offload_handshake(ah, pattern_enable); + AH9300(ah)->ah_chip_full_sleep = AH_FALSE; + + //OS_REG_SET_BIT(ah, AR_SW_WOW_CONTROL, AR_HW_WOW_DISABLE); + } + else +#endif /* ATH_WOW_OFFLOAD */ + { +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) { + OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); + } +#endif + ar9300_set_power_mode_wow_sleep(ah); + AH9300(ah)->ah_chip_full_sleep = AH_TRUE; + } + + return (AH_TRUE); +} + +u_int32_t +//ar9300_wow_wake_up(struct ath_hal *ah, u_int8_t *chipPatternBytes) +ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnabled) +{ + uint32_t wow_status = 0; + uint32_t val = 0, rval; + + OS_REG_CLR_BIT(ah, AR_SW_WOW_CONTROL, AR_HW_WOW_DISABLE); + OS_REG_CLR_BIT(ah, AR_SW_WOW_CONTROL, AR_SW_WOW_ENABLE); + +#if ATH_WOW_OFFLOAD + /* If WoW was offloaded to embedded CPU, use the global + * shared register to know the wakeup reason */ + if (offloadEnabled) { + val = OS_REG_READ(ah, AR_EMB_CPU_WOW_STATUS); + if (val) { + if (val & AR_EMB_CPU_WOW_STATUS_MAGIC_PATTERN) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) SW MAGIC_PATTERN\n"); + wow_status |= AH_WOW_MAGIC_PATTERN_EN; + } + if (val & AR_EMB_CPU_WOW_STATUS_PATTERN_MATCH) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) SW USER_PATTERN\n"); + wow_status |= AH_WOW_USER_PATTERN_EN; + } + if (val & AR_EMB_CPU_WOW_STATUS_KEEP_ALIVE_FAIL) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) SW KEEP_ALIVE_FAIL\n"); + wow_status |= AH_WOW_LINK_CHANGE; + } + if (val & AR_EMB_CPU_WOW_STATUS_BEACON_MISS) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) SW BEACON_FAIL\n"); + wow_status |= AH_WOW_BEACON_MISS; + } + } + + /* Clear status and mask registers */ + OS_REG_WRITE(ah, AR_EMB_CPU_WOW_STATUS, 0x0); + OS_REG_WRITE(ah, AR_EMB_CPU_WOW_ENABLE, 0); + OS_REG_WRITE(ah, AR_MBOX_CTRL_STATUS, 0); + + } + else +#endif /* ATH_WOW_OFFLOAD */ + { + /* + * Read the WOW Status register to know the wakeup reason. + */ + rval = OS_REG_READ(ah, AR_WOW_PATTERN_REG); + val = AR_WOW_STATUS(rval); + + /* + * Mask only the WOW events that we have enabled. + * Sometimes we have spurious WOW events from the AR_WOW_PATTERN_REG + * register. This mask will clean it up. + */ + val &= AH_PRIVATE(ah)->ah_wow_event_mask; + + if (val) { + if (val & AR_WOW_MAGIC_PAT_FOUND) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) HW MAGIC_PATTERN\n"); + wow_status |= AH_WOW_MAGIC_PATTERN_EN; + } + if (AR_WOW_PATTERN_FOUND(val)) { + //int i, offset; + //offset = OS_REG_READ(ah, AR_WOW_RXBUF_START_ADDR); + //// Read matched pattern for wake packet detection indication. + //for( i = 0; i< MAX_PATTERN_SIZE/4; i+=4) + //{ + // // RX FIFO is only 8K wrapping. + // if(offset >= 8 * 1024 / 4) offset = 0; + // *(u_int32_t*)(chipPatternBytes + i) = OS_REG_READ( ah,offset ); + // offset++; + //} + wow_status |= AH_WOW_USER_PATTERN_EN; + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) HW USER_PATTERN\n"); + } + if (val & AR_WOW_KEEP_ALIVE_FAIL) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) HW KEEP_ALIVE_FAIL\n"); + wow_status |= AH_WOW_LINK_CHANGE; + } + if (val & AR_WOW_BEACON_FAIL) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) HW BEACON_FAIL\n"); + wow_status |= AH_WOW_BEACON_MISS; + } + } + } + + /* + * Set and clear WOW_PME_CLEAR registers for the chip to generate next + * wow signal. + * Disable D3 before accessing other registers ? + */ + val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)); + /* Check the bit value 0x01000000 (7-10)? */ + val &= ~AR_PMCTRL_PWR_STATE_D1D3; + val |= AR_PMCTRL_WOW_PME_CLR; + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val); + + /* + * Clear all events. + */ + OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, + AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG))); + + //HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + // "%s: Skip PCIE WA programming\n", __func__); +#if 0 + /* + * Tie reset register. + * FIXME: Per David Quan not tieing it back might have some repurcussions. + */ + /* XXX */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), OS_REG_READ(ah, AR_WA) | + AR_WA_UNTIE_RESET_EN | AR_WA_POR_SHORT | AR_WA_RESET_EN); +#endif + + /* Restore the Beacon Threshold to init value */ + OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR, INIT_RSSI_THR); + + /* + * Restore the way the PCI-E Reset, Power-On-Reset, external PCIE_POR_SHORT + * pins are tied to its original value. Previously just before WOW sleep, + * we untie the PCI-E Reset to our Chip's Power On Reset so that + * any PCI-E reset from the bus will not reset our chip. + */ + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "%s: restore AR_WA\n", __func__); + if (AH_PRIVATE(ah)->ah_is_pci_express == AH_TRUE) { + ar9300_config_pci_power_save(ah, 0, 0); + } + + AH_PRIVATE(ah)->ah_wow_event_mask = 0; + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "(WOW) wow_status=%08x\n", wow_status); + + return (wow_status); +} + +void +ar9300_wow_set_gpio_reset_low(struct ath_hal *ah) +{ + uint32_t val; + + val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT)); + val |= (1 << (2 * 2)); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), val); + val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT)); + /* val = OS_REG_READ(ah,AR_GPIO_IN_OUT ); */ +} +#endif /* ATH_WOW */ + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_radar.c b/hal/ar9300/ar9300_radar.c new file mode 100644 index 000000000000..b2f5663d3ddc --- /dev/null +++ b/hal/ar9300/ar9300_radar.c @@ -0,0 +1,593 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_desc.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300phy.h" +#include "ar9300/ar9300reg.h" + +/* + * Default 5413/9300 radar phy parameters + * Values adjusted to fix EV76432/EV76320 + */ +#define AR9300_DFS_FIRPWR -28 +#define AR9300_DFS_RRSSI 0 +#define AR9300_DFS_HEIGHT 10 +#define AR9300_DFS_PRSSI 6 +#define AR9300_DFS_INBAND 8 +#define AR9300_DFS_RELPWR 8 +#define AR9300_DFS_RELSTEP 12 +#define AR9300_DFS_MAXLEN 255 +#define AR9300_DFS_PRSSI_CAC 10 + +#ifdef ATH_SUPPORT_DFS + +/* + * make sure that value matches value in ar9300_osprey_2p2_mac_core[][2] + * for register 0x1040 to 0x104c +*/ +#define AR9300_DEFAULT_DIFS 0x002ffc0f +#define AR9300_FCC_RADARS_FCC_OFFSET 4 + +struct dfs_pulse ar9300_etsi_radars[] = { + + /* for short pulses, RSSI threshold should be smaller than + * Kquick-drop. The chip has only one chance to drop the gain which + * will be reported as the estimated RSSI */ + + /* TYPE staggered pulse */ + /* 0.8-2us, 2-3 bursts,300-400 PRF, 10 pulses each */ + {30, 2, 300, 400, 2, 30, 3, 0, 5, 15, 0, 0, 1, 31}, /* Type 5*/ + /* 0.8-2us, 2-3 bursts, 400-1200 PRF, 15 pulses each */ + {30, 2, 400, 1200, 2, 30, 7, 0, 5, 15, 0, 0, 0, 32}, /* Type 6 */ + + /* constant PRF based */ + /* 0.8-5us, 200 300 PRF, 10 pulses */ + {10, 5, 200, 400, 0, 24, 5, 0, 8, 15, 0, 0, 2, 33}, /* Type 1 */ + {10, 5, 400, 600, 0, 24, 5, 0, 8, 15, 0, 0, 2, 37}, /* Type 1 */ + {10, 5, 600, 800, 0, 24, 5, 0, 8, 15, 0, 0, 2, 38}, /* Type 1 */ + {10, 5, 800, 1000, 0, 24, 5, 0, 8, 15, 0, 0, 2, 39}, /* Type 1 */ +// {10, 5, 200, 1000, 0, 24, 5, 0, 8, 15, 0, 0, 2, 33}, + + /* 0.8-15us, 200-1600 PRF, 15 pulses */ + {15, 15, 200, 1600, 0, 24, 8, 0, 18, 24, 0, 0, 0, 34}, /* Type 2 */ + + /* 0.8-15us, 2300-4000 PRF, 25 pulses*/ + {25, 15, 2300, 4000, 0, 24, 10, 0, 18, 24, 0, 0, 0, 35}, /* Type 3 */ + + /* 20-30us, 2000-4000 PRF, 20 pulses*/ + {20, 30, 2000, 4000, 0, 24, 8, 19, 33, 24, 0, 0, 0, 36}, /* Type 4 */ +}; + + +/* The following are for FCC Bin 1-4 pulses */ +struct dfs_pulse ar9300_fcc_radars[] = { + + /* following two filters are specific to Japan/MKK4 */ +// {18, 1, 720, 720, 1, 6, 6, 0, 1, 18, 0, 3, 0, 17}, // 1389 +/- 6 us +// {18, 4, 250, 250, 1, 10, 5, 1, 6, 18, 0, 3, 0, 18}, // 4000 +/- 6 us +// {18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 0, 19}, // 3846 +/- 7 us + {18, 1, 720, 720, 0, 6, 6, 0, 1, 18, 0, 3, 0, 17}, // 1389 +/- 6 us + {18, 4, 250, 250, 0, 10, 5, 1, 6, 18, 0, 3, 0, 18}, // 4000 +/- 6 us + {18, 5, 260, 260, 0, 10, 6, 1, 6, 18, 0, 3, 1, 19}, // 3846 +/- 7 us +// {18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 1, 20}, // 3846 +/- 7 us + + {18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 1, 20}, // 3846 +/- 7 us + + + /* following filters are common to both FCC and JAPAN */ + + // FCC TYPE 1 + // {18, 1, 325, 1930, 0, 6, 7, 0, 1, 18, 0, 3, 0, 0}, // 518 to 3066 + {18, 1, 700, 700, 0, 6, 5, 0, 1, 18, 0, 3, 1, 8}, + {18, 1, 350, 350, 0, 6, 5, 0, 1, 18, 0, 3, 0, 0}, + + + // FCC TYPE 6 + // {9, 1, 3003, 3003, 1, 7, 5, 0, 1, 18, 0, 0, 0, 1}, // 333 +/- 7 us + //{9, 1, 3003, 3003, 1, 7, 5, 0, 1, 18, 0, 0, 0, 1}, + {9, 1, 3003, 3003, 0, 7, 5, 0, 1, 18, 0, 0, 1, 1}, + + // FCC TYPE 2 + {23, 5, 4347, 6666, 0, 18, 11, 0, 7, 22, 0, 3, 0, 2}, + + // FCC TYPE 3 + {18, 10, 2000, 5000, 0, 23, 8, 6, 13, 22, 0, 3, 0, 5}, + + // FCC TYPE 4 + {16, 15, 2000, 5000, 0, 25, 7, 11, 23, 22, 0, 3, 0, 11}, + +}; + +struct dfs_bin5pulse ar9300_bin5pulses[] = { + {2, 28, 105, 12, 22, 5}, +}; + + +/* + * Find the internal HAL channel corresponding to the + * public HAL channel specified in c + */ + +static HAL_CHANNEL_INTERNAL * +getchannel(struct ath_hal *ah, const HAL_CHANNEL *c) +{ +#define CHAN_FLAGS (CHANNEL_ALL | CHANNEL_HALF | CHANNEL_QUARTER) + HAL_CHANNEL_INTERNAL *base, *cc; + int flags = c->channel_flags & CHAN_FLAGS; + int n, lim; + + /* + * Check current channel to avoid the lookup. + */ + cc = AH_PRIVATE(ah)->ah_curchan; + if (cc != AH_NULL && cc->channel == c->channel && + (cc->channel_flags & CHAN_FLAGS) == flags) { + return cc; + } + + /* binary search based on known sorting order */ + base = AH_TABLES(ah)->ah_channels; + n = AH_PRIVATE(ah)->ah_nchan; + /* binary search based on known sorting order */ + for (lim = n; lim != 0; lim >>= 1) { + int d; + cc = &base[lim >> 1]; + d = c->channel - cc->channel; + if (d == 0) { + if ((cc->channel_flags & CHAN_FLAGS) == flags) { + return cc; + } + d = flags - (cc->channel_flags & CHAN_FLAGS); + } + HALDEBUG(ah, HAL_DEBUG_DFS, "%s: channel %u/0x%x d %d\n", __func__, + cc->channel, cc->channel_flags, d); + if (d > 0) { + base = cc + 1; + lim--; + } + } + HALDEBUG(ah, HAL_DEBUG_DFS, "%s: no match for %u/0x%x\n", + __func__, c->channel, c->channel_flags); + return AH_NULL; +#undef CHAN_FLAGS +} + +/* + * Check the internal channel list to see if the desired channel + * is ok to release from the NOL. If not, then do nothing. If so, + * mark the channel as clear and reset the internal tsf time + */ +void +ar9300_check_dfs(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + HAL_CHANNEL_INTERNAL *ichan = AH_NULL; + + ichan = getchannel(ah, chan); + if (ichan == AH_NULL) { + return; + } + if (!(ichan->priv_flags & CHANNEL_INTERFERENCE)) { + return; + } + + ichan->priv_flags &= ~CHANNEL_INTERFERENCE; + ichan->dfs_tsf = 0; +} + +/* + * This function marks the channel as having found a dfs event + * It also marks the end time that the dfs event should be cleared + * If the channel is already marked, then tsf end time can only + * be increased + */ +void +ar9300_dfs_found(struct ath_hal *ah, HAL_CHANNEL *chan, u_int64_t nol_time) +{ + HAL_CHANNEL_INTERNAL *ichan; + + ichan = getchannel(ah, chan); + if (ichan == AH_NULL) { + return; + } + if (!(ichan->priv_flags & CHANNEL_INTERFERENCE)) { + ichan->dfs_tsf = ar9300_get_tsf64(ah); + } + ichan->dfs_tsf += nol_time; + ichan->priv_flags |= CHANNEL_INTERFERENCE; + chan->priv_flags |= CHANNEL_INTERFERENCE; +} + +/* + * Enable radar detection and set the radar parameters per the + * values in pe + */ +void +ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) +{ + u_int32_t val; + struct ath_hal_private *ahp = AH_PRIVATE(ah); + HAL_CHANNEL_INTERNAL *ichan = ahp->ah_curchan; + struct ath_hal_9300 *ah9300 = AH9300(ah); + int reg_writes = 0; + + val = OS_REG_READ(ah, AR_PHY_RADAR_0); + val |= AR_PHY_RADAR_0_FFT_ENA | AR_PHY_RADAR_0_ENA; + if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) { + val &= ~AR_PHY_RADAR_0_FIRPWR; + val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR); + } + if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) { + val &= ~AR_PHY_RADAR_0_RRSSI; + val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI); + } + if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) { + val &= ~AR_PHY_RADAR_0_HEIGHT; + val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT); + } + if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) { + val &= ~AR_PHY_RADAR_0_PRSSI; + if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + if (ah->ah_use_cac_prssi) { + val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI); + } else { + val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI); + } + } else { + val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI); + } + } + if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) { + val &= ~AR_PHY_RADAR_0_INBAND; + val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND); + } + OS_REG_WRITE(ah, AR_PHY_RADAR_0, val); + + val = OS_REG_READ(ah, AR_PHY_RADAR_1); + val |= AR_PHY_RADAR_1_MAX_RRSSI | AR_PHY_RADAR_1_BLOCK_CHECK; + if (pe->pe_maxlen != HAL_PHYERR_PARAM_NOVAL) { + val &= ~AR_PHY_RADAR_1_MAXLEN; + val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN); + } + if (pe->pe_relstep != HAL_PHYERR_PARAM_NOVAL) { + val &= ~AR_PHY_RADAR_1_RELSTEP_THRESH; + val |= SM(pe->pe_relstep, AR_PHY_RADAR_1_RELSTEP_THRESH); + } + if (pe->pe_relpwr != HAL_PHYERR_PARAM_NOVAL) { + val &= ~AR_PHY_RADAR_1_RELPWR_THRESH; + val |= SM(pe->pe_relpwr, AR_PHY_RADAR_1_RELPWR_THRESH); + } + OS_REG_WRITE(ah, AR_PHY_RADAR_1, val); + + if (ath_hal_getcapability(ah, HAL_CAP_EXT_CHAN_DFS, 0, 0) == HAL_OK) { + val = OS_REG_READ(ah, AR_PHY_RADAR_EXT); + if (IS_CHAN_HT40(ichan)) { + /* Enable extension channel radar detection */ + OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val | AR_PHY_RADAR_EXT_ENA); + } else { + /* HT20 mode, disable extension channel radar detect */ + OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val & ~AR_PHY_RADAR_EXT_ENA); + } + } + /* + apply DFS postamble array from INI + column 0 is register ID, column 1 is HT20 value, colum2 is HT40 value + */ + + if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_OSPREY_22(ah) || AR_SREV_SCORPION(ah)) { + REG_WRITE_ARRAY(&ah9300->ah_ini_dfs,IS_CHAN_HT40(ichan)? 2:1, reg_writes); + } +#ifdef ATH_HAL_DFS_CHIRPING_FIX_APH128 + HALDEBUG(ah, HAL_DEBUG_DFS,"DFS change the timing value\n"); + if (AR_SREV_AR9580(ah) && IS_CHAN_HT40(ichan)) { + OS_REG_WRITE(ah, AR_PHY_TIMING6, 0x3140c00a); + } +#endif + +} + +/* + * Get the radar parameter values and return them in the pe + * structure + */ +void +ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) +{ + u_int32_t val, temp; + + val = OS_REG_READ(ah, AR_PHY_RADAR_0); + temp = MS(val, AR_PHY_RADAR_0_FIRPWR); + temp |= ~(AR_PHY_RADAR_0_FIRPWR >> AR_PHY_RADAR_0_FIRPWR_S); + pe->pe_firpwr = temp; + pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI); + pe->pe_height = MS(val, AR_PHY_RADAR_0_HEIGHT); + pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI); + pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND); + + val = OS_REG_READ(ah, AR_PHY_RADAR_1); + + pe->pe_relpwr = MS(val, AR_PHY_RADAR_1_RELPWR_THRESH); + if (val & AR_PHY_RADAR_1_RELPWR_ENA) { + pe->pe_relpwr |= HAL_PHYERR_PARAM_ENABLE; + } + pe->pe_relstep = MS(val, AR_PHY_RADAR_1_RELSTEP_THRESH); + if (val & AR_PHY_RADAR_1_RELSTEP_CHECK) { + pe->pe_relstep |= HAL_PHYERR_PARAM_ENABLE; + } + pe->pe_maxlen = MS(val, AR_PHY_RADAR_1_MAXLEN); +} + +HAL_BOOL +ar9300_radar_wait(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + struct ath_hal_private *ahp = AH_PRIVATE(ah); + + if (!ahp->ah_curchan) { + return AH_TRUE; + } + + /* + * Rely on the upper layers to determine that we have spent + * enough time waiting. + */ + chan->channel = ahp->ah_curchan->channel; + chan->channel_flags = ahp->ah_curchan->channel_flags; + chan->max_reg_tx_power = ahp->ah_curchan->max_reg_tx_power; + + ahp->ah_curchan->priv_flags |= CHANNEL_DFS_CLEAR; + chan->priv_flags = ahp->ah_curchan->priv_flags; + return AH_FALSE; + +} + +struct dfs_pulse * +ar9300_get_dfs_radars( + struct ath_hal *ah, + u_int32_t dfsdomain, + int *numradars, + struct dfs_bin5pulse **bin5pulses, + int *numb5radars, + HAL_PHYERR_PARAM *pe) +{ + struct dfs_pulse *dfs_radars = AH_NULL; + switch (dfsdomain) { + case DFS_FCC_DOMAIN: + dfs_radars = &ar9300_fcc_radars[AR9300_FCC_RADARS_FCC_OFFSET]; + *numradars = + ARRAY_LENGTH(ar9300_fcc_radars) - AR9300_FCC_RADARS_FCC_OFFSET; + *bin5pulses = &ar9300_bin5pulses[0]; + *numb5radars = ARRAY_LENGTH(ar9300_bin5pulses); + HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_FCC_DOMAIN_9300\n", __func__); + break; + case DFS_ETSI_DOMAIN: + dfs_radars = &ar9300_etsi_radars[0]; + *numradars = ARRAY_LENGTH(ar9300_etsi_radars); + *bin5pulses = &ar9300_bin5pulses[0]; + *numb5radars = ARRAY_LENGTH(ar9300_bin5pulses); + HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_ETSI_DOMAIN_9300\n", __func__); + break; + case DFS_MKK4_DOMAIN: + dfs_radars = &ar9300_fcc_radars[0]; + *numradars = ARRAY_LENGTH(ar9300_fcc_radars); + *bin5pulses = &ar9300_bin5pulses[0]; + *numb5radars = ARRAY_LENGTH(ar9300_bin5pulses); + HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_MKK4_DOMAIN_9300\n", __func__); + break; + default: + HALDEBUG(ah, HAL_DEBUG_DFS, "%s: no domain\n", __func__); + return AH_NULL; + } + /* Set the default phy parameters per chip */ + pe->pe_firpwr = AR9300_DFS_FIRPWR; + pe->pe_rrssi = AR9300_DFS_RRSSI; + pe->pe_height = AR9300_DFS_HEIGHT; + pe->pe_prssi = AR9300_DFS_PRSSI; + /* + we have an issue with PRSSI. + For normal operation we use AR9300_DFS_PRSSI, which is set to 6. + Please refer to EV91563, 94164. + However, this causes problem during CAC as no radar is detected + during that period with PRSSI=6. Only PRSSI= 10 seems to fix this. + We use this flag to keep track of change in PRSSI. + */ + + ah->ah_use_cac_prssi = 0; + + pe->pe_inband = AR9300_DFS_INBAND; + pe->pe_relpwr = AR9300_DFS_RELPWR; + pe->pe_relstep = AR9300_DFS_RELSTEP; + pe->pe_maxlen = AR9300_DFS_MAXLEN; + return dfs_radars; +} + +void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val) +{ + if (val == 0) { + /* + * EV 116936: + * Restore the register values with that of the HAL structure. + * Do not assume and overwrite these values to whatever + * is in ar9300_osprey22.ini. + */ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_TX_QUEUE_INFO *qi; + int q; + + ah->ah_fccaifs = 0; + HALDEBUG(ah, HAL_DEBUG_DFS, "%s: restore DIFS \n", __func__); + for (q = 0; q < 4; q++) { + qi = &ahp->ah_txq[q]; + OS_REG_WRITE(ah, AR_DLCL_IFS(q), + SM(qi->tqi_cwmin, AR_D_LCL_IFS_CWMIN) + | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) + | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); + } + } else { + /* + * These are values from George Lai and are specific to + * FCC domain. They are yet to be determined for other domains. + */ + + ah->ah_fccaifs = 1; + HALDEBUG(ah, HAL_DEBUG_DFS, "%s: set DIFS to default\n", __func__); + /*printk("%s: modify DIFS\n", __func__);*/ + + OS_REG_WRITE(ah, AR_DLCL_IFS(0), 0x05fffc0f); + OS_REG_WRITE(ah, AR_DLCL_IFS(1), 0x05f0fc0f); + OS_REG_WRITE(ah, AR_DLCL_IFS(2), 0x05f03c07); + OS_REG_WRITE(ah, AR_DLCL_IFS(3), 0x05f01c03); + } +} + +u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable) +{ + u_int32_t val; + + val = OS_REG_READ(ah, AR_PHY_RADAR_0); + + if (is_enable) { + val |= AR_PHY_RADAR_0_FFT_ENA; + } else { + val &= ~AR_PHY_RADAR_0_FFT_ENA; + } + + OS_REG_WRITE(ah, AR_PHY_RADAR_0, val); + val = OS_REG_READ(ah, AR_PHY_RADAR_0); + return val; +} +/* + function to adjust PRSSI value for CAC problem + +*/ +void +ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start) +{ + u_int32_t val; + + if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + val = OS_REG_READ(ah, AR_PHY_RADAR_0); + if (start) { + val &= ~AR_PHY_RADAR_0_PRSSI; + val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI); + } else { + val &= ~AR_PHY_RADAR_0_PRSSI; + val |= SM(AR9300_DFS_PRSSI, AR_PHY_RADAR_0_PRSSI); + } + OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA); + ah->ah_use_cac_prssi = start; + } +} +#endif /* ATH_SUPPORT_DFS */ + +HAL_CHANNEL * +ar9300_get_extension_channel(struct ath_hal *ah) +{ + struct ath_hal_private *ahp = AH_PRIVATE(ah); + struct ath_hal_private_tables *aht = AH_TABLES(ah); + int i = 0; + + HAL_CHANNEL_INTERNAL *ichan = AH_NULL; + CHAN_CENTERS centers; + + ichan = ahp->ah_curchan; + ar9300_get_channel_centers(ah, ichan, ¢ers); + if (centers.ctl_center == centers.ext_center) { + return AH_NULL; + } + for (i = 0; i < ahp->ah_nchan; i++) { + ichan = &aht->ah_channels[i]; + if (ichan->channel == centers.ext_center) { + return (HAL_CHANNEL*)ichan; + } + } + return AH_NULL; +} + + +HAL_BOOL +ar9300_is_fast_clock_enabled(struct ath_hal *ah) +{ + struct ath_hal_private *ahp = AH_PRIVATE(ah); + + if (IS_5GHZ_FAST_CLOCK_EN(ah, ahp->ah_curchan)) { + return AH_TRUE; + } + return AH_FALSE; +} + +HAL_BOOL +ar9300_handle_radar_bb_panic(struct ath_hal *ah) +{ + u_int32_t status; + u_int32_t val; +#ifdef AH_DEBUG + struct ath_hal_9300 *ahp = AH9300(ah); +#endif + + status = AH_PRIVATE(ah)->ah_bb_panic_last_status; + + if ( status == 0x04000539 ) { + /* recover from this BB panic without reset*/ + /* set AR9300_DFS_FIRPWR to -1 */ + val = OS_REG_READ(ah, AR_PHY_RADAR_0); + val &= (~AR_PHY_RADAR_0_FIRPWR); + val |= SM( 0x7f, AR_PHY_RADAR_0_FIRPWR); + OS_REG_WRITE(ah, AR_PHY_RADAR_0, val); + OS_DELAY(1); + /* set AR9300_DFS_FIRPWR to its default value */ + val = OS_REG_READ(ah, AR_PHY_RADAR_0); + val &= ~AR_PHY_RADAR_0_FIRPWR; + val |= SM( AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR); + OS_REG_WRITE(ah, AR_PHY_RADAR_0, val); + return AH_TRUE; + } else if (status == 0x0400000a) { + /* EV 92527 : reset required if we see this signature */ + HALDEBUG(ah, HAL_DEBUG_DFS, "%s: BB Panic -- 0x0400000a\n", __func__); + return AH_FALSE; + } else if (status == 0x1300000a) { + /* EV92527: we do not need a reset if we see this signature */ + HALDEBUG(ah, HAL_DEBUG_DFS, "%s: BB Panic -- 0x1300000a\n", __func__); + return AH_TRUE; + } else if (AR_SREV_WASP(ah) && (status == 0x04000409)) { + return AH_TRUE; + } else { + if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK && + (status & 0xff00000f) == 0x04000009 && + status != 0x04000409 && + status != 0x04000b09 && + status != 0x04000e09 && + (status & 0x0000ff00)) + { + /* disable RIFS Rx */ +#ifdef AH_DEBUG + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: BB status=0x%08x rifs=%d - disable\n", + __func__, status, ahp->ah_rifs_enabled); +#endif + ar9300_set_rifs_delay(ah, AH_FALSE); + } + return AH_FALSE; + } +} + +#endif diff --git a/hal/ar9300/ar9300_radio.c b/hal/ar9300/ar9300_radio.c new file mode 100644 index 000000000000..ada803a5fff7 --- /dev/null +++ b/hal/ar9300/ar9300_radio.c @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300phy.h" + +/* chansel table, used by Hornet and Poseidon */ +static const u_int32_t ar9300_chansel_xtal_25M[] = { + 0x101479e, /* Freq 2412 - (128 << 17) + 83870 */ + 0x101d027, /* Freq 2417 - (128 << 17) + 118823 */ + 0x10258af, /* Freq 2422 - (129 << 17) + 22703 */ + 0x102e138, /* Freq 2427 - (129 << 17) + 57656 */ + 0x10369c0, /* Freq 2432 - (129 << 17) + 92608 */ + 0x103f249, /* Freq 2437 - (129 << 17) + 127561 */ + 0x1047ad1, /* Freq 2442 - (130 << 17) + 31441 */ + 0x105035a, /* Freq 2447 - (130 << 17) + 66394 */ + 0x1058be2, /* Freq 2452 - (130 << 17) + 101346 */ + 0x106146b, /* Freq 2457 - (131 << 17) + 5227 */ + 0x1069cf3, /* Freq 2462 - (131 << 17) + 40179 */ + 0x107257c, /* Freq 2467 - (131 << 17) + 75132 */ + 0x107ae04, /* Freq 2472 - (131 << 17) + 110084 */ + 0x108f5b2, /* Freq 2484 - (132 << 17) + 62898 */ +}; + +static const u_int32_t ar9300_chansel_xtal_40M[] = { + 0xa0ccbe, /* Freq 2412 - (80 << 17) + 52414 */ + 0xa12213, /* Freq 2417 - (80 << 17) + 74259 */ + 0xa17769, /* Freq 2422 - (80 << 17) + 96105 */ + 0xa1ccbe, /* Freq 2427 - (80 << 17) + 117950 */ + 0xa22213, /* Freq 2432 - (81 << 17) + 8723 */ + 0xa27769, /* Freq 2437 - (81 << 17) + 30569 */ + 0xa2ccbe, /* Freq 2442 - (81 << 17) + 52414 */ + 0xa32213, /* Freq 2447 - (81 << 17) + 74259 */ + 0xa37769, /* Freq 2452 - (81 << 17) + 96105 */ + 0xa3ccbe, /* Freq 2457 - (81 << 17) + 117950 */ + 0xa42213, /* Freq 2462 - (82 << 17) + 8723 */ + 0xa47769, /* Freq 2467 - (82 << 17) + 30569 */ + 0xa4ccbe, /* Freq 2472 - (82 << 17) + 52414 */ + 0xa5998b, /* Freq 2484 - (82 << 17) + 104843 */ +}; + + +/* + * Take the MHz channel value and set the Channel value + * + * ASSUMES: Writes enabled to analog bus + * + * Actual Expression, + * + * For 2GHz channel, + * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) + * (freq_ref = 40MHz) + * + * For 5GHz channel, + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) + * (freq_ref = 40MHz/(24>>amode_ref_sel)) + * + * For 5GHz channels which are 5MHz spaced, + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) + * (freq_ref = 40MHz) + */ +static HAL_BOOL +ar9300_set_channel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) +{ + u_int16_t b_mode, frac_mode = 0, a_mode_ref_sel = 0; + u_int32_t freq, channel_sel, reg32; + u_int8_t clk_25mhz = AH9300(ah)->clk_25mhz; + CHAN_CENTERS centers; + int load_synth_channel; + + OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel); + + ar9300_get_channel_centers(ah, chan, ¢ers); + freq = centers.synth_center; + + + if (freq < 4800) { /* 2 GHz, fractional mode */ + b_mode = 1; /* 2 GHz */ + + if (AR_SREV_HORNET(ah)) { + u_int32_t ichan = ath_hal_mhz2ieee(ah, freq, chan->channel_flags); + HALASSERT(ichan > 0 && ichan <= 14); + if (clk_25mhz) { + channel_sel = ar9300_chansel_xtal_25M[ichan - 1]; + } else { + channel_sel = ar9300_chansel_xtal_40M[ichan - 1]; + } + } else if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { + u_int32_t channel_frac; + /* + * freq_ref = (40 / (refdiva >> a_mode_ref_sel)); + * (where refdiva = 1 and amoderefsel = 0) + * ndiv = ((chan_mhz * 4) / 3) / freq_ref; + * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 + */ + channel_sel = (freq * 4) / 120; + channel_frac = (((freq * 4) % 120) * 0x20000) / 120; + channel_sel = (channel_sel << 17) | (channel_frac); + } else if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + u_int32_t channel_frac; + if (clk_25mhz) { + /* + * freq_ref = (50 / (refdiva >> a_mode_ref_sel)); + * (where refdiva = 1 and amoderefsel = 0) + * ndiv = ((chan_mhz * 4) / 3) / freq_ref; + * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 + */ + if (AR_SREV_SCORPION(ah)) { + /* Doubler is off for Scorpion */ + channel_sel = (freq * 4) / 75; + channel_frac = (((freq * 4) % 75) * 0x20000) / 75; + } else { + channel_sel = (freq * 2) / 75; + channel_frac = (((freq * 2) % 75) * 0x20000) / 75; + } + } else { + /* + * freq_ref = (50 / (refdiva >> a_mode_ref_sel)); + * (where refdiva = 1 and amoderefsel = 0) + * ndiv = ((chan_mhz * 4) / 3) / freq_ref; + * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 + */ + if (AR_SREV_SCORPION(ah)) { + /* Doubler is off for Scorpion */ + channel_sel = (freq * 4) / 120; + channel_frac = (((freq * 4) % 120) * 0x20000) / 120; + } else { + channel_sel = (freq * 2) / 120; + channel_frac = (((freq * 2) % 120) * 0x20000) / 120; + } + } + channel_sel = (channel_sel << 17) | (channel_frac); + } else { + channel_sel = CHANSEL_2G(freq); + } + } else { + b_mode = 0; /* 5 GHz */ + if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && clk_25mhz){ + u_int32_t channel_frac; + /* + * freq_ref = (50 / (refdiva >> amoderefsel)); + * (refdiva = 1, amoderefsel = 0) + * ndiv = ((chan_mhz * 2) / 3) / freq_ref; + * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 + */ + channel_sel = freq / 75 ; + channel_frac = ((freq % 75) * 0x20000) / 75; + channel_sel = (channel_sel << 17) | (channel_frac); + } else { + channel_sel = CHANSEL_5G(freq); + /* Doubler is ON, so, divide channel_sel by 2. */ + channel_sel >>= 1; + } + } + + + /* Enable fractional mode for all channels */ + frac_mode = 1; + a_mode_ref_sel = 0; + load_synth_channel = 0; + + reg32 = (b_mode << 29); + OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); + + /* Enable Long shift Select for Synthesizer */ + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_SYNTH4, AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); + + /* program synth. setting */ + reg32 = + (channel_sel << 2) | + (a_mode_ref_sel << 28) | + (frac_mode << 30) | + (load_synth_channel << 31); + if (IS_CHAN_QUARTER_RATE(chan)) { + reg32 += CHANSEL_5G_DOT5MHZ; + } + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); + /* Toggle Load Synth channel bit */ + load_synth_channel = 1; + reg32 |= load_synth_channel << 31; + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); + + + AH_PRIVATE(ah)->ah_curchan = chan; + + return AH_TRUE; +} + + +static HAL_BOOL +ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, + u_int32_t nchans) +{ + int i; + + for (i = 0; i < nchans; i++) { + chans[i].max_tx_power = AR9300_MAX_RATE_POWER; + chans[i].min_tx_power = AR9300_MAX_RATE_POWER; + } + return AH_TRUE; +} + +HAL_BOOL +ar9300_rf_attach(struct ath_hal *ah, HAL_STATUS *status) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + ahp->ah_rf_hal.set_channel = ar9300_set_channel; + ahp->ah_rf_hal.get_chip_power_lim = ar9300_get_chip_power_limits; + + *status = HAL_OK; + + return AH_TRUE; +} + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_raw_adc_capture.c b/hal/ar9300/ar9300_raw_adc_capture.c new file mode 100644 index 000000000000..348b0f5b93c3 --- /dev/null +++ b/hal/ar9300/ar9300_raw_adc_capture.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* + * Copyright (c) 2002-2009 Atheros Communications, Inc. + * All Rights Reserved. + * + * Copyright (c) 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Qualcomm Atheros Confidential and Proprietary. + * + */ + + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_desc.h" +#include "ah_internal.h" + +#include "ar9300/ar9300phy.h" +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300desc.h" + + +#else +/* + * Raw capture mode not enabled - insert dummy code to keep the compiler happy + */ +typedef int ar9300_dummy_adc_capture; + +#endif /* AH_SUPPORT_AR9300*/ diff --git a/hal/ar9300/ar9300_recv.c b/hal/ar9300/ar9300_recv.c new file mode 100644 index 000000000000..ffb9536b9145 --- /dev/null +++ b/hal/ar9300/ar9300_recv.c @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_desc.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300desc.h" + +/* + * Get the RXDP. + */ +u_int32_t +ar9300_get_rx_dp(struct ath_hal *ath, HAL_RX_QUEUE qtype) +{ + if (qtype == HAL_RX_QUEUE_HP) { + return OS_REG_READ(ath, AR_HP_RXDP); + } else { + return OS_REG_READ(ath, AR_LP_RXDP); + } +} + +/* + * Set the rx_dp. + */ +void +ar9300_set_rx_dp(struct ath_hal *ah, u_int32_t rxdp, HAL_RX_QUEUE qtype) +{ + HALASSERT((qtype == HAL_RX_QUEUE_HP) || (qtype == HAL_RX_QUEUE_LP)); + + if (qtype == HAL_RX_QUEUE_HP) { + OS_REG_WRITE(ah, AR_HP_RXDP, rxdp); + } else { + OS_REG_WRITE(ah, AR_LP_RXDP, rxdp); + } +} + +/* + * Set Receive Enable bits. + */ +void +ar9300_enable_receive(struct ath_hal *ah) +{ + OS_REG_WRITE(ah, AR_CR, 0); +} + +/* + * Set the RX abort bit. + */ +HAL_BOOL +ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL set) +{ + if (set) { + /* Set the force_rx_abort bit */ + OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); + + if ( AH_PRIVATE(ah)->ah_reset_reason == HAL_RESET_BBPANIC ){ + /* depending upon the BB panic status, rx state may not return to 0, + * so skipping the wait for BB panic reset */ + OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); + return AH_FALSE; + } else { + HAL_BOOL okay; + okay = ath_hal_wait( + ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0, AH_WAIT_TIMEOUT); + /* Wait for Rx state to return to 0 */ + if (!okay) { + /* abort: chip rx failed to go idle in 10 ms */ + OS_REG_CLR_BIT(ah, AR_DIAG_SW, + (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); + + HALDEBUG(ah, HAL_DEBUG_RX, + "%s: rx failed to go idle in 10 ms RXSM=0x%x\n", + __func__, OS_REG_READ(ah, AR_OBS_BUS_1)); + + return AH_FALSE; /* failure */ + } + } + } else { + OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); + } + + return AH_TRUE; /* success */ +} + +/* + * Stop Receive at the DMA engine + */ +HAL_BOOL +ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout) +{ + int wait; + HAL_BOOL status, okay; + u_int32_t org_value; + +#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ +#define AH_TIME_QUANTUM 100 /* usec */ + + if (timeout == 0) { + timeout = AH_RX_STOP_DMA_TIMEOUT; + } + + org_value = OS_REG_READ(ah, AR_MACMISC); + + OS_REG_WRITE(ah, AR_MACMISC, + ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | + (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); + + okay = ath_hal_wait( + ah, AR_DMADBG_7, AR_DMADBG_RX_STATE, 0, AH_WAIT_TIMEOUT); + /* wait for Rx DMA state machine to become idle */ + if (!okay) { + HALDEBUG(ah, HAL_DEBUG_RX, + "reg AR_DMADBG_7 is not 0, instead 0x%08x\n", + OS_REG_READ(ah, AR_DMADBG_7)); + } + + /* Set receive disable bit */ + OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); + + /* Wait for rx enable bit to go low */ + for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { + if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) { + break; + } + OS_DELAY(AH_TIME_QUANTUM); + } + + if (wait == 0) { + HALDEBUG(ah, HAL_DEBUG_RX, "%s: dma failed to stop in %d ms\n" + "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", + __func__, + timeout / 1000, + OS_REG_READ(ah, AR_CR), + OS_REG_READ(ah, AR_DIAG_SW)); + status = AH_FALSE; + } else { + status = AH_TRUE; + } + + OS_REG_WRITE(ah, AR_MACMISC, org_value); + + return status; +#undef AH_RX_STOP_DMA_TIMEOUT +#undef AH_TIME_QUANTUM +} + +/* + * Start Transmit at the PCU engine (unpause receive) + */ +void +ar9300_start_pcu_receive(struct ath_hal *ah, HAL_BOOL is_scanning) +{ + ar9300_enable_mib_counters(ah); + ar9300_ani_reset(ah, is_scanning); + /* Clear RX_DIS and RX_ABORT after enabling phy errors in ani_reset */ + OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); +} + +/* + * Stop Transmit at the PCU engine (pause receive) + */ +void +ar9300_stop_pcu_receive(struct ath_hal *ah) +{ + OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); + ar9300_disable_mib_counters(ah); +} + +/* + * Set multicast filter 0 (lower 32-bits) + * filter 1 (upper 32-bits) + */ +void +ar9300_set_multicast_filter( + struct ath_hal *ah, + u_int32_t filter0, + u_int32_t filter1) +{ + OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); + OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); +} + +/* + * Get the receive filter. + */ +u_int32_t +ar9300_get_rx_filter(struct ath_hal *ah) +{ + u_int32_t bits = OS_REG_READ(ah, AR_RX_FILTER); + u_int32_t phybits = OS_REG_READ(ah, AR_PHY_ERR); + if (phybits & AR_PHY_ERR_RADAR) { + bits |= HAL_RX_FILTER_PHYRADAR; + } + if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) { + bits |= HAL_RX_FILTER_PHYERR; + } + return bits; +} + +/* + * Set the receive filter. + */ +void +ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits) +{ + u_int32_t phybits; + + if (AR_SREV_SCORPION(ah)) { + /* Enable Rx for 4 address frames */ + bits |= AR_RX_4ADDRESS; + } + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + /* HW fix for rx hang and corruption. */ + bits |= AR_RX_CONTROL_WRAPPER; + } + OS_REG_WRITE(ah, AR_RX_FILTER, + bits | AR_RX_UNCOM_BA_BAR | AR_RX_COMPR_BAR); + phybits = 0; + if (bits & HAL_RX_FILTER_PHYRADAR) { + phybits |= AR_PHY_ERR_RADAR; + } + if (bits & HAL_RX_FILTER_PHYERR) { + phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; + } + OS_REG_WRITE(ah, AR_PHY_ERR, phybits); + if (phybits) { + OS_REG_WRITE(ah, AR_RXCFG, + OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); + } else { + OS_REG_WRITE(ah, AR_RXCFG, + OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA); + } +} + +/* + * Select to pass PLCP headr or EVM data. + */ +HAL_BOOL +ar9300_set_rx_sel_evm(struct ath_hal *ah, HAL_BOOL sel_evm, HAL_BOOL just_query) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL old_value = ahp->ah_get_plcp_hdr == 0; + + if (just_query) { + return old_value; + } + if (sel_evm) { + OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM); + } else { + OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM); + } + + ahp->ah_get_plcp_hdr = !sel_evm; + + return old_value; +} + +void ar9300_promisc_mode(struct ath_hal *ah, HAL_BOOL enable) +{ + u_int32_t reg_val = 0; + reg_val = OS_REG_READ(ah, AR_RX_FILTER); + if (enable){ + reg_val |= AR_RX_PROM; + } else{ /*Disable promisc mode */ + reg_val &= ~AR_RX_PROM; + } + OS_REG_WRITE(ah, AR_RX_FILTER, reg_val); +} + +void +ar9300_read_pktlog_reg( + struct ath_hal *ah, + u_int32_t *rxfilter_val, + u_int32_t *rxcfg_val, + u_int32_t *phy_err_mask_val, + u_int32_t *mac_pcu_phy_err_regval) +{ + *rxfilter_val = OS_REG_READ(ah, AR_RX_FILTER); + *rxcfg_val = OS_REG_READ(ah, AR_RXCFG); + *phy_err_mask_val = OS_REG_READ(ah, AR_PHY_ERR); + *mac_pcu_phy_err_regval = OS_REG_READ(ah, 0x8338); + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s[%d] rxfilter_val 0x%08x , rxcfg_val 0x%08x, " + "phy_err_mask_val 0x%08x mac_pcu_phy_err_regval 0x%08x\n", + __func__, __LINE__, + *rxfilter_val, *rxcfg_val, *phy_err_mask_val, *mac_pcu_phy_err_regval); +} + +void +ar9300_write_pktlog_reg( + struct ath_hal *ah, + HAL_BOOL enable, + u_int32_t rxfilter_val, + u_int32_t rxcfg_val, + u_int32_t phy_err_mask_val, + u_int32_t mac_pcu_phy_err_reg_val) +{ + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + /* HW fix for rx hang and corruption. */ + rxfilter_val |= AR_RX_CONTROL_WRAPPER; + } + if (enable) { /* Enable pktlog phyerr setting */ + OS_REG_WRITE(ah, AR_RX_FILTER, 0xffff | AR_RX_COMPR_BAR | rxfilter_val); + OS_REG_WRITE(ah, AR_PHY_ERR, 0xFFFFFFFF); + OS_REG_WRITE(ah, AR_RXCFG, rxcfg_val | AR_RXCFG_ZLFDMA); + OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, mac_pcu_phy_err_reg_val | 0xFF); + } else { /* Disable phyerr and Restore regs */ + OS_REG_WRITE(ah, AR_RX_FILTER, rxfilter_val); + OS_REG_WRITE(ah, AR_PHY_ERR, phy_err_mask_val); + OS_REG_WRITE(ah, AR_RXCFG, rxcfg_val); + OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, mac_pcu_phy_err_reg_val); + } + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s[%d] ena %d rxfilter_val 0x%08x , rxcfg_val 0x%08x, " + "phy_err_mask_val 0x%08x mac_pcu_phy_err_regval 0x%08x\n", + __func__, __LINE__, + enable, rxfilter_val, rxcfg_val, + phy_err_mask_val, mac_pcu_phy_err_reg_val); +} + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_recv_ds.c b/hal/ar9300/ar9300_recv_ds.c new file mode 100644 index 000000000000..48379dc8336e --- /dev/null +++ b/hal/ar9300/ar9300_recv_ds.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_desc.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300desc.h" + + + +/* + * Process an RX descriptor, and return the status to the caller. + * Copy some hardware specific items into the software portion + * of the descriptor. + * + * NB: the caller is responsible for validating the memory contents + * of the descriptor (e.g. flushing any cached copy). + */ +HAL_STATUS +ar9300_proc_rx_desc_fast(struct ath_hal *ah, struct ath_desc *ds, + u_int32_t pa, struct ath_desc *nds, struct ath_rx_status *rxs, + void *buf_addr) +{ + struct ar9300_rxs *rxsp = AR9300RXS(buf_addr); + + /* + ath_hal_printf(ah,"CHH=RX: ds_info 0x%x status1: 0x%x status11: 0x%x\n", + rxsp->ds_info,rxsp->status1,rxsp->status11); + */ + + if ((rxsp->status11 & AR_rx_done) == 0) { + return HAL_EINPROGRESS; + } + + if (MS(rxsp->ds_info, AR_desc_id) != 0x168c) { +#if __PKT_SERIOUS_ERRORS__ + /*BUG: 63564-HT */ + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "%s: Rx Descriptor error 0x%x\n", + __func__, rxsp->ds_info); +#endif + return HAL_EINVAL; + } + + if ((rxsp->ds_info & (AR_tx_rx_desc | AR_ctrl_stat)) != 0) { +#if __PKT_SERIOUS_ERRORS__ + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "%s: Rx Descriptor wrong info 0x%x\n", __func__, rxsp->ds_info); +#endif + return HAL_EINPROGRESS; + } + + rxs->rs_status = 0; + rxs->rs_flags = 0; + + rxs->rs_datalen = rxsp->status2 & AR_data_len; + rxs->rs_tstamp = rxsp->status3; + + /* XXX what about key_cache_miss? */ + rxs->rs_rssi = MS(rxsp->status5, AR_rx_rssi_combined); + rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_rx_rssi_ant00); + rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_rx_rssi_ant01); + rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_rx_rssi_ant02); + rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_rx_rssi_ant10); + rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_rx_rssi_ant11); + rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_rx_rssi_ant12); + if (rxsp->status11 & AR_rx_key_idx_valid) { + rxs->rs_keyix = MS(rxsp->status11, AR_key_idx); + } else { + rxs->rs_keyix = HAL_RXKEYIX_INVALID; + } + /* NB: caller expected to do rate table mapping */ + rxs->rs_rate = MS(rxsp->status1, AR_rx_rate); + rxs->rs_more = (rxsp->status2 & AR_rx_more) ? 1 : 0; + + rxs->rs_isaggr = (rxsp->status11 & AR_rx_aggr) ? 1 : 0; + rxs->rs_moreaggr = (rxsp->status11 & AR_rx_more_aggr) ? 1 : 0; + rxs->rs_antenna = (MS(rxsp->status4, AR_rx_antenna) & 0x7); + rxs->rs_isapsd = (rxsp->status11 & AR_apsd_trig) ? 1 : 0; + rxs->rs_flags = (rxsp->status4 & AR_gi) ? HAL_RX_GI : 0; + rxs->rs_flags |= (rxsp->status4 & AR_2040) ? HAL_RX_2040 : 0; + + /* Copy EVM information */ + rxs->evm0 = rxsp->status6; + rxs->evm1 = rxsp->status7; + rxs->evm2 = rxsp->status8; + rxs->evm3 = rxsp->status9; + rxs->evm4 = (rxsp->status10 & 0xffff); + + if (rxsp->status11 & AR_pre_delim_crc_err) { + rxs->rs_flags |= HAL_RX_DELIM_CRC_PRE; + } + if (rxsp->status11 & AR_post_delim_crc_err) { + rxs->rs_flags |= HAL_RX_DELIM_CRC_POST; + } + if (rxsp->status11 & AR_decrypt_busy_err) { + rxs->rs_flags |= HAL_RX_DECRYPT_BUSY; + } + if (rxsp->status11 & AR_hi_rx_chain) { + rxs->rs_flags |= HAL_RX_HI_RX_CHAIN; + } + if (rxsp->status11 & AR_key_miss) { + rxs->rs_status |= HAL_RXERR_KEYMISS; + } + + if ((rxsp->status11 & AR_rx_frame_ok) == 0) { + /* + * These four bits should not be set together. The + * 9300 spec states a Michael error can only occur if + * decrypt_crc_err not set (and TKIP is used). Experience + * indicates however that you can also get Michael errors + * when a CRC error is detected, but these are specious. + * Consequently we filter them out here so we don't + * confuse and/or complicate drivers. + */ + if (rxsp->status11 & AR_crc_err) { + rxs->rs_status |= HAL_RXERR_CRC; + /* + * ignore CRC flag for spectral phy reports + */ + if (rxsp->status11 & AR_phyerr) { + u_int phyerr = MS(rxsp->status11, AR_phy_err_code); + if (phyerr == HAL_PHYERR_SPECTRAL) { + rxs->rs_status |= HAL_RXERR_PHY; + rxs->rs_phyerr = phyerr; + } + } + } else if (rxsp->status11 & AR_phyerr) { + u_int phyerr; + + /* + * Packets with OFDM_RESTART on post delimiter are CRC OK and + * usable and MAC ACKs them. + * To avoid packet from being lost, we remove the PHY Err flag + * so that lmac layer does not drop them. + * (EV 70071) + */ + phyerr = MS(rxsp->status11, AR_phy_err_code); + if ((phyerr == HAL_PHYERR_OFDM_RESTART) && + (rxsp->status11 & AR_post_delim_crc_err)) { + rxs->rs_phyerr = 0; + } else { + rxs->rs_status |= HAL_RXERR_PHY; + rxs->rs_phyerr = phyerr; + } + } else if (rxsp->status11 & AR_decrypt_crc_err) { + rxs->rs_status |= HAL_RXERR_DECRYPT; + } else if (rxsp->status11 & AR_michael_err) { + rxs->rs_status |= HAL_RXERR_MIC; + } + } + + return HAL_OK; +} + +HAL_STATUS +ar9300_proc_rx_desc(struct ath_hal *ah, struct ath_desc *ds, + u_int32_t pa, struct ath_desc *nds, u_int64_t tsf, + struct ath_rx_status *rxs) +{ + return HAL_ENOTSUPP; +} + +/* + * rx path in ISR is different for ar9300 from ar5416, and + * ath_rx_proc_descfast will not be called if edmasupport is true. + * So this function ath_hal_get_rxkeyidx will not be + * called for ar9300. + * This function in ar9300's HAL is just a stub one because we need + * to link something to the callback interface of the HAL module. + */ +HAL_STATUS +ar9300_get_rx_key_idx(struct ath_hal *ah, struct ath_desc *ds, u_int8_t *keyix, + u_int8_t *status) +{ + *status = 0; + *keyix = HAL_RXKEYIX_INVALID; + return HAL_ENOTSUPP; +} + + +#endif diff --git a/hal/ar9300/ar9300_reset.c b/hal/ar9300/ar9300_reset.c new file mode 100644 index 000000000000..58ebc1ec076a --- /dev/null +++ b/hal/ar9300/ar9300_reset.c @@ -0,0 +1,6072 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" +#include "ah_devid.h" +#include "ah_desc.h" + +#include "ar9300.h" +#include "ar9300reg.h" +#include "ar9300phy.h" +#include "ar9300desc.h" + +#define FIX_NOISE_FLOOR 1 + + + +/* Additional Time delay to wait after activiting the Base band */ +#define BASE_ACTIVATE_DELAY 100 /* usec */ +#define RTC_PLL_SETTLE_DELAY 100 /* usec */ +#define COEF_SCALE_S 24 +#define HT40_CHANNEL_CENTER_SHIFT 10 /* MHz */ + +#define DELPT 32 + +extern HAL_BOOL ar9300_reset_tx_queue(struct ath_hal *ah, u_int q); +extern u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q); + + +#define MAX_MEASUREMENT 8 +#define MAXIQCAL 3 +struct coeff_t { + int32_t mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL]; + int32_t phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL]; + int32_t iqc_coeff[2]; + int last_nmeasurement; + HAL_BOOL last_cal; +}; + +static HAL_BOOL ar9300_tx_iq_cal_hw_run(struct ath_hal *ah); +static void ar9300_tx_iq_cal_post_proc(struct ath_hal *ah,HAL_CHANNEL_INTERNAL *ichan, + int iqcal_idx, int max_iqcal, HAL_BOOL is_cal_reusable, HAL_BOOL apply_last_corr); +static void ar9300_tx_iq_cal_outlier_detection(struct ath_hal *ah,HAL_CHANNEL_INTERNAL *ichan, + u_int32_t num_chains, struct coeff_t *coeff, HAL_BOOL is_cal_reusable); +#if ATH_SUPPORT_CAL_REUSE +static void ar9300_tx_iq_cal_apply(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan); +#endif + + +static inline void ar9300_prog_ini(struct ath_hal *ah, struct ar9300_ini_array *ini_arr, int column); +static inline void ar9300_set_rf_mode(struct ath_hal *ah, HAL_CHANNEL *chan); +static inline HAL_BOOL ar9300_init_cal(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL skip_if_none, HAL_BOOL apply_last_corr); +static inline void ar9300_init_user_settings(struct ath_hal *ah); + +#ifdef HOST_OFFLOAD +/* + * For usb offload solution, some USB registers must be tuned + * to gain better stability/performance but these registers + * might be changed while doing wlan reset so do this here + */ +#define WAR_USB_DISABLE_PLL_LOCK_DETECT(__ah) \ +do { \ + if (AR_SREV_HORNET(__ah) || AR_SREV_WASP(__ah)) { \ + volatile u_int32_t *usb_ctrl_r1 = (u_int32_t *) 0xb8116c84; \ + volatile u_int32_t *usb_ctrl_r2 = (u_int32_t *) 0xb8116c88; \ + *usb_ctrl_r1 = (*usb_ctrl_r1 & 0xffefffff); \ + *usb_ctrl_r2 = (*usb_ctrl_r2 & 0xfc1fffff) | (1 << 21) | (3 << 22); \ + } \ +} while (0) +#else +#define WAR_USB_DISABLE_PLL_LOCK_DETECT(__ah) +#endif + +static inline void +ar9300_attach_hw_platform(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + ahp->ah_hwp = HAL_TRUE_CHIP; + return; +} + +/* Adjust various register settings based on half/quarter rate clock setting. + * This includes: +USEC, TX/RX latency, + * + IFS params: slot, eifs, misc etc. + * SIFS stays the same. + */ +static void +ar9300_set_ifs_timing(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + u_int32_t tx_lat, rx_lat, usec, slot, regval, eifs; + + regval = OS_REG_READ(ah, AR_USEC); + regval &= ~(AR_USEC_RX_LATENCY | AR_USEC_TX_LATENCY | AR_USEC_USEC); + if (IS_CHAN_HALF_RATE(chan)) { /* half rates */ + slot = ar9300_mac_to_clks(ah, AR_SLOT_HALF); + eifs = ar9300_mac_to_clks(ah, AR_EIFS_HALF); + if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { /* fast clock */ + rx_lat = SM(AR_RX_LATENCY_HALF_FAST_CLOCK, AR_USEC_RX_LATENCY); + tx_lat = SM(AR_TX_LATENCY_HALF_FAST_CLOCK, AR_USEC_TX_LATENCY); + usec = SM(AR_USEC_HALF_FAST_CLOCK, AR_USEC_USEC); + } else { + rx_lat = SM(AR_RX_LATENCY_HALF, AR_USEC_RX_LATENCY); + tx_lat = SM(AR_TX_LATENCY_HALF, AR_USEC_TX_LATENCY); + usec = SM(AR_USEC_HALF, AR_USEC_USEC); + } + } else { /* quarter rate */ + slot = ar9300_mac_to_clks(ah, AR_SLOT_QUARTER); + eifs = ar9300_mac_to_clks(ah, AR_EIFS_QUARTER); + if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { /* fast clock */ + rx_lat = SM(AR_RX_LATENCY_QUARTER_FAST_CLOCK, AR_USEC_RX_LATENCY); + tx_lat = SM(AR_TX_LATENCY_QUARTER_FAST_CLOCK, AR_USEC_TX_LATENCY); + usec = SM(AR_USEC_QUARTER_FAST_CLOCK, AR_USEC_USEC); + } else { + rx_lat = SM(AR_RX_LATENCY_QUARTER, AR_USEC_RX_LATENCY); + tx_lat = SM(AR_TX_LATENCY_QUARTER, AR_USEC_TX_LATENCY); + usec = SM(AR_USEC_QUARTER, AR_USEC_USEC); + } + } + + OS_REG_WRITE(ah, AR_USEC, (usec | regval | tx_lat | rx_lat)); + OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot); + OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs); +} + + +/* + * This inline function configures the chip either + * to encrypt/decrypt management frames or pass thru + */ +static inline void +ar9300_init_mfp(struct ath_hal * ah) +{ + u_int32_t mfpcap, mfp_qos; + + ath_hal_getcapability(ah, HAL_CAP_MFP, 0, &mfpcap); + + if (mfpcap == HAL_MFP_QOSDATA) { + /* Treat like legacy hardware. Do not touch the MFP registers. */ + HALDEBUG(ah, HAL_DEBUG_RESET, "%s forced to use QOSDATA\n", __func__); + return; + } + + /* MFP support (Sowl 1.0 or greater) */ + if (mfpcap == HAL_MFP_HW_CRYPTO) { + /* configure hardware MFP support */ + HALDEBUG(ah, HAL_DEBUG_RESET, "%s using HW crypto\n", __func__); + OS_REG_RMW_FIELD(ah, + AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, AR_AES_MUTE_MASK1_FC_MGMT_MFP); + OS_REG_RMW(ah, + AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE, + AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); + /* + * Mask used to construct AAD for CCMP-AES + * Cisco spec defined bits 0-3 as mask + * IEEE802.11w defined as bit 4. + */ + if (ath_hal_get_mfp_qos(ah)) { + mfp_qos = AR_MFP_QOS_MASK_IEEE; + } else { + mfp_qos = AR_MFP_QOS_MASK_CISCO; + } + OS_REG_RMW_FIELD(ah, + AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_MGMT_QOS, mfp_qos); + } else if (mfpcap == HAL_MFP_PASSTHRU) { + /* Disable en/decrypt by hardware */ + HALDEBUG(ah, HAL_DEBUG_RESET, "%s using passthru\n", __func__); + OS_REG_RMW(ah, + AR_PCU_MISC_MODE2, + AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT, + AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); + } +} + +void +ar9300_get_channel_centers(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, + CHAN_CENTERS *centers) +{ + int8_t extoff; + struct ath_hal_9300 *ahp = AH9300(ah); + + if (!IS_CHAN_HT40(chan)) { + centers->ctl_center = centers->ext_center = + centers->synth_center = chan->channel; + return; + } + + HALASSERT(IS_CHAN_HT40(chan)); + + /* + * In 20/40 phy mode, the center frequency is + * "between" the primary and extension channels. + */ + if (chan->channel_flags & CHANNEL_HT40PLUS) { + centers->synth_center = chan->channel + HT40_CHANNEL_CENTER_SHIFT; + extoff = 1; + } else { + centers->synth_center = chan->channel - HT40_CHANNEL_CENTER_SHIFT; + extoff = -1; + } + + centers->ctl_center = + centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); + centers->ext_center = + centers->synth_center + + (extoff * ((ahp->ah_ext_prot_spacing == HAL_HT_EXTPROTSPACING_20) ? + HT40_CHANNEL_CENTER_SHIFT : 15)); +} + +/* + * Read the noise-floor values from the HW. + * Specifically, read the minimum clear-channel assessment value for + * each chain, for both the control and extension channels. + * (The received power level during clear-channel periods is the + * noise floor.) + * These noise floor values computed by the HW will be stored in the + * NF history buffer. + * The HW sometimes produces bogus NF values. To avoid using these + * bogus values, the NF data is (a) range-limited, and (b) filtered. + * However, this data-processing is done when reading the NF values + * out of the history buffer. The history buffer stores the raw values. + * This allows the NF history buffer to be used to check for interference. + * A single high NF reading might be a bogus HW value, but if the NF + * readings are consistently high, it must be due to interference. + * This is the purpose of storing raw NF values in the history buffer, + * rather than processed values. By looking at a history of NF values + * that have not been range-limited, we can check if they are consistently + * high (due to interference). + */ +#define AH_NF_SIGN_EXTEND(nf) \ + ((nf) & 0x100) ? \ + 0 - (((nf) ^ 0x1ff) + 1) : \ + (nf) +void +ar9300_upload_noise_floor(struct ath_hal *ah, int is_2g, + int16_t nfarray[NUM_NF_READINGS]) +{ + int16_t nf; + int chan, chain; + u_int32_t regs[NUM_NF_READINGS] = { + /* control channel */ + AR_PHY_CCA_0, /* chain 0 */ + AR_PHY_CCA_1, /* chain 1 */ + AR_PHY_CCA_2, /* chain 2 */ + /* extension channel */ + AR_PHY_EXT_CCA, /* chain 0 */ + AR_PHY_EXT_CCA_1, /* chain 1 */ + AR_PHY_EXT_CCA_2, /* chain 2 */ + }; + u_int8_t chainmask; + + /* + * Within a given channel (ctl vs. ext), the CH0, CH1, and CH2 + * masks and shifts are the same, though they differ for the + * control vs. extension channels. + */ + u_int32_t masks[2] = { + AR_PHY_MINCCA_PWR, /* control channel */ + AR_PHY_EXT_MINCCA_PWR, /* extention channel */ + }; + u_int8_t shifts[2] = { + AR_PHY_MINCCA_PWR_S, /* control channel */ + AR_PHY_EXT_MINCCA_PWR_S, /* extention channel */ + }; + + /* + * Force NF calibration for all chains. + */ + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { + chainmask = 0x01; + } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah)) { + chainmask = 0x03; + } else { + chainmask = 0x07; + } + + for (chan = 0; chan < 2 /*ctl,ext*/; chan++) { + for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { + int i; + + if (!((chainmask >> chain) & 0x1)) { + continue; + } + i = chan * AR9300_MAX_CHAINS + chain; + nf = (OS_REG_READ(ah, regs[i]) & masks[chan]) >> shifts[chan]; + nfarray[i] = AH_NF_SIGN_EXTEND(nf); + } + } +} + +/* ar9300_get_min_cca_pwr - + * Used by the scan function for a quick read of the noise floor. + * This is used to detect presence of CW interference such as video bridge. + * The noise floor is assumed to have been already started during reset + * called during channel change. The function checks if the noise floor + * reading is done. In case it has been done, it reads the noise floor value. + * If the noise floor calibration has not been finished, it assumes this is + * due to presence of CW interference an returns a high value for noise floor, + * derived from the CW interference threshold + margin fudge factor. + */ +#define BAD_SCAN_NF_MARGIN (30) +int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah) +{ + int16_t nf; + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + + if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) { + nf = MS(OS_REG_READ(ah, AR_PHY_CCA_0), AR9280_PHY_MINCCA_PWR); + if (nf & 0x100) { + nf = 0 - ((nf ^ 0x1ff) + 1); + } + } else { + /* NF calibration is not done, assume CW interference */ + nf = ahpriv->nfp->nominal + ahpriv->nf_cw_int_delta + + BAD_SCAN_NF_MARGIN; + } + return nf; +} + + +/* + * Noise Floor values for all chains. + * Most recently updated values from the NF history buffer are used. + */ +void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf, + HAL_CHANNEL *chan, int is_scan) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int i, nf_hist_len, recent_nf_index = 0; + HAL_NFCAL_HIST_FULL *h; + u_int8_t rx_chainmask = ahp->ah_rx_chainmask | (ahp->ah_rx_chainmask << 3); + HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); + HALASSERT(ichan); + +#ifdef ATH_NF_PER_CHAN + /* Fill 0 if valid internal channel is not found */ + if (ichan == AH_NULL) { + OS_MEMZERO(nf_buf, sizeof(nf_buf[0])*NUM_NF_READINGS); + return; + } + h = &ichan->nf_cal_hist; + nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL; +#else + /* + * If a scan is not in progress, then the most recent value goes + * into ahpriv->nf_cal_hist. If a scan is in progress, then + * the most recent value goes into ichan->nf_cal_hist. + * Thus, return the value from ahpriv->nf_cal_hist if there's + * no scan, and if the specified channel is the current channel. + * Otherwise, return the noise floor from ichan->nf_cal_hist. + */ + if ((!is_scan) && chan->channel == AH_PRIVATE(ah)->ah_curchan->channel) { + h = &AH_PRIVATE(ah)->nf_cal_hist; + nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL; + } else { + /* Fill 0 if valid internal channel is not found */ + if (ichan == AH_NULL) { + OS_MEMZERO(nf_buf, sizeof(nf_buf[0])*NUM_NF_READINGS); + return; + } + /* + * It is okay to treat a HAL_NFCAL_HIST_SMALL struct as if it were a + * HAL_NFCAL_HIST_FULL struct, as long as only the index 0 of the + * nf_cal_buffer is used (nf_cal_buffer[0][0:NUM_NF_READINGS-1]) + */ + h = (HAL_NFCAL_HIST_FULL *) &ichan->nf_cal_hist; + nf_hist_len = HAL_NF_CAL_HIST_LEN_SMALL; + } +#endif + /* Get most recently updated values from nf cal history buffer */ + recent_nf_index = + (h->base.curr_index) ? h->base.curr_index - 1 : nf_hist_len - 1; + + for (i = 0; i < NUM_NF_READINGS; i++) { + /* Fill 0 for unsupported chains */ + if (!(rx_chainmask & (1 << i))) { + nf_buf[i] = 0; + continue; + } + nf_buf[i] = h->nf_cal_buffer[recent_nf_index][i]; + } +} + + +/* + * Pick up the medium one in the noise floor buffer and update the + * corresponding range for valid noise floor values + */ +static int16_t +ar9300_get_nf_hist_mid(struct ath_hal *ah, HAL_NFCAL_HIST_FULL *h, int reading, + int hist_len) +{ + int16_t nfval; + int16_t sort[HAL_NF_CAL_HIST_LEN_FULL]; /* upper bound for hist_len */ + int i, j; + + for (i = 0; i < hist_len; i++) { + sort[i] = h->nf_cal_buffer[i][reading]; + HALDEBUG(ah, HAL_DEBUG_NF_CAL, + "nf_cal_buffer[%d][%d] = %d\n", i, reading, (int)sort[i]); + } + for (i = 0; i < hist_len - 1; i++) { + for (j = 1; j < hist_len - i; j++) { + if (sort[j] > sort[j - 1]) { + nfval = sort[j]; + sort[j] = sort[j - 1]; + sort[j - 1] = nfval; + } + } + } + nfval = sort[(hist_len - 1) >> 1]; + + return nfval; +} + +static int16_t ar9300_limit_nf_range(struct ath_hal *ah, int16_t nf) +{ + if (nf < AH_PRIVATE(ah)->nfp->min) { + return AH_PRIVATE(ah)->nfp->nominal; + } else if (nf > AH_PRIVATE(ah)->nfp->max) { + return AH_PRIVATE(ah)->nfp->max; + } + return nf; +} + +#ifndef ATH_NF_PER_CHAN +inline static void +ar9300_reset_nf_hist_buff(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan) +{ + HAL_CHAN_NFCAL_HIST *h = &ichan->nf_cal_hist; + HAL_NFCAL_HIST_FULL *home = &AH_PRIVATE(ah)->nf_cal_hist; + int i; + + /* + * Copy the value for the channel in question into the home-channel + * NF history buffer. The channel NF is probably a value filled in by + * a prior background channel scan, but if no scan has been done then + * it is the nominal noise floor filled in by ath_hal_init_NF_buffer + * for this chip and the channel's band. + * Replicate this channel NF into all entries of the home-channel NF + * history buffer. + * If the channel NF was filled in by a channel scan, it has not had + * bounds limits applied to it yet - do so now. It is important to + * apply bounds limits to the priv_nf value that gets loaded into the + * WLAN chip's min_cca_pwr register field. It is also necessary to + * apply bounds limits to the nf_cal_buffer[] elements. Since we are + * replicating a single NF reading into all nf_cal_buffer elements, + * if the single reading were above the CW_INT threshold, the CW_INT + * check in ar9300_get_nf would immediately conclude that CW interference + * is present, even though we're not supposed to set CW_INT unless + * NF values are _consistently_ above the CW_INT threshold. + * Applying the bounds limits to the nf_cal_buffer contents fixes this + * problem. + */ + for (i = 0; i < NUM_NF_READINGS; i ++) { + int j; + int16_t nf; + /* + * No need to set curr_index, since it already has a value in + * the range [0..HAL_NF_CAL_HIST_LEN_FULL), and all nf_cal_buffer + * values will be the same. + */ + nf = ar9300_limit_nf_range(ah, h->nf_cal_buffer[0][i]); + for (j = 0; j < HAL_NF_CAL_HIST_LEN_FULL; j++) { + home->nf_cal_buffer[j][i] = nf; + } + AH_PRIVATE(ah)->nf_cal_hist.base.priv_nf[i] = nf; + } +} +#endif + +/* + * Update the noise floor buffer as a ring buffer + */ +static int16_t +ar9300_update_nf_hist_buff(struct ath_hal *ah, HAL_NFCAL_HIST_FULL *h, + int16_t *nfarray, int hist_len) +{ + int i, nr; + int16_t nf_no_lim_chain0; + + nf_no_lim_chain0 = ar9300_get_nf_hist_mid(ah, h, 0, hist_len); + + HALDEBUG(ah, HAL_DEBUG_NF_CAL, "%s[%d] BEFORE\n", __func__, __LINE__); + for (nr = 0; nr < HAL_NF_CAL_HIST_LEN_FULL; nr++) { + for (i = 0; i < NUM_NF_READINGS; i++) { + HALDEBUG(ah, HAL_DEBUG_NF_CAL, + "nf_cal_buffer[%d][%d] = %d\n", + nr, i, (int)h->nf_cal_buffer[nr][i]); + } + } + for (i = 0; i < NUM_NF_READINGS; i++) { + h->nf_cal_buffer[h->base.curr_index][i] = nfarray[i]; + h->base.priv_nf[i] = ar9300_limit_nf_range( + ah, ar9300_get_nf_hist_mid(ah, h, i, hist_len)); + } + HALDEBUG(ah, HAL_DEBUG_NF_CAL, "%s[%d] AFTER\n", __func__, __LINE__); + for (nr = 0; nr < HAL_NF_CAL_HIST_LEN_FULL; nr++) { + for (i = 0; i < NUM_NF_READINGS; i++) { + HALDEBUG(ah, HAL_DEBUG_NF_CAL, + "nf_cal_buffer[%d][%d] = %d\n", + nr, i, (int)h->nf_cal_buffer[nr][i]); + } + } + + if (++h->base.curr_index >= hist_len) { + h->base.curr_index = 0; + } + + return nf_no_lim_chain0; +} + +#if UNUSED +static HAL_BOOL +get_noise_floor_thresh(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *chan, + int16_t *nft) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + switch (chan->channel_flags & CHANNEL_ALL_NOTURBO) { + case CHANNEL_A: + case CHANNEL_A_HT20: + case CHANNEL_A_HT40PLUS: + case CHANNEL_A_HT40MINUS: + *nft = (int8_t)ar9300_eeprom_get(ahp, EEP_NFTHRESH_5); + break; + case CHANNEL_B: + case CHANNEL_G: + case CHANNEL_G_HT20: + case CHANNEL_G_HT40PLUS: + case CHANNEL_G_HT40MINUS: + *nft = (int8_t)ar9300_eeprom_get(ahp, EEP_NFTHRESH_2); + break; + default: + HALDEBUG(ah, HAL_DEBUG_CHANNEL, "%s: invalid channel flags 0x%x\n", + __func__, chan->channel_flags); + return AH_FALSE; + } + return AH_TRUE; +} +#endif + +/* + * Read the NF and check it against the noise floor threshhold + */ +#define IS(_c, _f) (((_c)->channel_flags & _f) || 0) +static int +ar9300_store_new_nf(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, int is_scan) +{ + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + int nf_hist_len; + int16_t nf_no_lim; + int16_t nfarray[NUM_NF_READINGS] = {0}; + HAL_NFCAL_HIST_FULL *h; + int is_2g = 0; + + if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { + u_int32_t tsf32, nf_cal_dur_tsf; + /* + * The reason the NF calibration did not complete may just be that + * not enough time has passed since the NF calibration was started, + * because under certain conditions (when first moving to a new + * channel) the NF calibration may be checked very repeatedly. + * Or, there may be CW interference keeping the NF calibration + * from completing. Check the delta time between when the NF + * calibration was started and now to see whether the NF calibration + * should have already completed (but hasn't, probably due to CW + * interference), or hasn't had enough time to finish yet. + */ + /* + * AH_NF_CAL_DUR_MAX_TSF - A conservative maximum time that the + * HW should need to finish a NF calibration. If the HW + * does not complete a NF calibration within this time period, + * there must be a problem - probably CW interference. + * AH_NF_CAL_PERIOD_MAX_TSF - A conservative maximum time between + * check of the HW's NF calibration being finished. + * If the difference between the current TSF and the TSF + * recorded when the NF calibration started is larger than this + * value, the TSF must have been reset. + * In general, we expect the TSF to only be reset during + * regular operation for STAs, not for APs. However, an + * AP's TSF could be reset when joining an IBSS. + * There's an outside chance that this could result in the + * CW_INT flag being erroneously set, if the TSF adjustment + * is smaller than AH_NF_CAL_PERIOD_MAX_TSF but larger than + * AH_NF_CAL_DUR_TSF. However, even if this does happen, + * it shouldn't matter, as the IBSS case shouldn't be + * concerned about CW_INT. + */ + /* AH_NF_CAL_DUR_TSF - 90 sec in usec units */ + #define AH_NF_CAL_DUR_TSF (90 * 1000 * 1000) + /* AH_NF_CAL_PERIOD_MAX_TSF - 180 sec in usec units */ + #define AH_NF_CAL_PERIOD_MAX_TSF (180 * 1000 * 1000) + /* wraparound handled by using unsigned values */ + tsf32 = ar9300_get_tsf32(ah); + nf_cal_dur_tsf = tsf32 - AH9300(ah)->nf_tsf32; + if (nf_cal_dur_tsf > AH_NF_CAL_PERIOD_MAX_TSF) { + /* + * The TSF must have gotten reset during the NF cal - + * just reset the NF TSF timestamp, so the next time + * this function is called, the timestamp comparison + * will be valid. + */ + AH9300(ah)->nf_tsf32 = tsf32; + } else if (nf_cal_dur_tsf > AH_NF_CAL_DUR_TSF) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: NF did not complete in calibration window\n", __func__); + /* the NF incompletion is probably due to CW interference */ + chan->channel_flags |= CHANNEL_CW_INT; + } + return 0; /* HW's NF measurement not finished */ + } + HALDEBUG(ah, HAL_DEBUG_NF_CAL, + "%s[%d] chan %d\n", __func__, __LINE__, chan->channel); + is_2g = IS(chan, CHANNEL_2GHZ); + ar9300_upload_noise_floor(ah, is_2g, nfarray); + + /* Update the NF buffer for each chain masked by chainmask */ +#ifdef ATH_NF_PER_CHAN + h = &chan->nf_cal_hist; + nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL; +#else + if (is_scan) { + /* + * This channel's NF cal info is just a HAL_NFCAL_HIST_SMALL struct + * rather than a HAL_NFCAL_HIST_FULL struct. + * As long as we only use the first history element of nf_cal_buffer + * (nf_cal_buffer[0][0:NUM_NF_READINGS-1]), we can use + * HAL_NFCAL_HIST_SMALL and HAL_NFCAL_HIST_FULL interchangeably. + */ + h = (HAL_NFCAL_HIST_FULL *) &chan->nf_cal_hist; + nf_hist_len = HAL_NF_CAL_HIST_LEN_SMALL; + } else { + h = &AH_PRIVATE(ah)->nf_cal_hist; + nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL; + } +#endif + + /* + * nf_no_lim = median value from NF history buffer without bounds limits, + * priv_nf = median value from NF history buffer with bounds limits. + */ + nf_no_lim = ar9300_update_nf_hist_buff(ah, h, nfarray, nf_hist_len); + chan->raw_noise_floor = h->base.priv_nf[0]; + + /* check if there is interference */ + chan->channel_flags &= (~CHANNEL_CW_INT); + /* + * Use AR9300_EMULATION to check for emulation purpose as PCIE Device ID + * 0xABCD is recognized as valid Osprey as WAR in some EVs. + */ + if (nf_no_lim > ahpriv->nfp->nominal + ahpriv->nf_cw_int_delta) { + /* + * Since this CW interference check is being applied to the + * median element of the NF history buffer, this indicates that + * the CW interference is persistent. A single high NF reading + * will not show up in the median, and thus will not cause the + * CW_INT flag to be set. + */ + HALDEBUG(ah, HAL_DEBUG_NF_CAL, + "%s: NF Cal: CW interferer detected through NF: %d\n", + __func__, nf_no_lim); + chan->channel_flags |= CHANNEL_CW_INT; + } + return 1; /* HW's NF measurement finished */ +} +#undef IS + +static inline void +ar9300_get_delta_slope_values(struct ath_hal *ah, u_int32_t coef_scaled, + u_int32_t *coef_mantissa, u_int32_t *coef_exponent) +{ + u_int32_t coef_exp, coef_man; + + /* + * ALGO -> coef_exp = 14-floor(log2(coef)); + * floor(log2(x)) is the highest set bit position + */ + for (coef_exp = 31; coef_exp > 0; coef_exp--) { + if ((coef_scaled >> coef_exp) & 0x1) { + break; + } + } + /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ + HALASSERT(coef_exp); + coef_exp = 14 - (coef_exp - COEF_SCALE_S); + + + /* + * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); + * The coefficient is already shifted up for scaling + */ + coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); + + *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); + *coef_exponent = coef_exp - 16; +} + +#define MAX_ANALOG_START 319 /* XXX */ + +/* + * Delta slope coefficient computation. + * Required for OFDM operation. + */ +static void +ar9300_set_delta_slope(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) +{ + u_int32_t coef_scaled, ds_coef_exp, ds_coef_man; + u_int32_t fclk = COEFF; /* clock * 2.5 */ + + u_int32_t clock_mhz_scaled = 0x1000000 * fclk; + CHAN_CENTERS centers; + + /* + * half and quarter rate can divide the scaled clock by 2 or 4 + * scale for selected channel bandwidth + */ + if (IS_CHAN_HALF_RATE(chan)) { + clock_mhz_scaled = clock_mhz_scaled >> 1; + } else if (IS_CHAN_QUARTER_RATE(chan)) { + clock_mhz_scaled = clock_mhz_scaled >> 2; + } + + /* + * ALGO -> coef = 1e8/fcarrier*fclock/40; + * scaled coef to provide precision for this floating calculation + */ + ar9300_get_channel_centers(ah, chan, ¢ers); + coef_scaled = clock_mhz_scaled / centers.synth_center; + + ar9300_get_delta_slope_values(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); + + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, AR_PHY_TIMING3_DSC_MAN, ds_coef_man); + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); + + /* + * For Short GI, + * scaled coeff is 9/10 that of normal coeff + */ + coef_scaled = (9 * coef_scaled) / 10; + + ar9300_get_delta_slope_values(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); + + /* for short gi */ + OS_REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, AR_PHY_SGI_DSC_MAN, ds_coef_man); + OS_REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, AR_PHY_SGI_DSC_EXP, ds_coef_exp); +} + +#define IS(_c, _f) (((_c)->channel_flags & _f) || 0) + +static inline HAL_CHANNEL_INTERNAL* +ar9300_check_chan(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) { + HALDEBUG(ah, HAL_DEBUG_CHANNEL, + "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n", + __func__, chan->channel, chan->channel_flags); + return AH_NULL; + } + + if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK) ^ + IS(chan, CHANNEL_HT20) ^ IS(chan, CHANNEL_HT40PLUS) ^ + IS(chan, CHANNEL_HT40MINUS)) == 0) + { + HALDEBUG(ah, HAL_DEBUG_CHANNEL, + "%s: invalid channel %u/0x%x; not marked as " + "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n", + __func__, chan->channel, chan->channel_flags); + return AH_NULL; + } + + return (ath_hal_checkchannel(ah, chan)); +} +#undef IS + +static void +ar9300_set_11n_regs(struct ath_hal *ah, HAL_CHANNEL *chan, + HAL_HT_MACMODE macmode) +{ + u_int32_t phymode; + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t enable_dac_fifo; + + /* XXX */ + enable_dac_fifo = + OS_REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO; + + /* Enable 11n HT, 20 MHz */ + phymode = + AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_SHORT_GI_40 + | enable_dac_fifo; + /* Configure baseband for dynamic 20/40 operation */ + if (IS_CHAN_HT40(chan)) { + phymode |= AR_PHY_GC_DYN2040_EN; + /* Configure control (primary) channel at +-10MHz */ + if (chan->channel_flags & CHANNEL_HT40PLUS) { + phymode |= AR_PHY_GC_DYN2040_PRI_CH; + } + + /* Configure 20/25 spacing */ + if (ahp->ah_ext_prot_spacing == HAL_HT_EXTPROTSPACING_25) { + phymode |= AR_PHY_GC_DYN2040_EXT_CH; + } + } + + /* make sure we preserve INI settings */ + phymode |= OS_REG_READ(ah, AR_PHY_GEN_CTRL); + + /* EV 62881/64991 - turn off Green Field detection for Maverick STA beta */ + phymode &= ~AR_PHY_GC_GF_DETECT_EN; + + OS_REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); + + /* Set IFS timing for half/quarter rates */ + if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) { + u_int32_t modeselect = OS_REG_READ(ah, AR_PHY_MODE); + + if (IS_CHAN_HALF_RATE(chan)) { + modeselect |= AR_PHY_MS_HALF_RATE; + } else if (IS_CHAN_QUARTER_RATE(chan)) { + modeselect |= AR_PHY_MS_QUARTER_RATE; + } + OS_REG_WRITE(ah, AR_PHY_MODE, modeselect); + + ar9300_set_ifs_timing(ah, chan); + OS_REG_RMW_FIELD( + ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 0x3); + } + + /* Configure MAC for 20/40 operation */ + ar9300_set_11n_mac2040(ah, macmode); + + /* global transmit timeout (25 TUs default)*/ + /* XXX - put this elsewhere??? */ + OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); + + /* carrier sense timeout */ + OS_REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); +} + +/* + * Spur mitigation for MRC CCK + */ +static void +ar9300_spur_mitigate_mrc_cck(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + int i; + /* spur_freq_for_osprey - hardcoded by Systems team for now. */ + u_int32_t spur_freq_for_osprey[4] = { 2420, 2440, 2464, 2480 }; + u_int32_t spur_freq_for_jupiter[2] = { 2440, 2464}; + int cur_bb_spur, negative = 0, cck_spur_freq; + u_int8_t* spur_fbin_ptr = NULL; + int synth_freq; + int range = 10; + int max_spurcounts = OSPREY_EEPROM_MODAL_SPURS; + + /* + * Need to verify range +/- 10 MHz in control channel, otherwise spur + * is out-of-band and can be ignored. + */ + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || + AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + spur_fbin_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 1); + if (spur_fbin_ptr[0] == 0) { + return; /* No spur in the mode */ + } + if (IS_CHAN_HT40(chan)) { + range = 19; + if (OS_REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH) + == 0x0) + { + synth_freq = chan->channel + 10; + } else { + synth_freq = chan->channel - 10; + } + } else { + range = 10; + synth_freq = chan->channel; + } + } else if(AR_SREV_JUPITER(ah)) { + range = 5; + max_spurcounts = 2; /* Hardcoded by Jupiter Systems team for now. */ + synth_freq = chan->channel; + } else { + range = 10; + max_spurcounts = 4; /* Hardcoded by Osprey Systems team for now. */ + synth_freq = chan->channel; + } + + for (i = 0; i < max_spurcounts; i++) { + negative = 0; + + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || + AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + cur_bb_spur = + FBIN2FREQ(spur_fbin_ptr[i], HAL_FREQ_BAND_2GHZ) - synth_freq; + } else if(AR_SREV_JUPITER(ah)) { + cur_bb_spur = spur_freq_for_jupiter[i] - synth_freq; + } else { + cur_bb_spur = spur_freq_for_osprey[i] - synth_freq; + } + + if (cur_bb_spur < 0) { + negative = 1; + cur_bb_spur = -cur_bb_spur; + } + if (cur_bb_spur < range) { + cck_spur_freq = (int)((cur_bb_spur << 19) / 11); + if (negative == 1) { + cck_spur_freq = -cck_spur_freq; + } + cck_spur_freq = cck_spur_freq & 0xfffff; + /*OS_REG_WRITE_field(ah, BB_agc_control.ycok_max, 0x7);*/ + OS_REG_RMW_FIELD(ah, + AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); + /*OS_REG_WRITE_field(ah, BB_cck_spur_mit.spur_rssi_thr, 0x7f);*/ + OS_REG_RMW_FIELD(ah, + AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); + /*OS_REG_WRITE(ah, BB_cck_spur_mit.spur_filter_type, 0x2);*/ + OS_REG_RMW_FIELD(ah, + AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2); + /*OS_REG_WRITE(ah, BB_cck_spur_mit.use_cck_spur_mit, 0x1);*/ + OS_REG_RMW_FIELD(ah, + AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x1); + /*OS_REG_WRITE(ah, BB_cck_spur_mit.cck_spur_freq, cck_spur_freq);*/ + OS_REG_RMW_FIELD(ah, + AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, + cck_spur_freq); + return; + } + } + + /*OS_REG_WRITE(ah, BB_agc_control.ycok_max, 0x5);*/ + OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); + /*OS_REG_WRITE(ah, BB_cck_spur_mit.use_cck_spur_mit, 0x0);*/ + OS_REG_RMW_FIELD(ah, + AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); + /*OS_REG_WRITE(ah, BB_cck_spur_mit.cck_spur_freq, 0x0);*/ + OS_REG_RMW_FIELD(ah, + AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); +} + +/* Spur mitigation for OFDM */ +static void +ar9300_spur_mitigate_ofdm(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + int synth_freq; + int range = 10; + int freq_offset = 0; + int spur_freq_sd = 0; + int spur_subchannel_sd = 0; + int spur_delta_phase = 0; + int mask_index = 0; + int i; + int mode; + u_int8_t* spur_chans_ptr; + + if (IS_CHAN_5GHZ(chan)) { + spur_chans_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 0); + mode = 0; + } else { + spur_chans_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 1); + mode = 1; + } + + if (IS_CHAN_HT40(chan)) { + range = 19; + if (OS_REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH) + == 0x0) + { + synth_freq = chan->channel - 10; + } else { + synth_freq = chan->channel + 10; + } + } else { + range = 10; + synth_freq = chan->channel; + } + + /* Clean all spur register fields */ + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0); + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_FREQ_SD, 0); + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); + OS_REG_RMW_FIELD(ah, + AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0); + OS_REG_RMW_FIELD(ah, + AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0); + OS_REG_RMW_FIELD(ah, + AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0); + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0); + OS_REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0); + OS_REG_RMW_FIELD(ah, + AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0); + OS_REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0); + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0); + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0); + OS_REG_RMW_FIELD(ah, + AR_PHY_PILOT_SPUR_MASK, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0); + OS_REG_RMW_FIELD(ah, + AR_PHY_SPUR_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0); + OS_REG_RMW_FIELD(ah, + AR_PHY_CHAN_SPUR_MASK, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0); + OS_REG_RMW_FIELD(ah, + AR_PHY_PILOT_SPUR_MASK, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0); + OS_REG_RMW_FIELD(ah, + AR_PHY_CHAN_SPUR_MASK, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0); + OS_REG_RMW_FIELD(ah, + AR_PHY_SPUR_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0); + OS_REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); + + i = 0; + while (spur_chans_ptr[i] && i < 5) { + freq_offset = FBIN2FREQ(spur_chans_ptr[i], mode) - synth_freq; + if (abs(freq_offset) < range) { + /* + printf( + "Spur Mitigation for OFDM: Synth Frequency = %d, " + "Spur Frequency = %d\n", + synth_freq, FBIN2FREQ(spur_chans_ptr[i], mode)); + */ + if (IS_CHAN_HT40(chan)) { + if (freq_offset < 0) { + if (OS_REG_READ_FIELD( + ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH) == 0x0) + { + spur_subchannel_sd = 1; + } else { + spur_subchannel_sd = 0; + } + spur_freq_sd = ((freq_offset + 10) << 9) / 11; + } else { + if (OS_REG_READ_FIELD(ah, + AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH) == 0x0) + { + spur_subchannel_sd = 0; + } else { + spur_subchannel_sd = 1; + } + spur_freq_sd = ((freq_offset - 10) << 9) / 11; + } + spur_delta_phase = (freq_offset << 17) / 5; + } else { + spur_subchannel_sd = 0; + spur_freq_sd = (freq_offset << 9) / 11; + spur_delta_phase = (freq_offset << 18) / 5; + } + spur_freq_sd = spur_freq_sd & 0x3ff; + spur_delta_phase = spur_delta_phase & 0xfffff; + /* + printf( + "spur_subchannel_sd = %d, spur_freq_sd = 0x%x, " + "spur_delta_phase = 0x%x\n", spur_subchannel_sd, + spur_freq_sd, spur_delta_phase); + */ + + /* OFDM Spur mitigation */ + OS_REG_RMW_FIELD(ah, + AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1); + OS_REG_RMW_FIELD(ah, + AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd); + OS_REG_RMW_FIELD(ah, + AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_DELTA_PHASE, + spur_delta_phase); + OS_REG_RMW_FIELD(ah, + AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, + spur_subchannel_sd); + OS_REG_RMW_FIELD(ah, + AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); + OS_REG_RMW_FIELD(ah, + AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, + 0x1); + OS_REG_RMW_FIELD(ah, + AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); + OS_REG_RMW_FIELD(ah, + AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34); + OS_REG_RMW_FIELD(ah, + AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1); + + /* + * Do not subtract spur power from noise floor for wasp. + * This causes the maximum client test (on Veriwave) to fail + * when run on spur channel (2464 MHz). + * Refer to ev#82746 and ev#82744. + */ + if (!AR_SREV_WASP(ah) && (OS_REG_READ_FIELD(ah, AR_PHY_MODE, + AR_PHY_MODE_DYNAMIC) == 0x1)) { + OS_REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, + AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1); + } + + mask_index = (freq_offset << 4) / 5; + if (mask_index < 0) { + mask_index = mask_index - 1; + } + mask_index = mask_index & 0x7f; + /*printf("Bin 0x%x\n", mask_index);*/ + + OS_REG_RMW_FIELD(ah, + AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1); + OS_REG_RMW_FIELD(ah, + AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1); + OS_REG_RMW_FIELD(ah, + AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1); + OS_REG_RMW_FIELD(ah, + AR_PHY_PILOT_SPUR_MASK, + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index); + OS_REG_RMW_FIELD(ah, + AR_PHY_SPUR_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, + mask_index); + OS_REG_RMW_FIELD(ah, + AR_PHY_CHAN_SPUR_MASK, + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index); + OS_REG_RMW_FIELD(ah, + AR_PHY_PILOT_SPUR_MASK, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, + 0xc); + OS_REG_RMW_FIELD(ah, + AR_PHY_CHAN_SPUR_MASK, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, + 0xc); + OS_REG_RMW_FIELD(ah, + AR_PHY_SPUR_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); + OS_REG_RMW_FIELD(ah, + AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); + /* + printf("BB_timing_control_4 = 0x%x\n", + OS_REG_READ(ah, AR_PHY_TIMING4)); + printf("BB_timing_control_11 = 0x%x\n", + OS_REG_READ(ah, AR_PHY_TIMING11)); + printf("BB_ext_chan_scorr_thr = 0x%x\n", + OS_REG_READ(ah, AR_PHY_SFCORR_EXT)); + printf("BB_spur_mask_controls = 0x%x\n", + OS_REG_READ(ah, AR_PHY_SPUR_REG)); + printf("BB_pilot_spur_mask = 0x%x\n", + OS_REG_READ(ah, AR_PHY_PILOT_SPUR_MASK)); + printf("BB_chan_spur_mask = 0x%x\n", + OS_REG_READ(ah, AR_PHY_CHAN_SPUR_MASK)); + printf("BB_vit_spur_mask_A = 0x%x\n", + OS_REG_READ(ah, AR_PHY_SPUR_MASK_A)); + */ + break; + } + i++; + } +} + + +/* + * Convert to baseband spur frequency given input channel frequency + * and compute register settings below. + */ +static void +ar9300_spur_mitigate(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + ar9300_spur_mitigate_ofdm(ah, chan); + ar9300_spur_mitigate_mrc_cck(ah, chan); +} + + +/************************************************************** + * ar9300_channel_change + * Assumes caller wants to change channel, and not reset. + */ +static inline HAL_BOOL +ar9300_channel_change(struct ath_hal *ah, HAL_CHANNEL *chan, + HAL_CHANNEL_INTERNAL *ichan, HAL_HT_MACMODE macmode) +{ + + u_int32_t synth_delay, qnum; + struct ath_hal_9300 *ahp = AH9300(ah); + + /* TX must be stopped by now */ + for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { + if (ar9300_num_tx_pending(ah, qnum)) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: Transmit frames pending on queue %d\n", __func__, qnum); + HALASSERT(0); + return AH_FALSE; + } + } + + + /* + * Kill last Baseband Rx Frame - Request analog bus grant + */ + OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); + if (!ath_hal_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, + AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) + { + HALDEBUG(ah, HAL_DEBUG_PHY_IO, + "%s: Could not kill baseband RX\n", __func__); + return AH_FALSE; + } + + + /* Setup 11n MAC/Phy mode registers */ + ar9300_set_11n_regs(ah, chan, macmode); + + /* + * Change the synth + */ + if (!ahp->ah_rf_hal.set_channel(ah, ichan)) { + HALDEBUG(ah, HAL_DEBUG_CHANNEL, "%s: failed to set channel\n", __func__); + return AH_FALSE; + } + + /* + * Some registers get reinitialized during ATH_INI_POST INI programming. + */ + ar9300_init_user_settings(ah); + + /* + * Setup the transmit power values. + * + * After the public to private hal channel mapping, ichan contains the + * valid regulatory power value. + * ath_hal_getctl and ath_hal_getantennaallowed look up ichan from chan. + */ + if (ar9300_eeprom_set_transmit_power( + ah, &ahp->ah_eeprom, ichan, ath_hal_getctl(ah, chan), + ath_hal_getantennaallowed(ah, chan), + ath_hal_get_twice_max_regpower(AH_PRIVATE(ah), ichan, chan), + AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_power_limit)) != HAL_OK) + { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: error init'ing transmit power\n", __func__); + return AH_FALSE; + } + + /* + * Release the RFBus Grant. + */ + OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); + + /* + * Write spur immunity and delta slope for OFDM enabled modes (A, G, Turbo) + */ + if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) { + ar9300_set_delta_slope(ah, ichan); + } else { + /* Set to Ini default */ + OS_REG_WRITE(ah, AR_PHY_TIMING3, 0x9c0a9f6b); + OS_REG_WRITE(ah, AR_PHY_SGI_DELTA, 0x00046384); + } + + ar9300_spur_mitigate(ah, chan); + + + /* + * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). + * Read the phy active delay register. Value is in 100ns increments. + */ + synth_delay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; + if (IS_CHAN_CCK(chan)) { + synth_delay = (4 * synth_delay) / 22; + } else { + synth_delay /= 10; + } + + OS_DELAY(synth_delay + BASE_ACTIVATE_DELAY); + + /* + * Do calibration. + */ + + return AH_TRUE; +} + +void +ar9300_set_operating_mode(struct ath_hal *ah, int opmode) +{ + u_int32_t val; + + val = OS_REG_READ(ah, AR_STA_ID1); + val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); + switch (opmode) { + case HAL_M_HOSTAP: + OS_REG_WRITE(ah, AR_STA_ID1, + val | AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE); + OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); + break; + case HAL_M_IBSS: + OS_REG_WRITE(ah, AR_STA_ID1, + val | AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE); + OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); + break; + case HAL_M_STA: + case HAL_M_MONITOR: + OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); + break; + } +} + +/* XXX need the logic for Osprey */ +inline void +ar9300_init_pll(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + u_int32_t pll; + u_int8_t clk_25mhz = AH9300(ah)->clk_25mhz; + + if (AR_SREV_HORNET(ah)) { + if (clk_25mhz) { + /* Hornet uses PLL_CONTROL_2. Xtal is 25MHz for Hornet. + * REFDIV set to 0x1. + * $xtal_freq = 25; + * $PLL2_div = (704/$xtal_freq); # 176 * 4 = 704. + * MAC and BB run at 176 MHz. + * $PLL2_divint = int($PLL2_div); + * $PLL2_divfrac = $PLL2_div - $PLL2_divint; + * $PLL2_divfrac = int($PLL2_divfrac * 0x4000); # 2^14 + * $PLL2_Val = ($PLL2_divint & 0x3f) << 19 | (0x1) << 14 | + * $PLL2_divfrac & 0x3fff; + * Therefore, $PLL2_Val = 0xe04a3d + */ +#define DPLL2_KD_VAL 0x1D +#define DPLL2_KI_VAL 0x06 +#define DPLL3_PHASE_SHIFT_VAL 0x1 + + /* Rewrite DDR PLL2 and PLL3 */ + /* program DDR PLL ki and kd value, ki=0x6, kd=0x1d */ + OS_REG_WRITE(ah, AR_HORNET_CH0_DDR_DPLL2, 0x18e82f01); + + /* program DDR PLL phase_shift to 0x1 */ + OS_REG_RMW_FIELD(ah, AR_HORNET_CH0_DDR_DPLL3, + AR_PHY_BB_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL); + + OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); + OS_DELAY(1000); + + /* program refdiv, nint, frac to RTC register */ + OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0xe04a3d); + + /* program BB PLL ki and kd value, ki=0x6, kd=0x1d */ + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, + AR_PHY_BB_DPLL2_KD, DPLL2_KD_VAL); + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, + AR_PHY_BB_DPLL2_KI, DPLL2_KI_VAL); + + /* program BB PLL phase_shift to 0x1 */ + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL3, + AR_PHY_BB_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL); + } else { /* 40MHz */ +#undef DPLL2_KD_VAL +#undef DPLL2_KI_VAL +#define DPLL2_KD_VAL 0x3D +#define DPLL2_KI_VAL 0x06 + /* Rewrite DDR PLL2 and PLL3 */ + /* program DDR PLL ki and kd value, ki=0x6, kd=0x3d */ + OS_REG_WRITE(ah, AR_HORNET_CH0_DDR_DPLL2, 0x19e82f01); + + /* program DDR PLL phase_shift to 0x1 */ + OS_REG_RMW_FIELD(ah, AR_HORNET_CH0_DDR_DPLL3, + AR_PHY_BB_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL); + + OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); + OS_DELAY(1000); + + /* program refdiv, nint, frac to RTC register */ + OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666); + + /* program BB PLL ki and kd value, ki=0x6, kd=0x3d */ + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, + AR_PHY_BB_DPLL2_KD, DPLL2_KD_VAL); + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, + AR_PHY_BB_DPLL2_KI, DPLL2_KI_VAL); + + /* program BB PLL phase_shift to 0x1 */ + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL3, + AR_PHY_BB_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL); + } + OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c); + OS_DELAY(1000); + } else if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, AR_PHY_BB_DPLL2_PLL_PWD, 0x1); + + /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, + AR_PHY_BB_DPLL2_KD, 0x40); + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, + AR_PHY_BB_DPLL2_KI, 0x4); + + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL1, + AR_PHY_BB_DPLL1_REFDIV, 0x5); + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL1, + AR_PHY_BB_DPLL1_NINI, 0x58); + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL1, + AR_PHY_BB_DPLL1_NFRAC, 0x0); + + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, + AR_PHY_BB_DPLL2_OUTDIV, 0x1); + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, + AR_PHY_BB_DPLL2_LOCAL_PLL, 0x1); + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, + AR_PHY_BB_DPLL2_EN_NEGTRIG, 0x1); + + /* program BB PLL phase_shift to 0x6 */ + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL3, + AR_PHY_BB_DPLL3_PHASE_SHIFT, 0x6); + + OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, + AR_PHY_BB_DPLL2_PLL_PWD, 0x0); + OS_DELAY(1000); + + OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c); + OS_DELAY(1000); + } else if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { +#define SRIF_PLL 1 + u_int32_t regdata, pll2_divint, pll2_divfrac; + +#ifndef SRIF_PLL + u_int32_t pll2_clkmode; +#endif + +#ifdef SRIF_PLL + u_int32_t refdiv; +#endif + if (clk_25mhz) { +#ifndef SRIF_PLL + pll2_divint = 0x1c; + pll2_divfrac = 0xa3d7; +#else + pll2_divint = 0x54; + pll2_divfrac = 0x1eb85; + refdiv = 3; +#endif + } else { +#ifndef SRIF_PLL + pll2_divint = 0x11; + pll2_divfrac = 0x26666; +#else + if (AR_SREV_WASP(ah)) { + pll2_divint = 88; + pll2_divfrac = 0; + refdiv = 5; + } else { + pll2_divint = 0x11; + pll2_divfrac = 0x26666; + refdiv = 1; + } +#endif + } +#ifndef SRIF_PLL + pll2_clkmode = 0x3d; +#endif + /* PLL programming through SRIF Local Mode */ + OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); /* Bypass mode */ + OS_DELAY(1000); + do { + regdata = OS_REG_READ(ah, AR_PHY_PLL_MODE); + regdata = regdata | (0x1 << 16); + OS_REG_WRITE(ah, AR_PHY_PLL_MODE, regdata); /* PWD_PLL set to 1 */ + OS_DELAY(100); + /* override int, frac, refdiv */ +#ifndef SRIF_PLL + OS_REG_WRITE(ah, AR_PHY_PLL_CONTROL, + ((1 << 27) | (pll2_divint << 18) | pll2_divfrac)); +#else + OS_REG_WRITE(ah, AR_PHY_PLL_CONTROL, + ((refdiv << 27) | (pll2_divint << 18) | pll2_divfrac)); +#endif + OS_DELAY(100); + regdata = OS_REG_READ(ah, AR_PHY_PLL_MODE); +#ifndef SRIF_PLL + regdata = (regdata & 0x80071fff) | + (0x1 << 30) | (0x1 << 13) | (0x6 << 26) | (pll2_clkmode << 19); +#else + if (AR_SREV_WASP(ah)) { + regdata = (regdata & 0x80071fff) | + (0x1 << 30) | (0x1 << 13) | (0x4 << 26) | (0x18 << 19); + } else { + regdata = (regdata & 0x80071fff) | + (0x3 << 30) | (0x1 << 13) | (0x4 << 26) | (0x60 << 19); + } +#endif + /* Ki, Kd, Local PLL, Outdiv */ + OS_REG_WRITE(ah, AR_PHY_PLL_MODE, regdata); + regdata = OS_REG_READ(ah, AR_PHY_PLL_MODE); + regdata = (regdata & 0xfffeffff); + OS_REG_WRITE(ah, AR_PHY_PLL_MODE, regdata); /* PWD_PLL set to 0 */ + OS_DELAY(1000); + if (AR_SREV_WASP(ah)) { + /* clear do measure */ + regdata = OS_REG_READ(ah, AR_PHY_PLL_BB_DPLL3); + regdata &= ~(1 << 30); + OS_REG_WRITE(ah, AR_PHY_PLL_BB_DPLL3, regdata); + OS_DELAY(100); + + /* set do measure */ + regdata = OS_REG_READ(ah, AR_PHY_PLL_BB_DPLL3); + regdata |= (1 << 30); + OS_REG_WRITE(ah, AR_PHY_PLL_BB_DPLL3, regdata); + + /* wait for measure done */ + do { + regdata = OS_REG_READ(ah, AR_PHY_PLL_BB_DPLL4); + } while ((regdata & (1 << 3)) == 0); + + /* clear do measure */ + regdata = OS_REG_READ(ah, AR_PHY_PLL_BB_DPLL3); + regdata &= ~(1 << 30); + OS_REG_WRITE(ah, AR_PHY_PLL_BB_DPLL3, regdata); + + /* get measure sqsum dvc */ + regdata = (OS_REG_READ(ah, AR_PHY_PLL_BB_DPLL3) & 0x007FFFF8) >> 3; + } else { + break; + } + } while (regdata >= 0x40000); + + /* Remove from Bypass mode */ + OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c); + OS_DELAY(1000); + } else { + pll = SM(0x5, AR_RTC_PLL_REFDIV); + + /* Supposedly not needed on Osprey */ +#if 0 + if (chan && IS_CHAN_HALF_RATE(chan)) { + pll |= SM(0x1, AR_RTC_PLL_CLKSEL); + } else if (chan && IS_CHAN_QUARTER_RATE(chan)) { + pll |= SM(0x2, AR_RTC_PLL_CLKSEL); + } +#endif + if (chan && IS_CHAN_5GHZ(chan)) { + pll |= SM(0x28, AR_RTC_PLL_DIV); + /* + * When doing fast clock, set PLL to 0x142c + */ + if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { + pll = 0x142c; + } + } else { + pll |= SM(0x2c, AR_RTC_PLL_DIV); + } + + OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); + } + + /* TODO: + * For multi-band owl, switch between bands by reiniting the PLL. + */ + OS_DELAY(RTC_PLL_SETTLE_DELAY); + + OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, + AR_RTC_FORCE_DERIVED_CLK | AR_RTC_PCIE_RST_PWDN_EN); + + if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + if (clk_25mhz) { + OS_REG_WRITE(ah, + AR_RTC_DERIVED_RTC_CLK, (0x17c << 1)); /* 32KHz sleep clk */ + OS_REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); + OS_REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); + } else { + OS_REG_WRITE(ah, + AR_RTC_DERIVED_RTC_CLK, (0x261 << 1)); /* 32KHz sleep clk */ + OS_REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); + OS_REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); + } + OS_DELAY(100); + } +} + +static inline HAL_BOOL +ar9300_set_reset(struct ath_hal *ah, int type) +{ + u_int32_t rst_flags; + u_int32_t tmp_reg; + + HALASSERT(type == HAL_RESET_WARM || type == HAL_RESET_COLD); + + /* + * RTC Force wake should be done before resetting the MAC. + * MDK/ART does it that way. + */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), AH9300(ah)->ah_wa_reg_val); + OS_DELAY(10); /* delay to allow AR_WA reg write to kick in */ + OS_REG_WRITE(ah, + AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); + + /* Reset AHB */ + /* Bug26871 */ + tmp_reg = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)); + if (AR_SREV_WASP(ah)) { + if (tmp_reg & (AR9340_INTR_SYNC_LOCAL_TIMEOUT)) { + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE), 0); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF); + } + } else { + if (tmp_reg & (AR9300_INTR_SYNC_LOCAL_TIMEOUT | AR9300_INTR_SYNC_RADM_CPL_TIMEOUT)) { + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE), 0); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF); + } + else { + /* NO AR_RC_AHB in Osprey */ + /*OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_AHB);*/ + } + } + + rst_flags = AR_RTC_RC_MAC_WARM; + if (type == HAL_RESET_COLD) { + rst_flags |= AR_RTC_RC_MAC_COLD; + } + +#ifdef AH_SUPPORT_HORNET + /* Hornet WAR: trigger SoC to reset WMAC if ... + * (1) doing cold reset. Ref: EV 69254 + * (2) beacon pending. Ref: EV 70983 + */ + if (AR_SREV_HORNET(ah) && + (ar9300_num_tx_pending( + ah, AH_PRIVATE(ah)->ah_caps.hal_total_queues - 1) != 0 || + type == HAL_RESET_COLD)) + { + u_int32_t time_out; +#define AR_SOC_RST_RESET 0xB806001C +#define AR_SOC_BOOT_STRAP 0xB80600AC +#define AR_SOC_WLAN_RST 0x00000800 /* WLAN reset */ +#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); +#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Hornet SoC reset WMAC.\n", __func__); + + REG_WRITE(AR_SOC_RST_RESET, + REG_READ(AR_SOC_RST_RESET) | AR_SOC_WLAN_RST); + REG_WRITE(AR_SOC_RST_RESET, + REG_READ(AR_SOC_RST_RESET) & (~AR_SOC_WLAN_RST)); + + time_out = 0; + + while (1) { + tmp_reg = REG_READ(AR_SOC_BOOT_STRAP); + if ((tmp_reg & 0x10) == 0) { + break; + } + if (time_out > 20) { + break; + } + OS_DELAY(10000); + time_out++; + } + + OS_REG_WRITE(ah, AR_RTC_RESET, 1); +#undef REG_READ +#undef REG_WRITE +#undef AR_SOC_WLAN_RST +#undef AR_SOC_RST_RESET +#undef AR_SOC_BOOT_STRAP + } +#endif /* AH_SUPPORT_HORNET */ + +#ifdef AH_SUPPORT_SCORPION + if (AR_SREV_SCORPION(ah)) { +#define DDR_CTL_CONFIG_ADDRESS 0xb8000000 +#define DDR_CTL_CONFIG_OFFSET 0x0108 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MSB 29 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB 21 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK 0x3fe00000 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(x) (((x) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) >> DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x) (((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) +#define MAC_DMA_CFG_ADDRESS 0xb8100000 +#define MAC_DMA_CFG_OFFSET 0x0014 + +#define MAC_DMA_CFG_HALT_REQ_MSB 11 +#define MAC_DMA_CFG_HALT_REQ_LSB 11 +#define MAC_DMA_CFG_HALT_REQ_MASK 0x00000800 +#define MAC_DMA_CFG_HALT_REQ_GET(x) (((x) & MAC_DMA_CFG_HALT_REQ_MASK) >> MAC_DMA_CFG_HALT_REQ_LSB) +#define MAC_DMA_CFG_HALT_REQ_SET(x) (((x) << MAC_DMA_CFG_HALT_REQ_LSB) & MAC_DMA_CFG_HALT_REQ_MASK) +#define MAC_DMA_CFG_HALT_ACK_MSB 12 +#define MAC_DMA_CFG_HALT_ACK_LSB 12 +#define MAC_DMA_CFG_HALT_ACK_MASK 0x00001000 +#define MAC_DMA_CFG_HALT_ACK_GET(x) (((x) & MAC_DMA_CFG_HALT_ACK_MASK) >> MAC_DMA_CFG_HALT_ACK_LSB) +#define MAC_DMA_CFG_HALT_ACK_SET(x) (((x) << MAC_DMA_CFG_HALT_ACK_LSB) & MAC_DMA_CFG_HALT_ACK_MASK) + +#define RST_RESET 0xB806001c +#define RTC_RESET (1<<27) + +#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) +#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); + +#define DDR_REG_READ(_ah, _reg) \ + *((volatile u_int32_t *)( DDR_CTL_CONFIG_ADDRESS + (_reg))) +#define DDR_REG_WRITE(_ah, _reg, _val) \ + *((volatile u_int32_t *)(DDR_CTL_CONFIG_ADDRESS + (_reg))) = (_val) + + OS_REG_WRITE(ah,MAC_DMA_CFG_OFFSET, (OS_REG_READ(ah,MAC_DMA_CFG_OFFSET) & ~MAC_DMA_CFG_HALT_REQ_MASK) | + MAC_DMA_CFG_HALT_REQ_SET(1)); + + { + int count; + u_int32_t data; + + count = 0; + while (!MAC_DMA_CFG_HALT_ACK_GET(OS_REG_READ(ah, MAC_DMA_CFG_OFFSET) )) + { + count++; + if (count > 10) { + ath_hal_printf(ah, "Halt ACK timeout\n"); + break; + } + OS_DELAY(10); + } + + data = DDR_REG_READ(ah,DDR_CTL_CONFIG_OFFSET); + ath_hal_printf(ah, "check DDR Activity - HIGH\n"); + + count = 0; + while (DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(data)) { + // AVE_DEBUG(0,"DDR Activity - HIGH\n"); + ath_hal_printf(ah, "DDR Activity - HIGH\n"); + count++; + OS_DELAY(10); + data = DDR_REG_READ(ah,DDR_CTL_CONFIG_OFFSET); + if (count > 10) { + ath_hal_printf(ah, "DDR Activity timeout\n"); + break; + } + } + } + + + { + //Force RTC reset + REG_WRITE(RST_RESET, (REG_READ(RST_RESET) | RTC_RESET)); + OS_DELAY(10); + REG_WRITE(RST_RESET, (REG_READ(RST_RESET) & ~RTC_RESET)); + OS_DELAY(10); + OS_REG_WRITE(ah, AR_RTC_RESET, 0); + OS_DELAY(10); + OS_REG_WRITE(ah, AR_RTC_RESET, 1); + OS_DELAY(10); + ath_hal_printf(ah,"%s: Scorpion SoC RTC reset done.\n", __func__); + } +#undef REG_READ +#undef REG_WRITE + } +#endif /* AH_SUPPORT_SCORPION */ + + /* + * Set Mac(BB,Phy) Warm Reset + */ + OS_REG_WRITE(ah, AR_RTC_RC, rst_flags); + + OS_DELAY(50); /* XXX 50 usec */ + + /* + * Clear resets and force wakeup + */ + OS_REG_WRITE(ah, AR_RTC_RC, 0); + if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: RTC stuck in MAC reset\n", __FUNCTION__); + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: AR_RTC_RC = 0x%x\n", __func__, OS_REG_READ(ah, AR_RTC_RC)); + return AH_FALSE; + } + + /* Clear AHB reset */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), 0); + + ar9300_attach_hw_platform(ah); + + return AH_TRUE; +} + +static inline HAL_BOOL +ar9300_set_reset_power_on(struct ath_hal *ah) +{ + /* Force wake */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), AH9300(ah)->ah_wa_reg_val); + OS_DELAY(10); /* delay to allow AR_WA reg write to kick in */ + OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, + AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); + /* + * RTC reset and clear. Some delay in between is needed + * to give the chip time to settle. + */ + OS_REG_WRITE(ah, AR_RTC_RESET, 0); + OS_DELAY(2); + OS_REG_WRITE(ah, AR_RTC_RESET, 1); + + /* + * Poll till RTC is ON + */ +#define AH_RTC_POLL_TIMEOUT AH_WAIT_TIMEOUT + if (!ath_hal_wait(ah, + AR_RTC_STATUS, AR_RTC_STATUS_M, + AR_RTC_STATUS_ON, AH_RTC_POLL_TIMEOUT)) + { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s: RTC not waking up for %d\n", __FUNCTION__, AH_WAIT_TIMEOUT); + return AH_FALSE; + } + + /* + * Read Revisions from Chip right after RTC is on for the first time. + * This helps us detect the chip type early and initialize it accordingly. + */ + ar9300_read_revisions(ah); + + /* + * Warm reset if we aren't really powering on, + * just restarting the driver. + */ + return ar9300_set_reset(ah, HAL_RESET_WARM); +} + +/* + * Write the given reset bit mask into the reset register + */ +HAL_BOOL +ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type) +{ + HAL_BOOL ret = AH_FALSE; + + /* + * Set force wake + */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), AH9300(ah)->ah_wa_reg_val); + OS_DELAY(10); /* delay to allow AR_WA reg write to kick in */ + OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, + AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); + + switch (type) { + case HAL_RESET_POWER_ON: + ret = ar9300_set_reset_power_on(ah); + break; + case HAL_RESET_WARM: + case HAL_RESET_COLD: + ret = ar9300_set_reset(ah, type); + break; + default: + break; + } + +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) { + OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); + } +#endif + + return ret; +} + +/* + * Places the PHY and Radio chips into reset. A full reset + * must be called to leave this state. The PCI/MAC/PCU are + * not placed into reset as we must receive interrupt to + * re-enable the hardware. + */ +HAL_BOOL +ar9300_phy_disable(struct ath_hal *ah) +{ + if (!ar9300_set_reset_reg(ah, HAL_RESET_WARM)) { + return AH_FALSE; + } + +#ifdef ATH_SUPPORT_LED +#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) +#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); +#define ATH_GPIO_OE 0xB8040000 +#define ATH_GPIO_OUT 0xB8040008 /* GPIO Ouput Value reg.*/ + if (AR_SREV_WASP(ah)) { + if (IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan))) { + REG_WRITE(ATH_GPIO_OE, (REG_READ(ATH_GPIO_OE) | (0x1 << 13))); + } + else { + REG_WRITE(ATH_GPIO_OE, (REG_READ(ATH_GPIO_OE) | (0x1 << 12))); + } + } + else if (AR_SREV_SCORPION(ah)) { + if (IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan))) { + REG_WRITE(ATH_GPIO_OE, (REG_READ(ATH_GPIO_OE) | (0x1 << 13))); + } + else { + REG_WRITE(ATH_GPIO_OE, (REG_READ(ATH_GPIO_OE) | (0x1 << 12))); + } + /* Turn off JMPST led */ + REG_WRITE(ATH_GPIO_OUT, (REG_READ(ATH_GPIO_OUT) | (0x1 << 15))); + } +#undef REG_READ +#undef REG_WRITE +#endif + + if ( AR_SREV_OSPREY(ah) ) { + OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1), 0x0, 0x1f); + } + + + ar9300_init_pll(ah, AH_NULL); + + return AH_TRUE; +} + +/* + * Places all of hardware into reset + */ +HAL_BOOL +ar9300_disable(struct ath_hal *ah) +{ + if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { + return AH_FALSE; + } + if (!ar9300_set_reset_reg(ah, HAL_RESET_COLD)) { + return AH_FALSE; + } + + ar9300_init_pll(ah, AH_NULL); + + return AH_TRUE; +} + +/* + * TODO: Only write the PLL if we're changing to or from CCK mode + * + * WARNING: The order of the PLL and mode registers must be correct. + */ +static inline void +ar9300_set_rf_mode(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + u_int32_t rf_mode = 0; + + if (chan == AH_NULL) { + return; + } + switch (AH9300(ah)->ah_hwp) { + case HAL_TRUE_CHIP: + rf_mode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) ? + AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; + break; + default: + HALASSERT(0); + break; + } + /* Phy mode bits for 5GHz channels requiring Fast Clock */ + if ( IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { + rf_mode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); + } + OS_REG_WRITE(ah, AR_PHY_MODE, rf_mode); +} + +/* + * Places the hardware into reset and then pulls it out of reset + */ +HAL_BOOL +ar9300_chip_reset(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->channel : 0); + + /* + * Warm reset is optimistic. + */ + if (!ar9300_set_reset_reg(ah, HAL_RESET_WARM)) { + return AH_FALSE; + } + + /* Bring out of sleep mode (AGAIN) */ + if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { + return AH_FALSE; + } + + ahp->ah_chip_full_sleep = AH_FALSE; + + if (AR_SREV_HORNET(ah)) { + ar9300_internal_regulator_apply(ah); + } + + ar9300_init_pll(ah, chan); + + /* + * Perform warm reset before the mode/PLL/turbo registers + * are changed in order to deactivate the radio. Mode changes + * with an active radio can result in corrupted shifts to the + * radio device. + */ + ar9300_set_rf_mode(ah, chan); + + return AH_TRUE; +} + +/* ar9300_setup_calibration + * Setup HW to collect samples used for current cal + */ +inline static void +ar9300_setup_calibration(struct ath_hal *ah, HAL_CAL_LIST *curr_cal) +{ + /* Select calibration to run */ + switch (curr_cal->cal_data->cal_type) { + case IQ_MISMATCH_CAL: + /* Start calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */ + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4, + AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, + curr_cal->cal_data->cal_count_max); + OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: starting IQ Mismatch Calibration\n", __func__); + + /* Kick-off cal */ + OS_REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); + + break; + case TEMP_COMP_CAL: + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || + AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + OS_REG_RMW_FIELD(ah, + AR_HORNET_CH0_THERM, AR_PHY_65NM_CH0_THERM_LOCAL, 1); + OS_REG_RMW_FIELD(ah, + AR_HORNET_CH0_THERM, AR_PHY_65NM_CH0_THERM_START, 1); + } else if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_THERM_JUPITER, AR_PHY_65NM_CH0_THERM_LOCAL, 1); + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_THERM_JUPITER, AR_PHY_65NM_CH0_THERM_START, 1); + } else { + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_THERM, AR_PHY_65NM_CH0_THERM_LOCAL, 1); + OS_REG_RMW_FIELD(ah, + AR_PHY_65NM_CH0_THERM, AR_PHY_65NM_CH0_THERM_START, 1); + } + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: starting Temperature Compensation Calibration\n", __func__); + break; + default: + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s called with incorrect calibration type.\n", __func__); + } +} + +/* ar9300_reset_calibration + * Initialize shared data structures and prepare a cal to be run. + */ +inline static void +ar9300_reset_calibration(struct ath_hal *ah, HAL_CAL_LIST *curr_cal) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int i; + + /* Setup HW for new calibration */ + ar9300_setup_calibration(ah, curr_cal); + + /* Change SW state to RUNNING for this calibration */ + curr_cal->cal_state = CAL_RUNNING; + + /* Reset data structures shared between different calibrations */ + for (i = 0; i < AR9300_MAX_CHAINS; i++) { + ahp->ah_meas0.sign[i] = 0; + ahp->ah_meas1.sign[i] = 0; + ahp->ah_meas2.sign[i] = 0; + ahp->ah_meas3.sign[i] = 0; + } + + ahp->ah_cal_samples = 0; +} + +#ifdef XXX_UNUSED_FUNCTION +/* + * Find out which of the RX chains are enabled + */ +static u_int32_t +ar9300_get_rx_chain_mask(struct ath_hal *ah) +{ + u_int32_t ret_val = OS_REG_READ(ah, AR_PHY_RX_CHAINMASK); + /* The bits [2:0] indicate the rx chain mask and are to be + * interpreted as follows: + * 00x => Only chain 0 is enabled + * 01x => Chain 1 and 0 enabled + * 1xx => Chain 2,1 and 0 enabled + */ + return (ret_val & 0x7); +} +#endif + +static void +ar9300_get_nf_hist_base(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, + int is_scan, int16_t nf[]) +{ + HAL_NFCAL_BASE *h_base; + +#ifdef ATH_NF_PER_CHAN + h_base = &chan->nf_cal_hist.base; +#else + if (is_scan) { + /* + * The channel we are currently on is not the home channel, + * so we shouldn't use the home channel NF buffer's values on + * this channel. Instead, use the NF single value already + * read for this channel. (Or, if we haven't read the NF for + * this channel yet, the SW default for this chip/band will + * be used.) + */ + h_base = &chan->nf_cal_hist.base; + } else { + /* use the home channel NF info */ + h_base = &AH_PRIVATE(ah)->nf_cal_hist.base; + } +#endif + OS_MEMCPY(nf, h_base->priv_nf, sizeof(h_base->priv_nf)); +} + +HAL_BOOL +ar9300_load_nf(struct ath_hal *ah, int16_t nf[]) +{ + int i, j; + int32_t val; + /* XXX where are EXT regs defined */ + const u_int32_t ar9300_cca_regs[] = { + AR_PHY_CCA_0, + AR_PHY_CCA_1, + AR_PHY_CCA_2, + AR_PHY_EXT_CCA, + AR_PHY_EXT_CCA_1, + AR_PHY_EXT_CCA_2, + }; + u_int8_t chainmask; + + /* + * Force NF calibration for all chains, otherwise Vista station + * would conduct a bad performance + */ + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { + chainmask = 0x9; + } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah)) { + chainmask = 0x1b; + } else { + chainmask = 0x3F; + } + + /* + * Write filtered NF values into max_cca_pwr register parameter + * so we can load below. + */ + for (i = 0; i < NUM_NF_READINGS; i++) { + if (chainmask & (1 << i)) { + val = OS_REG_READ(ah, ar9300_cca_regs[i]); + val &= 0xFFFFFE00; + val |= (((u_int32_t)(nf[i]) << 1) & 0x1ff); + OS_REG_WRITE(ah, ar9300_cca_regs[i], val); + } + } + + /* + * Load software filtered NF value into baseband internal min_cca_pwr + * variable. + */ + OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); + OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); + OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); + + /* Wait for load to complete, should be fast, a few 10s of us. */ + /* Changed the max delay 250us back to 10000us, since 250us often + * results in NF load timeout and causes deaf condition + * during stress testing 12/12/2009 + */ + for (j = 0; j < 10000; j++) { + if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0){ + break; + } + OS_DELAY(10); + } + if (j == 10000) { + /* + * We timed out waiting for the noisefloor to load, probably + * due to an in-progress rx. Simply return here and allow + * the load plenty of time to complete before the next + * calibration interval. We need to avoid trying to load -50 + * (which happens below) while the previous load is still in + * progress as this can cause rx deafness (see EV 66368,62830). + * Instead by returning here, the baseband nf cal will + * just be capped by our present noisefloor until the next + * calibration timer. + */ + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "%s: *** TIMEOUT while waiting for nf to load: " + "AR_PHY_AGC_CONTROL=0x%x ***\n", + __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); + return AH_FALSE; + } + + /* + * Restore max_cca_power register parameter again so that we're not capped + * by the median we just loaded. This will be initial (and max) value + * of next noise floor calibration the baseband does. + */ + for (i = 0; i < NUM_NF_READINGS; i++) { + if (chainmask & (1 << i)) { + val = OS_REG_READ(ah, ar9300_cca_regs[i]); + val &= 0xFFFFFE00; + val |= (((u_int32_t)(-50) << 1) & 0x1ff); + OS_REG_WRITE(ah, ar9300_cca_regs[i], val); + } + } + return AH_TRUE; +} + +/* ar9300_per_calibration + * Generic calibration routine. + * Recalibrate the lower PHY chips to account for temperature/environment + * changes. + */ +inline static void +ar9300_per_calibration(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan, + u_int8_t rxchainmask, HAL_CAL_LIST *curr_cal, HAL_BOOL *is_cal_done) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + /* Cal is assumed not done until explicitly set below */ + *is_cal_done = AH_FALSE; + + /* Calibration in progress. */ + if (curr_cal->cal_state == CAL_RUNNING) { + /* Check to see if it has finished. */ + if (!(OS_REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { + int i, num_chains = 0; + for (i = 0; i < AR9300_MAX_CHAINS; i++) { + if (rxchainmask & (1 << i)) { + num_chains++; + } + } + + /* + * Accumulate cal measures for active chains + */ + curr_cal->cal_data->cal_collect(ah, num_chains); + + ahp->ah_cal_samples++; + + if (ahp->ah_cal_samples >= curr_cal->cal_data->cal_num_samples) { + /* + * Process accumulated data + */ + curr_cal->cal_data->cal_post_proc(ah, num_chains); + + /* Calibration has finished. */ + ichan->cal_valid |= curr_cal->cal_data->cal_type; + curr_cal->cal_state = CAL_DONE; + *is_cal_done = AH_TRUE; + } else { + /* Set-up collection of another sub-sample until we + * get desired number + */ + ar9300_setup_calibration(ah, curr_cal); + } + } + } else if (!(ichan->cal_valid & curr_cal->cal_data->cal_type)) { + /* If current cal is marked invalid in channel, kick it off */ + ar9300_reset_calibration(ah, curr_cal); + } +} + +static void +ar9300_start_nf_cal(struct ath_hal *ah) +{ + OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); + OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); + OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); + AH9300(ah)->nf_tsf32 = ar9300_get_tsf32(ah); +} + +/* ar9300_calibration + * Wrapper for a more generic Calibration routine. Primarily to abstract to + * upper layers whether there is 1 or more calibrations to be run. + */ +HAL_BOOL +ar9300_calibration(struct ath_hal *ah, HAL_CHANNEL *chan, u_int8_t rxchainmask, + HAL_BOOL do_nf_cal, HAL_BOOL *is_cal_done, int is_scan, + u_int32_t *sched_cals) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_CAL_LIST *curr_cal = ahp->ah_cal_list_curr; + HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); + int16_t nf_buf[NUM_NF_READINGS]; + + *is_cal_done = AH_TRUE; + + + /* XXX: For initial wasp bringup - disable periodic calibration */ + /* Invalid channel check */ + if (ichan == AH_NULL) { + HALDEBUG(ah, HAL_DEBUG_CHANNEL, + "%s: invalid channel %u/0x%x; no mapping\n", + __func__, chan->channel, chan->channel_flags); + return AH_FALSE; + } + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Entering, Doing NF Cal = %d\n", __func__, do_nf_cal); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s: Chain 0 Rx IQ Cal Correction 0x%08x\n", + __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); + if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah) && !AR_SREV_APHRODITE(ah)) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Chain 1 Rx IQ Cal Correction 0x%08x\n", + __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B1)); + if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Chain 2 Rx IQ Cal Correction 0x%08x\n", + __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B2)); + } + } + + OS_MARK(ah, AH_MARK_PERCAL, chan->channel); + + /* For given calibration: + * 1. Call generic cal routine + * 2. When this cal is done (is_cal_done) if we have more cals waiting + * (eg after reset), mask this to upper layers by not propagating + * is_cal_done if it is set to TRUE. + * Instead, change is_cal_done to FALSE and setup the waiting cal(s) + * to be run. + */ + if (curr_cal && (curr_cal->cal_data->cal_type & *sched_cals) && + (curr_cal->cal_state == CAL_RUNNING || + curr_cal->cal_state == CAL_WAITING)) + { + ar9300_per_calibration(ah, ichan, rxchainmask, curr_cal, is_cal_done); + + if (*is_cal_done == AH_TRUE) { + ahp->ah_cal_list_curr = curr_cal = curr_cal->cal_next; + + if (curr_cal && curr_cal->cal_state == CAL_WAITING) { + *is_cal_done = AH_FALSE; + ar9300_reset_calibration(ah, curr_cal); + } else { + *sched_cals &= ~IQ_MISMATCH_CAL; + } + } + } + + /* Do NF cal only at longer intervals */ + if (do_nf_cal) { + int nf_done; + + /* Get the value from the previous NF cal and update history buffer */ + nf_done = ar9300_store_new_nf(ah, ichan, is_scan); + if (ichan->channel_flags & CHANNEL_CW_INT) { + chan->channel_flags |= CHANNEL_CW_INT; + } + ichan->channel_flags &= (~CHANNEL_CW_INT); + + if (nf_done) { + /* + * Load the NF from history buffer of the current channel. + * NF is slow time-variant, so it is OK to use a historical value. + */ + ar9300_get_nf_hist_base(ah, + AH_PRIVATE(ah)->ah_curchan, is_scan, nf_buf); + ar9300_load_nf(ah, nf_buf); + + /* start NF calibration, without updating BB NF register*/ + ar9300_start_nf_cal(ah); + } + } + return AH_TRUE; +} + +/* ar9300_iq_cal_collect + * Collect data from HW to later perform IQ Mismatch Calibration + */ +void +ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int i; + + /* + * Accumulate IQ cal measures for active chains + */ + for (i = 0; i < num_chains; i++) { + ahp->ah_total_power_meas_i[i] = OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); + ahp->ah_total_power_meas_q[i] = OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); + ahp->ah_total_iq_corr_meas[i] = + (int32_t) OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%d: Chn %d " + "Reg Offset(0x%04x)pmi=0x%08x; " + "Reg Offset(0x%04x)pmq=0x%08x; " + "Reg Offset (0x%04x)iqcm=0x%08x;\n", + ahp->ah_cal_samples, + i, + (unsigned) AR_PHY_CAL_MEAS_0(i), + ahp->ah_total_power_meas_i[i], + (unsigned) AR_PHY_CAL_MEAS_1(i), + ahp->ah_total_power_meas_q[i], + (unsigned) AR_PHY_CAL_MEAS_2(i), + ahp->ah_total_iq_corr_meas[i]); + } +} + +/* ar9300_iq_calibration + * Use HW data to perform IQ Mismatch Calibration + */ +void +ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t power_meas_q, power_meas_i, iq_corr_meas; + u_int32_t q_coff_denom, i_coff_denom; + int32_t q_coff, i_coff; + int iq_corr_neg, i; + static const u_int32_t offset_array[3] = { + AR_PHY_RX_IQCAL_CORR_B0, + AR_PHY_RX_IQCAL_CORR_B1, + AR_PHY_RX_IQCAL_CORR_B2, + }; + + for (i = 0; i < num_chains; i++) { + power_meas_i = ahp->ah_total_power_meas_i[i]; + power_meas_q = ahp->ah_total_power_meas_q[i]; + iq_corr_meas = ahp->ah_total_iq_corr_meas[i]; + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "Starting IQ Cal and Correction for Chain %d\n", i); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "Orignal: Chn %diq_corr_meas = 0x%08x\n", + i, ahp->ah_total_iq_corr_meas[i]); + + iq_corr_neg = 0; + + /* iq_corr_meas is always negative. */ + if (iq_corr_meas > 0x80000000) { + iq_corr_meas = (0xffffffff - iq_corr_meas) + 1; + iq_corr_neg = 1; + } + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "Chn %d pwr_meas_i = 0x%08x\n", i, power_meas_i); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "Chn %d pwr_meas_q = 0x%08x\n", i, power_meas_q); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "iq_corr_neg is 0x%08x\n", iq_corr_neg); + + i_coff_denom = (power_meas_i / 2 + power_meas_q / 2) / 256; + q_coff_denom = power_meas_q / 64; + + /* Protect against divide-by-0 */ + if ((i_coff_denom != 0) && (q_coff_denom != 0)) { + /* IQ corr_meas is already negated if iqcorr_neg == 1 */ + i_coff = iq_corr_meas / i_coff_denom; + q_coff = power_meas_i / q_coff_denom - 64; + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "Chn %d i_coff = 0x%08x\n", i, i_coff); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "Chn %d q_coff = 0x%08x\n", i, q_coff); + + /* Force bounds on i_coff */ + if (i_coff >= 63) { + i_coff = 63; + } else if (i_coff <= -63) { + i_coff = -63; + } + + /* Negate i_coff if iq_corr_neg == 0 */ + if (iq_corr_neg == 0x0) { + i_coff = -i_coff; + } + + /* Force bounds on q_coff */ + if (q_coff >= 63) { + q_coff = 63; + } else if (q_coff <= -63) { + q_coff = -63; + } + + i_coff = i_coff & 0x7f; + q_coff = q_coff & 0x7f; + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "Chn %d : i_coff = 0x%x q_coff = 0x%x\n", i, i_coff, q_coff); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "Register offset (0x%04x) before update = 0x%x\n", + offset_array[i], OS_REG_READ(ah, offset_array[i])); + + OS_REG_RMW_FIELD(ah, offset_array[i], + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff); + OS_REG_RMW_FIELD(ah, offset_array[i], + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff); + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "Register offset (0x%04x) QI COFF (bitfields 0x%08x) " + "after update = 0x%x\n", + offset_array[i], AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, + OS_REG_READ(ah, offset_array[i])); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) " + "after update = 0x%x\n", + offset_array[i], AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, + OS_REG_READ(ah, offset_array[i])); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "IQ Cal and Correction done for Chain %d\n", i); + } + } + + OS_REG_SET_BIT(ah, + AR_PHY_RX_IQCAL_CORR_B0, AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "IQ Cal and Correction (offset 0x%04x) enabled " + "(bit position 0x%08x). New Value 0x%08x\n", + (unsigned) (AR_PHY_RX_IQCAL_CORR_B0), + AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE, + OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); +} + +/* + * Set a limit on the overall output power. Used for dynamic + * transmit power control and the like. + * + * NB: limit is in units of 0.5 dbM. + */ +HAL_BOOL +ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit, + u_int16_t extra_txpow, u_int16_t tpc_in_db) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + HAL_CHANNEL_INTERNAL *ichan = ahpriv->ah_curchan; + HAL_CHANNEL *chan = (HAL_CHANNEL *)ichan; + + if (NULL == chan) { + return AH_FALSE; + } + ahpriv->ah_power_limit = AH_MIN(limit, MAX_RATE_POWER); + ahpriv->ah_extra_txpow = extra_txpow; + + if(chan == NULL) { + return AH_FALSE; + } + if (ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, ichan, + ath_hal_getctl(ah, chan), ath_hal_getantennaallowed(ah, chan), + ath_hal_get_twice_max_regpower(ahpriv, ichan, chan), + AH_MIN(MAX_RATE_POWER, ahpriv->ah_power_limit)) != HAL_OK) + { + return AH_FALSE; + } + return AH_TRUE; +} + +/* + * Exported call to check for a recent gain reading and return + * the current state of the thermal calibration gain engine. + */ +HAL_RFGAIN +ar9300_get_rfgain(struct ath_hal *ah) +{ + return HAL_RFGAIN_INACTIVE; +} + +#define HAL_GREEN_AP_RX_MASK 0x1 + +static inline void +ar9300_init_chain_masks(struct ath_hal *ah, int rx_chainmask, int tx_chainmask) +{ + if (AH_PRIVATE(ah)->green_ap_ps_on ) { + rx_chainmask = HAL_GREEN_AP_RX_MASK; + } + if (rx_chainmask == 0x5) { + OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); + } + OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); + OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); + + /* + * Adaptive Power Management: + * Some 3 stream chips exceed the PCIe power requirements. + * This workaround will reduce power consumption by using 2 tx chains + * for 1 and 2 stream rates (5 GHz only). + * + * Set the self gen mask to 2 tx chains when APM is enabled. + * + */ + if (AH_PRIVATE(ah)->ah_caps.hal_enable_apm && (tx_chainmask == 0x7)) { + OS_REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); + } + else { + OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); + } + + if (tx_chainmask == 0x5) { + OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); + } +} + +/* + * Override INI values with chip specific configuration. + */ +static inline void +ar9300_override_ini(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + u_int32_t val; + HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + + /* + * Set the RX_ABORT and RX_DIS and clear it only after + * RXE is set for MAC. This prevents frames with + * corrupted descriptor status. + */ + OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); + /* + * For Merlin and above, there is a new feature that allows Multicast + * search based on both MAC Address and Key ID. + * By default, this feature is enabled. + * But since the driver is not using this feature, we switch it off; + * otherwise multicast search based on MAC addr only will fail. + */ + val = OS_REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); + OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, + val | AR_BUG_58603_FIX_ENABLE | AR_AGG_WEP_ENABLE); + + + /* Osprey revision specific configuration */ + + /* Osprey 2.0+ - if SW RAC support is disabled, must also disable + * the Osprey 2.0 hardware RAC fix. + */ + if (p_cap->hal_isr_rac_support == AH_FALSE) { + OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_MISSING_TX_INTR_FIX_ENABLE); + } + + /* try to enable old pal if it is needed for h/w green tx */ + ar9300_hwgreentx_set_pal_spare(ah, 1); +} + +static inline void +ar9300_prog_ini(struct ath_hal *ah, struct ar9300_ini_array *ini_arr, + int column) +{ + int i, reg_writes = 0; + + /* New INI format: Array may be undefined (pre, core, post arrays) */ + if (ini_arr->ia_array == NULL) { + return; + } + + /* + * New INI format: Pre, core, and post arrays for a given subsystem may be + * modal (> 2 columns) or non-modal (2 columns). + * Determine if the array is non-modal and force the column to 1. + */ + if (column >= ini_arr->ia_columns) { + column = 1; + } + + for (i = 0; i < ini_arr->ia_rows; i++) { + u_int32_t reg = INI_RA(ini_arr, i, 0); + u_int32_t val = INI_RA(ini_arr, i, column); + + /* + ** Determine if this is a shift register value + ** (reg >= 0x16000 && reg < 0x17000 for Osprey) , + ** and insert the configured delay if so. + ** -this delay is not required for Osprey (EV#71410) + */ + OS_REG_WRITE(ah, reg, val); + WAR_6773(reg_writes); + + } +} + +static inline HAL_STATUS +ar9300_process_ini(struct ath_hal *ah, HAL_CHANNEL *chan, + HAL_CHANNEL_INTERNAL *ichan, HAL_HT_MACMODE macmode) +{ + int reg_writes = 0; + struct ath_hal_9300 *ahp = AH9300(ah); + u_int modes_index, modes_txgaintable_index = 0; + int i; + HAL_STATUS status; + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + /* Setup the indices for the next set of register array writes */ + /* TODO: + * If the channel marker is indicative of the current mode rather + * than capability, we do not need to check the phy mode below. + */ + switch (chan->channel_flags & CHANNEL_ALL) { + case CHANNEL_A: + case CHANNEL_A_HT20: + if (AR_SREV_SCORPION(ah)){ + if (chan->channel <= 5350){ + modes_txgaintable_index = 1; + }else if ((chan->channel > 5350) && (chan->channel <= 5600)){ + modes_txgaintable_index = 3; + }else if (chan->channel > 5600){ + modes_txgaintable_index = 5; + } + } + modes_index = 1; + break; + + case CHANNEL_A_HT40PLUS: + case CHANNEL_A_HT40MINUS: + if (AR_SREV_SCORPION(ah)){ + if (chan->channel <= 5350){ + modes_txgaintable_index = 2; + }else if ((chan->channel > 5350) && (chan->channel <= 5600)){ + modes_txgaintable_index = 4; + }else if (chan->channel > 5600){ + modes_txgaintable_index = 6; + } + } + modes_index = 2; + break; + + case CHANNEL_PUREG: + case CHANNEL_G_HT20: + case CHANNEL_B: + if (AR_SREV_SCORPION(ah)){ + modes_txgaintable_index = 8; + } + modes_index = 4; + break; + + case CHANNEL_G_HT40PLUS: + case CHANNEL_G_HT40MINUS: + if (AR_SREV_SCORPION(ah)){ + modes_txgaintable_index = 7; + } + modes_index = 3; + break; + + case CHANNEL_108G: + modes_index = 5; + break; + + default: + HALASSERT(0); + return HAL_EINVAL; + } + +#if 0 + /* Set correct Baseband to analog shift setting to access analog chips. */ + OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); +#endif + + HALDEBUG(ah, HAL_DEBUG_RESET, + "ar9300_process_ini: " + "Skipping OS-REG-WRITE(ah, AR-PHY(0), 0x00000007)\n"); + HALDEBUG(ah, HAL_DEBUG_RESET, + "ar9300_process_ini: no ADDac programming\n"); + + + /* + * Osprey 2.0+ - new INI format. + * Each subsystem has a pre, core, and post array. + */ + for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { + ar9300_prog_ini(ah, &ahp->ah_ini_soc[i], modes_index); + ar9300_prog_ini(ah, &ahp->ah_ini_mac[i], modes_index); + ar9300_prog_ini(ah, &ahp->ah_ini_bb[i], modes_index); + ar9300_prog_ini(ah, &ahp->ah_ini_radio[i], modes_index); + if ((i == ATH_INI_POST) && (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah))) { + ar9300_prog_ini(ah, &ahp->ah_ini_radio_post_sys2ant, modes_index); + } + + } + + if (!(AR_SREV_SOC(ah))) { + /* Doubler issue : Some board doesn't work well with MCS15. Turn off doubler after freq locking is complete*/ + //ath_hal_printf(ah, "%s[%d] ==== before reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)); + OS_REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); /*Set synthon, synthover */ + //ath_hal_printf(ah, "%s[%d] ==== after reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)); + + OS_REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); /*Set synthon, synthover */ + OS_REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); /*Set synthon, synthover */ + OS_DELAY(200); + + //ath_hal_printf(ah, "%s[%d] ==== before reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)); + OS_REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); /* clr synthon */ + OS_REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); /* clr synthon */ + OS_REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); /* clr synthon */ + //ath_hal_printf(ah, "%s[%d] ==== after reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)); + + OS_DELAY(1); + + //ath_hal_printf(ah, "%s[%d] ==== before reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)); + OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); /* set synthon */ + OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); /* set synthon */ + OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); /* set synthon */ + //ath_hal_printf(ah, "%s[%d] ==== after reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)); + + OS_DELAY(200); + + //ath_hal_printf(ah, "%s[%d] ==== before reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_SYNTH12, OS_REG_READ(ah, AR_PHY_65NM_CH0_SYNTH12)); + OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12, AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf); + //OS_REG_CLR_BIT(ah, AR_PHY_65NM_CH0_SYNTH12, 1<< 16); /* clr charge pump */ + //ath_hal_printf(ah, "%s[%d] ==== After reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_SYNTH12, OS_REG_READ(ah, AR_PHY_65NM_CH0_SYNTH12)); + + OS_REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); /*Clr synthon, synthover */ + OS_REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); /*Clr synthon, synthover */ + OS_REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); /*Clr synthon, synthover */ + //ath_hal_printf(ah, "%s[%d] ==== after reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)); + } + + /* Write rxgain Array Parameters */ + REG_WRITE_ARRAY(&ahp->ah_ini_modes_rxgain, 1, reg_writes); + HALDEBUG(ah, HAL_DEBUG_RESET, "ar9300_process_ini: Rx Gain programming\n"); + + if (AR_SREV_SCORPION(ah)) { + /* Write rxgain bounds Array */ + REG_WRITE_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, modes_index, reg_writes); + HALDEBUG(ah, HAL_DEBUG_RESET, "ar9300_process_ini: Rx Gain table bounds programming\n"); + } + /* UB124 xLNA settings */ + if (AR_SREV_WASP(ah) && ar9300_rx_gain_index_get(ah) == 2) { +#define REG_WRITE(_reg,_val) *((volatile u_int32_t *)(_reg)) = (_val); +#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) + u_int32_t val; + /* B8040000: bit[0]=0, bit[3]=0; */ + val = REG_READ(0xB8040000); + val &= 0xfffffff6; + REG_WRITE(0xB8040000, val); + /* B804002c: bit[31:24]=0x2e; bit[7:0]=0x2f; */ + val = REG_READ(0xB804002c); + val &= 0x00ffff00; + val |= 0x2e00002f; + REG_WRITE(0xB804002c, val); + /* B804006c: bit[1]=1; */ + val = REG_READ(0xB804006c); + val |= 0x2; + REG_WRITE(0xB804006c, val); +#undef REG_READ +#undef REG_WRITE + } + + + /* Write txgain Array Parameters */ + if (AR_SREV_SCORPION(ah)) { + REG_WRITE_ARRAY(&ahp->ah_ini_modes_txgain, modes_txgaintable_index, + reg_writes); + }else{ + REG_WRITE_ARRAY(&ahp->ah_ini_modes_txgain, modes_index, reg_writes); + } + HALDEBUG(ah, HAL_DEBUG_RESET, "ar9300_process_ini: Tx Gain programming\n"); + + + /* For 5GHz channels requiring Fast Clock, apply different modal values */ + if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { + HALDEBUG(ah, HAL_DEBUG_RESET, + "%s: Fast clock enabled, use special ini values\n", __func__); + REG_WRITE_ARRAY(&ahp->ah_ini_modes_additional, modes_index, reg_writes); + } + + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah)) { + HALDEBUG(ah, HAL_DEBUG_RESET, + "%s: use xtal ini for AH9300(ah)->clk_25mhz: %d\n", + __func__, AH9300(ah)->clk_25mhz); + REG_WRITE_ARRAY( + &ahp->ah_ini_modes_additional, 1/*modes_index*/, reg_writes); + } + + if (AR_SREV_WASP(ah) && (AH9300(ah)->clk_25mhz == 0)) { + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Apply 40MHz ini settings\n", __func__); + REG_WRITE_ARRAY( + &ahp->ah_ini_modes_additional_40mhz, 1/*modesIndex*/, reg_writes); + } + + if (2484 == chan->channel) { + ar9300_prog_ini(ah, &ahp->ah_ini_japan2484, 1); + } + +#if 0 + if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) { + ar9300_prog_ini(ah, &ahp->ah_ini_BTCOEX_MAX_TXPWR, 1); + } +#endif + + /* Override INI with chip specific configuration */ + ar9300_override_ini(ah, chan); + + /* Setup 11n MAC/Phy mode registers */ + ar9300_set_11n_regs(ah, chan, macmode); + + /* + * Moved ar9300_init_chain_masks() here to ensure the swap bit is set before + * the pdadc table is written. Swap must occur before any radio dependent + * replicated register access. The pdadc curve addressing in particular + * depends on the consistent setting of the swap bit. + */ + ar9300_init_chain_masks(ah, ahp->ah_rx_chainmask, ahp->ah_tx_chainmask); + + /* + * Setup the transmit power values. + * + * After the public to private hal channel mapping, ichan contains the + * valid regulatory power value. + * ath_hal_getctl and ath_hal_getantennaallowed look up ichan from chan. + */ + status = ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, ichan, + ath_hal_getctl(ah, chan), ath_hal_getantennaallowed(ah, chan), + ath_hal_get_twice_max_regpower(ahpriv, ichan, chan), + AH_MIN(MAX_RATE_POWER, ahpriv->ah_power_limit)); + if (status != HAL_OK) { + HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, + "%s: error init'ing transmit power\n", __func__); + return HAL_EIO; + } + + + return HAL_OK; +#undef N +} + +/* ar9300_is_cal_supp + * Determine if calibration is supported by device and channel flags + */ +inline static HAL_BOOL +ar9300_is_cal_supp(struct ath_hal *ah, HAL_CHANNEL *chan, + HAL_CAL_TYPES cal_type) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL retval = AH_FALSE; + + switch (cal_type & ahp->ah_supp_cals) { + case IQ_MISMATCH_CAL: + /* Run IQ Mismatch for non-CCK only */ + if (!IS_CHAN_B(chan)) { + retval = AH_TRUE; + } + break; + case TEMP_COMP_CAL: + retval = AH_TRUE; + break; + } + + return retval; +} + + +#if 0 +/* ar9285_pa_cal + * PA Calibration for Kite 1.1 and later versions of Kite. + * - from system's team. + */ +static inline void +ar9285_pa_cal(struct ath_hal *ah) +{ + u_int32_t reg_val; + int i, lo_gn, offs_6_1, offs_0; + u_int8_t reflo; + u_int32_t phy_test2_reg_val, phy_adc_ctl_reg_val; + u_int32_t an_top2_reg_val, phy_tst_dac_reg_val; + + + /* Kite 1.1 WAR for Bug 35666 + * Increase the LDO value to 1.28V before accessing analog Reg */ + if (AR_SREV_KITE_11(ah)) { + OS_REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14) ); + } + an_top2_reg_val = OS_REG_READ(ah, AR9285_AN_TOP2); + + /* set pdv2i pdrxtxbb */ + reg_val = OS_REG_READ(ah, AR9285_AN_RXTXBB1); + reg_val |= ((0x1 << 5) | (0x1 << 7)); + OS_REG_WRITE(ah, AR9285_AN_RXTXBB1, reg_val); + + /* clear pwddb */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G7); + reg_val &= 0xfffffffd; + OS_REG_WRITE(ah, AR9285_AN_RF2G7, reg_val); + + /* clear enpacal */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G1); + reg_val &= 0xfffff7ff; + OS_REG_WRITE(ah, AR9285_AN_RF2G1, reg_val); + + /* set offcal */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G2); + reg_val |= (0x1 << 12); + OS_REG_WRITE(ah, AR9285_AN_RF2G2, reg_val); + + /* set pdpadrv1=pdpadrv2=pdpaout=1 */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G1); + reg_val |= (0x7 << 23); + OS_REG_WRITE(ah, AR9285_AN_RF2G1, reg_val); + + /* Read back reflo, increase it by 1 and write it. */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3); + reflo = ((reg_val >> 26) & 0x7); + + if (reflo < 0x7) { + reflo++; + } + reg_val = ((reg_val & 0xe3ffffff) | (reflo << 26)); + OS_REG_WRITE(ah, AR9285_AN_RF2G3, reg_val); + + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3); + reflo = ((reg_val >> 26) & 0x7); + + /* use TX single carrier to transmit + * dac const + * reg. 15 + */ + phy_tst_dac_reg_val = OS_REG_READ(ah, AR_PHY_TSTDAC_CONST); + OS_REG_WRITE(ah, AR_PHY_TSTDAC_CONST, ((0x7ff << 11) | 0x7ff)); + reg_val = OS_REG_READ(ah, AR_PHY_TSTDAC_CONST); + + /* source is dac const + * reg. 2 + */ + phy_test2_reg_val = OS_REG_READ(ah, AR_PHY_TEST2); + OS_REG_WRITE(ah, AR_PHY_TEST2, ((0x1 << 7) | (0x1 << 1))); + reg_val = OS_REG_READ(ah, AR_PHY_TEST2); + + /* set dac on + * reg. 11 + */ + phy_adc_ctl_reg_val = OS_REG_READ(ah, AR_PHY_ADC_CTL); + OS_REG_WRITE(ah, AR_PHY_ADC_CTL, 0x80008000); + reg_val = OS_REG_READ(ah, AR_PHY_ADC_CTL); + + OS_REG_WRITE(ah, AR9285_AN_TOP2, (0x1 << 27) | (0x1 << 17) | (0x1 << 16) | + (0x1 << 14) | (0x1 << 12) | (0x1 << 11) | + (0x1 << 7) | (0x1 << 5)); + + OS_DELAY(10); /* 10 usec */ + + /* clear off[6:0] */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G6); + reg_val &= 0xfc0fffff; + OS_REG_WRITE(ah, AR9285_AN_RF2G6, reg_val); + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3); + reg_val &= 0xfdffffff; + OS_REG_WRITE(ah, AR9285_AN_RF2G3, reg_val); + + offs_6_1 = 0; + for (i = 6; i > 0; i--) { + /* sef off[$k]==1 */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G6); + reg_val &= 0xfc0fffff; + reg_val = reg_val | (0x1 << (19 + i)) | ((offs_6_1) << 20); + OS_REG_WRITE(ah, AR9285_AN_RF2G6, reg_val); + lo_gn = (OS_REG_READ(ah, AR9285_AN_RF2G9)) & 0x1; + offs_6_1 = offs_6_1 | (lo_gn << (i - 1)); + } + + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G6); + reg_val &= 0xfc0fffff; + reg_val = reg_val | ((offs_6_1 - 1) << 20); + OS_REG_WRITE(ah, AR9285_AN_RF2G6, reg_val); + + /* set off_0=1; */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3); + reg_val &= 0xfdffffff; + reg_val = reg_val | (0x1 << 25); + OS_REG_WRITE(ah, AR9285_AN_RF2G3, reg_val); + + lo_gn = OS_REG_READ(ah, AR9285_AN_RF2G9) & 0x1; + offs_0 = lo_gn; + + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3); + reg_val &= 0xfdffffff; + reg_val = reg_val | (offs_0 << 25); + OS_REG_WRITE(ah, AR9285_AN_RF2G3, reg_val); + + /* clear pdv2i */ + reg_val = OS_REG_READ(ah, AR9285_AN_RXTXBB1); + reg_val &= 0xffffff5f; + OS_REG_WRITE(ah, AR9285_AN_RXTXBB1, reg_val); + + /* set enpacal */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G1); + reg_val |= (0x1 << 11); + OS_REG_WRITE(ah, AR9285_AN_RF2G1, reg_val); + + /* clear offcal */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G2); + reg_val &= 0xffffefff; + OS_REG_WRITE(ah, AR9285_AN_RF2G2, reg_val); + + /* set pdpadrv1=pdpadrv2=pdpaout=0 */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G1); + reg_val &= 0xfc7fffff; + OS_REG_WRITE(ah, AR9285_AN_RF2G1, reg_val); + + /* Read back reflo, decrease it by 1 and write it. */ + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3); + reflo = (reg_val >> 26) & 0x7; + if (reflo) { + reflo--; + } + reg_val = ((reg_val & 0xe3ffffff) | (reflo << 26)); + OS_REG_WRITE(ah, AR9285_AN_RF2G3, reg_val); + reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3); + reflo = (reg_val >> 26) & 0x7; + + /* write back registers */ + OS_REG_WRITE(ah, AR_PHY_TSTDAC_CONST, phy_tst_dac_reg_val); + OS_REG_WRITE(ah, AR_PHY_TEST2, phy_test2_reg_val); + OS_REG_WRITE(ah, AR_PHY_ADC_CTL, phy_adc_ctl_reg_val); + OS_REG_WRITE(ah, AR9285_AN_TOP2, an_top2_reg_val); + + /* Kite 1.1 WAR for Bug 35666 + * Decrease the LDO value back to 1.20V */ + if (AR_SREV_KITE_11(ah)) { + OS_REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT); + } +} +#endif + +/* ar9300_run_init_cals + * Runs non-periodic calibrations + */ +inline static HAL_BOOL +ar9300_run_init_cals(struct ath_hal *ah, int init_cal_count) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_CHANNEL_INTERNAL ichan; /* bogus */ + HAL_BOOL is_cal_done; + HAL_CAL_LIST *curr_cal; + int i; + + curr_cal = ahp->ah_cal_list_curr; + if (curr_cal == AH_NULL) { + return AH_FALSE; + } + ichan.cal_valid = 0; + + for (i = 0; i < init_cal_count; i++) { + /* Reset this Cal */ + ar9300_reset_calibration(ah, curr_cal); + /* Poll for offset calibration complete */ + if (!ath_hal_wait( + ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL, 0, AH_WAIT_TIMEOUT)) + { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Cal %d failed to complete in 100ms.\n", + __func__, curr_cal->cal_data->cal_type); + /* Re-initialize list pointers for periodic cals */ + ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr + = AH_NULL; + return AH_FALSE; + } + /* Run this cal */ + ar9300_per_calibration( + ah, &ichan, ahp->ah_rx_chainmask, curr_cal, &is_cal_done); + if (is_cal_done == AH_FALSE) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Not able to run Init Cal %d.\n", __func__, + curr_cal->cal_data->cal_type); + } + if (curr_cal->cal_next) { + curr_cal = curr_cal->cal_next; + } + } + + /* Re-initialize list pointers for periodic cals */ + ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = AH_NULL; + return AH_TRUE; +} + +#if 0 +static void +ar9300_tx_carrier_leak_war(struct ath_hal *ah) +{ + unsigned long tx_gain_table_max; + unsigned long reg_bb_cl_map_0_b0 = 0xffffffff; + unsigned long reg_bb_cl_map_1_b0 = 0xffffffff; + unsigned long reg_bb_cl_map_2_b0 = 0xffffffff; + unsigned long reg_bb_cl_map_3_b0 = 0xffffffff; + unsigned long tx_gain, cal_run = 0; + unsigned long cal_gain[AR_PHY_TPC_7_TX_GAIN_TABLE_MAX + 1]; + unsigned long cal_gain_index[AR_PHY_TPC_7_TX_GAIN_TABLE_MAX + 1]; + unsigned long new_gain[AR_PHY_TPC_7_TX_GAIN_TABLE_MAX + 1]; + int i, j; + + OS_MEMSET(new_gain, 0, sizeof(new_gain)); + /*printf(" Running TxCarrierLeakWAR\n");*/ + + /* process tx gain table, we use cl_map_hw_gen=0. */ + OS_REG_RMW_FIELD(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_MAP_HW_GEN, 0); + + //the table we used is txbb_gc[2:0], 1dB[2:1]. + tx_gain_table_max = OS_REG_READ_FIELD(ah, + AR_PHY_TPC_7, AR_PHY_TPC_7_TX_GAIN_TABLE_MAX); + + for (i = 0; i <= tx_gain_table_max; i++) { + tx_gain = OS_REG_READ(ah, AR_PHY_TXGAIN_TAB(1) + i * 4); + cal_gain[i] = (((tx_gain >> 5)& 0x7) << 2) | + (((tx_gain >> 1) & 0x3) << 0); + if (i == 0) { + cal_gain_index[i] = cal_run; + new_gain[i] = 1; + cal_run++; + } else { + new_gain[i] = 1; + for (j = 0; j < i; j++) { + /* + printf("i=%d, j=%d cal_gain[$i]=0x%04x\n", i, j, cal_gain[i]); + */ + if (new_gain[i]) { + if ((cal_gain[i] != cal_gain[j])) { + new_gain[i] = 1; + } else { + /* if old gain found, use old cal_run value. */ + new_gain[i] = 0; + cal_gain_index[i] = cal_gain_index[j]; + } + } + } + /* if new gain found, increase cal_run */ + if (new_gain[i] == 1) { + cal_gain_index[i] = cal_run; + cal_run++; + } + } + + reg_bb_cl_map_0_b0 = (reg_bb_cl_map_0_b0 & ~(0x1 << i)) | + ((cal_gain_index[i] >> 0 & 0x1) << i); + reg_bb_cl_map_1_b0 = (reg_bb_cl_map_1_b0 & ~(0x1 << i)) | + ((cal_gain_index[i] >> 1 & 0x1) << i); + reg_bb_cl_map_2_b0 = (reg_bb_cl_map_2_b0 & ~(0x1 << i)) | + ((cal_gain_index[i] >> 2 & 0x1) << i); + reg_bb_cl_map_3_b0 = (reg_bb_cl_map_3_b0 & ~(0x1 << i)) | + ((cal_gain_index[i] >> 3 & 0x1) << i); + + /* + printf("i=%2d, cal_gain[$i]= 0x%04x, cal_run= %d, " + "cal_gain_index[i]=%d, new_gain[i] = %d\n", + i, cal_gain[i], cal_run, cal_gain_index[i], new_gain[i]); + */ + } + OS_REG_WRITE(ah, AR_PHY_CL_MAP_0_B0, reg_bb_cl_map_0_b0); + OS_REG_WRITE(ah, AR_PHY_CL_MAP_1_B0, reg_bb_cl_map_1_b0); + OS_REG_WRITE(ah, AR_PHY_CL_MAP_2_B0, reg_bb_cl_map_2_b0); + OS_REG_WRITE(ah, AR_PHY_CL_MAP_3_B0, reg_bb_cl_map_3_b0); + if (AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_CL_MAP_0_B1, reg_bb_cl_map_0_b0); + OS_REG_WRITE(ah, AR_PHY_CL_MAP_1_B1, reg_bb_cl_map_1_b0); + OS_REG_WRITE(ah, AR_PHY_CL_MAP_2_B1, reg_bb_cl_map_2_b0); + OS_REG_WRITE(ah, AR_PHY_CL_MAP_3_B1, reg_bb_cl_map_3_b0); + } +} +#endif + + +static inline void +ar9300_invalidate_saved_cals(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan) +{ +#if ATH_SUPPORT_CAL_REUSE + if (AH_PRIVATE(ah)->ah_config.ath_hal_cal_reuse & + ATH_CAL_REUSE_REDO_IN_FULL_RESET) + { + ichan->one_time_txiqcal_done = AH_FALSE; + ichan->one_time_txclcal_done = AH_FALSE; + } +#endif +} + +static inline HAL_BOOL +ar9300_restore_rtt_cals(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan) +{ + HAL_BOOL restore_status = AH_FALSE; + + return restore_status; +} + +/* ar9300_init_cal + * Initialize Calibration infrastructure + */ +static inline HAL_BOOL +ar9300_init_cal_internal(struct ath_hal *ah, HAL_CHANNEL *chan, + HAL_CHANNEL_INTERNAL *ichan, HAL_BOOL enable_rtt, + HAL_BOOL do_rtt_cal, HAL_BOOL skip_if_none, HAL_BOOL apply_last_iqcorr) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL txiqcal_success_flag = AH_FALSE; + HAL_BOOL cal_done = AH_FALSE; + int iqcal_idx = 0; + HAL_BOOL do_sep_iq_cal = AH_FALSE; + HAL_BOOL do_agc_cal = do_rtt_cal; + HAL_BOOL is_cal_reusable = AH_TRUE; +#if ATH_SUPPORT_CAL_REUSE + HAL_BOOL cal_reuse_enable = AH_PRIVATE(ah)->ah_config.ath_hal_cal_reuse & + ATH_CAL_REUSE_ENABLE; + HAL_BOOL clc_success = AH_FALSE; + int32_t ch_idx, j, cl_tab_reg; + u_int32_t BB_cl_tab_entry = MAX_BB_CL_TABLE_ENTRY; + u_int32_t BB_cl_tab_b[AR9300_MAX_CHAINS] = { + AR_PHY_CL_TAB_0, + AR_PHY_CL_TAB_1, + AR_PHY_CL_TAB_2 + }; +#endif + + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { + /* Hornet: 1 x 1 */ + ahp->ah_rx_cal_chainmask = 0x1; + ahp->ah_tx_cal_chainmask = 0x1; + } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah)) { + /* Wasp/Jupiter: 2 x 2 */ + ahp->ah_rx_cal_chainmask = 0x3; + ahp->ah_tx_cal_chainmask = 0x3; + } else { + /* + * Osprey needs to be configured for the correct chain mode + * before running AGC/TxIQ cals. + */ + if (ahp->ah_enterprise_mode & AR_ENT_OTP_CHAIN2_DISABLE) { + /* chain 2 disabled - 2 chain mode */ + ahp->ah_rx_cal_chainmask = 0x3; + ahp->ah_tx_cal_chainmask = 0x3; + } else { + ahp->ah_rx_cal_chainmask = 0x7; + ahp->ah_tx_cal_chainmask = 0x7; + } + } + ar9300_init_chain_masks(ah, ahp->ah_rx_cal_chainmask, ahp->ah_tx_cal_chainmask); + + + if (ahp->tx_cl_cal_enable) { +#if ATH_SUPPORT_CAL_REUSE + /* disable Carrie Leak or set do_agc_cal accordingly */ + if (cal_reuse_enable && ichan->one_time_txclcal_done) + { + OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); + } else +#endif /* ATH_SUPPORT_CAL_REUSE */ + { + OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); + do_agc_cal = AH_TRUE; + } + } + + /* Do Tx IQ Calibration here for osprey hornet and wasp */ + /* XXX: For initial wasp bringup - check and enable this */ + /* EV 74233: Tx IQ fails to complete for half/quarter rates */ + if (!(IS_CHAN_HALF_RATE(ichan) || IS_CHAN_QUARTER_RATE(ichan))) { + if (ahp->tx_iq_cal_enable) { + /* this should be eventually moved to INI file */ + OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1(ah), + AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT); + + /* + * For poseidon and later chips, + * Tx IQ cal HW run will be a part of AGC calibration + */ + if (ahp->tx_iq_cal_during_agc_cal) { + /* + * txiqcal_success_flag always set to 1 to run + * ar9300_tx_iq_cal_post_proc + * if following AGC cal passes + */ +#if ATH_SUPPORT_CAL_REUSE + if (!cal_reuse_enable || !ichan->one_time_txiqcal_done) + { + txiqcal_success_flag = AH_TRUE; + OS_REG_WRITE(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah), + OS_REG_READ(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah)) | + AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL); + } else { + OS_REG_WRITE(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah), + OS_REG_READ(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah)) & + (~AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)); + } +#else + if (OS_REG_READ_FIELD(ah, + AR_PHY_TX_IQCAL_CONTROL_0(ah), + AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)){ + if (apply_last_iqcorr == AH_TRUE) { + OS_REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah), + AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL); + txiqcal_success_flag = AH_FALSE; + } else { + txiqcal_success_flag = AH_TRUE; + } + }else{ + txiqcal_success_flag = AH_FALSE; + } +#endif + if (txiqcal_success_flag) { + do_agc_cal = AH_TRUE; + } + } else +#if ATH_SUPPORT_CAL_REUSE + if (!cal_reuse_enable || !ichan->one_time_txiqcal_done) +#endif + { + do_sep_iq_cal = AH_TRUE; + do_agc_cal = AH_TRUE; + } + } + } + +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && + IS_CHAN_2GHZ(ichan) && + (ahp->ah_mci_bt_state == MCI_BT_AWAKE) && + do_agc_cal && + !(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_DISABLE_MCI_CAL)) + { + u_int32_t payload[4] = {0, 0, 0, 0}; + + /* Send CAL_REQ only when BT is AWAKE. */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send WLAN_CAL_REQ 0x%X\n", + __func__, ahp->ah_mci_wlan_cal_seq); + MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_REQ); + payload[MCI_GPM_WLAN_CAL_W_SEQUENCE] = ahp->ah_mci_wlan_cal_seq++; + ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, AH_TRUE, AH_FALSE); + + /* Wait BT_CAL_GRANT for 50ms */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Wait for BT_CAL_GRANT\n", __func__); + if (ar9300_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_GRANT, 0, 50000)) + { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Got BT_CAL_GRANT.\n", __func__); + } + else { + is_cal_reusable = AH_FALSE; + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: BT is not responding.\n", __func__); + } + } +#endif /* ATH_SUPPORT_MCI */ + + if (do_sep_iq_cal) + { + /* enable Tx IQ Calibration HW for osprey/hornet/wasp */ + txiqcal_success_flag = ar9300_tx_iq_cal_hw_run(ah); + OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); + OS_DELAY(5); + OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); + } +#if 0 + if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah)) { + ar9300_tx_carrier_leak_war(ah); + } +#endif + /* + * Calibrate the AGC + * + * Tx IQ cal is a part of AGC cal for Jupiter/Poseidon, etc. + * please enable the bit of txiqcal_control_0[31] in INI file + * for Jupiter/Poseidon/etc. + */ + if(!AR_SREV_SCORPION(ah)) { + if (do_agc_cal || !skip_if_none) { + OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, + OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); + + /* Poll for offset calibration complete */ + cal_done = ath_hal_wait(ah, + AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT); + if (!cal_done) { + HALDEBUG(ah, HAL_DEBUG_FCS_RTT, + "(FCS) CAL NOT DONE!!! - %d\n", ichan->channel); + } + } else { + cal_done = AH_TRUE; + } + /* + * Tx IQ cal post-processing in SW + * This part of code should be common to all chips, + * no chip specific code for Jupiter/Posdeion except for register names. + */ + if (txiqcal_success_flag) { + ar9300_tx_iq_cal_post_proc(ah,ichan, 1, 1,is_cal_reusable,false); + } + } else { + if (!txiqcal_success_flag) { + OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, + OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); + if (!ath_hal_wait( ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, + 0, AH_WAIT_TIMEOUT)) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: offset calibration failed to complete in 1ms; " + "noisy environment?\n", __func__); + return AH_FALSE; + } + if (apply_last_iqcorr == AH_TRUE) { + ar9300_tx_iq_cal_post_proc(ah, ichan, 0, 0, is_cal_reusable, AH_TRUE); + } + } else { + for (iqcal_idx=0;iqcal_idxah_caps.hal_mci_support && + IS_CHAN_2GHZ(ichan) && + (ahp->ah_mci_bt_state == MCI_BT_AWAKE) && + do_agc_cal && + !(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config & + ATH_MCI_CONFIG_DISABLE_MCI_CAL)) + { + u_int32_t payload[4] = {0, 0, 0, 0}; + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send WLAN_CAL_DONE 0x%X\n", + __func__, ahp->ah_mci_wlan_cal_done); + MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE); + payload[MCI_GPM_WLAN_CAL_W_SEQUENCE] = ahp->ah_mci_wlan_cal_done++; + ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, AH_TRUE, AH_FALSE); + } +#endif /* ATH_SUPPORT_MCI */ + + + if (!cal_done && !AR_SREV_SCORPION(ah) ) + { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: offset calibration failed to complete in 1ms; " + "noisy environment?\n", __func__); + return AH_FALSE; + } + +#if 0 + /* Beacon stuck fix, refer to EV 120056 */ + if(IS_CHAN_2GHZ(chan) && AR_SREV_SCORPION(ah)) + OS_REG_WRITE(ah, AR_PHY_TIMING5, OS_REG_READ(ah,AR_PHY_TIMING5) & ~AR_PHY_TIMING5_CYCPWR_THR1_ENABLE); +#endif + +#if 0 + /* Do PA Calibration */ + if (AR_SREV_KITE(ah) && AR_SREV_KITE_11_OR_LATER(ah)) { + ar9285_pa_cal(ah); + } +#endif + +#if ATH_SUPPORT_CAL_REUSE + if (ichan->one_time_txiqcal_done) { + ar9300_tx_iq_cal_apply(ah, ichan); + HALDEBUG(ah, HAL_DEBUG_FCS_RTT, + "(FCS) TXIQCAL applied - %d\n", ichan->channel); + } +#endif /* ATH_SUPPORT_CAL_REUSE */ + +#if ATH_SUPPORT_CAL_REUSE + if (cal_reuse_enable && ahp->tx_cl_cal_enable) + { + clc_success = (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & + AR_PHY_AGC_CONTROL_CLC_SUCCESS) ? 1 : 0; + + if (ichan->one_time_txclcal_done) + { + /* reapply CL cal results */ + for (ch_idx = 0; ch_idx < AR9300_MAX_CHAINS; ch_idx++) { + if ((ahp->ah_tx_cal_chainmask & (1 << ch_idx)) == 0) { + continue; + } + cl_tab_reg = BB_cl_tab_b[ch_idx]; + for (j = 0; j < BB_cl_tab_entry; j++) { + OS_REG_WRITE(ah, cl_tab_reg, ichan->tx_clcal[ch_idx][j]); + cl_tab_reg += 4;; + } + } + HALDEBUG(ah, HAL_DEBUG_FCS_RTT, + "(FCS) TX CL CAL applied - %d\n", ichan->channel); + } + else if (is_cal_reusable && clc_success) { + /* save CL cal results */ + for (ch_idx = 0; ch_idx < AR9300_MAX_CHAINS; ch_idx++) { + if ((ahp->ah_tx_cal_chainmask & (1 << ch_idx)) == 0) { + continue; + } + cl_tab_reg = BB_cl_tab_b[ch_idx]; + for (j = 0; j < BB_cl_tab_entry; j++) { + ichan->tx_clcal[ch_idx][j] = OS_REG_READ(ah, cl_tab_reg); + cl_tab_reg += 4; + } + } + ichan->one_time_txclcal_done = AH_TRUE; + HALDEBUG(ah, HAL_DEBUG_FCS_RTT, + "(FCS) TX CL CAL saved - %d\n", ichan->channel); + } + } +#endif /* ATH_SUPPORT_CAL_REUSE */ + + + /* Revert chainmasks to their original values before NF cal */ + ar9300_init_chain_masks(ah, ahp->ah_rx_chainmask, ahp->ah_tx_chainmask); + +#if !FIX_NOISE_FLOOR + /* + * Do NF calibration after DC offset and other CALs. + * Per system engineers, noise floor value can sometimes be 20 dB + * higher than normal value if DC offset and noise floor cal are + * triggered at the same time. + */ + OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, + OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF); +#endif + + /* Initialize list pointers */ + ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = AH_NULL; + + /* + * Enable IQ, ADC Gain, ADC DC Offset Cals + */ + /* Setup all non-periodic, init time only calibrations */ + /* XXX: Init DC Offset not working yet */ +#ifdef not_yet + if (AH_TRUE == ar9300_is_cal_supp(ah, chan, ADC_DC_INIT_CAL)) { + INIT_CAL(&ahp->ah_adc_dc_cal_init_data); + INSERT_CAL(ahp, &ahp->ah_adc_dc_cal_init_data); + } + + /* Initialize current pointer to first element in list */ + ahp->ah_cal_list_curr = ahp->ah_cal_list; + + if (ahp->ah_cal_list_curr) { + if (ar9300_run_init_cals(ah, 0) == AH_FALSE) { + return AH_FALSE; + } + } +#endif + /* end - Init time calibrations */ + + /* If Cals are supported, add them to list via INIT/INSERT_CAL */ + if (AH_TRUE == ar9300_is_cal_supp(ah, chan, IQ_MISMATCH_CAL)) { + INIT_CAL(&ahp->ah_iq_cal_data); + INSERT_CAL(ahp, &ahp->ah_iq_cal_data); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: enabling IQ Calibration.\n", __func__); + } + if (AH_TRUE == ar9300_is_cal_supp(ah, chan, TEMP_COMP_CAL)) { + INIT_CAL(&ahp->ah_temp_comp_cal_data); + INSERT_CAL(ahp, &ahp->ah_temp_comp_cal_data); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: enabling Temperature Compensation Calibration.\n", __func__); + } + + /* Initialize current pointer to first element in list */ + ahp->ah_cal_list_curr = ahp->ah_cal_list; + + /* Reset state within current cal */ + if (ahp->ah_cal_list_curr) { + ar9300_reset_calibration(ah, ahp->ah_cal_list_curr); + } + + /* Mark all calibrations on this channel as being invalid */ + ichan->cal_valid = 0; + + return AH_TRUE; +} + +static inline HAL_BOOL +ar9300_init_cal(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL skip_if_none, HAL_BOOL apply_last_iqcorr) +{ + HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); + HAL_BOOL do_rtt_cal = AH_TRUE; + HAL_BOOL enable_rtt = AH_FALSE; + + HALASSERT(ichan); + + + + return ar9300_init_cal_internal(ah, chan, ichan, enable_rtt, do_rtt_cal, skip_if_none, apply_last_iqcorr); +} + +/* ar9300_reset_cal_valid + * Entry point for upper layers to restart current cal. + * Reset the calibration valid bit in channel. + */ +void +ar9300_reset_cal_valid(struct ath_hal *ah, HAL_CHANNEL *chan, + HAL_BOOL *is_cal_done, u_int32_t cal_type) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); + HAL_CAL_LIST *curr_cal = ahp->ah_cal_list_curr; + + *is_cal_done = AH_TRUE; + + if (curr_cal == AH_NULL) { + return; + } + if (ichan == AH_NULL) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: invalid channel %u/0x%x; no mapping\n", + __func__, chan->channel, chan->channel_flags); + return; + } + + if (!(cal_type & IQ_MISMATCH_CAL)) { + *is_cal_done = AH_FALSE; + return; + } + + /* Expected that this calibration has run before, post-reset. + * Current state should be done + */ + if (curr_cal->cal_state != CAL_DONE) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Calibration state incorrect, %d\n", + __func__, curr_cal->cal_state); + return; + } + + /* Verify Cal is supported on this channel */ + if (ar9300_is_cal_supp(ah, chan, curr_cal->cal_data->cal_type) == AH_FALSE) { + return; + } + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Resetting Cal %d state for channel %u/0x%x\n", __func__, + curr_cal->cal_data->cal_type, chan->channel, chan->channel_flags); + + /* Disable cal validity in channel */ + ichan->cal_valid &= ~curr_cal->cal_data->cal_type; + curr_cal->cal_state = CAL_WAITING; + /* Indicate to upper layers that we need polling */ + *is_cal_done = AH_FALSE; +} + +static inline void +ar9300_set_dma(struct ath_hal *ah) +{ + u_int32_t regval; + struct ath_hal_9300 *ahp = AH9300(ah); + +#if 0 + /* + * set AHB_MODE not to do cacheline prefetches + */ + regval = OS_REG_READ(ah, AR_AHB_MODE); + OS_REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); +#endif + + /* + * let mac dma reads be in 128 byte chunks + */ + regval = OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; + OS_REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); + + /* + * Restore TX Trigger Level to its pre-reset value. + * The initial value depends on whether aggregation is enabled, and is + * adjusted whenever underruns are detected. + */ + /* + OS_REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, AH_PRIVATE(ah)->ah_tx_trig_level); + */ + /* + * Osprey 1.0 bug (EV 61936). Don't change trigger level from .ini default. + * Osprey 2.0 - hardware recommends using the default INI settings. + */ +#if 0 + OS_REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, 0x3f); +#endif + /* + * let mac dma writes be in 128 byte chunks + */ + regval = OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; + OS_REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); + + /* + * Setup receive FIFO threshold to hold off TX activities + */ + OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); + + /* + * reduce the number of usable entries in PCU TXBUF to avoid + * wrap around bugs. (bug 20428) + */ + + if (AR_SREV_WASP(ah) && + (AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_12)) { + /* Wasp 1.3 fix for EV#85395 requires usable entries + * to be set to 0x500 + */ + OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 0x500); + } else { + OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE); + } + + /* + * Enable HPQ for UAPSD + */ + if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) { + OS_REG_WRITE(ah, AR_HP_Q_CONTROL, + AR_HPQ_ENABLE | AR_HPQ_UAPSD | AR_HPQ_UAPSD_TRIGGER_EN); + } + + /* + * set the transmit status ring + */ + ar9300_reset_tx_status_ring(ah); + + /* + * set rxbp threshold. Must be non-zero for RX_EOL to occur. + * For Osprey 2.0+, keep the original thresholds + * otherwise performance is lost due to excessive RX EOL interrupts. + */ + OS_REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); + OS_REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); + + /* + * set receive buffer size. + */ + if (ahp->rx_buf_size) { + OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size); + } +} + +static inline void +ar9300_init_bb(struct ath_hal *ah, HAL_CHANNEL *chan) +{ + u_int32_t synth_delay; + + /* + * Wait for the frequency synth to settle (synth goes on + * via AR_PHY_ACTIVE_EN). Read the phy active delay register. + * Value is in 100ns increments. + */ + synth_delay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; + if (IS_CHAN_CCK(chan)) { + synth_delay = (4 * synth_delay) / 22; + } else { + synth_delay /= 10; + } + + /* Activate the PHY (includes baseband activate + synthesizer on) */ + OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); + + /* + * There is an issue if the AP starts the calibration before + * the base band timeout completes. This could result in the + * rx_clear AH_FALSE triggering. As a workaround we add delay an + * extra BASE_ACTIVATE_DELAY usecs to ensure this condition + * does not happen. + */ + OS_DELAY(synth_delay + BASE_ACTIVATE_DELAY); +} + +static inline void +ar9300_init_interrupt_masks(struct ath_hal *ah, HAL_OPMODE opmode) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t msi_cfg = 0; + u_int32_t sync_en_def = AR9300_INTR_SYNC_DEFAULT; + + /* + * Setup interrupt handling. Note that ar9300_reset_tx_queue + * manipulates the secondary IMR's as queues are enabled + * and disabled. This is done with RMW ops to insure the + * settings we make here are preserved. + */ + ahp->ah_mask_reg = + AR_IMR_TXERR | AR_IMR_TXURN | + AR_IMR_RXERR | AR_IMR_RXORN | + AR_IMR_BCNMISC; + + if (ahp->ah_intr_mitigation_rx) { + /* enable interrupt mitigation for rx */ + ahp->ah_mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR | AR_IMR_RXOK_HP; + msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR; + } else { + ahp->ah_mask_reg |= AR_IMR_RXOK_LP | AR_IMR_RXOK_HP; + msi_cfg |= AR_INTCFG_MSI_RXOK; + } + if (ahp->ah_intr_mitigation_tx) { + /* enable interrupt mitigation for tx */ + ahp->ah_mask_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; + msi_cfg |= AR_INTCFG_MSI_TXINTM | AR_INTCFG_MSI_TXMINTR; + } else { + ahp->ah_mask_reg |= AR_IMR_TXOK; + msi_cfg |= AR_INTCFG_MSI_TXOK; + } + if (opmode == HAL_M_HOSTAP) { + ahp->ah_mask_reg |= AR_IMR_MIB; + } + + OS_REG_WRITE(ah, AR_IMR, ahp->ah_mask_reg); + OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); + ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2); + + if (AH_PRIVATE(ah)->ah_config.ath_hal_enable_msi) { + /* Cache MSI register value */ + ahp->ah_msi_reg = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_MSI)); + ahp->ah_msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN; + if (AR_SREV_POSEIDON(ah)) { + ahp->ah_msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64; + } else { + ahp->ah_msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR; + } + /* Program MSI configuration */ + OS_REG_WRITE(ah, AR_INTCFG, msi_cfg); + } + + /* + * debug - enable to see all synchronous interrupts status + */ + /* Clear any pending sync cause interrupts */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE), 0xFFFFFFFF); + + /* Allow host interface sync interrupt sources to set cause bit */ + if (AR_SREV_POSEIDON(ah)) { + sync_en_def = AR9300_INTR_SYNC_DEF_NO_HOST1_PERR; + } + else if (AR_SREV_WASP(ah)) { + sync_en_def = AR9340_INTR_SYNC_DEFAULT; + } + OS_REG_WRITE(ah, + AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE), sync_en_def); + + /* _Disable_ host interface sync interrupt when cause bits set */ + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK), 0); + + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE), 0); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK), 0); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE), 0); + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK), 0); +} + +static inline void +ar9300_init_qos(struct ath_hal *ah) +{ + OS_REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); /* XXX magic */ + OS_REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); /* XXX magic */ + + /* Turn on NOACK Support for QoS packets */ + OS_REG_WRITE(ah, AR_QOS_NO_ACK, + SM(2, AR_QOS_NO_ACK_TWO_BIT) | + SM(5, AR_QOS_NO_ACK_BIT_OFF) | + SM(0, AR_QOS_NO_ACK_BYTE_OFF)); + + /* + * initialize TXOP for all TIDs + */ + OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); + OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); + OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); + OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); + OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); +} + +static inline void +ar9300_init_user_settings(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + /* Restore user-specified settings */ + HALDEBUG(ah, HAL_DEBUG_RESET, + "--AP %s ahp->ah_misc_mode 0x%x\n", __func__, ahp->ah_misc_mode); + if (ahp->ah_misc_mode != 0) { + OS_REG_WRITE(ah, + AR_PCU_MISC, OS_REG_READ(ah, AR_PCU_MISC) | ahp->ah_misc_mode); + } + if (ahp->ah_get_plcp_hdr) { + OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM); + } + if (ahp->ah_slot_time != (u_int) -1) { + ar9300_set_slot_time(ah, ahp->ah_slot_time); + } + if (ahp->ah_ack_timeout != (u_int) -1) { + ar9300_set_ack_timeout(ah, ahp->ah_ack_timeout); + } + if (AH_PRIVATE(ah)->ah_diagreg != 0) { + OS_REG_SET_BIT(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); + } + if (ahp->ah_beacon_rssi_threshold != 0) { + ar9300_set_hw_beacon_rssi_threshold(ah, ahp->ah_beacon_rssi_threshold); + } +#ifdef ATH_SUPPORT_DFS + if (ahp->ah_cac_quiet_enabled) { + ar9300_cac_tx_quiet(ah, 1); + } +#endif /* ATH_SUPPORT_DFS */ +} + +int +ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq) +{ + struct ath_hal_private *ap = AH_PRIVATE(ah); + int i, j; + + for (i = 0; i < len; i++) { + freq[i] = 0; + } + + *enable = ap->ah_config.ath_hal_spur_mode; + for (i = 0, j = 0; i < AR_EEPROM_MODAL_SPURS; i++) { + if (ap->ah_config.ath_hal_spur_chans[i][0] != AR_NO_SPUR) { + freq[j++] = ap->ah_config.ath_hal_spur_chans[i][0]; + HALDEBUG(ah, HAL_DEBUG_ANI, + "1. get spur %d\n", ap->ah_config.ath_hal_spur_chans[i][0]); + } + if (ap->ah_config.ath_hal_spur_chans[i][1] != AR_NO_SPUR) { + freq[j++] = ap->ah_config.ath_hal_spur_chans[i][1]; + HALDEBUG(ah, HAL_DEBUG_ANI, + "2. get spur %d\n", ap->ah_config.ath_hal_spur_chans[i][1]); + } + } + + return 0; +} + +#define ATH_HAL_2GHZ_FREQ_MIN 20000 +#define ATH_HAL_2GHZ_FREQ_MAX 29999 +#define ATH_HAL_5GHZ_FREQ_MIN 50000 +#define ATH_HAL_5GHZ_FREQ_MAX 59999 + +int +ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq) +{ + struct ath_hal_private *ap = AH_PRIVATE(ah); + int i, j, k; + + ap->ah_config.ath_hal_spur_mode = enable; + + if (ap->ah_config.ath_hal_spur_mode == SPUR_ENABLE_IOCTL) { + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { + ap->ah_config.ath_hal_spur_chans[i][0] = AR_NO_SPUR; + ap->ah_config.ath_hal_spur_chans[i][1] = AR_NO_SPUR; + } + for (i = 0, j = 0, k = 0; i < len; i++) { + if (freq[i] > ATH_HAL_2GHZ_FREQ_MIN && + freq[i] < ATH_HAL_2GHZ_FREQ_MAX) + { + /* 2GHz Spur */ + if (j < AR_EEPROM_MODAL_SPURS) { + ap->ah_config.ath_hal_spur_chans[j++][1] = freq[i]; + HALDEBUG(ah, HAL_DEBUG_ANI, "1 set spur %d\n", freq[i]); + } + } else if (freq[i] > ATH_HAL_5GHZ_FREQ_MIN && + freq[i] < ATH_HAL_5GHZ_FREQ_MAX) + { + /* 5Ghz Spur */ + if (k < AR_EEPROM_MODAL_SPURS) { + ap->ah_config.ath_hal_spur_chans[k++][0] = freq[i]; + HALDEBUG(ah, HAL_DEBUG_ANI, "2 set spur %d\n", freq[i]); + } + } + } + } + + return 0; +} + +#define ar9300_check_op_mode(_opmode) \ + ((_opmode == HAL_M_STA) || (_opmode == HAL_M_IBSS) ||\ + (_opmode == HAL_M_HOSTAP) || (_opmode == HAL_M_MONITOR)) + + + + +#ifndef ATH_NF_PER_CHAN +/* +* To fixed first reset noise floor value not correct issue +* For ART need it to fixed low rate sens too low issue +*/ +static int +First_NFCal(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan, + int is_scan, HAL_CHANNEL *chan) +{ + HAL_NFCAL_HIST_FULL *nfh; + int i, j, k; + int16_t nfarray[NUM_NF_READINGS] = {0}; + int is_2g = 0; + int nf_hist_len; + int stats = 0; + + int16_t nf_buf[NUM_NF_READINGS]; +#define IS(_c, _f) (((_c)->channel_flags & _f) || 0) + + + if ((!is_scan) && + chan->channel == AH_PRIVATE(ah)->ah_curchan->channel) + { + nfh = &AH_PRIVATE(ah)->nf_cal_hist; + } else { + nfh = (HAL_NFCAL_HIST_FULL *) &ichan->nf_cal_hist; + } + + ar9300_start_nf_cal(ah); + for (j = 0; j < 10000; j++) { + if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0){ + break; + } + OS_DELAY(10); + } + if (j < 10000) { + is_2g = IS(ichan, CHANNEL_2GHZ); + ar9300_upload_noise_floor(ah, is_2g, nfarray); + + if (is_scan) { + /* + * This channel's NF cal info is just a HAL_NFCAL_HIST_SMALL struct + * rather than a HAL_NFCAL_HIST_FULL struct. + * As long as we only use the first history element of nf_cal_buffer + * (nf_cal_buffer[0][0:NUM_NF_READINGS-1]), we can use + * HAL_NFCAL_HIST_SMALL and HAL_NFCAL_HIST_FULL interchangeably. + */ + nfh = (HAL_NFCAL_HIST_FULL *) &ichan->nf_cal_hist; + nf_hist_len = HAL_NF_CAL_HIST_LEN_SMALL; + } else { + nfh = &AH_PRIVATE(ah)->nf_cal_hist; + nf_hist_len = HAL_NF_CAL_HIST_LEN_FULL; + } + + for (i = 0; i < NUM_NF_READINGS; i ++) { + for (k = 0; k < HAL_NF_CAL_HIST_LEN_FULL; k++) { + nfh->nf_cal_buffer[k][i] = nfarray[i]; + } + nfh->base.priv_nf[i] = ar9300_limit_nf_range(ah, + ar9300_get_nf_hist_mid(ah, nfh, i, nf_hist_len)); + } + + + //ar9300StoreNewNf(ah, ichan, is_scan); + + /* + * See if the NF value from the old channel should be + * retained when switching to a new channel. + * TBD: this may need to be changed, as it wipes out the + * purpose of saving NF values for each channel. + */ + for (i = 0; i < NUM_NF_READINGS; i++) + { + if (IS_CHAN_2GHZ(chan)) + { + if (nfh->nf_cal_buffer[0][i] < + AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ) + { + ichan->nf_cal_hist.nf_cal_buffer[0][i] = + AH_PRIVATE(ah)->nf_cal_hist.nf_cal_buffer[0][i]; + } + } else { + if (AR_SREV_AR9580(ah)) { + if (nfh->nf_cal_buffer[0][i] < + AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ) + { + ichan->nf_cal_hist.nf_cal_buffer[0][i] = + AH_PRIVATE(ah)->nf_cal_hist.nf_cal_buffer[0][i]; + } + } else { + if (nfh->nf_cal_buffer[0][i] < + AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ) + { + ichan->nf_cal_hist.nf_cal_buffer[0][i] = + AH_PRIVATE(ah)->nf_cal_hist.nf_cal_buffer[0][i]; + } + } + } + } + /* + * Copy the channel's NF buffer, which may have been modified + * just above here, to the full NF history buffer. + */ + ar9300_reset_nf_hist_buff(ah, ichan); + ar9300_get_nf_hist_base(ah, + AH_PRIVATE(ah)->ah_curchan, is_scan, nf_buf); + ar9300_load_nf(ah, nf_buf); + stats = 0; + } else { + stats = 1; + } +#undef IS + return stats; +} +#endif + + +/* + * Places the device in and out of reset and then places sane + * values in the registers based on EEPROM config, initialization + * vectors (as determined by the mode), and station configuration + * + * b_channel_change is used to preserve DMA/PCU registers across + * a HW Reset during channel change. + */ +HAL_BOOL +ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, HAL_CHANNEL *chan, + HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask, + HAL_HT_EXTPROTSPACING extprotspacing, HAL_BOOL b_channel_change, + HAL_STATUS *status, int is_scan) +{ +#define FAIL(_code) do { ecode = _code; goto bad; } while (0) + u_int32_t save_led_state; + struct ath_hal_9300 *ahp = AH9300(ah); + struct ath_hal_private *ap = AH_PRIVATE(ah); + HAL_CHANNEL_INTERNAL *ichan; + HAL_CHANNEL_INTERNAL *curchan = ap->ah_curchan; +#if ATH_SUPPORT_MCI + HAL_BOOL save_full_sleep = ahp->ah_chip_full_sleep; +#endif + u_int32_t save_def_antenna; + u_int32_t mac_sta_id1; + HAL_STATUS ecode; + int i, rx_chainmask; + int nf_hist_buff_reset = 0; + int16_t nf_buf[NUM_NF_READINGS]; +#ifdef ATH_FORCE_PPM + u_int32_t save_force_val, tmp_reg; +#endif + HAL_BOOL stopped, cal_ret; + HAL_BOOL apply_last_iqcorr = AH_FALSE; + + if (OS_REG_READ(ah, AR_IER) == AR_IER_ENABLE) { + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "** Reset called with WLAN " + "interrupt enabled %08x **\n", ar9300_get_interrupts(ah)); + } + + /* + * Set the status to "ok" by default to cover the cases + * where we return AH_FALSE without going to "bad" + */ + HALASSERT(status); + *status = HAL_OK; + if ((AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable)) { + AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_NONE; + } + +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && + (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah))) + { + ar9300_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan)); + } +#endif + + ahp->ah_ext_prot_spacing = extprotspacing; + ahp->ah_tx_chainmask = txchainmask & ap->ah_caps.hal_tx_chain_mask; + ahp->ah_rx_chainmask = rxchainmask & ap->ah_caps.hal_rx_chain_mask; + ahp->ah_tx_cal_chainmask = ap->ah_caps.hal_tx_chain_mask; + ahp->ah_rx_cal_chainmask = ap->ah_caps.hal_rx_chain_mask; + HALASSERT(ar9300_check_op_mode(opmode)); + + OS_MARK(ah, AH_MARK_RESET, b_channel_change); + + /* + * Map public channel to private. + */ + ichan = ar9300_check_chan(ah, chan); + if (ichan == AH_NULL) { + HALDEBUG(ah, HAL_DEBUG_CHANNEL, + "%s: invalid channel %u/0x%x; no mapping\n", + __func__, chan->channel, chan->channel_flags); + FAIL(HAL_EINVAL); + } + + ichan->paprd_table_write_done = 0; /* Clear PAPRD table write flag */ + chan->paprd_table_write_done = 0; /* Clear PAPRD table write flag */ + + if (ar9300_get_power_mode(ah) != HAL_PM_FULL_SLEEP) { + /* Need to stop RX DMA before reset otherwise chip might hang */ + stopped = ar9300_set_rx_abort(ah, AH_TRUE); /* abort and disable PCU */ + ar9300_set_rx_filter(ah, 0); + stopped &= ar9300_stop_dma_receive(ah, 0); /* stop and disable RX DMA */ + if (!stopped) { + /* + * During the transition from full sleep to reset, + * recv DMA regs are not available to be read + */ + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s[%d]: ar9300_stop_dma_receive failed\n", __func__, __LINE__); + b_channel_change = AH_FALSE; + } + } else { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + "%s[%d]: Chip is already in full sleep\n", __func__, __LINE__); + } + +#if ATH_SUPPORT_MCI + if ((AH_PRIVATE(ah)->ah_caps.hal_mci_support) && + (ahp->ah_mci_bt_state == MCI_BT_CAL_START)) + { + u_int32_t payload[4] = {0, 0, 0, 0}; + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Stop rx for BT cal.\n", __func__); + ahp->ah_mci_bt_state = MCI_BT_CAL; + + /* + * MCIFIX: disable mci interrupt here. This is to avoid SW_MSG_DONE or + * RX_MSG bits to trigger MCI_INT and lead to mci_intr reentry. + */ + ar9300_mci_disable_interrupt(ah); + + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Send WLAN_CAL_GRANT\n", __func__); + MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT); + ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, AH_TRUE, AH_FALSE); + + /* Wait BT calibration to be completed for 25ms */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: BT is calibrating.\n", __func__); + if (ar9300_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE, 0, 25000)) { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: Got BT_CAL_DONE.\n", __func__); + } + else { + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) %s: ### BT cal takes too long. Force bt_state to be bt_awake.\n", + __func__); + } + ahp->ah_mci_bt_state = MCI_BT_AWAKE; + /* MCIFIX: enable mci interrupt here */ + ar9300_mci_enable_interrupt(ah); + + return AH_TRUE; + } +#endif + + /* Bring out of sleep mode */ + if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { + *status = HAL_INV_PMODE; + return AH_FALSE; + } + + /* Check the Rx mitigation config again, it might have changed + * during attach in ath_vap_attach. + */ + if (AH_PRIVATE(ah)->ah_config.ath_hal_intr_mitigation_rx != 0) { + ahp->ah_intr_mitigation_rx = AH_TRUE; + } else { + ahp->ah_intr_mitigation_rx = AH_FALSE; + } + + /* Get the value from the previous NF cal and update history buffer */ + if (curchan && (ahp->ah_chip_full_sleep != AH_TRUE)) { + ar9300_store_new_nf(ah, curchan, is_scan); + } + + /* + * Account for the effect of being in either the 2 GHz or 5 GHz band + * on the nominal, max allowable, and min allowable noise floor values. + */ + ap->nfp = IS_CHAN_2GHZ(chan) ? &ap->nf_2GHz : &ap->nf_5GHz; + + if (AR_SREV_SCORPION(ah) && curchan && (chan->channel == curchan->channel) && + ((chan->channel_flags & (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)) == + (curchan->channel_flags & + (CHANNEL_ALL | CHANNEL_HALF | CHANNEL_QUARTER)))) { + apply_last_iqcorr = AH_TRUE; + } + +#ifndef ATH_NF_PER_CHAN + /* + * If there's only one full-size home-channel NF history buffer + * rather than a full-size NF history buffer per channel, decide + * whether to (re)initialize the home-channel NF buffer. + * If this is just a channel change for a scan, or if the channel + * is not being changed, don't mess up the home channel NF history + * buffer with NF values from this scanned channel. If we're + * changing the home channel to a new channel, reset the home-channel + * NF history buffer with the most accurate NF known for the new channel. + */ + if (!is_scan && (!ap->ah_curchan || + ap->ah_curchan->channel != chan->channel || + ap->ah_curchan->channel_flags != chan->channel_flags)) + { + nf_hist_buff_reset = 1; + ar9300_reset_nf_hist_buff(ah, ichan); + } +#endif + /* + * Fast channel change (Change synthesizer based on channel freq + * without resetting chip) + * Don't do it when + * - Flag is not set + * - Chip is just coming out of full sleep + * - Channel to be set is same as current channel + * - Channel flags are different, like when moving from 2GHz to 5GHz + * channels + * - Merlin: Switching in/out of fast clock enabled channels + * (not currently coded, since fast clock is enabled + * across the 5GHz band + * and we already do a full reset when switching in/out + * of 5GHz channels) + */ + if (b_channel_change && + (ahp->ah_chip_full_sleep != AH_TRUE) && + (AH_PRIVATE(ah)->ah_curchan != AH_NULL) && + ((chan->channel != AH_PRIVATE(ah)->ah_curchan->channel) && + (((CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER) & chan->channel_flags) == + ((CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER) & AH_PRIVATE(ah)->ah_curchan->channel_flags)))) + { + if (ar9300_channel_change(ah, chan, ichan, macmode)) { + chan->channel_flags = ichan->channel_flags; + chan->priv_flags = ichan->priv_flags; + AH_PRIVATE(ah)->ah_curchan->ah_channel_time = 0; + AH_PRIVATE(ah)->ah_curchan->ah_tsf_last = ar9300_get_tsf64(ah); + + /* + * Load the NF from history buffer of the current channel. + * NF is slow time-variant, so it is OK to use a historical value. + */ + ar9300_get_nf_hist_base(ah, + AH_PRIVATE(ah)->ah_curchan, is_scan, nf_buf); + ar9300_load_nf(ah, nf_buf); + + /* start NF calibration, without updating BB NF register*/ + ar9300_start_nf_cal(ah); + + /* + * If channel_change completed and DMA was stopped + * successfully - skip the rest of reset + */ + if (AH9300(ah)->ah_dma_stuck != AH_TRUE) { + WAR_USB_DISABLE_PLL_LOCK_DETECT(ah); +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && ahp->ah_mci_ready) + { + ar9300_mci_2g5g_switch(ah, AH_TRUE); + } +#endif + return AH_TRUE; + } + } + } + +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) { + ar9300_mci_disable_interrupt(ah); + if (ahp->ah_mci_ready && !save_full_sleep) { + ar9300_mci_mute_bt(ah); + OS_DELAY(20); + OS_REG_WRITE(ah, AR_BTCOEX_CTRL, 0); + } + + ahp->ah_mci_bt_state = MCI_BT_SLEEP; + ahp->ah_mci_ready = AH_FALSE; + } +#endif + + AH9300(ah)->ah_dma_stuck = AH_FALSE; +#ifdef ATH_FORCE_PPM + /* Preserve force ppm state */ + save_force_val = + OS_REG_READ(ah, AR_PHY_TIMING2) & + (AR_PHY_TIMING2_USE_FORCE | AR_PHY_TIMING2_FORCE_VAL); +#endif + /* + * Preserve the antenna on a channel change + */ + save_def_antenna = OS_REG_READ(ah, AR_DEF_ANTENNA); + if (0 == ahp->ah_smartantenna_enable ) + { + if (save_def_antenna == 0) { + save_def_antenna = 1; + } + } + + /* Save hardware flag before chip reset clears the register */ + mac_sta_id1 = OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; + + /* Save led state from pci config register */ + save_led_state = OS_REG_READ(ah, AR_CFG_LED) & + (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | + AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); + + /* Mark PHY inactive prior to reset, to be undone in ar9300_init_bb () */ + ar9300_mark_phy_inactive(ah); + + if (!ar9300_chip_reset(ah, chan)) { + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: chip reset failed\n", __func__); + FAIL(HAL_EIO); + } + + OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); + + + /* Disable JTAG */ + OS_REG_SET_BIT(ah, + AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE); + + /* + * Note that ar9300_init_chain_masks() is called from within + * ar9300_process_ini() to ensure the swap bit is set before + * the pdadc table is written. + */ + ecode = ar9300_process_ini(ah, chan, ichan, macmode); + if (ecode != HAL_OK) { + goto bad; + } + + ahp->ah_immunity_on = AH_FALSE; + + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + ahp->tx_iq_cal_enable = OS_REG_READ_FIELD(ah, + AR_PHY_TX_IQCAL_CONTROL_0(ah), + AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL) ? + 1 : 0; + } + ahp->tx_cl_cal_enable = (OS_REG_READ(ah, AR_PHY_CL_CAL_CTL) & + AR_PHY_CL_CAL_ENABLE) ? 1 : 0; + + /* For devices with full HW RIFS Rx support (Sowl/Howl/Merlin, etc), + * restore register settings from prior to reset. + */ + if ((AH_PRIVATE(ah)->ah_curchan != AH_NULL) && + (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK)) + { + /* Re-program RIFS Rx policy after reset */ + ar9300_set_rifs_delay(ah, ahp->ah_rifs_enabled); + } + +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) { + ar9300_mci_reset(ah, AH_FALSE, IS_CHAN_2GHZ(chan), save_full_sleep); + } +#endif + + /* Initialize Management Frame Protection */ + ar9300_init_mfp(ah); + + ahp->ah_immunity_vals[0] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_M1_THRESH_LOW); + ahp->ah_immunity_vals[1] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_M2_THRESH_LOW); + ahp->ah_immunity_vals[2] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR, + AR_PHY_SFCORR_M1_THRESH); + ahp->ah_immunity_vals[3] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR, + AR_PHY_SFCORR_M2_THRESH); + ahp->ah_immunity_vals[4] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR, + AR_PHY_SFCORR_M2COUNT_THR); + ahp->ah_immunity_vals[5] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR_LOW, + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); + + /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ + if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) { + ar9300_set_delta_slope(ah, ichan); + } + + ar9300_spur_mitigate(ah, chan); + if (!ar9300_eeprom_set_board_values(ah, ichan)) { + HALDEBUG(ah, HAL_DEBUG_EEPROM, + "%s: error setting board options\n", __func__); + FAIL(HAL_EIO); + } + +#ifdef ATH_HAL_WAR_REG16284_APH128 + /* temp work around, will be removed. */ + if (AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, 0x16284, 0x1553e000); + } +#endif + + OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); + + OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); + OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) + | mac_sta_id1 + | AR_STA_ID1_RTS_USE_DEF + | (ap->ah_config.ath_hal_6mb_ack ? AR_STA_ID1_ACKCTS_6MB : 0) + | ahp->ah_sta_id1_defaults + ); + ar9300_set_operating_mode(ah, opmode); + + /* Set Venice BSSID mask according to current state */ + OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask)); + OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4)); + + /* Restore previous antenna */ + OS_REG_WRITE(ah, AR_DEF_ANTENNA, save_def_antenna); +#ifdef ATH_FORCE_PPM + /* Restore force ppm state */ + tmp_reg = OS_REG_READ(ah, AR_PHY_TIMING2) & + ~(AR_PHY_TIMING2_USE_FORCE | AR_PHY_TIMING2_FORCE_VAL); + OS_REG_WRITE(ah, AR_PHY_TIMING2, tmp_reg | save_force_val); +#endif + + /* then our BSSID and assocID */ + OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); + OS_REG_WRITE(ah, AR_BSS_ID1, + LE_READ_2(ahp->ah_bssid + 4) | + ((ahp->ah_assoc_id & 0x3fff) << AR_BSS_ID1_AID_S)); + + OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ + + OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR, INIT_RSSI_THR); + + /* HW beacon processing */ + OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_BCN_WEIGHT, + INIT_RSSI_BEACON_WEIGHT); + OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | + AR_HWBCNPROC1_EXCLUDE_TIM_ELM); + if (AH_PRIVATE(ah)->ah_config.ath_hal_beacon_filter_interval) { + OS_REG_RMW_FIELD(ah, AR_HWBCNPROC2, AR_HWBCNPROC2_FILTER_INTERVAL, + AH_PRIVATE(ah)->ah_config.ath_hal_beacon_filter_interval); + OS_REG_SET_BIT(ah, AR_HWBCNPROC2, + AR_HWBCNPROC2_FILTER_INTERVAL_ENABLE); + } + + + /* + * Set Channel now modifies bank 6 parameters for FOWL workaround + * to force rf_pwd_icsyndiv bias current as function of synth + * frequency.Thus must be called after ar9300_process_ini() to ensure + * analog register cache is valid. + */ + if (!ahp->ah_rf_hal.set_channel(ah, ichan)) { + FAIL(HAL_EIO); + } + + + OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); + + /* Set 1:1 QCU to DCU mapping for all queues */ + for (i = 0; i < AR_NUM_DCU; i++) { + OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); + } + + ahp->ah_intr_txqs = 0; + for (i = 0; i < AH_PRIVATE(ah)->ah_caps.hal_total_queues; i++) { + ar9300_reset_tx_queue(ah, i); + } + + ar9300_init_interrupt_masks(ah, opmode); + + /* Reset ier reference count to disabled */ + OS_ATOMIC_SET(&ahp->ah_ier_ref_count, 1); + if (ath_hal_isrfkillenabled(ah)) { + ar9300_enable_rf_kill(ah); + } + + /* must be called AFTER ini is processed */ + ar9300_ani_init_defaults(ah, macmode); + + ar9300_init_qos(ah); + + ar9300_init_user_settings(ah); + + + AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ + + OS_MARK(ah, AH_MARK_RESET_DONE, 0); + + /* + * disable seq number generation in hw + */ + OS_REG_WRITE(ah, AR_STA_ID1, + OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); + + ar9300_set_dma(ah); + + /* + * program OBS bus to see MAC interrupts + */ +#if ATH_SUPPORT_MCI + if (!AH_PRIVATE(ah)->ah_caps.hal_mci_support) { + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 8); + } +#else + OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 8); +#endif + + + /* enabling AR_GTTM_IGNORE_IDLE in GTTM register so that + GTT timer will not increment if the channel idle indicates + the air is busy or NAV is still counting down */ + OS_REG_WRITE(ah, AR_GTTM, AR_GTTM_IGNORE_IDLE); + + /* + * GTT debug mode setting + */ + /* + OS_REG_WRITE(ah, 0x64, 0x00320000); + OS_REG_WRITE(ah, 0x68, 7); + OS_REG_WRITE(ah, 0x4080, 0xC); + */ + /* + * Disable general interrupt mitigation by setting MIRT = 0x0 + * Rx and tx interrupt mitigation are conditionally enabled below. + */ + OS_REG_WRITE(ah, AR_MIRT, 0); + if (ahp->ah_intr_mitigation_rx) { + /* + * Enable Interrupt Mitigation for Rx. + * If no build-specific limits for the rx interrupt mitigation + * timer have been specified, use conservative defaults. + */ + #ifndef AH_RIMT_VAL_LAST + #define AH_RIMT_LAST_MICROSEC 500 + #endif + #ifndef AH_RIMT_VAL_FIRST + #define AH_RIMT_FIRST_MICROSEC 2000 + #endif +#ifndef HOST_OFFLOAD + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC); + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC); +#else + /* lower mitigation level to reduce latency for offload arch. */ + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, + (AH_RIMT_LAST_MICROSEC >> 2)); + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, + (AH_RIMT_FIRST_MICROSEC >> 2)); +#endif + } + + if (ahp->ah_intr_mitigation_tx) { + /* + * Enable Interrupt Mitigation for Tx. + * If no build-specific limits for the tx interrupt mitigation + * timer have been specified, use the values preferred for + * the carrier group's products. + */ + #ifndef AH_TIMT_LAST + #define AH_TIMT_LAST_MICROSEC 300 + #endif + #ifndef AH_TIMT_FIRST + #define AH_TIMT_FIRST_MICROSEC 750 + #endif + OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, AH_TIMT_LAST_MICROSEC); + OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, AH_TIMT_FIRST_MICROSEC); + } + + rx_chainmask = ahp->ah_rx_chainmask; + + OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); + OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); + + ar9300_init_bb(ah, chan); + + /* BB Step 7: Calibration */ + ar9300_invalidate_saved_cals(ah, ichan); + cal_ret = ar9300_init_cal(ah, chan, AH_FALSE, apply_last_iqcorr); + +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && ahp->ah_mci_ready) { + if (IS_CHAN_2GHZ(chan) && + (ahp->ah_mci_bt_state == MCI_BT_SLEEP)) + { + if (ar9300_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) || + ar9300_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) + { + /* + * BT is sleeping. Check if BT wakes up duing WLAN + * calibration. If BT wakes up during WLAN calibration, need + * to go through all message exchanges again and recal. + */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, + "(MCI) ### %s: BT wakes up during WLAN calibration.\n", + __func__); + OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, + AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | + AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE); + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) send REMOTE_RESET\n"); + ar9300_mci_remote_reset(ah, AH_TRUE); + ar9300_mci_send_sys_waking(ah, AH_TRUE); + OS_DELAY(1); + if (IS_CHAN_2GHZ(chan)) { + ar9300_mci_send_lna_transfer(ah, AH_TRUE); + } + ahp->ah_mci_bt_state = MCI_BT_AWAKE; + + /* Redo calibration */ + HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Re-calibrate.\n", + __func__); + ar9300_invalidate_saved_cals(ah, ichan); + cal_ret = ar9300_init_cal(ah, chan, AH_FALSE, ar9300_init_cal); + } + } + ar9300_mci_enable_interrupt(ah); + } +#endif + + if (!cal_ret) { + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Init Cal Failed\n", __func__); + FAIL(HAL_ESELFTEST); + } + + ar9300_init_txbf(ah); +#if 0 + /* + * WAR for owl 1.0 - restore chain mask for 2-chain cfgs after cal + */ + rx_chainmask = ahp->ah_rx_chainmask; + if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { + OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); + OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); + } +#endif + + /* Restore previous led state */ + OS_REG_WRITE(ah, AR_CFG_LED, save_led_state | AR_CFG_SCLK_32KHZ); + +#ifdef ATH_BT_COEX + if (ahp->ah_bt_coex_config_type != HAL_BT_COEX_CFG_NONE) { + ar9300_init_bt_coex(ah); + +#if ATH_SUPPORT_MCI + if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && ahp->ah_mci_ready) { + /* Check BT state again to make sure it's not changed. */ + ar9300_mci_sync_bt_state(ah); + ar9300_mci_2g5g_switch(ah, AH_TRUE); + + if ((ahp->ah_mci_bt_state == MCI_BT_AWAKE) && + (ahp->ah_mci_query_bt == AH_TRUE)) + { + ahp->ah_mci_need_flush_btinfo = AH_TRUE; + } + } +#endif + } +#endif + + /* Start TSF2 for generic timer 8-15. */ + ar9300_start_tsf2(ah); + + /* MIMO Power save setting */ + if (ar9300_get_capability(ah, HAL_CAP_DYNAMIC_SMPS, 0, AH_NULL) == HAL_OK) { + ar9300_set_sm_power_mode(ah, ahp->ah_sm_power_mode); + } + + /* + * For big endian systems turn on swapping for descriptors + */ +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB, 0); + } else { + ar9300_init_cfg_reg(ah); + } +#endif + + if ( AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + OS_REG_RMW(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, AR_CFG_LED_ASSOC_CTL); + } + +#if !(defined(ART_BUILD)) && defined(ATH_SUPPORT_LED) +#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); +#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) +#define ATH_GPIO_OUT_FUNCTION3 0xB8040038 +#define ATH_GPIO_OE 0xB8040000 + if ( AR_SREV_WASP(ah)) { + if (IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan))) { + REG_WRITE(ATH_GPIO_OUT_FUNCTION3, ( REG_READ(ATH_GPIO_OUT_FUNCTION3) & (~(0xff << 8))) | (0x33 << 8) ); + REG_WRITE(ATH_GPIO_OE, ( REG_READ(ATH_GPIO_OE) & (~(0x1 << 13) ))); + } + else { + + /* Disable 2G WLAN LED. During ath_open, reset function is called even before channel is set. + So 2GHz is taken as default and it also blinks. Hence + to avoid both from blinking, disable 2G led while in 5G mode */ + + REG_WRITE(ATH_GPIO_OE, ( REG_READ(ATH_GPIO_OE) | (1 << 13) )); + REG_WRITE(ATH_GPIO_OUT_FUNCTION3, ( REG_READ(ATH_GPIO_OUT_FUNCTION3) & (~(0xff))) | (0x33) ); + REG_WRITE(ATH_GPIO_OE, ( REG_READ(ATH_GPIO_OE) & (~(0x1 << 12) ))); + } + + } + else if (AR_SREV_SCORPION(ah)) { + if (IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan))) { + REG_WRITE(ATH_GPIO_OUT_FUNCTION3, ( REG_READ(ATH_GPIO_OUT_FUNCTION3) & (~(0xff << 8))) | (0x2F << 8) ); + REG_WRITE(ATH_GPIO_OE, (( REG_READ(ATH_GPIO_OE) & (~(0x1 << 13) )) | (0x1 << 12))); + } else if (IS_CHAN_5GHZ((AH_PRIVATE(ah)->ah_curchan))) { + REG_WRITE(ATH_GPIO_OUT_FUNCTION3, ( REG_READ(ATH_GPIO_OUT_FUNCTION3) & (~(0xff))) | (0x2F) ); + REG_WRITE(ATH_GPIO_OE, (( REG_READ(ATH_GPIO_OE) & (~(0x1 << 12) )) | (0x1 << 13))); + } + } +#undef REG_READ +#undef REG_WRITE +#endif + + chan->channel_flags = ichan->channel_flags; + chan->priv_flags = ichan->priv_flags; + +#if FIX_NOISE_FLOOR + ar9300_get_nf_hist_base(ah, AH_PRIVATE(ah)->ah_curchan, is_scan, nf_buf); + ar9300_load_nf(ah, nf_buf); + if (nf_hist_buff_reset == 1) + { + nf_hist_buff_reset = 0; + #ifndef ATH_NF_PER_CHAN + if (First_NFCal(ah, ichan, is_scan, chan)){ + } + #endif /* ATH_NF_PER_CHAN */ + } + else{ + ar9300_start_nf_cal(ah); + } +#endif + +#ifdef AH_SUPPORT_AR9300 + /* BB Panic Watchdog */ + if (ar9300_get_capability(ah, HAL_CAP_BB_PANIC_WATCHDOG, 0, AH_NULL) == + HAL_OK) + { + ar9300_config_bb_panic_watchdog(ah); + } +#endif + + /* While receiving unsupported rate frame receive state machine + * gets into a state 0xb and if phy_restart happens when rx + * state machine is in 0xb state, BB would go hang, if we + * see 0xb state after first bb panic, make sure that we + * disable the phy_restart. + * + * There may be multiple panics, make sure that we always do + * this if we see this panic at least once. This is required + * because reset seems to be writing from INI file. + */ + if ((ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) + == HAL_OK) && (((MS((AH_PRIVATE(ah)->ah_bb_panic_last_status), + AR_PHY_BB_WD_RX_OFDM_SM)) == 0xb) || + AH_PRIVATE(ah)->ah_phyrestart_disabled) ) + { + ar9300_disable_phy_restart(ah, 1); + } + + + + ahp->ah_radar1 = MS(OS_REG_READ(ah, AR_PHY_RADAR_1), + AR_PHY_RADAR_1_CF_BIN_THRESH); + ahp->ah_dc_offset = MS(OS_REG_READ(ah, AR_PHY_TIMING2), + AR_PHY_TIMING2_DC_OFFSET); + ahp->ah_disable_cck = MS(OS_REG_READ(ah, AR_PHY_MODE), + AR_PHY_MODE_DISABLE_CCK); + + if (ap->ah_enable_keysearch_always) { + ar9300_enable_keysearch_always(ah, 1); + } + +#if ATH_LOW_POWER_ENABLE +#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val) +#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) + if (AR_SREV_OSPREY(ah)) { + REG_WRITE(0xb4000080, REG_READ(0xb4000080) | 3); + OS_REG_WRITE(ah, AR_RTC_RESET, 1); + OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), + AR_PCIE_PM_CTRL_ENA); + OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_SPARE), 0xffffffff); + } +#undef REG_READ +#undef REG_WRITE +#endif /* ATH_LOW_POWER_ENABLE */ + + WAR_USB_DISABLE_PLL_LOCK_DETECT(ah); + + /* H/W Green TX */ + ar9300_control_signals_for_green_tx_mode(ah); + /* Smart Antenna, only for 5GHz on Scropion */ + if (IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan)) && AR_SREV_SCORPION(ah)) { + ahp->ah_smartantenna_enable = 0; + } + + ar9300_set_smart_antenna(ah, ahp->ah_smartantenna_enable); + + + return AH_TRUE; +bad: + OS_MARK(ah, AH_MARK_RESET_DONE, ecode); + *status = ecode; + + return AH_FALSE; +#undef FAIL +} + +void +ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t on_off) +{ + /* Set/reset the ps flag */ + AH_PRIVATE(ah)->green_ap_ps_on = !!on_off; +} + +/* + * This function returns 1, where it is possible to do + * single-chain power save. + */ +u_int16_t +ar9300_is_single_ant_power_save_possible(struct ath_hal *ah) +{ + return AH_TRUE; +} + +/* To avoid compilation warnings. Functions not used when EMULATION. */ +/* + * ar9300_find_mag_approx() + */ +static int32_t +ar9300_find_mag_approx(struct ath_hal *ah, int32_t in_re, int32_t in_im) +{ + int32_t abs_i = abs(in_re); + int32_t abs_q = abs(in_im); + int32_t max_abs, min_abs; + + if (abs_i > abs_q) { + max_abs = abs_i; + min_abs = abs_q; + } else { + max_abs = abs_q; + min_abs = abs_i; + } + + return (max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4)); +} + +/* + * ar9300_solve_iq_cal() + * solve 4x4 linear equation used in loopback iq cal. + */ +static HAL_BOOL +ar9300_solve_iq_cal( + struct ath_hal *ah, + int32_t sin_2phi_1, + int32_t cos_2phi_1, + int32_t sin_2phi_2, + int32_t cos_2phi_2, + int32_t mag_a0_d0, + int32_t phs_a0_d0, + int32_t mag_a1_d0, + int32_t phs_a1_d0, + int32_t solved_eq[]) +{ + int32_t f1 = cos_2phi_1 - cos_2phi_2; + int32_t f3 = sin_2phi_1 - sin_2phi_2; + int32_t f2; + int32_t mag_tx, phs_tx, mag_rx, phs_rx; + const int32_t result_shift = 1 << 15; + + f2 = (((int64_t)f1 * (int64_t)f1) / result_shift) + (((int64_t)f3 * (int64_t)f3) / result_shift); + + if (0 == f2) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s: Divide by 0(%d).\n", + __func__, __LINE__); + return AH_FALSE; + } + + /* magnitude mismatch, tx */ + mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0); + /* phase mismatch, tx */ + phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0); + + mag_tx = (mag_tx / f2); + phs_tx = (phs_tx / f2); + + /* magnitude mismatch, rx */ + mag_rx = + mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) / result_shift; + /* phase mismatch, rx */ + phs_rx = + phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) / result_shift; + + solved_eq[0] = mag_tx; + solved_eq[1] = phs_tx; + solved_eq[2] = mag_rx; + solved_eq[3] = phs_rx; + + return AH_TRUE; +} + +/* + * ar9300_calc_iq_corr() + */ +static HAL_BOOL +ar9300_calc_iq_corr(struct ath_hal *ah, int32_t chain_idx, + const int32_t iq_res[], int32_t iqc_coeff[]) +{ + int32_t i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0; + int32_t i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1; + int32_t i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0; + int32_t i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1; + int32_t mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1; + int32_t phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1; + int32_t sin_2phi_1, cos_2phi_1, sin_2phi_2, cos_2phi_2; + int32_t mag_tx, phs_tx, mag_rx, phs_rx; + int32_t solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx; + int32_t q_q_coff, q_i_coff; + const int32_t res_scale = 1 << 15; + const int32_t delpt_shift = 1 << 8; + int32_t mag1, mag2; + + i2_m_q2_a0_d0 = iq_res[0] & 0xfff; + i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff; + iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8); + + if (i2_m_q2_a0_d0 > 0x800) { + i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1); + } + if (iq_corr_a0_d0 > 0x800) { + iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1); + } + + i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff; + i2_p_q2_a0_d1 = (iq_res[2] & 0xfff); + iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff; + + if (i2_m_q2_a0_d1 > 0x800) { + i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1); + } + if (iq_corr_a0_d1 > 0x800) { + iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1); + } + + i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8); + i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff; + iq_corr_a1_d0 = iq_res[4] & 0xfff; + + if (i2_m_q2_a1_d0 > 0x800) { + i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1); + } + if (iq_corr_a1_d0 > 0x800) { + iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1); + } + + i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff; + i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8); + iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff; + + if (i2_m_q2_a1_d1 > 0x800) { + i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1); + } + if (iq_corr_a1_d1 > 0x800) { + iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1); + } + + if ((i2_p_q2_a0_d0 == 0) || + (i2_p_q2_a0_d1 == 0) || + (i2_p_q2_a1_d0 == 0) || + (i2_p_q2_a1_d1 == 0)) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Divide by 0(%d):\na0_d0=%d\na0_d1=%d\na2_d0=%d\na1_d1=%d\n", + __func__, __LINE__, + i2_p_q2_a0_d0, i2_p_q2_a0_d1, i2_p_q2_a1_d0, i2_p_q2_a1_d1); + return AH_FALSE; + } + + if ((i2_p_q2_a0_d0 <= 1024) || (i2_p_q2_a0_d0 > 2047) || + (i2_p_q2_a1_d0 < 0) || (i2_p_q2_a1_d1 < 0) || + (i2_p_q2_a0_d0 <= i2_m_q2_a0_d0) || + (i2_p_q2_a0_d0 <= iq_corr_a0_d0) || + (i2_p_q2_a0_d1 <= i2_m_q2_a0_d1) || + (i2_p_q2_a0_d1 <= iq_corr_a0_d1) || + (i2_p_q2_a1_d0 <= i2_m_q2_a1_d0) || + (i2_p_q2_a1_d0 <= iq_corr_a1_d0) || + (i2_p_q2_a1_d1 <= i2_m_q2_a1_d1) || + (i2_p_q2_a1_d1 <= iq_corr_a1_d1)) { + return AH_FALSE; + } + + mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0; + phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0; + + mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1; + phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1; + + mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0; + phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0; + + mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1; + phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1; + + /* without analog phase shift */ + sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT); + /* without analog phase shift */ + cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT); + /* with analog phase shift */ + sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT); + /* with analog phase shift */ + cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT); + + /* force sin^2 + cos^2 = 1; */ + /* find magnitude by approximation */ + mag1 = ar9300_find_mag_approx(ah, cos_2phi_1, sin_2phi_1); + mag2 = ar9300_find_mag_approx(ah, cos_2phi_2, sin_2phi_2); + + if ((mag1 == 0) || (mag2 == 0)) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Divide by 0(%d): mag1=%d, mag2=%d\n", + __func__, __LINE__, mag1, mag2); + return AH_FALSE; + } + + /* normalization sin and cos by mag */ + sin_2phi_1 = (sin_2phi_1 * res_scale / mag1); + cos_2phi_1 = (cos_2phi_1 * res_scale / mag1); + sin_2phi_2 = (sin_2phi_2 * res_scale / mag2); + cos_2phi_2 = (cos_2phi_2 * res_scale / mag2); + + /* calculate IQ mismatch */ + if (AH_FALSE== ar9300_solve_iq_cal(ah, + sin_2phi_1, cos_2phi_1, sin_2phi_2, cos_2phi_2, mag_a0_d0, + phs_a0_d0, mag_a1_d0, phs_a1_d0, solved_eq)) + { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Call to ar9300_solve_iq_cal failed.\n", __func__); + return AH_FALSE; + } + + mag_tx = solved_eq[0]; + phs_tx = solved_eq[1]; + mag_rx = solved_eq[2]; + phs_rx = solved_eq[3]; + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: chain %d: mag mismatch=%d phase mismatch=%d\n", + __func__, chain_idx, mag_tx / res_scale, phs_tx / res_scale); + + if (res_scale == mag_tx) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Divide by 0(%d): mag_tx=%d, res_scale=%d\n", + __func__, __LINE__, mag_tx, res_scale); + return AH_FALSE; + } + + /* calculate and quantize Tx IQ correction factor */ + mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx); + phs_corr_tx = -phs_tx; + + q_q_coff = (mag_corr_tx * 128 / res_scale); + q_i_coff = (phs_corr_tx * 256 / res_scale); + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: tx chain %d: mag corr=%d phase corr=%d\n", + __func__, chain_idx, q_q_coff, q_i_coff); + + if (q_i_coff < -63) { + q_i_coff = -63; + } + if (q_i_coff > 63) { + q_i_coff = 63; + } + if (q_q_coff < -63) { + q_q_coff = -63; + } + if (q_q_coff > 63) { + q_q_coff = 63; + } + + iqc_coeff[0] = (q_q_coff * 128) + (0x7f & q_i_coff); + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s: tx chain %d: iq corr coeff=%x\n", + __func__, chain_idx, iqc_coeff[0]); + + if (-mag_rx == res_scale) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Divide by 0(%d): mag_rx=%d, res_scale=%d\n", + __func__, __LINE__, mag_rx, res_scale); + return AH_FALSE; + } + + /* calculate and quantize Rx IQ correction factors */ + mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx); + phs_corr_rx = -phs_rx; + + q_q_coff = (mag_corr_rx * 128 / res_scale); + q_i_coff = (phs_corr_rx * 256 / res_scale); + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: rx chain %d: mag corr=%d phase corr=%d\n", + __func__, chain_idx, q_q_coff, q_i_coff); + + if (q_i_coff < -63) { + q_i_coff = -63; + } + if (q_i_coff > 63) { + q_i_coff = 63; + } + if (q_q_coff < -63) { + q_q_coff = -63; + } + if (q_q_coff > 63) { + q_q_coff = 63; + } + + iqc_coeff[1] = (q_q_coff * 128) + (0x7f & q_i_coff); + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s: rx chain %d: iq corr coeff=%x\n", + __func__, chain_idx, iqc_coeff[1]); + + return AH_TRUE; +} + +#define MAX_MAG_DELTA 11 //maximum magnitude mismatch delta across gains +#define MAX_PHS_DELTA 10 //maximum phase mismatch delta across gains +#define ABS(x) ((x) >= 0 ? (x) : (-(x))) + + u_int32_t tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS] = { + { AR_PHY_TX_IQCAL_CORR_COEFF_01_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_01_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_23_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_23_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_45_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_45_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_67_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_67_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B2}, + }; + +static void +ar9300_tx_iq_cal_outlier_detection(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan, u_int32_t num_chains, + struct coeff_t *coeff,HAL_BOOL is_cal_reusable) +{ + int nmeasurement, ch_idx, im; + int32_t magnitude, phase; + int32_t magnitude_max, phase_max; + int32_t magnitude_min, phase_min; + + int32_t magnitude_max_idx, phase_max_idx; + int32_t magnitude_min_idx, phase_min_idx; + + int32_t magnitude_avg, phase_avg; + int32_t outlier_mag_idx = 0; + int32_t outlier_phs_idx = 0; + + + if (AR_SREV_POSEIDON(ah)) { + HALASSERT(num_chains == 0x1); + + tx_corr_coeff[0][0] = AR_PHY_TX_IQCAL_CORR_COEFF_01_B0_POSEIDON; + tx_corr_coeff[1][0] = AR_PHY_TX_IQCAL_CORR_COEFF_01_B0_POSEIDON; + tx_corr_coeff[2][0] = AR_PHY_TX_IQCAL_CORR_COEFF_23_B0_POSEIDON; + tx_corr_coeff[3][0] = AR_PHY_TX_IQCAL_CORR_COEFF_23_B0_POSEIDON; + tx_corr_coeff[4][0] = AR_PHY_TX_IQCAL_CORR_COEFF_45_B0_POSEIDON; + tx_corr_coeff[5][0] = AR_PHY_TX_IQCAL_CORR_COEFF_45_B0_POSEIDON; + tx_corr_coeff[6][0] = AR_PHY_TX_IQCAL_CORR_COEFF_67_B0_POSEIDON; + tx_corr_coeff[7][0] = AR_PHY_TX_IQCAL_CORR_COEFF_67_B0_POSEIDON; + } + + for (ch_idx = 0; ch_idx < num_chains; ch_idx++) { + nmeasurement = OS_REG_READ_FIELD(ah, + AR_PHY_TX_IQCAL_STATUS_B0(ah), AR_PHY_CALIBRATED_GAINS_0); + if (nmeasurement > MAX_MEASUREMENT) { + nmeasurement = MAX_MEASUREMENT; + } + + if (!AR_SREV_SCORPION(ah)) { + /* + * reset max/min variable to min/max values so that + * we always start with 1st calibrated gain value + */ + magnitude_max = -64; + phase_max = -64; + magnitude_min = 63; + phase_min = 63; + magnitude_avg = 0; + phase_avg = 0; + magnitude_max_idx = 0; + magnitude_min_idx = 0; + phase_max_idx = 0; + phase_min_idx = 0; + + /* detect outlier only if nmeasurement > 1 */ + if (nmeasurement > 1) { + /* printf("----------- start outlier detection -----------\n"); */ + /* + * find max/min and phase/mag mismatch across all calibrated gains + */ + for (im = 0; im < nmeasurement; im++) { + magnitude = coeff->mag_coeff[ch_idx][im][0]; + phase = coeff->phs_coeff[ch_idx][im][0]; + + magnitude_avg = magnitude_avg + magnitude; + phase_avg = phase_avg + phase; + if (magnitude > magnitude_max) { + magnitude_max = magnitude; + magnitude_max_idx = im; + } + if (magnitude < magnitude_min) { + magnitude_min = magnitude; + magnitude_min_idx = im; + } + if (phase > phase_max) { + phase_max = phase; + phase_max_idx = im; + } + if (phase < phase_min) { + phase_min = phase; + phase_min_idx = im; + } + } + /* find average (exclude max abs value) */ + for (im = 0; im < nmeasurement; im++) { + magnitude = coeff->mag_coeff[ch_idx][im][0]; + phase = coeff->phs_coeff[ch_idx][im][0]; + if ((ABS(magnitude) < ABS(magnitude_max)) || + (ABS(magnitude) < ABS(magnitude_min))) + { + magnitude_avg = magnitude_avg + magnitude; + } + if ((ABS(phase) < ABS(phase_max)) || + (ABS(phase) < ABS(phase_min))) + { + phase_avg = phase_avg + phase; + } + } + magnitude_avg = magnitude_avg / (nmeasurement - 1); + phase_avg = phase_avg / (nmeasurement - 1); + + /* detect magnitude outlier */ + if (ABS(magnitude_max - magnitude_min) > MAX_MAG_DELTA) { + if (ABS(magnitude_max - magnitude_avg) > + ABS(magnitude_min - magnitude_avg)) + { + /* max is outlier, force to avg */ + outlier_mag_idx = magnitude_max_idx; + } else { + /* min is outlier, force to avg */ + outlier_mag_idx = magnitude_min_idx; + } + coeff->mag_coeff[ch_idx][outlier_mag_idx][0] = magnitude_avg; + coeff->phs_coeff[ch_idx][outlier_mag_idx][0] = phase_avg; + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "[ch%d][outlier mag gain%d]:: " + "mag_avg = %d (/128), phase_avg = %d (/256)\n", + ch_idx, outlier_mag_idx, magnitude_avg, phase_avg); + } + /* detect phase outlier */ + if (ABS(phase_max - phase_min) > MAX_PHS_DELTA) { + if (ABS(phase_max-phase_avg) > ABS(phase_min - phase_avg)) { + /* max is outlier, force to avg */ + outlier_phs_idx = phase_max_idx; + } else{ + /* min is outlier, force to avg */ + outlier_phs_idx = phase_min_idx; + } + coeff->mag_coeff[ch_idx][outlier_phs_idx][0] = magnitude_avg; + coeff->phs_coeff[ch_idx][outlier_phs_idx][0] = phase_avg; + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "[ch%d][outlier phs gain%d]:: " + "mag_avg = %d (/128), phase_avg = %d (/256)\n", + ch_idx, outlier_phs_idx, magnitude_avg, phase_avg); + } + } + } + + /*printf("------------ after outlier detection -------------\n");*/ + for (im = 0; im < nmeasurement; im++) { + magnitude = coeff->mag_coeff[ch_idx][im][0]; + phase = coeff->phs_coeff[ch_idx][im][0]; + + #if 0 + printf("[ch%d][gain%d]:: mag = %d (/128), phase = %d (/256)\n", + ch_idx, im, magnitude, phase); + #endif + + coeff->iqc_coeff[0] = (phase & 0x7f) | ((magnitude & 0x7f) << 7); + + if ((im % 2) == 0) { + OS_REG_RMW_FIELD(ah, + tx_corr_coeff[im][ch_idx], + AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE, + coeff->iqc_coeff[0]); + } else { + OS_REG_RMW_FIELD(ah, + tx_corr_coeff[im][ch_idx], + AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, + coeff->iqc_coeff[0]); + } +#if ATH_SUPPORT_CAL_REUSE + ichan->tx_corr_coeff[im][ch_idx] = coeff->iqc_coeff[0]; +#endif + } +#if ATH_SUPPORT_CAL_REUSE + ichan->num_measures[ch_idx] = nmeasurement; +#endif + } + + OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3, + AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1); + OS_REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0, + AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1); + +#if ATH_SUPPORT_CAL_REUSE + if (is_cal_reusable) { + ichan->one_time_txiqcal_done = AH_TRUE; + HALDEBUG(ah, HAL_DEBUG_FCS_RTT, + "(FCS) TXIQCAL saved - %d\n", ichan->channel); + } +#endif +} + +#if ATH_SUPPORT_CAL_REUSE +static void +ar9300_tx_iq_cal_apply(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + int nmeasurement, ch_idx, im; + + u_int32_t tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS] = { + { AR_PHY_TX_IQCAL_CORR_COEFF_01_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_01_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_23_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_23_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_45_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_45_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_67_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_67_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B2}, + }; + + if (AR_SREV_POSEIDON(ah)) { + HALASSERT(ahp->ah_tx_cal_chainmask == 0x1); + + tx_corr_coeff[0][0] = AR_PHY_TX_IQCAL_CORR_COEFF_01_B0_POSEIDON; + tx_corr_coeff[1][0] = AR_PHY_TX_IQCAL_CORR_COEFF_01_B0_POSEIDON; + tx_corr_coeff[2][0] = AR_PHY_TX_IQCAL_CORR_COEFF_23_B0_POSEIDON; + tx_corr_coeff[3][0] = AR_PHY_TX_IQCAL_CORR_COEFF_23_B0_POSEIDON; + tx_corr_coeff[4][0] = AR_PHY_TX_IQCAL_CORR_COEFF_45_B0_POSEIDON; + tx_corr_coeff[5][0] = AR_PHY_TX_IQCAL_CORR_COEFF_45_B0_POSEIDON; + tx_corr_coeff[6][0] = AR_PHY_TX_IQCAL_CORR_COEFF_67_B0_POSEIDON; + tx_corr_coeff[7][0] = AR_PHY_TX_IQCAL_CORR_COEFF_67_B0_POSEIDON; + } + + for (ch_idx = 0; ch_idx < AR9300_MAX_CHAINS; ch_idx++) { + if ((ahp->ah_tx_cal_chainmask & (1 << ch_idx)) == 0) { + continue; + } + nmeasurement = ichan->num_measures[ch_idx]; + + for (im = 0; im < nmeasurement; im++) { + if ((im % 2) == 0) { + OS_REG_RMW_FIELD(ah, + tx_corr_coeff[im][ch_idx], + AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE, + ichan->tx_corr_coeff[im][ch_idx]); + } else { + OS_REG_RMW_FIELD(ah, + tx_corr_coeff[im][ch_idx], + AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, + ichan->tx_corr_coeff[im][ch_idx]); + } + } + } + + OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3, + AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1); + OS_REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0, + AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1); +} +#endif + +/* + * ar9300_tx_iq_cal_hw_run is only needed for osprey/wasp/hornet + * It is not needed for jupiter/poseidon. + */ +HAL_BOOL +ar9300_tx_iq_cal_hw_run(struct ath_hal *ah) +{ + int is_tx_gain_forced; + + is_tx_gain_forced = OS_REG_READ_FIELD(ah, + AR_PHY_TX_FORCED_GAIN, AR_PHY_TXGAIN_FORCE); + if (is_tx_gain_forced) { + /*printf("Tx gain can not be forced during tx I/Q cal!\n");*/ + OS_REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN, AR_PHY_TXGAIN_FORCE, 0); + } + + /* enable tx IQ cal */ + OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START(ah), + AR_PHY_TX_IQCAL_START_DO_CAL, AR_PHY_TX_IQCAL_START_DO_CAL); + + if (!ath_hal_wait(ah, + AR_PHY_TX_IQCAL_START(ah), AR_PHY_TX_IQCAL_START_DO_CAL, 0, + AH_WAIT_TIMEOUT)) + { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Tx IQ Cal is never completed.\n", __func__); + return AH_FALSE; + } + return AH_TRUE; +} + +static void +ar9300_tx_iq_cal_post_proc(struct ath_hal *ah,HAL_CHANNEL_INTERNAL *ichan, + int iqcal_idx, int max_iqcal,HAL_BOOL is_cal_reusable, HAL_BOOL apply_last_corr) +{ + int nmeasurement=0, im, ix, iy, temp; + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t txiqcal_status[AR9300_MAX_CHAINS] = { + AR_PHY_TX_IQCAL_STATUS_B0(ah), + AR_PHY_TX_IQCAL_STATUS_B1, + AR_PHY_TX_IQCAL_STATUS_B2, + }; + const u_int32_t chan_info_tab[] = { + AR_PHY_CHAN_INFO_TAB_0, + AR_PHY_CHAN_INFO_TAB_1, + AR_PHY_CHAN_INFO_TAB_2, + }; + int32_t iq_res[6]; + int32_t ch_idx, j; + u_int32_t num_chains = 0; + static struct coeff_t coeff; + txiqcal_status[0] = AR_PHY_TX_IQCAL_STATUS_B0(ah); + + for (ch_idx = 0; ch_idx < AR9300_MAX_CHAINS; ch_idx++) { + if (ahp->ah_tx_chainmask & (1 << ch_idx)) { + num_chains++; + } + } + + if (apply_last_corr) { + if (coeff.last_cal == AH_TRUE) { + int32_t magnitude, phase; + int ch_idx, im; + u_int32_t tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS] = { + { AR_PHY_TX_IQCAL_CORR_COEFF_01_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_01_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_01_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_23_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_23_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_23_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_45_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_45_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_45_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_67_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B2}, + { AR_PHY_TX_IQCAL_CORR_COEFF_67_B0, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B1, + AR_PHY_TX_IQCAL_CORR_COEFF_67_B2}, + }; + for (ch_idx = 0; ch_idx < num_chains; ch_idx++) { + for (im = 0; im < coeff.last_nmeasurement; im++) { + magnitude = coeff.mag_coeff[ch_idx][im][0]; + phase = coeff.phs_coeff[ch_idx][im][0]; + +#if 0 + printf("[ch%d][gain%d]:: mag = %d (/128), phase = %d (/256)\n", + ch_idx, im, magnitude, phase); +#endif + + coeff.iqc_coeff[0] = (phase & 0x7f) | ((magnitude & 0x7f) << 7); + if ((im % 2) == 0) { + OS_REG_RMW_FIELD(ah, + tx_corr_coeff[im][ch_idx], + AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE, + coeff.iqc_coeff[0]); + } else { + OS_REG_RMW_FIELD(ah, + tx_corr_coeff[im][ch_idx], + AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, + coeff.iqc_coeff[0]); + } + } + } + OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3, + AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1); + } + return; + } + + + for (ch_idx = 0; ch_idx < num_chains; ch_idx++) { + nmeasurement = OS_REG_READ_FIELD(ah, + AR_PHY_TX_IQCAL_STATUS_B0(ah), AR_PHY_CALIBRATED_GAINS_0); + if (nmeasurement > MAX_MEASUREMENT) { + nmeasurement = MAX_MEASUREMENT; + } + + for (im = 0; im < nmeasurement; im++) { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Doing Tx IQ Cal for chain %d.\n", __func__, ch_idx); + if (OS_REG_READ(ah, txiqcal_status[ch_idx]) & + AR_PHY_TX_IQCAL_STATUS_FAILED) + { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Tx IQ Cal failed for chain %d.\n", __func__, ch_idx); + goto TX_IQ_CAL_FAILED_; + } + + for (j = 0; j < 3; j++) { + u_int32_t idx = 2 * j; + /* 3 registers for each calibration result */ + u_int32_t offset = 4 * (3 * im + j); + + OS_REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY, + AR_PHY_CHAN_INFO_TAB_S2_READ, 0); + /* 32 bits */ + iq_res[idx] = OS_REG_READ(ah, chan_info_tab[ch_idx] + offset); + OS_REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY, + AR_PHY_CHAN_INFO_TAB_S2_READ, 1); + /* 16 bits */ + iq_res[idx + 1] = 0xffff & + OS_REG_READ(ah, chan_info_tab[ch_idx] + offset); + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n", + __func__, idx, iq_res[idx], idx + 1, iq_res[idx + 1]); + } + + if (AH_FALSE== ar9300_calc_iq_corr( + ah, ch_idx, iq_res, coeff.iqc_coeff)) + { + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, + "%s: Failed in calculation of IQ correction.\n", + __func__); + goto TX_IQ_CAL_FAILED_; + } + + coeff.phs_coeff[ch_idx][im][iqcal_idx-1] = coeff.iqc_coeff[0] & 0x7f; + coeff.mag_coeff[ch_idx][im][iqcal_idx-1] = (coeff.iqc_coeff[0] >> 7) & 0x7f; + if (coeff.mag_coeff[ch_idx][im][iqcal_idx-1] > 63) { + coeff.mag_coeff[ch_idx][im][iqcal_idx-1] -= 128; + } + if (coeff.phs_coeff[ch_idx][im][iqcal_idx-1] > 63) { + coeff.phs_coeff[ch_idx][im][iqcal_idx-1] -= 128; + } +#if 0 + ath_hal_printf(ah, "IQCAL::[ch%d][gain%d]:: mag = %d phase = %d \n", + ch_idx, im, coeff.mag_coeff[ch_idx][im][iqcal_idx-1], + coeff.phs_coeff[ch_idx][im][iqcal_idx-1]); +#endif + } + } + //last iteration; calculate mag and phs + if (iqcal_idx == max_iqcal) { + if (max_iqcal>1) { + for (ch_idx = 0; ch_idx < num_chains; ch_idx++) { + for (im = 0; im < nmeasurement; im++) { + //sort mag and phs + for( ix=0;ixah_phyrestart_disabled = 1; + } else { + val |= AR_PHY_RESTART_ENA; + AH_PRIVATE(ah)->ah_phyrestart_disabled = 0; + } + OS_REG_WRITE(ah, AR_PHY_RESTART, val); + + val = OS_REG_READ(ah, AR_PHY_RESTART); +} + +HAL_BOOL +ar9300_interference_is_present(struct ath_hal *ah) +{ + int i; + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + + /* This function is called after a stuck beacon, if EACS is enabled. + * If CW interference is severe, then HW goes into a loop of continuous + * stuck beacons and resets. On reset the NF cal history is cleared. + * So the median value of the history cannot be used - + * hence check if any value (Chain 0/Primary Channel) + * is outside the bounds. + */ + HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah); + for (i = 0; i < HAL_NF_CAL_HIST_LEN_FULL; i++) { + if (h->nf_cal_buffer[i][0] > + ahpriv->nfp->nominal + ahpriv->nf_cw_int_delta) + { + return AH_TRUE; + } + + } + return AH_FALSE; +} + +#if ATH_SUPPORT_CRDC +void +ar9300_crdc_rx_notify(struct ath_hal *ah, struct ath_rx_status *rxs) +{ + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + int rssi_index; + + if ((!AR_SREV_WASP(ah)) || + (!ahpriv->ah_config.ath_hal_crdc_enable)) { + return; + } + + if (rxs->rs_isaggr && rxs->rs_moreaggr) { + return; + } + + if ((rxs->rs_rssi_ctl0 >= HAL_RSSI_BAD) || + (rxs->rs_rssi_ctl1 >= HAL_RSSI_BAD)) { + return; + } + + rssi_index = ah->ah_crdc_rssi_ptr % HAL_MAX_CRDC_RSSI_SAMPLE; + + ah->ah_crdc_rssi_sample[0][rssi_index] = rxs->rs_rssi_ctl0; + ah->ah_crdc_rssi_sample[1][rssi_index] = rxs->rs_rssi_ctl1; + + ah->ah_crdc_rssi_ptr++; +} + +static int +ar9300_crdc_avg_rssi(struct ath_hal *ah, int chain) +{ + int crdc_rssi_sum = 0; + int crdc_rssi_ptr = ah->ah_crdc_rssi_ptr, i; + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + int crdc_window = ahpriv->ah_config.ath_hal_crdc_window; + + if (crdc_window > HAL_MAX_CRDC_RSSI_SAMPLE) { + crdc_window = HAL_MAX_CRDC_RSSI_SAMPLE; + } + + for (i = 1; i <= crdc_window; i++) { + crdc_rssi_sum += + ah->ah_crdc_rssi_sample[chain] + [(crdc_rssi_ptr - i) % HAL_MAX_CRDC_RSSI_SAMPLE]; + } + + return crdc_rssi_sum / crdc_window; +} + +static void +ar9300_crdc_activate(struct ath_hal *ah, int rssi_diff, int enable) +{ + int val, orig_val; + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + int crdc_numerator = ahpriv->ah_config.ath_hal_crdc_numerator; + int crdc_denominator = ahpriv->ah_config.ath_hal_crdc_denominator; + int c = (rssi_diff * crdc_numerator) / crdc_denominator; + + val = orig_val = OS_REG_READ(ah, AR_PHY_MULTICHAIN_CTRL); + val &= 0xffffff00; + if (enable) { + val |= 0x1; + val |= ((c << 1) & 0xff); + } + OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_CTRL, val); + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "diff: %02d comp: %02d reg: %08x %08x\n", + rssi_diff, c, orig_val, val); +} + + +void ar9300_chain_rssi_diff_compensation(struct ath_hal *ah) +{ + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + int crdc_window = ahpriv->ah_config.ath_hal_crdc_window; + int crdc_rssi_ptr = ah->ah_crdc_rssi_ptr; + int crdc_rssi_thresh = ahpriv->ah_config.ath_hal_crdc_rssithresh; + int crdc_diff_thresh = ahpriv->ah_config.ath_hal_crdc_diffthresh; + int avg_rssi[2], avg_rssi_diff; + + if ((!AR_SREV_WASP(ah)) || + (!ahpriv->ah_config.ath_hal_crdc_enable)) { + if (ah->ah_crdc_rssi_ptr) { + ar9300_crdc_activate(ah, 0, 0); + ah->ah_crdc_rssi_ptr = 0; + } + return; + } + + if (crdc_window > HAL_MAX_CRDC_RSSI_SAMPLE) { + crdc_window = HAL_MAX_CRDC_RSSI_SAMPLE; + } + + if (crdc_rssi_ptr < crdc_window) { + return; + } + + avg_rssi[0] = ar9300_crdc_avg_rssi(ah, 0); + avg_rssi[1] = ar9300_crdc_avg_rssi(ah, 1); + avg_rssi_diff = avg_rssi[1] - avg_rssi[0]; + + HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "crdc: avg: %02d %02d ", + avg_rssi[0], avg_rssi[1]); + + if ((avg_rssi[0] < crdc_rssi_thresh) && + (avg_rssi[1] < crdc_rssi_thresh)) { + ar9300_crdc_activate(ah, 0, 0); + } else { + if (ABS(avg_rssi_diff) >= crdc_diff_thresh) { + ar9300_crdc_activate(ah, avg_rssi_diff, 1); + } else { + ar9300_crdc_activate(ah, 0, 1); + } + } +} +#endif + +#if ATH_ANT_DIV_COMB +HAL_BOOL +ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal *ah, HAL_BOOL enable, HAL_CHANNEL *chan) +{ + u_int32_t value; + u_int32_t regval; + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_CHANNEL_INTERNAL *ichan; + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + HAL_CAPABILITIES *pcap = &ahpriv->ah_caps; + + if (AR_SREV_POSEIDON(ah)) { + // Make sure this scheme is only used for WB225(Astra) + ahp->ah_lna_div_use_bt_ant_enable = enable; + + ichan = ar9300_check_chan(ah, chan); + if ( ichan == AH_NULL ) { + HALDEBUG(ah, HAL_DEBUG_CHANNEL, "%s: invalid channel %u/0x%x; no mapping\n", + __func__, chan->channel, chan->channel_flags); + return AH_FALSE; + } + + if ( enable == TRUE ) { + pcap->hal_ant_div_comb_support = TRUE; + } else { + pcap->hal_ant_div_comb_support = pcap->hal_ant_div_comb_support_org; + } + +#define AR_SWITCH_TABLE_COM2_ALL (0xffffff) +#define AR_SWITCH_TABLE_COM2_ALL_S (0) + value = ar9300_ant_ctrl_common2_get(ah, IS_CHAN_2GHZ(ichan)); + if ( enable == TRUE ) { + value &= ~AR_SWITCH_TABLE_COM2_ALL; + value |= ahpriv->ah_config.ath_hal_ant_ctrl_comm2g_switch_enable; + } + OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value); + + value = ar9300_eeprom_get(ahp, EEP_ANTDIV_control); + /* main_lnaconf, alt_lnaconf, main_tb, alt_tb */ + regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); + regval &= (~ANT_DIV_CONTROL_ALL); /* clear bit 25~30 */ + regval |= (value & 0x3f) << ANT_DIV_CONTROL_ALL_S; + /* enable_lnadiv */ + regval &= (~MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MASK); + regval |= ((value >> 6) & 0x1) << + MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__SHIFT; + if ( enable == TRUE ) { + regval |= ANT_DIV_ENABLE; + } + OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); + + /* enable fast_div */ + regval = OS_REG_READ(ah, AR_PHY_CCK_DETECT); + regval &= (~BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MASK); + regval |= ((value >> 7) & 0x1) << + BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SHIFT; + if ( enable == TRUE ) { + regval |= FAST_DIV_ENABLE; + } + OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); + + if ( AR_SREV_POSEIDON_11_OR_LATER(ah) ) { + if (pcap->hal_ant_div_comb_support) { + /* If support DivComb, set MAIN to LNA1 and ALT to LNA2 at the first beginning */ + regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); + /* clear bit 25~30 main_lnaconf, alt_lnaconf, main_tb, alt_tb */ + regval &= (~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK | + MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK)); + regval |= (HAL_ANT_DIV_COMB_LNA1 << + MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__SHIFT); + regval |= (HAL_ANT_DIV_COMB_LNA2 << + MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__SHIFT); + OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); + } + } + + return AH_TRUE; + } else { + return AH_TRUE; + } +} +#endif /* ATH_ANT_DIV_COMB */ + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_rtt.c b/hal/ar9300/ar9300_rtt.c new file mode 100644 index 000000000000..5b58696cc33d --- /dev/null +++ b/hal/ar9300/ar9300_rtt.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" +#include "ah_devid.h" + +#include "ar9300.h" +#include "ar9300reg.h" +#include "ar9300phy.h" +#include "ar9300desc.h" + + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_sim.c b/hal/ar9300/ar9300_sim.c new file mode 100644 index 000000000000..20ce6013d34d --- /dev/null +++ b/hal/ar9300/ar9300_sim.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "wbuf.h" + diff --git a/hal/ar9300/ar9300_sim.h b/hal/ar9300/ar9300_sim.h new file mode 100644 index 000000000000..83c452417a2d --- /dev/null +++ b/hal/ar9300/ar9300_sim.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _ATH_AR9300_SIM_H_ +#define _ATH_AR9300_SIM_H_ + + +#endif // _ATH_AR9300_SIM_H_ diff --git a/hal/ar9300/ar9300_spectral.c b/hal/ar9300/ar9300_spectral.c new file mode 100644 index 000000000000..1219b77e4947 --- /dev/null +++ b/hal/ar9300/ar9300_spectral.c @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_desc.h" +#include "ah_internal.h" + +#include "ar9300/ar9300phy.h" +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300desc.h" + +#if ATH_SUPPORT_SPECTRAL + +/* + * Default 9300 spectral scan parameters + */ +#define AR9300_SPECTRAL_SCAN_ENA 0 +#define AR9300_SPECTRAL_SCAN_ACTIVE 0 +#define AR9300_SPECTRAL_SCAN_FFT_PERIOD 8 +#define AR9300_SPECTRAL_SCAN_PERIOD 1 +#define AR9300_SPECTRAL_SCAN_COUNT 16 /* used to be 128 */ +#define AR9300_SPECTRAL_SCAN_SHORT_REPEAT 1 + +/* constants */ +#define MAX_RADAR_DC_PWR_THRESH 127 +#define MAX_RADAR_RSSI_THRESH 0x3f +#define MAX_RADAR_HEIGHT 0x3f +#define MAX_CCA_THRESH 127 +#define ENABLE_ALL_PHYERR 0xffffffff + +void ar9300_disable_cck(struct ath_hal *ah); +void ar9300_disable_radar(struct ath_hal *ah); +void ar9300_disable_restart(struct ath_hal *ah); +void ar9300_set_radar_dc_thresh(struct ath_hal *ah); +void ar9300_disable_weak_signal(struct ath_hal *ah); +void ar9300_disable_strong_signal(struct ath_hal *ah); +void ar9300_prep_spectral_scan(struct ath_hal *ah); +void ar9300_disable_dc_offset(struct ath_hal *ah); +void ar9300_enable_cck_detect(struct ath_hal *ah); + +void +ar9300_disable_cck(struct ath_hal *ah) +{ + u_int32_t val; + + val = OS_REG_READ(ah, AR_PHY_MODE); + val &= ~(AR_PHY_MODE_DYN_CCK_DISABLE); + + OS_REG_WRITE(ah, AR_PHY_MODE, val); +} + +void +ar9300_disable_radar(struct ath_hal *ah) +{ + u_int32_t val; + + /* Enable radar FFT */ + val = OS_REG_READ(ah, AR_PHY_RADAR_0); + val |= AR_PHY_RADAR_0_FFT_ENA; + + /* set radar detect thresholds to max to effectively disable radar */ + val &= ~AR_PHY_RADAR_0_RRSSI; + val |= SM(MAX_RADAR_RSSI_THRESH, AR_PHY_RADAR_0_RRSSI); + + val &= ~AR_PHY_RADAR_0_HEIGHT; + val |= SM(MAX_RADAR_HEIGHT, AR_PHY_RADAR_0_HEIGHT); + + val &= ~(AR_PHY_RADAR_0_ENA); + OS_REG_WRITE(ah, AR_PHY_RADAR_0, val); + + /* disable extension radar detect */ + val = OS_REG_READ(ah, AR_PHY_RADAR_EXT); + OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val & ~AR_PHY_RADAR_EXT_ENA); + + val = OS_REG_READ(ah, AR_RX_FILTER); + val |= (1 << 13); + OS_REG_WRITE(ah, AR_RX_FILTER, val); +} + +void ar9300_disable_restart(struct ath_hal *ah) +{ + u_int32_t val; + val = OS_REG_READ(ah, AR_PHY_RESTART); + val &= ~AR_PHY_RESTART_ENA; + OS_REG_WRITE(ah, AR_PHY_RESTART, val); + + val = OS_REG_READ(ah, AR_PHY_RESTART); +} + +void ar9300_set_radar_dc_thresh(struct ath_hal *ah) +{ + u_int32_t val; + val = OS_REG_READ(ah, AR_PHY_RADAR_EXT); + val &= ~AR_PHY_RADAR_DC_PWR_THRESH; + val |= SM(MAX_RADAR_DC_PWR_THRESH, AR_PHY_RADAR_DC_PWR_THRESH); + OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val); + + val = OS_REG_READ(ah, AR_PHY_RADAR_EXT); +} + +void +ar9300_disable_weak_signal(struct ath_hal *ah) +{ + /* set firpwr to max (signed) */ + OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR, 0x7f); + OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT); + + /* set firstep to max */ + OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, 0x3f); + + /* set relpwr to max (signed) */ + OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELPWR, 0x1f); + OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELPWR_SIGN_BIT); + + /* set relstep to max (signed) */ + OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELSTEP, 0x1f); + OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT); + + /* set firpwr_low to max (signed) */ + OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRPWR, 0x7f); + OS_REG_CLR_BIT( + ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT); + + /* set firstep_low to max */ + OS_REG_RMW_FIELD( + ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, 0x3f); + + /* set relstep_low to max (signed) */ + OS_REG_RMW_FIELD( + ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_RELSTEP, 0x1f); + OS_REG_CLR_BIT( + ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT); +} + +void +ar9300_disable_strong_signal(struct ath_hal *ah) +{ + u_int32_t val; + + val = OS_REG_READ(ah, AR_PHY_TIMING5); + val |= AR_PHY_TIMING5_RSSI_THR1A_ENA; + OS_REG_WRITE(ah, AR_PHY_TIMING5, val); + + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_RSSI_THR1A, 0x7f); + +} +void +ar9300_set_cca_threshold(struct ath_hal *ah, u_int8_t thresh62) +{ + OS_REG_RMW_FIELD(ah, AR_PHY_CCA_0, AR_PHY_CCA_THRESH62, thresh62); + OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, thresh62); + /* + OS_REG_RMW_FIELD(ah, + AR_PHY_EXTCHN_PWRTHR1, AR_PHY_EXT_CCA0_THRESH62, thresh62); + */ + OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62, thresh62); +} + +static void ar9300_classify_strong_bins(struct ath_hal *ah) +{ + OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_CF_BIN_THRESH, 0x1); +} + +void ar9300_disable_dc_offset(struct ath_hal *ah) +{ + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET, 0); +} + +void ar9300_enable_cck_detect(struct ath_hal *ah) +{ + OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DISABLE_CCK, 0); + OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DYNAMIC, 1); +} + +void ar9300_prep_spectral_scan(struct ath_hal *ah) +{ + ar9300_disable_radar(ah); + ar9300_classify_strong_bins(ah); + ar9300_disable_dc_offset(ah); + if (AH_PRIVATE(ah)->ah_curchan && + IS_5GHZ_FAST_CLOCK_EN(ah, AH_PRIVATE(ah)->ah_curchan)) + { /* fast clock */ + ar9300_enable_cck_detect(ah); + } +#ifdef DEMO_MODE + ar9300_disable_strong_signal(ah); + ar9300_disable_weak_signal(ah); + ar9300_set_radar_dc_thresh(ah); + ar9300_set_cca_threshold(ah, MAX_CCA_THRESH); + /*ar9300_disable_restart(ah);*/ +#endif + OS_REG_WRITE(ah, AR_PHY_ERR, HAL_PHYERR_SPECTRAL); +} + + +//#define TEST_NOISE_PWR_WITHOUT_EEPROM 1 +#ifdef TEST_NOISE_PWR_WITHOUT_EEPROM +struct nf_cal { + int cal; + int pwr; +}; +struct nf_cal_table_t { + int freq; + struct nf_cal chain[AH_MAX_CHAINS]; +}; + +static const struct nf_cal_table_t nf_cal_table[] = +{ +/* ch 1 */ {2412, { {N2DBM(-101, 00), N2DBM( -94, 25)}, + {N2DBM(-107, 75), N2DBM( -99, 75)}, + } }, +/* ch 6 */ {2437, { {N2DBM(-102, 25), N2DBM( -94, 25)}, + {N2DBM(-106, 00), N2DBM( -97, 25)}, + } }, +/* ch 11 */ {2462, { {N2DBM(-101, 50), N2DBM( -95, 00)}, + {N2DBM(-105, 50), N2DBM( -98, 00)}, + } }, +/* ch 36 */ {5180, { {N2DBM(-114, 25), N2DBM( -95, 00)}, + {N2DBM(-114, 75), N2DBM( -94, 00)}, + } }, +/* ch 44 */ {5220, { {N2DBM(-113, 00), N2DBM( -95, 00)}, + {N2DBM(-115, 00), N2DBM( -94, 50)}, + } }, +/* ch 64 */ {5320, { {N2DBM(-113, 00), N2DBM( -95, 00)}, // not cal'ed + {N2DBM(-115, 00), N2DBM( -94, 50)}, + } }, +/* ch 100*/ {5500, { {N2DBM(-111, 50), N2DBM( -93, 75)}, + {N2DBM(-112, 00), N2DBM( -95, 25)}, + } }, +/* ch 120*/ {5600, { {N2DBM(-111, 50), N2DBM( -93, 75)}, + {N2DBM(-112, 00), N2DBM( -95, 25)}, + } }, +/* ch 140*/ {5700, { {N2DBM(-111, 75), N2DBM( -95, 00)}, + {N2DBM(-111, 75), N2DBM( -96, 00)}, + } }, +/* ch 157*/ {5785, { {N2DBM(-112, 50), N2DBM( -94, 75)}, + {N2DBM(-111, 75), N2DBM( -95, 50)}, + } }, +/* ch 165*/ {5825, { {N2DBM(-111, 50), N2DBM( -95, 00)}, + {N2DBM(-112, 00), N2DBM( -95, 00)}, + } }, + {0} +}; + +static int +ar9300_noise_floor_get(struct ath_hal *ah, int freq_mhz, int ch) +{ + int i; + for (i = 0; nf_cal_table[i].freq != 0; i++) { + if (nf_cal_table[i + 0].freq == freq_mhz || + nf_cal_table[i + 1].freq > freq_mhz || + nf_cal_table[i + 1].freq == 0) { + return nf_cal_table[i].chain[ch].cal; + } + } + + ath_hal_printf(ah, + "%s: **Warning: device %d.%d: " + "no nf cal offset found for freq %d chain %d\n", + __func__, (AH_PRIVATE(ah))->ah_macVersion, + (AH_PRIVATE(ah))->ah_macRev, freq_mhz, ch); + return 0; +} + +static int +ar9300_noise_floor_power_get(struct ath_hal *ah, int freq_mhz, int ch) +{ + int i; + for (i = 0; nf_cal_table[i].freq != 0; i++) { + if (nf_cal_table[i + 0].freq == freq_mhz || + nf_cal_table[i + 1].freq > freq_mhz || + nf_cal_table[i + 1].freq == 0) { + return nf_cal_table[i].chain[ch].pwr; + } + } + + ath_hal_printf(ah, + "%s: **Warning: device %d.%d: " + "no nf pwr offset found for freq %d chain %d\n", + __func__, (AH_PRIVATE(ah))->ah_macVersion, + (AH_PRIVATE(ah))->ah_macRev, freq_mhz, ch); + return 0; +} +#else +#define ar9300_noise_floor_get(_ah,_f,_ich) ar9300_noise_floor_cal_or_power_get((_ah), (_f), (_ich), 1/*use_cal*/) +#define ar9300_noise_floor_power_get(_ah,_f,_ich) ar9300_noise_floor_cal_or_power_get((_ah), (_f), (_ich), 0/*use_cal*/) +#endif + + +void +ar9300_configure_spectral_scan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss) +{ + u_int32_t val, i; + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL asleep = ahp->ah_chip_full_sleep; + int16_t nf_buf[NUM_NF_READINGS]; + + if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { + ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE); + } + + ar9300_prep_spectral_scan(ah); + + if (ss->ss_spectral_pri) { + for (i = 0; i < NUM_NF_READINGS; i++) { + nf_buf[i] = NOISE_PWR_DBM_2_INT(ss->ss_nf_cal[i]); + } + ar9300_load_nf(ah, nf_buf); +#ifdef DEMO_MODE + ar9300_disable_strong_signal(ah); + ar9300_disable_weak_signal(ah); + ar9300_set_radar_dc_thresh(ah); + ar9300_set_cca_threshold(ah, MAX_CCA_THRESH); + /*ar9300_disable_restart(ah);*/ +#endif + } + + val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); + + if (ss->ss_fft_period != HAL_SPECTRAL_PARAM_NOVAL) { + val &= ~AR_PHY_SPECTRAL_SCAN_FFT_PERIOD; + val |= SM(ss->ss_fft_period, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD); + } + + if (ss->ss_period != HAL_SPECTRAL_PARAM_NOVAL) { + val &= ~AR_PHY_SPECTRAL_SCAN_PERIOD; + val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD); + } + + if (ss->ss_count != HAL_SPECTRAL_PARAM_NOVAL) { + val &= ~AR_PHY_SPECTRAL_SCAN_COUNT; + /* Remnants of a Merlin bug, 128 translates to 0 for + * continuous scanning. Instead we do piecemeal captures + * of 64 samples for Osprey. + */ + if (ss->ss_count == 128) { + val |= SM(0, AR_PHY_SPECTRAL_SCAN_COUNT); + } else { + val |= SM(ss->ss_count, AR_PHY_SPECTRAL_SCAN_COUNT); + } + } + + if (ss->ss_period != HAL_SPECTRAL_PARAM_NOVAL) { + val &= ~AR_PHY_SPECTRAL_SCAN_PERIOD; + val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD); + } + + if (ss->ss_short_report == AH_TRUE) { + val |= AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT; + } else { + val &= ~AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT; + } + + /* if noise power cal, force high priority */ + if (ss->ss_spectral_pri) { + val |= AR_PHY_SPECTRAL_SCAN_PRIORITY_HI; + } else { + val &= ~AR_PHY_SPECTRAL_SCAN_PRIORITY_HI; + } + + /* enable spectral scan */ + OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val | AR_PHY_SPECTRAL_SCAN_ENABLE); + + if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { + ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); + } +} + +/* + * Get the spectral parameter values and return them in the pe + * structure + */ + +void +ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss) +{ + u_int32_t val; + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + int i, ichain, rx_chain_status; + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL asleep = ahp->ah_chip_full_sleep; + + if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { + ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE); + } + + val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); + + ss->ss_fft_period = MS(val, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD); + ss->ss_period = MS(val, AR_PHY_SPECTRAL_SCAN_PERIOD); + ss->ss_count = MS(val, AR_PHY_SPECTRAL_SCAN_COUNT); + ss->ss_short_report = (val & AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT) ? 1:0; + ss->ss_spectral_pri = ( val & AR_PHY_SPECTRAL_SCAN_PRIORITY_HI) ? 1:0; + OS_MEMZERO(ss->ss_nf_cal, sizeof(ss->ss_nf_cal)); + OS_MEMZERO(ss->ss_nf_pwr, sizeof(ss->ss_nf_cal)); + ss->ss_nf_temp_data = 0; + + if (chan != NULL) { + rx_chain_status = OS_REG_READ(ah, AR_PHY_RX_CHAINMASK) & 0x7; + for (i = 0; i < NUM_NF_READINGS; i++) { + ichain = i % 3; + if (rx_chain_status & (1 << ichain)) { + ss->ss_nf_cal[i] = + ar9300_noise_floor_get(ah, chan->channel, ichain); + ss->ss_nf_pwr[i] = + ar9300_noise_floor_power_get(ah, chan->channel, ichain); + } + } + ss->ss_nf_temp_data = OS_REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4, AR_PHY_BB_THERM_ADC_4_LATEST_THERM); + } else { + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "%s: chan is NULL - no ss nf values\n", __func__); + } + + if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { + ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); + } +} + +HAL_BOOL +ar9300_is_spectral_active(struct ath_hal *ah) +{ + u_int32_t val; + + val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); + return MS(val, AR_PHY_SPECTRAL_SCAN_ACTIVE); +} + +HAL_BOOL +ar9300_is_spectral_enabled(struct ath_hal *ah) +{ + u_int32_t val; + + val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); + return MS(val, AR_PHY_SPECTRAL_SCAN_ENABLE); +} + +void ar9300_start_spectral_scan(struct ath_hal *ah) +{ + u_int32_t val; + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL asleep = ahp->ah_chip_full_sleep; + + if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { + ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE); + } + + ar9300_prep_spectral_scan(ah); + + /* activate spectral scan */ + val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); + /* This is a hardware bug fix, the enable and active bits should + * not be set/reset in the same write operation to the register + */ + if (!(val & AR_PHY_SPECTRAL_SCAN_ENABLE)) { + val |= AR_PHY_SPECTRAL_SCAN_ENABLE; + OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val); + val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); + } + val |= AR_PHY_SPECTRAL_SCAN_ACTIVE; + OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val); + + /* Reset the PHY_ERR_MASK */ + val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG); + OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val | AR_PHY_ERR_RADAR); + + if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { + ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); + } +} + +void ar9300_stop_spectral_scan(struct ath_hal *ah) +{ + u_int32_t val; + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL asleep = ahp->ah_chip_full_sleep; + + if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { + ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE); + } + val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); + + /* deactivate spectral scan */ + /* HW Bug fix -- Do not disable the spectral scan + * only turn off the active bit + */ + //val &= ~AR_PHY_SPECTRAL_SCAN_ENABLE; + val &= ~AR_PHY_SPECTRAL_SCAN_ACTIVE; + OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val); + val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); + + OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_CF_BIN_THRESH, + ahp->ah_radar1); + OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET, + ahp->ah_dc_offset); + OS_REG_WRITE(ah, AR_PHY_ERR, 0); + + if (AH_PRIVATE(ah)->ah_curchan && + IS_5GHZ_FAST_CLOCK_EN(ah, AH_PRIVATE(ah)->ah_curchan)) + { /* fast clock */ + OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DISABLE_CCK, + ahp->ah_disable_cck); + } + + val = OS_REG_READ(ah, AR_PHY_ERR); + + val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG) & (~AR_PHY_ERR_RADAR); + OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val); + + if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { + ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); + } +} + +u_int32_t ar9300_get_spectral_config(struct ath_hal *ah) +{ + u_int32_t val; + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_BOOL asleep = ahp->ah_chip_full_sleep; + + if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { + ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE); + } + + val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN); + + if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) { + ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); + } + return val; +} + +int16_t ar9300_get_ctl_chan_nf(struct ath_hal *ah) +{ + int16_t nf; + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + + if ( (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) { + /* Noise floor calibration value is ready */ + nf = MS(OS_REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR); + } else { + /* NF calibration is not done, return nominal value */ + nf = ahpriv->nfp->nominal; + } + if (nf & 0x100) { + nf = (0 - ((nf ^ 0x1ff) + 1)); + } + return nf; +} + +int16_t ar9300_get_ext_chan_nf(struct ath_hal *ah) +{ + int16_t nf; + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + + if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) { + /* Noise floor calibration value is ready */ + nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); + } else { + /* NF calibration is not done, return nominal value */ + nf = ahpriv->nfp->nominal; + } + if (nf & 0x100) { + nf = (0 - ((nf ^ 0x1ff) + 1)); + } + return nf; +} + +#endif +#endif /* ATH_SUPPORT_SPECTRAL */ + diff --git a/hal/ar9300/ar9300_timer.c b/hal/ar9300/ar9300_timer.c new file mode 100644 index 000000000000..baaadde470f6 --- /dev/null +++ b/hal/ar9300/ar9300_timer.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300desc.h" + +typedef struct gen_timer_configuation { + u_int32_t next_addr; + u_int32_t period_addr; + u_int32_t mode_addr; + u_int32_t mode_mask; +} GEN_TIMER_CONFIGURATION; + +#define AR_GEN_TIMERS2_CFG(num) \ + AR_GEN_TIMERS2_ ## num ## _NEXT, \ + AR_GEN_TIMERS2_ ## num ## _PERIOD, \ + AR_GEN_TIMERS2_MODE, \ + (1 << num) +static const GEN_TIMER_CONFIGURATION gen_timer_configuration[] = +{ + {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, + {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, + {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, + {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, + {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, + {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, + {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, + {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, + {AR_GEN_TIMERS2_CFG(0)}, + {AR_GEN_TIMERS2_CFG(1)}, + {AR_GEN_TIMERS2_CFG(2)}, + {AR_GEN_TIMERS2_CFG(3)}, + {AR_GEN_TIMERS2_CFG(4)}, + {AR_GEN_TIMERS2_CFG(5)}, + {AR_GEN_TIMERS2_CFG(6)}, + {AR_GEN_TIMERS2_CFG(7)} +}; + +#define AR_GENTMR_BIT(_index) (1 << (_index)) + +int +ar9300_alloc_generic_timer(struct ath_hal *ah, HAL_GEN_TIMER_DOMAIN tsf) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t i, mask; + u_int32_t avail_timer_start, avail_timer_end; + + if (tsf == HAL_GEN_TIMER_TSF) { + avail_timer_start = AR_FIRST_NDP_TIMER; + avail_timer_end = AR_GEN_TIMER_BANK_1_LEN; + } else { + avail_timer_start = AR_GEN_TIMER_BANK_1_LEN; + avail_timer_end = AR_NUM_GEN_TIMERS; + } + + /* Find the first availabe timer index */ + i = avail_timer_start; + mask = ahp->ah_avail_gen_timers >> i; + for ( ; mask && (i < avail_timer_end) ; mask >>= 1, i++ ) { + if (mask & 0x1) { + ahp->ah_avail_gen_timers &= ~(AR_GENTMR_BIT(i)); + + if ((tsf == HAL_GEN_TIMER_TSF2) && !ahp->ah_enable_tsf2) { + ahp->ah_enable_tsf2 = AH_TRUE; + ar9300_start_tsf2(ah); + } + return i; + } + } + return -1; +} + +void ar9300_start_tsf2(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + if (ahp->ah_enable_tsf2) { + /* Delay might be needed after TSF2 reset */ + OS_REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); + OS_REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); + } +} + +void +ar9300_free_generic_timer(struct ath_hal *ah, int index) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + ar9300_stop_generic_timer(ah, index); + ahp->ah_avail_gen_timers |= AR_GENTMR_BIT(index); +} + +void +ar9300_start_generic_timer( + struct ath_hal *ah, + int index, + u_int32_t timer_next, + u_int32_t timer_period) +{ + if ((index < AR_FIRST_NDP_TIMER) || (index >= AR_NUM_GEN_TIMERS)) { + return; + } + + /* + * Program generic timer registers + */ + OS_REG_WRITE(ah, gen_timer_configuration[index].next_addr, timer_next); + OS_REG_WRITE(ah, gen_timer_configuration[index].period_addr, timer_period); + OS_REG_SET_BIT(ah, + gen_timer_configuration[index].mode_addr, + gen_timer_configuration[index].mode_mask); + + if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { + /* + * Starting from Jupiter, each generic timer can select which tsf to + * use. But we still follow the old rule, 0 - 7 use tsf and 8 - 15 + * use tsf2. + */ + if ((index < AR_GEN_TIMER_BANK_1_LEN)) { + OS_REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, (1 << index)); + } + else { + OS_REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, (1 << index)); + } + } + + /* Enable both trigger and thresh interrupt masks */ + OS_REG_SET_BIT(ah, AR_IMR_S5, + (SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_THRESH) | + SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_TRIG))); +} + +void +ar9300_stop_generic_timer(struct ath_hal *ah, int index) +{ + if ((index < AR_FIRST_NDP_TIMER) || (index >= AR_NUM_GEN_TIMERS)) { + return; + } + + /* + * Clear generic timer enable bits. + */ + OS_REG_CLR_BIT(ah, + gen_timer_configuration[index].mode_addr, + gen_timer_configuration[index].mode_mask); + + /* Disable both trigger and thresh interrupt masks */ + OS_REG_CLR_BIT(ah, AR_IMR_S5, + (SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_THRESH) | + SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_TRIG))); +} + +void +ar9300_get_gen_timer_interrupts( + struct ath_hal *ah, + u_int32_t *trigger, + u_int32_t *thresh) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + *trigger = ahp->ah_intr_gen_timer_trigger; + *thresh = ahp->ah_intr_gen_timer_thresh; +} + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_tx99_tgt.c b/hal/ar9300/ar9300_tx99_tgt.c new file mode 100644 index 000000000000..eb9742e41d30 --- /dev/null +++ b/hal/ar9300/ar9300_tx99_tgt.c @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* + * Copyright (c) 2010 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "ah.h" +#include "ah_internal.h" +#include "ar9300phy.h" +#include "ar9300reg.h" +#include "ar9300eep.h" + +#ifdef ATH_TX99_DIAG +void +ar9300_tx99_tgt_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, u_int32_t txpower) +{ +#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) + static int16_t pPwrArray[ar9300_rate_size] = { 0 }; + int32_t i; + //u_int8_t ht40PowerIncForPdadc = 2; + + for (i = 0; i < ar9300_rate_size; i++) + pPwrArray[i] = txpower; + + OS_REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0); + + /* Write the OFDM power per rate set */ + /* 6 (LSB), 9, 12, 18 (MSB) */ + OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1), + PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) + | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) + | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) + | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 0) + ); + /* 24 (LSB), 36, 48, 54 (MSB) */ + OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2), + PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_54], 24) + | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_48], 16) + | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_36], 8) + | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 0) + ); + + /* Write the CCK power per rate set */ + /* 1L (LSB), reserved, 2L, 2S (MSB) */ + OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3), + PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) + | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) +// | PWR_MAS(txPowerTimes2, 8) /* this is reserved for Osprey */ + | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) + ); + /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ + OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4), + PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_11S], 24) + | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_11L], 16) + | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_5S], 8) + | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) + ); + + /* Write the HT20 power per rate set */ + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ + OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5), + PWR_MAS(pPwrArray[ALL_TARGET_HT20_5], 24) + | PWR_MAS(pPwrArray[ALL_TARGET_HT20_4], 16) + | PWR_MAS(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) + | PWR_MAS(pPwrArray[ALL_TARGET_HT20_0_8_16], 0) + ); + + /* 6 (LSB), 7, 12, 13 (MSB) */ + OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6), + PWR_MAS(pPwrArray[ALL_TARGET_HT20_13], 24) + | PWR_MAS(pPwrArray[ALL_TARGET_HT20_12], 16) + | PWR_MAS(pPwrArray[ALL_TARGET_HT20_7], 8) + | PWR_MAS(pPwrArray[ALL_TARGET_HT20_6], 0) + ); + + /* 14 (LSB), 15, 20, 21 */ + OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10), + PWR_MAS(pPwrArray[ALL_TARGET_HT20_21], 24) + | PWR_MAS(pPwrArray[ALL_TARGET_HT20_20], 16) + | PWR_MAS(pPwrArray[ALL_TARGET_HT20_15], 8) + | PWR_MAS(pPwrArray[ALL_TARGET_HT20_14], 0) + ); + + /* Mixed HT20 and HT40 rates */ + /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ + OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11), + PWR_MAS(pPwrArray[ALL_TARGET_HT40_23], 24) + | PWR_MAS(pPwrArray[ALL_TARGET_HT40_22], 16) + | PWR_MAS(pPwrArray[ALL_TARGET_HT20_23], 8) + | PWR_MAS(pPwrArray[ALL_TARGET_HT20_22], 0) + ); + + /* Write the HT40 power per rate set */ + // correct PAR difference between HT40 and HT20/LEGACY + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ + OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7), + PWR_MAS(pPwrArray[ALL_TARGET_HT40_5], 24) + | PWR_MAS(pPwrArray[ALL_TARGET_HT40_4], 16) + | PWR_MAS(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) + | PWR_MAS(pPwrArray[ALL_TARGET_HT40_0_8_16], 0) + ); + + /* 6 (LSB), 7, 12, 13 (MSB) */ + OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8), + PWR_MAS(pPwrArray[ALL_TARGET_HT40_13], 24) + | PWR_MAS(pPwrArray[ALL_TARGET_HT40_12], 16) + | PWR_MAS(pPwrArray[ALL_TARGET_HT40_7], 8) + | PWR_MAS(pPwrArray[ALL_TARGET_HT40_6], 0) + ); + + /* 14 (LSB), 15, 20, 21 */ + OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(12), + PWR_MAS(pPwrArray[ALL_TARGET_HT40_21], 24) + | PWR_MAS(pPwrArray[ALL_TARGET_HT40_20], 16) + | PWR_MAS(pPwrArray[ALL_TARGET_HT40_15], 8) + | PWR_MAS(pPwrArray[ALL_TARGET_HT40_14], 0) + ); +#undef PWR_MAS +} + +void +ar9300_tx99_tgt_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) +{ + if (tx_chainmask == 0x5) { + OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); + } + OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); + OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); + + OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); + if (tx_chainmask == 0x5) { + OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); + } +} + +void +ar9300_tx99_tgt_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype) +{ + OS_REG_WRITE(ah, AR_PHY_TST_DAC_CONST, OS_REG_READ(ah, AR_PHY_TST_DAC_CONST) | (0x7ff<<11) | 0x7ff); + OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, OS_REG_READ(ah, AR_PHY_TEST_CTL_STATUS) | (1<<7) | (1<<1)); + OS_REG_WRITE(ah, AR_PHY_ADDAC_PARA_CTL, (OS_REG_READ(ah, AR_PHY_ADDAC_PARA_CTL) | (1<<31) | (1<<15)) & ~(1<<13)); + + /* 11G mode */ + if (!chtype) + { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) + | (0x1 << 3) | (0x1 << 2)); + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) + & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24)) + & ~(0x1 << 22)); + } else { + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP) + & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24)) + & ~(0x1 << 22)); + } + + /* chain zero */ + if((tx_chain_mask & 0x01) == 0x01) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) + | (0x1 << 31) | (0x5 << 15) + | (0x3 << 9)) & ~(0x1 << 27) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7)) & ~(0x1 << 11)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) + | (0x1 << 31)); + } + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + /* chain one */ + if ((tx_chain_mask & 0x02) == 0x02 ) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) + | (0x1 << 31) | (0x5 << 15) + | (0x3 << 9)) & ~(0x1 << 27) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7)) & ~(0x1 << 11)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) + | (0x1 << 31)); + } + } + if (AR_SREV_OSPREY(ah)) { + /* chain two */ + if ((tx_chain_mask & 0x04) == 0x04 ) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) + | (0x1 << 31) | (0x5 << 15) + | (0x3 << 9)) & ~(0x1 << 27) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7)) & ~(0x1 << 11)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) + | (0x1 << 31)); + } + } + + OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0x11111); + OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x111); + } + else + { + /* chain zero */ + if((tx_chain_mask & 0x01) == 0x01) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) + | (0x1 << 31) | (0x1 << 27) + | (0x3 << 23) | (0x1 << 19) + | (0x1 << 15) | (0x3 << 9)) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7) | (0x1 << 3) + | (0x1 << 2) | (0x1 << 1)) + & ~(0x1 << 11)& ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) + | (0x3 << 3) | (0x3 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) + | (0x3 << 29) | (0x3 << 26) + | (0x2 << 23) | (0x2 << 20) + | (0x2 << 17))& ~(0x1 << 14)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) + | (0x1 << 31)); + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) + & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } else { + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP) + & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } + + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) + | (0x1 << 23)); + } + if (AR_SREV_OSPREY(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) + | (0x1 << 23)); + } + } + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + /* chain one */ + if ((tx_chain_mask & 0x02) == 0x02 ) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) + | (0x1 << 23)); + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) + & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } else { + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP) + & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } + + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) + | (0x1 << 31) | (0x1 << 27) + | (0x3 << 23) | (0x1 << 19) + | (0x1 << 15) | (0x3 << 9)) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7) | (0x1 << 3) + | (0x1 << 2) | (0x1 << 1)) + & ~(0x1 << 11)& ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) + | (0x3 << 3) | (0x3 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) + | (0x3 << 29) | (0x3 << 26) + | (0x2 << 23) | (0x2 << 20) + | (0x2 << 17))& ~(0x1 << 14)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) + | (0x1 << 31)); + + if (AR_SREV_OSPREY(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) + | (0x1 << 23)); + } + } + } + if (AR_SREV_OSPREY(ah)) { + /* chain two */ + if ((tx_chain_mask & 0x04) == 0x04 ) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) + | (0x1 << 23)); + if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) + & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } else { + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP) + & ~(0x1 << 4)); + OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2) + | (0x1 << 26) | (0x7 << 24) + | (0x3 << 22)); + } + + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) + | (0x1 << 3) | (0x1 << 2) + | (0x1 << 1)) & ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) + | (0x1 << 19) | (0x1 << 3)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) + | (0x1 << 23)); + + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) + | (0x1 << 31) | (0x1 << 27) + | (0x3 << 23) | (0x1 << 19) + | (0x1 << 15) | (0x3 << 9)) + & ~(0x1 << 12)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 7) | (0x1 << 3) + | (0x1 << 2) | (0x1 << 1)) + & ~(0x1 << 11)& ~(0x1 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) + | (0x1 << 29) | (0x1 << 25) + | (0x1 << 23) | (0x1 << 19) + | (0x1 << 10) | (0x1 << 9) + | (0x1 << 8) | (0x1 << 3)) + & ~(0x1 << 28)& ~(0x1 << 24) + & ~(0x1 << 22)& ~(0x1 << 7)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) + | (0x1 << 23))& ~(0x1 << 21)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) + | (0x3 << 3) | (0x3 << 0)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) + | (0x3 << 29) | (0x3 << 26) + | (0x2 << 23) | (0x2 << 20) + | (0x2 << 17))& ~(0x1 << 14)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) + | (0x1 << 12) | (0x1 << 10) + | (0x1 << 9) | (0x1 << 8) + | (0x1 << 6) | (0x1 << 5) + | (0x1 << 4) | (0x1 << 3) + | (0x1 << 2)); + OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) + | (0x1 << 31)); + } + } + + OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0x22222); + OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x222); + } +} + +void +ar9300_tx99_tgt_start(struct ath_hal *ah, u_int8_t data) +{ + a_uint32_t val; + a_uint32_t qnum = (a_uint32_t)data; + + /* Disable AGC to A2 */ + OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) ); + OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000); + OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe); + OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); + //OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_FORCE_RX_CLEAR+AR_DIAG_IGNORE_VIRT_CS)); + OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); // set receive disable + //set CW_MIN and CW_MAX both to 0, AIFS=2 + OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); + OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); //50 OK + OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); + OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); //200 ok for HT20, 400 ok for HT40 + OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); + + /* set QCU modes to early termination */ + val = OS_REG_READ(ah, AR_QMISC(qnum)); + OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); +} + +void +ar9300_tx99_tgt_stop(struct ath_hal *ah) +{ + OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); + OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ (AR_DIAG_FORCE_RX_CLEAR | AR_DIAG_IGNORE_VIRT_CS)); +} +#endif diff --git a/hal/ar9300/ar9300_txbf.c b/hal/ar9300/ar9300_txbf.c new file mode 100644 index 000000000000..64aa12dce231 --- /dev/null +++ b/hal/ar9300/ar9300_txbf.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" +#include "ah_desc.h" +#include "ar9300.h" +#include "ar9300desc.h" +#include "ar9300reg.h" +#include "ar9300phy.h" + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_txbf.h b/hal/ar9300/ar9300_txbf.h new file mode 100644 index 000000000000..f0119ab0b4d6 --- /dev/null +++ b/hal/ar9300/ar9300_txbf.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _ATH_AR9000_TxBF_CAL_H_ +#define _ATH_AR9300_TxBF_CAL_H_ +#endif diff --git a/hal/ar9300/ar9300_txbf_cal.c b/hal/ar9300/ar9300_txbf_cal.c new file mode 100644 index 000000000000..a0756f5d800c --- /dev/null +++ b/hal/ar9300/ar9300_txbf_cal.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_internal.h" +#include "ar9300reg.h" + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_xmit.c b/hal/ar9300/ar9300_xmit.c new file mode 100644 index 000000000000..8dcbf5aaee40 --- /dev/null +++ b/hal/ar9300/ar9300_xmit.c @@ -0,0 +1,910 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_desc.h" +#include "ah_internal.h" + +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300phy.h" +#include "ar9300/ar9300desc.h" + +/* + * Update Tx FIFO trigger level. + * + * Set b_inc_trig_level to TRUE to increase the trigger level. + * Set b_inc_trig_level to FALSE to decrease the trigger level. + * + * Returns TRUE if the trigger level was updated + */ +HAL_BOOL +ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + u_int32_t txcfg, cur_level, new_level; + HAL_INT omask; + + if (AH_PRIVATE(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD && + b_inc_trig_level) + { + return AH_FALSE; + } + + /* + * Disable interrupts while futzing with the fifo level. + */ + omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0); + + txcfg = OS_REG_READ(ah, AR_TXCFG); + cur_level = MS(txcfg, AR_FTRIG); + new_level = cur_level; + + if (b_inc_trig_level) { /* increase the trigger level */ + if (cur_level < MAX_TX_FIFO_THRESHOLD) { + new_level++; + } + } else if (cur_level > MIN_TX_FIFO_THRESHOLD) { + new_level--; + } + + if (new_level != cur_level) { + /* Update the trigger level */ + OS_REG_WRITE(ah, + AR_TXCFG, (txcfg &~ AR_FTRIG) | SM(new_level, AR_FTRIG)); + } + + /* re-enable chip interrupts */ + ar9300_set_interrupts(ah, omask, 0); + + AH_PRIVATE(ah)->ah_tx_trig_level = new_level; + + return (new_level != cur_level); +} + +/* + * Returns the value of Tx Trigger Level + */ +u_int16_t +ar9300_get_tx_trig_level(struct ath_hal *ah) +{ + return (AH_PRIVATE(ah)->ah_tx_trig_level); +} + +/* + * Set the properties of the tx queue with the parameters + * from q_info. + */ +HAL_BOOL +ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + + if (q >= p_cap->hal_total_queues) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); + return AH_FALSE; + } + return ath_hal_set_tx_q_props(ah, &ahp->ah_txq[q], q_info); +} + +/* + * Return the properties for the specified tx queue. + */ +HAL_BOOL +ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + + + if (q >= p_cap->hal_total_queues) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); + return AH_FALSE; + } + return ath_hal_get_tx_q_props(ah, q_info, &ahp->ah_txq[q]); +} + +enum { + AH_TX_QUEUE_MINUS_OFFSET_BEACON = 1, + AH_TX_QUEUE_MINUS_OFFSET_CAB = 2, + AH_TX_QUEUE_MINUS_OFFSET_UAPSD = 3, + AH_TX_QUEUE_MINUS_OFFSET_PAPRD = 4, +}; + +/* + * Allocate and initialize a tx DCU/QCU combination. + */ +int +ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type, + const HAL_TXQ_INFO *q_info) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_TX_QUEUE_INFO *qi; + HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + int q; + + /* XXX move queue assignment to driver */ + switch (type) { + case HAL_TX_QUEUE_BEACON: + /* highest priority */ + q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_BEACON; + break; + case HAL_TX_QUEUE_CAB: + /* next highest priority */ + q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_CAB; + break; + case HAL_TX_QUEUE_UAPSD: + q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_UAPSD; + break; + case HAL_TX_QUEUE_PAPRD: + q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD; + break; + case HAL_TX_QUEUE_DATA: + /* + * don't infringe on top 4 queues, reserved for: + * beacon, CAB, UAPSD, PAPRD + */ + for (q = 0; + q < p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD; + q++) + { + if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) { + break; + } + } + if (q == p_cap->hal_total_queues - 3) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: no available tx queue\n", __func__); + return -1; + } + break; + default: + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: bad tx queue type %u\n", __func__, type); + return -1; + } + + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: queue %u\n", __func__, q); + + qi = &ahp->ah_txq[q]; + if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: tx queue %u already active\n", __func__, q); + return -1; + } + + OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO)); + qi->tqi_type = type; + + if (q_info == AH_NULL) { + /* by default enable OK+ERR+DESC+URN interrupts */ + qi->tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE + | TXQ_FLAG_TXERRINT_ENABLE + | TXQ_FLAG_TXDESCINT_ENABLE + | TXQ_FLAG_TXURNINT_ENABLE; + qi->tqi_aifs = INIT_AIFS; + qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */ + qi->tqi_cwmax = INIT_CWMAX; + qi->tqi_shretry = INIT_SH_RETRY; + qi->tqi_lgretry = INIT_LG_RETRY; + qi->tqi_phys_comp_buf = 0; + } else { + qi->tqi_phys_comp_buf = q_info->tqi_comp_buf; + (void) ar9300_set_tx_queue_props(ah, q, q_info); + } + /* NB: must be followed by ar9300_reset_tx_queue */ + return q; +} + +/* + * Update the h/w interrupt registers to reflect a tx q's configuration. + */ +static void +set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s: tx ok 0x%x err 0x%x eol 0x%x urn 0x%x\n", + __func__, + ahp->ah_tx_ok_interrupt_mask, + ahp->ah_tx_err_interrupt_mask, + ahp->ah_tx_eol_interrupt_mask, + ahp->ah_tx_urn_interrupt_mask); + + OS_REG_WRITE(ah, AR_IMR_S0, + SM(ahp->ah_tx_ok_interrupt_mask, AR_IMR_S0_QCU_TXOK)); + OS_REG_WRITE(ah, AR_IMR_S1, + SM(ahp->ah_tx_err_interrupt_mask, AR_IMR_S1_QCU_TXERR) + | SM(ahp->ah_tx_eol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); + OS_REG_RMW_FIELD(ah, + AR_IMR_S2, AR_IMR_S2_QCU_TXURN, ahp->ah_tx_urn_interrupt_mask); + ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2); +} + +/* + * Free a tx DCU/QCU combination. + */ +HAL_BOOL +ar9300_release_tx_queue(struct ath_hal *ah, u_int q) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + HAL_TX_QUEUE_INFO *qi; + + if (q >= p_cap->hal_total_queues) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); + return AH_FALSE; + } + + qi = &ahp->ah_txq[q]; + if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q); + return AH_FALSE; + } + + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: release queue %u\n", __func__, q); + + qi->tqi_type = HAL_TX_QUEUE_INACTIVE; + ahp->ah_tx_ok_interrupt_mask &= ~(1 << q); + ahp->ah_tx_err_interrupt_mask &= ~(1 << q); + ahp->ah_tx_eol_interrupt_mask &= ~(1 << q); + ahp->ah_tx_urn_interrupt_mask &= ~(1 << q); + set_tx_q_interrupts(ah, qi); + + return AH_TRUE; +} + +/* + * Set the retry, aifs, cwmin/max, ready_time regs for specified queue + * Assumes: + * phw_channel has been set to point to the current channel + */ +HAL_BOOL +ar9300_reset_tx_queue(struct ath_hal *ah, u_int q) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ath_hal_private *ap = AH_PRIVATE(ah); + HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; + HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + HAL_TX_QUEUE_INFO *qi; + u_int32_t cw_min, chan_cw_min, value; + + if (q >= p_cap->hal_total_queues) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); + return AH_FALSE; + } + + qi = &ahp->ah_txq[q]; + if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q); + return AH_TRUE; /* XXX??? */ + } + + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: reset queue %u\n", __func__, q); + + if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) { + /* + * Select cwmin according to channel type. + * NB: chan can be NULL during attach + */ + if (chan && IS_CHAN_B(chan)) { + chan_cw_min = INIT_CWMIN_11B; + } else { + chan_cw_min = INIT_CWMIN; + } + /* make sure that the CWmin is of the form (2^n - 1) */ + for (cw_min = 1; cw_min < chan_cw_min; cw_min = (cw_min << 1) | 1) {} + } else { + cw_min = qi->tqi_cwmin; + } + + /* set cw_min/Max and AIFS values */ + if (q > 3 || (!ah->ah_fccaifs)) + /* values should not be overwritten if domain is FCC and manual rate + less than 24Mb is set, this check is making sure this */ + { + OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN) + | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) + | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); + } + + /* Set retry limit values */ + OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), + SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | + SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | + SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); + + /* enable early termination on the QCU */ + OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); + + /* enable DCU to wait for next fragment from QCU */ + if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) { + /* WAR for EV#85395: Wasp Rx overrun issue - reduces Tx queue backoff + * threshold to 1 to avoid Rx overruns - Fixed in Wasp 1.3 */ + OS_REG_WRITE(ah, AR_DMISC(q), + AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1); + } else { + OS_REG_WRITE(ah, AR_DMISC(q), + AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2); + } + + /* multiqueue support */ + if (qi->tqi_cbr_period) { + OS_REG_WRITE(ah, + AR_QCBRCFG(q), + SM(qi->tqi_cbr_period, AR_Q_CBRCFG_INTERVAL) | + SM(qi->tqi_cbr_overflow_limit, + AR_Q_CBRCFG_OVF_THRESH)); + OS_REG_WRITE(ah, AR_QMISC(q), + OS_REG_READ(ah, AR_QMISC(q)) | + AR_Q_MISC_FSP_CBR | + (qi->tqi_cbr_overflow_limit ? + AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0)); + } + + if (qi->tqi_ready_time && (qi->tqi_type != HAL_TX_QUEUE_CAB)) { + OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), + SM(qi->tqi_ready_time, AR_Q_RDYTIMECFG_DURATION) | + AR_Q_RDYTIMECFG_EN); + } + + OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burst_time, AR_D_CHNTIME_DUR) | + (qi->tqi_burst_time ? AR_D_CHNTIME_EN : 0)); + + if (qi->tqi_burst_time && + (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) + { + OS_REG_WRITE(ah, AR_QMISC(q), OS_REG_READ(ah, AR_QMISC(q)) | + AR_Q_MISC_RDYTIME_EXP_POLICY); + } + + if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) { + OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) | + AR_D_MISC_POST_FR_BKOFF_DIS); + } + + if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { + OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) | + AR_D_MISC_FRAG_BKOFF_EN); + } + + switch (qi->tqi_type) { + case HAL_TX_QUEUE_BEACON: /* beacon frames */ + OS_REG_WRITE(ah, AR_QMISC(q), + OS_REG_READ(ah, AR_QMISC(q)) + | AR_Q_MISC_FSP_DBA_GATED + | AR_Q_MISC_BEACON_USE + | AR_Q_MISC_CBR_INCR_DIS1); + + OS_REG_WRITE(ah, AR_DMISC(q), + OS_REG_READ(ah, AR_DMISC(q)) + | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << + AR_D_MISC_ARB_LOCKOUT_CNTRL_S) + | AR_D_MISC_BEACON_USE + | AR_D_MISC_POST_FR_BKOFF_DIS); + /* XXX cwmin and cwmax should be 0 for beacon queue */ + if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) { + OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) + | SM(0, AR_D_LCL_IFS_CWMAX) + | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); + } + break; + case HAL_TX_QUEUE_CAB: /* CAB frames */ + /* + * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY, + * bug #6079. There is an issue with the CAB Queue + * not properly refreshing the Tx descriptor if + * the TXE clear setting is used. + */ + OS_REG_WRITE(ah, AR_QMISC(q), + OS_REG_READ(ah, AR_QMISC(q)) + | AR_Q_MISC_FSP_DBA_GATED + | AR_Q_MISC_CBR_INCR_DIS1 + | AR_Q_MISC_CBR_INCR_DIS0); + + value = TU_TO_USEC(qi->tqi_ready_time) + - (ap->ah_config.ath_hal_sw_beacon_response_time + - ap->ah_config.ath_hal_dma_beacon_response_time) + - ap->ah_config.ath_hal_additional_swba_backoff; + OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN); + + OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) + | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << + AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); + break; + case HAL_TX_QUEUE_PSPOLL: + /* + * We may configure ps_poll QCU to be TIM-gated in the + * future; TIM_GATED bit is not enabled currently because + * of a hardware problem in Oahu that overshoots the TIM + * bitmap in beacon and may find matching associd bit in + * non-TIM elements and send PS-poll PS poll processing + * will be done in software + */ + OS_REG_WRITE(ah, AR_QMISC(q), + OS_REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1); + break; + case HAL_TX_QUEUE_UAPSD: + OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) + | AR_D_MISC_POST_FR_BKOFF_DIS); + break; + default: /* NB: silence compiler */ + break; + } + +#ifndef AH_DISABLE_WME + /* + * Yes, this is a hack and not the right way to do it, but + * it does get the lockout bits and backoff set for the + * high-pri WME queues for testing. We need to either extend + * the meaning of queue_info->mode, or create something like + * queue_info->dcumode. + */ + if (qi->tqi_int_flags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) { + OS_REG_WRITE(ah, AR_DMISC(q), + OS_REG_READ(ah, AR_DMISC(q)) | + SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, + AR_D_MISC_ARB_LOCKOUT_CNTRL) | + AR_D_MISC_POST_FR_BKOFF_DIS); + } +#endif + + OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); + + /* + * Always update the secondary interrupt mask registers - this + * could be a new queue getting enabled in a running system or + * hw getting re-initialized during a reset! + * + * Since we don't differentiate between tx interrupts corresponding + * to individual queues - secondary tx mask regs are always unmasked; + * tx interrupts are enabled/disabled for all queues collectively + * using the primary mask reg + */ + if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) { + ahp->ah_tx_ok_interrupt_mask |= (1 << q); + } else { + ahp->ah_tx_ok_interrupt_mask &= ~(1 << q); + } + if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) { + ahp->ah_tx_err_interrupt_mask |= (1 << q); + } else { + ahp->ah_tx_err_interrupt_mask &= ~(1 << q); + } + if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) { + ahp->ah_tx_eol_interrupt_mask |= (1 << q); + } else { + ahp->ah_tx_eol_interrupt_mask &= ~(1 << q); + } + if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) { + ahp->ah_tx_urn_interrupt_mask |= (1 << q); + } else { + ahp->ah_tx_urn_interrupt_mask &= ~(1 << q); + } + set_tx_q_interrupts(ah, qi); + + return AH_TRUE; +} + +/* + * Get the TXDP for the specified queue + */ +u_int32_t +ar9300_get_tx_dp(struct ath_hal *ah, u_int q) +{ + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); + return OS_REG_READ(ah, AR_QTXDP(q)); +} + +/* + * Set the tx_dp for the specified queue + */ +HAL_BOOL +ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp) +{ + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); + HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); + HALASSERT(txdp != 0); + + OS_REG_WRITE(ah, AR_QTXDP(q), txdp); + + return AH_TRUE; +} + +/* + * Transmit Enable is read-only now + */ +HAL_BOOL +ar9300_start_tx_dma(struct ath_hal *ah, u_int q) +{ + return AH_TRUE; +} + +/* + * Return the number of pending frames or 0 if the specified + * queue is stopped. + */ +u_int32_t +ar9300_num_tx_pending(struct ath_hal *ah, u_int q) +{ + u_int32_t npend; + + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); + + npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; + if (npend == 0) { + /* + * Pending frame count (PFC) can momentarily go to zero + * while TXE remains asserted. In other words a PFC of + * zero is not sufficient to say that the queue has stopped. + */ + if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) { + npend = 1; /* arbitrarily return 1 */ + } + } +#ifdef DEBUG + if (npend && (AH9300(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) { + if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, "RTSD on CAB queue\n"); + /* Clear the ready_time shutdown status bits */ + OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q); + } + } +#endif + HALASSERT((npend == 0) || + (AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE)); + + return npend; +} + +/* + * Stop transmit on the specified queue + */ +HAL_BOOL +ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout) +{ + /* + * Directly call abort. It is better, hardware-wise, to stop all + * queues at once than individual ones. + */ + return ar9300_abort_tx_dma(ah); + +#if 0 +#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */ +#define AH_TIME_QUANTUM 100 /* usec */ + u_int wait; + + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); + + HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); + + if (timeout == 0) { + timeout = AH_TX_STOP_DMA_TIMEOUT; + } + + OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); + + for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { + if (ar9300_num_tx_pending(ah, q) == 0) { + break; + } + OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */ + } + +#ifdef AH_DEBUG + if (wait == 0) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: queue %u DMA did not stop in 100 msec\n", __func__, q); + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", + __func__, + OS_REG_READ(ah, AR_QSTS(q)), + OS_REG_READ(ah, AR_Q_TXE), + OS_REG_READ(ah, AR_Q_TXD), + OS_REG_READ(ah, AR_QCBRCFG(q))); + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n", + __func__, + OS_REG_READ(ah, AR_QMISC(q)), + OS_REG_READ(ah, AR_QRDYTIMECFG(q)), + OS_REG_READ(ah, AR_Q_RDYTIMESHDN)); + } +#endif /* AH_DEBUG */ + + /* 2413+ and up can kill packets at the PCU level */ + if (ar9300_num_tx_pending(ah, q)) { + u_int32_t tsf_low, j; + + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n", + __func__, ar9300_num_tx_pending(ah, q), q); + + /* Kill last PCU Tx Frame */ + /* TODO - save off and restore current values of Q1/Q2? */ + for (j = 0; j < 2; j++) { + tsf_low = OS_REG_READ(ah, AR_TSF_L32); + OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR)); + OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100); + OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10); + OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); + + if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) { + break; + } + + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: TSF have moved while trying to set " + "quiet time TSF: 0x%08x\n", + __func__, tsf_low); + /* TSF shouldn't count twice or reg access is taking forever */ + HALASSERT(j < 1); + } + + OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); + + /* Allow the quiet mechanism to do its work */ + OS_DELAY(200); + OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); + + /* Verify all transmit is dead */ + wait = timeout / AH_TIME_QUANTUM; + while (ar9300_num_tx_pending(ah, q)) { + if ((--wait) == 0) { + HALDEBUG(ah, HAL_DEBUG_TX, + "%s: Failed to stop Tx DMA in %d msec " + "after killing last frame\n", + __func__, timeout / 1000); + break; + } + OS_DELAY(AH_TIME_QUANTUM); + } + + OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); + } + + OS_REG_WRITE(ah, AR_Q_TXD, 0); + return (wait != 0); + +#undef AH_TX_STOP_DMA_TIMEOUT +#undef AH_TIME_QUANTUM +#endif +} + +/* + * Really Stop transmit on the specified queue + */ +HAL_BOOL +ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout) +{ +#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */ +#define AH_TIME_QUANTUM 100 /* usec */ + u_int wait; + + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); + + HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); + + if (timeout == 0) { + timeout = AH_TX_STOP_DMA_TIMEOUT; + } + + OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); + + for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { + if (ar9300_num_tx_pending(ah, q) == 0) { + break; + } + OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */ + } + +#ifdef AH_DEBUG + if (wait == 0) { + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: queue %u DMA did not stop in 100 msec\n", __func__, q); + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", + __func__, + OS_REG_READ(ah, AR_QSTS(q)), + OS_REG_READ(ah, AR_Q_TXE), + OS_REG_READ(ah, AR_Q_TXD), + OS_REG_READ(ah, AR_QCBRCFG(q))); + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n", + __func__, + OS_REG_READ(ah, AR_QMISC(q)), + OS_REG_READ(ah, AR_QRDYTIMECFG(q)), + OS_REG_READ(ah, AR_Q_RDYTIMESHDN)); + } +#endif /* AH_DEBUG */ + + /* 2413+ and up can kill packets at the PCU level */ + if (ar9300_num_tx_pending(ah, q)) { + u_int32_t tsf_low, j; + + HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n", + __func__, ar9300_num_tx_pending(ah, q), q); + + /* Kill last PCU Tx Frame */ + /* TODO - save off and restore current values of Q1/Q2? */ + for (j = 0; j < 2; j++) { + tsf_low = OS_REG_READ(ah, AR_TSF_L32); + OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR)); + OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100); + OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10); + OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); + + if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) { + break; + } + + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: TSF have moved while trying to set " + "quiet time TSF: 0x%08x\n", + __func__, tsf_low); + /* TSF shouldn't count twice or reg access is taking forever */ + HALASSERT(j < 1); + } + + OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); + + /* Allow the quiet mechanism to do its work */ + OS_DELAY(200); + OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); + + /* Verify all transmit is dead */ + wait = timeout / AH_TIME_QUANTUM; + while (ar9300_num_tx_pending(ah, q)) { + if ((--wait) == 0) { + HALDEBUG(ah, HAL_DEBUG_TX, + "%s: Failed to stop Tx DMA in %d msec " + "after killing last frame\n", + __func__, timeout / 1000); + break; + } + OS_DELAY(AH_TIME_QUANTUM); + } + + OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); + } + + OS_REG_WRITE(ah, AR_Q_TXD, 0); + return (wait != 0); + +#undef AH_TX_STOP_DMA_TIMEOUT +#undef AH_TIME_QUANTUM +} + +/* + * Abort transmit on all queues + */ +#define AR9300_ABORT_LOOPS 1000 +#define AR9300_ABORT_WAIT 5 +HAL_BOOL +ar9300_abort_tx_dma(struct ath_hal *ah) +{ + int i, q; + + /* + * set txd on all queues + */ + OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); + + /* + * set tx abort bits (also disable rx) + */ + OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); + OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | + AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR)); + OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); + + /* Let TXE (all queues) clear before waiting on any pending frames */ + for (i = 0; i < AR9300_ABORT_LOOPS; i++) { + if (OS_REG_READ(ah, AR_Q_TXE) == 0) { + break; + } + OS_DELAY(AR9300_ABORT_WAIT); + } + if (i == AR9300_ABORT_LOOPS) { + HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n", + __func__, __LINE__); + } + + /* + * wait on all tx queues + */ + for (q = 0; q < AR_NUM_QCU; q++) { + for (i = 0; i < AR9300_ABORT_LOOPS; i++) { + if (!ar9300_num_tx_pending(ah, q)) { + break; + } + OS_DELAY(AR9300_ABORT_WAIT); + } + if (i == AR9300_ABORT_LOOPS) { + HALDEBUG(ah, HAL_DEBUG_TX, + "%s[%d] reached max wait on pending tx, q %d\n", + __func__, __LINE__, q); + return AH_FALSE; + } + } + + /* + * clear tx abort bits + */ + OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); + OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | + AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR)); + OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); + + /* + * clear txd + */ + OS_REG_WRITE(ah, AR_Q_TXD, 0); + + return AH_TRUE; +} + +/* + * Determine which tx queues need interrupt servicing. + */ +void +ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs) +{ + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, + "ar9300_get_tx_intr_queue: Should not be called\n"); +#if 0 + struct ath_hal_9300 *ahp = AH9300(ah); + *txqs &= ahp->ah_intr_txqs; + ahp->ah_intr_txqs &= ~(*txqs); +#endif +} + +void +ar9300_reset_tx_status_ring(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + ahp->ts_tail = 0; + + /* Zero out the status descriptors */ + OS_MEMZERO((void *)ahp->ts_ring, ahp->ts_size * sizeof(struct ar9300_txs)); + HALDEBUG(ah, HAL_DEBUG_QUEUE, + "%s: TS Start 0x%x End 0x%x Virt %p, Size %d\n", __func__, + ahp->ts_paddr_start, ahp->ts_paddr_end, ahp->ts_ring, ahp->ts_size); + + OS_REG_WRITE(ah, AR_Q_STATUS_RING_START, ahp->ts_paddr_start); + OS_REG_WRITE(ah, AR_Q_STATUS_RING_END, ahp->ts_paddr_end); +} + +void +ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start, + u_int32_t ts_paddr_start, u_int16_t size) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + + ahp->ts_paddr_start = ts_paddr_start; + ahp->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9300_txs)); + ahp->ts_size = size; + ahp->ts_ring = (struct ar9300_txs *)ts_start; + + ar9300_reset_tx_status_ring(ah); +} + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300_xmit_ds.c b/hal/ar9300/ar9300_xmit_ds.c new file mode 100644 index 000000000000..820c5116ccbd --- /dev/null +++ b/hal/ar9300/ar9300_xmit_ds.c @@ -0,0 +1,947 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "opt_ah.h" + +#ifdef AH_SUPPORT_AR9300 + +#include "ah.h" +#include "ah_desc.h" +#include "ah_internal.h" + +#include "ar9300/ar9300desc.h" +#include "ar9300/ar9300.h" +#include "ar9300/ar9300reg.h" +#include "ar9300/ar9300phy.h" +#include "ah_devid.h" + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN +static void ar9300_swap_tx_desc(void *ds); +#endif + +void +ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds) +{ + HALDEBUG(ah, HAL_DEBUG_INTERRUPT, + "%s:Desc Interrupt not supported\n", __func__); +} + +static inline u_int16_t +ar9300_calc_ptr_chk_sum(struct ar9300_txc *ads) +{ + u_int checksum; + u_int16_t ptrchecksum; + + /* checksum = __bswap32(ads->ds_info) + ads->ds_link */ + checksum = ads->ds_info + ads->ds_link + + ads->ds_data0 + ads->ds_ctl3 + + ads->ds_data1 + ads->ds_ctl5 + + ads->ds_data2 + ads->ds_ctl7 + + ads->ds_data3 + ads->ds_ctl9; + + ptrchecksum = ((checksum & 0xffff) + (checksum >> 16)) & AR_tx_ptr_chk_sum; + return ptrchecksum; +} + + +HAL_BOOL +ar9300_fill_tx_desc( + struct ath_hal *ah, + void *ds, + dma_addr_t *buf_addr, + u_int32_t *seg_len, + u_int desc_id, + u_int qcu, + HAL_KEY_TYPE key_type, + HAL_BOOL first_seg, + HAL_BOOL last_seg, + const void *ds0) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + /* Fill TXC info field */ + ads->ds_info = TXC_INFO(qcu); + + /* Set the buffer addresses */ + ads->ds_data0 = buf_addr[0]; + ads->ds_data1 = buf_addr[1]; + ads->ds_data2 = buf_addr[2]; + ads->ds_data3 = buf_addr[3]; + + /* Set the buffer lengths */ + ads->ds_ctl3 = (seg_len[0] << AR_buf_len_S) & AR_buf_len; + ads->ds_ctl5 = (seg_len[1] << AR_buf_len_S) & AR_buf_len; + ads->ds_ctl7 = (seg_len[2] << AR_buf_len_S) & AR_buf_len; + ads->ds_ctl9 = (seg_len[3] << AR_buf_len_S) & AR_buf_len; + + /* Fill in pointer checksum and descriptor id */ + ads->ds_ctl10 = (desc_id << AR_tx_desc_id_S) | ar9300_calc_ptr_chk_sum(ads); + + if (first_seg) { + /* + * First descriptor, don't clobber xmit control data + * setup by ar9300_set_11n_tx_desc. + * + * Note: AR_encr_type is already setup in the first descriptor by + * set_11n_tx_desc(). + */ + ads->ds_ctl12 |= (last_seg ? 0 : AR_tx_more); + } else if (last_seg) { /* !first_seg && last_seg */ + /* + * Last descriptor in a multi-descriptor frame, + * copy the multi-rate transmit parameters from + * the first frame for processing on completion. + */ + ads->ds_ctl11 = 0; + ads->ds_ctl12 = 0; +#ifdef AH_NEED_DESC_SWAP + ads->ds_ctl13 = __bswap32(AR9300TXC_CONST(ds0)->ds_ctl13); + ads->ds_ctl14 = __bswap32(AR9300TXC_CONST(ds0)->ds_ctl14); + ads->ds_ctl17 = __bswap32(SM(key_type, AR_encr_type)); +#else + ads->ds_ctl13 = AR9300TXC_CONST(ds0)->ds_ctl13; + ads->ds_ctl14 = AR9300TXC_CONST(ds0)->ds_ctl14; + ads->ds_ctl17 = SM(key_type, AR_encr_type); +#endif + } else { /* !first_seg && !last_seg */ + /* + * XXX Intermediate descriptor in a multi-descriptor frame. + */ + ads->ds_ctl11 = 0; + ads->ds_ctl12 = AR_tx_more; + ads->ds_ctl13 = 0; + ads->ds_ctl14 = 0; + ads->ds_ctl17 = SM(key_type, AR_encr_type); + } + + return AH_TRUE; +} + +void +ar9300_set_desc_link(struct ath_hal *ah, void *ds, u_int32_t link) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + ads->ds_link = link; + + /* TODO - checksum is calculated twice for subframes + * Once in filldesc and again when linked. Need to fix. + */ + /* Fill in pointer checksum. Preserve descriptor id */ + ads->ds_ctl10 &= ~AR_tx_ptr_chk_sum; + ads->ds_ctl10 |= ar9300_calc_ptr_chk_sum(ads); +} + +void +ar9300_get_desc_link_ptr(struct ath_hal *ah, void *ds, u_int32_t **link) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + *link = &ads->ds_link; +} + +void +ar9300_clear_tx_desc_status(struct ath_hal *ah, void *ds) +{ + struct ar9300_txs *ads = AR9300TXS(ds); + ads->status1 = ads->status2 = 0; + ads->status3 = ads->status4 = 0; + ads->status5 = ads->status6 = 0; + ads->status7 = ads->status8 = 0; +} + +#ifdef ATH_SWRETRY +void +ar9300_clear_dest_mask(struct ath_hal *ah, void *ds) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + ads->ds_ctl11 |= AR_clr_dest_mask; +} +#endif + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN +/* XXX what words need swapping */ +/* Swap transmit descriptor */ +static __inline void +ar9300_swap_tx_desc(void *dsp) +{ + struct ar9300_txs *ds = (struct ar9300_txs *)dsp; + + ds->ds_info = __bswap32(ds->ds_info); + ds->status1 = __bswap32(ds->status1); + ds->status2 = __bswap32(ds->status2); + ds->status3 = __bswap32(ds->status3); + ds->status4 = __bswap32(ds->status4); + ds->status5 = __bswap32(ds->status5); + ds->status6 = __bswap32(ds->status6); + ds->status7 = __bswap32(ds->status7); + ds->status8 = __bswap32(ds->status8); +} +#endif + + +/* + * Extract the transmit rate code. + */ +void +ar9300_get_tx_rate_code(struct ath_hal *ah, void *ds, struct ath_tx_status *ts) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + switch (ts->ts_rateindex) { + case 0: + ts->ts_ratecode = MS(ads->ds_ctl14, AR_xmit_rate0); + break; + case 1: + ts->ts_ratecode = MS(ads->ds_ctl14, AR_xmit_rate1); + break; + case 2: + ts->ts_ratecode = MS(ads->ds_ctl14, AR_xmit_rate2); + break; + case 3: + ts->ts_ratecode = MS(ads->ds_ctl14, AR_xmit_rate3); + break; + } + + ar9300_set_selfgenrate_limit(ah, ts->ts_ratecode); +} + +/* + * Get TX Status descriptor contents. + */ +void +ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *txstatus) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_txs *ads; + + ads = &ahp->ts_ring[ahp->ts_tail]; + + OS_MEMCPY(txstatus, ads, sizeof(struct ar9300_txs)); +} + +/* + * Processing of HW TX descriptor. + */ +HAL_STATUS +ar9300_proc_tx_desc(struct ath_hal *ah, void *txstatus) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_txs *ads; + struct ath_tx_status *ts = (struct ath_tx_status *)txstatus; + u_int32_t dsinfo; + + ads = &ahp->ts_ring[ahp->ts_tail]; + + if ((ads->status8 & AR_tx_done) == 0) { + return HAL_EINPROGRESS; + } + /* Increment the tail to point to the next status element. */ + ahp->ts_tail = (ahp->ts_tail + 1) & (ahp->ts_size-1); + + /* + ** For big endian systems, ds_info is not swapped as the other + ** registers are. Ensure we use the bswap32 version (which is + ** defined to "nothing" in little endian systems + */ + + /* + * Sanity check + */ + +#if 0 + ath_hal_printf(ah, + "CHH: ds_info 0x%x status1: 0x%x status8: 0x%x\n", + ads->ds_info, ads->status1, ads->status8); +#endif + + dsinfo = ads->ds_info; + + if ((MS(dsinfo, AR_desc_id) != ATHEROS_VENDOR_ID) || + (MS(dsinfo, AR_tx_rx_desc) != 1)) + { + HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "%s: Tx Descriptor error %x\n", + __func__, dsinfo); + HALASSERT(0); + /* Zero out the status for reuse */ + OS_MEMZERO(ads, sizeof(struct ar9300_txs)); + return HAL_EIO; + } + + /* Update software copies of the HW status */ + ts->queue_id = MS(dsinfo, AR_tx_qcu_num); + ts->desc_id = MS(ads->status1, AR_tx_desc_id); + ts->ts_seqnum = MS(ads->status8, AR_seq_num); + ts->ts_tstamp = ads->status4; + ts->ts_status = 0; + ts->ts_flags = 0; + + if (ads->status3 & AR_excessive_retries) { + ts->ts_status |= HAL_TXERR_XRETRY; + } + if (ads->status3 & AR_filtered) { + ts->ts_status |= HAL_TXERR_FILT; + } + if (ads->status3 & AR_fifounderrun) { + ts->ts_status |= HAL_TXERR_FIFO; + ar9300_update_tx_trig_level(ah, AH_TRUE); + } + if (ads->status8 & AR_tx_op_exceeded) { + ts->ts_status |= HAL_TXERR_XTXOP; + } + if (ads->status3 & AR_tx_timer_expired) { + ts->ts_status |= HAL_TXERR_TIMER_EXPIRED; + } + if (ads->status3 & AR_desc_cfg_err) { + ts->ts_flags |= HAL_TX_DESC_CFG_ERR; + } + if (ads->status3 & AR_tx_data_underrun) { + ts->ts_flags |= HAL_TX_DATA_UNDERRUN; + ar9300_update_tx_trig_level(ah, AH_TRUE); + } + if (ads->status3 & AR_tx_delim_underrun) { + ts->ts_flags |= HAL_TX_DELIM_UNDERRUN; + ar9300_update_tx_trig_level(ah, AH_TRUE); + } + if (ads->status2 & AR_tx_ba_status) { + ts->ts_flags |= HAL_TX_BA; + ts->ba_low = ads->status5; + ts->ba_high = ads->status6; + } + + /* + * Extract the transmit rate. + */ + ts->ts_rateindex = MS(ads->status8, AR_final_tx_idx); + + ts->ts_rssi = MS(ads->status7, AR_tx_rssi_combined); + ts->ts_rssi_ctl0 = MS(ads->status2, AR_tx_rssi_ant00); + ts->ts_rssi_ctl1 = MS(ads->status2, AR_tx_rssi_ant01); + ts->ts_rssi_ctl2 = MS(ads->status2, AR_tx_rssi_ant02); + ts->ts_rssi_ext0 = MS(ads->status7, AR_tx_rssi_ant10); + ts->ts_rssi_ext1 = MS(ads->status7, AR_tx_rssi_ant11); + ts->ts_rssi_ext2 = MS(ads->status7, AR_tx_rssi_ant12); + ts->ts_shortretry = MS(ads->status3, AR_rts_fail_cnt); + ts->ts_longretry = MS(ads->status3, AR_data_fail_cnt); + ts->ts_virtcol = MS(ads->status3, AR_virt_retry_cnt); + ts->ts_antenna = 0; + + /* extract TID from block ack */ + ts->tid = MS(ads->status8, AR_tx_tid); + + /* Zero out the status for reuse */ + OS_MEMZERO(ads, sizeof(struct ar9300_txs)); + + return HAL_OK; +} + +/* + * Calculate air time of a transmit packet + * if comp_wastedt is 1, calculate air time only for failed subframes + * this is required for VOW_DCS ( dynamic channel selection ) + */ +u_int32_t +ar9300_calc_tx_airtime(struct ath_hal *ah, void *ds, struct ath_tx_status *ts, + HAL_BOOL comp_wastedt, u_int8_t nbad, u_int8_t nframes ) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + int finalindex_tries; + u_int32_t airtime, lastrate_dur; + + + /* + * Number of attempts made on the final index + * Note: If no BA was recv, then the data_fail_cnt is the number of tries + * made on the final index. If BA was recv, then add 1 to account for the + * successful attempt. + */ + if ( !comp_wastedt ){ + finalindex_tries = ts->ts_longretry + (ts->ts_flags & HAL_TX_BA)? 1 : 0; + } else { + finalindex_tries = ts->ts_longretry ; + } + + /* + * Calculate time of transmit on air for packet including retries + * at different rates. + */ + switch (ts->ts_rateindex) { + case 0: + lastrate_dur = MS(ads->ds_ctl15, AR_packet_dur0); + airtime = (lastrate_dur * finalindex_tries); + break; + case 1: + lastrate_dur = MS(ads->ds_ctl15, AR_packet_dur1); + airtime = (lastrate_dur * finalindex_tries) + + (MS(ads->ds_ctl13, AR_xmit_data_tries0) * + MS(ads->ds_ctl15, AR_packet_dur0)); + break; + case 2: + lastrate_dur = MS(ads->ds_ctl16, AR_packet_dur2); + airtime = (lastrate_dur * finalindex_tries) + + (MS(ads->ds_ctl13, AR_xmit_data_tries1) * + MS(ads->ds_ctl15, AR_packet_dur1)) + + (MS(ads->ds_ctl13, AR_xmit_data_tries0) * + MS(ads->ds_ctl15, AR_packet_dur0)); + break; + case 3: + lastrate_dur = MS(ads->ds_ctl16, AR_packet_dur3); + airtime = (lastrate_dur * finalindex_tries) + + (MS(ads->ds_ctl13, AR_xmit_data_tries2) * + MS(ads->ds_ctl16, AR_packet_dur2)) + + (MS(ads->ds_ctl13, AR_xmit_data_tries1) * + MS(ads->ds_ctl15, AR_packet_dur1)) + + (MS(ads->ds_ctl13, AR_xmit_data_tries0) * + MS(ads->ds_ctl15, AR_packet_dur0)); + break; + default: + HALASSERT(0); + return 0; + } + + if ( comp_wastedt && (ts->ts_flags & HAL_TX_BA)){ + airtime += nbad?((lastrate_dur*nbad) / nframes):0; + } + return airtime; + +} + +#ifdef AH_PRIVATE_DIAG +void +ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode) +{ +#if 0 + static int qnum = 0; + int i; + unsigned int qbits, val, val1, val2; + int prefetch; + struct ar9300_txs *ads = AR9300TXS(ds); + + if (mode == 10) { + return; + } + + if (mode == 7) { /* print status from the cont tx desc */ + if (ads) { + val1 = ads->ds_txstatus1; + val2 = ads->ds_txstatus2; + HALDEBUG(ah, HAL_DEBUG_TXDESC, "s0(%x) s1(%x)\n", + (unsigned)val1, (unsigned)val2); + } + HALDEBUG(ah, HAL_DEBUG_TXDESC, "txe(%x) txd(%x)\n", + OS_REG_READ(ah, AR_Q_TXE), + OS_REG_READ(ah, AR_Q_TXD) + ); + for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { + val = OS_REG_READ(ah, AR_QTXDP(i)); + val2 = OS_REG_READ(ah, AR_QSTS(i)) & AR_Q_STS_PEND_FR_CNT; + HALDEBUG(ah, HAL_DEBUG_TXDESC, "[%d] %x %d\n", i, val, val2); + } + return; + } + if (mode == 8) { /* set TXE for qnum */ + OS_REG_WRITE(ah, AR_Q_TXE, 1 << qnum); + return; + } + if (mode == 9) { + prefetch = (int)ds; + return; + } + + if (mode >= 1) { /* initiate cont tx operation */ + /* Disable AGC to A2 */ + qnum = (int) ds; + + OS_REG_WRITE(ah, AR_PHY_TEST, + (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) ); + + OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000); + OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe); + OS_REG_WRITE(ah, AR_DIAG_SW, + (OS_REG_READ(ah, AR_DIAG_SW) | + (AR_DIAG_FORCE_RX_CLEAR + AR_DIAG_IGNORE_VIRT_CS)) ); + + + OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ + + if (mode == 3 || mode == 4) { + int txcfg; + + if (mode == 3) { + OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); + OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); + OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 100); + OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 100); + OS_REG_WRITE(ah, AR_TIME_OUT, 2); + OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 100); + } + + OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); + /* enable prefetch on qnum */ + OS_REG_WRITE(ah, AR_D_FPCTL, 0x10 | qnum); + txcfg = 5 | (6 << AR_FTRIG_S); + OS_REG_WRITE(ah, AR_TXCFG, txcfg); + + OS_REG_WRITE(ah, AR_QMISC(qnum), /* set QCU modes */ + AR_Q_MISC_DCU_EARLY_TERM_REQ + + AR_Q_MISC_FSP_ASAP + + AR_Q_MISC_CBR_INCR_DIS1 + + AR_Q_MISC_CBR_INCR_DIS0 + ); + + /* stop tx dma all all except qnum */ + qbits = 0x3ff; + qbits &= ~(1 << qnum); + for (i = 0; i < 10; i++) { + if (i == qnum) { + continue; + } + OS_REG_WRITE(ah, AR_Q_TXD, 1 << i); + } + + OS_REG_WRITE(ah, AR_Q_TXD, qbits); + + /* clear and freeze MIB counters */ + OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); + OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); + + OS_REG_WRITE(ah, AR_DMISC(qnum), + (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << + AR_D_MISC_ARB_LOCKOUT_CNTRL_S) + + (AR_D_MISC_ARB_LOCKOUT_IGNORE) + + (AR_D_MISC_POST_FR_BKOFF_DIS) + + (AR_D_MISC_VIR_COL_HANDLING_IGNORE << + AR_D_MISC_VIR_COL_HANDLING_S)); + + for (i = 0; i < HAL_NUM_TX_QUEUES + 2; i++) { /* disconnect QCUs */ + if (i == qnum) { + continue; + } + OS_REG_WRITE(ah, AR_DQCUMASK(i), 0); + } + } + } + if (mode == 0) { + OS_REG_WRITE(ah, AR_PHY_TEST, + (OS_REG_READ(ah, AR_PHY_TEST) & ~PHY_AGC_CLR)); + OS_REG_WRITE(ah, AR_DIAG_SW, + (OS_REG_READ(ah, AR_DIAG_SW) & + ~(AR_DIAG_FORCE_RX_CLEAR + AR_DIAG_IGNORE_VIRT_CS))); + } +#endif +} +#endif + +void +ar9300_set_paprd_tx_desc(struct ath_hal *ah, void *ds, int chain_num) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + ads->ds_ctl12 |= SM((1 << chain_num), AR_paprd_chain_mask); +} +HAL_STATUS +ar9300_is_tx_done(struct ath_hal *ah) +{ + struct ath_hal_9300 *ahp = AH9300(ah); + struct ar9300_txs *ads; + + ads = &ahp->ts_ring[ahp->ts_tail]; + + if (ads->status8 & AR_tx_done) { + return HAL_OK; + } + return HAL_EINPROGRESS; +} + +void +ar9300_set_11n_tx_desc( + struct ath_hal *ah, + void *ds, + u_int pkt_len, + HAL_PKT_TYPE type, + u_int tx_power, + u_int key_ix, + HAL_KEY_TYPE key_type, + u_int flags) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + struct ath_hal_9300 *ahp = AH9300(ah); + + HALASSERT(is_valid_pkt_type(type)); + HALASSERT(is_valid_key_type(key_type)); + + tx_power += ahp->ah_tx_power_index_offset; + if (tx_power > 63) { + tx_power = 63; + } + ads->ds_ctl11 = + (pkt_len & AR_frame_len) + | (flags & HAL_TXDESC_VMF ? AR_virt_more_frag : 0) + | SM(tx_power, AR_xmit_power0) + | (flags & HAL_TXDESC_VEOL ? AR_veol : 0) + | (flags & HAL_TXDESC_CLRDMASK ? AR_clr_dest_mask : 0) + | (key_ix != HAL_TXKEYIX_INVALID ? AR_dest_idx_valid : 0) + | (flags & HAL_TXDESC_LOWRXCHAIN ? AR_low_rx_chain : 0); + + ads->ds_ctl12 = + (key_ix != HAL_TXKEYIX_INVALID ? SM(key_ix, AR_dest_idx) : 0) + | SM(type, AR_frame_type) + | (flags & HAL_TXDESC_NOACK ? AR_no_ack : 0) + | (flags & HAL_TXDESC_EXT_ONLY ? AR_ext_only : 0) + | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ext_and_ctl : 0); + + ads->ds_ctl17 = + SM(key_type, AR_encr_type) | (flags & HAL_TXDESC_LDPC ? AR_ldpc : 0); + + ads->ds_ctl18 = 0; + ads->ds_ctl19 = AR_not_sounding; /* set not sounding for normal frame */ + + + /* + * Clear Ness1/2/3 (Number of Extension Spatial Streams) fields. + * Ness0 is cleared in ctl19. See EV66059 (BB panic). + */ + ads->ds_ctl20 = 0; + ads->ds_ctl21 = 0; + ads->ds_ctl22 = 0; +} + +void ar9300_set_rx_chainmask(struct ath_hal *ah, int rxchainmask) +{ + OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rxchainmask); +} + +void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit) +{ + u_int32_t reg_val; + reg_val = OS_REG_READ(ah, AR_LOC_CTL_REG); + if (pos_bit) { + if (!(reg_val & AR_LOC_CTL_REG_FS)) { + /* set fast timestamp bit in the regiter */ + OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val | AR_LOC_CTL_REG_FS)); + OS_REG_WRITE(ah, AR_LOC_TIMER_REG, 0); + } + } + else { + OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val & ~AR_LOC_CTL_REG_FS)); + } +} + +#if 0 +#define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) +static const u_int8_t ba_duration_delta[] = { + 24, /* 0: BPSK */ + 12, /* 1: QPSK 1/2 */ + 12, /* 2: QPSK 3/4 */ + 4, /* 3: 16-QAM 1/2 */ + 4, /* 4: 16-QAM 3/4 */ + 4, /* 5: 64-QAM 2/3 */ + 4, /* 6: 64-QAM 3/4 */ + 4, /* 7: 64-QAM 5/6 */ + 24, /* 8: BPSK */ + 12, /* 9: QPSK 1/2 */ + 12, /* 10: QPSK 3/4 */ + 4, /* 11: 16-QAM 1/2 */ + 4, /* 12: 16-QAM 3/4 */ + 4, /* 13: 64-QAM 2/3 */ + 4, /* 14: 64-QAM 3/4 */ + 4, /* 15: 64-QAM 5/6 */ +}; +#endif + + +static u_int8_t +ar9300_get_tx_mode(u_int rate_flags) +{ + + /* Check whether STBC is enabled if TxBF is not enabled */ + if (rate_flags & HAL_RATESERIES_STBC){ + return AR9300_STBC_MODE; + } + return AR9300_DEF_MODE; +} +void +ar9300_set_11n_rate_scenario( + struct ath_hal *ah, + void *ds, + void *lastds, + u_int dur_update_en, + u_int rts_cts_rate, + u_int rts_cts_duration, + HAL_11N_RATE_SERIES series[], + u_int nseries, + u_int flags, + u_int32_t smart_antenna) +{ + struct ath_hal_private *ap = AH_PRIVATE(ah); + struct ar9300_txc *ads = AR9300TXC(ds); + struct ar9300_txc *last_ads = AR9300TXC(lastds); + u_int32_t ds_ctl11; + u_int8_t ant, cal_pkt = 0; + u_int mode, tx_mode = AR9300_DEF_MODE; + + HALASSERT(nseries == 4); + (void)nseries; + (void)rts_cts_duration; /* use H/W to calculate RTSCTSDuration */ + + ds_ctl11 = ads->ds_ctl11; + /* + * Rate control settings override + */ + if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { + if (flags & HAL_TXDESC_RTSENA) { + ds_ctl11 &= ~AR_cts_enable; + ds_ctl11 |= AR_rts_enable; + } else { + ds_ctl11 &= ~AR_rts_enable; + ds_ctl11 |= AR_cts_enable; + } + } else { + ds_ctl11 = (ds_ctl11 & ~(AR_rts_enable | AR_cts_enable)); + } + + mode = ath_hal_get_curmode(ah, ap->ah_curchan); + cal_pkt = (ads->ds_ctl12 & AR_paprd_chain_mask)?1:0; + + if (ap->ah_config.ath_hal_desc_tpc ) { + int16_t txpower; + + if (!cal_pkt) { + /* Series 0 TxPower */ + tx_mode = ar9300_get_tx_mode(series[0].RateFlags); + txpower = ar9300_get_rate_txpower(ah, mode, series[0].rate_index, + series[0].ch_sel, tx_mode); + } else { + txpower = AH9300(ah)->paprd_training_power; + } + ds_ctl11 &= ~AR_xmit_power0; + ds_ctl11 |= + set_11n_tx_power(0, AH_MIN(txpower, series[0].tx_power_cap)); + } + + ads->ds_ctl11 = ds_ctl11; + + + ads->ds_ctl13 = set_11n_tries(series, 0) + | set_11n_tries(series, 1) + | set_11n_tries(series, 2) + | set_11n_tries(series, 3) + | (dur_update_en ? AR_dur_update_ena : 0) + | SM(0, AR_burst_dur); + + ads->ds_ctl14 = set_11n_rate(series, 0) + | set_11n_rate(series, 1) + | set_11n_rate(series, 2) + | set_11n_rate(series, 3); + + ads->ds_ctl15 = set_11n_pkt_dur_rts_cts(series, 0) + | set_11n_pkt_dur_rts_cts(series, 1); + + ads->ds_ctl16 = set_11n_pkt_dur_rts_cts(series, 2) + | set_11n_pkt_dur_rts_cts(series, 3); + + ads->ds_ctl18 = set_11n_rate_flags(series, 0) + | set_11n_rate_flags(series, 1) + | set_11n_rate_flags(series, 2) + | set_11n_rate_flags(series, 3) + | SM(rts_cts_rate, AR_rts_cts_rate); + /* set not sounding for normal frame */ + ads->ds_ctl19 = AR_not_sounding; + + if (ap->ah_config.ath_hal_desc_tpc) { + int16_t txpower; + + if (!cal_pkt) { + /* Series 1 TxPower */ + tx_mode = ar9300_get_tx_mode(series[1].RateFlags); + txpower = ar9300_get_rate_txpower( + ah, mode, series[1].rate_index, series[1].ch_sel, tx_mode); + } else { + txpower = AH9300(ah)->paprd_training_power; + } + ads->ds_ctl20 |= + set_11n_tx_power(1, AH_MIN(txpower, series[1].tx_power_cap)); + + + /* Series 2 TxPower */ + if (!cal_pkt) { + tx_mode = ar9300_get_tx_mode(series[2].RateFlags); + txpower = ar9300_get_rate_txpower( + ah, mode, series[2].rate_index, series[2].ch_sel, tx_mode); + } else { + txpower = AH9300(ah)->paprd_training_power; + } + ads->ds_ctl21 |= + set_11n_tx_power(2, AH_MIN(txpower, series[2].tx_power_cap)); + + /* Series 3 TxPower */ + if (!cal_pkt) { + tx_mode = ar9300_get_tx_mode(series[3].RateFlags); + txpower = ar9300_get_rate_txpower( + ah, mode, series[3].rate_index, series[3].ch_sel, tx_mode); + } else { + txpower = AH9300(ah)->paprd_training_power; + } + ads->ds_ctl22 |= + set_11n_tx_power(3, AH_MIN(txpower, series[3].tx_power_cap)); + } + + if (smart_antenna != 0xffffffff) + { + /* TX DESC dword 19 to 23 are used for smart antenna configuaration + * ctl19 for rate series 0 ... ctrl22 for series 3 + * bits[2:0] used to configure smart anntenna + */ + ant = (smart_antenna&0x000000ff); + ads->ds_ctl19 |= ant; /* rateseries 0 */ + + ant = (smart_antenna&0x0000ff00) >> 8; + ads->ds_ctl20 |= ant; /* rateseries 1 */ + + ant = (smart_antenna&0x00ff0000) >> 16; + ads->ds_ctl21 |= ant; /* rateseries 2 */ + + ant = (smart_antenna&0xff000000) >> 24; + ads->ds_ctl22 |= ant; /* rateseries 3 */ + } + +#ifdef AH_NEED_DESC_SWAP + last_ads->ds_ctl13 = __bswap32(ads->ds_ctl13); + last_ads->ds_ctl14 = __bswap32(ads->ds_ctl14); +#else + last_ads->ds_ctl13 = ads->ds_ctl13; + last_ads->ds_ctl14 = ads->ds_ctl14; +#endif +} + +void +ar9300_set_11n_aggr_first(struct ath_hal *ah, void *ds, u_int aggr_len) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + ads->ds_ctl12 |= (AR_is_aggr | AR_more_aggr); + + ads->ds_ctl17 &= ~AR_aggr_len; + ads->ds_ctl17 |= SM(aggr_len, AR_aggr_len); +} + +void +ar9300_set_11n_aggr_middle(struct ath_hal *ah, void *ds, u_int num_delims) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + unsigned int ctl17; + + ads->ds_ctl12 |= (AR_is_aggr | AR_more_aggr); + + /* + * We use a stack variable to manipulate ctl6 to reduce uncached + * read modify, modfiy, write. + */ + ctl17 = ads->ds_ctl17; + ctl17 &= ~AR_pad_delim; + ctl17 |= SM(num_delims, AR_pad_delim); + ads->ds_ctl17 = ctl17; +} + +void +ar9300_set_11n_aggr_last(struct ath_hal *ah, void *ds) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + ads->ds_ctl12 |= AR_is_aggr; + ads->ds_ctl12 &= ~AR_more_aggr; + ads->ds_ctl17 &= ~AR_pad_delim; +} + +void +ar9300_clr_11n_aggr(struct ath_hal *ah, void *ds) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + ads->ds_ctl12 &= (~AR_is_aggr & ~AR_more_aggr); +} + +void +ar9300_set_11n_burst_duration(struct ath_hal *ah, void *ds, + u_int burst_duration) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + ads->ds_ctl13 &= ~AR_burst_dur; + ads->ds_ctl13 |= SM(burst_duration, AR_burst_dur); +} + +void +ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + ads->ds_ctl12 |= AR_more_rifs | AR_no_ack; +} + +void +ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + ads->ds_ctl12 &= (~AR_more_aggr & ~AR_more_rifs); +} + +void +ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + ads->ds_ctl12 &= (~AR_more_rifs & ~AR_no_ack); +} + +void +ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + ads->ds_ctl12 |= AR_no_ack; + ads->ds_ctl12 &= ~AR_more_rifs; +} + +void +ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, void *ds, + u_int vmf) +{ + struct ar9300_txc *ads = AR9300TXC(ds); + + if (vmf) { + ads->ds_ctl11 |= AR_virt_more_frag; + } else { + ads->ds_ctl11 &= ~AR_virt_more_frag; + } +} + +void +ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info) +{ + desc_info->txctl_numwords = TXCTL_NUMWORDS(ah); + desc_info->txctl_offset = TXCTL_OFFSET(ah); + desc_info->txstatus_numwords = TXSTATUS_NUMWORDS(ah); + desc_info->txstatus_offset = TXSTATUS_OFFSET(ah); + + desc_info->rxctl_numwords = RXCTL_NUMWORDS(ah); + desc_info->rxctl_offset = RXCTL_OFFSET(ah); + desc_info->rxstatus_numwords = RXSTATUS_NUMWORDS(ah); + desc_info->rxstatus_offset = RXSTATUS_OFFSET(ah); +} + +#endif /* AH_SUPPORT_AR9300 */ diff --git a/hal/ar9300/ar9300desc.h b/hal/ar9300/ar9300desc.h new file mode 100644 index 000000000000..b3d27adafa2a --- /dev/null +++ b/hal/ar9300/ar9300desc.h @@ -0,0 +1,591 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + /* Contains descriptor definitions for Osprey */ + + +#ifndef _ATH_AR9300_DESC_H_ +#define _ATH_AR9300_DESC_H_ + + +/* Osprey Status Descriptor. */ +struct ar9300_txs { + u_int32_t ds_info; + u_int32_t status1; + u_int32_t status2; + u_int32_t status3; + u_int32_t status4; + u_int32_t status5; + u_int32_t status6; + u_int32_t status7; + u_int32_t status8; +}; + +struct ar9300_rxs { + u_int32_t ds_info; + u_int32_t status1; + u_int32_t status2; + u_int32_t status3; + u_int32_t status4; + u_int32_t status5; + u_int32_t status6; + u_int32_t status7; + u_int32_t status8; + u_int32_t status9; + u_int32_t status10; + u_int32_t status11; +}; + +/* Transmit Control Descriptor */ +struct ar9300_txc { + u_int32_t ds_info; /* descriptor information */ + u_int32_t ds_link; /* link pointer */ + u_int32_t ds_data0; /* data pointer to 1st buffer */ + u_int32_t ds_ctl3; /* DMA control 3 */ + u_int32_t ds_data1; /* data pointer to 2nd buffer */ + u_int32_t ds_ctl5; /* DMA control 5 */ + u_int32_t ds_data2; /* data pointer to 3rd buffer */ + u_int32_t ds_ctl7; /* DMA control 7 */ + u_int32_t ds_data3; /* data pointer to 4th buffer */ + u_int32_t ds_ctl9; /* DMA control 9 */ + u_int32_t ds_ctl10; /* DMA control 10 */ + u_int32_t ds_ctl11; /* DMA control 11 */ + u_int32_t ds_ctl12; /* DMA control 12 */ + u_int32_t ds_ctl13; /* DMA control 13 */ + u_int32_t ds_ctl14; /* DMA control 14 */ + u_int32_t ds_ctl15; /* DMA control 15 */ + u_int32_t ds_ctl16; /* DMA control 16 */ + u_int32_t ds_ctl17; /* DMA control 17 */ + u_int32_t ds_ctl18; /* DMA control 18 */ + u_int32_t ds_ctl19; /* DMA control 19 */ + u_int32_t ds_ctl20; /* DMA control 20 */ + u_int32_t ds_ctl21; /* DMA control 21 */ + u_int32_t ds_ctl22; /* DMA control 22 */ + u_int32_t ds_pad[9]; /* pad to cache line (128 bytes/32 dwords) */ +}; + + +#define AR9300RXS(_rxs) ((struct ar9300_rxs *)(_rxs)) +#define AR9300TXS(_txs) ((struct ar9300_txs *)(_txs)) +#define AR9300TXC(_ds) ((struct ar9300_txc *)(_ds)) + +#define AR9300TXC_CONST(_ds) ((const struct ar9300_txc *)(_ds)) + + +/* ds_info */ +#define AR_desc_len 0x000000ff +#define AR_rx_priority 0x00000100 +#define AR_tx_qcu_num 0x00000f00 +#define AR_tx_qcu_num_S 8 +#define AR_ctrl_stat 0x00004000 +#define AR_ctrl_stat_S 14 +#define AR_tx_rx_desc 0x00008000 +#define AR_tx_rx_desc_S 15 +#define AR_desc_id 0xffff0000 +#define AR_desc_id_S 16 + +/*********** + * TX Desc * + ***********/ + +/* ds_ctl3 */ +/* ds_ctl5 */ +/* ds_ctl7 */ +/* ds_ctl9 */ +#define AR_buf_len 0x0fff0000 +#define AR_buf_len_S 16 + +/* ds_ctl10 */ +#define AR_tx_desc_id 0xffff0000 +#define AR_tx_desc_id_S 16 +#define AR_tx_ptr_chk_sum 0x0000ffff + +/* ds_ctl11 */ +#define AR_frame_len 0x00000fff +#define AR_virt_more_frag 0x00001000 +#define AR_tx_ctl_rsvd00 0x00002000 +#define AR_low_rx_chain 0x00004000 +#define AR_tx_clear_retry 0x00008000 +#define AR_xmit_power0 0x003f0000 +#define AR_xmit_power0_S 16 +#define AR_rts_enable 0x00400000 +#define AR_veol 0x00800000 +#define AR_clr_dest_mask 0x01000000 +#define AR_tx_bf0 0x02000000 +#define AR_tx_bf1 0x04000000 +#define AR_tx_bf2 0x08000000 +#define AR_tx_bf3 0x10000000 +#define AR_TxBfSteered 0x1e000000 /* for tx_bf*/ +#define AR_tx_intr_req 0x20000000 +#define AR_dest_idx_valid 0x40000000 +#define AR_cts_enable 0x80000000 + +/* ds_ctl12 */ +#define AR_tx_ctl_rsvd02 0x000001ff +#define AR_paprd_chain_mask 0x00000e00 +#define AR_paprd_chain_mask_S 9 +#define AR_tx_more 0x00001000 +#define AR_dest_idx 0x000fe000 +#define AR_dest_idx_S 13 +#define AR_frame_type 0x00f00000 +#define AR_frame_type_S 20 +#define AR_no_ack 0x01000000 +#define AR_insert_ts 0x02000000 +#define AR_corrupt_fcs 0x04000000 +#define AR_ext_only 0x08000000 +#define AR_ext_and_ctl 0x10000000 +#define AR_more_aggr 0x20000000 +#define AR_is_aggr 0x40000000 +#define AR_more_rifs 0x80000000 +#define AR_loc_mode 0x00000100 /* Positioning bit in TX desc */ + +/* ds_ctl13 */ +#define AR_burst_dur 0x00007fff +#define AR_burst_dur_S 0 +#define AR_dur_update_ena 0x00008000 +#define AR_xmit_data_tries0 0x000f0000 +#define AR_xmit_data_tries0_S 16 +#define AR_xmit_data_tries1 0x00f00000 +#define AR_xmit_data_tries1_S 20 +#define AR_xmit_data_tries2 0x0f000000 +#define AR_xmit_data_tries2_S 24 +#define AR_xmit_data_tries3 0xf0000000 +#define AR_xmit_data_tries3_S 28 + +/* ds_ctl14 */ +#define AR_xmit_rate0 0x000000ff +#define AR_xmit_rate0_S 0 +#define AR_xmit_rate1 0x0000ff00 +#define AR_xmit_rate1_S 8 +#define AR_xmit_rate2 0x00ff0000 +#define AR_xmit_rate2_S 16 +#define AR_xmit_rate3 0xff000000 +#define AR_xmit_rate3_S 24 + +/* ds_ctl15 */ +#define AR_packet_dur0 0x00007fff +#define AR_packet_dur0_S 0 +#define AR_rts_cts_qual0 0x00008000 +#define AR_packet_dur1 0x7fff0000 +#define AR_packet_dur1_S 16 +#define AR_rts_cts_qual1 0x80000000 + +/* ds_ctl16 */ +#define AR_packet_dur2 0x00007fff +#define AR_packet_dur2_S 0 +#define AR_rts_cts_qual2 0x00008000 +#define AR_packet_dur3 0x7fff0000 +#define AR_packet_dur3_S 16 +#define AR_rts_cts_qual3 0x80000000 + +/* ds_ctl17 */ +#define AR_aggr_len 0x0000ffff +#define AR_aggr_len_S 0 +#define AR_tx_ctl_rsvd60 0x00030000 +#define AR_pad_delim 0x03fc0000 +#define AR_pad_delim_S 18 +#define AR_encr_type 0x1c000000 +#define AR_encr_type_S 26 +#define AR_tx_dc_ap_sta_sel 0x40000000 +#define AR_tx_ctl_rsvd61 0xc0000000 +#define AR_calibrating 0x40000000 +#define AR_ldpc 0x80000000 + +/* ds_ctl18 */ +#define AR_2040_0 0x00000001 +#define AR_gi0 0x00000002 +#define AR_chain_sel0 0x0000001c +#define AR_chain_sel0_S 2 +#define AR_2040_1 0x00000020 +#define AR_gi1 0x00000040 +#define AR_chain_sel1 0x00000380 +#define AR_chain_sel1_S 7 +#define AR_2040_2 0x00000400 +#define AR_gi2 0x00000800 +#define AR_chain_sel2 0x00007000 +#define AR_chain_sel2_S 12 +#define AR_2040_3 0x00008000 +#define AR_gi3 0x00010000 +#define AR_chain_sel3 0x000e0000 +#define AR_chain_sel3_S 17 +#define AR_rts_cts_rate 0x0ff00000 +#define AR_rts_cts_rate_S 20 +#define AR_stbc0 0x10000000 +#define AR_stbc1 0x20000000 +#define AR_stbc2 0x40000000 +#define AR_stbc3 0x80000000 + +/* ds_ctl19 */ +#define AR_tx_ant0 0x00ffffff +#define AR_tx_ant_sel0 0x80000000 +#define AR_RTS_HTC_TRQ 0x10000000 /* bit 28 for rts_htc_TRQ*/ /*for tx_bf*/ +#define AR_not_sounding 0x20000000 +#define AR_ness 0xc0000000 +#define AR_ness_S 30 + +/* ds_ctl20 */ +#define AR_tx_ant1 0x00ffffff +#define AR_xmit_power1 0x3f000000 +#define AR_xmit_power1_S 24 +#define AR_tx_ant_sel1 0x80000000 +#define AR_ness1 0xc0000000 +#define AR_ness1_S 30 + +/* ds_ctl21 */ +#define AR_tx_ant2 0x00ffffff +#define AR_xmit_power2 0x3f000000 +#define AR_xmit_power2_S 24 +#define AR_tx_ant_sel2 0x80000000 +#define AR_ness2 0xc0000000 +#define AR_ness2_S 30 + +/* ds_ctl22 */ +#define AR_tx_ant3 0x00ffffff +#define AR_xmit_power3 0x3f000000 +#define AR_xmit_power3_S 24 +#define AR_tx_ant_sel3 0x80000000 +#define AR_ness3 0xc0000000 +#define AR_ness3_S 30 + +/************* + * TX Status * + *************/ + +/* ds_status1 */ +#define AR_tx_status_rsvd 0x0000ffff + +/* ds_status2 */ +#define AR_tx_rssi_ant00 0x000000ff +#define AR_tx_rssi_ant00_S 0 +#define AR_tx_rssi_ant01 0x0000ff00 +#define AR_tx_rssi_ant01_S 8 +#define AR_tx_rssi_ant02 0x00ff0000 +#define AR_tx_rssi_ant02_S 16 +#define AR_tx_status_rsvd00 0x3f000000 +#define AR_tx_ba_status 0x40000000 +#define AR_tx_status_rsvd01 0x80000000 + +/* ds_status3 */ +#define AR_frm_xmit_ok 0x00000001 +#define AR_excessive_retries 0x00000002 +#define AR_fifounderrun 0x00000004 +#define AR_filtered 0x00000008 +#define AR_rts_fail_cnt 0x000000f0 +#define AR_rts_fail_cnt_S 4 +#define AR_data_fail_cnt 0x00000f00 +#define AR_data_fail_cnt_S 8 +#define AR_virt_retry_cnt 0x0000f000 +#define AR_virt_retry_cnt_S 12 +#define AR_tx_delim_underrun 0x00010000 +#define AR_tx_data_underrun 0x00020000 +#define AR_desc_cfg_err 0x00040000 +#define AR_tx_timer_expired 0x00080000 +#define AR_tx_status_rsvd10 0xfff00000 + +/* ds_status7 */ +#define AR_tx_rssi_ant10 0x000000ff +#define AR_tx_rssi_ant10_S 0 +#define AR_tx_rssi_ant11 0x0000ff00 +#define AR_tx_rssi_ant11_S 8 +#define AR_tx_rssi_ant12 0x00ff0000 +#define AR_tx_rssi_ant12_S 16 +#define AR_tx_rssi_combined 0xff000000 +#define AR_tx_rssi_combined_S 24 + +/* ds_status8 */ +#define AR_tx_done 0x00000001 +#define AR_seq_num 0x00001ffe +#define AR_seq_num_S 1 +#define AR_tx_status_rsvd80 0x0001e000 +#define AR_tx_op_exceeded 0x00020000 +#define AR_tx_status_rsvd81 0x001c0000 +#define AR_TXBFStatus 0x001c0000 +#define AR_TXBFStatus_S 18 +#define AR_tx_bf_bw_mismatch 0x00040000 +#define AR_tx_bf_stream_miss 0x00080000 +#define AR_final_tx_idx 0x00600000 +#define AR_final_tx_idx_S 21 +#define AR_tx_bf_dest_miss 0x00800000 +#define AR_tx_bf_expired 0x01000000 +#define AR_power_mgmt 0x02000000 +#define AR_tx_status_rsvd83 0x0c000000 +#define AR_tx_tid 0xf0000000 +#define AR_tx_tid_S 28 +#define AR_tx_fast_ts 0x08000000 /* 27th bit for locationing */ + + +/************* + * Rx Status * + *************/ + +/* ds_status1 */ +#define AR_rx_rssi_ant00 0x000000ff +#define AR_rx_rssi_ant00_S 0 +#define AR_rx_rssi_ant01 0x0000ff00 +#define AR_rx_rssi_ant01_S 8 +#define AR_rx_rssi_ant02 0x00ff0000 +#define AR_rx_rssi_ant02_S 16 +#define AR_rx_rate 0xff000000 +#define AR_rx_rate_S 24 + +/* ds_status2 */ +#define AR_data_len 0x00000fff +#define AR_rx_more 0x00001000 +#define AR_num_delim 0x003fc000 +#define AR_num_delim_S 14 +#define AR_hw_upload_data 0x00400000 +#define AR_hw_upload_data_S 22 +#define AR_rx_status_rsvd10 0xff800000 + + +/* ds_status4 */ +#define AR_gi 0x00000001 +#define AR_2040 0x00000002 +#define AR_parallel40 0x00000004 +#define AR_parallel40_S 2 +#define AR_rx_stbc 0x00000008 +#define AR_rx_not_sounding 0x00000010 +#define AR_rx_ness 0x00000060 +#define AR_rx_ness_S 5 +#define AR_hw_upload_data_valid 0x00000080 +#define AR_hw_upload_data_valid_S 7 +#define AR_rx_antenna 0xffffff00 +#define AR_rx_antenna_S 8 + +/* ds_status5 */ +#define AR_rx_rssi_ant10 0x000000ff +#define AR_rx_rssi_ant10_S 0 +#define AR_rx_rssi_ant11 0x0000ff00 +#define AR_rx_rssi_ant11_S 8 +#define AR_rx_rssi_ant12 0x00ff0000 +#define AR_rx_rssi_ant12_S 16 +#define AR_rx_rssi_combined 0xff000000 +#define AR_rx_rssi_combined_S 24 + +/* ds_status6 */ +#define AR_rx_evm0 status6 + +/* ds_status7 */ +#define AR_rx_evm1 status7 + +/* ds_status8 */ +#define AR_rx_evm2 status8 + +/* ds_status9 */ +#define AR_rx_evm3 status9 + +/* ds_status11 */ +#define AR_rx_done 0x00000001 +#define AR_rx_frame_ok 0x00000002 +#define AR_crc_err 0x00000004 +#define AR_decrypt_crc_err 0x00000008 +#define AR_phyerr 0x00000010 +#define AR_michael_err 0x00000020 +#define AR_pre_delim_crc_err 0x00000040 +#define AR_apsd_trig 0x00000080 +#define AR_rx_key_idx_valid 0x00000100 +#define AR_key_idx 0x0000fe00 +#define AR_key_idx_S 9 +#define AR_phy_err_code 0x0000ff00 +#define AR_phy_err_code_S 8 +#define AR_rx_more_aggr 0x00010000 +#define AR_rx_aggr 0x00020000 +#define AR_post_delim_crc_err 0x00040000 +#define AR_rx_status_rsvd71 0x01f80000 +#define AR_hw_upload_data_type 0x06000000 +#define AR_hw_upload_data_type_S 25 +#define AR_position_bit 0x08000000 /* positioning bit */ +#define AR_hi_rx_chain 0x10000000 +#define AR_rx_first_aggr 0x20000000 +#define AR_decrypt_busy_err 0x40000000 +#define AR_key_miss 0x80000000 + +#define TXCTL_OFFSET(ah) 11 +#define TXCTL_NUMWORDS(ah) 12 +#define TXSTATUS_OFFSET(ah) 2 +#define TXSTATUS_NUMWORDS(ah) 7 + +#define RXCTL_OFFSET(ah) 0 +#define RXCTL_NUMWORDS(ah) 0 +#define RXSTATUS_OFFSET(ah) 1 +#define RXSTATUS_NUMWORDS(ah) 11 + + +#define TXC_INFO(_qcu) (ATHEROS_VENDOR_ID << AR_desc_id_S) \ + | (1 << AR_tx_rx_desc_S) \ + | (1 << AR_ctrl_stat_S) \ + | (_qcu << AR_tx_qcu_num_S) \ + | (0x17) + +#define VALID_KEY_TYPES \ + ((1 << HAL_KEY_TYPE_CLEAR) | (1 << HAL_KEY_TYPE_WEP)|\ + (1 << HAL_KEY_TYPE_AES) | (1 << HAL_KEY_TYPE_TKIP)) +#define is_valid_key_type(_t) ((1 << (_t)) & VALID_KEY_TYPES) + +#define set_11n_tries(_series, _index) \ + (SM((_series)[_index].Tries, AR_xmit_data_tries##_index)) + +#define set_11n_rate(_series, _index) \ + (SM((_series)[_index].Rate, AR_xmit_rate##_index)) + +#define set_11n_pkt_dur_rts_cts(_series, _index) \ + (SM((_series)[_index].PktDuration, AR_packet_dur##_index) |\ + ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\ + AR_rts_cts_qual##_index : 0)) + +#define not_two_stream_rate(_rate) (((_rate) >0x8f) || ((_rate)<0x88)) + +#define set_11n_tx_bf_ldpc( _series) \ + ((( not_two_stream_rate((_series)[0].Rate) && (not_two_stream_rate((_series)[1].Rate)|| \ + (!(_series)[1].Tries)) && (not_two_stream_rate((_series)[2].Rate)||(!(_series)[2].Tries)) \ + && (not_two_stream_rate((_series)[3].Rate)||(!(_series)[3].Tries)))) \ + ? AR_ldpc : 0) + +#define set_11n_rate_flags(_series, _index) \ + ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \ + |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_gi##_index : 0) \ + |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_stbc##_index : 0) \ + |SM((_series)[_index].ch_sel, AR_chain_sel##_index) + +#define set_11n_tx_power(_index, _txpower) \ + SM(_txpower, AR_xmit_power##_index) + + +#define IS_3CHAIN_TX(_ah) (AH9300(_ah)->ah_tx_chainmask == 7) +/* + * Descriptor Access Functions + */ +/* XXX valid Tx rates will change for 3 stream support */ +#define VALID_PKT_TYPES \ + ((1<= AR9300_EEP_MINOR_VER_3) + +#define ar9300_get_ntxchains(_txchainmask) \ + (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) + +/* RF silent fields in \ */ +#define EEP_RFSILENT_ENABLED 0x0001 /* bit 0: enabled/disabled */ +#define EEP_RFSILENT_ENABLED_S 0 /* bit 0: enabled/disabled */ +#define EEP_RFSILENT_POLARITY 0x0002 /* bit 1: polarity */ +#define EEP_RFSILENT_POLARITY_S 1 /* bit 1: polarity */ +#define EEP_RFSILENT_GPIO_SEL 0x00fc /* bits 2..7: gpio PIN */ +#define EEP_RFSILENT_GPIO_SEL_S 2 /* bits 2..7: gpio PIN */ +#define AR9300_EEP_VER 0xE +#define AR9300_BCHAN_UNUSED 0xFF +#define AR9300_MAX_RATE_POWER 63 + +typedef enum { + CALDATA_AUTO=0, + CALDATA_EEPROM, + CALDATA_FLASH, + CALDATA_OTP +} CALDATA_TYPE; + +typedef enum { + EEP_NFTHRESH_5, + EEP_NFTHRESH_2, + EEP_MAC_MSW, + EEP_MAC_MID, + EEP_MAC_LSW, + EEP_REG_0, + EEP_REG_1, + EEP_OP_CAP, + EEP_OP_MODE, + EEP_RF_SILENT, + EEP_OB_5, + EEP_DB_5, + EEP_OB_2, + EEP_DB_2, + EEP_MINOR_REV, + EEP_TX_MASK, + EEP_RX_MASK, + EEP_FSTCLK_5G, + EEP_RXGAIN_TYPE, + EEP_OL_PWRCTRL, + EEP_TXGAIN_TYPE, + EEP_RC_CHAIN_MASK, + EEP_DAC_HPWR_5G, + EEP_FRAC_N_5G, + EEP_DEV_TYPE, + EEP_TEMPSENSE_SLOPE, + EEP_TEMPSENSE_SLOPE_PAL_ON, + EEP_PWR_TABLE_OFFSET, + EEP_DRIVE_STRENGTH, + EEP_INTERNAL_REGULATOR, + EEP_SWREG, + EEP_PAPRD_ENABLED, + EEP_ANTDIV_control, + EEP_CHAIN_MASK_REDUCE, +} EEPROM_PARAM; + +#define AR9300_RATES_OFDM_OFFSET 0 +#define AR9300_RATES_CCK_OFFSET 4 +#define AR9300_RATES_HT20_OFFSET 8 +#define AR9300_RATES_HT40_OFFSET 22 +typedef enum ar9300_Rates { + ALL_TARGET_LEGACY_6_24, + ALL_TARGET_LEGACY_36, + ALL_TARGET_LEGACY_48, + ALL_TARGET_LEGACY_54, + ALL_TARGET_LEGACY_1L_5L, + ALL_TARGET_LEGACY_5S, + ALL_TARGET_LEGACY_11L, + ALL_TARGET_LEGACY_11S, + ALL_TARGET_HT20_0_8_16, + ALL_TARGET_HT20_1_3_9_11_17_19, + ALL_TARGET_HT20_4, + ALL_TARGET_HT20_5, + ALL_TARGET_HT20_6, + ALL_TARGET_HT20_7, + ALL_TARGET_HT20_12, + ALL_TARGET_HT20_13, + ALL_TARGET_HT20_14, + ALL_TARGET_HT20_15, + ALL_TARGET_HT20_20, + ALL_TARGET_HT20_21, + ALL_TARGET_HT20_22, + ALL_TARGET_HT20_23, + ALL_TARGET_HT40_0_8_16, + ALL_TARGET_HT40_1_3_9_11_17_19, + ALL_TARGET_HT40_4, + ALL_TARGET_HT40_5, + ALL_TARGET_HT40_6, + ALL_TARGET_HT40_7, + ALL_TARGET_HT40_12, + ALL_TARGET_HT40_13, + ALL_TARGET_HT40_14, + ALL_TARGET_HT40_15, + ALL_TARGET_HT40_20, + ALL_TARGET_HT40_21, + ALL_TARGET_HT40_22, + ALL_TARGET_HT40_23, + ar9300_rate_size +} AR9300_RATES; + + +/************************************************************************** + * fbin2freq + * + * Get channel value from binary representation held in eeprom + * RETURNS: the frequency in MHz + */ +static inline u_int16_t +fbin2freq(u_int8_t fbin, HAL_BOOL is_2ghz) +{ + /* + * Reserved value 0xFF provides an empty definition both as + * an fbin and as a frequency - do not convert + */ + if (fbin == AR9300_BCHAN_UNUSED) + { + return fbin; + } + + return (u_int16_t)((is_2ghz) ? (2300 + fbin) : (4800 + 5 * fbin)); +} + +extern int CompressionHeaderUnpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); +extern void Ar9300EepromFormatConvert(ar9300_eeprom_t *mptr); +extern HAL_BOOL ar9300_eeprom_restore(struct ath_hal *ah); +extern int ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, int /*msize*/); +extern int ar9300_eeprom_base_address(struct ath_hal *ah); +extern int ar9300_eeprom_volatile(struct ath_hal *ah); +extern int ar9300_eeprom_low_limit(struct ath_hal *ah); +extern u_int16_t ar9300_compression_checksum(u_int8_t *data, int dsize); +extern int ar9300_compression_header_unpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); + +extern u_int16_t ar9300_eeprom_struct_size(void); +extern ar9300_eeprom_t *ar9300EepromStructInit(int default_index); +extern ar9300_eeprom_t *ar9300EepromStructGet(void); +extern ar9300_eeprom_t *ar9300_eeprom_struct_default(int default_index); +extern ar9300_eeprom_t *ar9300_eeprom_struct_default_find_by_id(int ver); +extern int ar9300_eeprom_struct_default_many(void); +extern int ar9300EepromUpdateCalPier(int pierIdx, int freq, int chain, + int pwrCorrection, int volt_meas, int temp_meas); +extern int ar9300_power_control_override(struct ath_hal *ah, int frequency, int *correction, int *voltage, int *temperature); + +extern void ar9300EepromDisplayCalData(int for2GHz); +extern void ar9300EepromDisplayAll(void); +extern void ar9300_set_target_power_from_eeprom(struct ath_hal *ah, u_int16_t freq, + u_int8_t *target_power_val_t2); +extern HAL_BOOL ar9300_eeprom_set_power_per_rate_table(struct ath_hal *ah, + ar9300_eeprom_t *p_eep_data, + HAL_CHANNEL_INTERNAL *chan, + u_int8_t *p_pwr_array, + u_int16_t cfg_ctl, + u_int16_t antenna_reduction, + u_int16_t twice_max_regulatory_power, + u_int16_t power_limit, + u_int8_t chainmask); +extern int ar9300_transmit_power_reg_write(struct ath_hal *ah, u_int8_t *p_pwr_array); +extern int ar9300_compression_header_unpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); + +extern u_int8_t ar9300_eeprom_get_legacy_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); +extern u_int8_t ar9300_eeprom_get_ht20_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); +extern u_int8_t ar9300_eeprom_get_ht40_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); +extern u_int8_t ar9300_eeprom_get_cck_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq); +extern HAL_BOOL ar9300_internal_regulator_apply(struct ath_hal *ah); +extern HAL_BOOL ar9300_drive_strength_apply(struct ath_hal *ah); +extern HAL_BOOL ar9300_attenuation_apply(struct ath_hal *ah, u_int16_t channel); +extern int32_t ar9300_thermometer_get(struct ath_hal *ah); +extern HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah); +extern HAL_BOOL ar9300_xpa_timing_control_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); +extern HAL_BOOL ar9300_x_lNA_bias_strength_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); + +extern int32_t ar9300MacAdressGet(u_int8_t *mac); +extern int32_t ar9300CustomerDataGet(u_int8_t *data, int32_t len); +extern int32_t ar9300ReconfigDriveStrengthGet(void); +extern int32_t ar9300EnableTempCompensationGet(void); +extern int32_t ar9300EnableVoltCompensationGet(void); +extern int32_t ar9300FastClockEnableGet(void); +extern int32_t ar9300EnableDoublingGet(void); + +extern u_int16_t *ar9300_regulatory_domain_get(struct ath_hal *ah); +extern int32_t ar9300_eeprom_write_enable_gpio_get(struct ath_hal *ah); +extern int32_t ar9300_wlan_led_gpio_get(struct ath_hal *ah); +extern int32_t ar9300_wlan_disable_gpio_get(struct ath_hal *ah); +extern int32_t ar9300_rx_band_select_gpio_get(struct ath_hal *ah); +extern int32_t ar9300_rx_gain_index_get(struct ath_hal *ah); +extern int32_t ar9300_tx_gain_index_get(struct ath_hal *ah); +extern int32_t ar9300_xpa_bias_level_get(struct ath_hal *ah, HAL_BOOL is_2ghz); +extern HAL_BOOL ar9300_xpa_bias_level_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); +extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz); +extern u_int32_t ar9300_ant_ctrl_common2_get(struct ath_hal *ah, HAL_BOOL is_2ghz); +extern u_int16_t ar9300_ant_ctrl_chain_get(struct ath_hal *ah, int chain, HAL_BOOL is_2ghz); +extern HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); +/* since valid noise floor values are negative, returns 1 on error */ +extern int32_t ar9300_noise_floor_cal_or_power_get( + struct ath_hal *ah, int32_t frequency, int32_t ichain, HAL_BOOL use_cal); +#define ar9300NoiseFloorGet(ah, frequency, ichain) \ + ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 1/*use_cal*/) +#define ar9300NoiseFloorPowerGet(ah, frequency, ichain) \ + ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 0/*use_cal*/) +extern void ar9300_eeprom_template_preference(int32_t value); +extern int32_t ar9300_eeprom_template_install(struct ath_hal *ah, int32_t value); +extern void ar9300_calibration_data_set(struct ath_hal *ah, int32_t source); +extern int32_t ar9300_calibration_data_get(struct ath_hal *ah); +extern int32_t ar9300_calibration_data_address_get(struct ath_hal *ah); +extern void ar9300_calibration_data_address_set(struct ath_hal *ah, int32_t source); +extern HAL_BOOL ar9300_calibration_data_read_flash(struct ath_hal *ah, long address, u_int8_t *buffer, int many); +extern HAL_BOOL ar9300_calibration_data_read_eeprom(struct ath_hal *ah, long address, u_int8_t *buffer, int many); +extern HAL_BOOL ar9300_calibration_data_read_otp(struct ath_hal *ah, long address, u_int8_t *buffer, int many, HAL_BOOL is_wifi); +extern HAL_BOOL ar9300_calibration_data_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); +extern int32_t ar9300_eeprom_size(struct ath_hal *ah); +extern int32_t ar9300_otp_size(struct ath_hal *ah); +extern HAL_BOOL ar9300_calibration_data_read_array(struct ath_hal *ah, int address, u_int8_t *buffer, int many); + + + +#if defined(WIN32) || defined(WIN64) +#pragma pack (pop, ar9300) +#endif + +#endif /* _ATH_AR9300_EEP_H_ */ diff --git a/hal/ar9300/ar9300paprd.h b/hal/ar9300/ar9300paprd.h new file mode 100644 index 000000000000..df97fd3c645f --- /dev/null +++ b/hal/ar9300/ar9300paprd.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* + + * Copyright (c) 2002-2010 Atheros Communications, Inc. + * All Rights Reserved. + * + * Copyright (c) 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Qualcomm Atheros Confidential and Proprietary. + * + + */ + + + +#ifndef __AR9300PAPRD_H__ + +#define __AR9300PAPRD_H__ + + + +#include + +#include "ar9300.h" + +#include "ar9300phy.h" + +#define AH_PAPRD_AM_PM_MASK 0x1ffffff +#define AH_PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 +extern int ar9300_paprd_init_table(struct ath_hal *ah, HAL_CHANNEL *chan); +extern HAL_STATUS ar9300_paprd_setup_gain_table(struct ath_hal *ah, int chain_num); +extern HAL_STATUS ar9300_paprd_create_curve(struct ath_hal *ah, HAL_CHANNEL *chan, int chain_num); +extern int ar9300_paprd_is_done(struct ath_hal *ah); +extern void ar9300_enable_paprd(struct ath_hal *ah, HAL_BOOL enable_flag, HAL_CHANNEL * chan); +extern void ar9300_swizzle_paprd_entries(struct ath_hal *ah, unsigned int txchain); +extern void ar9300_populate_paprd_single_table(struct ath_hal *ah, HAL_CHANNEL *chan, int chain_num); +extern void ar9300_paprd_dec_tx_pwr(struct ath_hal *ah); +extern int ar9300_paprd_thermal_send(struct ath_hal *ah); +#endif + diff --git a/hal/ar9300/ar9300phy.h b/hal/ar9300/ar9300phy.h new file mode 100644 index 000000000000..e372e746e7d6 --- /dev/null +++ b/hal/ar9300/ar9300phy.h @@ -0,0 +1,1955 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* + * Copyright (c) 2002-2005 Atheros Communications, Inc. + * All Rights Reserved. + * + * Copyright (c) 2011 Qualcomm Atheros, Inc. + * All Rights Reserved. + * Qualcomm Atheros Confidential and Proprietary. + * + */ + +#ifndef _ATH_AR9300PHY_H_ +#define _ATH_AR9300PHY_H_ + +#include "osprey_reg_map.h" + +/* + * BB PHY register map + */ +#define AR_PHY_BASE offsetof(struct bb_reg_map, bb_chn_reg_map) /* base address of phy regs */ +#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) + +/* + * Channel Register Map + */ +#define AR_CHAN_BASE offsetof(struct bb_reg_map, bb_chn_reg_map) +#define AR_CHAN_OFFSET(_x) (AR_CHAN_BASE + offsetof(struct chn_reg_map, _x)) + +#define AR_PHY_TIMING1 AR_CHAN_OFFSET(BB_timing_controls_1) +#define AR_PHY_TIMING2 AR_CHAN_OFFSET(BB_timing_controls_2) +#define AR_PHY_TIMING3 AR_CHAN_OFFSET(BB_timing_controls_3) +#define AR_PHY_TIMING4 AR_CHAN_OFFSET(BB_timing_control_4) +#define AR_PHY_TIMING5 AR_CHAN_OFFSET(BB_timing_control_5) +#define AR_PHY_TIMING6 AR_CHAN_OFFSET(BB_timing_control_6) +#define AR_PHY_TIMING11 AR_CHAN_OFFSET(BB_timing_control_11) +#define AR_PHY_SPUR_REG AR_CHAN_OFFSET(BB_spur_mask_controls) +#define AR_PHY_RX_IQCAL_CORR_B0 AR_CHAN_OFFSET(BB_rx_iq_corr_b0) +#define AR_PHY_TX_IQCAL_CONTROL_3 AR_CHAN_OFFSET(BB_txiqcal_control_3) + +/* BB_timing_control_11 */ +#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 +#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 + +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 + +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30 + +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31 + +/* BB_spur_mask_controls */ +#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000 +#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26 + +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 +#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100 +#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 + +/* BB_rx_iq_corr_b0 */ +#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000 +#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29 +/* BB_txiqcal_control_3 */ +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000 +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31 + +#if 0 +/* enable vit puncture per rate, 8 bits, lsb is low rate */ +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ +#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */ +#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 +#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 +#endif + +#define AR_PHY_FIND_SIG_LOW AR_CHAN_OFFSET(BB_find_signal_low) +#define AR_PHY_SFCORR AR_CHAN_OFFSET(BB_sfcorr) +#if 0 +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F +#define AR_PHY_SFCORR_M2COUNT_THR_S 0 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 +#define AR_PHY_SFCORR_M1_THRESH_S 17 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000 +#define AR_PHY_SFCORR_M2_THRESH_S 24 +#endif + +#define AR_PHY_SFCORR_LOW AR_CHAN_OFFSET(BB_self_corr_low) +#define AR_PHY_SFCORR_EXT AR_CHAN_OFFSET(BB_ext_chan_scorr_thr) +#if 0 +#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F // [06:00] +#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 +#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 // [13:07] +#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 // [20:14] +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 // [27:21] +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 +#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 +#endif + +#define AR_PHY_EXT_CCA AR_CHAN_OFFSET(BB_ext_chan_pwr_thr_2_b0) +#define AR_PHY_RADAR_0 AR_CHAN_OFFSET(BB_radar_detection) /* radar detection settings */ +#define AR_PHY_RADAR_1 AR_CHAN_OFFSET(BB_radar_detection_2) +#define AR_PHY_RADAR_1_CF_BIN_THRESH 0x07000000 +#define AR_PHY_RADAR_1_CF_BIN_THRESH_S 24 +#define AR_PHY_RADAR_EXT AR_CHAN_OFFSET(BB_extension_radar) /* extension channel radar settings */ +#define AR_PHY_MULTICHAIN_CTRL AR_CHAN_OFFSET(BB_multichain_control) +#define AR_PHY_PERCHAIN_CSD AR_CHAN_OFFSET(BB_per_chain_csd) + +#define AR_PHY_TX_PHASE_RAMP_0 AR_CHAN_OFFSET(BB_tx_phase_ramp_b0) +#define AR_PHY_ADC_GAIN_DC_CORR_0 AR_CHAN_OFFSET(BB_adc_gain_dc_corr_b0) +#define AR_PHY_IQ_ADC_MEAS_0_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_0_b0) +#define AR_PHY_IQ_ADC_MEAS_1_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_1_b0) +#define AR_PHY_IQ_ADC_MEAS_2_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_2_b0) +#define AR_PHY_IQ_ADC_MEAS_3_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_3_b0) + +#define AR_PHY_TX_IQ_CORR_0 AR_CHAN_OFFSET(BB_tx_iq_corr_b0) +#define AR_PHY_TX_CRC AR_CHAN_OFFSET(BB_tx_crc) +#define AR_PHY_TST_DAC_CONST AR_CHAN_OFFSET(BB_tstdac_constant) +#define AR_PHY_SPUR_REPORT_0 AR_CHAN_OFFSET(BB_spur_report_b0) +#define AR_PHY_CHAN_INFO_TAB_0 AR_CHAN_OFFSET(BB_chan_info_chan_tab_b0) + + +/* + * Channel Field Definitions + */ +/* BB_timing_controls_2 */ +#define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000 +#define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff +#define AR_PHY_TIMING2_HT_Fine_Timing_EN 0x80000000 +#define AR_PHY_TIMING2_DC_OFFSET 0x08000000 +#define AR_PHY_TIMING2_DC_OFFSET_S 27 + +/* BB_timing_controls_3 */ +#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 +#define AR_PHY_TIMING3_DSC_MAN_S 17 +#define AR_PHY_TIMING3_DSC_EXP 0x0001E000 +#define AR_PHY_TIMING3_DSC_EXP_S 13 +/* BB_timing_control_4 */ +#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */ +#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ +#define AR_PHY_TIMING4_DO_CAL 0x10000 /* perform calibration */ +#define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000 +#define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28 +#define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000 +#define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29 + +#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000 +#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30 +#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000 +#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31 + +/* BB_adc_gain_dc_corr_b0 */ +#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 +#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 +/* BB_self_corr_low */ +#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 +/* BB_sfcorr */ +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F +#define AR_PHY_SFCORR_M2COUNT_THR_S 0 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 +#define AR_PHY_SFCORR_M1_THRESH_S 17 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000 +#define AR_PHY_SFCORR_M2_THRESH_S 24 +/* BB_ext_chan_scorr_thr */ +#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F // [06:00] +#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 +#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 // [13:07] +#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 // [20:14] +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 // [27:21] +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 +#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000 +#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28 +#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 +/* BB_ext_chan_pwr_thr_2_b0 */ +#define AR_PHY_EXT_CCA_THRESH62 0x007F0000 +#define AR_PHY_EXT_CCA_THRESH62_S 16 +#define AR_PHY_EXT_MINCCA_PWR 0x01FF0000 +#define AR_PHY_EXT_MINCCA_PWR_S 16 +#define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L // [15:09] +#define AR_PHY_EXT_CYCPWR_THR1_S 9 +/* BB_timing_control_5 */ +#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE +#define AR_PHY_TIMING5_CYCPWR_THR1_S 1 +#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001 +#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0 +#define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000 +#define AR_PHY_TIMING5_CYCPWR_THR1A_S 16 +#define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16) +#define AR_PHY_TIMING5_RSSI_THR1A_S 16 +#define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15) +/* BB_radar_detection) */ +#define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */ +#define AR_PHY_RADAR_0_FFT_ENA 0x80000000 /* Enable FFT data */ +#define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */ +#define AR_PHY_RADAR_0_INBAND_S 1 +#define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */ +#define AR_PHY_RADAR_0_PRSSI_S 6 +#define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */ +#define AR_PHY_RADAR_0_HEIGHT_S 12 +#define AR_PHY_RADAR_0_RRSSI 0x00FC0000 /* Radar rssi threshold */ +#define AR_PHY_RADAR_0_RRSSI_S 18 +#define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */ +#define AR_PHY_RADAR_0_FIRPWR_S 24 +/* BB_radar_detection_2 */ +#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 /* enable to check radar relative power */ +#define AR_PHY_RADAR_1_USE_FIR128 0x00400000 /* enable to use the average inband power + * measured over 128 cycles + */ +#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 /* relative pwr thresh */ +#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 +#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 /* Enable to block radar check if weak OFDM + * sig or pkt is immediately after tx to rx + * transition + */ +#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 /* Enable to use max rssi */ +#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 /* Enable to use pulse relative step check */ +#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 /* Pulse relative step threshold */ +#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 +#define AR_PHY_RADAR_1_MAXLEN 0x000000FF /* Max length of radar pulse */ +#define AR_PHY_RADAR_1_MAXLEN_S 0 +/* BB_extension_radar */ +#define AR_PHY_RADAR_EXT_ENA 0x00004000 /* Enable extension channel radar detection */ +#define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000 +#define AR_PHY_RADAR_DC_PWR_THRESH_S 15 +#define AR_PHY_RADAR_LB_DC_CAP 0x7f800000 +#define AR_PHY_RADAR_LB_DC_CAP_S 23 +/* per chain csd*/ +#define AR_PHY_PERCHAIN_CSD_chn1_2chains 0x0000001f +#define AR_PHY_PERCHAIN_CSD_chn1_2chains_S 0 +#define AR_PHY_PERCHAIN_CSD_chn1_3chains 0x000003e0 +#define AR_PHY_PERCHAIN_CSD_chn1_3chains_S 5 +#define AR_PHY_PERCHAIN_CSD_chn2_3chains 0x00007c00 +#define AR_PHY_PERCHAIN_CSD_chn2_3chains_S 10 +/* BB_find_signal_low */ +#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6) +#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6 +#define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12) +#define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12 +#define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19 +#define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f +#define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0 +#define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5 +/* BB_chan_info_chan_tab_b* */ +#define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008 +#define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3 +/* BB_rx_iq_corr_b* */ +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F /* Mask for kcos_theta-1 for q correction */ +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */ +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80 /* Mask for sin_theta for i correction */ +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7 /* Shift for sin_theta for i correction */ +#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000 /* enable IQ correction */ +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22 + +/* + * MRC Register Map + */ +#define AR_MRC_BASE offsetof(struct bb_reg_map, bb_mrc_reg_map) +#define AR_MRC_OFFSET(_x) (AR_MRC_BASE + offsetof(struct mrc_reg_map, _x)) + +#define AR_PHY_TIMING_3A AR_MRC_OFFSET(BB_timing_control_3a) +#define AR_PHY_LDPC_CNTL1 AR_MRC_OFFSET(BB_ldpc_cntl1) +#define AR_PHY_LDPC_CNTL2 AR_MRC_OFFSET(BB_ldpc_cntl2) +#define AR_PHY_PILOT_SPUR_MASK AR_MRC_OFFSET(BB_pilot_spur_mask) +#define AR_PHY_CHAN_SPUR_MASK AR_MRC_OFFSET(BB_chan_spur_mask) +#define AR_PHY_SGI_DELTA AR_MRC_OFFSET(BB_short_gi_delta_slope) +#define AR_PHY_ML_CNTL_1 AR_MRC_OFFSET(BB_ml_cntl1) +#define AR_PHY_ML_CNTL_2 AR_MRC_OFFSET(BB_ml_cntl2) +#define AR_PHY_TST_ADC AR_MRC_OFFSET(BB_tstadc) + +/* BB_pilot_spur_mask fields */ +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0 + +/* BB_chan_spur_mask fields */ +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0 + +/* + * MRC Feild Definitions + */ +#define AR_PHY_SGI_DSC_MAN 0x0007FFF0 +#define AR_PHY_SGI_DSC_MAN_S 4 +#define AR_PHY_SGI_DSC_EXP 0x0000000F +#define AR_PHY_SGI_DSC_EXP_S 0 +/* + * BBB Register Map + */ +#define AR_BBB_BASE offsetof(struct bb_reg_map, bb_bbb_reg_map) +#define AR_BBB_OFFSET(_x) (AR_BBB_BASE + offsetof(struct bbb_reg_map, _x)) + +#define AR_PHY_BBB_RX_CTRL(_i) AR_BBB_OFFSET(BB_bbb_rx_ctrl_##_i) + +/* + * AGC Register Map + */ +#define AR_AGC_BASE offsetof(struct bb_reg_map, bb_agc_reg_map) +#define AR_AGC_OFFSET(_x) (AR_AGC_BASE + offsetof(struct agc_reg_map, _x)) + +#define AR_PHY_SETTLING AR_AGC_OFFSET(BB_settling_time) +#define AR_PHY_FORCEMAX_GAINS_0 AR_AGC_OFFSET(BB_gain_force_max_gains_b0) +#define AR_PHY_GAINS_MINOFF0 AR_AGC_OFFSET(BB_gains_min_offsets_b0) +#define AR_PHY_DESIRED_SZ AR_AGC_OFFSET(BB_desired_sigsize) +#define AR_PHY_FIND_SIG AR_AGC_OFFSET(BB_find_signal) +#define AR_PHY_AGC AR_AGC_OFFSET(BB_agc) +#define AR_PHY_EXT_ATTEN_CTL_0 AR_AGC_OFFSET(BB_ext_atten_switch_ctl_b0) +#define AR_PHY_CCA_0 AR_AGC_OFFSET(BB_cca_b0) +#define AR_PHY_EXT_CCA0 AR_AGC_OFFSET(BB_cca_ctrl_2_b0) +#define AR_PHY_RESTART AR_AGC_OFFSET(BB_restart) +#define AR_PHY_MC_GAIN_CTRL AR_AGC_OFFSET(BB_multichain_gain_ctrl) +#define AR_PHY_EXTCHN_PWRTHR1 AR_AGC_OFFSET(BB_ext_chan_pwr_thr_1) +#define AR_PHY_EXT_CHN_WIN AR_AGC_OFFSET(BB_ext_chan_detect_win) +#define AR_PHY_20_40_DET_THR AR_AGC_OFFSET(BB_pwr_thr_20_40_det) +#define AR_PHY_RIFS_SRCH AR_AGC_OFFSET(BB_rifs_srch) +#define AR_PHY_PEAK_DET_CTRL_1 AR_AGC_OFFSET(BB_peak_det_ctrl_1) + +#define AR_PHY_PEAK_DET_ENABLE 0x00000002 + +#define AR_PHY_PEAK_DET_CTRL_2 AR_AGC_OFFSET(BB_peak_det_ctrl_2) +#define AR_PHY_RX_GAIN_BOUNDS_1 AR_AGC_OFFSET(BB_rx_gain_bounds_1) +#define AR_PHY_RX_GAIN_BOUNDS_2 AR_AGC_OFFSET(BB_rx_gain_bounds_2) +#define AR_PHY_RSSI_0 AR_AGC_OFFSET(BB_rssi_b0) +#define AR_PHY_SPUR_CCK_REP0 AR_AGC_OFFSET(BB_spur_est_cck_report_b0) +#define AR_PHY_CCK_DETECT AR_AGC_OFFSET(BB_bbb_sig_detect) +#define AR_PHY_DAG_CTRLCCK AR_AGC_OFFSET(BB_bbb_dagc_ctrl) +#define AR_PHY_IQCORR_CTRL_CCK AR_AGC_OFFSET(BB_iqcorr_ctrl_cck) +#define AR_PHY_DIG_DC_STATUS_I_B0 AR_AGC_OFFSET(BB_agc_dig_dc_status_i_b0) +#define AR_PHY_DIG_DC_STATUS_Q_B0 AR_AGC_OFFSET(BB_agc_dig_dc_status_q_b0) +#define AR_PHY_DIG_DC_C1_RES 0x000001ff +#define AR_PHY_DIG_DC_C1_RES_S 0 +#define AR_PHY_DIG_DC_C2_RES 0x0003fe00 +#define AR_PHY_DIG_DC_C2_RES_S 9 +#define AR_PHY_DIG_DC_C3_RES 0x07fc0000 +#define AR_PHY_DIG_DC_C3_RES_S 18 + +#define AR_PHY_CCK_SPUR_MIT AR_AGC_OFFSET(BB_cck_spur_mit) +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1 +#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000 +#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29 +#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001 +#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0 +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00 +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9 + +#define AR_PHY_MRC_CCK_CTRL AR_AGC_OFFSET(BB_mrc_cck_ctrl) +#define AR_PHY_MRC_CCK_ENABLE 0x00000001 +#define AR_PHY_MRC_CCK_ENABLE_S 0 +#define AR_PHY_MRC_CCK_MUX_REG 0x00000002 +#define AR_PHY_MRC_CCK_MUX_REG_S 1 + +#define AR_PHY_RX_OCGAIN AR_AGC_OFFSET(BB_rx_ocgain) + +#define AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ -110 +#define AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ -115 +#define AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ -125 +#define AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ -125 +#define AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ -95 +#define AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ -100 +#define AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ -105 + +#define AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ -127 +#define AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ -127 +#define AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ -127 +#define AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ -127 + +#define AR_PHY_BT_COEX_4 AR_AGC_OFFSET(BB_bt_coex_4) +#define AR_PHY_BT_COEX_5 AR_AGC_OFFSET(BB_bt_coex_5) + +/* + * Noise floor readings at least CW_INT_DELTA above the nominal NF + * indicate that CW interference is present. + */ +#define AR_PHY_CCA_CW_INT_DELTA 30 + +/* + * AGC Field Definitions + */ +/* BB_ext_atten_switch_ctl_b0 */ +#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000 +#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18 +#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00 +#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10 +#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F +#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0 +/* BB_gain_force_max_gains_b0 */ +#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 +#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 +#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 +#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 +/* BB_settling_time */ +#define AR_PHY_SETTLING_SWITCH 0x00003F80 +#define AR_PHY_SETTLING_SWITCH_S 7 +/* BB_desired_sigsize */ +#define AR_PHY_DESIRED_SZ_ADC 0x000000FF +#define AR_PHY_DESIRED_SZ_ADC_S 0 +#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 +#define AR_PHY_DESIRED_SZ_PGA_S 8 +#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 +#define AR_PHY_DESIRED_SZ_TOT_DES_S 20 +/* BB_cca_b0 */ +#define AR_PHY_MINCCA_PWR 0x1FF00000 +#define AR_PHY_MINCCA_PWR_S 20 +#define AR_PHY_CCA_THRESH62 0x0007F000 +#define AR_PHY_CCA_THRESH62_S 12 +#define AR9280_PHY_MINCCA_PWR 0x1FF00000 +#define AR9280_PHY_MINCCA_PWR_S 20 +#define AR9280_PHY_CCA_THRESH62 0x000FF000 +#define AR9280_PHY_CCA_THRESH62_S 12 +/* BB_cca_ctrl_2_b0 */ +#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF +#define AR_PHY_EXT_CCA0_THRESH62_S 0 +/* BB_bbb_sig_detect */ +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 // [12:6] settling time for antenna switch +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 + +/* BB_bbb_dagc_ctrl */ +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 + +/* BB_rifs_srch */ +#define AR_PHY_RIFS_INIT_DELAY 0x3ff0000 + +/*B_tpc_7*/ +#define AR_PHY_TPC_7_TX_GAIN_TABLE_MAX 0x3f +#define AR_PHY_TPC_7_TX_GAIN_TABLE_MAX_S (0) + +/* BB_agc */ +#define AR_PHY_AGC_QUICK_DROP_S (22) +#define AR_PHY_AGC_QUICK_DROP (0xf << AR_PHY_AGC_QUICK_DROP_S) +#define AR_PHY_AGC_COARSE_LOW 0x00007F80 +#define AR_PHY_AGC_COARSE_LOW_S 7 +#define AR_PHY_AGC_COARSE_HIGH 0x003F8000 +#define AR_PHY_AGC_COARSE_HIGH_S 15 +#define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F +#define AR_PHY_AGC_COARSE_PWR_CONST_S 0 +/* BB_find_signal */ +#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 +#define AR_PHY_FIND_SIG_FIRSTEP_S 12 +#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 +#define AR_PHY_FIND_SIG_FIRPWR_S 18 +#define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25 +#define AR_PHY_FIND_SIG_RELPWR (0x1f << 6) +#define AR_PHY_FIND_SIG_RELPWR_S 6 +#define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11 +#define AR_PHY_FIND_SIG_RELSTEP 0x1f +#define AR_PHY_FIND_SIG_RELSTEP_S 0 +#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5 +/* BB_restart */ +#define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */ +#define AR_PHY_RESTART_DIV_GC_S 18 +#define AR_PHY_RESTART_ENA 0x01 /* enable restart */ +#define AR_PHY_DC_RESTART_DIS 0x40000000 /* disable DC restart */ + +#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000 //Mask BIT[31:24] +#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24 +#define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000 //Mask BIT[23:16] +#define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16 + +#define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000 //Mask BIT[25:24] +#define AR_PHY_TPC_6_ERROR_EST_MODE_S 24 + +/* + * SM Register Map + */ +#define AR_SM_BASE offsetof(struct bb_reg_map, bb_sm_reg_map) +#define AR_SM_OFFSET(_x) (AR_SM_BASE + offsetof(struct sm_reg_map, _x)) + +#define AR_PHY_D2_CHIP_ID AR_SM_OFFSET(BB_D2_chip_id) +#define AR_PHY_GEN_CTRL AR_SM_OFFSET(BB_gen_controls) +#define AR_PHY_MODE AR_SM_OFFSET(BB_modes_select) +#define AR_PHY_ACTIVE AR_SM_OFFSET(BB_active) +#define AR_PHY_SPUR_MASK_A AR_SM_OFFSET(BB_vit_spur_mask_A) +#define AR_PHY_SPUR_MASK_B AR_SM_OFFSET(BB_vit_spur_mask_B) +#define AR_PHY_SPECTRAL_SCAN AR_SM_OFFSET(BB_spectral_scan) +#define AR_PHY_RADAR_BW_FILTER AR_SM_OFFSET(BB_radar_bw_filter) +#define AR_PHY_SEARCH_START_DELAY AR_SM_OFFSET(BB_search_start_delay) +#define AR_PHY_MAX_RX_LEN AR_SM_OFFSET(BB_max_rx_length) +#define AR_PHY_FRAME_CTL AR_SM_OFFSET(BB_frame_control) +#define AR_PHY_RFBUS_REQ AR_SM_OFFSET(BB_rfbus_request) +#define AR_PHY_RFBUS_GRANT AR_SM_OFFSET(BB_rfbus_grant) +#define AR_PHY_RIFS AR_SM_OFFSET(BB_rifs) +#define AR_PHY_RX_CLR_DELAY AR_SM_OFFSET(BB_rx_clear_delay) +#define AR_PHY_RX_DELAY AR_SM_OFFSET(BB_analog_power_on_time) +#define AR_PHY_BB_POWERTX_RATE9 AR_SM_OFFSET(BB_powertx_rate9) +#define AR_PHY_TPC_7 AR_SM_OFFSET(BB_tpc_7) +#define AR_PHY_CL_MAP_0_B0 AR_SM_OFFSET(BB_cl_map_0_b0) +#define AR_PHY_CL_MAP_1_B0 AR_SM_OFFSET(BB_cl_map_1_b0) +#define AR_PHY_CL_MAP_2_B0 AR_SM_OFFSET(BB_cl_map_2_b0) +#define AR_PHY_CL_MAP_3_B0 AR_SM_OFFSET(BB_cl_map_3_b0) + +#define AR_PHY_RF_CTL(_i) AR_SM_OFFSET(BB_tx_timing_##_i) + +#define AR_PHY_XPA_TIMING_CTL AR_SM_OFFSET(BB_xpa_timing_control) +#define AR_PHY_MISC_PA_CTL AR_SM_OFFSET(BB_misc_pa_control) +#define AR_PHY_SWITCH_CHAIN_0 AR_SM_OFFSET(BB_switch_table_chn_b0) +#define AR_PHY_SWITCH_COM AR_SM_OFFSET(BB_switch_table_com1) +#define AR_PHY_SWITCH_COM_2 AR_SM_OFFSET(BB_switch_table_com2) +#define AR_PHY_RX_CHAINMASK AR_SM_OFFSET(BB_multichain_enable) +#define AR_PHY_CAL_CHAINMASK AR_SM_OFFSET(BB_cal_chain_mask) +#define AR_PHY_AGC_CONTROL AR_SM_OFFSET(BB_agc_control) +#define AR_PHY_CALMODE AR_SM_OFFSET(BB_iq_adc_cal_mode) +#define AR_PHY_FCAL_1 AR_SM_OFFSET(BB_fcal_1) +#define AR_PHY_FCAL_2_0 AR_SM_OFFSET(BB_fcal_2_b0) +#define AR_PHY_DFT_TONE_CTL_0 AR_SM_OFFSET(BB_dft_tone_ctrl_b0) +#define AR_PHY_CL_CAL_CTL AR_SM_OFFSET(BB_cl_cal_ctrl) +#define AR_PHY_BBGAINMAP_0_1_0 AR_SM_OFFSET(BB_cl_bbgain_map_0_1_b0) +#define AR_PHY_BBGAINMAP_2_3_0 AR_SM_OFFSET(BB_cl_bbgain_map_2_3_b0) +#define AR_PHY_CL_TAB_0 AR_SM_OFFSET(BB_cl_tab_b0) +#define AR_PHY_SYNTH_CONTROL AR_SM_OFFSET(BB_synth_control) +#define AR_PHY_ADDAC_CLK_SEL AR_SM_OFFSET(BB_addac_clk_select) +#define AR_PHY_PLL_CTL AR_SM_OFFSET(BB_pll_cntl) +#define AR_PHY_ANALOG_SWAP AR_SM_OFFSET(BB_analog_swap) +#define AR_PHY_ADDAC_PARA_CTL AR_SM_OFFSET(BB_addac_parallel_control) +#define AR_PHY_XPA_CFG AR_SM_OFFSET(BB_force_analog) +#define AR_PHY_AIC_CTRL_0_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_0_b0) +#define AR_PHY_AIC_CTRL_1_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_1_b0) +#define AR_PHY_AIC_CTRL_2_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_2_b0) +#define AR_PHY_AIC_CTRL_3_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_3_b0) +#define AR_PHY_AIC_STAT_0_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_stat_0_b0) +#define AR_PHY_AIC_STAT_1_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_stat_1_b0) +#define AR_PHY_AIC_CTRL_0_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_0_b0) +#define AR_PHY_AIC_CTRL_1_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_1_b0) +#define AR_PHY_AIC_CTRL_2_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_2_b0) +#define AR_PHY_AIC_CTRL_3_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_3_b0) +#define AR_PHY_AIC_CTRL_4_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_4_b0) +#define AR_PHY_AIC_STAT_0_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_0_b0) +#define AR_PHY_AIC_STAT_1_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_1_b0) +#define AR_PHY_AIC_STAT_2_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_2_b0) +#define AR_PHY_AIC_CTRL_0_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_ctrl_0_b1) +#define AR_PHY_AIC_CTRL_1_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_ctrl_1_b1) +#define AR_PHY_AIC_STAT_0_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_stat_0_b1) +#define AR_PHY_AIC_STAT_1_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_stat_1_b1) +#define AR_PHY_AIC_CTRL_0_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_0_b1) +#define AR_PHY_AIC_CTRL_1_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_1_b1) +#define AR_PHY_AIC_CTRL_4_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_4_b1) +#define AR_PHY_AIC_STAT_0_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_0_b1) +#define AR_PHY_AIC_STAT_1_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_1_b1) +#define AR_PHY_AIC_STAT_2_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_2_b1) +#define AR_PHY_AIC_SRAM_ADDR_B0 AR_SM_OFFSET(BB_tables_intf_addr_b0) +#define AR_PHY_AIC_SRAM_DATA_B0 AR_SM_OFFSET(BB_tables_intf_data_b0) +#define AR_PHY_AIC_SRAM_ADDR_B1 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_tables_intf_addr_b1) +#define AR_PHY_AIC_SRAM_DATA_B1 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_tables_intf_data_b1) + + +/* AIC fields */ +#define AR_PHY_AIC_MON_ENABLE 0x80000000 +#define AR_PHY_AIC_MON_ENABLE_S 31 +#define AR_PHY_AIC_CAL_MAX_HOP_COUNT 0x7F000000 +#define AR_PHY_AIC_CAL_MAX_HOP_COUNT_S 24 +#define AR_PHY_AIC_CAL_MIN_VALID_COUNT 0x00FE0000 +#define AR_PHY_AIC_CAL_MIN_VALID_COUNT_S 17 +#define AR_PHY_AIC_F_WLAN 0x0001FC00 +#define AR_PHY_AIC_F_WLAN_S 10 +#define AR_PHY_AIC_CAL_CH_VALID_RESET 0x00000200 +#define AR_PHY_AIC_CAL_CH_VALID_RESET_S 9 +#define AR_PHY_AIC_CAL_ENABLE 0x00000100 +#define AR_PHY_AIC_CAL_ENABLE_S 8 +#define AR_PHY_AIC_BTTX_PWR_THR 0x000000FE +#define AR_PHY_AIC_BTTX_PWR_THR_S 1 +#define AR_PHY_AIC_ENABLE 0x00000001 +#define AR_PHY_AIC_ENABLE_S 0 +#define AR_PHY_AIC_CAL_BT_REF_DELAY 0x78000000 +#define AR_PHY_AIC_CAL_BT_REF_DELAY_S 27 +#define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO 0x07000000 +#define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO_S 24 +#define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO 0x00F00000 +#define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO_S 20 +#define AR_PHY_AIC_BT_IDLE_CFG 0x00080000 +#define AR_PHY_AIC_BT_IDLE_CFG_S 19 +#define AR_PHY_AIC_STDBY_COND 0x00060000 +#define AR_PHY_AIC_STDBY_COND_S 17 +#define AR_PHY_AIC_STDBY_ROT_ATT_DB 0x0001F800 +#define AR_PHY_AIC_STDBY_ROT_ATT_DB_S 11 +#define AR_PHY_AIC_STDBY_COM_ATT_DB 0x00000700 +#define AR_PHY_AIC_STDBY_COM_ATT_DB_S 8 +#define AR_PHY_AIC_RSSI_MAX 0x000000F0 +#define AR_PHY_AIC_RSSI_MAX_S 4 +#define AR_PHY_AIC_RSSI_MIN 0x0000000F +#define AR_PHY_AIC_RSSI_MIN_S 0 +#define AR_PHY_AIC_RADIO_DELAY 0x7F000000 +#define AR_PHY_AIC_RADIO_DELAY_S 24 +#define AR_PHY_AIC_CAL_STEP_SIZE_CORR 0x00F00000 +#define AR_PHY_AIC_CAL_STEP_SIZE_CORR_S 20 +#define AR_PHY_AIC_CAL_ROT_IDX_CORR 0x000F8000 +#define AR_PHY_AIC_CAL_ROT_IDX_CORR_S 15 +#define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR 0x00006000 +#define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR_S 13 +#define AR_PHY_AIC_ROT_IDX_COUNT_MAX 0x00001C00 +#define AR_PHY_AIC_ROT_IDX_COUNT_MAX_S 10 +#define AR_PHY_AIC_CAL_SYNTH_TOGGLE 0x00000200 +#define AR_PHY_AIC_CAL_SYNTH_TOGGLE_S 9 +#define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX 0x00000100 +#define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX_S 8 +#define AR_PHY_AIC_CAL_SYNTH_SETTLING 0x000000FF +#define AR_PHY_AIC_CAL_SYNTH_SETTLING_S 0 +#define AR_PHY_AIC_MON_MAX_HOP_COUNT 0x0FE00000 +#define AR_PHY_AIC_MON_MAX_HOP_COUNT_S 21 +#define AR_PHY_AIC_MON_MIN_STALE_COUNT 0x001FC000 +#define AR_PHY_AIC_MON_MIN_STALE_COUNT_S 14 +#define AR_PHY_AIC_MON_PWR_EST_LONG 0x00002000 +#define AR_PHY_AIC_MON_PWR_EST_LONG_S 13 +#define AR_PHY_AIC_MON_PD_TALLY_SCALING 0x00001800 +#define AR_PHY_AIC_MON_PD_TALLY_SCALING_S 11 +#define AR_PHY_AIC_MON_PERF_THR 0x000007C0 +#define AR_PHY_AIC_MON_PERF_THR_S 6 +#define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED 0x00000020 +#define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED_S 5 +#define AR_PHY_AIC_CAL_TARGET_MAG_SETTING 0x00000018 +#define AR_PHY_AIC_CAL_TARGET_MAG_SETTING_S 3 +#define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR 0x00000006 +#define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR_S 1 +#define AR_PHY_AIC_CAL_PWR_EST_LONG 0x00000001 +#define AR_PHY_AIC_CAL_PWR_EST_LONG_S 0 +#define AR_PHY_AIC_MON_DONE 0x80000000 +#define AR_PHY_AIC_MON_DONE_S 31 +#define AR_PHY_AIC_MON_ACTIVE 0x40000000 +#define AR_PHY_AIC_MON_ACTIVE_S 30 +#define AR_PHY_AIC_MEAS_COUNT 0x3F000000 +#define AR_PHY_AIC_MEAS_COUNT_S 24 +#define AR_PHY_AIC_CAL_ANT_ISO_EST 0x00FC0000 +#define AR_PHY_AIC_CAL_ANT_ISO_EST_S 18 +#define AR_PHY_AIC_CAL_HOP_COUNT 0x0003F800 +#define AR_PHY_AIC_CAL_HOP_COUNT_S 11 +#define AR_PHY_AIC_CAL_VALID_COUNT 0x000007F0 +#define AR_PHY_AIC_CAL_VALID_COUNT_S 4 +#define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR 0x00000008 +#define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR_S 3 +#define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR 0x00000004 +#define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR_S 2 +#define AR_PHY_AIC_CAL_DONE 0x00000002 +#define AR_PHY_AIC_CAL_DONE_S 1 +#define AR_PHY_AIC_CAL_ACTIVE 0x00000001 +#define AR_PHY_AIC_CAL_ACTIVE_S 0 +#define AR_PHY_AIC_MEAS_MAG_MIN 0xFFC00000 +#define AR_PHY_AIC_MEAS_MAG_MIN_S 22 +#define AR_PHY_AIC_MON_STALE_COUNT 0x003F8000 +#define AR_PHY_AIC_MON_STALE_COUNT_S 15 +#define AR_PHY_AIC_MON_HOP_COUNT 0x00007F00 +#define AR_PHY_AIC_MON_HOP_COUNT_S 8 +#define AR_PHY_AIC_CAL_AIC_SM 0x000000F8 +#define AR_PHY_AIC_CAL_AIC_SM_S 3 +#define AR_PHY_AIC_SM 0x00000007 +#define AR_PHY_AIC_SM_S 0 +#define AR_PHY_AIC_SRAM_VALID 0x00000001 +#define AR_PHY_AIC_SRAM_VALID_S 0 +#define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB 0x0000007E +#define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB_S 1 +#define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN 0x00000080 +#define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN_S 7 +#define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB 0x00003F00 +#define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB_S 8 +#define AR_PHY_AIC_SRAM_VGA_DIR_SIGN 0x00004000 +#define AR_PHY_AIC_SRAM_VGA_DIR_SIGN_S 14 +#define AR_PHY_AIC_SRAM_COM_ATT_6DB 0x00038000 +#define AR_PHY_AIC_SRAM_COM_ATT_6DB_S 15 + +#define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW 3 +#define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S 0 + +/* BB_cl_tab_bx */ +#define AR_PHY_CL_TAB_CARR_LK_DC_ADD_I 0x07FF0000 +#define AR_PHY_CL_TAB_CARR_LK_DC_ADD_I_S 16 +#define AR_PHY_CL_TAB_CARR_LK_DC_ADD_Q 0x0000FFE0 +#define AR_PHY_CL_TAB_CARR_LK_DC_ADD_Q_S 5 +#define AR_PHY_CL_TAB_GAIN_MOD 0x0000001F +#define AR_PHY_CL_TAB_GAIN_MOD_S 0 + +/* BB_vit_spur_mask_A fields */ +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0 + +/* enable_flt_svd*/ +#define AR_PHY_ENABLE_FLT_SVD 0x00001000 +#define AR_PHY_ENABLE_FLT_SVD_S 12 + +#define AR_PHY_TEST AR_SM_OFFSET(BB_test_controls) + +#define AR_PHY_TEST_BBB_OBS_SEL 0x780000 +#define AR_PHY_TEST_BBB_OBS_SEL_S 19 /* bits 19 to 22 are cf_bbb_obs_sel*/ + +#define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23 +#define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)// This is bit 5 for cf_rx_obs_sel + +#define AR_PHY_TEST_CHAIN_SEL 0xC0000000 +#define AR_PHY_TEST_CHAIN_SEL_S 30 /*bits 30 and 31 are tstdac_out_sel which selects which chain to drive out*/ + +#define AR_PHY_TEST_CTL_STATUS AR_SM_OFFSET(BB_test_controls_status) +#define AR_PHY_TEST_CTL_TSTDAC_EN 0x1 +#define AR_PHY_TEST_CTL_TSTDAC_EN_S 0 /*cf_tstdac_en, driver to tstdac bus, 0=disable, 1=enable*/ +#define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C +#define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2 /* cf_tx_obs_sel, bits 2:4*/ +#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60 +#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5 /* cf_tx_obs_sel, bits 5:6, setting to 11 selects ADC*/ +#define AR_PHY_TEST_CTL_TSTADC_EN 0x100 +#define AR_PHY_TEST_CTL_TSTADC_EN_S 8 /*cf_tstadc_en, driver to tstadc bus, 0=disable, 1=enable*/ +#define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00 +#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10 /* cf_tx_obs_sel, bits 10:13*/ +#define AR_PHY_TEST_CTL_DEBUGPORT_SEL 0xe0000000 +#define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S 29 + + +#define AR_PHY_TSTDAC AR_SM_OFFSET(BB_tstdac) + +#define AR_PHY_CHAN_STATUS AR_SM_OFFSET(BB_channel_status) +#define AR_PHY_CHAN_INFO_MEMORY AR_SM_OFFSET(BB_chaninfo_ctrl) +#define AR_PHY_CHNINFO_NOISEPWR AR_SM_OFFSET(BB_chan_info_noise_pwr) +#define AR_PHY_CHNINFO_GAINDIFF AR_SM_OFFSET(BB_chan_info_gain_diff) +#define AR_PHY_CHNINFO_FINETIM AR_SM_OFFSET(BB_chan_info_fine_timing) +#define AR_PHY_CHAN_INFO_GAIN_0 AR_SM_OFFSET(BB_chan_info_gain_b0) +#define AR_PHY_SCRAMBLER_SEED AR_SM_OFFSET(BB_scrambler_seed) +#define AR_PHY_CCK_TX_CTRL AR_SM_OFFSET(BB_bbb_tx_ctrl) + +#define AR_PHY_TX_FIR(_i) AR_SM_OFFSET(BB_bbb_txfir_##_i) + +#define AR_PHY_HEAVYCLIP_CTL AR_SM_OFFSET(BB_heavy_clip_ctrl) +#define AR_PHY_HEAVYCLIP_20 AR_SM_OFFSET(BB_heavy_clip_20) +#define AR_PHY_HEAVYCLIP_40 AR_SM_OFFSET(BB_heavy_clip_40) +#define AR_PHY_ILLEGAL_TXRATE AR_SM_OFFSET(BB_illegal_tx_rate) + +#define AR_PHY_POWER_TX_RATE(_i) AR_SM_OFFSET(BB_powertx_rate##_i) + +#define AR_PHY_PWRTX_MAX AR_SM_OFFSET(BB_powertx_max) /* TPC register */ +#define AR_PHY_PWRTX_MAX_TPC_ENABLE 0x00000040 +#define AR_PHY_POWER_TX_SUB AR_SM_OFFSET(BB_powertx_sub) +#define AR_PHY_PER_PACKET_POWERTX_MAX 0x00000040 +#define AR_PHY_PER_PACKET_POWERTX_MAX_S 6 +#define AR_PHY_POWER_TX_SUB_2_DISABLE 0xFFFFFFC0 /* 2 chain */ +#define AR_PHY_POWER_TX_SUB_3_DISABLE 0xFFFFF000 /* 3 chain */ + +#define AR_PHY_TPC(_i) AR_SM_OFFSET(BB_tpc_##_i) /* values 1-3, 7-10 and 12-15 */ +#define AR_PHY_TPC_4_B0 AR_SM_OFFSET(BB_tpc_4_b0) +#define AR_PHY_TPC_5_B0 AR_SM_OFFSET(BB_tpc_5_b0) +#define AR_PHY_TPC_6_B0 AR_SM_OFFSET(BB_tpc_6_b0) +#define AR_PHY_TPC_18 AR_SM_OFFSET(BB_tpc_18) +#define AR_PHY_TPC_19 AR_SM_OFFSET(BB_tpc_19) + +#define AR_PHY_TX_FORCED_GAIN AR_SM_OFFSET(BB_tx_forced_gain) + +#define AR_PHY_PDADC_TAB_0 AR_SM_OFFSET(BB_pdadc_tab_b0) + +#define AR_PHY_RTT_CTRL AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_ctrl) +#define AR_PHY_RTT_TABLE_SW_INTF_B0 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_table_sw_intf_b0) +#define AR_PHY_RTT_TABLE_SW_INTF_1_B0 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_table_sw_intf_1_b0) + +#define AR_PHY_TX_IQCAL_CONTROL_0(_ah) \ + (AR_SREV_POSEIDON(_ah) ? \ + AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_0) : \ + AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_control_0)) + +#define AR_PHY_TX_IQCAL_CONTROL_1(_ah) \ + (AR_SREV_POSEIDON(_ah) ? \ + AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_1) : \ + AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_control_1)) + +#define AR_PHY_TX_IQCAL_START(_ah) \ + (AR_SREV_POSEIDON(_ah) ? \ + AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_0) : \ + AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_start)) + +#define AR_PHY_TX_IQCAL_STATUS_B0(_ah) \ + (AR_SREV_POSEIDON(_ah) ? \ + AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_status_b0) : \ + AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_status_b0)) + +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_01_b0) +#define AR_PHY_TX_IQCAL_CORR_COEFF_23_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_23_b0) +#define AR_PHY_TX_IQCAL_CORR_COEFF_45_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_45_b0) +#define AR_PHY_TX_IQCAL_CORR_COEFF_67_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_67_b0) + +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_01_b0) +#define AR_PHY_TX_IQCAL_CORR_COEFF_23_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_23_b0) +#define AR_PHY_TX_IQCAL_CORR_COEFF_45_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_45_b0) +#define AR_PHY_TX_IQCAL_CORR_COEFF_67_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_67_b0) + +#define AR_PHY_TXGAIN_TAB(_i) AR_SM_OFFSET(BB_tx_gain_tab_##_i) /* values 1-22 */ +#define AR_PHY_TXGAIN_TAB_PAL(_i) AR_SM_OFFSET(BB_tx_gain_tab_pal_##_i) /* values 1-22 */ +#define AR_PHY_PANIC_WD_STATUS AR_SM_OFFSET(BB_panic_watchdog_status) +#define AR_PHY_PANIC_WD_CTL_1 AR_SM_OFFSET(BB_panic_watchdog_ctrl_1) +#define AR_PHY_PANIC_WD_CTL_2 AR_SM_OFFSET(BB_panic_watchdog_ctrl_2) +#define AR_PHY_BT_CTL AR_SM_OFFSET(BB_bluetooth_cntl) +#define AR_PHY_ONLY_WARMRESET AR_SM_OFFSET(BB_phyonly_warm_reset) +#define AR_PHY_ONLY_CTL AR_SM_OFFSET(BB_phyonly_control) +#define AR_PHY_ECO_CTRL AR_SM_OFFSET(BB_eco_ctrl) +#define AR_PHY_BB_THERM_ADC_1 AR_SM_OFFSET(BB_therm_adc_1) +#define AR_PHY_BB_THERM_ADC_4 AR_SM_OFFSET(BB_therm_adc_4) + +#define AR_PHY_65NM(_field) offsetof(struct radio65_reg, _field) +#define AR_PHY_65NM_CH0_TXRF1 AR_PHY_65NM(ch0_TXRF1) +#define AR_PHY_65NM_CH0_TXRF2 AR_PHY_65NM(ch0_TXRF2) +#define AR_PHY_65NM_CH0_TXRF2_DB2G 0x07000000 +#define AR_PHY_65NM_CH0_TXRF2_DB2G_S 24 +#define AR_PHY_65NM_CH0_TXRF2_OB2G_CCK 0x00E00000 +#define AR_PHY_65NM_CH0_TXRF2_OB2G_CCK_S 21 +#define AR_PHY_65NM_CH0_TXRF2_OB2G_PSK 0x001C0000 +#define AR_PHY_65NM_CH0_TXRF2_OB2G_PSK_S 18 +#define AR_PHY_65NM_CH0_TXRF2_OB2G_QAM 0x00038000 +#define AR_PHY_65NM_CH0_TXRF2_OB2G_QAM_S 15 +#define AR_PHY_65NM_CH0_TXRF3 AR_PHY_65NM(ch0_TXRF3) +#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G 0x0000001E +#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1 +#define AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE 0x00000001 +#define AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE_S 0 +#define AR_PHY_65NM_CH1_TXRF1 AR_PHY_65NM(ch1_TXRF1) +#define AR_PHY_65NM_CH1_TXRF2 AR_PHY_65NM(ch1_TXRF2) +#define AR_PHY_65NM_CH1_TXRF3 AR_PHY_65NM(ch1_TXRF3) +#define AR_PHY_65NM_CH2_TXRF1 AR_PHY_65NM(ch2_TXRF1) +#define AR_PHY_65NM_CH2_TXRF2 AR_PHY_65NM(ch2_TXRF2) +#define AR_PHY_65NM_CH2_TXRF3 AR_PHY_65NM(ch2_TXRF3) + +#define AR_PHY_65NM_CH0_SYNTH4 AR_PHY_65NM(ch0_SYNTH4) +#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002 +#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1 +#define AR_PHY_65NM_CH0_SYNTH7 AR_PHY_65NM(ch0_SYNTH7) +#define AR_PHY_65NM_CH0_BIAS1 AR_PHY_65NM(ch0_BIAS1) +#define AR_PHY_65NM_CH0_BIAS2 AR_PHY_65NM(ch0_BIAS2) +#define AR_PHY_65NM_CH0_BIAS4 AR_PHY_65NM(ch0_BIAS4) +#define AR_PHY_65NM_CH0_RXTX4 AR_PHY_65NM(ch0_RXTX4) +#define AR_PHY_65NM_CH0_SYNTH12 AR_PHY_65NM(ch0_SYNTH12) +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000 +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S 19 +#define AR_PHY_65NM_CH1_RXTX4 AR_PHY_65NM(ch1_RXTX4) +#define AR_PHY_65NM_CH2_RXTX4 AR_PHY_65NM(ch2_RXTX4) +#define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000 +#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30 + +#define AR_PHY_65NM_CH0_TOP AR_PHY_65NM(overlay_0x16180.Osprey.ch0_TOP) +#define AR_PHY_65NM_CH0_TOP_JUPITER AR_PHY_65NM(overlay_0x16180.Jupiter.ch0_TOP1) +#define AR_PHY_65NM_CH0_TOP_XPABIASLVL 0x00000300 +#define AR_PHY_65NM_CH0_TOP_XPABIASLVL_S 8 +#define AR_PHY_65NM_CH0_TOP2 AR_PHY_65NM(overlay_0x16180.Osprey.ch0_TOP2) + +#define AR_OSPREY_CH0_XTAL AR_PHY_65NM(overlay_0x16180.Osprey.ch0_XTAL) +#define AR_OSPREY_CHO_XTAL_CAPINDAC 0x7F000000 +#define AR_OSPREY_CHO_XTAL_CAPINDAC_S 24 +#define AR_OSPREY_CHO_XTAL_CAPOUTDAC 0x00FE0000 +#define AR_OSPREY_CHO_XTAL_CAPOUTDAC_S 17 + +#define AR_PHY_65NM_CH0_THERM AR_PHY_65NM(overlay_0x16180.Osprey.ch0_THERM) +#define AR_PHY_65NM_CH0_THERM_JUPITER AR_PHY_65NM(overlay_0x16180.Jupiter.ch0_THERM) + +#define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB 0x00000003 +#define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_S 0 +#define AR_PHY_65NM_CH0_THERM_XPASHORT2GND 0x00000004 +#define AR_PHY_65NM_CH0_THERM_XPASHORT2GND_S 2 +#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00 +#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8 +#define AR_PHY_65NM_CH0_THERM_START 0x20000000 +#define AR_PHY_65NM_CH0_THERM_START_S 29 +#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 +#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 + +#define AR_PHY_65NM_CH0_RXTX1 AR_PHY_65NM(ch0_RXTX1) +#define AR_PHY_65NM_CH0_RXTX2 AR_PHY_65NM(ch0_RXTX2) +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S 2 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK 0x00000008 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S 3 +#define AR_PHY_65NM_CH0_RXTX3 AR_PHY_65NM(ch0_RXTX3) +#define AR_PHY_65NM_CH1_RXTX1 AR_PHY_65NM(ch1_RXTX1) +#define AR_PHY_65NM_CH1_RXTX2 AR_PHY_65NM(ch1_RXTX2) +#define AR_PHY_65NM_CH1_RXTX3 AR_PHY_65NM(ch1_RXTX3) +#define AR_PHY_65NM_CH2_RXTX1 AR_PHY_65NM(ch2_RXTX1) +#define AR_PHY_65NM_CH2_RXTX2 AR_PHY_65NM(ch2_RXTX2) +#define AR_PHY_65NM_CH2_RXTX3 AR_PHY_65NM(ch2_RXTX3) + +#define AR_PHY_65NM_CH0_BB1 AR_PHY_65NM(ch0_BB1) +#define AR_PHY_65NM_CH0_BB2 AR_PHY_65NM(ch0_BB2) +#define AR_PHY_65NM_CH0_BB3 AR_PHY_65NM(ch0_BB3) +#define AR_PHY_65NM_CH1_BB1 AR_PHY_65NM(ch1_BB1) +#define AR_PHY_65NM_CH1_BB2 AR_PHY_65NM(ch1_BB2) +#define AR_PHY_65NM_CH1_BB3 AR_PHY_65NM(ch1_BB3) +#define AR_PHY_65NM_CH2_BB1 AR_PHY_65NM(ch2_BB1) +#define AR_PHY_65NM_CH2_BB2 AR_PHY_65NM(ch2_BB2) +#define AR_PHY_CH_BB3_SEL_OFST_READBK 0x00000300 +#define AR_PHY_CH_BB3_SEL_OFST_READBK_S 8 +#define AR_PHY_CH_BB3_OFSTCORRI2VQ 0x03e00000 +#define AR_PHY_CH_BB3_OFSTCORRI2VQ_S 21 +#define AR_PHY_CH_BB3_OFSTCORRI2VI 0x7c000000 +#define AR_PHY_CH_BB3_OFSTCORRI2VI_S 26 + +#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000 +#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19 +#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000 +#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22 +#define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000 +#define AR_PHY_LNAGAIN_LONG_SHIFT_S 29 +#define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000 +#define AR_PHY_MXRGAIN_LONG_SHIFT_S 24 +#define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000 +#define AR_PHY_VGAGAIN_LONG_SHIFT_S 26 +#define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001 +#define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0 +#define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002 +#define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1 +#define AR_PHY_MANTXGAIN_LONG_SHIFT 0x80000000 +#define AR_PHY_MANTXGAIN_LONG_SHIFT_S 31 + +/* + * SM Field Definitions + */ + +/* BB_cl_cal_ctrl - AR_PHY_CL_CAL_CTL */ +#define AR_PHY_CL_CAL_ENABLE 0x00000002 /* do carrier leak calibration after agc_calibrate_done */ +#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 +#define AR_PHY_CL_MAP_HW_GEN 0x80000000 +#define AR_PHY_CL_MAP_HW_GEN_S 31 + +/* BB_addac_parallel_control - AR_PHY_ADDAC_PARA_CTL */ +#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000 + +/* BB_fcal_2_b0 - AR_PHY_FCAL_2_0 */ +#define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000 +#define AR_PHY_FCAL20_CAP_STATUS_0_S 20 + +/* BB_rfbus_request */ +#define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */ +/* BB_rfbus_grant */ +#define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */ +/* BB_gen_controls */ +#define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */ +#define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */ +#define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */ +#define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ +#define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ +#define AR_PHY_GC_DYN2040_PRI_CH_S 4 + +#define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ +#define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */ +#define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ +#define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ +#define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ +#define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */ +#define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */ + +#define AR_PHY_MS_HALF_RATE 0x00000020 +#define AR_PHY_MS_QUARTER_RATE 0x00000040 + +/* BB_analog_power_on_time */ +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ +/* BB_agc_control */ +#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */ +#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */ +#define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */ +#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */ +#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */ +#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */ +#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */ +#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */ +#define AR_PHY_AGC_CONTROL_PKDET_CAL 0x00100000 /* allow peak deteter calibration */ + +#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 +#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 + +/* BB_iq_adc_cal_mode */ +#define AR_PHY_CALMODE_IQ 0x00000000 +#define AR_PHY_CALMODE_ADC_GAIN 0x00000001 +#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 +#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 +/* BB_analog_swap */ +#define AR_PHY_SWAP_ALT_CHAIN 0x00000040 +/* BB_modes_select */ +#define AR_PHY_MODE_OFDM 0x00000000 /* OFDM */ +#define AR_PHY_MODE_CCK 0x00000001 /* CCK */ +#define AR_PHY_MODE_DYNAMIC 0x00000004 /* dynamic CCK/OFDM mode */ +#define AR_PHY_MODE_DYNAMIC_S 2 +#define AR_PHY_MODE_HALF 0x00000020 /* enable half rate */ +#define AR_PHY_MODE_QUARTER 0x00000040 /* enable quarter rate */ +#define AR_PHY_MAC_CLK_MODE 0x00000080 /* MAC runs at 128/141MHz clock */ +#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100 /* Disable dynamic CCK detection */ +#define AR_PHY_MODE_SVD_HALF 0x00000200 /* enable svd half rate */ +#define AR_PHY_MODE_DISABLE_CCK 0x00000100 +#define AR_PHY_MODE_DISABLE_CCK_S 8 +/* BB_active */ +#define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */ +#define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */ +/* BB_force_analog */ +#define AR_PHY_FORCE_XPA_CFG 0x000000001 +#define AR_PHY_FORCE_XPA_CFG_S 0 +/* BB_xpa_timing_control */ +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0 +/* BB_tx_timing_3 */ +#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 +#define AR_PHY_TX_END_TO_A2_RX_ON_S 16 +/* BB_tx_timing_2 */ +#define AR_PHY_TX_END_DATA_START 0x000000FF +#define AR_PHY_TX_END_DATA_START_S 0 +#define AR_PHY_TX_END_PA_ON 0x0000FF00 +#define AR_PHY_TX_END_PA_ON_S 8 +/* BB_tpc_5_b0 */ +/* ar2413 power control */ +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 +/* BB_tpc_1 */ +#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 +#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 +#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 +#define AR_PHY_TPCRG1_PD_GAIN_1_S 16 +#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 +#define AR_PHY_TPCRG1_PD_GAIN_2_S 18 +#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 +#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 +#define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e +#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1 +#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001 + +/* BB_tx_forced_gain */ +#define AR_PHY_TXGAIN_FORCE 0x00000001 +#define AR_PHY_TXGAIN_FORCE_S 0 +#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00 +#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10 +#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000 +#define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14 +#define AR_PHY_TXGAIN_FORCED_PADVGNRC 0x003c0000 +#define AR_PHY_TXGAIN_FORCED_PADVGNRC_S 18 +#define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000 +#define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22 +#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0 +#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6 +#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e +#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1 +#define AR_PHY_TXGAIN_FORCED_TXBB6DBGAIN 0x00000030 +#define AR_PHY_TXGAIN_FORCED_TXBB6DBGAIN_S 4 + +/* BB_powertx_rate1 */ +#define AR_PHY_POWER_TX_RATE1 0x9934 +#define AR_PHY_POWER_TX_RATE2 0x9938 +#define AR_PHY_POWER_TX_RATE_MAX AR_PHY_PWRTX_MAX +#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 +/* BB_test_controls */ +#define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */ +#define RFSILENT_BB 0x00002000 /* shush bb */ +/* BB_chan_info_gain_diff */ +#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF /* PPM value is 12-bit signed integer */ +#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800 /* Sign bit */ +#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 /* Maximum absolute value */ +/* BB_chaninfo_ctrl */ +#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 +/* BB_search_start_delay */ +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ +/* BB_bbb_tx_ctrl */ +#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 +/* BB_spectral_scan */ +#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001 /* Enable spectral scan */ +#define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan */ +#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports */ +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 +#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports */ +#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 +#define AR_PHY_SPECTRAL_SCAN_COUNT 0x0FFF0000 /* Number of reports */ +#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x10000000 /* Short repeat */ +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 28 +#define AR_PHY_SPECTRAL_SCAN_PRIORITY_HI 0x20000000 /* high priority */ +#define AR_PHY_SPECTRAL_SCAN_PRIORITY_HI_S 29 +/* BB_channel_status */ +#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004 +/* BB_rtt_ctrl */ +#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001 +#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0 +#define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E +#define AR_PHY_RTT_CTRL_RESTORE_MASK_S 1 +#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080 +#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S 7 +/* BB_rtt_table_sw_intf_b0 */ +#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_0 0x00000001 +#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_0_S 0 +#define AR_PHY_RTT_SW_RTT_TABLE_WRITE_0 0x00000002 +#define AR_PHY_RTT_SW_RTT_TABLE_WRITE_0_S 1 +#define AR_PHY_RTT_SW_RTT_TABLE_ADDR_0 0x0000001C +#define AR_PHY_RTT_SW_RTT_TABLE_ADDR_0_S 2 +/* BB_rtt_table_sw_intf_1_b0 */ +#define AR_PHY_RTT_SW_RTT_TABLE_DATA_0 0xFFFFFFF0 +#define AR_PHY_RTT_SW_RTT_TABLE_DATA_0_S 4 +/* BB_txiqcal_control_0 */ +#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000 +#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S 31 +/* BB_txiqcal_control_1 */ +#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000 +#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18 +/* BB_txiqcal_start */ +#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001 +#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0 +/* BB_txiqcal_start for Poseidon */ +#define AR_PHY_TX_IQCAL_START_DO_CAL_POSEIDON 0x80000000 +#define AR_PHY_TX_IQCAL_START_DO_CAL_POSEIDON_S 31 + +/* Generic B0, B1, B2 IQ Cal bit fields */ +/* BB_txiqcal_status_b* */ +#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001 +#define AR_PHY_CALIBRATED_GAINS_0_S 1 +#define AR_PHY_CALIBRATED_GAINS_0 (0x1f< */ +#define AR_CFG_LED_POWER_S 7 /* LED mode: bits 7..9 */ +#define AR_CFG_LED_NETWORK 0x00000300 /* Network LED: bit 9=1, bit 8= */ +#define AR_CFG_LED_NETWORK_S 7 /* LED mode: bits 7..9 */ +#define AR_CFG_LED_MODE_PROP 0x0 /* Blink prop to filtered tx/rx */ +#define AR_CFG_LED_MODE_RPROP 0x1 /* Blink prop to unfiltered tx/rx */ +#define AR_CFG_LED_MODE_SPLIT 0x2 /* Blink power for tx/net for rx */ +#define AR_CFG_LED_MODE_RAND 0x3 /* Blink randomly */ +#define AR_CFG_LED_MODE_POWER_OFF 0x4 /* Power LED OFF */ +#define AR_CFG_LED_MODE_POWER_ON 0x5 /* Power LED ON */ +#define AR_CFG_LED_MODE_NETWORK_OFF 0x4 /* Network LED OFF */ +#define AR_CFG_LED_MODE_NETWORK_ON 0x6 /* Network LED ON */ +#define AR_CFG_LED_ASSOC_CTL 0x00000c00 /* LED control: bits 10..11 */ +#define AR_CFG_LED_ASSOC_CTL_S 10 /* LED control: bits 10..11 */ +#define AR_CFG_LED_ASSOC_NONE 0x0 /* 0x00000000: STA is not associated or trying */ +#define AR_CFG_LED_ASSOC_ACTIVE 0x1 /* 0x00000400: STA is associated */ +#define AR_CFG_LED_ASSOC_PENDING 0x2 /* 0x00000800: STA is trying to associate */ + +#define AR_CFG_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode: bit 3 */ +#define AR_CFG_LED_BLINK_SLOW_S 3 /* LED slowest blink rate mode: bit 3 */ + +#define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select: bits 4..6 */ +#define AR_CFG_LED_BLINK_THRESH_SEL_S 4 /* LED blink threshold select: bits 4..6 */ + +#define AR_MAC_SLEEP 0x1f00 +#define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 // mac is now awake +#define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 // mac is now asleep + + + +/****************************************************************************** + * Host Interface Register Map +******************************************************************************/ +// DMA & PCI Registers in PCI space (usable during sleep) + +#define AR_HOSTIF_REG(_ah, _reg) (AH9300(_ah)->ah_hostifregs._reg) +#define AR9300_HOSTIF_OFFSET(_x) offsetof(struct host_intf_reg, _x) +#define AR9340_HOSTIF_OFFSET(_x) offsetof(struct host_intf_reg_ar9340, _x) + +/* Interface Reset Control Register */ +#define AR_RC_AHB 0x00000001 // ahb reset +#define AR_RC_APB 0x00000002 // apb reset +#define AR_RC_HOSTIF 0x00000100 // host interface reset + +/* PCI express work-arounds */ +#define AR_WA_D3_TO_L1_DISABLE (1 << 14) +#define AR_WA_UNTIE_RESET_EN (1 << 15) /* Enable PCI Reset to POR (power-on-reset) */ +#define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16) +#define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17) +#define AR_WA_RESET_EN (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */ +#define AR_WA_ANALOG_SHIFT (1 << 20) +#define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */ +#define AR_WA_COLD_RESET_OVERRIDE (1 << 13) /* PCI-E Cold reset override */ + +/* power management state */ +#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 //for wow + +/* CXPL Debug signals which help debug Link Negotiation */ +/* CXPL Debug signals which help debug Link Negotiation */ + +/* XXX check bit feilds */ +/* Power Management Control Register */ +#define AR_PCIE_PM_CTRL_ENA 0x00080000 +#define AR_PMCTRL_WOW_PME_CLR 0x00200000 /* Clear WoW event */ +#define AR_PMCTRL_HOST_PME_EN 0x00400000 /* Send OOB WAKE_L on WoW event */ +#define AR_PMCTRL_D3COLD_VAUX 0x00800000 +#define AR_PMCTRL_PWR_STATE_MASK 0x0F000000 /* Power State Mask */ +#define AR_PMCTRL_PWR_STATE_D1D3 0x0F000000 /* Activate D1 and D3 */ +#define AR_PMCTRL_PWR_STATE_D0 0x08000000 /* Activate D0 */ +#define AR_PMCTRL_PWR_PM_CTRL_ENA 0x00008000 /* Enable power management */ +#define AR_PMCTRL_AUX_PWR_DET 0x10000000 /* Puts Chip in L2 state */ + + + +/* APB and Local Bus Timeout Counters */ +#define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF +#define AR_HOST_TIMEOUT_APB_CNTR_S 0 +#define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 +#define AR_HOST_TIMEOUT_LCL_CNTR_S 16 + +/* EEPROM Control Register */ +#define AR_EEPROM_ABSENT 0x00000100 +#define AR_EEPROM_CORRUPT 0x00000200 +#define AR_EEPROM_PROT_MASK 0x03FFFC00 +#define AR_EEPROM_PROT_MASK_S 10 + +// Protect Bits RP is read protect WP is write protect +#define EEPROM_PROTECT_RP_0_31 0x0001 +#define EEPROM_PROTECT_WP_0_31 0x0002 +#define EEPROM_PROTECT_RP_32_63 0x0004 +#define EEPROM_PROTECT_WP_32_63 0x0008 +#define EEPROM_PROTECT_RP_64_127 0x0010 +#define EEPROM_PROTECT_WP_64_127 0x0020 +#define EEPROM_PROTECT_RP_128_191 0x0040 +#define EEPROM_PROTECT_WP_128_191 0x0080 +#define EEPROM_PROTECT_RP_192_255 0x0100 +#define EEPROM_PROTECT_WP_192_255 0x0200 +#define EEPROM_PROTECT_RP_256_511 0x0400 +#define EEPROM_PROTECT_WP_256_511 0x0800 +#define EEPROM_PROTECT_RP_512_1023 0x1000 +#define EEPROM_PROTECT_WP_512_1023 0x2000 +#define EEPROM_PROTECT_RP_1024_2047 0x4000 +#define EEPROM_PROTECT_WP_1024_2047 0x8000 + +/* RF silent */ +#define AR_RFSILENT_FORCE 0x01 + +/* MAC silicon Rev ID */ +#define AR_SREV_ID 0x000000FF /* Mask to read SREV info */ +#define AR_SREV_VERSION 0x000000F0 /* Mask for Chip version */ +#define AR_SREV_VERSION_S 4 /* Mask to shift Major Rev Info */ +#define AR_SREV_REVISION 0x00000007 /* Mask for Chip revision level */ + +/* Sowl extension to SREV. AR_SREV_ID must be 0xFF */ +#define AR_SREV_ID2 0xFFFFFFFF /* Mask to read SREV info */ +#define AR_SREV_VERSION2 0xFFFC0000 /* Mask for Chip version */ +#define AR_SREV_VERSION2_S 18 /* Mask to shift Major Rev Info */ +#define AR_SREV_TYPE2 0x0003F000 /* Mask for Chip type */ +#define AR_SREV_TYPE2_S 12 /* Mask to shift Major Rev Info */ +#define AR_SREV_TYPE2_CHAIN 0x00001000 /* chain mode (1 = 3 chains, 0 = 2 chains) */ +#define AR_SREV_TYPE2_HOST_MODE 0x00002000 /* host mode (1 = PCI, 0 = PCIe) */ +/* Jupiter has a different TYPE2 definition. */ +#define AR_SREV_TYPE2_JUPITER_CHAIN 0x00001000 /* chain (1 = 2 chains, 0 = 1 chain) */ +#define AR_SREV_TYPE2_JUPITER_BAND 0x00002000 /* band (1 = dual band, 0 = single band) */ +#define AR_SREV_TYPE2_JUPITER_BT 0x00004000 /* BT (1 = shared BT, 0 = no BT) */ +#define AR_SREV_TYPE2_JUPITER_MODE 0x00008000 /* mode (1 = premium, 0 = standard) */ +#define AR_SREV_REVISION2 0x00000F00 +#define AR_SREV_REVISION2_S 8 + +#define AR_RADIO_SREV_MAJOR 0xf0 +#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ +#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ +#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ +#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ + +#if 0 +#define AR_AHB_MODE 0x4024 // ahb mode for dma +#define AR_AHB_EXACT_WR_EN 0x00000000 // write exact bytes +#define AR_AHB_BUF_WR_EN 0x00000001 // buffer write upto cacheline +#define AR_AHB_EXACT_RD_EN 0x00000000 // read exact bytes +#define AR_AHB_CACHELINE_RD_EN 0x00000002 // read upto end of cacheline +#define AR_AHB_PREFETCH_RD_EN 0x00000004 // prefetch upto page boundary +#define AR_AHB_PAGE_SIZE_1K 0x00000000 // set page-size as 1k +#define AR_AHB_PAGE_SIZE_2K 0x00000008 // set page-size as 2k +#define AR_AHB_PAGE_SIZE_4K 0x00000010 // set page-size as 4k +#endif + +#define AR_INTR_RTC_IRQ 0x00000001 // rtc in shutdown state +#define AR_INTR_MAC_IRQ 0x00000002 // pending mac interrupt +#if 0 +/* + * the following definitions might be differents for WASP so + * disable them to avoid improper use + */ +#define AR_INTR_EEP_PROT_ACCESS 0x00000004 // eeprom protected area access +#define AR_INTR_MAC_AWAKE 0x00020000 // mac is awake +#define AR_INTR_MAC_ASLEEP 0x00040000 // mac is asleep +#endif +#define AR_INTR_SPURIOUS 0xFFFFFFFF + +/* TODO: fill in other values */ + +/* Synchronous Interrupt Cause Register */ + +/* Synchronous Interrupt Enable Register */ +#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31 +#define AR_INTR_SYNC_ENABLE_GPIO_S 18 // enable interrupts: bits 18..31 + +/* + * synchronous interrupt signals + */ +enum { + AR9300_INTR_SYNC_RTC_IRQ = 0x00000001, + AR9300_INTR_SYNC_MAC_IRQ = 0x00000002, + AR9300_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, + AR9300_INTR_SYNC_APB_TIMEOUT = 0x00000008, + AR9300_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, + AR9300_INTR_SYNC_HOST1_FATAL = 0x00000020, + AR9300_INTR_SYNC_HOST1_PERR = 0x00000040, + AR9300_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, + AR9300_INTR_SYNC_RADM_CPL_EP = 0x00000100, + AR9300_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, + AR9300_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400, + AR9300_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, + AR9300_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, + AR9300_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, + AR9300_INTR_SYNC_PM_ACCESS = 0x00004000, + AR9300_INTR_SYNC_MAC_AWAKE = 0x00008000, + AR9300_INTR_SYNC_MAC_ASLEEP = 0x00010000, + AR9300_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, + AR9300_INTR_SYNC_ALL = 0x0003FFFF, + + /* + * Do not enable and turn on mask for both sync and async interrupt, since + * chip can generate interrupt storm. + */ + AR9300_INTR_SYNC_DEF_NO_HOST1_PERR = (AR9300_INTR_SYNC_HOST1_FATAL | + AR9300_INTR_SYNC_RADM_CPL_EP | + AR9300_INTR_SYNC_RADM_CPL_DLLP_ABORT | + AR9300_INTR_SYNC_RADM_CPL_TLP_ABORT | + AR9300_INTR_SYNC_RADM_CPL_ECRC_ERR | + AR9300_INTR_SYNC_RADM_CPL_TIMEOUT | + AR9300_INTR_SYNC_LOCAL_TIMEOUT | + AR9300_INTR_SYNC_MAC_SLEEP_ACCESS), + AR9300_INTR_SYNC_DEFAULT = (AR9300_INTR_SYNC_DEF_NO_HOST1_PERR | + AR9300_INTR_SYNC_HOST1_PERR), + + AR9300_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, + + /* WASP */ + AR9340_INTR_SYNC_RTC_IRQ = 0x00000001, + AR9340_INTR_SYNC_MAC_IRQ = 0x00000002, + AR9340_INTR_SYNC_HOST1_FATAL = 0x00000004, + AR9340_INTR_SYNC_HOST1_PERR = 0x00000008, + AR9340_INTR_SYNC_LOCAL_TIMEOUT = 0x00000010, + AR9340_INTR_SYNC_MAC_ASLEEP = 0x00000020, + AR9340_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00000040, + + AR9340_INTR_SYNC_DEFAULT = (AR9340_INTR_SYNC_HOST1_FATAL | + AR9340_INTR_SYNC_HOST1_PERR | + AR9340_INTR_SYNC_LOCAL_TIMEOUT | + AR9340_INTR_SYNC_MAC_SLEEP_ACCESS), + + AR9340_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, +}; + +/* Asynchronous Interrupt Mask Register */ +#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 // asynchronous interrupt mask: bits 18..31 +#define AR_INTR_ASYNC_MASK_GPIO_S 18 // asynchronous interrupt mask: bits 18..31 +#define AR_INTR_ASYNC_MASK_MCI 0x00000080 +#define AR_INTR_ASYNC_MASK_MCI_S 7 + +/* Synchronous Interrupt Mask Register */ +#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 // synchronous interrupt mask: bits 18..31 +#define AR_INTR_SYNC_MASK_GPIO_S 18 // synchronous interrupt mask: bits 18..31 + +/* Asynchronous Interrupt Cause Register */ +#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 // GPIO interrupts: bits 18..31 +#define AR_INTR_ASYNC_CAUSE_MCI 0x00000080 +#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO | AR_INTR_ASYNC_CAUSE_MCI) + +/* Asynchronous Interrupt Enable Register */ +#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31 +#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 // enable interrupts: bits 18..31 +#define AR_INTR_ASYNC_ENABLE_MCI 0x00000080 +#define AR_INTR_ASYNC_ENABLE_MCI_S 7 + +/* PCIE PHY Data Register */ + +/* PCIE PHY Load Register */ +#define AR_PCIE_PM_CTRL_ENA 0x00080000 + +#define AR93XX_NUM_GPIO 16 // 0 to 15 + +/* GPIO Output Register */ +#define AR_GPIO_OUT_VAL 0x000FFFF +#define AR_GPIO_OUT_VAL_S 0 + +/* GPIO Input Register */ +#define AR_GPIO_IN_VAL 0x000FFFF +#define AR_GPIO_IN_VAL_S 0 + +/* Host GPIO output enable bits */ +#define AR_GPIO_OE_OUT_DRV 0x3 // 2 bit field mask, shifted by 2*bitpos +#define AR_GPIO_OE_OUT_DRV_NO 0x0 // tristate +#define AR_GPIO_OE_OUT_DRV_LOW 0x1 // drive if low +#define AR_GPIO_OE_OUT_DRV_HI 0x2 // drive if high +#define AR_GPIO_OE_OUT_DRV_ALL 0x3 // drive always + +/* Host GPIO output enable bits */ + +/* Host GPIO Interrupt Polarity */ +#define AR_GPIO_INTR_POL_VAL 0x0001FFFF // bits 16:0 correspond to gpio 16:0 +#define AR_GPIO_INTR_POL_VAL_S 0 // bits 16:0 correspond to gpio 16:0 + +/* Host GPIO Input Value */ +#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 // default value for bt_priority_async +#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 +#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 // default value for bt_frequency_async +#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 +#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 // default value for bt_active_async +#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 +#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 // default value for rfsilent_bb_l +#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 +#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 // 0 == set bt_priority_async to default, 1 == connect bt_prority_async to baseband +#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 +#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB 0x00000800 // 0 == set bt_frequency_async to default, 1 == connect bt_frequency_async to baseband +#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB_S 11 +#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 // 0 == set bt_active_async to default, 1 == connect bt_active_async to baseband +#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 +#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 // 0 == set rfsilent_bb_l to default, 1 == connect rfsilent_bb_l to baseband +#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 +#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 +#define AR_GPIO_JTAG_DISABLE 0x00020000 // 1 == disable JTAG + +/* GPIO Input Mux1 */ +#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 /* bits 8..11: input mux for BT priority input */ +#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 /* bits 8..11: input mux for BT priority input */ +#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY 0x0000f000 /* bits 12..15: input mux for BT frequency input */ +#define AR_GPIO_INPUT_MUX1_BT_FREQUENCY_S 12 /* bits 12..15: input mux for BT frequency input */ +#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 /* bits 16..19: input mux for BT active input */ +#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 /* bits 16..19: input mux for BT active input */ + +/* GPIO Input Mux2 */ +#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f // bits 0..3: input mux for clk25 input +#define AR_GPIO_INPUT_MUX2_CLK25_S 0 // bits 0..3: input mux for clk25 input +#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 // bits 4..7: input mux for rfsilent_bb_l input +#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 // bits 4..7: input mux for rfsilent_bb_l input +#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 // bits 8..11: input mux for RTC Reset input +#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 // bits 8..11: input mux for RTC Reset input + +/* GPIO Output Mux1 */ +/* GPIO Output Mux2 */ +/* GPIO Output Mux3 */ + +#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 +#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 +#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 +#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 +#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 +#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 +#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 +#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 +#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 +#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 +#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 +#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 +#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 +#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 +#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 +#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d +#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e + +#define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0 0x1d +#define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1 0x1e +#define AR_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2 0x1b +/* The above three seems to be functional values for peacock chip. For some + * reason these are continued for different boards as simple place holders. + * Now continuing to use these and adding the extra definitions for Scropion + */ +#define AR_GPIO_OUTPUT_MUX_AS_SWCOM3 0x26 + +#define AR_ENABLE_SMARTANTENNA 0x00000001 + +/* Host GPIO Input State */ + +/* Host Spare */ + +/* Host PCIE Core Reset Enable */ + +/* Host CLKRUN */ + + +/* Host EEPROM Status */ +#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff +#define AR_EEPROM_STATUS_DATA_VAL_S 0 +#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 +#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 +#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 +#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 + +/* Host Observation Control */ + +/* Host RF Silent */ + +/* Host GPIO PDPU */ +#define AR_GPIO_PDPU_OPTION 0x03 +#define AR_GPIO_PULL_DOWN 0x02 + +/* Host GPIO Drive Strength */ + +/* Host Miscellaneous */ + +/* Host PCIE MSI Control Register */ +#define AR_PCIE_MSI_ENABLE 0x00000001 +#define AR_PCIE_MSI_HW_DBI_WR_EN 0x02000000 +#define AR_PCIE_MSI_HW_INT_PENDING_ADDR 0xFFA0C1FF // bits 8..11: value must be 0x5060 +#define AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64 0xFFA0C9FF // bits 8..11: value must be 0x5064 + + +#define AR_INTR_PRIO_TX 0x00000001 +#define AR_INTR_PRIO_RXLP 0x00000002 +#define AR_INTR_PRIO_RXHP 0x00000004 + +/* OTP Interface Register */ +#define AR_ENT_OTP AR9300_HOSTIF_OFFSET(HOST_INTF_OTP) + +#define AR_ENT_OTP_DUAL_BAND_DISABLE 0x00010000 +#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 +#define AR_ENT_OTP_5MHZ_DISABLE 0x00040000 +#define AR_ENT_OTP_10MHZ_DISABLE 0x00080000 +#define AR_ENT_OTP_49GHZ_DISABLE 0x00100000 +#define AR_ENT_OTP_LOOPBACK_DISABLE 0x00200000 +#define AR_ENT_OTP_TPC_PERF_DISABLE 0x00400000 +#define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x00800000 +#define AR_ENT_OTP_SPECTRAL_PRECISION 0x03000000 + +/* OTP EFUSE registers */ +#define AR_OTP_EFUSE_OFFSET(_x) offsetof(struct efuse_reg_WLAN, _x) +#define AR_OTP_EFUSE_INTF0 AR_OTP_EFUSE_OFFSET(OTP_INTF0) +#define AR_OTP_EFUSE_INTF5 AR_OTP_EFUSE_OFFSET(OTP_INTF5) +#define AR_OTP_EFUSE_PGENB_SETUP_HOLD_TIME AR_OTP_EFUSE_OFFSET(OTP_PGENB_SETUP_HOLD_TIME) +#define AR_OTP_EFUSE_MEM AR_OTP_EFUSE_OFFSET(OTP_MEM) + +/****************************************************************************** + * RTC Register Map +******************************************************************************/ + +#define AR_RTC_OFFSET(_x) offsetof(struct rtc_reg, _x) + +/* Reset Control */ +#define AR_RTC_RC AR_RTC_OFFSET(RESET_CONTROL) +#define AR_RTC_RC_M 0x00000003 +#define AR_RTC_RC_MAC_WARM 0x00000001 +#define AR_RTC_RC_MAC_COLD 0x00000002 + +/* Crystal Control */ +#define AR_RTC_XTAL_CONTROL AR_RTC_OFFSET(XTAL_CONTROL) + +/* Reg Control 0 */ +#define AR_RTC_REG_CONTROL0 AR_RTC_OFFSET(REG_CONTROL0) + +/* Reg Control 1 */ +#define AR_RTC_REG_CONTROL1 AR_RTC_OFFSET(REG_CONTROL1) +#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 + +/* TCXO Detect */ +#define AR_RTC_TCXO_DETECT AR_RTC_OFFSET(TCXO_DETECT) + +/* Crystal Test */ +#define AR_RTC_XTAL_TEST AR_RTC_OFFSET(XTAL_TEST) + +/* Sets the ADC/DAC clock quadrature */ +#define AR_RTC_QUADRATURE AR_RTC_OFFSET(QUADRATURE) + +/* PLL Control */ +#define AR_RTC_PLL_CONTROL AR_RTC_OFFSET(PLL_CONTROL) +#define AR_RTC_PLL_DIV 0x000003ff +#define AR_RTC_PLL_DIV_S 0 +#define AR_RTC_PLL_REFDIV 0x00003C00 +#define AR_RTC_PLL_REFDIV_S 10 +#define AR_RTC_PLL_CLKSEL 0x0000C000 +#define AR_RTC_PLL_CLKSEL_S 14 +#define AR_RTC_PLL_BYPASS 0x00010000 +#define AR_RTC_PLL_BYPASS_S 16 + + +/* PLL Control 2: for Hornet */ +#define AR_RTC_PLL_CONTROL2 AR_RTC_OFFSET(PLL_CONTROL2) + +/* PLL Settle */ +#define AR_RTC_PLL_SETTLE AR_RTC_OFFSET(PLL_SETTLE) + +/* Crystal Settle */ +#define AR_RTC_XTAL_SETTLE AR_RTC_OFFSET(XTAL_SETTLE) + +/* Controls CLK_OUT pin clock speed */ +#define AR_RTC_CLOCK_OUT AR_RTC_OFFSET(CLOCK_OUT) + +/* Forces bias block on at all times */ +#define AR_RTC_BIAS_OVERRIDE AR_RTC_OFFSET(BIAS_OVERRIDE) + +/* System Sleep status bits */ +#define AR_RTC_SYSTEM_SLEEP AR_RTC_OFFSET(SYSTEM_SLEEP) + +/* Controls sleep options for MAC */ +#define AR_RTC_MAC_SLEEP_CONTROL AR_RTC_OFFSET(MAC_SLEEP_CONTROL) + +/* Keep Awake Timer */ +#define AR_RTC_KEEP_AWAKE AR_RTC_OFFSET(KEEP_AWAKE) + +/* Create a 32kHz clock derived from HF */ +#define AR_RTC_DERIVED_RTC_CLK AR_RTC_OFFSET(DERIVED_RTC_CLK) + + +/****************************************************************************** + * RTC SYNC Register Map +******************************************************************************/ + +#define AR_RTC_SYNC_OFFSET(_x) offsetof(struct rtc_sync_reg, _x) + +/* reset RTC */ +#define AR_RTC_RESET AR_RTC_SYNC_OFFSET(RTC_SYNC_RESET) +#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ + +/* system sleep status */ +#define AR_RTC_STATUS AR_RTC_SYNC_OFFSET(RTC_SYNC_STATUS) +#define AR_RTC_STATUS_M 0x0000003f +#define AR_RTC_STATUS_SHUTDOWN 0x00000001 +#define AR_RTC_STATUS_ON 0x00000002 +#define AR_RTC_STATUS_SLEEP 0x00000004 +#define AR_RTC_STATUS_WAKEUP 0x00000008 +#define AR_RTC_STATUS_SLEEP_ACCESS 0x00000010 +#define AR_RTC_STATUS_PLL_CHANGING 0x00000020 + +/* RTC Derived Register */ +#define AR_RTC_SLEEP_CLK AR_RTC_SYNC_OFFSET(RTC_SYNC_DERIVED) +#define AR_RTC_FORCE_DERIVED_CLK 0x00000002 +#define AR_RTC_FORCE_SWREG_PRD 0x00000004 +#define AR_RTC_PCIE_RST_PWDN_EN 0x00000008 + +/* RTC Force Wake Register */ +#define AR_RTC_FORCE_WAKE AR_RTC_SYNC_OFFSET(RTC_SYNC_FORCE_WAKE) +#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ +#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ + +/* RTC interrupt cause/clear */ +#define AR_RTC_INTR_CAUSE AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_CAUSE) +/* RTC interrupt enable */ +#define AR_RTC_INTR_ENABLE AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_ENABLE) +/* RTC interrupt mask */ +#define AR_RTC_INTR_MASK AR_RTC_SYNC_OFFSET(RTC_SYNC_INTR_MASK) + + + +/****************************************************************************** + * Analog Interface Register Map +******************************************************************************/ + +#define AR_AN_OFFSET(_x) offsetof(struct analog_intf_reg_csr, _x) + +/* XXX */ +#if 1 +// AR9280: rf long shift registers +#define AR_AN_RF2G1_CH0 0x7810 +#define AR_AN_RF2G1_CH0_OB 0x03800000 +#define AR_AN_RF2G1_CH0_OB_S 23 +#define AR_AN_RF2G1_CH0_DB 0x1C000000 +#define AR_AN_RF2G1_CH0_DB_S 26 + +#define AR_AN_RF5G1_CH0 0x7818 +#define AR_AN_RF5G1_CH0_OB5 0x00070000 +#define AR_AN_RF5G1_CH0_OB5_S 16 +#define AR_AN_RF5G1_CH0_DB5 0x00380000 +#define AR_AN_RF5G1_CH0_DB5_S 19 + +#define AR_AN_RF2G1_CH1 0x7834 +#define AR_AN_RF2G1_CH1_OB 0x03800000 +#define AR_AN_RF2G1_CH1_OB_S 23 +#define AR_AN_RF2G1_CH1_DB 0x1C000000 +#define AR_AN_RF2G1_CH1_DB_S 26 + +#define AR_AN_RF5G1_CH1 0x783C +#define AR_AN_RF5G1_CH1_OB5 0x00070000 +#define AR_AN_RF5G1_CH1_OB5_S 16 +#define AR_AN_RF5G1_CH1_DB5 0x00380000 +#define AR_AN_RF5G1_CH1_DB5_S 19 + +#define AR_AN_TOP2 0x7894 +#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 +#define AR_AN_TOP2_XPABIAS_LVL_S 30 +#define AR_AN_TOP2_LOCALBIAS 0x00200000 +#define AR_AN_TOP2_LOCALBIAS_S 21 +#define AR_AN_TOP2_PWDCLKIND 0x00400000 +#define AR_AN_TOP2_PWDCLKIND_S 22 + +#define AR_AN_SYNTH9 0x7868 +#define AR_AN_SYNTH9_REFDIVA 0xf8000000 +#define AR_AN_SYNTH9_REFDIVA_S 27 + +// AR9285 Analog registers +#define AR9285_AN_RF2G1 0x7820 +#define AR9285_AN_RF2G2 0x7824 + +#define AR9285_AN_RF2G3 0x7828 +#define AR9285_AN_RF2G3_OB_0 0x00E00000 +#define AR9285_AN_RF2G3_OB_0_S 21 +#define AR9285_AN_RF2G3_OB_1 0x001C0000 +#define AR9285_AN_RF2G3_OB_1_S 18 +#define AR9285_AN_RF2G3_OB_2 0x00038000 +#define AR9285_AN_RF2G3_OB_2_S 15 +#define AR9285_AN_RF2G3_OB_3 0x00007000 +#define AR9285_AN_RF2G3_OB_3_S 12 +#define AR9285_AN_RF2G3_OB_4 0x00000E00 +#define AR9285_AN_RF2G3_OB_4_S 9 + +#define AR9285_AN_RF2G3_DB1_0 0x000001C0 +#define AR9285_AN_RF2G3_DB1_0_S 6 +#define AR9285_AN_RF2G3_DB1_1 0x00000038 +#define AR9285_AN_RF2G3_DB1_1_S 3 +#define AR9285_AN_RF2G3_DB1_2 0x00000007 +#define AR9285_AN_RF2G3_DB1_2_S 0 +#define AR9285_AN_RF2G4 0x782C +#define AR9285_AN_RF2G4_DB1_3 0xE0000000 +#define AR9285_AN_RF2G4_DB1_3_S 29 +#define AR9285_AN_RF2G4_DB1_4 0x1C000000 +#define AR9285_AN_RF2G4_DB1_4_S 26 + +#define AR9285_AN_RF2G4_DB2_0 0x03800000 +#define AR9285_AN_RF2G4_DB2_0_S 23 +#define AR9285_AN_RF2G4_DB2_1 0x00700000 +#define AR9285_AN_RF2G4_DB2_1_S 20 +#define AR9285_AN_RF2G4_DB2_2 0x000E0000 +#define AR9285_AN_RF2G4_DB2_2_S 17 +#define AR9285_AN_RF2G4_DB2_3 0x0001C000 +#define AR9285_AN_RF2G4_DB2_3_S 14 +#define AR9285_AN_RF2G4_DB2_4 0x00003800 +#define AR9285_AN_RF2G4_DB2_4_S 11 + +#define AR9285_AN_RF2G6 0x7834 +#define AR9285_AN_RF2G7 0x7838 +#define AR9285_AN_RF2G9 0x7840 +#define AR9285_AN_RXTXBB1 0x7854 +#define AR9285_AN_TOP2 0x7868 + +#define AR9285_AN_TOP3 0x786c +#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C +#define AR9285_AN_TOP3_XPABIAS_LVL_S 2 + +#define AR9285_AN_TOP4 0x7870 +#define AR9285_AN_TOP4_DEFAULT 0x10142c00 +#endif + + +/****************************************************************************** + * MAC PCU Register Map +******************************************************************************/ + +#define AR_MAC_PCU_OFFSET(_x) offsetof(struct mac_pcu_reg, _x) + +/* MAC station ID0 - low 32 bits */ +#define AR_STA_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_STA_ADDR_L32) +/* MAC station ID1 - upper 16 bits */ +#define AR_STA_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_STA_ADDR_U16) +#define AR_STA_ID1_SADH_MASK 0x0000FFFF // Mask for 16 msb of MAC addr +#define AR_STA_ID1_STA_AP 0x00010000 // Device is AP +#define AR_STA_ID1_ADHOC 0x00020000 // Device is ad-hoc +#define AR_STA_ID1_PWR_SAV 0x00040000 // Power save in generated frames +#define AR_STA_ID1_KSRCHDIS 0x00080000 // Key search disable +#define AR_STA_ID1_PCF 0x00100000 // Observe PCF +#define AR_STA_ID1_USE_DEFANT 0x00200000 // Use default antenna +#define AR_STA_ID1_DEFANT_UPDATE 0x00400000 // Update default ant w/TX antenna +#define AR_STA_ID1_RTS_USE_DEF 0x00800000 // Use default antenna to send RTS +#define AR_STA_ID1_ACKCTS_6MB 0x01000000 // Use 6Mb/s rate for ACK & CTS +#define AR_STA_ID1_BASE_RATE_11B 0x02000000 // Use 11b base rate for ACK & CTS +#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 // default ant for generated frames +#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 // Enable Michael +#define AR_STA_ID1_KSRCH_MODE 0x10000000 // Look-up unique key when !keyID +#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 // Don't replace seq num +#define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 // IV endian-ness in CBC nonce +#define AR_STA_ID1_MCAST_KSRCH 0x80000000 // Adhoc key search enable + +/* MAC BSSID low 32 bits */ +#define AR_BSS_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID_L32) +/* MAC BSSID upper 16 bits / AID */ +#define AR_BSS_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID_U16) +#define AR_BSS_ID1_U16 0x0000FFFF // Mask for upper 16 bits of BSSID +#define AR_BSS_ID1_AID 0x07FF0000 // Mask for association ID +#define AR_BSS_ID1_AID_S 16 // Shift for association ID + +/* + * Added to support dual BSSID/TSF which are needed in the application + * of Mesh networking. See bug 35189. Note that the only function added + * with this BSSID2 is to receive multi/broadcast from BSSID2 as well + */ +/* MAC BSSID low 32 bits */ +#define AR_BSS2_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_L32) +/* MAC BSSID upper 16 bits / AID */ +#define AR_BSS2_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_U16) + +/* MAC Beacon average RSSI + * + * This register holds the average RSSI with 1/16 dB resolution. + * The RSSI is averaged over multiple beacons which matched our BSSID. + * Note that AVE_VALUE is 12 bits with 4 bits below the normal 8 bits. + * These lowest 4 bits provide for a resolution of 1/16 dB. + * + */ +#define AR_BCN_RSSI_AVE AR_MAC_PCU_OFFSET(MAC_PCU_BCN_RSSI_AVE) +#define AR_BCN_RSSI_AVE_VAL 0x00000FFF // Beacon RSSI value +#define AR_BCN_RSSI_AVE_VAL_S 0 + +/* MAC ACK & CTS time-out */ +#define AR_TIME_OUT AR_MAC_PCU_OFFSET(MAC_PCU_ACK_CTS_TIMEOUT) +#define AR_TIME_OUT_ACK 0x00003FFF // Mask for ACK time-out +#define AR_TIME_OUT_ACK_S 0 +#define AR_TIME_OUT_CTS 0x3FFF0000 // Mask for CTS time-out +#define AR_TIME_OUT_CTS_S 16 + +/* beacon RSSI warning / bmiss threshold */ +#define AR_RSSI_THR AR_MAC_PCU_OFFSET(MAC_PCU_BCN_RSSI_CTL) +#define AR_RSSI_THR_VAL 0x000000FF // Beacon RSSI warning threshold +#define AR_RSSI_THR_VAL_S 0 +#define AR_RSSI_THR_BM_THR 0x0000FF00 // Mask for Missed beacon threshold +#define AR_RSSI_THR_BM_THR_S 8 // Shift for Missed beacon threshold +#define AR_RSSI_BCN_WEIGHT 0x1F000000 // RSSI average weight +#define AR_RSSI_BCN_WEIGHT_S 24 +#define AR_RSSI_BCN_RSSI_RST 0x20000000 // Reset RSSI value + +/* MAC transmit latency register */ +#define AR_USEC AR_MAC_PCU_OFFSET(MAC_PCU_USEC_LATENCY) +#define AR_USEC_USEC 0x000000FF // Mask for clock cycles in 1 usec +#define AR_USEC_USEC_S 0 // Shift for clock cycles in 1 usec +#define AR_USEC_TX_LAT 0x007FC000 // tx latency to start of SIGNAL (usec) +#define AR_USEC_TX_LAT_S 14 // tx latency to start of SIGNAL (usec) +#define AR_USEC_RX_LAT 0x1F800000 // rx latency to start of SIGNAL (usec) +#define AR_USEC_RX_LAT_S 23 // rx latency to start of SIGNAL (usec) + +#define AR_SLOT_HALF 13 +#define AR_SLOT_QUARTER 21 + +#define AR_USEC_RX_LATENCY 0x1f800000 +#define AR_USEC_RX_LATENCY_S 23 +#define AR_RX_LATENCY_FULL 37 +#define AR_RX_LATENCY_HALF 74 +#define AR_RX_LATENCY_QUARTER 148 +#define AR_RX_LATENCY_FULL_FAST_CLOCK 41 +#define AR_RX_LATENCY_HALF_FAST_CLOCK 82 +#define AR_RX_LATENCY_QUARTER_FAST_CLOCK 163 + +#define AR_USEC_TX_LATENCY 0x007fc000 +#define AR_USEC_TX_LATENCY_S 14 +#define AR_TX_LATENCY_FULL 54 +#define AR_TX_LATENCY_HALF 108 +#define AR_TX_LATENCY_QUARTER 216 +#define AR_TX_LATENCY_FULL_FAST_CLOCK 54 +#define AR_TX_LATENCY_HALF_FAST_CLOCK 119 +#define AR_TX_LATENCY_QUARTER_FAST_CLOCK 238 + +#define AR_USEC_HALF 19 +#define AR_USEC_QUARTER 9 +#define AR_USEC_HALF_FAST_CLOCK 21 +#define AR_USEC_QUARTER_FAST_CLOCK 10 + +#define AR_EIFS_HALF 175 +#define AR_EIFS_QUARTER 340 + +#define AR_RESET_TSF AR_MAC_PCU_OFFSET(MAC_PCU_RESET_TSF) +#define AR_RESET_TSF_ONCE 0x01000000 // reset tsf once ; self-clears bit +#define AR_RESET_TSF2_ONCE 0x02000000 // reset tsf2 once ; self-clears bit + +/* MAC CFP Interval (TU/msec) */ +#define AR_CFP_PERIOD 0x8024 /* MAC CFP Interval (TU/msec) */ +#define AR_TIMER0 0x8028 /* MAC Next beacon time (TU/msec) */ +#define AR_TIMER1 0x802c /* MAC DMA beacon alert time (1/8 TU) */ +#define AR_TIMER2 0x8030 /* MAC Software beacon alert (1/8 TU) */ +#define AR_TIMER3 0x8034 /* MAC ATIM window time */ + +/* MAC maximum CFP duration */ +#define AR_MAX_CFP_DUR AR_MAC_PCU_OFFSET(MAC_PCU_MAX_CFP_DUR) +#define AR_CFP_VAL 0x0000FFFF // CFP value in uS + +/* MAC receive filter register */ +#define AR_RX_FILTER AR_MAC_PCU_OFFSET(MAC_PCU_RX_FILTER) +#define AR_RX_FILTER_ALL 0x00000000 // Disallow all frames +#define AR_RX_UCAST 0x00000001 // Allow unicast frames +#define AR_RX_MCAST 0x00000002 // Allow multicast frames +#define AR_RX_BCAST 0x00000004 // Allow broadcast frames +#define AR_RX_CONTROL 0x00000008 // Allow control frames +#define AR_RX_BEACON 0x00000010 // Allow beacon frames +#define AR_RX_PROM 0x00000020 // Promiscuous mode all packets +#define AR_RX_PROBE_REQ 0x00000080 // Any probe request frameA +#define AR_RX_MY_BEACON 0x00000200 // Any beacon frame with matching BSSID +#define AR_RX_COMPR_BAR 0x00000400 // Compressed directed block ack request +#define AR_RX_COMPR_BA 0x00000800 // Compressed directed block ack +#define AR_RX_UNCOM_BA_BAR 0x00001000 // Uncompressed directed BA or BAR +#define AR_RX_HWBCNPROC_EN 0x00020000 // Enable hw beacon processing (see AR_HWBCNPROC1) +#define AR_RX_CONTROL_WRAPPER 0x00080000 // Control wrapper. Jupiter only. +#define AR_RX_4ADDRESS 0x00100000 // 4-Address frames + +#define AR_PHY_ERR_MASK_REG AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK_CONT) + + +/* MAC multicast filter lower 32 bits */ +#define AR_MCAST_FIL0 AR_MAC_PCU_OFFSET(MAC_PCU_MCAST_FILTER_L32) +/* MAC multicast filter upper 32 bits */ +#define AR_MCAST_FIL1 AR_MAC_PCU_OFFSET(MAC_PCU_MCAST_FILTER_U32) + +/* MAC PCU diagnostic switches */ +#define AR_DIAG_SW AR_MAC_PCU_OFFSET(MAC_PCU_DIAG_SW) +#define AR_DIAG_CACHE_ACK 0x00000001 // disable ACK when no valid key +#define AR_DIAG_ACK_DIS 0x00000002 // disable ACK generation +#define AR_DIAG_CTS_DIS 0x00000004 // disable CTS generation +#define AR_DIAG_ENCRYPT_DIS 0x00000008 // disable encryption +#define AR_DIAG_DECRYPT_DIS 0x00000010 // disable decryption +#define AR_DIAG_RX_DIS 0x00000020 // disable receive +#define AR_DIAG_LOOP_BACK 0x00000040 // enable loopback +#define AR_DIAG_CORR_FCS 0x00000080 // corrupt FCS +#define AR_DIAG_CHAN_INFO 0x00000100 // dump channel info +#define AR_DIAG_FRAME_NV0 0x00020000 // accept w/protocol version !0 +#define AR_DIAG_OBS_PT_SEL1 0x000C0000 // observation point select +#define AR_DIAG_OBS_PT_SEL1_S 18 // Shift for observation point select +#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 // force rx_clear high +#define AR_DIAG_IGNORE_VIRT_CS 0x00200000 // ignore virtual carrier sense +#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 // force channel idle high +#define AR_DIAG_EIFS_CTRL_ENA 0x00800000 // use framed and ~wait_wep if 0 +#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 // dual chain channel info +#define AR_DIAG_RX_ABORT 0x02000000 // abort rx +#define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 // saturate cycle cnts (no shift) +#define AR_DIAG_OBS_PT_SEL2 0x08000000 // Mask for observation point sel +#define AR_DIAG_OBS_PT_SEL2_S 27 +#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 // force rx_clear (ctl) low (i.e. busy) +#define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 // force rx_clear (ext) low (i.e. busy) + +/* MAC local clock lower 32 bits */ +#define AR_TSF_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF_L32) +/* MAC local clock upper 32 bits */ +#define AR_TSF_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF_U32) + +/* + * Secondary TSF support added for dual BSSID/TSF + * which is needed in the application of DirectConnect or + * Mesh networking + */ +/* MAC local clock lower 32 bits */ +#define AR_TSF2_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_L32) +/* MAC local clock upper 32 bits */ +#define AR_TSF2_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_U32) + +/* ADDAC test register */ +#define AR_TST_ADDAC AR_MAC_PCU_OFFSET(MAC_PCU_TST_ADDAC) + +#define AR_TST_ADDAC_TST_MODE 0x1 +#define AR_TST_ADDAC_TST_MODE_S 0 +#define AR_TST_ADDAC_TST_LOOP_ENA 0x2 +#define AR_TST_ADDAC_TST_LOOP_ENA_S 1 +#define AR_TST_ADDAC_BEGIN_CAPTURE 0x80000 +#define AR_TST_ADDAC_BEGIN_CAPTURE_S 19 + +/* default antenna register */ +#define AR_DEF_ANTENNA AR_MAC_PCU_OFFSET(MAC_PCU_DEF_ANTENNA) + +/* MAC AES mute mask */ +#define AR_AES_MUTE_MASK0 AR_MAC_PCU_OFFSET(MAC_PCU_AES_MUTE_MASK_0) +#define AR_AES_MUTE_MASK0_FC 0x0000FFFF // frame ctrl mask bits +#define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 // qos ctrl mask bits +#define AR_AES_MUTE_MASK0_QOS_S 16 + +/* MAC AES mute mask 1 */ +#define AR_AES_MUTE_MASK1 AR_MAC_PCU_OFFSET(MAC_PCU_AES_MUTE_MASK_1) +#define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF // seq + frag mask bits +#define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 // frame ctrl mask for mgmt frames (Sowl) +#define AR_AES_MUTE_MASK1_FC_MGMT_S 16 + +/* control clock domain */ +#define AR_GATED_CLKS AR_MAC_PCU_OFFSET(MAC_PCU_GATED_CLKS) +#define AR_GATED_CLKS_TX 0x00000002 +#define AR_GATED_CLKS_RX 0x00000004 +#define AR_GATED_CLKS_REG 0x00000008 + +/* MAC PCU observation bus 2 */ +#define AR_OBS_BUS_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_OBS_BUS_2) +#define AR_OBS_BUS_SEL_1 0x00040000 +#define AR_OBS_BUS_SEL_2 0x00080000 +#define AR_OBS_BUS_SEL_3 0x000C0000 +#define AR_OBS_BUS_SEL_4 0x08040000 +#define AR_OBS_BUS_SEL_5 0x08080000 + +/* MAC PCU observation bus 1 */ +#define AR_OBS_BUS_1 AR_MAC_PCU_OFFSET(MAC_PCU_OBS_BUS_1) +#define AR_OBS_BUS_1_PCU 0x00000001 +#define AR_OBS_BUS_1_RX_END 0x00000002 +#define AR_OBS_BUS_1_RX_WEP 0x00000004 +#define AR_OBS_BUS_1_RX_BEACON 0x00000008 +#define AR_OBS_BUS_1_RX_FILTER 0x00000010 +#define AR_OBS_BUS_1_TX_HCF 0x00000020 +#define AR_OBS_BUS_1_QUIET_TIME 0x00000040 +#define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 +#define AR_OBS_BUS_1_TX_HOLD 0x00000100 +#define AR_OBS_BUS_1_TX_FRAME 0x00000200 +#define AR_OBS_BUS_1_RX_FRAME 0x00000400 +#define AR_OBS_BUS_1_RX_CLEAR 0x00000800 +#define AR_OBS_BUS_1_WEP_STATE 0x0003F000 +#define AR_OBS_BUS_1_WEP_STATE_S 12 +#define AR_OBS_BUS_1_RX_STATE 0x01F00000 +#define AR_OBS_BUS_1_RX_STATE_S 20 +#define AR_OBS_BUS_1_TX_STATE 0x7E000000 +#define AR_OBS_BUS_1_TX_STATE_S 25 + +/* MAC PCU dynamic MIMO power save */ +#define AR_PCU_SMPS AR_MAC_PCU_OFFSET(MAC_PCU_DYM_MIMO_PWR_SAVE) +#define AR_PCU_SMPS_MAC_CHAINMASK 0x00000001 // Use the Rx Chainmask of MAC's setting +#define AR_PCU_SMPS_HW_CTRL_EN 0x00000002 // Enable hardware control of dynamic MIMO PS +#define AR_PCU_SMPS_SW_CTRL_HPWR 0x00000004 // Software controlled High power chainmask setting +#define AR_PCU_SMPS_LPWR_CHNMSK 0x00000070 // Low power setting of Rx Chainmask +#define AR_PCU_SMPS_LPWR_CHNMSK_S 4 +#define AR_PCU_SMPS_HPWR_CHNMSK 0x00000700 // High power setting of Rx Chainmask +#define AR_PCU_SMPS_HPWR_CHNMSK_S 8 +#define AR_PCU_SMPS_LPWR_CHNMSK_VAL 0x1 + +/* MAC PCU frame start time trigger for the AP's Downlink Traffic in TDMA mode */ +#define AR_TDMA_TXSTARTTRIG_LSB AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB) +#define AR_TDMA_TXSTARTTRIG_MSB AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB) + +/* MAC Time stamp of the last beacon received */ +#define AR_LAST_TSTP AR_MAC_PCU_OFFSET(MAC_PCU_LAST_BEACON_TSF) +/* MAC current NAV value */ +#define AR_NAV AR_MAC_PCU_OFFSET(MAC_PCU_NAV) +/* MAC RTS exchange success counter */ +#define AR_RTS_OK AR_MAC_PCU_OFFSET(MAC_PCU_RTS_SUCCESS_CNT) +/* MAC RTS exchange failure counter */ +#define AR_RTS_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_RTS_FAIL_CNT) +/* MAC ACK failure counter */ +#define AR_ACK_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_ACK_FAIL_CNT) +/* MAC FCS check failure counter */ +#define AR_FCS_FAIL AR_MAC_PCU_OFFSET(MAC_PCU_FCS_FAIL_CNT) +/* MAC Valid beacon value */ +#define AR_BEACON_CNT AR_MAC_PCU_OFFSET(MAC_PCU_BEACON_CNT) + +/* MAC PCU tdma slot alert control */ +#define AR_TDMA_SLOT_ALERT_CNTL AR_MAC_PCU_OFFSET(MAC_PCU_TDMA_SLOT_ALERT_CNTL) + +/* MAC PCU Basic MCS set for MCS 0 to 31 */ +#define AR_BASIC_SET AR_MAC_PCU_OFFSET(MAC_PCU_BASIC_SET) +#define ALL_RATE 0xff + +/* MAC_PCU_ _SEQ */ +#define AR_MGMT_SEQ AR_MAC_PCU_OFFSET(MAC_PCU_MGMT_SEQ) +#define AR_MGMT_SEQ_MIN 0xFFF /* sequence minimum value*/ +#define AR_MGMT_SEQ_MIN_S 0 +#define AR_MIN_HW_SEQ 0 +#define AR_MGMT_SEQ_MAX 0xFFF0000 /* sequence maximum value*/ +#define AR_MGMT_SEQ_MAX_S 16 +#define AR_MAX_HW_SEQ 0xFF +/*MAC PCU Key Cache Antenna 1 */ +#define AR_TX_ANT_1 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_1) +/*MAC PCU Key Cache Antenna 2 */ +#define AR_TX_ANT_2 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_2) +/*MAC PCU Key Cache Antenna 3 */ +#define AR_TX_ANT_3 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_3) +/*MAC PCU Key Cache Antenna 4 */ +#define AR_TX_ANT_4 AR_MAC_PCU_OFFSET(MAC_PCU_TX_ANT_4) + + +/* Extended range mode */ +#define AR_XRMODE AR_MAC_PCU_OFFSET(MAC_PCU_XRMODE) +/* Extended range mode delay */ +#define AR_XRDEL AR_MAC_PCU_OFFSET(MAC_PCU_XRDEL) +/* Extended range mode timeout */ +#define AR_XRTO AR_MAC_PCU_OFFSET(MAC_PCU_XRTO) +/* Extended range mode chirp */ +#define AR_XRCRP AR_MAC_PCU_OFFSET(MAC_PCU_XRCRP) +/* Extended range stomp */ +#define AR_XRSTMP AR_MAC_PCU_OFFSET(MAC_PCU_XRSTMP) + + +/* Enhanced sleep control 1 */ +#define AR_SLEEP1 AR_MAC_PCU_OFFSET(MAC_PCU_SLP1) +#define AR_SLEEP1_ASSUME_DTIM 0x00080000 // Assume DTIM on missed beacon +#define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 // Cab timeout(TU) mask +#define AR_SLEEP1_CAB_TIMEOUT_S 21 // Cab timeout(TU) shift + +/* Enhanced sleep control 2 */ +#define AR_SLEEP2 AR_MAC_PCU_OFFSET(MAC_PCU_SLP2) +#define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 // Beacon timeout(TU) mask +#define AR_SLEEP2_BEACON_TIMEOUT_S 21 // Beacon timeout(TU) shift + +/*MAC_PCU_SELF_GEN_DEFAULT*/ +#define AR_SELFGEN AR_MAC_PCU_OFFSET(MAC_PCU_SELF_GEN_DEFAULT) +#define AR_MMSS 0x00000007 +#define AR_MMSS_S 0 +#define AR_SELFGEN_MMSS_NO RESTRICTION 0 +#define AR_SELFGEN_MMSS_ONEOVER4_us 1 +#define AR_SELFGEN_MMSS_ONEOVER2_us 2 +#define AR_SELFGEN_MMSS_ONE_us 3 +#define AR_SELFGEN_MMSS_TWO_us 4 +#define AR_SELFGEN_MMSS_FOUR_us 5 +#define AR_SELFGEN_MMSS_EIGHT_us 6 +#define AR_SELFGEN_MMSS_SIXTEEN_us 7 + +#define AR_CEC 0x00000018 +#define AR_CEC_S 3 +/* Although in original standard 0 is for 1 stream and 1 is for 2 stream */ +/* due to H/W resaon, Here should set 1 for 1 stream and 2 for 2 stream */ +#define AR_SELFGEN_CEC_ONE_SPACETIMESTREAM 1 +#define AR_SELFGEN_CEC_TWO_SPACETIMESTREAM 2 + +/* BSSID mask lower 32 bits */ +#define AR_BSSMSKL AR_MAC_PCU_OFFSET(MAC_PCU_ADDR1_MASK_L32) +/* BSSID mask upper 16 bits */ +#define AR_BSSMSKU AR_MAC_PCU_OFFSET(MAC_PCU_ADDR1_MASK_U16) + +/* Transmit power control for gen frames */ +#define AR_TPC AR_MAC_PCU_OFFSET(MAC_PCU_TPC) +#define AR_TPC_ACK 0x0000003f // ack frames mask +#define AR_TPC_ACK_S 0x00 // ack frames shift +#define AR_TPC_CTS 0x00003f00 // cts frames mask +#define AR_TPC_CTS_S 0x08 // cts frames shift +#define AR_TPC_CHIRP 0x003f0000 // chirp frames mask +#define AR_TPC_CHIRP_S 16 // chirp frames shift +#define AR_TPC_RPT 0x3f000000 // rpt frames mask +#define AR_TPC_RPT_S 24 // rpt frames shift + +/* Profile count transmit frames */ +#define AR_TFCNT AR_MAC_PCU_OFFSET(MAC_PCU_TX_FRAME_CNT) +/* Profile count receive frames */ +#define AR_RFCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_FRAME_CNT) +/* Profile count receive clear */ +#define AR_RCCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_CLEAR_CNT) +/* Profile count cycle counter */ +#define AR_CCCNT AR_MAC_PCU_OFFSET(MAC_PCU_CYCLE_CNT) + +/* Quiet time programming for TGh */ +#define AR_QUIET1 AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1) +#define AR_QUIET1_NEXT_QUIET_S 0 // TSF of next quiet period (TU) +#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff +#define AR_QUIET1_QUIET_ENABLE 0x00010000 // Enable Quiet time operation +#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 // ack/cts in quiet period +#define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17 +#define AR_QUIET2 AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_2) +#define AR_QUIET2_QUIET_PERIOD_S 0 // Periodicity of quiet period (TU) +#define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff +#define AR_QUIET2_QUIET_DUR_S 16 // quiet period (TU) +#define AR_QUIET2_QUIET_DUR 0xffff0000 + +/* locate no_ack in qos */ +#define AR_QOS_NO_ACK AR_MAC_PCU_OFFSET(MAC_PCU_QOS_NO_ACK) +#define AR_QOS_NO_ACK_TWO_BIT 0x0000000f // 2 bit sentinel for no-ack +#define AR_QOS_NO_ACK_TWO_BIT_S 0 +#define AR_QOS_NO_ACK_BIT_OFF 0x00000070 // offset for no-ack +#define AR_QOS_NO_ACK_BIT_OFF_S 4 +#define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 // from end of header +#define AR_QOS_NO_ACK_BYTE_OFF_S 7 + +/* Phy errors to be filtered */ +#define AR_PHY_ERR AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK) + /* XXX validate! XXX */ +#define AR_PHY_ERR_DCHIRP 0x00000008 // Bit 3 enables double chirp +#define AR_PHY_ERR_RADAR 0x00000020 // Bit 5 is Radar signal +#define AR_PHY_ERR_OFDM_TIMING 0x00020000 // Bit 17 is AH_FALSE detect for OFDM +#define AR_PHY_ERR_CCK_TIMING 0x02000000 // Bit 25 is AH_FALSE detect for CCK + +/* MAC PCU extended range latency */ +#define AR_XRLAT AR_MAC_PCU_OFFSET(MAC_PCU_XRLAT) + +/* MAC PCU Receive Buffer settings */ +#define AR_RXFIFO_CFG AR_MAC_PCU_OFFSET(MAC_PCU_RXBUF) +#define AR_RXFIFO_CFG_REG_RD_ENA_S 11 +#define AR_RXFIFO_CFG_REG_RD_ENA (0x1 << AR_RXFIFO_CFG_REG_RD_ENA_S) + +/* MAC PCU QoS control */ +#define AR_MIC_QOS_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_MIC_QOS_CONTROL) +/* MAC PCU Michael QoS select */ +#define AR_MIC_QOS_SELECT AR_MAC_PCU_OFFSET(MAC_PCU_MIC_QOS_SELECT) + +/* PCU Miscellaneous Mode */ +#define AR_PCU_MISC AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE) +#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 // force bssid to match +#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 // tx/rx mic key are together +#define AR_PCU_TX_ADD_TSF 0x00000008 // add tx_tsf + int_tsf +#define AR_PCU_CCK_SIFS_MODE 0x00000010 // assume 11b sifs programmed +#define AR_PCU_RX_ANT_UPDT 0x00000800 // KC_RX_ANT_UPDATE +#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 // enforce txop / tbtt +#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 // count bmiss's when sleeping +#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 // use rx_clear to count sifs +#define AR_PCU_FORCE_QUIET_COLL 0x00040000 // kill xmit for channel change +#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 +#define AR_PCU_BT_ANT_PREVENT_RX_S 20 +#define AR_PCU_TBTT_PROTECT 0x00200000 // no xmit upto tbtt + 20 uS +#define AR_PCU_CLEAR_VMF 0x01000000 // clear vmf mode (fast cc) +#define AR_PCU_CLEAR_BA_VALID 0x04000000 // clear ba state +#define AR_PCU_SEL_EVM 0x08000000 // select EVM data or PLCP header +#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000 /* always perform key search */ +/* count of filtered ofdm */ +#define AR_FILT_OFDM AR_MAC_PCU_OFFSET(MAC_PCU_FILTER_OFDM_CNT) +#define AR_FILT_OFDM_COUNT 0x00FFFFFF // count of filtered ofdm + +/* count of filtered cck */ +#define AR_FILT_CCK AR_MAC_PCU_OFFSET(MAC_PCU_FILTER_CCK_CNT) +#define AR_FILT_CCK_COUNT 0x00FFFFFF // count of filtered cck + +/* MAC PCU PHY error counter 1 */ +#define AR_PHY_ERR_1 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_1) +#define AR_PHY_ERR_1_COUNT 0x00FFFFFF // phy errs that pass mask_1 +/* MAC PCU PHY error mask 1 */ +#define AR_PHY_ERR_MASK_1 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_1_MASK) + +/* MAC PCU PHY error counter 2 */ +#define AR_PHY_ERR_2 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_2) +#define AR_PHY_ERR_2_COUNT 0x00FFFFFF // phy errs that pass mask_2 +/* MAC PCU PHY error mask 2 */ +#define AR_PHY_ERR_MASK_2 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_2_MASK) + +#define AR_PHY_COUNTMAX (3 << 22) // Max counted before intr +#define AR_MIBCNT_INTRMASK (3 << 22) // Mask top 2 bits of counters + +/* interrupt if rx_tsf-int_tsf */ +#define AR_TSFOOR_THRESHOLD AR_MAC_PCU_OFFSET(MAC_PCU_TSF_THRESHOLD) +#define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF // field width + +/* MAC PCU PHY error counter 3 */ +#define AR_PHY_ERR_3 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_3) +#define AR_PHY_ERR_3_COUNT 0x00FFFFFF // phy errs that pass mask_3 +/* MAC PCU PHY error mask 3 */ +#define AR_PHY_ERR_MASK_3 AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_3_MASK) + +/* Bluetooth coexistance mode */ +#define AR_BT_COEX_MODE AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE) +#define AR_BT_TIME_EXTEND 0x000000ff +#define AR_BT_TIME_EXTEND_S 0 +#define AR_BT_TXSTATE_EXTEND 0x00000100 +#define AR_BT_TXSTATE_EXTEND_S 8 +#define AR_BT_TX_FRAME_EXTEND 0x00000200 +#define AR_BT_TX_FRAME_EXTEND_S 9 +#define AR_BT_MODE 0x00000c00 +#define AR_BT_MODE_S 10 +#define AR_BT_QUIET 0x00001000 +#define AR_BT_QUIET_S 12 +#define AR_BT_QCU_THRESH 0x0001e000 +#define AR_BT_QCU_THRESH_S 13 +#define AR_BT_RX_CLEAR_POLARITY 0x00020000 +#define AR_BT_RX_CLEAR_POLARITY_S 17 +#define AR_BT_PRIORITY_TIME 0x00fc0000 +#define AR_BT_PRIORITY_TIME_S 18 +#define AR_BT_FIRST_SLOT_TIME 0xff000000 +#define AR_BT_FIRST_SLOT_TIME_S 24 + +/* BlueTooth coexistance WLAN weights */ +#define AR_BT_COEX_WL_WEIGHTS0 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_WL_WEIGHTS0) +#define AR_BT_BT_WGHT 0x0000ffff +#define AR_BT_BT_WGHT_S 0 +#define AR_BT_WL_WGHT 0xffff0000 +#define AR_BT_WL_WGHT_S 16 + +/* HCF timeout: Slotted behavior */ +#define AR_HCFTO AR_MAC_PCU_OFFSET(MAC_PCU_HCF_TIMEOUT) + +/* BlueTooth mode 2: Slotted behavior */ +#define AR_BT_COEX_MODE2 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE2) +#define AR_BT_BCN_MISS_THRESH 0x000000ff +#define AR_BT_BCN_MISS_THRESH_S 0 +#define AR_BT_BCN_MISS_CNT 0x0000ff00 +#define AR_BT_BCN_MISS_CNT_S 8 +#define AR_BT_HOLD_RX_CLEAR 0x00010000 +#define AR_BT_HOLD_RX_CLEAR_S 16 +#define AR_BT_SLEEP_ALLOW_BT 0x00020000 +#define AR_BT_SLEEP_ALLOW_BT_S 17 +#define AR_BT_PROTECT_AFTER_WAKE 0x00080000 +#define AR_BT_PROTECT_AFTER_WAKE_S 19 +#define AR_BT_DISABLE_BT_ANT 0x00100000 +#define AR_BT_DISABLE_BT_ANT_S 20 +#define AR_BT_QUIET_2_WIRE 0x00200000 +#define AR_BT_QUIET_2_WIRE_S 21 +#define AR_BT_WL_ACTIVE_MODE 0x00c00000 +#define AR_BT_WL_ACTIVE_MODE_S 22 +#define AR_BT_WL_TXRX_SEPARATE 0x01000000 +#define AR_BT_WL_TXRX_SEPARATE_S 24 +#define AR_BT_RS_DISCARD_EXTEND 0x02000000 +#define AR_BT_RS_DISCARD_EXTEND_S 25 +#define AR_BT_TSF_BT_ACTIVE_CTRL 0x0c000000 +#define AR_BT_TSF_BT_ACTIVE_CTRL_S 26 +#define AR_BT_TSF_BT_PRIORITY_CTRL 0x30000000 +#define AR_BT_TSF_BT_PRIORITY_CTRL_S 28 +#define AR_BT_INTERRUPT_ENABLE 0x40000000 +#define AR_BT_INTERRUPT_ENABLE_S 30 +#define AR_BT_PHY_ERR_BT_COLL_ENABLE 0x80000000 +#define AR_BT_PHY_ERR_BT_COLL_ENABLE_S 31 + +/* Generic Timers 2 */ +#define AR_GEN_TIMERS2_0 AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS2) +#define AR_GEN_TIMERS2_NEXT(_i) (AR_GEN_TIMERS2_0 + ((_i)<<2)) +#define AR_GEN_TIMERS2_PERIOD(_i) (AR_GEN_TIMERS2_NEXT(8) + ((_i)<<2)) + +#define AR_GEN_TIMERS2_0_NEXT AR_GEN_TIMERS2_NEXT(0) +#define AR_GEN_TIMERS2_1_NEXT AR_GEN_TIMERS2_NEXT(1) +#define AR_GEN_TIMERS2_2_NEXT AR_GEN_TIMERS2_NEXT(2) +#define AR_GEN_TIMERS2_3_NEXT AR_GEN_TIMERS2_NEXT(3) +#define AR_GEN_TIMERS2_4_NEXT AR_GEN_TIMERS2_NEXT(4) +#define AR_GEN_TIMERS2_5_NEXT AR_GEN_TIMERS2_NEXT(5) +#define AR_GEN_TIMERS2_6_NEXT AR_GEN_TIMERS2_NEXT(6) +#define AR_GEN_TIMERS2_7_NEXT AR_GEN_TIMERS2_NEXT(7) +#define AR_GEN_TIMERS2_0_PERIOD AR_GEN_TIMERS2_PERIOD(0) +#define AR_GEN_TIMERS2_1_PERIOD AR_GEN_TIMERS2_PERIOD(1) +#define AR_GEN_TIMERS2_2_PERIOD AR_GEN_TIMERS2_PERIOD(2) +#define AR_GEN_TIMERS2_3_PERIOD AR_GEN_TIMERS2_PERIOD(3) +#define AR_GEN_TIMERS2_4_PERIOD AR_GEN_TIMERS2_PERIOD(4) +#define AR_GEN_TIMERS2_5_PERIOD AR_GEN_TIMERS2_PERIOD(5) +#define AR_GEN_TIMERS2_6_PERIOD AR_GEN_TIMERS2_PERIOD(6) +#define AR_GEN_TIMERS2_7_PERIOD AR_GEN_TIMERS2_PERIOD(7) + +#define AR_GEN_TIMER_BANK_1_LEN 8 +#define AR_FIRST_NDP_TIMER 7 +#define AR_NUM_GEN_TIMERS 16 +#define AR_GEN_TIMER_RESERVED 8 + +/* Generic Timers 2 Mode */ +#define AR_GEN_TIMERS2_MODE AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS2_MODE) + +/* BlueTooth coexistance WLAN weights 1 */ +#define AR_BT_COEX_WL_WEIGHTS1 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_WL_WEIGHTS1) + +/* BlueTooth Coexistence TSF Snapshot for BT_ACTIVE */ +#define AR_BT_TSF_ACTIVE AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE) + +/* BlueTooth Coexistence TSF Snapshot for BT_PRIORITY */ +#define AR_BT_TSF_PRIORITY AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY) + +/* SIFS, TX latency and ACK shift */ +#define AR_TXSIFS AR_MAC_PCU_OFFSET(MAC_PCU_TXSIFS) +#define AR_TXSIFS_TIME 0x000000FF // uS in SIFS +#define AR_TXSIFS_TX_LATENCY 0x00000F00 // uS for transmission thru bb +#define AR_TXSIFS_TX_LATENCY_S 8 +#define AR_TXSIFS_ACK_SHIFT 0x00007000 // chan width for ack +#define AR_TXSIFS_ACK_SHIFT_S 12 + +/* BlueTooth mode 3 */ +#define AR_BT_COEX_MODE3 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_MODE3) + + +/* TXOP for legacy non-qos */ +#define AR_TXOP_X AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_X) +#define AR_TXOP_X_VAL 0x000000FF + +/* TXOP for TID 0 to 3 */ +#define AR_TXOP_0_3 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_0_3) +/* TXOP for TID 4 to 7 */ +#define AR_TXOP_4_7 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_4_7) +/* TXOP for TID 8 to 11 */ +#define AR_TXOP_8_11 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_8_11) +/* TXOP for TID 12 to 15 */ +#define AR_TXOP_12_15 AR_MAC_PCU_OFFSET(MAC_PCU_TXOP_12_15) + +/* Generic Timers */ +#define AR_GEN_TIMERS_0 AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS) +#define AR_GEN_TIMERS(_i) (AR_GEN_TIMERS_0 + ((_i)<<2)) + +/* generic timers based on tsf - all uS */ +#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0) +#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1) +#define AR_NEXT_SWBA AR_GEN_TIMERS(2) +#define AR_NEXT_HCF AR_GEN_TIMERS(3) +#define AR_NEXT_TIM AR_GEN_TIMERS(4) +#define AR_NEXT_DTIM AR_GEN_TIMERS(5) +#define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6) +#define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7) +#define AR_BEACON_PERIOD AR_GEN_TIMERS(8) +#define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9) +#define AR_SWBA_PERIOD AR_GEN_TIMERS(10) +#define AR_HCF_PERIOD AR_GEN_TIMERS(11) +#define AR_TIM_PERIOD AR_GEN_TIMERS(12) +#define AR_DTIM_PERIOD AR_GEN_TIMERS(13) +#define AR_QUIET_PERIOD AR_GEN_TIMERS(14) +#define AR_NDP_PERIOD AR_GEN_TIMERS(15) + +/* Generic Timers Mode */ +#define AR_TIMER_MODE AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS_MODE) +#define AR_TBTT_TIMER_EN 0x00000001 +#define AR_DBA_TIMER_EN 0x00000002 +#define AR_SWBA_TIMER_EN 0x00000004 +#define AR_HCF_TIMER_EN 0x00000008 +#define AR_TIM_TIMER_EN 0x00000010 +#define AR_DTIM_TIMER_EN 0x00000020 +#define AR_QUIET_TIMER_EN 0x00000040 +#define AR_NDP_TIMER_EN 0x00000080 +#define AR_TIMER_OVERFLOW_INDEX 0x00000700 +#define AR_TIMER_OVERFLOW_INDEX_S 8 +#define AR_TIMER_THRESH 0xFFFFF000 +#define AR_TIMER_THRESH_S 12 + +#define AR_SLP32_MODE AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_MODE) +#define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF // rising <-> falling edge +#define AR_SLP32_ENA 0x00100000 +#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 // tsf update in progress + +#define AR_SLP32_WAKE AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_WAKE) +#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF // time to wake crystal + +#define AR_SLP32_INC AR_MAC_PCU_OFFSET(MAC_PCU_SLP32_INC) +#define AR_SLP32_TST_INC 0x000FFFFF + +/* Sleep MIB cycle count 32kHz cycles for which mac is asleep */ +#define AR_SLP_CNT AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB1) +#define AR_SLP_CYCLE_CNT 0x8254 // absolute number of 32kHz cycles + +/* Sleep MIB cycle count 2 */ +#define AR_SLP_MIB2 AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB2) + +/* Sleep MIB control status */ +#define AR_SLP_MIB_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_SLP_MIB3) +#define AR_SLP_MIB_CLEAR 0x00000001 // clear pending +#define AR_SLP_MIB_PENDING 0x00000002 // clear counters + +//#ifdef AR9300_EMULATION +// MAC trace buffer registers (emulation only) +#define AR_MAC_PCU_LOGIC_ANALYZER AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER) +#define AR_MAC_PCU_LOGIC_ANALYZER_CTL 0x0000000F +#define AR_MAC_PCU_LOGIC_ANALYZER_HOLD 0x00000001 +#define AR_MAC_PCU_LOGIC_ANALYZER_CLEAR 0x00000002 +#define AR_MAC_PCU_LOGIC_ANALYZER_STATE 0x00000004 +#define AR_MAC_PCU_LOGIC_ANALYZER_ENABLE 0x00000008 +#define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL 0x000000F0 +#define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL_S 4 +#define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR 0x0003FF00 +#define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR_S 8 + +#define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE 0xFFFC0000 +#define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_S 18 +#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20614 0x00040000 +#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 +#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20803 0x40000000 +#define AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996 0x9d500010 +#define AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE 0x9d400010 + +#define AR_MAC_PCU_LOGIC_ANALYZER_32L AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER_32L) +#define AR_MAC_PCU_LOGIC_ANALYZER_16U AR_MAC_PCU_OFFSET(MAC_PCU_LOGIC_ANALYZER_16U) + +#define AR_MAC_PCU_TRACE_REG_START 0xE000 +#define AR_MAC_PCU_TRACE_REG_END 0xFFFC +#define AR_MAC_PCU_TRACE_BUFFER_LENGTH (AR_MAC_PCU_TRACE_REG_END - AR_MAC_PCU_TRACE_REG_START + sizeof(uint32_t)) +//#endif // AR9300_EMULATION + +/* MAC PCU global mode register */ +#define AR_2040_MODE AR_MAC_PCU_OFFSET(MAC_PCU_20_40_MODE) +#define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca + +/* MAC PCU H transfer timeout register */ +#define AR_H_XFER_TIMEOUT AR_MAC_PCU_OFFSET(MAC_PCU_H_XFER_TIMEOUT) +#define AR_EXBF_IMMDIATE_RESP 0x00000040 +#define AR_EXBF_NOACK_NO_RPT 0x00000100 +#define AR_H_XFER_TIMEOUT_COUNT 0xf +#define AR_H_XFER_TIMEOUT_COUNT_S 0 + +/* + * Additional cycle counter. See also AR_CCCNT + * extension channel rx clear count + * counts number of cycles rx_clear (ext) is low (i.e. busy) + * when the MAC is not actively transmitting/receiving + */ +#define AR_EXTRCCNT AR_MAC_PCU_OFFSET(MAC_PCU_RX_CLEAR_DIFF_CNT) + +/* antenna mask for self generated files */ +#define AR_SELFGEN_MASK AR_MAC_PCU_OFFSET(MAC_PCU_SELF_GEN_ANTENNA_MASK) + +/* control registers for block BA control fields */ +#define AR_BA_BAR_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_BA_BAR_CONTROL) + +/* legacy PLCP spoof */ +#define AR_LEG_PLCP_SPOOF AR_MAC_PCU_OFFSET(MAC_PCU_LEGACY_PLCP_SPOOF) + +/* PHY error mask and EIFS mask continued */ +#define AR_PHY_ERR_MASK_CONT AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERROR_MASK_CONT) + +/* MAC PCU transmit timer */ +#define AR_TX_TIMER AR_MAC_PCU_OFFSET(MAC_PCU_TX_TIMER) + +/* MAC PCU transmit buffer control */ +#define AR_PCU_TXBUF_CTRL AR_MAC_PCU_OFFSET(MAC_PCU_TXBUF_CTRL) +#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF +#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 + +/* + * MAC PCU miscellaneous mode 2 + * WAR flags for various bugs, see mac_pcu_reg documentation. + */ +#define AR_PCU_MISC_MODE2 AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE2) +#define AR_PCU_MISC_MODE2_BUG_21532_ENABLE 0x00000001 +#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 /* Decrypt MGT frames using MFP method */ +#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 /* Don't decrypt MGT frames at all */ + +#define AR_BUG_58603_FIX_ENABLE 0x00000008 /* Enable fix for bug 58603. This allows + * the use of AR_AGG_WEP_ENABLE. + */ + +#define AR_PCU_MISC_MODE2_PROM_VC_MODE 0xa148103b /* Enable promiscous in azimuth mode */ + +#define AR_PCU_MISC_MODE2_RESERVED 0x00000038 + +#define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search + * based on both MAC Address and Key ID. + * If bit is 0, then Multicast search is + * based on MAC address only. + * For Merlin and above only. + */ + +#define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 +#define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00 +#define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 +#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000 +#define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature, + * when it is enable, AGG_WEP would takes + * charge of the encryption interface of + * pcu_txsm. + */ +#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 +#define AR_PCU_MISC_MODE2_PROXY_STA 0x01000000 /* see EV 75996 */ +#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 +#define AR_DECOUPLE_DECRYPTION 0x08000000 + +#define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 + +/* MAC PCU Alternate AES QoS mute mask */ +#define AR_ALT_AES_MUTE_MASK AR_MAC_PCU_OFFSET(MAC_PCU_ALT_AES_MUTE_MASK) + +/* Async Fifo registers - debug only */ +#define AR_ASYNC_FIFO_1 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG1) +#define AR_ASYNC_FIFO_2 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG2) +#define AR_ASYNC_FIFO_3 AR_MAC_PCU_OFFSET(ASYNC_FIFO_REG3) + +/* Maps the 16 user priority TID values to Access categories */ +#define AR_TID_TO_AC_MAP AR_MAC_PCU_OFFSET(MAC_PCU_TID_TO_AC) + +/* High Priority Queue Control */ +#define AR_HP_Q_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_HP_QUEUE) + +/* Rx High Priority Queue Control */ +#define AR_HPQ_CONTROL AR_MAC_PCU_OFFSET(MAC_PCU_HP_QUEUE) +#define AR_HPQ_ENABLE 0x00000001 +#define AR_HPQ_MASK_BE 0x00000002 +#define AR_HPQ_MASK_BK 0x00000004 +#define AR_HPQ_MASK_VI 0x00000008 +#define AR_HPQ_MASK_VO 0x00000010 +#define AR_HPQ_UAPSD 0x00000020 +#define AR_HPQ_FRAME_FILTER_0 0x00000040 +#define AR_HPQ_FRAME_BSSID_MATCH_0 0x00000080 +#define AR_HPQ_UAPSD_TRIGGER_EN 0x00100000 + +#define AR_BT_COEX_BT_WEIGHTS0 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS0) +#define AR_BT_COEX_BT_WEIGHTS1 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS1) +#define AR_BT_COEX_BT_WEIGHTS2 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS2) +#define AR_BT_COEX_BT_WEIGHTS3 AR_MAC_PCU_OFFSET(MAC_PCU_BLUETOOTH_BT_WEIGHTS3) + +#define AR_AGC_SATURATION_CNT0 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT0) +#define AR_AGC_SATURATION_CNT1 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT1) +#define AR_AGC_SATURATION_CNT2 AR_MAC_PCU_OFFSET(MAC_PCU_AGC_SATURATION_CNT2) + +/* Hardware beacon processing */ +#define AR_HWBCNPROC1 AR_MAC_PCU_OFFSET(MAC_PCU_HW_BCN_PROC1) +#define AR_HWBCNPROC1_CRC_ENABLE 0x00000001 /* Enable hw beacon processing */ +#define AR_HWBCNPROC1_RESET_CRC 0x00000002 /* Reset the last beacon CRC calculated */ +#define AR_HWBCNPROC1_EXCLUDE_BCN_INTVL 0x00000004 /* Exclude Beacon interval in CRC calculation */ +#define AR_HWBCNPROC1_EXCLUDE_CAP_INFO 0x00000008 /* Exclude Beacon capability information in CRC calculation */ +#define AR_HWBCNPROC1_EXCLUDE_TIM_ELM 0x00000010 /* Exclude Beacon TIM element in CRC calculation */ +#define AR_HWBCNPROC1_EXCLUDE_ELM0 0x00000020 /* Exclude element ID ELM0 in CRC calculation */ +#define AR_HWBCNPROC1_EXCLUDE_ELM1 0x00000040 /* Exclude element ID ELM1 in CRC calculation */ +#define AR_HWBCNPROC1_EXCLUDE_ELM2 0x00000080 /* Exclude element ID ELM2 in CRC calculation */ +#define AR_HWBCNPROC1_ELM0_ID 0x0000FF00 /* Element ID 0 */ +#define AR_HWBCNPROC1_ELM0_ID_S 8 +#define AR_HWBCNPROC1_ELM1_ID 0x00FF0000 /* Element ID 1 */ +#define AR_HWBCNPROC1_ELM1_ID_S 16 +#define AR_HWBCNPROC1_ELM2_ID 0xFF000000 /* Element ID 2 */ +#define AR_HWBCNPROC1_ELM2_ID_S 24 + +#define AR_HWBCNPROC2 AR_MAC_PCU_OFFSET(MAC_PCU_HW_BCN_PROC2) +#define AR_HWBCNPROC2_FILTER_INTERVAL_ENABLE 0x00000001 /* Enable filtering beacons based on filter interval */ +#define AR_HWBCNPROC2_RESET_INTERVAL 0x00000002 /* Reset internal interval counter interval */ +#define AR_HWBCNPROC2_EXCLUDE_ELM3 0x00000004 /* Exclude element ID ELM3 in CRC calculation */ +#define AR_HWBCNPROC2_RSVD 0x000000F8 /* reserved */ +#define AR_HWBCNPROC2_FILTER_INTERVAL 0x0000FF00 /* Filter interval for beacons */ +#define AR_HWBCNPROC2_FILTER_INTERVAL_S 8 +#define AR_HWBCNPROC2_ELM3_ID 0x00FF0000 /* Element ID 3 */ +#define AR_HWBCNPROC2_ELM3_ID_S 16 +#define AR_HWBCNPROC2_RSVD2 0xFF000000 /* reserved */ + +#define AR_MAC_PCU_MISC_MODE3 AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE3) +#define AR_BUG_61936_FIX_ENABLE 0x00000040 /* EV61936 - rx descriptor corruption */ +#define AR_TIME_BASED_DISCARD_EN 0x80000000 +#define AR_TIME_BASED_DISCARD_EN_S 31 + +#define AR_MAC_PCU_GEN_TIMER_TSF_SEL AR_MAC_PCU_OFFSET(MAC_PCU_GENERIC_TIMERS_TSF_SEL) + +#define AR_MAC_PCU_TBD_FILTER AR_MAC_PCU_OFFSET(MAC_PCU_TBD_FILTER) +#define AR_MAC_PCU_USE_WBTIMER_TX_TS 0x00000001 +#define AR_MAC_PCU_USE_WBTIMER_TX_TS_S 0 +#define AR_MAC_PCU_USE_WBTIMER_RX_TS 0x00000002 +#define AR_MAC_PCU_USE_WBTIMER_RX_TS_S 1 + +#define AR_TXBUF_BA AR_MAC_PCU_OFFSET(MAC_PCU_TXBUF_BA) + + +/* MAC Key Cache */ +#define AR_KEYTABLE_0 AR_MAC_PCU_OFFSET(MAC_PCU_KEY_CACHE) +#define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) +#define AR_KEY_CACHE_SIZE 128 +#define AR_RSVD_KEYTABLE_ENTRIES 4 +#define AR_KEY_TYPE 0x00000007 // MAC Key Type Mask +#define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */ +#define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */ +#define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */ +#define AR_KEYTABLE_TYPE_TKIP 0x00000004 /* TKIP and Michael */ +#define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES/OCB 128 bit key */ +#define AR_KEYTABLE_TYPE_CCM 0x00000006 /* AES/CCM 128 bit key */ +#define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */ +#define AR_KEYTABLE_ANT 0x00000008 /* previous transmit antenna */ +#define AR_KEYTABLE_UAPSD 0x000001E0 /* UAPSD AC mask */ +#define AR_KEYTABLE_UAPSD_S 5 +#define AR_KEYTABLE_PWRMGT 0x00000200 /* hw managed PowerMgt bit */ + +#define AR_KEYTABLE_MMSS 0x00001c00 /* remote's MMSS*/ +#define AR_KEYTABLE_MMSS_S 10 +#define AR_KEYTABLE_CEC 0x00006000 /* remote's CEC*/ +#define AR_KEYTABLE_CEC_S 13 +#define AR_KEYTABLE_STAGGED 0x00010000 /* remote's stagged sounding*/ +#define AR_KEYTABLE_STAGGED_S 16 + +#define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */ +#define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */ +#define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */ +#define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */ +#define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */ +#define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */ +#define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) /* key type */ +#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */ +#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */ +#define AR_KEYTABLE_DIR_ACK_BIT 0x00000010 /* Directed ACK bit */ + + + +/* + * MAC WoW Registers. + */ +#define AR_WOW_PATTERN_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW1) +#define AR_WOW_PAT_BACKOFF 0x00000004 +#define AR_WOW_BACK_OFF_SHIFT(x) ((x & 0xf) << 27) /* in usecs */ +#define AR_WOW_MAC_INTR_EN 0x00040000 +#define AR_WOW_MAGIC_EN 0x00010000 +#define AR_WOW_PATTERN_EN(x) ((x & 0xff) << 0) +#define AR_WOW_PATTERN_FOUND_SHIFT 8 +#define AR_WOW_PATTERN_FOUND(x) (x & (0xff << AR_WOW_PATTERN_FOUND_SHIFT)) +#define AR_WOW_PATTERN_FOUND_MASK ((0xff) << AR_WOW_PATTERN_FOUND_SHIFT) +#define AR_WOW_MAGIC_PAT_FOUND 0x00020000 +#define AR_WOW_MAC_INTR 0x00080000 +#define AR_WOW_KEEP_ALIVE_FAIL 0x00100000 +#define AR_WOW_BEACON_FAIL 0x00200000 + + +#define AR_WOW_COUNT_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW2) +#define AR_WOW_AIFS_CNT(x) ((x & 0xff) << 0) +#define AR_WOW_SLOT_CNT(x) ((x & 0xff) << 8) +#define AR_WOW_KEEP_ALIVE_CNT(x) ((x & 0xff) << 16) +/* + * Default values for Wow Configuration for backoff, aifs, slot, keep-alive, etc. + * to be programmed into various registers. + */ +#define AR_WOW_CNT_AIFS_CNT 0x00000022 // AR_WOW_COUNT_REG +#define AR_WOW_CNT_SLOT_CNT 0x00000009 // AR_WOW_COUNT_REG +/* + * Keepalive count applicable for Merlin 2.0 and above. + */ +#define AR_WOW_CNT_KA_CNT 0x00000008 // AR_WOW_COUNT_REG + + +#define AR_WOW_BCN_EN_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_BEACON_FAIL) +#define AR_WOW_BEACON_FAIL_EN 0x00000001 + +#define AR_WOW_BCN_TIMO_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_BEACON) +#define AR_WOW_BEACON_TIMO 0x40000000 /* Valid if BCN_EN is set */ +#define AR_WOW_BEACON_TIMO_MAX 0xFFFFFFFF /* Max. value for Beacon Timeout */ + +#define AR_WOW_KEEP_ALIVE_TIMO_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW3_KEEP_ALIVE) +#define AR_WOW_KEEP_ALIVE_TIMO 0x00007A12 +#define AR_WOW_KEEP_ALIVE_NEVER 0xFFFFFFFF + +#define AR_WOW_KEEP_ALIVE_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_KA) +#define AR_WOW_KEEP_ALIVE_AUTO_DIS 0x00000001 +#define AR_WOW_KEEP_ALIVE_FAIL_DIS 0x00000002 + +#define AR_WOW_US_SCALAR_REG AR_MAC_PCU_OFFSET(PCU_1US) + +#define AR_WOW_KEEP_ALIVE_DELAY_REG AR_MAC_PCU_OFFSET(PCU_KA) +#define AR_WOW_KEEP_ALIVE_DELAY 0x000003E8 // 1 msec + +#define AR_WOW_PATTERN_MATCH_REG AR_MAC_PCU_OFFSET(WOW_EXACT) +#define AR_WOW_PAT_END_OF_PKT(x) ((x & 0xf) << 0) +#define AR_WOW_PAT_OFF_MATCH(x) ((x & 0xf) << 8) + +#define AR_WOW_PATTERN_MATCH_REG_2 AR_MAC_PCU_OFFSET(WOW2_EXACT) +#define AR_WOW_PATTERN_OFF1_REG AR_MAC_PCU_OFFSET(PCU_WOW4) /* Pattern bytes 0 -> 3 */ +#define AR_WOW_PATTERN_OFF2_REG AR_MAC_PCU_OFFSET(PCU_WOW5) /* Pattern bytes 4 -> 7 */ +#define AR_WOW_PATTERN_OFF3_REG AR_MAC_PCU_OFFSET(PCU_WOW6) /* Pattern bytes 8 -> 11 */ +#define AR_WOW_PATTERN_OFF4_REG AR_MAC_PCU_OFFSET(PCU_WOW7) /* Pattern bytes 12 -> 15 */ + +/* start address of the frame in RxBUF */ +#define AR_WOW_RXBUF_START_ADDR AR_MAC_PCU_OFFSET(MAC_PCU_WOW6) + +/* Pattern detect and enable bits */ +#define AR_WOW_PATTERN_DETECT_ENABLE AR_MAC_PCU_OFFSET(MAC_PCU_WOW4) + +/* Rx Abort Enable */ +#define AR_WOW_RX_ABORT_ENABLE AR_MAC_PCU_OFFSET(MAC_PCU_WOW5) + +/* PHY error counter 1, 2, and 3 mask continued */ +#define AR_PHY_ERR_CNT_MASK_CONT AR_MAC_PCU_OFFSET(MAC_PCU_PHY_ERR_CNT_MASK_CONT) + +/* AZIMUTH mode reg can be used for proxySTA */ +#define AR_AZIMUTH_MODE AR_MAC_PCU_OFFSET(MAC_PCU_AZIMUTH_MODE) +#define AR_AZIMUTH_KEY_SEARCH_AD1 0x00000002 +#define AR_AZIMUTH_CTS_MATCH_TX_AD2 0x00000040 +#define AR_AZIMUTH_BA_USES_AD1 0x00000080 +#define AR_AZIMUTH_FILTER_PASS_HOLD 0x00000200 + +/* Length of Pattern Match for Pattern */ +#define AR_WOW_LENGTH1_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH1) +#define AR_WOW_LENGTH2_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH2) +#define AR_WOW_LENGTH3_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH3) +#define AR_WOW_LENGTH4_REG AR_MAC_PCU_OFFSET(MAC_PCU_WOW_LENGTH4) + +#define AR_LOC_CTL_REG AR_MAC_PCU_OFFSET(MAC_PCU_LOCATION_MODE_CONTROL) +#define AR_LOC_TIMER_REG AR_MAC_PCU_OFFSET(MAC_PCU_LOCATION_MODE_TIMER) +#define AR_LOC_CTL_REG_FS 0x1 + +/* Register to enable pattern match for less than 256 bytes packets */ +#define AR_WOW_PATTERN_MATCH_LT_256B_REG AR_MAC_PCU_OFFSET(WOW_PATTERN_MATCH_LESS_THAN_256_BYTES) + + +#define AR_WOW_STATUS(x) (x & (AR_WOW_PATTERN_FOUND_MASK | AR_WOW_MAGIC_PAT_FOUND | \ + AR_WOW_KEEP_ALIVE_FAIL | AR_WOW_BEACON_FAIL)) +#define AR_WOW_CLEAR_EVENTS(x) (x & ~(AR_WOW_PATTERN_EN(0xff) | \ + AR_WOW_MAGIC_EN | AR_WOW_MAC_INTR_EN | AR_WOW_BEACON_FAIL | \ + AR_WOW_KEEP_ALIVE_FAIL)) + + +/* + * Keep it long for Beacon workaround - ensures no AH_FALSE alarm + */ +#define AR_WOW_BMISSTHRESHOLD 0x20 + + +/* WoW - Transmit buffer for keep alive frames */ +#define AR_WOW_TRANSMIT_BUFFER AR_MAC_PCU_OFFSET(MAC_PCU_BUF) +#define AR_WOW_TXBUF(_i) (AR_WOW_TRANSMIT_BUFFER + ((_i)<<2)) + +#define AR_WOW_KA_DESC_WORD2 AR_WOW_TXBUF(0) +#define AR_WOW_KA_DESC_WORD3 AR_WOW_TXBUF(1) +#define AR_WOW_KA_DESC_WORD4 AR_WOW_TXBUF(2) +#define AR_WOW_KA_DESC_WORD5 AR_WOW_TXBUF(3) +#define AR_WOW_KA_DESC_WORD6 AR_WOW_TXBUF(4) +#define AR_WOW_KA_DESC_WORD7 AR_WOW_TXBUF(5) +#define AR_WOW_KA_DESC_WORD8 AR_WOW_TXBUF(6) +#define AR_WOW_KA_DESC_WORD9 AR_WOW_TXBUF(7) +#define AR_WOW_KA_DESC_WORD10 AR_WOW_TXBUF(8) +#define AR_WOW_KA_DESC_WORD11 AR_WOW_TXBUF(9) +#define AR_WOW_KA_DESC_WORD12 AR_WOW_TXBUF(10) +#define AR_WOW_KA_DESC_WORD13 AR_WOW_TXBUF(11) + +/* KA_DATA_WORD = 6 words. Depending on the number of + * descriptor words, it can start at AR_WOW_TXBUF(12) + * or AR_WOW_TXBUF(13) */ + +#define AR_WOW_OFFLOAD_GTK_DATA_START AR_WOW_TXBUF(19) + +#define AR_WOW_KA_DATA_WORD_END_JUPITER AR_WOW_TXBUF(60) + +#define AR_WOW_SW_NULL_PARAMETER AR_WOW_TXBUF(61) +#define AR_WOW_SW_NULL_LONG_PERIOD_MASK 0x0000FFFF +#define AR_WOW_SW_NULL_LONG_PERIOD_MASK_S 0 +#define AR_WOW_SW_NULL_SHORT_PERIOD_MASK 0xFFFF0000 +#define AR_WOW_SW_NULL_SHORT_PERIOD_MASK_S 16 + +#define AR_WOW_OFFLOAD_COMMAND_JUPITER AR_WOW_TXBUF(62) +#define AR_WOW_OFFLOAD_ENA_GTK 0x80000000 +#define AR_WOW_OFFLOAD_ENA_ACER_MAGIC 0x40000000 +#define AR_WOW_OFFLOAD_ENA_STD_MAGIC 0x20000000 +#define AR_WOW_OFFLOAD_ENA_SWKA 0x10000000 +#define AR_WOW_OFFLOAD_ENA_ARP_OFFLOAD 0x08000000 +#define AR_WOW_OFFLOAD_ENA_NS_OFFLOAD 0x04000000 +#define AR_WOW_OFFLOAD_ENA_4WAY_WAKE 0x02000000 +#define AR_WOW_OFFLOAD_ENA_GTK_ERROR_WAKE 0x01000000 +#define AR_WOW_OFFLOAD_ENA_AP_LOSS_WAKE 0x00800000 +#define AR_WOW_OFFLOAD_ENA_BT_SLEEP 0x00080000 +#define AR_WOW_OFFLOAD_ENA_SW_NULL 0x00040000 +#define AR_WOW_OFFLOAD_ENA_HWKA_FAIL 0x00020000 +#define AR_WOW_OFFLOAD_ENA_DEVID_SWAR 0x00010000 + +#define AR_WOW_OFFLOAD_STATUS_JUPITER AR_WOW_TXBUF(63) + +/* WoW Transmit Buffer for patterns */ +#define AR_WOW_TB_PATTERN0 AR_WOW_TXBUF(64) +#define AR_WOW_TB_PATTERN1 AR_WOW_TXBUF(128) +#define AR_WOW_TB_PATTERN2 AR_WOW_TXBUF(192) +#define AR_WOW_TB_PATTERN3 AR_WOW_TXBUF(256) +#define AR_WOW_TB_PATTERN4 AR_WOW_TXBUF(320) +#define AR_WOW_TB_PATTERN5 AR_WOW_TXBUF(384) +#define AR_WOW_TB_PATTERN6 AR_WOW_TXBUF(448) +#define AR_WOW_TB_PATTERN7 AR_WOW_TXBUF(512) +#define AR_WOW_TB_MASK0 AR_WOW_TXBUF(768) +#define AR_WOW_TB_MASK1 AR_WOW_TXBUF(776) +#define AR_WOW_TB_MASK2 AR_WOW_TXBUF(784) +#define AR_WOW_TB_MASK3 AR_WOW_TXBUF(792) +#define AR_WOW_TB_MASK4 AR_WOW_TXBUF(800) +#define AR_WOW_TB_MASK5 AR_WOW_TXBUF(808) +#define AR_WOW_TB_MASK6 AR_WOW_TXBUF(816) +#define AR_WOW_TB_MASK7 AR_WOW_TXBUF(824) + + +#define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START AR_WOW_TXBUF(825) +#define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_START_JUPITER AR_WOW_TXBUF(832) +#define AR_WOW_OFFLOAD_GTK_TXDESC_PARAM_WORDS 4 + +#define AR_WOW_OFFLOAD_GTK_DATA_START_JUPITER AR_WOW_TXBUF(836) +#define AR_WOW_OFFLOAD_GTK_DATA_WORDS_JUPITER 20 + +#define AR_WOW_OFFLOAD_ACER_MAGIC_START AR_WOW_TXBUF(856) +#define AR_WOW_OFFLOAD_ACER_MAGIC_WORDS 2 + +#define AR_WOW_OFFLOAD_ACER_KA0_START AR_WOW_TXBUF(858) +#define AR_WOW_OFFLOAD_ACER_KA0_PERIOD_MS AR_WOW_TXBUF(858) +#define AR_WOW_OFFLOAD_ACER_KA0_SIZE AR_WOW_TXBUF(859) +#define AR_WOW_OFFLOAD_ACER_KA0_DATA AR_WOW_TXBUF(860) +#define AR_WOW_OFFLOAD_ACER_KA0_DATA_WORDS 20 +#define AR_WOW_OFFLOAD_ACER_KA0_WORDS 22 + +#define AR_WOW_OFFLOAD_ACER_KA1_START AR_WOW_TXBUF(880) +#define AR_WOW_OFFLOAD_ACER_KA1_PERIOD_MS AR_WOW_TXBUF(880) +#define AR_WOW_OFFLOAD_ACER_KA1_SIZE AR_WOW_TXBUF(881) +#define AR_WOW_OFFLOAD_ACER_KA1_DATA AR_WOW_TXBUF(882) +#define AR_WOW_OFFLOAD_ACER_KA1_DATA_WORDS 20 +#define AR_WOW_OFFLOAD_ACER_KA1_WORDS 22 + +#define AR_WOW_OFFLOAD_ARP0_START AR_WOW_TXBUF(902) +#define AR_WOW_OFFLOAD_ARP0_VALID AR_WOW_TXBUF(902) +#define AR_WOW_OFFLOAD_ARP0_RMT_IP AR_WOW_TXBUF(903) +#define AR_WOW_OFFLOAD_ARP0_HOST_IP AR_WOW_TXBUF(904) +#define AR_WOW_OFFLOAD_ARP0_MAC_L AR_WOW_TXBUF(905) +#define AR_WOW_OFFLOAD_ARP0_MAC_H AR_WOW_TXBUF(906) +#define AR_WOW_OFFLOAD_ARP0_WORDS 5 + +#define AR_WOW_OFFLOAD_ARP1_START AR_WOW_TXBUF(907) +#define AR_WOW_OFFLOAD_ARP1_VALID AR_WOW_TXBUF(907) +#define AR_WOW_OFFLOAD_ARP1_RMT_IP AR_WOW_TXBUF(908) +#define AR_WOW_OFFLOAD_ARP1_HOST_IP AR_WOW_TXBUF(909) +#define AR_WOW_OFFLOAD_ARP1_MAC_L AR_WOW_TXBUF(910) +#define AR_WOW_OFFLOAD_ARP1_MAC_H AR_WOW_TXBUF(911) +#define AR_WOW_OFFLOAD_ARP1_WORDS 5 + +#define AR_WOW_OFFLOAD_NS0_START AR_WOW_TXBUF(912) +#define AR_WOW_OFFLOAD_NS0_VALID AR_WOW_TXBUF(912) +#define AR_WOW_OFFLOAD_NS0_RMT_IPV6 AR_WOW_TXBUF(913) +#define AR_WOW_OFFLOAD_NS0_SOLICIT_IPV6 AR_WOW_TXBUF(917) +#define AR_WOW_OFFLOAD_NS0_MAC_L AR_WOW_TXBUF(921) +#define AR_WOW_OFFLOAD_NS0_MAC_H AR_WOW_TXBUF(922) +#define AR_WOW_OFFLOAD_NS0_TGT0_IPV6 AR_WOW_TXBUF(923) +#define AR_WOW_OFFLOAD_NS0_TGT1_IPV6 AR_WOW_TXBUF(927) +#define AR_WOW_OFFLOAD_NS0_WORDS 19 + +#define AR_WOW_OFFLOAD_NS1_START AR_WOW_TXBUF(931) +#define AR_WOW_OFFLOAD_NS1_VALID AR_WOW_TXBUF(931) +#define AR_WOW_OFFLOAD_NS1_RMT_IPV6 AR_WOW_TXBUF(932) +#define AR_WOW_OFFLOAD_NS1_SOLICIT_IPV6 AR_WOW_TXBUF(936) +#define AR_WOW_OFFLOAD_NS1_MAC_L AR_WOW_TXBUF(940) +#define AR_WOW_OFFLOAD_NS1_MAC_H AR_WOW_TXBUF(941) +#define AR_WOW_OFFLOAD_NS1_TGT0_IPV6 AR_WOW_TXBUF(942) +#define AR_WOW_OFFLOAD_NS1_TGT1_IPV6 AR_WOW_TXBUF(946) +#define AR_WOW_OFFLOAD_NS1_WORDS 19 + +#define AR_WOW_OFFLOAD_WLAN_REGSET_START AR_WOW_TXBUF(950) +#define AR_WOW_OFFLOAD_WLAN_REGSET_NUM AR_WOW_TXBUF(950) +#define AR_WOW_OFFLOAD_WLAN_REGSET_REGVAL AR_WOW_TXBUF(951) +#define AR_WOW_OFFLOAD_WLAN_REGSET_MAX_PAIR 32 +#define AR_WOW_OFFLOAD_WLAN_REGSET_WORDS 65 //(1 + AR_WOW_OFFLOAD_WLAN_REGSET_MAX_PAIR * 2) + +/* Currently Pattern 0-7 are supported - so bit 0-7 are set */ +#define AR_WOW_PATTERN_SUPPORTED 0xFF +#define AR_WOW_LENGTH_MAX 0xFF +#define AR_WOW_LENGTH1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3) +#define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LENGTH1_SHIFT(_i)) +#define AR_WOW_LENGTH2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3) +#define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LENGTH2_SHIFT(_i)) + +/* + * MAC Direct Connect registers + * + * Added to support dual BSSID/TSF which are needed in the application + * of Mesh networking or Direct Connect. + */ + +/* + * Note that the only function added with this BSSID2 is to receive + * multi/broadcast from BSSID2 as well + */ +/* MAC BSSID low 32 bits */ +#define AR_BSS2_ID0 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_L32) +/* MAC BSSID upper 16 bits / AID */ +#define AR_BSS2_ID1 AR_MAC_PCU_OFFSET(MAC_PCU_BSSID2_U16) + +/* + * Secondary TSF support added for dual BSSID/TSF + */ +/* MAC local clock lower 32 bits */ +#define AR_TSF2_L32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_L32) +/* MAC local clock upper 32 bits */ +#define AR_TSF2_U32 AR_MAC_PCU_OFFSET(MAC_PCU_TSF2_U32) + +/* MAC Direct Connect Control */ +#define AR_DIRECT_CONNECT AR_MAC_PCU_OFFSET(MAC_PCU_DIRECT_CONNECT) +#define AR_DC_AP_STA_EN 0x00000001 +#define AR_DC_AP_STA_EN_S 0 + +/* + * tx_bf Register + */ +#define AR_SVD_OFFSET(_x) offsetof(struct svd_reg, _x) + +#define AR_TXBF_DBG AR_SVD_OFFSET(TXBF_DBG) + +#define AR_TXBF AR_SVD_OFFSET(TXBF) +#define AR_TXBF_CB_TX 0x00000003 +#define AR_TXBF_CB_TX_S 0 +#define AR_TXBF_PSI_1_PHI_3 0 +#define AR_TXBF_PSI_2_PHI_4 1 +#define AR_TXBF_PSI_3_PHI_5 2 +#define AR_TXBF_PSI_4_PHI_6 3 + +#define AR_TXBF_NB_TX 0x0000000C +#define AR_TXBF_NB_TX_S 2 +#define AR_TXBF_NUMBEROFBIT_4 0 +#define AR_TXBF_NUMBEROFBIT_2 1 +#define AR_TXBF_NUMBEROFBIT_6 2 +#define AR_TXBF_NUMBEROFBIT_8 3 + +#define AR_TXBF_NG_RPT_TX 0x00000030 +#define AR_TXBF_NG_RPT_TX_S 4 +#define AR_TXBF_No_GROUP 0 +#define AR_TXBF_TWO_GROUP 1 +#define AR_TXBF_FOUR_GROUP 2 + +#define AR_TXBF_NG_CVCACHE 0x000000C0 +#define AR_TXBF_NG_CVCACHE_S 6 +#define AR_TXBF_FOUR_CLIENTS 0 +#define AR_TXBF_EIGHT_CLIENTS 1 +#define AR_TXBF_SIXTEEN_CLIENTS 2 + +#define AR_TXBF_TXCV_BFWEIGHT_METHOD 0x00000600 +#define AR_TXBF_TXCV_BFWEIGHT_METHOD_S 9 +#define AR_TXBF_NO_WEIGHTING 0 +#define AR_TXBF_MAX_POWER 1 +#define AR_TXBF_KEEP_RATIO 2 + +#define AR_TXBF_RLR_EN 0x00000800 +#define AR_TXBF_RC_20_U_DONE 0x00001000 +#define AR_TXBF_RC_20_L_DONE 0x00002000 +#define AR_TXBF_RC_40_DONE 0x00004000 +#define AR_TXBF_FORCE_UPDATE_V2BB 0x00008000 + +#define AR_TXBF_TIMER AR_SVD_OFFSET(TXBF_TIMER) +#define AR_TXBF_TIMER_TIMEOUT 0x000000FF +#define AR_TXBF_TIMER_TIMEOUT_S 0 +#define AR_TXBF_TIMER_ATIMEOU 0x0000FF00 +#define AR_TXBF_TIMER_ATIMEOUT_S 8 + +/* for SVD cache update */ +#define AR_TXBF_SW AR_SVD_OFFSET(TXBF_SW) +#define AR_LRU_ACK 0x00000001 +#define AR_LRU_ADDR 0x000003FE +#define AR_LRU_ADDR_S 1 +#define AR_LRU_EN 0x00000800 +#define AR_LRU_EN_S 11 +#define AR_DEST_IDX 0x0007f000 +#define AR_DEST_IDX_S 12 +#define AR_LRU_WR_ACK 0x00080000 +#define AR_LRU_WR_ACK_S 19 +#define AR_LRU_RD_ACK 0x00100000 +#define AR_LRU_RD_ACK_S 20 + +#define AR_RC0_0 AR_SVD_OFFSET(RC0) +#define AR_RC0(_idx) (AR_RC0_0+(_idx)) +#define AR_RC1_0 AR_SVD_OFFSET(RC1) +#define AR_RC1(_idx) (AR_RC1_0+(_idx)) + +#define AR_CVCACHE_0 AR_SVD_OFFSET(CVCACHE) +#define AR_CVCACHE(_idx) (AR_CVCACHE_0+(_idx)) +/* for CV CACHE Header */ +#define AR_CVCACHE_Ng_IDX 0x0000C000 +#define AR_CVCACHE_Ng_IDX_S 14 +#define AR_CVCACHE_BW40 0x00010000 +#define AR_CVCACHE_BW40_S 16 +#define AR_CVCACHE_IMPLICIT 0x00020000 +#define AR_CVCACHE_IMPLICIT_S 17 +#define AR_CVCACHE_DEST_IDX 0x01FC0000 +#define AR_CVCACHE_DEST_IDX_S 18 +#define AR_CVCACHE_Nc_IDX 0x06000000 +#define AR_CVCACHE_Nc_IDX_S 25 +#define AR_CVCACHE_Nr_IDX 0x18000000 +#define AR_CVCACHE_Nr_IDX_S 27 +#define AR_CVCACHE_EXPIRED 0x20000000 +#define AR_CVCACHE_EXPIRED_S 29 +#define AR_CVCACHE_WRITE 0x80000000 +/* for CV cache data*/ +#define AR_CVCACHE_RD_EN 0x40000000 +#define AR_CVCACHE_DATA 0x3fffffff +/* + * ANT DIV setting + */ +#define ANT_DIV_CONTROL_ALL (0x7e000000) +#define ANT_DIV_CONTROL_ALL_S (25) +#define ANT_DIV_ENABLE (0x1000000) +#define ANT_DIV_ENABLE_S (24) +#define FAST_DIV_ENABLE (0x2000) +#define FAST_DIV_ENABLE_S (13) + +/* Global register */ +#define AR_GLB_REG_OFFSET(_x) offsetof(struct wlan_bt_glb_reg_pcie, _x) + +#define AR_MBOX_CTRL_STATUS AR_GLB_REG_OFFSET(GLB_MBOX_CONTROL_STATUS) +#define AR_MBOX_INT_EMB_CPU 0x0001 +#define AR_MBOX_INT_WLAN 0x0002 +#define AR_MBOX_RESET 0x0004 +#define AR_MBOX_RAM_REQ_MASK 0x0018 +#define AR_MBOX_RAM_REQ_NO_RAM 0x0000 +#define AR_MBOX_RAM_REQ_USB 0x0008 +#define AR_MBOX_RAM_REQ_WLAN_BUF 0x0010 +#define AR_MBOX_RAM_REQ_PATCH_REAPPY 0x0018 +#define AR_MBOX_RAM_CONF 0x0020 +#define AR_MBOX_WLAN_BUF 0x0040 +#define AR_MBOX_WOW_REQ 0x0080 +#define AR_MBOX_WOW_CONF 0x0100 +#define AR_MBOX_WOW_ERROR_MASK 0x1e00 +#define AR_MBOX_WOW_ERROR_NONE 0x0000 +#define AR_MBOX_WOW_ERROR_INVALID_MSG 0x0200 +#define AR_MBOX_WOW_ERROR_MALFORMED_MSG 0x0400 +#define AR_MBOX_WOW_ERROR_INVALID_RAM_IMAGE 0x0600 + +#define AR_WLAN_WOW_STATUS AR_GLB_REG_OFFSET(GLB_WLAN_WOW_STATUS) + +#define AR_WLAN_WOW_ENABLE AR_GLB_REG_OFFSET(GLB_WLAN_WOW_ENABLE) + +#define AR_EMB_CPU_WOW_STATUS AR_GLB_REG_OFFSET(GLB_EMB_CPU_WOW_STATUS) +#define AR_EMB_CPU_WOW_STATUS_KEEP_ALIVE_FAIL 0x1 +#define AR_EMB_CPU_WOW_STATUS_BEACON_MISS 0x2 +#define AR_EMB_CPU_WOW_STATUS_PATTERN_MATCH 0x4 +#define AR_EMB_CPU_WOW_STATUS_MAGIC_PATTERN 0x8 + +#define AR_EMB_CPU_WOW_ENABLE AR_GLB_REG_OFFSET(GLB_EMB_CPU_WOW_ENABLE) +#define AR_EMB_CPU_WOW_ENABLE_KEEP_ALIVE_FAIL 0x1 +#define AR_EMB_CPU_WOW_ENABLE_BEACON_MISS 0x2 +#define AR_EMB_CPU_WOW_ENABLE_PATTERN_MATCH 0x4 +#define AR_EMB_CPU_WOW_ENABLE_MAGIC_PATTERN 0x8 + +#define AR_SW_WOW_CONTROL AR_GLB_REG_OFFSET(GLB_SW_WOW_CONTROL) +#define AR_SW_WOW_ENABLE 0x1 +#define AR_SWITCH_TO_REFCLK 0x2 +#define AR_RESET_CONTROL 0x4 +#define AR_RESET_VALUE_MASK 0x8 +#define AR_HW_WOW_DISABLE 0x10 +#define AR_CLR_MAC_INTERRUPT 0x20 +#define AR_CLR_KA_INTERRUPT 0x40 + +/* + * WLAN coex registers + */ +#define AR_WLAN_COEX_OFFSET(_x) offsetof(struct wlan_coex_reg, _x) + +#define AR_MCI_COMMAND0 AR_WLAN_COEX_OFFSET(MCI_COMMAND0) +#define AR_MCI_COMMAND0_HEADER 0xFF +#define AR_MCI_COMMAND0_HEADER_S 0 +#define AR_MCI_COMMAND0_LEN 0x1f00 +#define AR_MCI_COMMAND0_LEN_S 8 +#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000 +#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13 + +#define AR_MCI_COMMAND1 AR_WLAN_COEX_OFFSET(MCI_COMMAND1) + +#define AR_MCI_COMMAND2 AR_WLAN_COEX_OFFSET(MCI_COMMAND2) +#define AR_MCI_COMMAND2_RESET_TX 0x01 +#define AR_MCI_COMMAND2_RESET_TX_S 0 +#define AR_MCI_COMMAND2_RESET_RX 0x02 +#define AR_MCI_COMMAND2_RESET_RX_S 1 +#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC +#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 2 +#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400 +#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 10 + +#define AR_MCI_RX_CTRL AR_WLAN_COEX_OFFSET(MCI_RX_CTRL) + +#define AR_MCI_TX_CTRL AR_WLAN_COEX_OFFSET(MCI_TX_CTRL) +/* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */ +#define AR_MCI_TX_CTRL_CLK_DIV 0x03 +#define AR_MCI_TX_CTRL_CLK_DIV_S 0 +#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04 +#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2 +#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8 +#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3 +#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000 +#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24 + +#define AR_MCI_MSG_ATTRIBUTES_TABLE AR_WLAN_COEX_OFFSET(MCI_MSG_ATTRIBUTES_TABLE) +#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF +#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0 +#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000 +#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16 + +#define AR_MCI_SCHD_TABLE_0 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_0) +#define AR_MCI_SCHD_TABLE_1 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_1) +#define AR_MCI_GPM_0 AR_WLAN_COEX_OFFSET(MCI_GPM_0) +#define AR_MCI_GPM_1 AR_WLAN_COEX_OFFSET(MCI_GPM_1) +#define AR_MCI_GPM_WRITE_PTR 0xFFFF0000 +#define AR_MCI_GPM_WRITE_PTR_S 16 +#define AR_MCI_GPM_BUF_LEN 0x0000FFFF +#define AR_MCI_GPM_BUF_LEN_S 0 + +#define AR_MCI_INTERRUPT_RAW AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RAW) +#define AR_MCI_INTERRUPT_EN AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_EN) +#define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 +#define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0 +#define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 +#define AR_MCI_INTERRUPT_CPU_INT_MSG_S 1 +#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004 +#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 2 +#define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 +#define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 3 +#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 +#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 4 +#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 +#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 5 +#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 +#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 7 +#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 +#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 8 +#define AR_MCI_INTERRUPT_RX_MSG 0x00000200 +#define AR_MCI_INTERRUPT_RX_MSG_S 9 +#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 +#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 10 +#define AR_MCI_INTERRUPT_BT_PRI 0x07fff800 +#define AR_MCI_INTERRUPT_BT_PRI_S 11 +#define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000 +#define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27 +#define AR_MCI_INTERRUPT_BT_FREQ 0x10000000 +#define AR_MCI_INTERRUPT_BT_FREQ_S 28 +#define AR_MCI_INTERRUPT_BT_STOMP 0x20000000 +#define AR_MCI_INTERRUPT_BT_STOMP_S 29 +#define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000 +#define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30 +#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 +#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31 + +#define AR_MCI_INTERRUPT_MSG_FAIL_MASK ( AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ + AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ + AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ + AR_MCI_INTERRUPT_TX_SW_MSG_FAIL ) + +#define AR_MCI_INTERRUPT_DEFAULT ( AR_MCI_INTERRUPT_SW_MSG_DONE | \ + AR_MCI_INTERRUPT_RX_INVALID_HDR | \ + AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ + AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ + AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ + AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \ + AR_MCI_INTERRUPT_RX_MSG | \ + AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \ + AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT ) + +#define AR_MCI_REMOTE_CPU_INT AR_WLAN_COEX_OFFSET(MCI_REMOTE_CPU_INT) +#define AR_MCI_REMOTE_CPU_INT_EN AR_WLAN_COEX_OFFSET(MCI_REMOTE_CPU_INT_EN) + +#define AR_MCI_INTERRUPT_RX_MSG_RAW AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RX_MSG_RAW) +#define AR_MCI_INTERRUPT_RX_MSG_EN AR_WLAN_COEX_OFFSET(MCI_INTERRUPT_RX_MSG_EN) +#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 +#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0 +#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 +#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1 +#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 +#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2 +#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 +#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3 +#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 +#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4 +#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 +#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5 +#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 +#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6 +#define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 +#define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8 +#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 +#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9 +#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 +#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10 +#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 +#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11 +#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 +#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12 +#ifdef AH_DEBUG +#define AR_MCI_INTERRUPT_RX_MSG_DEFAULT ( AR_MCI_INTERRUPT_RX_MSG_GPM | \ + AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | \ + AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ + AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | \ + AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ + AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ + AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ + AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ + AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ + AR_MCI_INTERRUPT_RX_MSG_CONT_RST | \ + AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE ) +#else +#define AR_MCI_INTERRUPT_RX_MSG_DEFAULT ( AR_MCI_INTERRUPT_RX_MSG_GPM | \ + AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | \ + AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ + AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | \ + AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE ) +#endif +#define AR_MCI_INTERRUPT_RX_HW_MSG_MASK ( AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ + AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ + AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ + AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ + AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ + AR_MCI_INTERRUPT_RX_MSG_CONT_RST ) + +#define AR_MCI_CPU_INT AR_WLAN_COEX_OFFSET(MCI_CPU_INT) + +#define AR_MCI_RX_STATUS AR_WLAN_COEX_OFFSET(MCI_RX_STATUS) +#define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00 +#define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8 +#define AR_MCI_RX_REMOTE_SLEEP 0x00001000 +#define AR_MCI_RX_REMOTE_SLEEP_S 12 +#define AR_MCI_RX_MCI_CLK_REQ 0x00002000 +#define AR_MCI_RX_MCI_CLK_REQ_S 13 + +#define AR_MCI_CONT_STATUS AR_WLAN_COEX_OFFSET(MCI_CONT_STATUS) +#define AR_MCI_CONT_RSSI_POWER 0x000000FF +#define AR_MCI_CONT_RSSI_POWER_S 0 +#define AR_MCI_CONT_RRIORITY 0x0000FF00 +#define AR_MCI_CONT_RRIORITY_S 8 +#define AR_MCI_CONT_TXRX 0x00010000 +#define AR_MCI_CONT_TXRX_S 16 + +#define AR_MCI_BT_PRI0 AR_WLAN_COEX_OFFSET(MCI_BT_PRI0) +#define AR_MCI_BT_PRI1 AR_WLAN_COEX_OFFSET(MCI_BT_PRI1) +#define AR_MCI_BT_PRI2 AR_WLAN_COEX_OFFSET(MCI_BT_PRI2) +#define AR_MCI_BT_PRI3 AR_WLAN_COEX_OFFSET(MCI_BT_PRI3) +#define AR_MCI_BT_PRI AR_WLAN_COEX_OFFSET(MCI_BT_PRI) +#define AR_MCI_WL_FREQ0 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ0) +#define AR_MCI_WL_FREQ1 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ1) +#define AR_MCI_WL_FREQ2 AR_WLAN_COEX_OFFSET(MCI_WL_FREQ2) +#define AR_MCI_GAIN AR_WLAN_COEX_OFFSET(MCI_GAIN) +#define AR_MCI_WBTIMER1 AR_WLAN_COEX_OFFSET(MCI_WBTIMER1) +#define AR_MCI_WBTIMER2 AR_WLAN_COEX_OFFSET(MCI_WBTIMER2) +#define AR_MCI_WBTIMER3 AR_WLAN_COEX_OFFSET(MCI_WBTIMER3) +#define AR_MCI_WBTIMER4 AR_WLAN_COEX_OFFSET(MCI_WBTIMER4) +#define AR_MCI_MAXGAIN AR_WLAN_COEX_OFFSET(MCI_MAXGAIN) +#define AR_MCI_HW_SCHD_TBL_CTL AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_CTL) +#define AR_MCI_HW_SCHD_TBL_D0 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D0) +#define AR_MCI_HW_SCHD_TBL_D1 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D1) +#define AR_MCI_HW_SCHD_TBL_D2 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D2) +#define AR_MCI_HW_SCHD_TBL_D3 AR_WLAN_COEX_OFFSET(MCI_HW_SCHD_TBL_D3) +#define AR_MCI_TX_PAYLOAD0 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD0) +#define AR_MCI_TX_PAYLOAD1 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD1) +#define AR_MCI_TX_PAYLOAD2 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD2) +#define AR_MCI_TX_PAYLOAD3 AR_WLAN_COEX_OFFSET(MCI_TX_PAYLOAD3) +#define AR_BTCOEX_WBTIMER AR_WLAN_COEX_OFFSET(BTCOEX_WBTIMER) + +#define AR_BTCOEX_CTRL AR_WLAN_COEX_OFFSET(BTCOEX_CTRL) +#define AR_BTCOEX_CTRL_JUPITER_MODE 0x00000001 +#define AR_BTCOEX_CTRL_JUPITER_MODE_S 0 +#define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002 +#define AR_BTCOEX_CTRL_WBTIMER_EN_S 1 +#define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004 +#define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2 +#define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008 +#define AR_BTCOEX_CTRL_LNA_SHARED_S 3 +#define AR_BTCOEX_CTRL_PA_SHARED 0x00000010 +#define AR_BTCOEX_CTRL_PA_SHARED_S 4 +#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020 +#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5 +#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040 +#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6 +#define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180 +#define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7 +#define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00 +#define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9 +#define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000 +#define AR_BTCOEX_CTRL_AGGR_THRESH_S 12 +#define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000 +#define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19 +#define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000 +#define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20 +#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000 +#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28 +#define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000 +#define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29 +#define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000 +#define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30 +#define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000 +#define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31 + +#define AR_BTCOEX_WL_WEIGHTS0 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS0) +#define AR_BTCOEX_WL_WEIGHTS1 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS1) +#define AR_BTCOEX_WL_WEIGHTS2 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS2) +#define AR_BTCOEX_WL_WEIGHTS3 AR_WLAN_COEX_OFFSET(BTCOEX_WL_WEIGHTS3) +#define AR_BTCOEX_MAX_TXPWR(_x) (AR_WLAN_COEX_OFFSET(BTCOEX_MAX_TXPWR) + ((_x) << 2)) +#define AR_BTCOEX_WL_LNA AR_WLAN_COEX_OFFSET(BTCOEX_WL_LNA) +#define AR_BTCOEX_RFGAIN_CTRL AR_WLAN_COEX_OFFSET(BTCOEX_RFGAIN_CTRL) + +#define AR_BTCOEX_CTRL2 AR_WLAN_COEX_OFFSET(BTCOEX_CTRL2) +#define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800 +#define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11 +#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000 +#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19 +#define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000 +#define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22 +#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000 +#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23 +#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000 +#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24 +#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000 +#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25 + +#define AR_BTCOEX_RC AR_WLAN_COEX_OFFSET(BTCOEX_RC) +#define AR_BTCOEX_MAX_RFGAIN(_x) AR_WLAN_COEX_OFFSET(BTCOEX_MAX_RFGAIN[_x]) +#define AR_BTCOEX_DBG AR_WLAN_COEX_OFFSET(BTCOEX_DBG) +#define AR_MCI_LAST_HW_MSG_HDR AR_WLAN_COEX_OFFSET(MCI_LAST_HW_MSG_HDR) +#define AR_MCI_LAST_HW_MSG_BDY AR_WLAN_COEX_OFFSET(MCI_LAST_HW_MSG_BDY) + +#define AR_MCI_SCHD_TABLE_2 AR_WLAN_COEX_OFFSET(MCI_SCHD_TABLE_2) +#define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001 +#define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0 +#define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002 +#define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1 + +#define AR_BTCOEX_CTRL3 AR_WLAN_COEX_OFFSET(BTCOEX_CTRL3) +#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000FFF +#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0 + +/****************************************************************************** + * WLAN BT Global Register Map +******************************************************************************/ +#define AR_WLAN_BT_GLB_OFFSET(_x) offsetof(struct wlan_bt_glb_reg_pcie, _x) + +/* + * WLAN BT Global Registers + */ + +#define AR_GLB_GPIO_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_GPIO_CONTROL) +#define AR_GLB_WLAN_WOW_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_WLAN_WOW_STATUS) +#define AR_GLB_WLAN_WOW_ENABLE AR_WLAN_BT_GLB_OFFSET(GLB_WLAN_WOW_ENABLE) +#define AR_GLB_EMB_CPU_WOW_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_EMB_CPU_WOW_STATUS) +#define AR_GLB_EMB_CPU_WOW_ENABLE AR_WLAN_BT_GLB_OFFSET(GLB_EMB_CPU_WOW_ENABLE) +#define AR_GLB_MBOX_CONTROL_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_MBOX_CONTROL_STATUS) +#define AR_GLB_SW_WOW_CLK_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_SW_WOW_CLK_CONTROL) +#define AR_GLB_APB_TIMEOUT AR_WLAN_BT_GLB_OFFSET(GLB_APB_TIMEOUT) +#define AR_GLB_OTP_LDO_CONTROL AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_CONTROL) +#define AR_GLB_OTP_LDO_POWER_GOOD AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_POWER_GOOD) +#define AR_GLB_OTP_LDO_STATUS AR_WLAN_BT_GLB_OFFSET(GLB_OTP_LDO_STATUS) +#define AR_GLB_SWREG_DISCONT_MODE AR_WLAN_BT_GLB_OFFSET(GLB_SWREG_DISCONT_MODE) +#define AR_GLB_BT_GPIO_REMAP_OUT_CONTROL0 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_OUT_CONTROL0) +#define AR_GLB_BT_GPIO_REMAP_OUT_CONTROL1 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_OUT_CONTROL1) +#define AR_GLB_BT_GPIO_REMAP_IN_CONTROL0 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL0) +#define AR_GLB_BT_GPIO_REMAP_IN_CONTROL1 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL1) +#define AR_GLB_BT_GPIO_REMAP_IN_CONTROL2 AR_WLAN_BT_GLB_OFFSET(GLB_BT_GPIO_REMAP_IN_CONTROL2) +#define AR_GLB_SCRATCH(_ah) \ + (AR_SREV_APHRODITE(_ah)? \ + AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Aphrodite_10.GLB_SCRATCH) : \ + (AR_SREV_JUPITER_20(_ah) ? \ + AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_SCRATCH) : \ + AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_10.GLB_SCRATCH))) + +#define AR_GLB_CONTROL AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_CONTROL) +#define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001 +#define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0 +#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002 +#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1 +#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004 +#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2 +#define AR_GLB_WLAN_UART_INTF_EN 0x00020000 +#define AR_GLB_WLAN_UART_INTF_EN_S 17 +#define AR_GLB_DS_JTAG_DISABLE 0x00040000 +#define AR_GLB_DS_JTAG_DISABLE_S 18 + +#define AR_GLB_STATUS AR_WLAN_BT_GLB_OFFSET(overlay_0x20044.Jupiter_20.GLB_STATUS) + +/* + * MAC Version and Revision + */ + +#define AR_SREV_VERSION_OSPREY 0x1C0 +#define AR_SREV_VERSION_AR9580 0x1C0 +#define AR_SREV_VERSION_JUPITER 0x280 +#define AR_SREV_VERSION_HORNET 0x200 +#define AR_SREV_VERSION_WASP 0x300 /* XXX: Check Wasp version number */ +#define AR_SREV_VERSION_SCORPION 0x400 +#define AR_SREV_VERSION_POSEIDON 0x240 +#define AR_SREV_VERSION_APHRODITE 0x2C0 + +#define AR_SREV_REVISION_OSPREY_10 0 /* Osprey 1.0 */ +#define AR_SREV_REVISION_OSPREY_20 2 /* Osprey 2.0/2.1 */ +#define AR_SREV_REVISION_OSPREY_22 3 /* Osprey 2.2 */ +#define AR_SREV_REVISION_AR9580_10 4 /* AR9580/Peacock 1.0 */ + +#define AR_SREV_REVISION_HORNET_10 0 /* Hornet 1.0 */ +#define AR_SREV_REVISION_HORNET_11 1 /* Hornet 1.1 */ +#define AR_SREV_REVISION_HORNET_12 2 /* Hornet 1.2 */ +#define AR_SREV_REVISION_HORNET_11_MASK 0xf /* Hornet 1.1 revision mask */ + +#define AR_SREV_REVISION_POSEIDON_10 0 /* Poseidon 1.0 */ +#define AR_SREV_REVISION_POSEIDON_11 1 /* Poseidon 1.1 */ + +#define AR_SREV_REVISION_WASP_10 0 /* Wasp 1.0 */ +#define AR_SREV_REVISION_WASP_11 1 /* Wasp 1.1 */ +#define AR_SREV_REVISION_WASP_12 2 /* Wasp 1.2 */ +#define AR_SREV_REVISION_WASP_13 3 /* Wasp 1.3 */ +#define AR_SREV_REVISION_WASP_MASK 0xf /* Wasp revision mask */ +#define AR_SREV_REVISION_WASP_MINOR_MINOR_MASK 0x10000 /* Wasp minor minor revision mask */ +#define AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT 16 /* Wasp minor minor revision shift */ + +#define AR_SREV_REVISION_JUPITER_10 0 /* Jupiter 1.0 */ +#define AR_SREV_REVISION_JUPITER_20 2 /* Jupiter 2.0 */ + +#define AR_SREV_REVISION_APHRODITE_10 0 /* Aphrodite 1.0 */ + +#if defined(AH_SUPPORT_OSPREY) +#define AR_SREV_OSPREY(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_OSPREY)) + +#define AR_SREV_OSPREY_22(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OSPREY_22)) +#else +#define AR_SREV_OSPREY(_ah) 0 +#define AR_SREV_OSPREY_10(_ah) 0 +#define AR_SREV_OSPREY_20(_ah) 0 +#define AR_SREV_OSPREY_22(_ah) 0 +#define AR_SREV_OSPREY_20_OR_LATER(_ah) 0 +#define AR_SREV_OSPREY_22_OR_LATER(_ah) 0 +#endif /* #if defined(AH_SUPPORT_OSPREY) */ + +#define AR_SREV_AR9580(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && \ + (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_AR9580_10)) + +#define AR_SREV_AR9580_10(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_AR9580_10)) + +/* NOTE: When adding chips newer than Peacock, add chip check here. */ +#define AR_SREV_AR9580_10_OR_LATER(_ah) \ + (AR_SREV_AR9580(_ah)) + +#define AR_SREV_JUPITER(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER)) + +#define AR_SREV_JUPITER_10(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_10)) + +#define AR_SREV_JUPITER_20(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_JUPITER_20)) + +#define AR_SREV_JUPITER_20_OR_LATER(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_JUPITER) && \ + (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_JUPITER_20)) + +#define AR_SREV_APHRODITE(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_APHRODITE)) + +#define AR_SREV_APHRODITE_10(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_APHRODITE) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_APHRODITE_10)) + +#if defined(AH_SUPPORT_HORNET) +#define AR_SREV_HORNET_10(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_10)) + +#define AR_SREV_HORNET_11(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_11)) + +#define AR_SREV_HORNET_12(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_HORNET) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_HORNET_12)) + +#define AR_SREV_HORNET(_ah) \ + ( AR_SREV_HORNET_10(_ah) || AR_SREV_HORNET_11(_ah) || AR_SREV_HORNET_12(_ah) ) +#else +#define AR_SREV_HORNET_10(_ah) 0 +#define AR_SREV_HORNET_11(_ah) 0 +#define AR_SREV_HORNET_12(_ah) 0 +#define AR_SREV_HORNET(_ah) 0 +#endif /* #if defined(AH_SUPPORT_HORNET) */ + +#if defined(AH_SUPPORT_WASP) +#define AR_SREV_WASP(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP)) +#else +#define AR_SREV_WASP(_ah) 0 +#endif /* #if defined(AH_SUPPORT_WASP) */ + +#define AR_SREV_WASP_10(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_10)) + +#define AR_SREV_WASP_11(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_11)) + +#define AR_SREV_WASP_12(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_WASP) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_WASP_12)) + +#if defined(AH_SUPPORT_SCORPION) +#define AR_SREV_SCORPION(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_SCORPION)) +#else +#define AR_SREV_SCORPION(_ah) 0 +#endif /* #if defined(AH_SUPPORT_SCORPION) */ + +#if defined(AH_SUPPORT_POSEIDON) +#define AR_SREV_POSEIDON(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON)) + +#define AR_SREV_POSEIDON_10(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_POSEIDON_10)) + +#define AR_SREV_POSEIDON_11(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ + (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_POSEIDON_11)) +#else +#define AR_SREV_POSEIDON(_ah) 0 +#define AR_SREV_POSEIDON_10(_ah) 0 +#define AR_SREV_POSEIDON_11(_ah) 0 +#endif /* #if defined(AH_SUPPORT_POSEIDON) */ + +#define AR_SREV_POSEIDON_11_OR_LATER(_ah) \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_POSEIDON) && \ + (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_POSEIDON_11)) + +#define AR_SREV_POSEIDON_OR_LATER(_ah) \ + (AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_POSEIDON) +#define AR_SREV_SOC(_ah) (AR_SREV_HORNET(_ah) || AR_SREV_POSEIDON(_ah) || AR_SREV_WASP(_ah)) +/* +* Mask used to construct AAD for CCMP-AES +* Cisco spec defined bits 0-3 as mask +* IEEE802.11w defined as bit 4. +*/ +#define AR_MFP_QOS_MASK_IEEE 0x10 +#define AR_MFP_QOS_MASK_CISCO 0xf + +/* +* frame control field mask: +* 0 0 0 0 0 0 0 0 +* | | | | | | | | _ Order bit +* | | | | | | | _ _ Protected Frame bit +* | | | | | | _ _ _ More data bit +* | | | | | _ _ _ _ Power management bit +* | | | | _ _ _ _ _ Retry bit +* | | | _ _ _ _ _ _ More fragments bit +* | | _ _ _ _ _ _ _ FromDS bit +* | _ _ _ _ _ _ _ _ ToDS bit +*/ +#define AR_AES_MUTE_MASK1_FC_MGMT_MFP 0xC7FF +#endif diff --git a/hal/ar9300/ar9300template_ap121.h b/hal/ar9300/ar9300template_ap121.h new file mode 100644 index 000000000000..6468445b8a82 --- /dev/null +++ b/hal/ar9300/ar9300template_ap121.h @@ -0,0 +1,748 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * READ THIS NOTICE! + * + * Values defined in this file may only be changed under exceptional circumstances. + * + * Please ask Fiona Cain before making any changes. + */ + +#ifndef __ar9300templateAP121_h__ +#define __ar9300templateAP121_h__ + +static ar9300_eeprom_t ar9300_template_ap121= +{ + + 2, // eeprom_version; + + ar9300_eeprom_template_ap121, // template_version; + + {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; + + //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= + + {"ap121-010-00000"}, +// {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + + //static OSPREY_BASE_EEP_HEADER base_eep_header= + + { + {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration + 0x11, // txrx_mask; //4 bits tx and 4 bits rx + {AR9300_OPFLAGS_11G , 0}, // op_cap_flags; + 0, // rf_silent; + 0, // blue_tooth_options; + 0, // device_cap; + 4, // device_type; // takes lower byte in eeprom location + OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration + {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don + 0x0d, //feature_enable; //bit0 - enable tx temp comp + //bit1 - enable tx volt comp + //bit2 - enable fastClock - default to 1 + //bit3 - enable doubling - default to 1 + //bit4 - enable internal regulator - default to 0 + //bit5 - enable paprd -- default to 0 + 0, //misc_configuration: bit0 - turn down drivestrength + 6, // eeprom_write_enable_gpio + 0, // wlan_disable_gpio + 8, // wlan_led_gpio + 0xff, // rx_band_select_gpio + 0x10, // txrxgain + 0, // swreg + }, + + + //static OSPREY_MODAL_EEP_HEADER modal_header_2g= + { + + 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 25, // temp_slope; + 0, // voltSlope; + {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2c, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x80c0e0, // paprd_rate_mask_ht20 // 4 + 0x1ffffff, // paprd_rate_mask_ht40 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { + 6, // ant_div_control + {0,0}, // base_ext1 + 0, // misc_enable + {0,0,0,0,0,0,0,0}, // temp slop extension + 0, // quick drop low + 0, // quick drop high + }, + //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2462, 1) + }, + + //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= + + { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + }, + + //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= + { + //1L-5L,5S,11L,11S + {{34,34,34,34}}, + {{34,34,34,34}} + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //6-24,36,48,54 + {{34,34,32,32}}, + {{34,34,32,32}}, + {{34,34,32,32}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, + {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, + {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, + {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, + {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, + }, + +//static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= + + { + + 0x11, + 0x12, + 0x15, + 0x17, + 0x41, + 0x42, + 0x45, + 0x47, + 0x31, + 0x32, + 0x35, + 0x37 + + }, + +//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; + + { + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2457, 1), + FREQ2FBIN(2462, 1)}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2422, 1), + FREQ2FBIN(2427, 1), + FREQ2FBIN(2447, 1), + FREQ2FBIN(2452, 1)}, + + {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, + + {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + FREQ2FBIN(2472, 1), + 0}, + + {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, + + {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} + }, + + +//OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, + + {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + + }, +#else + { + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, + + {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + }, +#endif + +//static OSPREY_MODAL_EEP_HEADER modal_header_5g= + + { + + 0x220, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 45, // temp_slope; + 0, // voltSlope; + {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2d, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0xf0e0e0, // paprd_rate_mask_ht20 // 4 + 0xf0e0e0, // paprd_rate_mask_ht40 // 4 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { // base_ext2 + 40, // temp_slope_low + 50, // temp_slope_high + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} + }, + +//static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= + { + //pPiers[0] = + FREQ2FBIN(5180, 0), + //pPiers[1] = + FREQ2FBIN(5220, 0), + //pPiers[2] = + FREQ2FBIN(5320, 0), + //pPiers[3] = + FREQ2FBIN(5400, 0), + //pPiers[4] = + FREQ2FBIN(5500, 0), + //pPiers[5] = + FREQ2FBIN(5600, 0), + //pPiers[6] = + FREQ2FBIN(5700, 0), + //pPiers[7] = + FREQ2FBIN(5785, 0), + }, + +//static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= + + { + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + + }, + +//static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5825, 0) + }, + + +//static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + + { + //6-24,36,48,54 + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{30,30,30,28,24,20,30,28,24,20,20,20,20,16}}, + {{30,30,30,28,24,20,30,28,24,20,20,20,20,16}}, + {{30,30,30,26,22,18,30,26,22,18,18,18,18,16}}, + {{30,30,30,26,22,18,30,26,22,18,18,18,18,16}}, + {{30,30,30,24,20,16,30,24,20,16,16,16,16,14}}, + {{30,30,30,24,20,16,30,24,20,16,16,16,16,14}}, + {{30,30,30,22,18,14,30,22,18,14,14,14,14,12}}, + {{30,30,30,22,18,14,30,22,18,14,14,14,14,12}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{28,28,28,26,22,18,28,26,22,18,18,18,18,14}}, + {{28,28,28,26,22,18,28,26,22,18,18,18,18,14}}, + {{28,28,28,24,20,16,28,24,20,16,16,16,16,12}}, + {{28,28,28,24,20,16,28,24,20,16,16,16,16,12}}, + {{28,28,28,22,18,14,28,22,18,14,14,14,14,10}}, + {{28,28,28,22,18,14,28,22,18,14,14,14,14,10}}, + {{28,28,28,20,16,12,28,20,16,12,12,12,12,8}}, + {{28,28,28,20,16,12,28,20,16,12,12,12,12,8}}, + }, + +//static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= + + { + //pCtlIndex[0] = + 0x10, + //pCtlIndex[1] = + 0x16, + //pCtlIndex[2] = + 0x18, + //pCtlIndex[3] = + 0x40, + //pCtlIndex[4] = + 0x46, + //pCtlIndex[5] = + 0x48, + //pCtlIndex[6] = + 0x30, + //pCtlIndex[7] = + 0x36, + //pCtlIndex[8] = + 0x38 + }, + +// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; + + { + {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), + /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), + /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), + /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), + /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), + /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), + /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, + + {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), + /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), + /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[3].ctl_edges[6].bChannel*/0xFF, + /* Data[3].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), + /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), + /* Data[4].ctl_edges[4].bChannel*/0xFF, + /* Data[4].ctl_edges[5].bChannel*/0xFF, + /* Data[4].ctl_edges[6].bChannel*/0xFF, + /* Data[4].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), + /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), + /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), + /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[5].ctl_edges[6].bChannel*/0xFF, + /* Data[5].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), + /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), + /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), + /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), + /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, + + {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), + /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), + /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), + /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), + /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} + }, + +//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{0, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{0, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}}}, + } +#else + { + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 0}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 0}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}}}, + } +#endif +}; + +#endif + diff --git a/hal/ar9300/ar9300template_aphrodite.h b/hal/ar9300/ar9300template_aphrodite.h new file mode 100644 index 000000000000..a9e5f3635976 --- /dev/null +++ b/hal/ar9300/ar9300template_aphrodite.h @@ -0,0 +1,749 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + +/* + * READ THIS NOTICE! + * + * Values defined in this file may only be changed under exceptional circumstances. + * + * Please ask Fiona Cain before making any changes. + */ + +#ifndef __ar9300templateAphrodite_h__ +#define __ar9300templateAphrodite_h__ + +static ar9300_eeprom_t ar9300_template_aphrodite= +{ + + 0, // eeprom_version; + + ar9300_eeprom_template_aphrodite, // template_version; + + {0x00,0x03,0x7f,0x0,0x0,0x11}, //mac_addr[6]; + + //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= + + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + + //static OSPREY_BASE_EEP_HEADER base_eep_header= + + { + {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration + 0x11, // txrx_mask; //4 bits tx and 4 bits rx + {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags; + 0, // rf_silent; + 0, // blue_tooth_options; + 0, // device_cap; + 4, // device_type; // takes lower byte in eeprom location + OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration + {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don + 0x10, //feature_enable; //bit0 - enable tx temp comp + //bit1 - enable tx volt comp + //bit2 - enable fastClock - default to 1 + //bit3 - enable doubling - default to 1 + //bit4 - enable internal regulator - default to 0 + 0, //misc_configuration: bit0 - turn down drivestrength + 3, // eeprom_write_enable_gpio + 0, // wlan_disable_gpio + 8, // wlan_led_gpio + 0xff, // rx_band_select_gpio + 0, // txrxgain + 0, // swreg + }, + + + //static OSPREY_MODAL_EEP_HEADER modal_header_2g= + { + + 0x0, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x0, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x0,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 36, // temp_slope; + 0, // voltSlope; + {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2c, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0c80C080, // paprd_rate_mask_ht20 // 4 + 0x0080C080, // paprd_rate_mask_ht40 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { + 0, // ant_div_control + {0,0}, // base_ext1 + 0, // misc_enable + {0,0,0,0,0,0,0,0}, // temp slop extension + 0, // quick drop low + 0, // quick drop high + }, + + //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= + + { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + }, + + //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2484, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= + { + //1L-5L,5S,11L,11S + {{36,36,36,36}}, + {{36,36,36,36}} + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //6-24,36,48,54 + {{32,32,28,24}}, + {{32,32,28,24}}, + {{32,32,28,24}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + }, + +//static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= + + { + + 0x11, + 0x12, + 0x15, + 0x17, + 0x41, + 0x42, + 0x45, + 0x47, + 0x31, + 0x32, + 0x35, + 0x37 + + }, + +//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; + + { + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2457, 1), + FREQ2FBIN(2462, 1)}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2422, 1), + FREQ2FBIN(2427, 1), + FREQ2FBIN(2447, 1), + FREQ2FBIN(2452, 1)}, + + {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, + + {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + FREQ2FBIN(2472, 1), + 0}, + + {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, + + {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} + }, + + +//OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, + + {{{1, 60}, {0, 60}, {0, 0}, {0, 0}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + + }, +#else + { + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, + + {{{60, 1}, {60, 0}, {0, 0}, {0, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + }, +#endif + +//static OSPREY_MODAL_EEP_HEADER modal_header_5g= + + { + + 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x22222, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x000,0x000,0x000}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 68, // temp_slope; + 0, // voltSlope; + {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2d, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 + 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { // base_ext2 + 0, + 0, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} + }, + +//static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= + { + //pPiers[0] = + FREQ2FBIN(5180, 0), + //pPiers[1] = + FREQ2FBIN(5220, 0), + //pPiers[2] = + FREQ2FBIN(5320, 0), + //pPiers[3] = + FREQ2FBIN(5400, 0), + //pPiers[4] = + FREQ2FBIN(5500, 0), + //pPiers[5] = + FREQ2FBIN(5600, 0), + //pPiers[6] = + FREQ2FBIN(5725, 0), + //pPiers[7] = + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= + + { + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + + }, + +//static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5220, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + + +//static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + + { + //6-24,36,48,54 + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + }, + +//static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= + + { + //pCtlIndex[0] = + 0x10, + //pCtlIndex[1] = + 0x16, + //pCtlIndex[2] = + 0x18, + //pCtlIndex[3] = + 0x40, + //pCtlIndex[4] = + 0x46, + //pCtlIndex[5] = + 0x48, + //pCtlIndex[6] = + 0x30, + //pCtlIndex[7] = + 0x36, + //pCtlIndex[8] = + 0x38 + }, + +// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; + + { + {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), + /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), + /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), + /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), + /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), + /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), + /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, + + {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), + /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), + /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[3].ctl_edges[6].bChannel*/0xFF, + /* Data[3].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), + /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), + /* Data[4].ctl_edges[4].bChannel*/0xFF, + /* Data[4].ctl_edges[5].bChannel*/0xFF, + /* Data[4].ctl_edges[6].bChannel*/0xFF, + /* Data[4].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), + /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), + /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), + /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[5].ctl_edges[6].bChannel*/0xFF, + /* Data[5].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), + /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), + /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), + /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), + /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, + + {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), + /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), + /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), + /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), + /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} + }, + +//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{0, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{0, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}}}, + } +#else + { + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 0}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 0}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}}}, + } +#endif +}; + +#endif diff --git a/hal/ar9300/ar9300template_cus157.h b/hal/ar9300/ar9300template_cus157.h new file mode 100644 index 000000000000..dc37977956ec --- /dev/null +++ b/hal/ar9300/ar9300template_cus157.h @@ -0,0 +1,737 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * READ THIS NOTICE! + * + * Values defined in this file may only be changed under exceptional circumstances. + * + * Please ask Fiona Cain before making any changes. + */ + +#ifndef __ar9300template_cus157_h__ +#define __ar9300template_cus157_h__ + +static ar9300_eeprom_t Ar9300Template_cus157= +{ + + 2, // eepromVersion; + + ar9300_eeprom_template_cus157, // templateVersion; + + {0x00,0x03,0x7f,0x0,0x0,0x0}, //macAddr[6]; + + //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= + + {"cus157-030-f0000"}, +// {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + + //static OSPREY_BASE_EEP_HEADER baseEepHeader= + + { + {0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written after calibration + 0x77, // txrxMask; //4 bits tx and 4 bits rx + {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // opCapFlags; + 0, // rfSilent; + 0, // blueToothOptions; + 0, // deviceCap; + 5, // deviceType; // takes lower byte in eeprom location + OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration + {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don + 0x0d, //featureEnable; //bit0 - enable tx temp comp + //bit1 - enable tx volt comp + //bit2 - enable fastClock - default to 1 + //bit3 - enable doubling - default to 1 + //bit4 - enable internal regulator - default to 0 + //bit5 - enable paprd -- default to 0 + 0, //miscConfiguration: bit0 - turn down drivestrength + 6, // eepromWriteEnableGpio + 0, // wlanDisableGpio + 8, // wlanLedGpio + 0xff, // rxBandSelectGpio + 0x10, // txrxgain + 0, // swreg + }, + + + //static OSPREY_MODAL_EEP_HEADER modalHeader2G= + { + + 0x110, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) + 0x44444, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 25, // tempSlope; + 0, // voltSlope; + {FREQ2FBIN(2464, 1),0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpaBiasLvl; // 1 + 0x0e, // txFrameToDataStart; // 1 + 0x0e, // txFrameToPaOn; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antennaGain; // 1 + 0x2c, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // txFrameToXpaOn; // 1 + 28, // thresh62; // 1 + 0x80C080, // paprdRateMaskHt20 // 4 + 0x80C080, // paprdRateMaskHt40 + 0, // ant_div_control + {0,0,0,0,0,0,0,0,0} //futureModal[9]; + }, + + {{0,0,0,0,0,0,0,0,0,0,0,0,0,0}}, // base_ext1 + + //static A_UINT8 calFreqPier2G[OSPREY_NUM_2G_CAL_PIERS]= + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2462, 1) + }, + + //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData2G[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= + + { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + }, + + //A_UINT8 calTarget_freqbin_Cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG calTarget_freqbin_2G[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG calTargetPowerCck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= + { + //1L-5L,5S,11L,11S + {{34,34,34,34}}, + {{34,34,34,34}} + }, + + //static CAL_TARGET_POWER_LEG calTargetPower2G[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //6-24,36,48,54 + {{34,34,34,30}}, + {{34,34,34,30}}, + {{34,34,34,30}}, + }, + + //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}}, + {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}}, + {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}}, + }, + + //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}}, + {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}}, + {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}}, + }, + +//static A_UINT8 ctlIndex_2G[OSPREY_NUM_CTLS_2G]= + + { + + 0x11, + 0x12, + 0x15, + 0x17, + 0x41, + 0x42, + 0x45, + 0x47, + 0x31, + 0x32, + 0x35, + 0x37 + + }, + +//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; + + { + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2457, 1), + FREQ2FBIN(2462, 1)}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2422, 1), + FREQ2FBIN(2427, 1), + FREQ2FBIN(2447, 1), + FREQ2FBIN(2452, 1)}, + + {/*Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + /*Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(2484, 1)}, + + {/*Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + FREQ2FBIN(2472, 1), + 0}, + + {/*Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)}, + + {/*Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[9].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[9].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[9].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[10].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[10].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[10].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[11].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[11].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[11].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[11].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)} + }, + + +//OSP_CAL_CTL_DATA_2G ctlPowerData_2G[OSPREY_NUM_CTLS_2G]; + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, + + {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + + }, +#else + { + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, + + {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + }, +#endif + +//static OSPREY_MODAL_EEP_HEADER modalHeader5G= + + { + + 0x220, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) + 0x44444, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 45, // tempSlope; + 0, // voltSlope; + {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpaBiasLvl; // 1 + 0x0e, // txFrameToDataStart; // 1 + 0x0e, // txFrameToPaOn; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antennaGain; // 1 + 0x2d, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // txFrameToXpaOn; // 1 + 28, // thresh62; // 1 + 0xf0e0e0, // paprdRateMaskHt20 // 4 + 0xf0e0e0, // paprdRateMaskHt40 // 4 + {0,0,0,0,0,0,0,0,0,0} //futureModal[10]; + }, + + { // base_ext2 + 40, // tempSlopeLow + 50, // tempSlopeHigh + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} + }, + +//static A_UINT8 calFreqPier5G[OSPREY_NUM_5G_CAL_PIERS]= + { + //pPiers[0] = + FREQ2FBIN(5180, 0), + //pPiers[1] = + FREQ2FBIN(5220, 0), + //pPiers[2] = + FREQ2FBIN(5320, 0), + //pPiers[3] = + FREQ2FBIN(5400, 0), + //pPiers[4] = + FREQ2FBIN(5500, 0), + //pPiers[5] = + FREQ2FBIN(5600, 0), + //pPiers[6] = + FREQ2FBIN(5700, 0), + //pPiers[7] = + FREQ2FBIN(5785, 0), + }, + +//static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData5G[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= + + { + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + + }, + +//static CAL_TARGET_POWER_LEG calTarget_freqbin_5G[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5825, 0) + }, + + +//static CAL_TARGET_POWER_LEG calTargetPower5G[OSPREY_NUM_5G_20_TARGET_POWERS]= + + + { + //6-24,36,48,54 + {{30,30,26,22}}, + {{30,30,26,22}}, + {{30,30,30,24}}, + {{30,30,30,24}}, + {{30,30,26,22}}, + {{30,24,20,18}}, + {{30,24,20,18}}, + {{30,24,20,18}}, + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{30,30,30,28,24,20,30,28,24,18,30,26,22,16}}, + {{30,30,30,28,24,20,30,28,24,18,30,26,22,16}}, + {{30,30,30,26,22,18,30,26,22,16,30,24,20,14}}, + {{30,30,30,26,22,18,30,26,22,16,30,24,20,14}}, + {{30,30,30,24,20,16,30,24,20,14,30,22,18,12}}, + {{30,30,30,24,20,16,30,24,20,14,30,22,18,12}}, + {{28,28,28,22,18,14,28,22,18,12,28,20,16,10}}, + {{28,28,28,22,18,14,28,22,18,12,28,20,16,10}}, + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{28,28,28,26,22,18,28,24,20,16,20,16,16,16}}, + {{28,28,28,26,22,18,28,24,20,16,20,16,16,16}}, + {{28,28,28,28,24,20,28,28,24,20,22,20,20,20}}, + {{28,28,28,28,24,20,28,28,24,20,22,20,20,20}}, + {{28,28,28,24,20,16,28,24,20,16,18,16,16,16}}, + {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}}, + {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}}, + {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}}, + }, + +//static A_UINT8 ctlIndex_5G[OSPREY_NUM_CTLS_5G]= + + { + //pCtlIndex[0] = + 0x10, + //pCtlIndex[1] = + 0x16, + //pCtlIndex[2] = + 0x18, + //pCtlIndex[3] = + 0x40, + //pCtlIndex[4] = + 0x46, + //pCtlIndex[5] = + 0x48, + //pCtlIndex[6] = + 0x30, + //pCtlIndex[7] = + 0x36, + //pCtlIndex[8] = + 0x38 + }, + +// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; + + { + {/* Data[0].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[0].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[0].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[0].ctlEdges[4].bChannel*/FREQ2FBIN(5600, 0), + /* Data[0].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[0].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[0].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[1].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[1].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[1].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[1].ctlEdges[4].bChannel*/FREQ2FBIN(5520, 0), + /* Data[1].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[1].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[1].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[2].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[2].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[2].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[2].ctlEdges[3].bChannel*/FREQ2FBIN(5310, 0), + /* Data[2].ctlEdges[4].bChannel*/FREQ2FBIN(5510, 0), + /* Data[2].ctlEdges[5].bChannel*/FREQ2FBIN(5550, 0), + /* Data[2].ctlEdges[6].bChannel*/FREQ2FBIN(5670, 0), + /* Data[2].ctlEdges[7].bChannel*/FREQ2FBIN(5755, 0)}, + + {/* Data[3].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[3].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[3].ctlEdges[2].bChannel*/FREQ2FBIN(5260, 0), + /* Data[3].ctlEdges[3].bChannel*/FREQ2FBIN(5320, 0), + /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[3].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[3].ctlEdges[6].bChannel*/0xFF, + /* Data[3].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0), + /* Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(5700, 0), + /* Data[4].ctlEdges[4].bChannel*/0xFF, + /* Data[4].ctlEdges[5].bChannel*/0xFF, + /* Data[4].ctlEdges[6].bChannel*/0xFF, + /* Data[4].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(5270, 0), + /* Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(5310, 0), + /* Data[5].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[5].ctlEdges[4].bChannel*/FREQ2FBIN(5590, 0), + /* Data[5].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[5].ctlEdges[6].bChannel*/0xFF, + /* Data[5].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[6].ctlEdges[2].bChannel*/FREQ2FBIN(5220, 0), + /* Data[6].ctlEdges[3].bChannel*/FREQ2FBIN(5260, 0), + /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[6].ctlEdges[5].bChannel*/FREQ2FBIN(5600, 0), + /* Data[6].ctlEdges[6].bChannel*/FREQ2FBIN(5700, 0), + /* Data[6].ctlEdges[7].bChannel*/FREQ2FBIN(5745, 0)}, + + {/* Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(5320, 0), + /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[7].ctlEdges[4].bChannel*/FREQ2FBIN(5560, 0), + /* Data[7].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[7].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[7].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[8].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[8].ctlEdges[4].bChannel*/FREQ2FBIN(5550, 0), + /* Data[8].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[8].ctlEdges[6].bChannel*/FREQ2FBIN(5755, 0), + /* Data[8].ctlEdges[7].bChannel*/FREQ2FBIN(5795, 0)} + }, + +//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{0, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{0, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}}}, + } +#else + { + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 0}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 0}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}}}, + } +#endif +}; + +#endif + diff --git a/hal/ar9300/ar9300template_generic.h b/hal/ar9300/ar9300template_generic.h new file mode 100644 index 000000000000..6b7a0d1bb8f4 --- /dev/null +++ b/hal/ar9300/ar9300template_generic.h @@ -0,0 +1,748 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * READ THIS NOTICE! + * + * Values defined in this file may only be changed under exceptional circumstances. + * + * Please ask Fiona Cain before making any changes. + */ + +#ifndef __ar9300templateGeneric_h__ +#define __ar9300templateGeneric_h__ + +static ar9300_eeprom_t ar9300_template_generic= +{ + + 2, // eeprom_version; + + ar9300_eeprom_template_generic, // template_version; + + {0,2,3,4,5,6}, //mac_addr[6]; + + //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= + + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + + //static OSPREY_BASE_EEP_HEADER base_eep_header= + + { + {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration + 0x77, // txrx_mask; //4 bits tx and 4 bits rx + {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags; + 0, // rf_silent; + 0, // blue_tooth_options; + 0, // device_cap; + 5, // device_type; // takes lower byte in eeprom location + OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration + {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don + 0x0c, //feature_enable; //bit0 - enable tx temp comp + //bit1 - enable tx volt comp + //bit2 - enable fastClock - default to 1 + //bit3 - enable doubling - default to 1 + //bit4 - enable internal regulator - default to 0 + 0, //misc_configuration: bit0 - turn down drivestrength + 3, // eeprom_write_enable_gpio + 0, // wlan_disable_gpio + 8, // wlan_led_gpio + 0xff, // rx_band_select_gpio + 0, // txrxgain + 0, // swreg + }, + + + //static OSPREY_MODAL_EEP_HEADER modal_header_2g= + { + + 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x22222, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 36, // temp_slope; + 0, // voltSlope; + {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2c, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0c80C080, // paprd_rate_mask_ht20 // 4 + 0x0080C080, // paprd_rate_mask_ht40 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { + 0, // ant_div_control + {0,0}, // base_ext1 + 0, // misc_enable + {0,0,0,0,0,0,0,0}, // temp slop extension + 0, // quick drop low + 0, // quick drop high + }, + + //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= + + { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + }, + + //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2484, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= + { + //1L-5L,5S,11L,11S + {{36,36,36,36}}, + {{36,36,36,36}} + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //6-24,36,48,54 + {{32,32,28,24}}, + {{32,32,28,24}}, + {{32,32,28,24}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + }, + +//static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= + + { + + 0x11, + 0x12, + 0x15, + 0x17, + 0x41, + 0x42, + 0x45, + 0x47, + 0x31, + 0x32, + 0x35, + 0x37 + + }, + +//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; + + { + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2457, 1), + FREQ2FBIN(2462, 1)}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2422, 1), + FREQ2FBIN(2427, 1), + FREQ2FBIN(2447, 1), + FREQ2FBIN(2452, 1)}, + + {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, + + {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + FREQ2FBIN(2472, 1), + 0}, + + {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, + + {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} + }, + + +//OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, + + {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + + }, +#else + { + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, + + {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + }, +#endif + +//static OSPREY_MODAL_EEP_HEADER modal_header_5g= + + { + + 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x22222, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x000,0x000,0x000}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 68, // temp_slope; + 0, // voltSlope; + {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2d, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 + 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { // base_ext2 + 0, + 0, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} + }, + +//static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= + { + //pPiers[0] = + FREQ2FBIN(5180, 0), + //pPiers[1] = + FREQ2FBIN(5220, 0), + //pPiers[2] = + FREQ2FBIN(5320, 0), + //pPiers[3] = + FREQ2FBIN(5400, 0), + //pPiers[4] = + FREQ2FBIN(5500, 0), + //pPiers[5] = + FREQ2FBIN(5600, 0), + //pPiers[6] = + FREQ2FBIN(5725, 0), + //pPiers[7] = + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= + + { + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + + }, + +//static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5220, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + + +//static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + + { + //6-24,36,48,54 + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + }, + +//static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= + + { + //pCtlIndex[0] = + 0x10, + //pCtlIndex[1] = + 0x16, + //pCtlIndex[2] = + 0x18, + //pCtlIndex[3] = + 0x40, + //pCtlIndex[4] = + 0x46, + //pCtlIndex[5] = + 0x48, + //pCtlIndex[6] = + 0x30, + //pCtlIndex[7] = + 0x36, + //pCtlIndex[8] = + 0x38 + }, + +// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; + + { + {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), + /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), + /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), + /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), + /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), + /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), + /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, + + {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), + /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), + /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[3].ctl_edges[6].bChannel*/0xFF, + /* Data[3].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), + /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), + /* Data[4].ctl_edges[4].bChannel*/0xFF, + /* Data[4].ctl_edges[5].bChannel*/0xFF, + /* Data[4].ctl_edges[6].bChannel*/0xFF, + /* Data[4].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), + /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), + /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), + /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[5].ctl_edges[6].bChannel*/0xFF, + /* Data[5].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), + /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), + /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), + /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), + /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, + + {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), + /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), + /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), + /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), + /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} + }, + +//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{0, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{0, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}}}, + } +#else + { + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 0}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 0}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}}}, + } +#endif +}; + +#endif diff --git a/hal/ar9300/ar9300template_hb112.h b/hal/ar9300/ar9300template_hb112.h new file mode 100644 index 000000000000..c3bbc1d30203 --- /dev/null +++ b/hal/ar9300/ar9300template_hb112.h @@ -0,0 +1,751 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * READ THIS NOTICE! + * + * Values defined in this file may only be changed under exceptional circumstances. + * + * Please ask Fiona Cain before making any changes. + */ + +#ifndef __ar9300templateHB112_h__ +#define __ar9300templateHB112_h__ + +static ar9300_eeprom_t ar9300_template_hb112= +{ + + 2, // eeprom_version; + + ar9300_eeprom_template_hb112, // template_version; + + {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; + + //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= + + {"cus157-241-f0000"}, +// {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + + //static OSPREY_BASE_EEP_HEADER base_eep_header= + + { + {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration + 0x77, // txrx_mask; //4 bits tx and 4 bits rx + {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags; + 0, // rf_silent; + 0, // blue_tooth_options; + 0, // device_cap; + 5, // device_type; // takes lower byte in eeprom location + OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration + {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don + 0x0d, //feature_enable; //bit0 - enable tx temp comp + //bit1 - enable tx volt comp + //bit2 - enable fastClock - default to 1 + //bit3 - enable doubling - default to 1 + //bit4 - enable internal regulator - default to 0 + //bit5 - enable paprd -- default to 0 + 0, //misc_configuration: bit0 - turn down drivestrength + 6, // eeprom_write_enable_gpio + 0, // wlan_disable_gpio + 8, // wlan_led_gpio + 0xff, // rx_band_select_gpio + 0x10, // txrxgain + 0, // swreg + }, + + + //static OSPREY_MODAL_EEP_HEADER modal_header_2g= + { + + 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 25, // temp_slope; + 0, // voltSlope; + {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2c, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0c80C080, // paprd_rate_mask_ht20 // 4 + 0x0080C080, // paprd_rate_mask_ht40 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { + 0, // ant_div_control + {0,0}, // base_ext1 + 0, // misc_enable + {0,0,0,0,0,0,0,0}, // temp slop extension + 0, // quick drop low + 0, // quick drop high + }, + + //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2462, 1) + }, + + //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= + + { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + }, + + //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= + { + //1L-5L,5S,11L,11S + {{34,34,34,34}}, + {{34,34,34,34}} + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //6-24,36,48,54 + {{34,34,32,32}}, + {{34,34,32,32}}, + {{34,34,32,32}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, + {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, + {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, + {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, + {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, + }, + +//static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= + + { + + 0x11, + 0x12, + 0x15, + 0x17, + 0x41, + 0x42, + 0x45, + 0x47, + 0x31, + 0x32, + 0x35, + 0x37 + + }, + +//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; + + { + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2457, 1), + FREQ2FBIN(2462, 1)}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2422, 1), + FREQ2FBIN(2427, 1), + FREQ2FBIN(2447, 1), + FREQ2FBIN(2452, 1)}, + + {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, + + {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + FREQ2FBIN(2472, 1), + 0}, + + {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, + + {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} + }, + + +//OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, + + {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + + }, +#else + { + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, + + {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + }, +#endif + +//static OSPREY_MODAL_EEP_HEADER modal_header_5g= + + { + + 0x220, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 45, // temp_slope; + 0, // voltSlope; + {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2d, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 + 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { // base_ext2 + 40, // temp_slope_low + 50, // temp_slope_high + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} + }, + +//static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= + { + //pPiers[0] = + FREQ2FBIN(5180, 0), + //pPiers[1] = + FREQ2FBIN(5220, 0), + //pPiers[2] = + FREQ2FBIN(5320, 0), + //pPiers[3] = + FREQ2FBIN(5400, 0), + //pPiers[4] = + FREQ2FBIN(5500, 0), + //pPiers[5] = + FREQ2FBIN(5600, 0), + //pPiers[6] = + FREQ2FBIN(5700, 0), + //pPiers[7] = + FREQ2FBIN(5785, 0), + }, + +//static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= + + { + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + + }, + +//static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5825, 0) + }, + + +//static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + + { + //6-24,36,48,54 + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{30,30,30,28,24,20,30,28,24,20,20,20,20,16}}, + {{30,30,30,28,24,20,30,28,24,20,20,20,20,16}}, + {{30,30,30,26,22,18,30,26,22,18,18,18,18,16}}, + {{30,30,30,26,22,18,30,26,22,18,18,18,18,16}}, + {{30,30,30,24,20,16,30,24,20,16,16,16,16,14}}, + {{30,30,30,24,20,16,30,24,20,16,16,16,16,14}}, + {{30,30,30,22,18,14,30,22,18,14,14,14,14,12}}, + {{30,30,30,22,18,14,30,22,18,14,14,14,14,12}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{28,28,28,26,22,18,28,26,22,18,18,18,18,14}}, + {{28,28,28,26,22,18,28,26,22,18,18,18,18,14}}, + {{28,28,28,24,20,16,28,24,20,16,16,16,16,12}}, + {{28,28,28,24,20,16,28,24,20,16,16,16,16,12}}, + {{28,28,28,22,18,14,28,22,18,14,14,14,14,10}}, + {{28,28,28,22,18,14,28,22,18,14,14,14,14,10}}, + {{28,28,28,20,16,12,28,20,16,12,12,12,12,8}}, + {{28,28,28,20,16,12,28,20,16,12,12,12,12,8}}, + }, + +//static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= + + { + //pCtlIndex[0] = + 0x10, + //pCtlIndex[1] = + 0x16, + //pCtlIndex[2] = + 0x18, + //pCtlIndex[3] = + 0x40, + //pCtlIndex[4] = + 0x46, + //pCtlIndex[5] = + 0x48, + //pCtlIndex[6] = + 0x30, + //pCtlIndex[7] = + 0x36, + //pCtlIndex[8] = + 0x38 + }, + +// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; + + { + {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), + /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), + /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), + /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), + /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), + /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), + /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, + + {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), + /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), + /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[3].ctl_edges[6].bChannel*/0xFF, + /* Data[3].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), + /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), + /* Data[4].ctl_edges[4].bChannel*/0xFF, + /* Data[4].ctl_edges[5].bChannel*/0xFF, + /* Data[4].ctl_edges[6].bChannel*/0xFF, + /* Data[4].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), + /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), + /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), + /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[5].ctl_edges[6].bChannel*/0xFF, + /* Data[5].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), + /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), + /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), + /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), + /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, + + {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), + /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), + /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), + /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), + /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} + }, + +//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{0, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{0, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}}}, + } +#else + { + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 0}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 0}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}}}, + } +#endif +}; + +#endif + diff --git a/hal/ar9300/ar9300template_hb116.h b/hal/ar9300/ar9300template_hb116.h new file mode 100644 index 000000000000..c1de18ebbe0e --- /dev/null +++ b/hal/ar9300/ar9300template_hb116.h @@ -0,0 +1,751 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * READ THIS NOTICE! + * + * Values defined in this file may only be changed under exceptional circumstances. + * + * Please ask Fiona Cain before making any changes. + */ + + +#ifndef __ar9300templateHB116_h__ +#define __ar9300templateHB116_h__ + +static ar9300_eeprom_t ar9300_template_hb116= +{ + + 2, // eeprom_version; + + ar9300_eeprom_template_hb116, // template_version; + + {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; + + //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= + + {"hb116-041-f0000"}, +// {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + + //static OSPREY_BASE_EEP_HEADER base_eep_header= + + { + {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration + 0x33, // txrx_mask; //4 bits tx and 4 bits rx + {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags; + 0, // rf_silent; + 0, // blue_tooth_options; + 0, // device_cap; + 5, // device_type; // takes lower byte in eeprom location + OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration + {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don + 0x0d, //feature_enable; //bit0 - enable tx temp comp + //bit1 - enable tx volt comp + //bit2 - enable fastClock - default to 1 + //bit3 - enable doubling - default to 1 + //bit4 - enable internal regulator - default to 0 + //bit5 - enable paprd -- default to 0 + 0, //misc_configuration: bit0 - turn down drivestrength + 6, // eeprom_write_enable_gpio + 0, // wlan_disable_gpio + 8, // wlan_led_gpio + 0xff, // rx_band_select_gpio + 0x10, // txrxgain + 0, // swreg + }, + + + //static OSPREY_MODAL_EEP_HEADER modal_header_2g= + { + + 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x10,0x10,0x10}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0x1f,0x1f,0x1f}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0x12,0x12,0x12}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 25, // temp_slope; + 0, // voltSlope; + {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2c, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0c80C080, // paprd_rate_mask_ht20 // 4 + 0x0080C080, // paprd_rate_mask_ht40 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { + 0, // ant_div_control + {0,0}, // base_ext1 + 0, // misc_enable + {0,0,0,0,0,0,0,0}, // temp slop extension + 0, // quick drop low + 0, // quick drop high + }, + + //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2462, 1) + }, + + //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= + + { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + }, + + //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= + { + //1L-5L,5S,11L,11S + {{34,34,34,34}}, + {{34,34,34,34}} + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //6-24,36,48,54 + {{34,34,32,32}}, + {{34,34,32,32}}, + {{34,34,32,32}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, + {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, + {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, + {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, + {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, + }, + +//static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= + + { + + 0x11, + 0x12, + 0x15, + 0x17, + 0x41, + 0x42, + 0x45, + 0x47, + 0x31, + 0x32, + 0x35, + 0x37 + + }, + +//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; + + { + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2457, 1), + FREQ2FBIN(2462, 1)}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2422, 1), + FREQ2FBIN(2427, 1), + FREQ2FBIN(2447, 1), + FREQ2FBIN(2452, 1)}, + + {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, + + {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + FREQ2FBIN(2472, 1), + 0}, + + {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, + + {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} + }, + + +//OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, + + {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + + }, +#else + { + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, + + {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + }, +#endif + +//static OSPREY_MODAL_EEP_HEADER modal_header_5g= + + { + + 0x220, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0x19,0x19,0x19}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0x14,0x14,0x14}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 70, // temp_slope; + 0, // voltSlope; + {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2d, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 + 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { // base_ext2 + 35, // temp_slope_low + 50, // temp_slope_high + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} + }, + +//static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= + { + //pPiers[0] = + FREQ2FBIN(5160, 0), + //pPiers[1] = + FREQ2FBIN(5220, 0), + //pPiers[2] = + FREQ2FBIN(5320, 0), + //pPiers[3] = + FREQ2FBIN(5400, 0), + //pPiers[4] = + FREQ2FBIN(5500, 0), + //pPiers[5] = + FREQ2FBIN(5600, 0), + //pPiers[6] = + FREQ2FBIN(5700, 0), + //pPiers[7] = + FREQ2FBIN(5785, 0), + }, + +//static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= + + { + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + + }, + +//static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5825, 0) + }, + + +//static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + + { + //6-24,36,48,54 + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{30,30,30,28,24,20,30,28,24,20,0,0,0,0}}, + {{30,30,30,28,24,20,30,28,24,20,0,0,0,0}}, + {{30,30,30,26,22,18,30,26,22,18,0,0,0,0}}, + {{30,30,30,26,22,18,30,26,22,18,0,0,0,0}}, + {{30,30,30,24,20,16,30,24,20,16,0,0,0,0}}, + {{30,30,30,24,20,16,30,24,20,16,0,0,0,0}}, + {{30,30,30,22,18,14,30,22,18,14,0,0,0,0}}, + {{30,30,30,22,18,14,30,22,18,14,0,0,0,0}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{28,28,28,26,22,18,28,26,22,18,0,0,0,0}}, + {{28,28,28,26,22,18,28,26,22,18,0,0,0,0}}, + {{28,28,28,24,20,16,28,24,20,16,0,0,0,0}}, + {{28,28,28,24,20,16,28,24,20,16,0,0,0,0}}, + {{28,28,28,22,18,14,28,22,18,14,0,0,0,0}}, + {{28,28,28,22,18,14,28,22,18,14,0,0,0,0}}, + {{28,28,28,20,16,12,28,20,16,12,0,0,0,0}}, + {{28,28,28,20,16,12,28,20,16,12,0,0,0,0}}, + }, + +//static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= + + { + //pCtlIndex[0] = + 0x10, + //pCtlIndex[1] = + 0x16, + //pCtlIndex[2] = + 0x18, + //pCtlIndex[3] = + 0x40, + //pCtlIndex[4] = + 0x46, + //pCtlIndex[5] = + 0x48, + //pCtlIndex[6] = + 0x30, + //pCtlIndex[7] = + 0x36, + //pCtlIndex[8] = + 0x38 + }, + +// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; + + { + {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), + /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), + /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), + /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), + /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), + /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), + /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, + + {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), + /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), + /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[3].ctl_edges[6].bChannel*/0xFF, + /* Data[3].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), + /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), + /* Data[4].ctl_edges[4].bChannel*/0xFF, + /* Data[4].ctl_edges[5].bChannel*/0xFF, + /* Data[4].ctl_edges[6].bChannel*/0xFF, + /* Data[4].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), + /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), + /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), + /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[5].ctl_edges[6].bChannel*/0xFF, + /* Data[5].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), + /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), + /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), + /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), + /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, + + {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), + /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), + /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), + /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), + /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} + }, + +//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{0, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{0, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}}}, + } +#else + { + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 0}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 0}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}}}, + } +#endif +}; + +#endif diff --git a/hal/ar9300/ar9300template_osprey_k31.h b/hal/ar9300/ar9300template_osprey_k31.h new file mode 100644 index 000000000000..b6b09e80985b --- /dev/null +++ b/hal/ar9300/ar9300template_osprey_k31.h @@ -0,0 +1,751 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * READ THIS NOTICE! + * + * Values defined in this file may only be changed under exceptional circumstances. + * + * Please ask Fiona Cain before making any changes. + */ + +#ifndef __ar9300templateOsprey_k31_h__ +#define __ar9300templateOsprey_k31_h__ + +static ar9300_eeprom_t ar9300_template_osprey_k31= +{ + + 2, // eepromVersion; + + ar9300_eeprom_template_osprey_k31, // templateVersion; + + //NC, Mac Address Colon from HB116 + {0,3,0x7f,41,22,0xb4}, //macAddr[6]; + + //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= + + //NC, No Serial Number + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + + //static OSPREY_BASE_EEP_HEADER baseEepHeader= + + { + {0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written after calibration + 0x33, // txrxMask; //4 bits tx and 4 bits rx + {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // opCapFlags; + 0, // rfSilent; + 0, // blueToothOptions; + 0, // deviceCap; + 5, // deviceType; // takes lower byte in eeprom location + OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration + {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don + 0x1d, //featureEnable; //bit0 - enable tx temp comp + //bit1 - enable tx volt comp + //bit2 - enable fastClock - default to 1 + //bit3 - enable doubling - default to 1 + //bit4 - enable internal regulator - default to 0 + 0, //miscConfiguration: bit0 - turn down drivestrength + 6, // eepromWriteEnableGpio + 0, // wlanDisableGpio + 8, // wlanLedGpio + 0xff, // rxBandSelectGpio + 10, // txrxgain + 0x709142fe, // swreg + }, + + + //static OSPREY_MODAL_EEP_HEADER modalHeader2G= + { + + 0x110, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) + 0xeeeee, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 25, // tempSlope; + 0, // voltSlope; + {0xa4,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0xf, // xpaBiasLvl; // 1 + 0x0e, // txFrameToDataStart; // 1 + 0x0e, // txFrameToPaOn; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antennaGain; // 1 + 0x2c, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // txFrameToXpaOn; // 1 + 28, // thresh62; // 1 + 0x0c80C080, // papdRateMaskHt20 // 4 + 0x0080C080, // papdRateMaskHt40 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { + 0, // ant_div_control + {0,0}, // base_ext1 + 0, // misc_enable + {0,0,0,0,0,0,0,0}, // temp slop extension + 0, // quick drop low + 0, // quick drop high + }, + + + //static A_UINT8 calFreqPier2G[OSPREY_NUM_2G_CAL_PIERS]= + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2462, 1) + }, + + //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData2G[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= + + { {{235,0,148,150,162,0}, {235,0,147,150,163,0}, {235,0,147,150,163,0}}, + {{232,0,147,148,162,0}, {233,0,147,148,163,0}, {234,0,147,148,163,0}}, + {{0,0,0,136,162,0}, {0,0,0,136,163,0}, {0,0,0,136,163,0}}, + }, + + //A_UINT8 calTarget_freqbin_Cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG calTarget_freqbin_2G[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG calTargetPowerCck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= + { + //1L-5L,5S,11L,11S + {{34,34,34,34}}, + {{34,34,34,34}} + }, + + //static CAL_TARGET_POWER_LEG calTargetPower2G[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //6-24,36,48,54 + {{34,34,32,32}}, + {{34,34,32,32}}, + {{34,34,32,32}}, + }, + + //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, + {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, + {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, + }, + + //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, + {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, + {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, + }, + +//static A_UINT8 ctlIndex_2G[OSPREY_NUM_CTLS_2G]= + + { + + 0x11, + 0x12, + 0x15, + 0x17, + 0x41, + 0x42, + 0x45, + 0x47, + 0x31, + 0x32, + 0x35, + 0x37 + + }, + +//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; + + { + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2457, 1), + FREQ2FBIN(2462, 1)}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2422, 1), + FREQ2FBIN(2427, 1), + FREQ2FBIN(2447, 1), + FREQ2FBIN(2452, 1)}, + + {/*Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + /*Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(2484, 1)}, + + {/*Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + FREQ2FBIN(2472, 1), + 0}, + + {/*Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)}, + + {/*Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[9].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[9].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[9].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[10].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[10].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[10].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[11].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[11].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[11].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[11].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)} + }, + + +//OSP_CAL_CTL_DATA_2G ctlPowerData_2G[OSPREY_NUM_CTLS_2G]; + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, + + {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + + }, +#else + { + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, + + {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + }, +#endif + +//static OSPREY_MODAL_EEP_HEADER modalHeader5G= + + { + + 0x220, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) + 0x11111, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 45, // tempSlope; + 0, // voltSlope; + {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpaBiasLvl; // 1 + 0x0e, // txFrameToDataStart; // 1 + 0x0e, // txFrameToPaOn; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antennaGain; // 1 + 0x2d, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // txFrameToXpaOn; // 1 + 28, // thresh62; // 1 + 0x0cf0e0e0, // papdRateMaskHt20 // 4 + 0x6cf0e0e0, // papdRateMaskHt40 // 4 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { // base_ext2 + 0, + 0, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} + }, + +//static A_UINT8 calFreqPier5G[OSPREY_NUM_5G_CAL_PIERS]= + { + //pPiers[0] = + FREQ2FBIN(5160, 0), + //pPiers[1] = + FREQ2FBIN(5220, 0), + //pPiers[2] = + FREQ2FBIN(5320, 0), + //pPiers[3] = + FREQ2FBIN(5400, 0), + //pPiers[4] = + FREQ2FBIN(5500, 0), + //pPiers[5] = + FREQ2FBIN(5600, 0), + //pPiers[6] = + FREQ2FBIN(5700, 0), + //pPiers[7] = + FREQ2FBIN(5785, 0) + }, + +//static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData5G[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= + + { +{{170,0,149,0,0,0},{170,0,149,147,167,0},{170,0,149,0,0,0},{170,0,147,0,0,0}, {170,0,146,148,164,0}, {170,0,146,0,0,0}, {170,0,147,145,163,0}, {170,0,146,143,162,0}}, +{{170,0,149,0,0,0},{170,0,149,147,167,0},{170,0,149,0,0,0},{170,0,147,0,0,0}, {170,0,146,148,164,0}, {170,0,146,0,0,0}, {170,0,147,145,163,0}, {170,0,146,143,162,0}}, +{{0,0,0,0,0,0}, {0,0,0,136,167,0},{0,0,0,0,0}, {0,0,0,0,0}, {0 ,0,0 ,137,164,0}, {0,0,0,0,0}, {0 ,0,0 ,136,163,0}, {0 ,0,0 ,136,162,0}}, + + }, + +//static CAL_TARGET_POWER_LEG calTarget_freqbin_5G[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5825, 0) + }, + + +//static CAL_TARGET_POWER_LEG calTargetPower5G[OSPREY_NUM_5G_20_TARGET_POWERS]= + + + { + //6-24,36,48,54 + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + {{30,30,28,24}}, + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{30,30,30,28,24,20,30,28,24,20,0,0,0,0}}, + {{30,30,30,28,24,20,30,28,24,20,0,0,0,0}}, + {{30,30,30,26,22,18,30,26,22,18,0,0,0,0}}, + {{30,30,30,26,22,18,30,26,22,18,0,0,0,0}}, + {{30,30,30,24,20,16,30,24,20,16,0,0,0,0}}, + {{30,30,30,24,20,16,30,24,20,16,0,0,0,0}}, + {{30,30,30,22,18,14,30,22,18,14,0,0,0,0}}, + {{30,30,30,22,18,14,30,22,18,14,0,0,0,0}}, + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0}}, + {{28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0}}, + {{28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0}}, + {{28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0}}, + {{28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0}}, + {{28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0}}, + {{28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0}}, + {{28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0}}, + }, + +//static A_UINT8 ctlIndex_5G[OSPREY_NUM_CTLS_5G]= + + { + //pCtlIndex[0] = + 0x10, + //pCtlIndex[1] = + 0x16, + //pCtlIndex[2] = + 0x18, + //pCtlIndex[3] = + 0x40, + //pCtlIndex[4] = + 0x46, + //pCtlIndex[5] = + 0x48, + //pCtlIndex[6] = + 0x30, + //pCtlIndex[7] = + 0x36, + //pCtlIndex[8] = + 0x38 + }, + +// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; + + { + {/* Data[0].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[0].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[0].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[0].ctlEdges[4].bChannel*/FREQ2FBIN(5600, 0), + /* Data[0].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[0].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[0].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[1].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[1].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[1].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[1].ctlEdges[4].bChannel*/FREQ2FBIN(5520, 0), + /* Data[1].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[1].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[1].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[2].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[2].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[2].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[2].ctlEdges[3].bChannel*/FREQ2FBIN(5310, 0), + /* Data[2].ctlEdges[4].bChannel*/FREQ2FBIN(5510, 0), + /* Data[2].ctlEdges[5].bChannel*/FREQ2FBIN(5550, 0), + /* Data[2].ctlEdges[6].bChannel*/FREQ2FBIN(5670, 0), + /* Data[2].ctlEdges[7].bChannel*/FREQ2FBIN(5755, 0)}, + + {/* Data[3].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[3].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[3].ctlEdges[2].bChannel*/FREQ2FBIN(5260, 0), + /* Data[3].ctlEdges[3].bChannel*/FREQ2FBIN(5320, 0), + /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[3].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[3].ctlEdges[6].bChannel*/0xFF, + /* Data[3].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0), + /* Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(5700, 0), + /* Data[4].ctlEdges[4].bChannel*/0xFF, + /* Data[4].ctlEdges[5].bChannel*/0xFF, + /* Data[4].ctlEdges[6].bChannel*/0xFF, + /* Data[4].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(5270, 0), + /* Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(5310, 0), + /* Data[5].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[5].ctlEdges[4].bChannel*/FREQ2FBIN(5590, 0), + /* Data[5].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[5].ctlEdges[6].bChannel*/0xFF, + /* Data[5].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[6].ctlEdges[2].bChannel*/FREQ2FBIN(5220, 0), + /* Data[6].ctlEdges[3].bChannel*/FREQ2FBIN(5260, 0), + /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[6].ctlEdges[5].bChannel*/FREQ2FBIN(5600, 0), + /* Data[6].ctlEdges[6].bChannel*/FREQ2FBIN(5700, 0), + /* Data[6].ctlEdges[7].bChannel*/FREQ2FBIN(5745, 0)}, + + {/* Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(5320, 0), + /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[7].ctlEdges[4].bChannel*/FREQ2FBIN(5560, 0), + /* Data[7].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[7].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[7].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[8].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[8].ctlEdges[4].bChannel*/FREQ2FBIN(5550, 0), + /* Data[8].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[8].ctlEdges[6].bChannel*/FREQ2FBIN(5755, 0), + /* Data[8].ctlEdges[7].bChannel*/FREQ2FBIN(5795, 0)} + }, + +//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{0, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{0, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}}}, + } +#else + { + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 0}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 0}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}}}, + } +#endif +}; + +#endif diff --git a/hal/ar9300/ar9300template_wasp_2.h b/hal/ar9300/ar9300template_wasp_2.h new file mode 100644 index 000000000000..2eb165f3a72f --- /dev/null +++ b/hal/ar9300/ar9300template_wasp_2.h @@ -0,0 +1,747 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * READ THIS NOTICE! + * + * Values defined in this file may only be changed under exceptional circumstances. + * + * Please ask Fiona Cain before making any changes. + */ + +#ifndef __ar9300template_wasp_2_h__ +#define __ar9300template_wasp_2_h__ +static ar9300_eeprom_t ar9300_template_wasp_2= +{ + + 2, // eepromVersion; + + ar9300_eeprom_template_wasp_2, // templateVersion; + + {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; + + //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= + + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + + //static OSPREY_BASE_EEP_HEADER baseEepHeader= + + { + {0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written after calibration + 0x33, // txrxMask; //4 bits tx and 4 bits rx + {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 3}, // opCapFlags; + 0, // rfSilent; + 0, // blueToothOptions; + 0, // deviceCap; + 4, // deviceType; // takes lower byte in eeprom location + OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration + {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don + 0x0c, //featureEnable; //bit0 - enable tx temp comp + //bit1 - enable tx volt comp + //bit2 - enable fastClock - default to 1 + //bit3 - enable doubling - default to 1 + //bit4 - enable internal regulator - default to 0 + 0, //miscConfiguration: bit0 - turn down drivestrength + 3, // eepromWriteEnableGpio + 0, // wlanDisableGpio + 8, // wlanLedGpio + 0xff, // rxBandSelectGpio + 0, // txrxgain + 0, // swreg + }, + + + //static OSPREY_MODAL_EEP_HEADER modalHeader2G= + { + + 0x220, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) + 0x88888, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 36, // tempSlope; + 0, // voltSlope; + {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpaBiasLvl; // 1 + 0x0e, // txFrameToDataStart; // 1 + 0x0e, // txFrameToPaOn; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antennaGain; // 1 + 0x2c, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // txFrameToXpaOn; // 1 + 28, // thresh62; // 1 + 0x0c80C080, // papdRateMaskHt20 // 4 + 0x0080C080, // papdRateMaskHt40 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { + 0, // ant_div_control + {0,0}, // base_ext1 + 0, // misc_enable + {0,0,0,0,0,0,0,0}, // temp slop extension + 0, // quick drop low + 0, // quick drop high + }, + + //static A_UINT8 calFreqPier2G[OSPREY_NUM_2G_CAL_PIERS]= + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData2G[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= + + { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + }, + + //A_UINT8 calTarget_freqbin_Cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2484, 1) + }, + + //static CAL_TARGET_POWER_LEG calTarget_freqbin_2G[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG calTargetPowerCck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= + { + //1L-5L,5S,11L,11S + {{36,36,36,36}}, + {{36,36,36,36}} + }, + + //static CAL_TARGET_POWER_LEG calTargetPower2G[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //6-24,36,48,54 + {{32,32,28,24}}, + {{32,32,28,24}}, + {{32,32,28,24}}, + }, + + //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + }, + + //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + }, + +//static A_UINT8 ctlIndex_2G[OSPREY_NUM_CTLS_2G]= + + { + + 0x11, + 0x12, + 0x15, + 0x17, + 0x41, + 0x42, + 0x45, + 0x47, + 0x31, + 0x32, + 0x35, + 0x37 + + }, + +//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; + + { + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2457, 1), + FREQ2FBIN(2462, 1)}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2422, 1), + FREQ2FBIN(2427, 1), + FREQ2FBIN(2447, 1), + FREQ2FBIN(2452, 1)}, + + {/*Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + /*Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(2484, 1)}, + + {/*Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + FREQ2FBIN(2472, 1), + 0}, + + {/*Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)}, + + {/*Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[9].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[9].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[9].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[10].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[10].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[10].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[11].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[11].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[11].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[11].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)} + }, + + +//OSP_CAL_CTL_DATA_2G ctlPowerData_2G[OSPREY_NUM_CTLS_2G]; + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, + + {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + + }, +#else + { + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, + + {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + }, +#endif + +//static OSPREY_MODAL_EEP_HEADER modalHeader5G= + + { + + 0x440, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) + 0x11111, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x000,0x000,0x000}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 68, // tempSlope; + 0, // voltSlope; + {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpaBiasLvl; // 1 + 0x0e, // txFrameToDataStart; // 1 + 0x0e, // txFrameToPaOn; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antennaGain; // 1 + 0x2d, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // txFrameToXpaOn; // 1 + 28, // thresh62; // 1 + 0x0cf0e0e0, // papdRateMaskHt20 // 4 + 0x6cf0e0e0, // papdRateMaskHt40 // 4 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { // base_ext2 + 0, + 0, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} + }, + +//static A_UINT8 calFreqPier5G[OSPREY_NUM_5G_CAL_PIERS]= + { + //pPiers[0] = + FREQ2FBIN(5180, 0), + //pPiers[1] = + FREQ2FBIN(5220, 0), + //pPiers[2] = + FREQ2FBIN(5320, 0), + //pPiers[3] = + FREQ2FBIN(5400, 0), + //pPiers[4] = + FREQ2FBIN(5500, 0), + //pPiers[5] = + FREQ2FBIN(5600, 0), + //pPiers[6] = + FREQ2FBIN(5725, 0), + //pPiers[7] = + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData5G[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= + + { + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + + }, + +//static CAL_TARGET_POWER_LEG calTarget_freqbin_5G[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5220, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + + +//static CAL_TARGET_POWER_LEG calTargetPower5G[OSPREY_NUM_5G_20_TARGET_POWERS]= + + + { + //6-24,36,48,54 + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + }, + +//static A_UINT8 ctlIndex_5G[OSPREY_NUM_CTLS_5G]= + + { + //pCtlIndex[0] = + 0x10, + //pCtlIndex[1] = + 0x16, + //pCtlIndex[2] = + 0x18, + //pCtlIndex[3] = + 0x40, + //pCtlIndex[4] = + 0x46, + //pCtlIndex[5] = + 0x48, + //pCtlIndex[6] = + 0x30, + //pCtlIndex[7] = + 0x36, + //pCtlIndex[8] = + 0x38 + }, + +// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; + + { + {/* Data[0].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[0].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[0].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[0].ctlEdges[4].bChannel*/FREQ2FBIN(5600, 0), + /* Data[0].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[0].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[0].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[1].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[1].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[1].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[1].ctlEdges[4].bChannel*/FREQ2FBIN(5520, 0), + /* Data[1].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[1].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[1].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[2].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[2].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[2].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[2].ctlEdges[3].bChannel*/FREQ2FBIN(5310, 0), + /* Data[2].ctlEdges[4].bChannel*/FREQ2FBIN(5510, 0), + /* Data[2].ctlEdges[5].bChannel*/FREQ2FBIN(5550, 0), + /* Data[2].ctlEdges[6].bChannel*/FREQ2FBIN(5670, 0), + /* Data[2].ctlEdges[7].bChannel*/FREQ2FBIN(5755, 0)}, + + {/* Data[3].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[3].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[3].ctlEdges[2].bChannel*/FREQ2FBIN(5260, 0), + /* Data[3].ctlEdges[3].bChannel*/FREQ2FBIN(5320, 0), + /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[3].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[3].ctlEdges[6].bChannel*/0xFF, + /* Data[3].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0), + /* Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(5700, 0), + /* Data[4].ctlEdges[4].bChannel*/0xFF, + /* Data[4].ctlEdges[5].bChannel*/0xFF, + /* Data[4].ctlEdges[6].bChannel*/0xFF, + /* Data[4].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(5270, 0), + /* Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(5310, 0), + /* Data[5].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[5].ctlEdges[4].bChannel*/FREQ2FBIN(5590, 0), + /* Data[5].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[5].ctlEdges[6].bChannel*/0xFF, + /* Data[5].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[6].ctlEdges[2].bChannel*/FREQ2FBIN(5220, 0), + /* Data[6].ctlEdges[3].bChannel*/FREQ2FBIN(5260, 0), + /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[6].ctlEdges[5].bChannel*/FREQ2FBIN(5600, 0), + /* Data[6].ctlEdges[6].bChannel*/FREQ2FBIN(5700, 0), + /* Data[6].ctlEdges[7].bChannel*/FREQ2FBIN(5745, 0)}, + + {/* Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(5320, 0), + /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[7].ctlEdges[4].bChannel*/FREQ2FBIN(5560, 0), + /* Data[7].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[7].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[7].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[8].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[8].ctlEdges[4].bChannel*/FREQ2FBIN(5550, 0), + /* Data[8].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[8].ctlEdges[6].bChannel*/FREQ2FBIN(5755, 0), + /* Data[8].ctlEdges[7].bChannel*/FREQ2FBIN(5795, 0)} + }, + +//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{0, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{0, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}}}, + } +#else + { + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 0}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 0}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}}}, + } +#endif +}; + +#endif diff --git a/hal/ar9300/ar9300template_wasp_k31.h b/hal/ar9300/ar9300template_wasp_k31.h new file mode 100644 index 000000000000..413e0e5f95fa --- /dev/null +++ b/hal/ar9300/ar9300template_wasp_k31.h @@ -0,0 +1,748 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * READ THIS NOTICE! + * + * Values defined in this file may only be changed under exceptional circumstances. + * + * Please ask Fiona Cain before making any changes. + */ + +#ifndef __ar9300template_wasp_k31_h__ +#define __ar9300template_wasp_k31_h__ + +static ar9300_eeprom_t ar9300_template_wasp_k31= +{ + + 2, // eepromVersion; + + ar9300_eeprom_template_wasp_k31, // templateVersion; + + {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; + + //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= + + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + + //static OSPREY_BASE_EEP_HEADER baseEepHeader= + + { + {0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written after calibration + 0x33, // txrxMask; //4 bits tx and 4 bits rx + {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 3}, // opCapFlags; + 0, // rfSilent; + 0, // blueToothOptions; + 0, // deviceCap; + 4, // deviceType; // takes lower byte in eeprom location + OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration + {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don + 0x0c, //featureEnable; //bit0 - enable tx temp comp + //bit1 - enable tx volt comp + //bit2 - enable fastClock - default to 1 + //bit3 - enable doubling - default to 1 + //bit4 - enable internal regulator - default to 0 + 0, //miscConfiguration: bit0 - turn down drivestrength + 3, // eepromWriteEnableGpio + 0, // wlanDisableGpio + 8, // wlanLedGpio + 0xff, // rxBandSelectGpio + 0, // txrxgain + 0, // swreg + }, + + + //static OSPREY_MODAL_EEP_HEADER modalHeader2G= + { + + 0x110, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) + 0x22222, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 36, // tempSlope; + 0, // voltSlope; + {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpaBiasLvl; // 1 + 0x0e, // txFrameToDataStart; // 1 + 0x0e, // txFrameToPaOn; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antennaGain; // 1 + 0x2c, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // txFrameToXpaOn; // 1 + 28, // thresh62; // 1 + 0x0c80C080, // papdRateMaskHt20 // 4 + 0x0080C080, // papdRateMaskHt40 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { + 0, // ant_div_control + {0,0}, // base_ext1 + 0, // misc_enable + {0,0,0,0,0,0,0,0}, // temp slop extension + 0, // quick drop low + 0, // quick drop high + }, + + //static A_UINT8 calFreqPier2G[OSPREY_NUM_2G_CAL_PIERS]= + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData2G[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= + + { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + }, + + //A_UINT8 calTarget_freqbin_Cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2484, 1) + }, + + //static CAL_TARGET_POWER_LEG calTarget_freqbin_2G[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG calTargetPowerCck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= + { + //1L-5L,5S,11L,11S + {{36,36,36,36}}, + {{36,36,36,36}} + }, + + //static CAL_TARGET_POWER_LEG calTargetPower2G[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //6-24,36,48,54 + {{32,32,28,24}}, + {{32,32,28,24}}, + {{32,32,28,24}}, + }, + + //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + }, + + //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, + }, + +//static A_UINT8 ctlIndex_2G[OSPREY_NUM_CTLS_2G]= + + { + + 0x11, + 0x12, + 0x15, + 0x17, + 0x41, + 0x42, + 0x45, + 0x47, + 0x31, + 0x32, + 0x35, + 0x37 + + }, + +//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; + + { + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2457, 1), + FREQ2FBIN(2462, 1)}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2422, 1), + FREQ2FBIN(2427, 1), + FREQ2FBIN(2447, 1), + FREQ2FBIN(2452, 1)}, + + {/*Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + /*Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(2484, 1)}, + + {/*Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + FREQ2FBIN(2472, 1), + 0}, + + {/*Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)}, + + {/*Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[9].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[9].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[9].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[10].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[10].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[10].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[11].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[11].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[11].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[11].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)} + }, + + +//OSP_CAL_CTL_DATA_2G ctlPowerData_2G[OSPREY_NUM_CTLS_2G]; + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, + + {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + + }, +#else + { + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, + + {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + }, +#endif + +//static OSPREY_MODAL_EEP_HEADER modalHeader5G= + + { + + 0x440, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) + 0x11111, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x000,0x000,0x000}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 68, // tempSlope; + 0, // voltSlope; + {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpaBiasLvl; // 1 + 0x0e, // txFrameToDataStart; // 1 + 0x0e, // txFrameToPaOn; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antennaGain; // 1 + 0x2d, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // txFrameToXpaOn; // 1 + 28, // thresh62; // 1 + 0x0cf0e0e0, // papdRateMaskHt20 // 4 + 0x6cf0e0e0, // papdRateMaskHt40 // 4 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { // base_ext2 + 0, + 0, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} + }, + +//static A_UINT8 calFreqPier5G[OSPREY_NUM_5G_CAL_PIERS]= + { + //pPiers[0] = + FREQ2FBIN(5180, 0), + //pPiers[1] = + FREQ2FBIN(5220, 0), + //pPiers[2] = + FREQ2FBIN(5320, 0), + //pPiers[3] = + FREQ2FBIN(5400, 0), + //pPiers[4] = + FREQ2FBIN(5500, 0), + //pPiers[5] = + FREQ2FBIN(5600, 0), + //pPiers[6] = + FREQ2FBIN(5725, 0), + //pPiers[7] = + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData5G[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= + + { + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, + + }, + +//static CAL_TARGET_POWER_LEG calTarget_freqbin_5G[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5220, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + + +//static CAL_TARGET_POWER_LEG calTargetPower5G[OSPREY_NUM_5G_20_TARGET_POWERS]= + + + { + //6-24,36,48,54 + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + {{20,20,20,10}}, + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + }, + +//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, + }, + +//static A_UINT8 ctlIndex_5G[OSPREY_NUM_CTLS_5G]= + + { + //pCtlIndex[0] = + 0x10, + //pCtlIndex[1] = + 0x16, + //pCtlIndex[2] = + 0x18, + //pCtlIndex[3] = + 0x40, + //pCtlIndex[4] = + 0x46, + //pCtlIndex[5] = + 0x48, + //pCtlIndex[6] = + 0x30, + //pCtlIndex[7] = + 0x36, + //pCtlIndex[8] = + 0x38 + }, + +// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; + + { + {/* Data[0].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[0].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[0].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[0].ctlEdges[4].bChannel*/FREQ2FBIN(5600, 0), + /* Data[0].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[0].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[0].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[1].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[1].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[1].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[1].ctlEdges[4].bChannel*/FREQ2FBIN(5520, 0), + /* Data[1].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[1].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[1].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[2].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[2].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[2].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[2].ctlEdges[3].bChannel*/FREQ2FBIN(5310, 0), + /* Data[2].ctlEdges[4].bChannel*/FREQ2FBIN(5510, 0), + /* Data[2].ctlEdges[5].bChannel*/FREQ2FBIN(5550, 0), + /* Data[2].ctlEdges[6].bChannel*/FREQ2FBIN(5670, 0), + /* Data[2].ctlEdges[7].bChannel*/FREQ2FBIN(5755, 0)}, + + {/* Data[3].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[3].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[3].ctlEdges[2].bChannel*/FREQ2FBIN(5260, 0), + /* Data[3].ctlEdges[3].bChannel*/FREQ2FBIN(5320, 0), + /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[3].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[3].ctlEdges[6].bChannel*/0xFF, + /* Data[3].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0), + /* Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(5700, 0), + /* Data[4].ctlEdges[4].bChannel*/0xFF, + /* Data[4].ctlEdges[5].bChannel*/0xFF, + /* Data[4].ctlEdges[6].bChannel*/0xFF, + /* Data[4].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(5270, 0), + /* Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(5310, 0), + /* Data[5].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[5].ctlEdges[4].bChannel*/FREQ2FBIN(5590, 0), + /* Data[5].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[5].ctlEdges[6].bChannel*/0xFF, + /* Data[5].ctlEdges[7].bChannel*/0xFF}, + + {/* Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[6].ctlEdges[2].bChannel*/FREQ2FBIN(5220, 0), + /* Data[6].ctlEdges[3].bChannel*/FREQ2FBIN(5260, 0), + /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[6].ctlEdges[5].bChannel*/FREQ2FBIN(5600, 0), + /* Data[6].ctlEdges[6].bChannel*/FREQ2FBIN(5700, 0), + /* Data[6].ctlEdges[7].bChannel*/FREQ2FBIN(5745, 0)}, + + {/* Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(5320, 0), + /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[7].ctlEdges[4].bChannel*/FREQ2FBIN(5560, 0), + /* Data[7].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[7].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[7].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[8].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[8].ctlEdges[4].bChannel*/FREQ2FBIN(5550, 0), + /* Data[8].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[8].ctlEdges[6].bChannel*/FREQ2FBIN(5755, 0), + /* Data[8].ctlEdges[7].bChannel*/FREQ2FBIN(5795, 0)} + }, + +//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{0, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{0, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}}}, + } +#else + { + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 0}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 0}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}}}, + } +#endif +}; + +#endif diff --git a/hal/ar9300/ar9300template_xb112.h b/hal/ar9300/ar9300template_xb112.h new file mode 100644 index 000000000000..864efbab8ce1 --- /dev/null +++ b/hal/ar9300/ar9300template_xb112.h @@ -0,0 +1,750 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * READ THIS NOTICE! + * + * Values defined in this file may only be changed under exceptional circumstances. + * + * Please ask Fiona Cain before making any changes. + */ + +#ifndef __ar9300templateXB112_h__ +#define __ar9300templateXB112_h__ + +static ar9300_eeprom_t ar9300_template_xb112= +{ + + 2, // eeprom_version; + + ar9300_eeprom_template_xb112, // template_version; + + {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; + + //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= + + {"xb112-041-f0000"}, +// {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + + //static OSPREY_BASE_EEP_HEADER base_eep_header= + + { + {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration + 0x77, // txrx_mask; //4 bits tx and 4 bits rx + {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags; + 0, // rf_silent; + 0, // blue_tooth_options; + 0, // device_cap; + 5, // device_type; // takes lower byte in eeprom location + OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration + {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don + 0x0d, //feature_enable; //bit0 - enable tx temp comp + //bit1 - enable tx volt comp + //bit2 - enable fastClock - default to 1 + //bit3 - enable doubling - default to 1 + //bit4 - enable internal regulator - default to 0 + //bit5 - enable paprd -- default to 0 + 0, //misc_configuration: bit0 - turn down drivestrength + 6, // eeprom_write_enable_gpio + 0, // wlan_disable_gpio + 8, // wlan_led_gpio + 0xff, // rx_band_select_gpio + 0, // txrxgain + 0, // swreg + }, + + + //static OSPREY_MODAL_EEP_HEADER modal_header_2g= + { + + 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x22222, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x10,0x10,0x10}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0x1b,0x1b,0x1b}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0x15,0x15,0x15}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 50, // temp_slope; + 0, // voltSlope; + {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2c, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0c80C080, // paprd_rate_mask_ht20 // 4 + 0x0080C080, // paprd_rate_mask_ht40 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { + 0, // ant_div_control + {0,0}, // base_ext1 + 0, // misc_enable + {0,0,0,0,0,0,0,0}, // temp slop extension + 0, // quick drop low + 0, // quick drop high + }, + + //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2462, 1) + }, + + //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= + + { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + }, + + //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= + { + //1L-5L,5S,11L,11S + {{38,38,38,38}}, + {{38,38,38,38}} + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //6-24,36,48,54 + {{38,38,36,34}}, + {{38,38,36,34}}, + {{38,38,34,32}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{36,36,36,36,36,34,34,32,30,28,28,28,28,26}}, + {{36,36,36,36,36,34,36,34,32,30,30,30,28,26}}, + {{36,36,36,36,36,34,34,32,30,28,28,28,28,26}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{36,36,36,36,34,32,32,30,28,26,26,26,26,24}}, + {{36,36,36,36,34,32,34,32,30,28,28,28,28,24}}, + {{36,36,36,36,34,32,32,30,28,26,26,26,26,24}}, + }, + +//static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= + + { + + 0x11, + 0x12, + 0x15, + 0x17, + 0x41, + 0x42, + 0x45, + 0x47, + 0x31, + 0x32, + 0x35, + 0x37 + + }, + +//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; + + { + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2457, 1), + FREQ2FBIN(2462, 1)}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2422, 1), + FREQ2FBIN(2427, 1), + FREQ2FBIN(2447, 1), + FREQ2FBIN(2452, 1)}, + + {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, + + {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + FREQ2FBIN(2472, 1), + 0}, + + {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, + + {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} + }, + + +//OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, + + {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + + }, +#else + { + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, + + {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + }, +#endif + +//static OSPREY_MODAL_EEP_HEADER modal_header_5g= + + { + + 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x22222, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x000,0x000,0x000}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0x13,0x19,0x17}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0x19,0x19,0x19}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 70, // temp_slope; + 15, // voltSlope; + {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2d, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 + 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { // base_ext2 + 72, // tempSlopeL; + 105, // tempSlopeH; + {0x10,0x14,0x10}, // xatten1_db_low + {0x19,0x19,0x19}, // xatten1_margin_low + {0x1d,0x20,0x24}, // xatten1_db_high + {0x10,0x10,0x10} // xatten1_margin_high + }, + +//static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= + { + //pPiers[0] = + FREQ2FBIN(5180, 0), + //pPiers[1] = + FREQ2FBIN(5220, 0), + //pPiers[2] = + FREQ2FBIN(5320, 0), + //pPiers[3] = + FREQ2FBIN(5400, 0), + //pPiers[4] = + FREQ2FBIN(5500, 0), + //pPiers[5] = + FREQ2FBIN(5600, 0), + //pPiers[6] = + FREQ2FBIN(5700, 0), + //pPiers[7] = + FREQ2FBIN(5785, 0) + }, + +//static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= + + { + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + + }, + +//static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5220, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5220, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5220, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5600, 0), + FREQ2FBIN(5725, 0), + FREQ2FBIN(5825, 0) + }, + + +//static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + + { + //6-24,36,48,54 + {{32,32,28,26}}, + {{32,32,28,26}}, + {{32,32,28,26}}, + {{32,32,26,24}}, + {{32,32,26,24}}, + {{32,32,24,22}}, + {{30,30,24,22}}, + {{30,30,24,22}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,28,26,32,28,26,24,24,24,22,22}}, + {{32,32,32,32,28,26,32,28,26,24,24,24,22,22}}, + {{32,32,32,32,28,26,32,28,26,24,24,24,22,22}}, + {{32,32,32,32,28,26,32,26,24,22,22,22,20,20}}, + {{32,32,32,32,28,26,32,26,24,22,20,18,16,16}}, + {{32,32,32,32,28,26,32,24,20,16,18,16,14,14}}, + {{30,30,30,30,28,26,30,24,20,16,18,16,14,14}}, + {{30,30,30,30,28,26,30,24,20,16,18,16,14,14}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,30,28,26,30,28,26,24,24,24,22,22}}, + {{32,32,32,30,28,26,30,28,26,24,24,24,22,22}}, + {{32,32,32,30,28,26,30,28,26,24,24,24,22,22}}, + {{32,32,32,30,28,26,30,26,24,22,22,22,20,20}}, + {{32,32,32,30,28,26,30,26,24,22,20,18,16,16}}, + {{32,32,32,30,28,26,30,22,20,16,18,16,14,14}}, + {{30,30,30,30,28,26,30,22,20,16,18,16,14,14}}, + {{30,30,30,30,28,26,30,22,20,16,18,16,14,14}}, + }, + +//static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= + + { + //pCtlIndex[0] = + 0x10, + //pCtlIndex[1] = + 0x16, + //pCtlIndex[2] = + 0x18, + //pCtlIndex[3] = + 0x40, + //pCtlIndex[4] = + 0x46, + //pCtlIndex[5] = + 0x48, + //pCtlIndex[6] = + 0x30, + //pCtlIndex[7] = + 0x36, + //pCtlIndex[8] = + 0x38 + }, + +// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; + + { + {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), + /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), + /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), + /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), + /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), + /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), + /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, + + {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), + /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), + /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[3].ctl_edges[6].bChannel*/0xFF, + /* Data[3].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), + /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), + /* Data[4].ctl_edges[4].bChannel*/0xFF, + /* Data[4].ctl_edges[5].bChannel*/0xFF, + /* Data[4].ctl_edges[6].bChannel*/0xFF, + /* Data[4].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), + /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), + /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), + /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[5].ctl_edges[6].bChannel*/0xFF, + /* Data[5].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), + /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), + /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), + /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), + /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, + + {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), + /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), + /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), + /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), + /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} + }, + +//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{0, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{0, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}}}, + } +#else + { + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 0}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 0}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}}}, + } +#endif +}; + +#endif diff --git a/hal/ar9300/ar9300template_xb113.h b/hal/ar9300/ar9300template_xb113.h new file mode 100644 index 000000000000..7b715455a6cb --- /dev/null +++ b/hal/ar9300/ar9300template_xb113.h @@ -0,0 +1,750 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * READ THIS NOTICE! + * + * Values defined in this file may only be changed under exceptional circumstances. + * + * Please ask Fiona Cain before making any changes. + */ + +#ifndef __ar9300templateXB113_h__ +#define __ar9300templateXB113_h__ + +static ar9300_eeprom_t ar9300_template_xb113= +{ + + 2, // eeprom_version; + + ar9300_eeprom_template_xb113, // template_version; + + {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; + + //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= + + {"xb113-023-f0000"}, +// {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + + //static OSPREY_BASE_EEP_HEADER base_eep_header= + + { + {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration + 0x77, // txrx_mask; //4 bits tx and 4 bits rx + { AR9300_OPFLAGS_11A, 0}, // op_cap_flags; + 0, // rf_silent; + 0, // blue_tooth_options; + 0, // device_cap; + 5, // device_type; // takes lower byte in eeprom location + OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration + {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don + 0x0d, //feature_enable; //bit0 - enable tx temp comp + //bit1 - enable tx volt comp + //bit2 - enable fastClock - default to 1 + //bit3 - enable doubling - default to 1 + //bit4 - enable internal regulator - default to 0 + //bit5 - enable paprd -- default to 0 + 0, //misc_configuration: bit0 - turn down drivestrength + 6, // eeprom_write_enable_gpio + 0, // wlan_disable_gpio + 8, // wlan_led_gpio + 0xff, // rx_band_select_gpio + 0x21, // txrxgain + 0, // swreg + }, + + + //static OSPREY_MODAL_EEP_HEADER modal_header_2g= + { + + 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 25, // temp_slope; + 0, // voltSlope; + {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2c, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0c80C080, // paprd_rate_mask_ht20 // 4 + 0x0080C080, // paprd_rate_mask_ht40 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { + 0, // ant_div_control + {0,0}, // base_ext1 + 0, // misc_enable + {0,0,0,0,0,0,0,0}, // temp slop extension + 0, // quick drop low + 0, // quick drop high + }, + + //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2462, 1) + }, + + //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= + + { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + }, + + //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; + + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] + { + FREQ2FBIN(2412, 1), + FREQ2FBIN(2437, 1), + FREQ2FBIN(2472, 1) + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= + { + //1L-5L,5S,11L,11S + {{34,34,34,34}}, + {{34,34,34,34}} + }, + + //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //6-24,36,48,54 + {{34,34,32,32}}, + {{34,34,32,32}}, + {{34,34,32,32}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{32,32,32,32,32,28,32,32,30,28,0,0,0,0}}, + {{32,32,32,32,32,28,32,32,30,28,0,0,0,0}}, + {{32,32,32,32,32,28,32,32,30,28,0,0,0,0}}, + }, + + //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, + {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, + {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, + }, + +//static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= + + { + + 0x11, + 0x12, + 0x15, + 0x17, + 0x41, + 0x42, + 0x45, + 0x47, + 0x31, + 0x32, + 0x35, + 0x37 + + }, + +//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; + + { + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2457, 1), + FREQ2FBIN(2462, 1)}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2412, 1), + FREQ2FBIN(2417, 1), + FREQ2FBIN(2462, 1), + 0xFF}, + + {FREQ2FBIN(2422, 1), + FREQ2FBIN(2427, 1), + FREQ2FBIN(2447, 1), + FREQ2FBIN(2452, 1)}, + + {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, + + {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + FREQ2FBIN(2472, 1), + 0}, + + {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, + + {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), + /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), + /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), + 0}, + + {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), + /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), + /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), + /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} + }, + + +//OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, + + {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + + {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, + + }, +#else + { + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, + + {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, + }, +#endif + +//static OSPREY_MODAL_EEP_HEADER modal_header_5g= + + { + + 0x220, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) + 0x11111, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 + {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) + {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) + {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 + 68, // temp_slope; + 0, // voltSlope; + {FREQ2FBIN(5500, 0),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format + {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain + {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved + 0, // quick drop + 0xf, // xpa_bias_lvl; // 1 + 0x0e, // tx_frame_to_data_start; // 1 + 0x0e, // tx_frame_to_pa_on; // 1 + 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck + 0, // antenna_gain; // 1 + 0x2d, // switchSettling; // 1 + -30, // adcDesiredSize; // 1 + 0, // txEndToXpaOff; // 1 + 0x2, // txEndToRxOn; // 1 + 0xe, // tx_frame_to_xpa_on; // 1 + 28, // thresh62; // 1 + 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 + 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 + 0, // switchcomspdt; // 2 + 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 + 0, // rf_gain_cap + 0, // tx_gain_cap + {0,0,0,0,0} //futureModal[5]; + }, + + { // base_ext2 + 72, // tempSlopeL; + 105, // tempSlopeH; + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} + }, + +//static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= + { + //pPiers[0] = + FREQ2FBIN(5180, 0), + //pPiers[1] = + FREQ2FBIN(5240, 0), + //pPiers[2] = + FREQ2FBIN(5320, 0), + //pPiers[3] = + FREQ2FBIN(5400, 0), + //pPiers[4] = + FREQ2FBIN(5500, 0), + //pPiers[5] = + FREQ2FBIN(5700, 0), + //pPiers[6] = + FREQ2FBIN(5745, 0), + //pPiers[7] = + FREQ2FBIN(5785, 0), + }, + +//static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= + + { + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, + + }, + +//static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5785, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + FREQ2FBIN(5180, 0), + FREQ2FBIN(5240, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5400, 0), + FREQ2FBIN(5500, 0), + FREQ2FBIN(5700, 0), + FREQ2FBIN(5745, 0), + FREQ2FBIN(5825, 0) + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + + { + FREQ2FBIN(5190, 0), + FREQ2FBIN(5230, 0), + FREQ2FBIN(5320, 0), + FREQ2FBIN(5410, 0), + FREQ2FBIN(5510, 0), + FREQ2FBIN(5670, 0), + FREQ2FBIN(5755, 0), + FREQ2FBIN(5785, 0) + }, + + +//static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= + + + { + //6-24,36,48,54 + {{42,40,40,34}}, + {{42,40,40,34}}, + {{42,40,40,34}}, + {{42,40,40,34}}, + {{42,40,40,34}}, + {{42,40,40,34}}, + {{42,40,40,34}}, + {{42,40,40,34}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= + + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{40,40,40,40,32,28,40,40,32,28,40,40,32,20}}, + {{40,40,40,40,32,28,40,40,32,28,40,40,32,20}}, + {{40,40,40,40,32,28,40,40,32,28,40,40,32,20}}, + {{40,40,40,40,32,28,40,40,32,28,40,40,32,20}}, + {{40,40,40,40,32,28,40,40,32,28,40,40,32,20}}, + {{40,40,40,40,32,28,40,40,32,28,40,40,32,20}}, + {{38,38,38,38,32,28,38,38,32,28,38,38,32,26}}, + {{36,36,36,36,32,28,36,36,32,28,36,36,32,26}}, + }, + +//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= + { + //0_8_16,1-3_9-11_17-19, + // 4,5,6,7,12,13,14,15,20,21,22,23 + {{40,40,40,38,30,26,40,40,30,26,40,40,30,24}}, + {{40,40,40,38,30,26,40,40,30,26,40,40,30,24}}, + {{40,40,40,38,30,26,40,40,30,26,40,40,30,24}}, + {{40,40,40,38,30,26,40,40,30,26,40,40,30,24}}, + {{40,40,40,38,30,26,40,40,30,26,40,40,30,24}}, + {{40,40,40,38,30,26,40,40,30,26,40,40,30,24}}, + {{36,36,36,36,30,26,36,36,30,26,36,36,30,24}}, + {{34,34,34,34,30,26,34,34,30,26,34,34,30,24}}, + }, + +//static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= + + { + //pCtlIndex[0] = + 0x10, + //pCtlIndex[1] = + 0x16, + //pCtlIndex[2] = + 0x18, + //pCtlIndex[3] = + 0x40, + //pCtlIndex[4] = + 0x46, + //pCtlIndex[5] = + 0x48, + //pCtlIndex[6] = + 0x30, + //pCtlIndex[7] = + 0x36, + //pCtlIndex[8] = + 0x38 + }, + +// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; + + { + {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), + /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), + /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), + /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), + /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), + /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), + /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), + /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, + + {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), + /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), + /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[3].ctl_edges[6].bChannel*/0xFF, + /* Data[3].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), + /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), + /* Data[4].ctl_edges[4].bChannel*/0xFF, + /* Data[4].ctl_edges[5].bChannel*/0xFF, + /* Data[4].ctl_edges[6].bChannel*/0xFF, + /* Data[4].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), + /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), + /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), + /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[5].ctl_edges[6].bChannel*/0xFF, + /* Data[5].ctl_edges[7].bChannel*/0xFF}, + + {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), + /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), + /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), + /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), + /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), + /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), + /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, + + {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), + /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), + /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), + /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), + /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), + /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), + /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), + /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, + + {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), + /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), + /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), + /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), + /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), + /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), + /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), + /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} + }, + +//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN + { + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{0, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{0, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {0, 60}, + {0, 60}}}, + + {{{1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}}}, + + {{{1, 60}, + {1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}}}, + + {{{1, 60}, + {0, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {1, 60}, + {0, 60}, + {1, 60}}}, + } +#else + { + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 0}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 0}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 0}, + {60, 0}}}, + + {{{60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}}}, + + {{{60, 1}, + {60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}}}, + + {{{60, 1}, + {60, 0}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 1}, + {60, 0}, + {60, 1}}}, + } +#endif +}; + +#endif diff --git a/hal/ar9300/ar9330_11.ini b/hal/ar9300/ar9330_11.ini new file mode 100644 index 000000000000..da88de6d7593 --- /dev/null +++ b/hal/ar9300/ar9330_11.ini @@ -0,0 +1,1356 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +static const u_int32_t ar9331_modes_lowest_ob_db_tx_gain_hornet1_1[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2d8 , 0x7999a83a , 0x7999a83a , 0x7999a83a , 0x7999a83a }, + { 0x0000a2dc , 0xffff2a52 , 0xffff2a52 , 0xffff2a52 , 0xffff2a52 }, + { 0x0000a2e0 , 0xffffcc84 , 0xffffcc84 , 0xffffcc84 , 0xffffcc84 }, + { 0x0000a2e4 , 0xfffff000 , 0xfffff000 , 0xfffff000 , 0xfffff000 }, + { 0x0000a2e8 , 0xfffe0000 , 0xfffe0000 , 0xfffe0000 , 0xfffe0000 }, + { 0x0000a410 , 0x000050d7 , 0x000050d7 , 0x000050d0 , 0x000050d0 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x23000a00 , 0x23000a00 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x27000a02 , 0x27000a02 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2b000a04 , 0x2b000a04 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2d000a20 , 0x2d000a20 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x31000a22 , 0x31000a22 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x35000a24 , 0x35000a24 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x38000a43 , 0x38000a43 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x3b000e42 , 0x3b000e42 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x3f000e44 , 0x3f000e44 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x42000e64 , 0x42000e64 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x46000e66 , 0x46000e66 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a580 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a584 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a588 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a58c , 0x11062202 , 0x11062202 , 0x0b000200 , 0x0b000200 }, + { 0x0000a590 , 0x17022e00 , 0x17022e00 , 0x0f000202 , 0x0f000202 }, + { 0x0000a594 , 0x1d000ec2 , 0x1d000ec2 , 0x11000400 , 0x11000400 }, + { 0x0000a598 , 0x25020ec0 , 0x25020ec0 , 0x15000402 , 0x15000402 }, + { 0x0000a59c , 0x2b020ec3 , 0x2b020ec3 , 0x19000404 , 0x19000404 }, + { 0x0000a5a0 , 0x2f001f04 , 0x2f001f04 , 0x1b000603 , 0x1b000603 }, + { 0x0000a5a4 , 0x35001fc4 , 0x35001fc4 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a5a8 , 0x3c022f04 , 0x3c022f04 , 0x23000a04 , 0x23000a04 }, + { 0x0000a5ac , 0x41023e85 , 0x41023e85 , 0x26000a20 , 0x26000a20 }, + { 0x0000a5b0 , 0x48023ec6 , 0x48023ec6 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a5b4 , 0x4d023f01 , 0x4d023f01 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a5b8 , 0x53023f4b , 0x53023f4b , 0x31000e24 , 0x31000e24 }, + { 0x0000a5bc , 0x5a027f09 , 0x5a027f09 , 0x34001640 , 0x34001640 }, + { 0x0000a5c0 , 0x5f027fc9 , 0x5f027fc9 , 0x38001660 , 0x38001660 }, + { 0x0000a5c4 , 0x6502feca , 0x6502feca , 0x3b001861 , 0x3b001861 }, + { 0x0000a5c8 , 0x6b02ff4a , 0x6b02ff4a , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a5cc , 0x7203feca , 0x7203feca , 0x42001a83 , 0x42001a83 }, + { 0x0000a5d0 , 0x7703ff0b , 0x7703ff0b , 0x44001c84 , 0x44001c84 }, + { 0x0000a5d4 , 0x7d06ffcb , 0x7d06ffcb , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a5d8 , 0x8407ff0b , 0x8407ff0b , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a5dc , 0x8907ffcb , 0x8907ffcb , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a5e0 , 0x900fff0b , 0x900fff0b , 0x54001ceb , 0x54001ceb }, + { 0x0000a5e4 , 0x960fffcb , 0x960fffcb , 0x56001eec , 0x56001eec }, + { 0x0000a5e8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5ec , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f0 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f4 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5fc , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008802 , 0x02008802 }, + { 0x0000a620 , 0x0280c802 , 0x0280c802 , 0x0280c802 , 0x0280c802 }, + { 0x0000a624 , 0x03010a03 , 0x03010a03 , 0x03010a03 , 0x03010a03 }, + { 0x0000a628 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a62c , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a630 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a634 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a638 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a63c , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x00016044 , 0x034922db , 0x034922db , 0x034922db , 0x034922db }, + { 0x00016284 , 0x14d3f000 , 0x14d3f000 , 0x14d3f000 , 0x14d3f000 }, +}; + +static const u_int32_t ar9331_hornet1_1_baseband_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 }, + { 0x00009820 , 0x206a002e , 0x206a002e , 0x206a002e , 0x206a002e }, + { 0x00009824 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 }, + { 0x00009828 , 0x06903081 , 0x06903081 , 0x06903881 , 0x06903881 }, + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000059c , 0x0000059c }, + { 0x00009c00 , 0x00000044 , 0x00000044 , 0x00000044 , 0x00000044 }, + { 0x00009e00 , 0x0372161e , 0x0372161e , 0x037216a4 , 0x037216a4 }, + { 0x00009e04 , 0x00202020 , 0x00202020 , 0x00202020 , 0x00202020 }, + { 0x00009e0c , 0x6c4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + { 0x00009e10 , 0x7ec80d2e , 0x7ec80d2e , 0x7ec80d2e , 0x7ec80d2e }, + { 0x00009e14 , 0x31365d5e , 0x3136605e , 0x3136605e , 0x31365d5e }, + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + { 0x00009e2c , 0x0000001c , 0x0000001c , 0x00003221 , 0x00003221 }, + { 0x00009e3c , 0xcf946222 , 0xcf946222 , 0xcf946222 , 0xcf946222 }, + { 0x00009e44 , 0x02321e27 , 0x02321e27 , 0x02282324 , 0x02282324 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302010 , 0x50302010 }, + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, + { 0x0000a204 , 0x00003fc0 , 0x00003fc4 , 0x00003fc4 , 0x00003fc0 }, + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + { 0x0000a230 , 0x0000000a , 0x00000014 , 0x00000016 , 0x0000000b }, + { 0x0000a234 , 0x00000fff , 0x00000fff , 0x10000fff , 0x00000fff }, + { 0x0000a238 , 0xffb81018 , 0xffb81018 , 0xffb81018 , 0xffb81018 }, + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a260 , 0x3a021501 , 0x3a021501 , 0x3a021501 , 0x3a021501 }, + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a288 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a28c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2d0 , 0x00071982 , 0x00071982 , 0x00071982 , 0x00071982 }, + { 0x0000a2d8 , 0xf999a83a , 0xf999a83a , 0xf999a83a , 0xf999a83a }, + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000ae04 , 0x00802020 , 0x00802020 , 0x00802020 , 0x00802020 }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +}; + +static const u_int32_t ar9331_modes_high_ob_db_tx_gain_hornet1_1[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2d8 , 0x7999a83a , 0x7999a83a , 0x7999a83a , 0x7999a83a }, + { 0x0000a2dc , 0xffaa9a52 , 0xffaa9a52 , 0xffaa9a52 , 0xffaa9a52 }, + { 0x0000a2e0 , 0xffb31c84 , 0xffb31c84 , 0xffb31c84 , 0xffb31c84 }, + { 0x0000a2e4 , 0xff43e000 , 0xff43e000 , 0xff43e000 , 0xff43e000 }, + { 0x0000a2e8 , 0xfffc0000 , 0xfffc0000 , 0xfffc0000 , 0xfffc0000 }, + { 0x0000a410 , 0x000050d7 , 0x000050d7 , 0x000050d7 , 0x000050d7 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x23000a00 , 0x23000a00 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x27000a02 , 0x27000a02 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2b000a04 , 0x2b000a04 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x3d001620 , 0x3d001620 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x3f001621 , 0x3f001621 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x42001640 , 0x42001640 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x44001641 , 0x44001641 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x46001642 , 0x46001642 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x49001644 , 0x49001644 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4c001a81 , 0x4c001a81 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4f001a83 , 0x4f001a83 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x52001c84 , 0x52001c84 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x55001ce3 , 0x55001ce3 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x59001ce5 , 0x59001ce5 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5d001ce9 , 0x5d001ce9 }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x64001eec , 0x64001eec }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x64001eec , 0x64001eec }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x64001eec , 0x64001eec }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x64001eec , 0x64001eec }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x64001eec , 0x64001eec }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x64001eec , 0x64001eec }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x64001eec , 0x64001eec }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x64001eec , 0x64001eec }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x64001eec , 0x64001eec }, + { 0x0000a580 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a584 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a588 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a58c , 0x11062202 , 0x11062202 , 0x0b000200 , 0x0b000200 }, + { 0x0000a590 , 0x17022e00 , 0x17022e00 , 0x0f000202 , 0x0f000202 }, + { 0x0000a594 , 0x1d000ec2 , 0x1d000ec2 , 0x11000400 , 0x11000400 }, + { 0x0000a598 , 0x25020ec0 , 0x25020ec0 , 0x15000402 , 0x15000402 }, + { 0x0000a59c , 0x2b020ec3 , 0x2b020ec3 , 0x19000404 , 0x19000404 }, + { 0x0000a5a0 , 0x2f001f04 , 0x2f001f04 , 0x1b000603 , 0x1b000603 }, + { 0x0000a5a4 , 0x35001fc4 , 0x35001fc4 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a5a8 , 0x3c022f04 , 0x3c022f04 , 0x23000a04 , 0x23000a04 }, + { 0x0000a5ac , 0x41023e85 , 0x41023e85 , 0x26000a20 , 0x26000a20 }, + { 0x0000a5b0 , 0x48023ec6 , 0x48023ec6 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a5b4 , 0x4d023f01 , 0x4d023f01 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a5b8 , 0x53023f4b , 0x53023f4b , 0x31000e24 , 0x31000e24 }, + { 0x0000a5bc , 0x5a027f09 , 0x5a027f09 , 0x34001640 , 0x34001640 }, + { 0x0000a5c0 , 0x5f027fc9 , 0x5f027fc9 , 0x38001660 , 0x38001660 }, + { 0x0000a5c4 , 0x6502feca , 0x6502feca , 0x3b001861 , 0x3b001861 }, + { 0x0000a5c8 , 0x6b02ff4a , 0x6b02ff4a , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a5cc , 0x7203feca , 0x7203feca , 0x42001a83 , 0x42001a83 }, + { 0x0000a5d0 , 0x7703ff0b , 0x7703ff0b , 0x44001c84 , 0x44001c84 }, + { 0x0000a5d4 , 0x7d06ffcb , 0x7d06ffcb , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a5d8 , 0x8407ff0b , 0x8407ff0b , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a5dc , 0x8907ffcb , 0x8907ffcb , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a5e0 , 0x900fff0b , 0x900fff0b , 0x54001ceb , 0x54001ceb }, + { 0x0000a5e4 , 0x960fffcb , 0x960fffcb , 0x56001eec , 0x56001eec }, + { 0x0000a5e8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5ec , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f0 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f4 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5fc , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x02008501 , 0x02008501 , 0x02008501 , 0x02008501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008802 , 0x02008802 }, + { 0x0000a620 , 0x0280c802 , 0x0280c802 , 0x0280c802 , 0x0280c802 }, + { 0x0000a624 , 0x0280ca03 , 0x0280ca03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a628 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a62c , 0x04015005 , 0x04015005 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04015005 , 0x04015005 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04015005 , 0x04015005 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04015005 , 0x04015005 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04015005 , 0x04015005 , 0x04015005 , 0x04015005 }, +}; + +static const u_int32_t ar9331_modes_low_ob_db_tx_gain_hornet1_1[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2d8 , 0x7999a83a , 0x7999a83a , 0x7999a83a , 0x7999a83a }, + { 0x0000a2dc , 0xffff2a52 , 0xffff2a52 , 0xffff2a52 , 0xffff2a52 }, + { 0x0000a2e0 , 0xffffcc84 , 0xffffcc84 , 0xffffcc84 , 0xffffcc84 }, + { 0x0000a2e4 , 0xfffff000 , 0xfffff000 , 0xfffff000 , 0xfffff000 }, + { 0x0000a2e8 , 0xfffe0000 , 0xfffe0000 , 0xfffe0000 , 0xfffe0000 }, + { 0x0000a410 , 0x000050d7 , 0x000050d7 , 0x000050d0 , 0x000050d0 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x23000a00 , 0x23000a00 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x27000a02 , 0x27000a02 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2b000a04 , 0x2b000a04 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2d000a20 , 0x2d000a20 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x31000a22 , 0x31000a22 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x35000a24 , 0x35000a24 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x38000a43 , 0x38000a43 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x3b000e42 , 0x3b000e42 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x3f000e44 , 0x3f000e44 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x42000e64 , 0x42000e64 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x46000e66 , 0x46000e66 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a580 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a584 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a588 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a58c , 0x11062202 , 0x11062202 , 0x0b000200 , 0x0b000200 }, + { 0x0000a590 , 0x17022e00 , 0x17022e00 , 0x0f000202 , 0x0f000202 }, + { 0x0000a594 , 0x1d000ec2 , 0x1d000ec2 , 0x11000400 , 0x11000400 }, + { 0x0000a598 , 0x25020ec0 , 0x25020ec0 , 0x15000402 , 0x15000402 }, + { 0x0000a59c , 0x2b020ec3 , 0x2b020ec3 , 0x19000404 , 0x19000404 }, + { 0x0000a5a0 , 0x2f001f04 , 0x2f001f04 , 0x1b000603 , 0x1b000603 }, + { 0x0000a5a4 , 0x35001fc4 , 0x35001fc4 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a5a8 , 0x3c022f04 , 0x3c022f04 , 0x23000a04 , 0x23000a04 }, + { 0x0000a5ac , 0x41023e85 , 0x41023e85 , 0x26000a20 , 0x26000a20 }, + { 0x0000a5b0 , 0x48023ec6 , 0x48023ec6 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a5b4 , 0x4d023f01 , 0x4d023f01 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a5b8 , 0x53023f4b , 0x53023f4b , 0x31000e24 , 0x31000e24 }, + { 0x0000a5bc , 0x5a027f09 , 0x5a027f09 , 0x34001640 , 0x34001640 }, + { 0x0000a5c0 , 0x5f027fc9 , 0x5f027fc9 , 0x38001660 , 0x38001660 }, + { 0x0000a5c4 , 0x6502feca , 0x6502feca , 0x3b001861 , 0x3b001861 }, + { 0x0000a5c8 , 0x6b02ff4a , 0x6b02ff4a , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a5cc , 0x7203feca , 0x7203feca , 0x42001a83 , 0x42001a83 }, + { 0x0000a5d0 , 0x7703ff0b , 0x7703ff0b , 0x44001c84 , 0x44001c84 }, + { 0x0000a5d4 , 0x7d06ffcb , 0x7d06ffcb , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a5d8 , 0x8407ff0b , 0x8407ff0b , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a5dc , 0x8907ffcb , 0x8907ffcb , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a5e0 , 0x900fff0b , 0x900fff0b , 0x54001ceb , 0x54001ceb }, + { 0x0000a5e4 , 0x960fffcb , 0x960fffcb , 0x56001eec , 0x56001eec }, + { 0x0000a5e8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5ec , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f0 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f4 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5fc , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008802 , 0x02008802 }, + { 0x0000a620 , 0x0280c802 , 0x0280c802 , 0x0280c802 , 0x0280c802 }, + { 0x0000a624 , 0x03010a03 , 0x03010a03 , 0x03010a03 , 0x03010a03 }, + { 0x0000a628 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a62c , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a630 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a634 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a638 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a63c , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x00016044 , 0x034922db , 0x034922db , 0x034922db , 0x034922db }, + { 0x00016284 , 0x14d3f000 , 0x14d3f000 , 0x14d3f000 , 0x14d3f000 }, +}; + +static const u_int32_t ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484[][2] = { +/* Addr allmodes */ + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x6f7f0301 }, + { 0x0000a3a0 , 0xca9228ee }, +}; + +static const u_int32_t ar9331_hornet1_1_xtal_25M[][2] = { +/* Addr allmodes */ + { 0x00007038 , 0x000002f8 }, + { 0x00008244 , 0x0010f3d7 }, + { 0x0000824c , 0x0001e7ae }, + { 0x0001609c , 0x0f508f29 }, +}; + +static const u_int32_t ar9331_hornet1_1_radio_core[][2] = { +/* Addr allmodes */ + { 0x00016000 , 0x36db6db6 }, + { 0x00016004 , 0x6db6db40 }, + { 0x00016008 , 0x73800000 }, + { 0x0001600c , 0x00000000 }, + { 0x00016040 , 0x7f80fff8 }, + { 0x00016044 , 0x03db62db }, + { 0x00016048 , 0x6c924268 }, + { 0x0001604c , 0x000f0278 }, + { 0x00016050 , 0x4db6db8c }, + { 0x00016054 , 0x6db60000 }, + { 0x00016080 , 0x00080000 }, + { 0x00016084 , 0x0e48048c }, + { 0x00016088 , 0x14214514 }, + { 0x0001608c , 0x119f081c }, + { 0x00016090 , 0x24926490 }, + { 0x00016098 , 0xd411eb84 }, + { 0x000160a0 , 0xc2108ffe }, + { 0x000160a4 , 0x812fc370 }, + { 0x000160a8 , 0x423c8000 }, + { 0x000160ac , 0x24651800 }, + { 0x000160b0 , 0x03284f3e }, + { 0x000160b4 , 0x92480040 }, + { 0x000160c0 , 0x006db6db }, + { 0x000160c4 , 0x0186db60 }, + { 0x000160c8 , 0x6db4db6c }, + { 0x000160cc , 0x6de6c300 }, + { 0x000160d0 , 0x14500820 }, + { 0x00016100 , 0x04cb0001 }, + { 0x00016104 , 0xfff80015 }, + { 0x00016108 , 0x00080010 }, + { 0x0001610c , 0x00170000 }, + { 0x00016140 , 0x10800000 }, + { 0x00016144 , 0x01884080 }, + { 0x00016148 , 0x000080c0 }, + { 0x00016280 , 0x01000015 }, + { 0x00016284 , 0x14d20000 }, + { 0x00016288 , 0x00318000 }, + { 0x0001628c , 0x50000000 }, + { 0x00016290 , 0x4b96210f }, + { 0x00016380 , 0x00000000 }, + { 0x00016384 , 0x00000000 }, + { 0x00016388 , 0x00800700 }, + { 0x0001638c , 0x00800700 }, + { 0x00016390 , 0x00800700 }, + { 0x00016394 , 0x00000000 }, + { 0x00016398 , 0x00000000 }, + { 0x0001639c , 0x00000000 }, + { 0x000163a0 , 0x00000001 }, + { 0x000163a4 , 0x00000001 }, + { 0x000163a8 , 0x00000000 }, + { 0x000163ac , 0x00000000 }, + { 0x000163b0 , 0x00000000 }, + { 0x000163b4 , 0x00000000 }, + { 0x000163b8 , 0x00000000 }, + { 0x000163bc , 0x00000000 }, + { 0x000163c0 , 0x000000a0 }, + { 0x000163c4 , 0x000c0000 }, + { 0x000163c8 , 0x14021402 }, + { 0x000163cc , 0x00001402 }, + { 0x000163d0 , 0x00000000 }, + { 0x000163d4 , 0x00000000 }, +}; + +static const u_int32_t ar9331_hornet1_1_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e3c , 0xcf946221 , 0xcf946221 , 0xcf946221 , 0xcf946221 }, + { 0x00009e44 , 0x005c0000 , 0x005c0000 , 0x005c0000 , 0x005c0000 }, + { 0x0000a2d8 , 0x7999a800 , 0x7999a800 , 0x7999a80c , 0x7999a80c }, +}; + +static const u_int32_t ar9331_hornet1_1_mac_core_emulation[][2] = { +/* Addr allmodes */ + { 0x0000805c , 0xffffc7ff }, + { 0x00008344 , 0xaa4a105b }, +}; + +static const u_int32_t ar9331_hornet1_1_emulation_baseband_core[][2] = { +/* Addr allmodes */ + { 0x0000a344 , 0x00000010 }, +}; + +static const u_int32_t ar9331_hornet1_1_soc_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00007010 , 0x00000022 , 0x00000022 , 0x00000022 , 0x00000022 }, +}; + +static const u_int32_t ar9331_common_wo_xlna_rx_gain_hornet1_1[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00060005 }, + { 0x0000a004 , 0x00810080 }, + { 0x0000a008 , 0x00830082 }, + { 0x0000a00c , 0x00850084 }, + { 0x0000a010 , 0x01820181 }, + { 0x0000a014 , 0x01840183 }, + { 0x0000a018 , 0x01880185 }, + { 0x0000a01c , 0x018a0189 }, + { 0x0000a020 , 0x02850284 }, + { 0x0000a024 , 0x02890288 }, + { 0x0000a028 , 0x028b028a }, + { 0x0000a02c , 0x03850384 }, + { 0x0000a030 , 0x03890388 }, + { 0x0000a034 , 0x038b038a }, + { 0x0000a038 , 0x038d038c }, + { 0x0000a03c , 0x03910390 }, + { 0x0000a040 , 0x03930392 }, + { 0x0000a044 , 0x03950394 }, + { 0x0000a048 , 0x00000396 }, + { 0x0000a04c , 0x00000000 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x28282828 }, + { 0x0000a084 , 0x28282828 }, + { 0x0000a088 , 0x28282828 }, + { 0x0000a08c , 0x28282828 }, + { 0x0000a090 , 0x28282828 }, + { 0x0000a094 , 0x24242428 }, + { 0x0000a098 , 0x171e1e1e }, + { 0x0000a09c , 0x02020b0b }, + { 0x0000a0a0 , 0x02020202 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x22072208 }, + { 0x0000a0c4 , 0x22052206 }, + { 0x0000a0c8 , 0x22032204 }, + { 0x0000a0cc , 0x22012202 }, + { 0x0000a0d0 , 0x221f2200 }, + { 0x0000a0d4 , 0x221d221e }, + { 0x0000a0d8 , 0x33023303 }, + { 0x0000a0dc , 0x33003301 }, + { 0x0000a0e0 , 0x331e331f }, + { 0x0000a0e4 , 0x4402331d }, + { 0x0000a0e8 , 0x44004401 }, + { 0x0000a0ec , 0x441e441f }, + { 0x0000a0f0 , 0x55025503 }, + { 0x0000a0f4 , 0x55005501 }, + { 0x0000a0f8 , 0x551e551f }, + { 0x0000a0fc , 0x6602551d }, + { 0x0000a100 , 0x66006601 }, + { 0x0000a104 , 0x661e661f }, + { 0x0000a108 , 0x7703661d }, + { 0x0000a10c , 0x77017702 }, + { 0x0000a110 , 0x00007700 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x111f1100 }, + { 0x0000a148 , 0x111d111e }, + { 0x0000a14c , 0x111b111c }, + { 0x0000a150 , 0x22032204 }, + { 0x0000a154 , 0x22012202 }, + { 0x0000a158 , 0x221f2200 }, + { 0x0000a15c , 0x221d221e }, + { 0x0000a160 , 0x33013302 }, + { 0x0000a164 , 0x331f3300 }, + { 0x0000a168 , 0x4402331e }, + { 0x0000a16c , 0x44004401 }, + { 0x0000a170 , 0x441e441f }, + { 0x0000a174 , 0x55015502 }, + { 0x0000a178 , 0x551f5500 }, + { 0x0000a17c , 0x6602551e }, + { 0x0000a180 , 0x66006601 }, + { 0x0000a184 , 0x661e661f }, + { 0x0000a188 , 0x7703661d }, + { 0x0000a18c , 0x77017702 }, + { 0x0000a190 , 0x00007700 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000296 }, +}; + +static const u_int32_t ar9331_common_rx_gain_hornet1_1_emulation[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x02000101 }, + { 0x0000a004 , 0x02000102 }, + { 0x0000a008 , 0x02000103 }, + { 0x0000a00c , 0x02000104 }, + { 0x0000a010 , 0x02000200 }, + { 0x0000a014 , 0x02000201 }, + { 0x0000a018 , 0x02000202 }, + { 0x0000a01c , 0x02000203 }, + { 0x0000a020 , 0x02000204 }, + { 0x0000a024 , 0x02000205 }, + { 0x0000a028 , 0x02000208 }, + { 0x0000a02c , 0x02000302 }, + { 0x0000a030 , 0x02000303 }, + { 0x0000a034 , 0x02000304 }, + { 0x0000a038 , 0x02000400 }, + { 0x0000a03c , 0x02010300 }, + { 0x0000a040 , 0x02010301 }, + { 0x0000a044 , 0x02010302 }, + { 0x0000a048 , 0x02000500 }, + { 0x0000a04c , 0x02010400 }, + { 0x0000a050 , 0x02020300 }, + { 0x0000a054 , 0x02020301 }, + { 0x0000a058 , 0x02020302 }, + { 0x0000a05c , 0x02020303 }, + { 0x0000a060 , 0x02020400 }, + { 0x0000a064 , 0x02030300 }, + { 0x0000a068 , 0x02030301 }, + { 0x0000a06c , 0x02030302 }, + { 0x0000a070 , 0x02030303 }, + { 0x0000a074 , 0x02030400 }, + { 0x0000a078 , 0x02040300 }, + { 0x0000a07c , 0x02040301 }, + { 0x0000a080 , 0x02040302 }, + { 0x0000a084 , 0x02040303 }, + { 0x0000a088 , 0x02030500 }, + { 0x0000a08c , 0x02040400 }, + { 0x0000a090 , 0x02050203 }, + { 0x0000a094 , 0x02050204 }, + { 0x0000a098 , 0x02050205 }, + { 0x0000a09c , 0x02040500 }, + { 0x0000a0a0 , 0x02050301 }, + { 0x0000a0a4 , 0x02050302 }, + { 0x0000a0a8 , 0x02050303 }, + { 0x0000a0ac , 0x02050400 }, + { 0x0000a0b0 , 0x02050401 }, + { 0x0000a0b4 , 0x02050402 }, + { 0x0000a0b8 , 0x02050403 }, + { 0x0000a0bc , 0x02050500 }, + { 0x0000a0c0 , 0x02050501 }, + { 0x0000a0c4 , 0x02050502 }, + { 0x0000a0c8 , 0x02050503 }, + { 0x0000a0cc , 0x02050504 }, + { 0x0000a0d0 , 0x02050600 }, + { 0x0000a0d4 , 0x02050601 }, + { 0x0000a0d8 , 0x02050602 }, + { 0x0000a0dc , 0x02050603 }, + { 0x0000a0e0 , 0x02050604 }, + { 0x0000a0e4 , 0x02050700 }, + { 0x0000a0e8 , 0x02050701 }, + { 0x0000a0ec , 0x02050702 }, + { 0x0000a0f0 , 0x02050703 }, + { 0x0000a0f4 , 0x02050704 }, + { 0x0000a0f8 , 0x02050705 }, + { 0x0000a0fc , 0x02050708 }, + { 0x0000a100 , 0x02050709 }, + { 0x0000a104 , 0x0205070a }, + { 0x0000a108 , 0x0205070b }, + { 0x0000a10c , 0x0205070c }, + { 0x0000a110 , 0x0205070d }, + { 0x0000a114 , 0x02050710 }, + { 0x0000a118 , 0x02050711 }, + { 0x0000a11c , 0x02050712 }, + { 0x0000a120 , 0x02050713 }, + { 0x0000a124 , 0x02050714 }, + { 0x0000a128 , 0x02050715 }, + { 0x0000a12c , 0x02050730 }, + { 0x0000a130 , 0x02050731 }, + { 0x0000a134 , 0x02050732 }, + { 0x0000a138 , 0x02050733 }, + { 0x0000a13c , 0x02050734 }, + { 0x0000a140 , 0x02050735 }, + { 0x0000a144 , 0x02050750 }, + { 0x0000a148 , 0x02050751 }, + { 0x0000a14c , 0x02050752 }, + { 0x0000a150 , 0x02050753 }, + { 0x0000a154 , 0x02050754 }, + { 0x0000a158 , 0x02050755 }, + { 0x0000a15c , 0x02050770 }, + { 0x0000a160 , 0x02050771 }, + { 0x0000a164 , 0x02050772 }, + { 0x0000a168 , 0x02050773 }, + { 0x0000a16c , 0x02050774 }, + { 0x0000a170 , 0x02050775 }, + { 0x0000a174 , 0x00000776 }, + { 0x0000a178 , 0x00000776 }, + { 0x0000a17c , 0x00000776 }, + { 0x0000a180 , 0x00000776 }, + { 0x0000a184 , 0x00000776 }, + { 0x0000a188 , 0x00000776 }, + { 0x0000a18c , 0x00000776 }, + { 0x0000a190 , 0x00000776 }, + { 0x0000a194 , 0x00000776 }, + { 0x0000a198 , 0x00000776 }, + { 0x0000a19c , 0x00000776 }, + { 0x0000a1a0 , 0x00000776 }, + { 0x0000a1a4 , 0x00000776 }, + { 0x0000a1a8 , 0x00000776 }, + { 0x0000a1ac , 0x00000776 }, + { 0x0000a1b0 , 0x00000776 }, + { 0x0000a1b4 , 0x00000776 }, + { 0x0000a1b8 , 0x00000776 }, + { 0x0000a1bc , 0x00000776 }, + { 0x0000a1c0 , 0x00000776 }, + { 0x0000a1c4 , 0x00000776 }, + { 0x0000a1c8 , 0x00000776 }, + { 0x0000a1cc , 0x00000776 }, + { 0x0000a1d0 , 0x00000776 }, + { 0x0000a1d4 , 0x00000776 }, + { 0x0000a1d8 , 0x00000776 }, + { 0x0000a1dc , 0x00000776 }, + { 0x0000a1e0 , 0x00000776 }, + { 0x0000a1e4 , 0x00000776 }, + { 0x0000a1e8 , 0x00000776 }, + { 0x0000a1ec , 0x00000776 }, + { 0x0000a1f0 , 0x00000776 }, + { 0x0000a1f4 , 0x00000776 }, + { 0x0000a1f8 , 0x00000776 }, + { 0x0000a1fc , 0x00000776 }, +}; + +static const u_int32_t ar9331_hornet1_1_baseband_core[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009804 , 0xfd14e000 }, + { 0x00009808 , 0x9c0a8f6b }, + { 0x0000980c , 0x04800000 }, + { 0x00009814 , 0x9280c00a }, + { 0x00009818 , 0x00000000 }, + { 0x0000981c , 0x00020028 }, + { 0x00009834 , 0x5f3ca3de }, + { 0x00009838 , 0x0108ecff }, + { 0x0000983c , 0x14750600 }, + { 0x00009880 , 0x201fff00 }, + { 0x00009884 , 0x00001042 }, + { 0x000098a4 , 0x00200400 }, + { 0x000098b0 , 0x32840bbe }, + { 0x000098d0 , 0x004b6a8e }, + { 0x000098d4 , 0x00000820 }, + { 0x000098dc , 0x00000000 }, + { 0x000098f0 , 0x00000000 }, + { 0x000098f4 , 0x00000000 }, + { 0x00009c04 , 0x00000000 }, + { 0x00009c08 , 0x03200000 }, + { 0x00009c0c , 0x00000000 }, + { 0x00009c10 , 0x00000000 }, + { 0x00009c14 , 0x00046384 }, + { 0x00009c18 , 0x05b6b440 }, + { 0x00009c1c , 0x00b6b440 }, + { 0x00009d00 , 0xc080a333 }, + { 0x00009d04 , 0x40206c10 }, + { 0x00009d08 , 0x009c4060 }, + { 0x00009d0c , 0x1883800a }, + { 0x00009d10 , 0x01834061 }, + { 0x00009d14 , 0x00c00400 }, + { 0x00009d18 , 0x00000000 }, + { 0x00009e08 , 0x0038233c }, + { 0x00009e24 , 0x9927b515 }, + { 0x00009e28 , 0x12ef0200 }, + { 0x00009e30 , 0x06336f77 }, + { 0x00009e34 , 0x6af6532f }, + { 0x00009e38 , 0x0cc80c00 }, + { 0x00009e40 , 0x0d261820 }, + { 0x00009e4c , 0x00001004 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009fc0 , 0x803e4788 }, + { 0x00009fc4 , 0x0001efb5 }, + { 0x00009fcc , 0x40000014 }, + { 0x0000a20c , 0x00000000 }, + { 0x0000a220 , 0x00000000 }, + { 0x0000a224 , 0x00000000 }, + { 0x0000a228 , 0x10002310 }, + { 0x0000a23c , 0x00000000 }, + { 0x0000a244 , 0x0c000000 }, + { 0x0000a2a0 , 0x00000001 }, + { 0x0000a2c0 , 0x00000001 }, + { 0x0000a2c8 , 0x00000000 }, + { 0x0000a2cc , 0x18c43433 }, + { 0x0000a2d4 , 0x00000000 }, + { 0x0000a2dc , 0x00000000 }, + { 0x0000a2e0 , 0x00000000 }, + { 0x0000a2e4 , 0x00000000 }, + { 0x0000a2e8 , 0x00000000 }, + { 0x0000a2ec , 0x00000000 }, + { 0x0000a2f0 , 0x00000000 }, + { 0x0000a2f4 , 0x00000000 }, + { 0x0000a2f8 , 0x00000000 }, + { 0x0000a344 , 0x00000000 }, + { 0x0000a34c , 0x00000000 }, + { 0x0000a350 , 0x0000a000 }, + { 0x0000a364 , 0x00000000 }, + { 0x0000a370 , 0x00000000 }, + { 0x0000a390 , 0x00000001 }, + { 0x0000a394 , 0x00000444 }, + { 0x0000a398 , 0x001f0e0f }, + { 0x0000a39c , 0x0075393f }, + { 0x0000a3a0 , 0xb79f6427 }, + { 0x0000a3a4 , 0x00000000 }, + { 0x0000a3a8 , 0xaaaaaaaa }, + { 0x0000a3ac , 0x3c466478 }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a3c8 , 0x20200020 }, + { 0x0000a3cc , 0x20202020 }, + { 0x0000a3d0 , 0x20202020 }, + { 0x0000a3d4 , 0x20202020 }, + { 0x0000a3d8 , 0x20202020 }, + { 0x0000a3dc , 0x20202020 }, + { 0x0000a3e0 , 0x20202020 }, + { 0x0000a3e4 , 0x20202020 }, + { 0x0000a3e8 , 0x20202020 }, + { 0x0000a3ec , 0x20202020 }, + { 0x0000a3f0 , 0x00000000 }, + { 0x0000a3f4 , 0x00000006 }, + { 0x0000a3f8 , 0x0cdbd380 }, + { 0x0000a3fc , 0x000f0f01 }, + { 0x0000a400 , 0x8fa91f01 }, + { 0x0000a404 , 0x00000000 }, + { 0x0000a408 , 0x0e79e5c6 }, + { 0x0000a40c , 0x00820820 }, + { 0x0000a414 , 0x1ce739ce }, + { 0x0000a418 , 0x2d001dce }, + { 0x0000a41c , 0x1ce739ce }, + { 0x0000a420 , 0x000001ce }, + { 0x0000a424 , 0x1ce739ce }, + { 0x0000a428 , 0x000001ce }, + { 0x0000a42c , 0x1ce739ce }, + { 0x0000a430 , 0x1ce739ce }, + { 0x0000a434 , 0x00000000 }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a43c , 0x00000000 }, + { 0x0000a440 , 0x00000000 }, + { 0x0000a444 , 0x00000000 }, + { 0x0000a448 , 0x04000000 }, + { 0x0000a44c , 0x00000001 }, + { 0x0000a450 , 0x00010000 }, + { 0x0000a458 , 0x00000000 }, + { 0x0000a640 , 0x00000000 }, + { 0x0000a644 , 0x3fad9d74 }, + { 0x0000a648 , 0x0048060a }, + { 0x0000a64c , 0x00003c37 }, + { 0x0000a670 , 0x03020100 }, + { 0x0000a674 , 0x09080504 }, + { 0x0000a678 , 0x0d0c0b0a }, + { 0x0000a67c , 0x13121110 }, + { 0x0000a680 , 0x31301514 }, + { 0x0000a684 , 0x35343332 }, + { 0x0000a688 , 0x00000036 }, + { 0x0000a690 , 0x00000838 }, + { 0x0000a7c0 , 0x00000000 }, + { 0x0000a7c4 , 0xfffffffc }, + { 0x0000a7c8 , 0x00000000 }, + { 0x0000a7cc , 0x00000000 }, + { 0x0000a7d0 , 0x00000000 }, + { 0x0000a7d4 , 0x00000004 }, + { 0x0000a7dc , 0x00000001 }, +}; + +static const u_int32_t ar9331_modes_high_power_tx_gain_hornet1_1[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2d8 , 0x7999a83a , 0x7999a83a , 0x7999a83a , 0x7999a83a }, + { 0x0000a2dc , 0xffff2a52 , 0xffff2a52 , 0xffff2a52 , 0xffff2a52 }, + { 0x0000a2e0 , 0xffffcc84 , 0xffffcc84 , 0xffffcc84 , 0xffffcc84 }, + { 0x0000a2e4 , 0xfffff000 , 0xfffff000 , 0xfffff000 , 0xfffff000 }, + { 0x0000a2e8 , 0xfffe0000 , 0xfffe0000 , 0xfffe0000 , 0xfffe0000 }, + { 0x0000a410 , 0x000050d7 , 0x000050d7 , 0x000050d0 , 0x000050d0 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x23000a00 , 0x23000a00 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x27000a02 , 0x27000a02 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2b000a04 , 0x2b000a04 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2d000a20 , 0x2d000a20 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x31000a22 , 0x31000a22 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x35000a24 , 0x35000a24 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x38000a43 , 0x38000a43 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x3b000e42 , 0x3b000e42 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x3f000e44 , 0x3f000e44 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x42000e64 , 0x42000e64 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x46000e66 , 0x46000e66 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x4a000ea6 , 0x4a000ea6 }, + { 0x0000a580 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a584 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a588 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a58c , 0x11062202 , 0x11062202 , 0x0b000200 , 0x0b000200 }, + { 0x0000a590 , 0x17022e00 , 0x17022e00 , 0x0f000202 , 0x0f000202 }, + { 0x0000a594 , 0x1d000ec2 , 0x1d000ec2 , 0x11000400 , 0x11000400 }, + { 0x0000a598 , 0x25020ec0 , 0x25020ec0 , 0x15000402 , 0x15000402 }, + { 0x0000a59c , 0x2b020ec3 , 0x2b020ec3 , 0x19000404 , 0x19000404 }, + { 0x0000a5a0 , 0x2f001f04 , 0x2f001f04 , 0x1b000603 , 0x1b000603 }, + { 0x0000a5a4 , 0x35001fc4 , 0x35001fc4 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a5a8 , 0x3c022f04 , 0x3c022f04 , 0x23000a04 , 0x23000a04 }, + { 0x0000a5ac , 0x41023e85 , 0x41023e85 , 0x26000a20 , 0x26000a20 }, + { 0x0000a5b0 , 0x48023ec6 , 0x48023ec6 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a5b4 , 0x4d023f01 , 0x4d023f01 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a5b8 , 0x53023f4b , 0x53023f4b , 0x31000e24 , 0x31000e24 }, + { 0x0000a5bc , 0x5a027f09 , 0x5a027f09 , 0x34001640 , 0x34001640 }, + { 0x0000a5c0 , 0x5f027fc9 , 0x5f027fc9 , 0x38001660 , 0x38001660 }, + { 0x0000a5c4 , 0x6502feca , 0x6502feca , 0x3b001861 , 0x3b001861 }, + { 0x0000a5c8 , 0x6b02ff4a , 0x6b02ff4a , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a5cc , 0x7203feca , 0x7203feca , 0x42001a83 , 0x42001a83 }, + { 0x0000a5d0 , 0x7703ff0b , 0x7703ff0b , 0x44001c84 , 0x44001c84 }, + { 0x0000a5d4 , 0x7d06ffcb , 0x7d06ffcb , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a5d8 , 0x8407ff0b , 0x8407ff0b , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a5dc , 0x8907ffcb , 0x8907ffcb , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a5e0 , 0x900fff0b , 0x900fff0b , 0x54001ceb , 0x54001ceb }, + { 0x0000a5e4 , 0x960fffcb , 0x960fffcb , 0x56001eec , 0x56001eec }, + { 0x0000a5e8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5ec , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f0 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f4 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5fc , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008802 , 0x02008802 }, + { 0x0000a620 , 0x0280c802 , 0x0280c802 , 0x0280c802 , 0x0280c802 }, + { 0x0000a624 , 0x03010a03 , 0x03010a03 , 0x03010a03 , 0x03010a03 }, + { 0x0000a628 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a62c , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a630 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a634 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a638 , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x0000a63c , 0x03010c04 , 0x03010c04 , 0x03010c04 , 0x03010c04 }, + { 0x00016044 , 0x034922db , 0x034922db , 0x034922db , 0x034922db }, + { 0x00016284 , 0x14d3f000 , 0x14d3f000 , 0x14d3f000 , 0x14d3f000 }, +}; + +static const u_int32_t ar9331_hornet1_1_mac_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 }, + { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 }, +}; + +static const u_int32_t ar9331_hornet1_1_mac_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, +}; + +static const u_int32_t ar9331_hornet1_1_soc_preamble[][2] = { +/* Addr allmodes */ + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000002f8 }, +}; + +static const u_int32_t ar9331_hornet1_1_xtal_40M[][2] = { +/* Addr allmodes */ + { 0x00007038 , 0x000004c2 }, + { 0x00008244 , 0x0010f400 }, + { 0x0000824c , 0x0001e800 }, + { 0x0001609c , 0x0b283f31 }, +}; + +static const u_int32_t ar9331_hornet1_1_mac_core[][2] = { +/* Addr allmodes */ + { 0x00000008 , 0x00000000 }, + { 0x00000030 , 0x00020085 }, + { 0x00000034 , 0x00000005 }, + { 0x00000040 , 0x00000000 }, + { 0x00000044 , 0x00000000 }, + { 0x00000048 , 0x00000008 }, + { 0x0000004c , 0x00000010 }, + { 0x00000050 , 0x00000000 }, + { 0x00001040 , 0x002ffc0f }, + { 0x00001044 , 0x002ffc0f }, + { 0x00001048 , 0x002ffc0f }, + { 0x0000104c , 0x002ffc0f }, + { 0x00001050 , 0x002ffc0f }, + { 0x00001054 , 0x002ffc0f }, + { 0x00001058 , 0x002ffc0f }, + { 0x0000105c , 0x002ffc0f }, + { 0x00001060 , 0x002ffc0f }, + { 0x00001064 , 0x002ffc0f }, + { 0x000010f0 , 0x00000100 }, + { 0x00001270 , 0x00000000 }, + { 0x000012b0 , 0x00000000 }, + { 0x000012f0 , 0x00000000 }, + { 0x0000143c , 0x00000000 }, + { 0x0000147c , 0x00000000 }, + { 0x00008000 , 0x00000000 }, + { 0x00008004 , 0x00000000 }, + { 0x00008008 , 0x00000000 }, + { 0x0000800c , 0x00000000 }, + { 0x00008018 , 0x00000000 }, + { 0x00008020 , 0x00000000 }, + { 0x00008038 , 0x00000000 }, + { 0x0000803c , 0x00000000 }, + { 0x00008040 , 0x00000000 }, + { 0x00008044 , 0x00000000 }, + { 0x00008048 , 0x00000000 }, + { 0x0000804c , 0xffffffff }, + { 0x00008054 , 0x00000000 }, + { 0x00008058 , 0x00000000 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008060 , 0x0000000f }, + { 0x00008064 , 0x00000000 }, + { 0x00008070 , 0x00000310 }, + { 0x00008074 , 0x00000020 }, + { 0x00008078 , 0x00000000 }, + { 0x0000809c , 0x0000000f }, + { 0x000080a0 , 0x00000000 }, + { 0x000080a4 , 0x02ff0000 }, + { 0x000080a8 , 0x0e070605 }, + { 0x000080ac , 0x0000000d }, + { 0x000080b0 , 0x00000000 }, + { 0x000080b4 , 0x00000000 }, + { 0x000080b8 , 0x00000000 }, + { 0x000080bc , 0x00000000 }, + { 0x000080c0 , 0x2a800000 }, + { 0x000080c4 , 0x06900168 }, + { 0x000080c8 , 0x13881c20 }, + { 0x000080cc , 0x01f40000 }, + { 0x000080d0 , 0x00252500 }, + { 0x000080d4 , 0x00a00000 }, + { 0x000080d8 , 0x00400000 }, + { 0x000080dc , 0x00000000 }, + { 0x000080e0 , 0xffffffff }, + { 0x000080e4 , 0x0000ffff }, + { 0x000080e8 , 0x3f3f3f3f }, + { 0x000080ec , 0x00000000 }, + { 0x000080f0 , 0x00000000 }, + { 0x000080f4 , 0x00000000 }, + { 0x000080fc , 0x00020000 }, + { 0x00008100 , 0x00000000 }, + { 0x00008108 , 0x00000052 }, + { 0x0000810c , 0x00000000 }, + { 0x00008110 , 0x00000000 }, + { 0x00008114 , 0x000007ff }, + { 0x00008118 , 0x000000aa }, + { 0x0000811c , 0x00003210 }, + { 0x00008124 , 0x00000000 }, + { 0x00008128 , 0x00000000 }, + { 0x0000812c , 0x00000000 }, + { 0x00008130 , 0x00000000 }, + { 0x00008134 , 0x00000000 }, + { 0x00008138 , 0x00000000 }, + { 0x0000813c , 0x0000ffff }, + { 0x00008144 , 0xffffffff }, + { 0x00008168 , 0x00000000 }, + { 0x0000816c , 0x00000000 }, + { 0x00008170 , 0x18486200 }, + { 0x00008174 , 0x33332210 }, + { 0x00008178 , 0x00000000 }, + { 0x0000817c , 0x00020000 }, + { 0x000081c0 , 0x00000000 }, + { 0x000081c4 , 0x33332210 }, + { 0x000081c8 , 0x00000000 }, + { 0x000081cc , 0x00000000 }, + { 0x000081d4 , 0x00000000 }, + { 0x000081ec , 0x00000000 }, + { 0x000081f0 , 0x00000000 }, + { 0x000081f4 , 0x00000000 }, + { 0x000081f8 , 0x00000000 }, + { 0x000081fc , 0x00000000 }, + { 0x00008240 , 0x00100000 }, + { 0x00008248 , 0x00000800 }, + { 0x00008250 , 0x00000000 }, + { 0x00008254 , 0x00000000 }, + { 0x00008258 , 0x00000000 }, + { 0x0000825c , 0x40000000 }, + { 0x00008260 , 0x00080922 }, + { 0x00008264 , 0x9d400010 }, + { 0x00008268 , 0xffffffff }, + { 0x0000826c , 0x0000ffff }, + { 0x00008270 , 0x00000000 }, + { 0x00008274 , 0x40000000 }, + { 0x00008278 , 0x003e4180 }, + { 0x0000827c , 0x00000004 }, + { 0x00008284 , 0x0000002c }, + { 0x00008288 , 0x0000002c }, + { 0x0000828c , 0x000000ff }, + { 0x00008294 , 0x00000000 }, + { 0x00008298 , 0x00000000 }, + { 0x0000829c , 0x00000000 }, + { 0x00008300 , 0x00000140 }, + { 0x00008314 , 0x00000000 }, + { 0x0000831c , 0x0000010d }, + { 0x00008328 , 0x00000000 }, + { 0x0000832c , 0x00000007 }, + { 0x00008330 , 0x00000302 }, + { 0x00008334 , 0x00000700 }, + { 0x00008338 , 0x00ff0000 }, + { 0x0000833c , 0x02400000 }, + { 0x00008340 , 0x000107ff }, + { 0x00008344 , 0xaa48105b }, + { 0x00008348 , 0x008f0000 }, + { 0x0000835c , 0x00000000 }, + { 0x00008360 , 0xffffffff }, + { 0x00008364 , 0xffffffff }, + { 0x00008368 , 0x00000000 }, + { 0x00008370 , 0x00000000 }, + { 0x00008374 , 0x000000ff }, + { 0x00008378 , 0x00000000 }, + { 0x0000837c , 0x00000000 }, + { 0x00008380 , 0xffffffff }, + { 0x00008384 , 0xffffffff }, + { 0x00008390 , 0xffffffff }, + { 0x00008394 , 0xffffffff }, + { 0x00008398 , 0x00000000 }, + { 0x0000839c , 0x00000000 }, + { 0x000083a0 , 0x00000000 }, + { 0x000083a4 , 0x0000fa14 }, + { 0x000083a8 , 0x000f0c00 }, + { 0x000083ac , 0x33332210 }, + { 0x000083b0 , 0x33332210 }, + { 0x000083b4 , 0x33332210 }, + { 0x000083b8 , 0x33332210 }, + { 0x000083bc , 0x00000000 }, + { 0x000083c0 , 0x00000000 }, + { 0x000083c4 , 0x00000000 }, + { 0x000083c8 , 0x00000000 }, + { 0x000083cc , 0x00000200 }, + { 0x000083d0 , 0x000301ff }, +}; + +static const u_int32_t ar9331_common_rx_gain_hornet1_1[][2] = { +/* Addr allmodes */ + { 0x00009e18 , 0x05000000 }, + { 0x0000a000 , 0x00060005 }, + { 0x0000a004 , 0x00810080 }, + { 0x0000a008 , 0x00830082 }, + { 0x0000a00c , 0x00850084 }, + { 0x0000a010 , 0x01820181 }, + { 0x0000a014 , 0x01840183 }, + { 0x0000a018 , 0x01880185 }, + { 0x0000a01c , 0x018a0189 }, + { 0x0000a020 , 0x02850284 }, + { 0x0000a024 , 0x02890288 }, + { 0x0000a028 , 0x028b028a }, + { 0x0000a02c , 0x03850384 }, + { 0x0000a030 , 0x03890388 }, + { 0x0000a034 , 0x038b038a }, + { 0x0000a038 , 0x038d038c }, + { 0x0000a03c , 0x03910390 }, + { 0x0000a040 , 0x03930392 }, + { 0x0000a044 , 0x03950394 }, + { 0x0000a048 , 0x00000396 }, + { 0x0000a04c , 0x00000000 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x28282828 }, + { 0x0000a084 , 0x28282828 }, + { 0x0000a088 , 0x28282828 }, + { 0x0000a08c , 0x28282828 }, + { 0x0000a090 , 0x28282828 }, + { 0x0000a094 , 0x24242428 }, + { 0x0000a098 , 0x171e1e1e }, + { 0x0000a09c , 0x02020b0b }, + { 0x0000a0a0 , 0x02020202 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x22072208 }, + { 0x0000a0c4 , 0x22052206 }, + { 0x0000a0c8 , 0x22032204 }, + { 0x0000a0cc , 0x22012202 }, + { 0x0000a0d0 , 0x221f2200 }, + { 0x0000a0d4 , 0x221d221e }, + { 0x0000a0d8 , 0x33023303 }, + { 0x0000a0dc , 0x33003301 }, + { 0x0000a0e0 , 0x331e331f }, + { 0x0000a0e4 , 0x4402331d }, + { 0x0000a0e8 , 0x44004401 }, + { 0x0000a0ec , 0x441e441f }, + { 0x0000a0f0 , 0x55025503 }, + { 0x0000a0f4 , 0x55005501 }, + { 0x0000a0f8 , 0x551e551f }, + { 0x0000a0fc , 0x6602551d }, + { 0x0000a100 , 0x66006601 }, + { 0x0000a104 , 0x661e661f }, + { 0x0000a108 , 0x7703661d }, + { 0x0000a10c , 0x77017702 }, + { 0x0000a110 , 0x00007700 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x111f1100 }, + { 0x0000a148 , 0x111d111e }, + { 0x0000a14c , 0x111b111c }, + { 0x0000a150 , 0x22032204 }, + { 0x0000a154 , 0x22012202 }, + { 0x0000a158 , 0x221f2200 }, + { 0x0000a15c , 0x221d221e }, + { 0x0000a160 , 0x33013302 }, + { 0x0000a164 , 0x331f3300 }, + { 0x0000a168 , 0x4402331e }, + { 0x0000a16c , 0x44004401 }, + { 0x0000a170 , 0x441e441f }, + { 0x0000a174 , 0x55015502 }, + { 0x0000a178 , 0x551f5500 }, + { 0x0000a17c , 0x6602551e }, + { 0x0000a180 , 0x66006601 }, + { 0x0000a184 , 0x661e661f }, + { 0x0000a188 , 0x7703661d }, + { 0x0000a18c , 0x77017702 }, + { 0x0000a190 , 0x00007700 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000296 }, +}; +static const u_int32_t ar9331_common_tx_gain_offset1_1[][1] = { + {0}, + {3}, + {0}, + {0}, +}; + +static const u_int32_t ar9331_hornet1_1_chansel_xtal_25M[] = { + 0x101479e, //Freq 2412 - (128 << 17) + 83870 + 0x101d027, //Freq 2417 - (128 << 17) + 118823 + 0x10258af, //Freq 2422 - (129 << 17) + 22703 + 0x102e138, //Freq 2427 - (129 << 17) + 57656 + 0x10369c0, //Freq 2432 - (129 << 17) + 92608 + 0x103f249, //Freq 2437 - (129 << 17) + 127561 + 0x1047ad1, //Freq 2442 - (130 << 17) + 31441 + 0x105035a, //Freq 2447 - (130 << 17) + 66394 + 0x1058be2, //Freq 2452 - (130 << 17) + 101346 + 0x106146b, //Freq 2457 - (131 << 17) + 5227 + 0x1069cf3, //Freq 2462 - (131 << 17) + 40179 + 0x107257c, //Freq 2467 - (131 << 17) + 75132 + 0x107ae04, //Freq 2472 - (131 << 17) + 110084 + 0x108f5b2, //Freq 2484 - (132 << 17) + 62898 +}; + +static const u_int32_t ar9331_hornet1_1_chansel_xtal_40M[] = { + 0xa0ccbe, // Freq 2412 - (80 << 17) + 52414 + 0xa12213, // Freq 2417 - (80 << 17) + 74259 + 0xa17769, // Freq 2422 - (80 << 17) + 96105 + 0xa1ccbe, // Freq 2427 - (80 << 17) + 117950 + 0xa22213, // Freq 2432 - (81 << 17) + 8723 + 0xa27769, // Freq 2437 - (81 << 17) + 30569 + 0xa2ccbe, // Freq 2442 - (81 << 17) + 52414 + 0xa32213, // Freq 2447 - (81 << 17) + 74259 + 0xa37769, // Freq 2452 - (81 << 17) + 96105 + 0xa3ccbe, // Freq 2457 - (81 << 17) + 117950 + 0xa42213, // Freq 2462 - (82 << 17) + 8723 + 0xa47769, // Freq 2467 - (82 << 17) + 30569 + 0xa4ccbe, // Freq 2472 - (82 << 17) + 52414 + 0xa5998b, // Freq 2484 - (82 << 17) + 104843 + +}; diff --git a/hal/ar9300/ar9330_12.ini b/hal/ar9300/ar9330_12.ini new file mode 100755 index 000000000000..6b8f1ae2ab8a --- /dev/null +++ b/hal/ar9300/ar9330_12.ini @@ -0,0 +1,1289 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +static const u_int32_t ar9331_modes_lowest_ob_db_tx_gain_hornet1_2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000050d7 , 0x000050d7 , 0x000050d7 , 0x000050d7 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x23000a00 , 0x23000a00 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x27000a02 , 0x27000a02 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2b000a04 , 0x2b000a04 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x3f001620 , 0x3f001620 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x41001621 , 0x41001621 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x44001640 , 0x44001640 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x46001641 , 0x46001641 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x48001642 , 0x48001642 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x4b001644 , 0x4b001644 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4e001a81 , 0x4e001a81 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x51001a83 , 0x51001a83 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x54001c84 , 0x54001c84 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x57001ce3 , 0x57001ce3 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x5b001ce5 , 0x5b001ce5 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5f001ce9 , 0x5f001ce9 }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x66001eec , 0x66001eec }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x66001eec , 0x66001eec }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a580 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a584 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a588 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a58c , 0x11062202 , 0x11062202 , 0x0b000200 , 0x0b000200 }, + { 0x0000a590 , 0x17022e00 , 0x17022e00 , 0x0f000202 , 0x0f000202 }, + { 0x0000a594 , 0x1d000ec2 , 0x1d000ec2 , 0x11000400 , 0x11000400 }, + { 0x0000a598 , 0x25020ec0 , 0x25020ec0 , 0x15000402 , 0x15000402 }, + { 0x0000a59c , 0x2b020ec3 , 0x2b020ec3 , 0x19000404 , 0x19000404 }, + { 0x0000a5a0 , 0x2f001f04 , 0x2f001f04 , 0x1b000603 , 0x1b000603 }, + { 0x0000a5a4 , 0x35001fc4 , 0x35001fc4 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a5a8 , 0x3c022f04 , 0x3c022f04 , 0x23000a04 , 0x23000a04 }, + { 0x0000a5ac , 0x41023e85 , 0x41023e85 , 0x26000a20 , 0x26000a20 }, + { 0x0000a5b0 , 0x48023ec6 , 0x48023ec6 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a5b4 , 0x4d023f01 , 0x4d023f01 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a5b8 , 0x53023f4b , 0x53023f4b , 0x31000e24 , 0x31000e24 }, + { 0x0000a5bc , 0x5a027f09 , 0x5a027f09 , 0x34001640 , 0x34001640 }, + { 0x0000a5c0 , 0x5f027fc9 , 0x5f027fc9 , 0x38001660 , 0x38001660 }, + { 0x0000a5c4 , 0x6502feca , 0x6502feca , 0x3b001861 , 0x3b001861 }, + { 0x0000a5c8 , 0x6b02ff4a , 0x6b02ff4a , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a5cc , 0x7203feca , 0x7203feca , 0x42001a83 , 0x42001a83 }, + { 0x0000a5d0 , 0x7703ff0b , 0x7703ff0b , 0x44001c84 , 0x44001c84 }, + { 0x0000a5d4 , 0x7d06ffcb , 0x7d06ffcb , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a5d8 , 0x8407ff0b , 0x8407ff0b , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a5dc , 0x8907ffcb , 0x8907ffcb , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a5e0 , 0x900fff0b , 0x900fff0b , 0x54001ceb , 0x54001ceb }, + { 0x0000a5e4 , 0x960fffcb , 0x960fffcb , 0x56001eec , 0x56001eec }, + { 0x0000a5e8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5ec , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f0 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f4 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5fc , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x02008501 , 0x02008501 , 0x02008501 , 0x02008501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008802 , 0x02008802 }, + { 0x0000a620 , 0x0300c802 , 0x0300c802 , 0x0300c802 , 0x0300c802 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x0300cc03 , 0x0300cc03 }, + { 0x0000a628 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a62c , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a630 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a634 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a638 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a63c , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, +}; + +static const u_int32_t ar9331_hornet1_2_baseband_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 }, + { 0x00009820 , 0x206a002e , 0x206a002e , 0x206a002e , 0x206a002e }, + { 0x00009824 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 }, + { 0x00009828 , 0x06903081 , 0x06903081 , 0x06903881 , 0x06903881 }, + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000059c , 0x0000059c }, + { 0x00009c00 , 0x00000044 , 0x00000044 , 0x00000044 , 0x00000044 }, + { 0x00009e00 , 0x0372161e , 0x0372161e , 0x037216a4 , 0x037216a4 }, + { 0x00009e04 , 0x00182020 , 0x00182020 , 0x00182020 , 0x00182020 }, + { 0x00009e0c , 0x6c4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + { 0x00009e10 , 0x7ec80d2e , 0x7ec80d2e , 0x7ec80d2e , 0x7ec80d2e }, + { 0x00009e14 , 0x31395d5e , 0x3139605e , 0x3139605e , 0x31395d5e }, + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + { 0x00009e2c , 0x0000001c , 0x0000001c , 0x00003221 , 0x00003221 }, + { 0x00009e3c , 0xcf946222 , 0xcf946222 , 0xcf946222 , 0xcf946222 }, + { 0x00009e44 , 0x02321e27 , 0x02321e27 , 0x02282324 , 0x02282324 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302010 , 0x50302010 }, + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, + { 0x0000a204 , 0x00003fc0 , 0x00003fc4 , 0x00003fc4 , 0x00003fc0 }, + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + { 0x0000a230 , 0x0000000a , 0x00000014 , 0x00000016 , 0x0000000b }, + { 0x0000a234 , 0x00000fff , 0x00000fff , 0x10000fff , 0x00000fff }, + { 0x0000a238 , 0xffb81018 , 0xffb81018 , 0xffb81018 , 0xffb81018 }, + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a260 , 0x3a021501 , 0x3a021501 , 0x3a021501 , 0x3a021501 }, + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a288 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a28c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2d0 , 0x00071981 , 0x00071981 , 0x00071981 , 0x00071981 }, + { 0x0000a2d8 , 0xf999a83a , 0xf999a83a , 0xf999a83a , 0xf999a83a }, + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000ae04 , 0x00802020 , 0x00802020 , 0x00802020 , 0x00802020 }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +}; + +static const u_int32_t ar9331_modes_high_ob_db_tx_gain_hornet1_2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000050d7 , 0x000050d7 , 0x000050d7 , 0x000050d7 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x23000a00 , 0x23000a00 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x27000a02 , 0x27000a02 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2b000a04 , 0x2b000a04 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x3f001620 , 0x3f001620 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x41001621 , 0x41001621 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x44001640 , 0x44001640 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x46001641 , 0x46001641 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x48001642 , 0x48001642 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x4b001644 , 0x4b001644 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4e001a81 , 0x4e001a81 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x51001a83 , 0x51001a83 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x54001c84 , 0x54001c84 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x57001ce3 , 0x57001ce3 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x5b001ce5 , 0x5b001ce5 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5f001ce9 , 0x5f001ce9 }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x66001eec , 0x66001eec }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x66001eec , 0x66001eec }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a580 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a584 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a588 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a58c , 0x11062202 , 0x11062202 , 0x0b000200 , 0x0b000200 }, + { 0x0000a590 , 0x17022e00 , 0x17022e00 , 0x0f000202 , 0x0f000202 }, + { 0x0000a594 , 0x1d000ec2 , 0x1d000ec2 , 0x11000400 , 0x11000400 }, + { 0x0000a598 , 0x25020ec0 , 0x25020ec0 , 0x15000402 , 0x15000402 }, + { 0x0000a59c , 0x2b020ec3 , 0x2b020ec3 , 0x19000404 , 0x19000404 }, + { 0x0000a5a0 , 0x2f001f04 , 0x2f001f04 , 0x1b000603 , 0x1b000603 }, + { 0x0000a5a4 , 0x35001fc4 , 0x35001fc4 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a5a8 , 0x3c022f04 , 0x3c022f04 , 0x23000a04 , 0x23000a04 }, + { 0x0000a5ac , 0x41023e85 , 0x41023e85 , 0x26000a20 , 0x26000a20 }, + { 0x0000a5b0 , 0x48023ec6 , 0x48023ec6 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a5b4 , 0x4d023f01 , 0x4d023f01 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a5b8 , 0x53023f4b , 0x53023f4b , 0x31000e24 , 0x31000e24 }, + { 0x0000a5bc , 0x5a027f09 , 0x5a027f09 , 0x34001640 , 0x34001640 }, + { 0x0000a5c0 , 0x5f027fc9 , 0x5f027fc9 , 0x38001660 , 0x38001660 }, + { 0x0000a5c4 , 0x6502feca , 0x6502feca , 0x3b001861 , 0x3b001861 }, + { 0x0000a5c8 , 0x6b02ff4a , 0x6b02ff4a , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a5cc , 0x7203feca , 0x7203feca , 0x42001a83 , 0x42001a83 }, + { 0x0000a5d0 , 0x7703ff0b , 0x7703ff0b , 0x44001c84 , 0x44001c84 }, + { 0x0000a5d4 , 0x7d06ffcb , 0x7d06ffcb , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a5d8 , 0x8407ff0b , 0x8407ff0b , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a5dc , 0x8907ffcb , 0x8907ffcb , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a5e0 , 0x900fff0b , 0x900fff0b , 0x54001ceb , 0x54001ceb }, + { 0x0000a5e4 , 0x960fffcb , 0x960fffcb , 0x56001eec , 0x56001eec }, + { 0x0000a5e8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5ec , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f0 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f4 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5fc , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x02008501 , 0x02008501 , 0x02008501 , 0x02008501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008802 , 0x02008802 }, + { 0x0000a620 , 0x0300c802 , 0x0300c802 , 0x0300c802 , 0x0300c802 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x0300cc03 , 0x0300cc03 }, + { 0x0000a628 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a62c , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a630 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a634 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a638 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a63c , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, +}; + +static const u_int32_t ar9331_modes_low_ob_db_tx_gain_hornet1_2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000050d7 , 0x000050d7 , 0x000050d7 , 0x000050d7 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x23000a00 , 0x23000a00 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x27000a02 , 0x27000a02 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2b000a04 , 0x2b000a04 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x3f001620 , 0x3f001620 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x41001621 , 0x41001621 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x44001640 , 0x44001640 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x46001641 , 0x46001641 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x48001642 , 0x48001642 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x4b001644 , 0x4b001644 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4e001a81 , 0x4e001a81 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x51001a83 , 0x51001a83 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x54001c84 , 0x54001c84 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x57001ce3 , 0x57001ce3 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x5b001ce5 , 0x5b001ce5 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5f001ce9 , 0x5f001ce9 }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x66001eec , 0x66001eec }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x66001eec , 0x66001eec }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a580 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a584 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a588 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a58c , 0x11062202 , 0x11062202 , 0x0b000200 , 0x0b000200 }, + { 0x0000a590 , 0x17022e00 , 0x17022e00 , 0x0f000202 , 0x0f000202 }, + { 0x0000a594 , 0x1d000ec2 , 0x1d000ec2 , 0x11000400 , 0x11000400 }, + { 0x0000a598 , 0x25020ec0 , 0x25020ec0 , 0x15000402 , 0x15000402 }, + { 0x0000a59c , 0x2b020ec3 , 0x2b020ec3 , 0x19000404 , 0x19000404 }, + { 0x0000a5a0 , 0x2f001f04 , 0x2f001f04 , 0x1b000603 , 0x1b000603 }, + { 0x0000a5a4 , 0x35001fc4 , 0x35001fc4 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a5a8 , 0x3c022f04 , 0x3c022f04 , 0x23000a04 , 0x23000a04 }, + { 0x0000a5ac , 0x41023e85 , 0x41023e85 , 0x26000a20 , 0x26000a20 }, + { 0x0000a5b0 , 0x48023ec6 , 0x48023ec6 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a5b4 , 0x4d023f01 , 0x4d023f01 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a5b8 , 0x53023f4b , 0x53023f4b , 0x31000e24 , 0x31000e24 }, + { 0x0000a5bc , 0x5a027f09 , 0x5a027f09 , 0x34001640 , 0x34001640 }, + { 0x0000a5c0 , 0x5f027fc9 , 0x5f027fc9 , 0x38001660 , 0x38001660 }, + { 0x0000a5c4 , 0x6502feca , 0x6502feca , 0x3b001861 , 0x3b001861 }, + { 0x0000a5c8 , 0x6b02ff4a , 0x6b02ff4a , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a5cc , 0x7203feca , 0x7203feca , 0x42001a83 , 0x42001a83 }, + { 0x0000a5d0 , 0x7703ff0b , 0x7703ff0b , 0x44001c84 , 0x44001c84 }, + { 0x0000a5d4 , 0x7d06ffcb , 0x7d06ffcb , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a5d8 , 0x8407ff0b , 0x8407ff0b , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a5dc , 0x8907ffcb , 0x8907ffcb , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a5e0 , 0x900fff0b , 0x900fff0b , 0x54001ceb , 0x54001ceb }, + { 0x0000a5e4 , 0x960fffcb , 0x960fffcb , 0x56001eec , 0x56001eec }, + { 0x0000a5e8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5ec , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f0 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f4 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5fc , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x02008501 , 0x02008501 , 0x02008501 , 0x02008501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008802 , 0x02008802 }, + { 0x0000a620 , 0x0300c802 , 0x0300c802 , 0x0300c802 , 0x0300c802 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x0300cc03 , 0x0300cc03 }, + { 0x0000a628 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a62c , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a630 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a634 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a638 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a63c , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, +}; + +static const u_int32_t ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484[][2] = { +/* Addr allmodes */ + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x6f7f0301 }, + { 0x0000a3a0 , 0xca9228ee }, +}; + +static const u_int32_t ar9331_hornet1_2_xtal_25M[][2] = { +/* Addr allmodes */ + { 0x00007038 , 0x000002f8 }, + { 0x00008244 , 0x0010f3d7 }, + { 0x0000824c , 0x0001e7ae }, + { 0x0001609c , 0x0f508f29 }, +}; + +static const u_int32_t ar9331_hornet1_2_radio_core[][2] = { +/* Addr allmodes */ + { 0x00016000 , 0x36db6db6 }, + { 0x00016004 , 0x6db6db40 }, + { 0x00016008 , 0x73800000 }, + { 0x0001600c , 0x00000000 }, + { 0x00016040 , 0x7f80fff8 }, + { 0x00016044 , 0x03d6d2db }, + { 0x00016048 , 0x6c924268 }, + { 0x0001604c , 0x000f0278 }, + { 0x00016050 , 0x4db6db8c }, + { 0x00016054 , 0x6db60000 }, + { 0x00016080 , 0x00080000 }, + { 0x00016084 , 0x0e48048c }, + { 0x00016088 , 0x14214514 }, + { 0x0001608c , 0x119f081c }, + { 0x00016090 , 0x24926490 }, + { 0x00016098 , 0xd411eb84 }, + { 0x000160a0 , 0xc2108ffe }, + { 0x000160a4 , 0x812fc370 }, + { 0x000160a8 , 0x423c8000 }, + { 0x000160ac , 0x24651800 }, + { 0x000160b0 , 0x03284f3e }, + { 0x000160b4 , 0x92480040 }, + { 0x000160c0 , 0x006db6db }, + { 0x000160c4 , 0x0186db60 }, + { 0x000160c8 , 0x6db6db6c }, + { 0x000160cc , 0x6de6c300 }, + { 0x000160d0 , 0x14500820 }, + { 0x00016100 , 0x04cb0001 }, + { 0x00016104 , 0xfff80015 }, + { 0x00016108 , 0x00080010 }, + { 0x0001610c , 0x00170000 }, + { 0x00016140 , 0x10804000 }, + { 0x00016144 , 0x01884080 }, + { 0x00016148 , 0x000080c0 }, + { 0x00016280 , 0x01000015 }, + { 0x00016284 , 0x14d20000 }, + { 0x00016288 , 0x00318000 }, + { 0x0001628c , 0x50000000 }, + { 0x00016290 , 0x4b96210f }, + { 0x00016380 , 0x00000000 }, + { 0x00016384 , 0x00000000 }, + { 0x00016388 , 0x00800700 }, + { 0x0001638c , 0x00800700 }, + { 0x00016390 , 0x00800700 }, + { 0x00016394 , 0x00000000 }, + { 0x00016398 , 0x00000000 }, + { 0x0001639c , 0x00000000 }, + { 0x000163a0 , 0x00000001 }, + { 0x000163a4 , 0x00000001 }, + { 0x000163a8 , 0x00000000 }, + { 0x000163ac , 0x00000000 }, + { 0x000163b0 , 0x00000000 }, + { 0x000163b4 , 0x00000000 }, + { 0x000163b8 , 0x00000000 }, + { 0x000163bc , 0x00000000 }, + { 0x000163c0 , 0x000000a0 }, + { 0x000163c4 , 0x000c0000 }, + { 0x000163c8 , 0x14021402 }, + { 0x000163cc , 0x00001402 }, + { 0x000163d0 , 0x00000000 }, + { 0x000163d4 , 0x00000000 }, +}; + +static const u_int32_t ar9331_hornet1_2_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e3c , 0xcf946221 , 0xcf946221 , 0xcf946221 , 0xcf946221 }, + { 0x00009e44 , 0x005c0000 , 0x005c0000 , 0x005c0000 , 0x005c0000 }, + { 0x0000a2d8 , 0x7999a800 , 0x7999a800 , 0x7999a80c , 0x7999a80c }, +}; + +static const u_int32_t ar9331_hornet1_2_mac_core_emulation[][2] = { +/* Addr allmodes */ + { 0x0000805c , 0xffffc7ff }, + { 0x00008344 , 0xaa4a105b }, +}; + +static const u_int32_t ar9331_hornet1_2_soc_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00007010 , 0x00000022 , 0x00000022 , 0x00000022 , 0x00000022 }, +}; + +static const u_int32_t ar9331_common_wo_xlna_rx_gain_hornet1_2[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00060005 }, + { 0x0000a004 , 0x00810080 }, + { 0x0000a008 , 0x00830082 }, + { 0x0000a00c , 0x00850084 }, + { 0x0000a010 , 0x01820181 }, + { 0x0000a014 , 0x01840183 }, + { 0x0000a018 , 0x01880185 }, + { 0x0000a01c , 0x018a0189 }, + { 0x0000a020 , 0x02850284 }, + { 0x0000a024 , 0x02890288 }, + { 0x0000a028 , 0x028b028a }, + { 0x0000a02c , 0x03850384 }, + { 0x0000a030 , 0x03890388 }, + { 0x0000a034 , 0x038b038a }, + { 0x0000a038 , 0x038d038c }, + { 0x0000a03c , 0x03910390 }, + { 0x0000a040 , 0x03930392 }, + { 0x0000a044 , 0x03950394 }, + { 0x0000a048 , 0x00000396 }, + { 0x0000a04c , 0x00000000 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x28282828 }, + { 0x0000a084 , 0x28282828 }, + { 0x0000a088 , 0x28282828 }, + { 0x0000a08c , 0x28282828 }, + { 0x0000a090 , 0x28282828 }, + { 0x0000a094 , 0x24242428 }, + { 0x0000a098 , 0x171e1e1e }, + { 0x0000a09c , 0x02020b0b }, + { 0x0000a0a0 , 0x02020202 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x22072208 }, + { 0x0000a0c4 , 0x22052206 }, + { 0x0000a0c8 , 0x22032204 }, + { 0x0000a0cc , 0x22012202 }, + { 0x0000a0d0 , 0x221f2200 }, + { 0x0000a0d4 , 0x221d221e }, + { 0x0000a0d8 , 0x33023303 }, + { 0x0000a0dc , 0x33003301 }, + { 0x0000a0e0 , 0x331e331f }, + { 0x0000a0e4 , 0x4402331d }, + { 0x0000a0e8 , 0x44004401 }, + { 0x0000a0ec , 0x441e441f }, + { 0x0000a0f0 , 0x55025503 }, + { 0x0000a0f4 , 0x55005501 }, + { 0x0000a0f8 , 0x551e551f }, + { 0x0000a0fc , 0x6602551d }, + { 0x0000a100 , 0x66006601 }, + { 0x0000a104 , 0x661e661f }, + { 0x0000a108 , 0x7703661d }, + { 0x0000a10c , 0x77017702 }, + { 0x0000a110 , 0x00007700 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x111f1100 }, + { 0x0000a148 , 0x111d111e }, + { 0x0000a14c , 0x111b111c }, + { 0x0000a150 , 0x22032204 }, + { 0x0000a154 , 0x22012202 }, + { 0x0000a158 , 0x221f2200 }, + { 0x0000a15c , 0x221d221e }, + { 0x0000a160 , 0x33013302 }, + { 0x0000a164 , 0x331f3300 }, + { 0x0000a168 , 0x4402331e }, + { 0x0000a16c , 0x44004401 }, + { 0x0000a170 , 0x441e441f }, + { 0x0000a174 , 0x55015502 }, + { 0x0000a178 , 0x551f5500 }, + { 0x0000a17c , 0x6602551e }, + { 0x0000a180 , 0x66006601 }, + { 0x0000a184 , 0x661e661f }, + { 0x0000a188 , 0x7703661d }, + { 0x0000a18c , 0x77017702 }, + { 0x0000a190 , 0x00007700 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000296 }, +}; + +static const u_int32_t ar9331_hornet1_2_emulation_baseband_core[][2] = { +/* Addr allmodes */ + { 0x0000a344 , 0x00000010 }, +}; + +static const u_int32_t ar9331_common_rx_gain_hornet1_2_emulation[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x02000101 }, + { 0x0000a004 , 0x02000102 }, + { 0x0000a008 , 0x02000103 }, + { 0x0000a00c , 0x02000104 }, + { 0x0000a010 , 0x02000200 }, + { 0x0000a014 , 0x02000201 }, + { 0x0000a018 , 0x02000202 }, + { 0x0000a01c , 0x02000203 }, + { 0x0000a020 , 0x02000204 }, + { 0x0000a024 , 0x02000205 }, + { 0x0000a028 , 0x02000208 }, + { 0x0000a02c , 0x02000302 }, + { 0x0000a030 , 0x02000303 }, + { 0x0000a034 , 0x02000304 }, + { 0x0000a038 , 0x02000400 }, + { 0x0000a03c , 0x02010300 }, + { 0x0000a040 , 0x02010301 }, + { 0x0000a044 , 0x02010302 }, + { 0x0000a048 , 0x02000500 }, + { 0x0000a04c , 0x02010400 }, + { 0x0000a050 , 0x02020300 }, + { 0x0000a054 , 0x02020301 }, + { 0x0000a058 , 0x02020302 }, + { 0x0000a05c , 0x02020303 }, + { 0x0000a060 , 0x02020400 }, + { 0x0000a064 , 0x02030300 }, + { 0x0000a068 , 0x02030301 }, + { 0x0000a06c , 0x02030302 }, + { 0x0000a070 , 0x02030303 }, + { 0x0000a074 , 0x02030400 }, + { 0x0000a078 , 0x02040300 }, + { 0x0000a07c , 0x02040301 }, + { 0x0000a080 , 0x02040302 }, + { 0x0000a084 , 0x02040303 }, + { 0x0000a088 , 0x02030500 }, + { 0x0000a08c , 0x02040400 }, + { 0x0000a090 , 0x02050203 }, + { 0x0000a094 , 0x02050204 }, + { 0x0000a098 , 0x02050205 }, + { 0x0000a09c , 0x02040500 }, + { 0x0000a0a0 , 0x02050301 }, + { 0x0000a0a4 , 0x02050302 }, + { 0x0000a0a8 , 0x02050303 }, + { 0x0000a0ac , 0x02050400 }, + { 0x0000a0b0 , 0x02050401 }, + { 0x0000a0b4 , 0x02050402 }, + { 0x0000a0b8 , 0x02050403 }, + { 0x0000a0bc , 0x02050500 }, + { 0x0000a0c0 , 0x02050501 }, + { 0x0000a0c4 , 0x02050502 }, + { 0x0000a0c8 , 0x02050503 }, + { 0x0000a0cc , 0x02050504 }, + { 0x0000a0d0 , 0x02050600 }, + { 0x0000a0d4 , 0x02050601 }, + { 0x0000a0d8 , 0x02050602 }, + { 0x0000a0dc , 0x02050603 }, + { 0x0000a0e0 , 0x02050604 }, + { 0x0000a0e4 , 0x02050700 }, + { 0x0000a0e8 , 0x02050701 }, + { 0x0000a0ec , 0x02050702 }, + { 0x0000a0f0 , 0x02050703 }, + { 0x0000a0f4 , 0x02050704 }, + { 0x0000a0f8 , 0x02050705 }, + { 0x0000a0fc , 0x02050708 }, + { 0x0000a100 , 0x02050709 }, + { 0x0000a104 , 0x0205070a }, + { 0x0000a108 , 0x0205070b }, + { 0x0000a10c , 0x0205070c }, + { 0x0000a110 , 0x0205070d }, + { 0x0000a114 , 0x02050710 }, + { 0x0000a118 , 0x02050711 }, + { 0x0000a11c , 0x02050712 }, + { 0x0000a120 , 0x02050713 }, + { 0x0000a124 , 0x02050714 }, + { 0x0000a128 , 0x02050715 }, + { 0x0000a12c , 0x02050730 }, + { 0x0000a130 , 0x02050731 }, + { 0x0000a134 , 0x02050732 }, + { 0x0000a138 , 0x02050733 }, + { 0x0000a13c , 0x02050734 }, + { 0x0000a140 , 0x02050735 }, + { 0x0000a144 , 0x02050750 }, + { 0x0000a148 , 0x02050751 }, + { 0x0000a14c , 0x02050752 }, + { 0x0000a150 , 0x02050753 }, + { 0x0000a154 , 0x02050754 }, + { 0x0000a158 , 0x02050755 }, + { 0x0000a15c , 0x02050770 }, + { 0x0000a160 , 0x02050771 }, + { 0x0000a164 , 0x02050772 }, + { 0x0000a168 , 0x02050773 }, + { 0x0000a16c , 0x02050774 }, + { 0x0000a170 , 0x02050775 }, + { 0x0000a174 , 0x00000776 }, + { 0x0000a178 , 0x00000776 }, + { 0x0000a17c , 0x00000776 }, + { 0x0000a180 , 0x00000776 }, + { 0x0000a184 , 0x00000776 }, + { 0x0000a188 , 0x00000776 }, + { 0x0000a18c , 0x00000776 }, + { 0x0000a190 , 0x00000776 }, + { 0x0000a194 , 0x00000776 }, + { 0x0000a198 , 0x00000776 }, + { 0x0000a19c , 0x00000776 }, + { 0x0000a1a0 , 0x00000776 }, + { 0x0000a1a4 , 0x00000776 }, + { 0x0000a1a8 , 0x00000776 }, + { 0x0000a1ac , 0x00000776 }, + { 0x0000a1b0 , 0x00000776 }, + { 0x0000a1b4 , 0x00000776 }, + { 0x0000a1b8 , 0x00000776 }, + { 0x0000a1bc , 0x00000776 }, + { 0x0000a1c0 , 0x00000776 }, + { 0x0000a1c4 , 0x00000776 }, + { 0x0000a1c8 , 0x00000776 }, + { 0x0000a1cc , 0x00000776 }, + { 0x0000a1d0 , 0x00000776 }, + { 0x0000a1d4 , 0x00000776 }, + { 0x0000a1d8 , 0x00000776 }, + { 0x0000a1dc , 0x00000776 }, + { 0x0000a1e0 , 0x00000776 }, + { 0x0000a1e4 , 0x00000776 }, + { 0x0000a1e8 , 0x00000776 }, + { 0x0000a1ec , 0x00000776 }, + { 0x0000a1f0 , 0x00000776 }, + { 0x0000a1f4 , 0x00000776 }, + { 0x0000a1f8 , 0x00000776 }, + { 0x0000a1fc , 0x00000776 }, +}; + +static const u_int32_t ar9331_hornet1_2_baseband_core[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009804 , 0xfd14e000 }, + { 0x00009808 , 0x9c0a8f6b }, + { 0x0000980c , 0x04800000 }, + { 0x00009814 , 0x9280c00a }, + { 0x00009818 , 0x00000000 }, + { 0x0000981c , 0x00020028 }, + { 0x00009834 , 0x5f3ca3de }, + { 0x00009838 , 0x0108ecff }, + { 0x0000983c , 0x14750600 }, + { 0x00009880 , 0x201fff00 }, + { 0x00009884 , 0x00001042 }, + { 0x000098a4 , 0x00200400 }, + { 0x000098b0 , 0x32840bbe }, + { 0x000098d0 , 0x004b6a8e }, + { 0x000098d4 , 0x00000820 }, + { 0x000098dc , 0x00000000 }, + { 0x000098f0 , 0x00000000 }, + { 0x000098f4 , 0x00000000 }, + { 0x00009c04 , 0x00000000 }, + { 0x00009c08 , 0x03200000 }, + { 0x00009c0c , 0x00000000 }, + { 0x00009c10 , 0x00000000 }, + { 0x00009c14 , 0x00046384 }, + { 0x00009c18 , 0x05b6b440 }, + { 0x00009c1c , 0x00b6b440 }, + { 0x00009d00 , 0xc080a333 }, + { 0x00009d04 , 0x40206c10 }, + { 0x00009d08 , 0x009c4060 }, + { 0x00009d0c , 0x1883800a }, + { 0x00009d10 , 0x01834061 }, + { 0x00009d14 , 0x00c00400 }, + { 0x00009d18 , 0x00000000 }, + { 0x00009e08 , 0x0038233c }, + { 0x00009e24 , 0x9927b515 }, + { 0x00009e28 , 0x12ef0200 }, + { 0x00009e30 , 0x06336f77 }, + { 0x00009e34 , 0x6af6532f }, + { 0x00009e38 , 0x0cc80c00 }, + { 0x00009e40 , 0x0d261820 }, + { 0x00009e4c , 0x00001004 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009fc0 , 0x803e4788 }, + { 0x00009fc4 , 0x0001efb5 }, + { 0x00009fcc , 0x40000014 }, + { 0x0000a20c , 0x00000000 }, + { 0x0000a220 , 0x00000000 }, + { 0x0000a224 , 0x00000000 }, + { 0x0000a228 , 0x10002310 }, + { 0x0000a23c , 0x00000000 }, + { 0x0000a244 , 0x0c000000 }, + { 0x0000a2a0 , 0x00000001 }, + { 0x0000a2c0 , 0x00000001 }, + { 0x0000a2c8 , 0x00000000 }, + { 0x0000a2cc , 0x18c43433 }, + { 0x0000a2d4 , 0x00000000 }, + { 0x0000a2dc , 0x00000000 }, + { 0x0000a2e0 , 0x00000000 }, + { 0x0000a2e4 , 0x00000000 }, + { 0x0000a2e8 , 0x00000000 }, + { 0x0000a2ec , 0x00000000 }, + { 0x0000a2f0 , 0x00000000 }, + { 0x0000a2f4 , 0x00000000 }, + { 0x0000a2f8 , 0x00000000 }, + { 0x0000a344 , 0x00000000 }, + { 0x0000a34c , 0x00000000 }, + { 0x0000a350 , 0x0000a000 }, + { 0x0000a364 , 0x00000000 }, + { 0x0000a370 , 0x00000000 }, + { 0x0000a390 , 0x00000001 }, + { 0x0000a394 , 0x00000444 }, + { 0x0000a398 , 0x001f0e0f }, + { 0x0000a39c , 0x0075393f }, + { 0x0000a3a0 , 0xb79f6427 }, + { 0x0000a3a4 , 0x00000000 }, + { 0x0000a3a8 , 0xaaaaaaaa }, + { 0x0000a3ac , 0x3c466478 }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a3c8 , 0x20200020 }, + { 0x0000a3cc , 0x20202020 }, + { 0x0000a3d0 , 0x20202020 }, + { 0x0000a3d4 , 0x20202020 }, + { 0x0000a3d8 , 0x20202020 }, + { 0x0000a3dc , 0x20202020 }, + { 0x0000a3e0 , 0x20202020 }, + { 0x0000a3e4 , 0x20202020 }, + { 0x0000a3e8 , 0x20202020 }, + { 0x0000a3ec , 0x20202020 }, + { 0x0000a3f0 , 0x00000000 }, + { 0x0000a3f4 , 0x00000006 }, + { 0x0000a3f8 , 0x0cdbd380 }, + { 0x0000a3fc , 0x000f0f01 }, + { 0x0000a400 , 0x8fa91f01 }, + { 0x0000a404 , 0x00000000 }, + { 0x0000a408 , 0x0e79e5c6 }, + { 0x0000a40c , 0x00820820 }, + { 0x0000a414 , 0x1ce739ce }, + { 0x0000a418 , 0x2d001dce }, + { 0x0000a41c , 0x1ce739ce }, + { 0x0000a420 , 0x000001ce }, + { 0x0000a424 , 0x1ce739ce }, + { 0x0000a428 , 0x000001ce }, + { 0x0000a42c , 0x1ce739ce }, + { 0x0000a430 , 0x1ce739ce }, + { 0x0000a434 , 0x00000000 }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a43c , 0x00000000 }, + { 0x0000a440 , 0x00000000 }, + { 0x0000a444 , 0x00000000 }, + { 0x0000a448 , 0x04000000 }, + { 0x0000a44c , 0x00000001 }, + { 0x0000a450 , 0x00010000 }, + { 0x0000a458 , 0x00000000 }, + { 0x0000a640 , 0x00000000 }, + { 0x0000a644 , 0x3fad9d74 }, + { 0x0000a648 , 0x0048060a }, + { 0x0000a64c , 0x00003c37 }, + { 0x0000a670 , 0x03020100 }, + { 0x0000a674 , 0x09080504 }, + { 0x0000a678 , 0x0d0c0b0a }, + { 0x0000a67c , 0x13121110 }, + { 0x0000a680 , 0x31301514 }, + { 0x0000a684 , 0x35343332 }, + { 0x0000a688 , 0x00000036 }, + { 0x0000a690 , 0x00000838 }, + { 0x0000a7c0 , 0x00000000 }, + { 0x0000a7c4 , 0xfffffffc }, + { 0x0000a7c8 , 0x00000000 }, + { 0x0000a7cc , 0x00000000 }, + { 0x0000a7d0 , 0x00000000 }, + { 0x0000a7d4 , 0x00000004 }, + { 0x0000a7dc , 0x00000001 }, +}; + +static const u_int32_t ar9331_modes_high_power_tx_gain_hornet1_2[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000050d7 , 0x000050d7 , 0x000050d7 , 0x000050d7 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x23000a00 , 0x23000a00 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x27000a02 , 0x27000a02 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2b000a04 , 0x2b000a04 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x3f001620 , 0x3f001620 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x41001621 , 0x41001621 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x44001640 , 0x44001640 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x46001641 , 0x46001641 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x48001642 , 0x48001642 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x4b001644 , 0x4b001644 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4e001a81 , 0x4e001a81 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x51001a83 , 0x51001a83 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x54001c84 , 0x54001c84 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x57001ce3 , 0x57001ce3 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x5b001ce5 , 0x5b001ce5 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5f001ce9 , 0x5f001ce9 }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x66001eec , 0x66001eec }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x66001eec , 0x66001eec }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x66001eec , 0x66001eec }, + { 0x0000a580 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a584 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a588 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a58c , 0x11062202 , 0x11062202 , 0x0b000200 , 0x0b000200 }, + { 0x0000a590 , 0x17022e00 , 0x17022e00 , 0x0f000202 , 0x0f000202 }, + { 0x0000a594 , 0x1d000ec2 , 0x1d000ec2 , 0x11000400 , 0x11000400 }, + { 0x0000a598 , 0x25020ec0 , 0x25020ec0 , 0x15000402 , 0x15000402 }, + { 0x0000a59c , 0x2b020ec3 , 0x2b020ec3 , 0x19000404 , 0x19000404 }, + { 0x0000a5a0 , 0x2f001f04 , 0x2f001f04 , 0x1b000603 , 0x1b000603 }, + { 0x0000a5a4 , 0x35001fc4 , 0x35001fc4 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a5a8 , 0x3c022f04 , 0x3c022f04 , 0x23000a04 , 0x23000a04 }, + { 0x0000a5ac , 0x41023e85 , 0x41023e85 , 0x26000a20 , 0x26000a20 }, + { 0x0000a5b0 , 0x48023ec6 , 0x48023ec6 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a5b4 , 0x4d023f01 , 0x4d023f01 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a5b8 , 0x53023f4b , 0x53023f4b , 0x31000e24 , 0x31000e24 }, + { 0x0000a5bc , 0x5a027f09 , 0x5a027f09 , 0x34001640 , 0x34001640 }, + { 0x0000a5c0 , 0x5f027fc9 , 0x5f027fc9 , 0x38001660 , 0x38001660 }, + { 0x0000a5c4 , 0x6502feca , 0x6502feca , 0x3b001861 , 0x3b001861 }, + { 0x0000a5c8 , 0x6b02ff4a , 0x6b02ff4a , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a5cc , 0x7203feca , 0x7203feca , 0x42001a83 , 0x42001a83 }, + { 0x0000a5d0 , 0x7703ff0b , 0x7703ff0b , 0x44001c84 , 0x44001c84 }, + { 0x0000a5d4 , 0x7d06ffcb , 0x7d06ffcb , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a5d8 , 0x8407ff0b , 0x8407ff0b , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a5dc , 0x8907ffcb , 0x8907ffcb , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a5e0 , 0x900fff0b , 0x900fff0b , 0x54001ceb , 0x54001ceb }, + { 0x0000a5e4 , 0x960fffcb , 0x960fffcb , 0x56001eec , 0x56001eec }, + { 0x0000a5e8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5ec , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f0 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f4 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5f8 , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a5fc , 0x9c1fff0b , 0x9c1fff0b , 0x56001eec , 0x56001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x02008501 , 0x02008501 , 0x02008501 , 0x02008501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008802 , 0x02008802 }, + { 0x0000a620 , 0x0300c802 , 0x0300c802 , 0x0300c802 , 0x0300c802 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x0300cc03 , 0x0300cc03 }, + { 0x0000a628 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a62c , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a630 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a634 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a638 , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, + { 0x0000a63c , 0x04011004 , 0x04011004 , 0x04011004 , 0x04011004 }, +}; + +static const u_int32_t ar9331_hornet1_2_mac_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 }, + { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 }, +}; + +static const u_int32_t ar9331_hornet1_2_mac_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, +}; + +static const u_int32_t ar9331_hornet1_2_soc_preamble[][2] = { +/* Addr allmodes */ + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000002f8 }, +}; + +static const u_int32_t ar9331_hornet1_2_xtal_40M[][2] = { +/* Addr allmodes */ + { 0x00007038 , 0x000004c2 }, + { 0x00008244 , 0x0010f400 }, + { 0x0000824c , 0x0001e800 }, + { 0x0001609c , 0x0b283f31 }, +}; + +static const u_int32_t ar9331_hornet1_2_mac_core[][2] = { +/* Addr allmodes */ + { 0x00000008 , 0x00000000 }, + { 0x00000030 , 0x00020085 }, + { 0x00000034 , 0x00000005 }, + { 0x00000040 , 0x00000000 }, + { 0x00000044 , 0x00000000 }, + { 0x00000048 , 0x00000008 }, + { 0x0000004c , 0x00000010 }, + { 0x00000050 , 0x00000000 }, + { 0x00001040 , 0x002ffc0f }, + { 0x00001044 , 0x002ffc0f }, + { 0x00001048 , 0x002ffc0f }, + { 0x0000104c , 0x002ffc0f }, + { 0x00001050 , 0x002ffc0f }, + { 0x00001054 , 0x002ffc0f }, + { 0x00001058 , 0x002ffc0f }, + { 0x0000105c , 0x002ffc0f }, + { 0x00001060 , 0x002ffc0f }, + { 0x00001064 , 0x002ffc0f }, + { 0x000010f0 , 0x00000100 }, + { 0x00001270 , 0x00000000 }, + { 0x000012b0 , 0x00000000 }, + { 0x000012f0 , 0x00000000 }, + { 0x0000143c , 0x00000000 }, + { 0x0000147c , 0x00000000 }, + { 0x00008000 , 0x00000000 }, + { 0x00008004 , 0x00000000 }, + { 0x00008008 , 0x00000000 }, + { 0x0000800c , 0x00000000 }, + { 0x00008018 , 0x00000000 }, + { 0x00008020 , 0x00000000 }, + { 0x00008038 , 0x00000000 }, + { 0x0000803c , 0x00000000 }, + { 0x00008040 , 0x00000000 }, + { 0x00008044 , 0x00000000 }, + { 0x00008048 , 0x00000000 }, + { 0x0000804c , 0xffffffff }, + { 0x00008054 , 0x00000000 }, + { 0x00008058 , 0x00000000 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008060 , 0x0000000f }, + { 0x00008064 , 0x00000000 }, + { 0x00008070 , 0x00000310 }, + { 0x00008074 , 0x00000020 }, + { 0x00008078 , 0x00000000 }, + { 0x0000809c , 0x0000000f }, + { 0x000080a0 , 0x00000000 }, + { 0x000080a4 , 0x02ff0000 }, + { 0x000080a8 , 0x0e070605 }, + { 0x000080ac , 0x0000000d }, + { 0x000080b0 , 0x00000000 }, + { 0x000080b4 , 0x00000000 }, + { 0x000080b8 , 0x00000000 }, + { 0x000080bc , 0x00000000 }, + { 0x000080c0 , 0x2a800000 }, + { 0x000080c4 , 0x06900168 }, + { 0x000080c8 , 0x13881c20 }, + { 0x000080cc , 0x01f40000 }, + { 0x000080d0 , 0x00252500 }, + { 0x000080d4 , 0x00a00000 }, + { 0x000080d8 , 0x00400000 }, + { 0x000080dc , 0x00000000 }, + { 0x000080e0 , 0xffffffff }, + { 0x000080e4 , 0x0000ffff }, + { 0x000080e8 , 0x3f3f3f3f }, + { 0x000080ec , 0x00000000 }, + { 0x000080f0 , 0x00000000 }, + { 0x000080f4 , 0x00000000 }, + { 0x000080fc , 0x00020000 }, + { 0x00008100 , 0x00000000 }, + { 0x00008108 , 0x00000052 }, + { 0x0000810c , 0x00000000 }, + { 0x00008110 , 0x00000000 }, + { 0x00008114 , 0x000007ff }, + { 0x00008118 , 0x000000aa }, + { 0x0000811c , 0x00003210 }, + { 0x00008124 , 0x00000000 }, + { 0x00008128 , 0x00000000 }, + { 0x0000812c , 0x00000000 }, + { 0x00008130 , 0x00000000 }, + { 0x00008134 , 0x00000000 }, + { 0x00008138 , 0x00000000 }, + { 0x0000813c , 0x0000ffff }, + { 0x00008144 , 0xffffffff }, + { 0x00008168 , 0x00000000 }, + { 0x0000816c , 0x00000000 }, + { 0x00008170 , 0x18486200 }, + { 0x00008174 , 0x33332210 }, + { 0x00008178 , 0x00000000 }, + { 0x0000817c , 0x00020000 }, + { 0x000081c0 , 0x00000000 }, + { 0x000081c4 , 0x33332210 }, + { 0x000081c8 , 0x00000000 }, + { 0x000081cc , 0x00000000 }, + { 0x000081d4 , 0x00000000 }, + { 0x000081ec , 0x00000000 }, + { 0x000081f0 , 0x00000000 }, + { 0x000081f4 , 0x00000000 }, + { 0x000081f8 , 0x00000000 }, + { 0x000081fc , 0x00000000 }, + { 0x00008240 , 0x00100000 }, + { 0x00008248 , 0x00000800 }, + { 0x00008250 , 0x00000000 }, + { 0x00008254 , 0x00000000 }, + { 0x00008258 , 0x00000000 }, + { 0x0000825c , 0x40000000 }, + { 0x00008260 , 0x00080922 }, + { 0x00008264 , 0x9d400010 }, + { 0x00008268 , 0xffffffff }, + { 0x0000826c , 0x0000ffff }, + { 0x00008270 , 0x00000000 }, + { 0x00008274 , 0x40000000 }, + { 0x00008278 , 0x003e4180 }, + { 0x0000827c , 0x00000004 }, + { 0x00008284 , 0x0000002c }, + { 0x00008288 , 0x0000002c }, + { 0x0000828c , 0x000000ff }, + { 0x00008294 , 0x00000000 }, + { 0x00008298 , 0x00000000 }, + { 0x0000829c , 0x00000000 }, + { 0x00008300 , 0x00000140 }, + { 0x00008314 , 0x00000000 }, + { 0x0000831c , 0x0000010d }, + { 0x00008328 , 0x00000000 }, + { 0x0000832c , 0x00000007 }, + { 0x00008330 , 0x00000302 }, + { 0x00008334 , 0x00000700 }, + { 0x00008338 , 0x00ff0000 }, + { 0x0000833c , 0x02400000 }, + { 0x00008340 , 0x000107ff }, + { 0x00008344 , 0xaa48105b }, + { 0x00008348 , 0x008f0000 }, + { 0x0000835c , 0x00000000 }, + { 0x00008360 , 0xffffffff }, + { 0x00008364 , 0xffffffff }, + { 0x00008368 , 0x00000000 }, + { 0x00008370 , 0x00000000 }, + { 0x00008374 , 0x000000ff }, + { 0x00008378 , 0x00000000 }, + { 0x0000837c , 0x00000000 }, + { 0x00008380 , 0xffffffff }, + { 0x00008384 , 0xffffffff }, + { 0x00008390 , 0xffffffff }, + { 0x00008394 , 0xffffffff }, + { 0x00008398 , 0x00000000 }, + { 0x0000839c , 0x00000000 }, + { 0x000083a0 , 0x00000000 }, + { 0x000083a4 , 0x0000fa14 }, + { 0x000083a8 , 0x000f0c00 }, + { 0x000083ac , 0x33332210 }, + { 0x000083b0 , 0x33332210 }, + { 0x000083b4 , 0x33332210 }, + { 0x000083b8 , 0x33332210 }, + { 0x000083bc , 0x00000000 }, + { 0x000083c0 , 0x00000000 }, + { 0x000083c4 , 0x00000000 }, + { 0x000083c8 , 0x00000000 }, + { 0x000083cc , 0x00000200 }, + { 0x000083d0 , 0x000301ff }, +}; + +static const u_int32_t ar9331_common_rx_gain_hornet1_2[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x01800082 }, + { 0x0000a014 , 0x01820181 }, + { 0x0000a018 , 0x01840183 }, + { 0x0000a01c , 0x01880185 }, + { 0x0000a020 , 0x018a0189 }, + { 0x0000a024 , 0x02850284 }, + { 0x0000a028 , 0x02890288 }, + { 0x0000a02c , 0x03850384 }, + { 0x0000a030 , 0x03890388 }, + { 0x0000a034 , 0x038b038a }, + { 0x0000a038 , 0x038d038c }, + { 0x0000a03c , 0x03910390 }, + { 0x0000a040 , 0x03930392 }, + { 0x0000a044 , 0x03950394 }, + { 0x0000a048 , 0x00000396 }, + { 0x0000a04c , 0x00000000 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x28282828 }, + { 0x0000a084 , 0x28282828 }, + { 0x0000a088 , 0x28282828 }, + { 0x0000a08c , 0x28282828 }, + { 0x0000a090 , 0x28282828 }, + { 0x0000a094 , 0x21212128 }, + { 0x0000a098 , 0x171c1c1c }, + { 0x0000a09c , 0x02020212 }, + { 0x0000a0a0 , 0x00000202 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x111f1100 }, + { 0x0000a0c8 , 0x111d111e }, + { 0x0000a0cc , 0x111b111c }, + { 0x0000a0d0 , 0x22032204 }, + { 0x0000a0d4 , 0x22012202 }, + { 0x0000a0d8 , 0x221f2200 }, + { 0x0000a0dc , 0x221d221e }, + { 0x0000a0e0 , 0x33013302 }, + { 0x0000a0e4 , 0x331f3300 }, + { 0x0000a0e8 , 0x4402331e }, + { 0x0000a0ec , 0x44004401 }, + { 0x0000a0f0 , 0x441e441f }, + { 0x0000a0f4 , 0x55015502 }, + { 0x0000a0f8 , 0x551f5500 }, + { 0x0000a0fc , 0x6602551e }, + { 0x0000a100 , 0x66006601 }, + { 0x0000a104 , 0x661e661f }, + { 0x0000a108 , 0x7703661d }, + { 0x0000a10c , 0x77017702 }, + { 0x0000a110 , 0x00007700 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x111f1100 }, + { 0x0000a148 , 0x111d111e }, + { 0x0000a14c , 0x111b111c }, + { 0x0000a150 , 0x22032204 }, + { 0x0000a154 , 0x22012202 }, + { 0x0000a158 , 0x221f2200 }, + { 0x0000a15c , 0x221d221e }, + { 0x0000a160 , 0x33013302 }, + { 0x0000a164 , 0x331f3300 }, + { 0x0000a168 , 0x4402331e }, + { 0x0000a16c , 0x44004401 }, + { 0x0000a170 , 0x441e441f }, + { 0x0000a174 , 0x55015502 }, + { 0x0000a178 , 0x551f5500 }, + { 0x0000a17c , 0x6602551e }, + { 0x0000a180 , 0x66006601 }, + { 0x0000a184 , 0x661e661f }, + { 0x0000a188 , 0x7703661d }, + { 0x0000a18c , 0x77017702 }, + { 0x0000a190 , 0x00007700 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000296 }, +}; + diff --git a/hal/ar9300/ar9340.ini b/hal/ar9300/ar9340.ini new file mode 100644 index 000000000000..81894de89d21 --- /dev/null +++ b/hal/ar9300/ar9340.ini @@ -0,0 +1,4330 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + + + + + + + +static const u_int32_t ar9340_wasp_1p0_baseband_postamble_emulation[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x00009e44 , 0x005c0000 , 0x005c0000 , 0x005c0000 , 0x005c0000 }, + + { 0x0000a258 , 0x02020200 , 0x02020200 , 0x02020200 , 0x02020200 }, + + { 0x0000a25c , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + + { 0x0000a28c , 0x00011111 , 0x00011111 , 0x00011111 , 0x00011111 }, + + { 0x0000a2c4 , 0x00148d18 , 0x00148d18 , 0x00148d20 , 0x00148d20 }, + + { 0x0000a2d8 , 0xf999a800 , 0xf999a800 , 0xf999a80c , 0xf999a80c }, + + { 0x0000a50c , 0x0000c00a , 0x0000c00a , 0x0000c00a , 0x0000c00a }, + + { 0x0000a538 , 0x00038e8c , 0x00038e8c , 0x00038e8c , 0x00038e8c }, + + { 0x0000a53c , 0x0003cecc , 0x0003cecc , 0x0003cecc , 0x0003cecc }, + + { 0x0000a540 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 }, + + { 0x0000a544 , 0x00044edc , 0x00044edc , 0x00044edc , 0x00044edc }, + + { 0x0000a548 , 0x00048ede , 0x00048ede , 0x00048ede , 0x00048ede }, + + { 0x0000a54c , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e }, + + { 0x0000a550 , 0x00050f5e , 0x00050f5e , 0x00050f5e , 0x00050f5e }, + + { 0x0000a554 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_mac_core_emulation[][2] = { + +/* Addr allmodes */ + + { 0x00000030 , 0x00020085 }, + + { 0x00000044 , 0x00000008 }, + + { 0x0000805c , 0xffffc7ff }, + + { 0x00008344 , 0xaa4a105b }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_radio_postamble[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x000160ac , 0xa4646800 , 0xa4646800 , 0xa4646800 , 0xa4646800 }, + + { 0x0001610c , 0x08000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x00016140 , 0x10804000 , 0x10804000 , 0x50804000 , 0x50804000 }, + + { 0x0001650c , 0x08000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x00016540 , 0x10804000 , 0x10804000 , 0x50804000 , 0x50804000 }, + +}; + + + +static const u_int32_t ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + + { 0x0000a518 , 0x21020220 , 0x21020220 , 0x16000402 , 0x16000402 }, + + { 0x0000a51c , 0x27020223 , 0x27020223 , 0x19000404 , 0x19000404 }, + + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3f001861 , 0x3f001861 }, + + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x43001a81 , 0x43001a81 }, + + { 0x0000a54c , 0x5c04286b , 0x5c04286b , 0x47001a83 , 0x47001a83 }, + + { 0x0000a550 , 0x61042a6c , 0x61042a6c , 0x4a001c84 , 0x4a001c84 }, + + { 0x0000a554 , 0x66062a6c , 0x66062a6c , 0x4e001ce3 , 0x4e001ce3 }, + + { 0x0000a558 , 0x6b062e6c , 0x6b062e6c , 0x52001ce5 , 0x52001ce5 }, + + { 0x0000a55c , 0x7006308c , 0x7006308c , 0x56001ce9 , 0x56001ce9 }, + + { 0x0000a560 , 0x730a308a , 0x730a308a , 0x5a001ceb , 0x5a001ceb }, + + { 0x0000a564 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a568 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a56c , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a570 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a574 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a578 , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a57c , 0x770a308c , 0x770a308c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x12800400 , 0x12800400 }, + + { 0x0000a598 , 0x21820220 , 0x21820220 , 0x16800402 , 0x16800402 }, + + { 0x0000a59c , 0x27820223 , 0x27820223 , 0x19800404 , 0x19800404 }, + + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1c800603 , 0x1c800603 }, + + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x21800a02 , 0x21800a02 }, + + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x25800a04 , 0x25800a04 }, + + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x28800a20 , 0x28800a20 }, + + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2c800e20 , 0x2c800e20 }, + + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x30800e22 , 0x30800e22 }, + + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x34800e24 , 0x34800e24 }, + + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x38801640 , 0x38801640 }, + + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x3c801660 , 0x3c801660 }, + + { 0x0000a5c4 , 0x5382266c , 0x5382266c , 0x3f801861 , 0x3f801861 }, + + { 0x0000a5c8 , 0x5782286c , 0x5782286c , 0x43801a81 , 0x43801a81 }, + + { 0x0000a5cc , 0x5c84286b , 0x5c84286b , 0x47801a83 , 0x47801a83 }, + + { 0x0000a5d0 , 0x61842a6c , 0x61842a6c , 0x4a801c84 , 0x4a801c84 }, + + { 0x0000a5d4 , 0x66862a6c , 0x66862a6c , 0x4e801ce3 , 0x4e801ce3 }, + + { 0x0000a5d8 , 0x6b862e6c , 0x6b862e6c , 0x52801ce5 , 0x52801ce5 }, + + { 0x0000a5dc , 0x7086308c , 0x7086308c , 0x56801ce9 , 0x56801ce9 }, + + { 0x0000a5e0 , 0x738a308a , 0x738a308a , 0x5a801ceb , 0x5a801ceb }, + + { 0x0000a5e4 , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5e8 , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5ec , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5f0 , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5f4 , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5f8 , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5fc , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x00016044 , 0x056db2db , 0x056db2db , 0x056db2db , 0x056db2db }, + + { 0x00016048 , 0x24925266 , 0x24925266 , 0x24925266 , 0x24925266 }, + + { 0x00016444 , 0x056db2db , 0x056db2db , 0x056db2db , 0x056db2db }, + + { 0x00016448 , 0x24925266 , 0x24925266 , 0x24925266 , 0x24925266 }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_baseband_core_emulation[][2] = { + +/* Addr allmodes */ + + { 0x00009800 , 0xafa68e30 }, + + { 0x00009884 , 0x00002842 }, + + { 0x00009c04 , 0xff55ff55 }, + + { 0x00009c08 , 0x0320ff55 }, + + { 0x00009e3c , 0xcf946221 }, + + { 0x00009e50 , 0x00000000 }, + + { 0x00009fcc , 0x00000014 }, + + { 0x0000a344 , 0x00000010 }, + + { 0x0000a398 , 0x00000000 }, + + { 0x0000a39c , 0x71733d01 }, + + { 0x0000a3a0 , 0xd0ad5c12 }, + + { 0x0000a3c0 , 0x22222220 }, + + { 0x0000a3c4 , 0x22222222 }, + + { 0x0000a404 , 0x00418a11 }, + + { 0x0000a418 , 0x050001ce }, + + { 0x0000a438 , 0x00001800 }, + + { 0x0000a458 , 0x01444452 }, + + { 0x0000a690 , 0x00000038 }, + +}; + + + +static const u_int32_t ar9340Modes_fast_clock_wasp_1p0[][3] = { + +/* Addr 5G_HT20 5G_HT40 */ + + { 0x00001030 , 0x00000268 , 0x000004d0 }, + + { 0x00001070 , 0x0000018c , 0x00000318 }, + + { 0x000010b0 , 0x00000fd0 , 0x00001fa0 }, + + { 0x00008014 , 0x044c044c , 0x08980898 }, + + { 0x0000801c , 0x148ec02b , 0x148ec057 }, + + { 0x00008318 , 0x000044c0 , 0x00008980 }, + + { 0x00009e00 , 0x0372131c , 0x0372131c }, + + { 0x0000a230 , 0x0000000b , 0x00000016 }, + + { 0x0000a254 , 0x00000898 , 0x00001130 }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_radio_core[][2] = { + +/* Addr allmodes */ + + { 0x00016000 , 0x36db6db6 }, //rxrf_bias1 + + { 0x00016004 , 0x6db6db40 }, //rxrf_bias2 + + { 0x00016008 , 0x73f00000 }, //rxrf_gainstages + + { 0x0001600c , 0x00000000 }, //rxrf_agc + + { 0x00016040 , 0x7f80fff8 }, //txrf1 + + { 0x00016044 , 0x03b6d2db }, //txrf2 + + { 0x00016048 , 0x24925266 }, //txrf3 + + { 0x0001604c , 0x000f0278 }, //txrf4 + + { 0x00016050 , 0x6db6db6c }, //txrf5 + + { 0x00016054 , 0x6db60000 }, //txrf6 + + { 0x00016080 , 0x00080000 }, //synth1 + + { 0x00016084 , 0x0e48048c }, //synth2 + + { 0x00016088 , 0x14214514 }, //synth3 + + { 0x0001608c , 0x119f081c }, //synth4 (beta4 -> beta6 change) ===> Revert to Beta4 setting + + { 0x00016090 , 0x24926490 }, //synth5 + + { 0x00016094 , 0x00000000 }, //synth6 + + { 0x00016098 , 0xd411eb84 }, //synth7 + + { 0x0001609c , 0x03e47f32 }, //synth8 (beta4 -> beta6 change) + + { 0x000160a0 , 0xc2108ffe }, //synth9 + + { 0x000160a4 , 0x812fc370 }, //synth10 + + { 0x000160a8 , 0x423c8000 }, //synth11 + + { 0x000160ac , 0xa4646800 }, //synth12 + + { 0x000160b0 , 0x00fe7f46 }, //synth13 (beta4 -> beta6 change) + + { 0x000160b4 , 0x92480000 }, //synth14 + + { 0x000160c0 , 0x006db6db }, //bias1 + + { 0x000160c4 , 0x6db6db60 }, //bias2 + + { 0x000160c8 , 0x6db6db6c }, //bias3 + + { 0x000160cc , 0x6de6db6c }, //bias4 + + { 0x000160d0 , 0xb6da4924 }, //bias5 + + { 0x00016100 , 0x04cb0001 }, //rxtx1 + + { 0x00016104 , 0xfff80000 }, //rxtx2 + + { 0x00016108 , 0x00080010 }, //rxtx3 + + { 0x00016140 , 0x50804008 }, //bb1 + + { 0x00016144 , 0x01884080 }, //bb2 + + { 0x00016148 , 0x000080c0 }, //bb3 + + { 0x00016280 , 0x01000015 }, //top + + { 0x00016284 , 0x15530000 }, //top2 (beta4 -> beta6 change to address the 2G RX reset-reset variation) + + { 0x00016288 , 0x00318000 }, //top3 + + { 0x0001628c , 0x50000000 }, //therm + + { 0x00016380 , 0x00000000 }, //rbist_cntrl + + { 0x00016384 , 0x00000000 }, //tx_dc_offset + + { 0x00016388 , 0x00800700 }, //tx_tonegen0 + + { 0x0001638c , 0x00800700 }, //tx_tonegen1 + + { 0x00016390 , 0x00800700 }, //tx_lftonegen0 + + { 0x00016394 , 0x00000000 }, //tx_linear_ramp_i + + { 0x00016398 , 0x00000000 }, //tx_linear_ramp_q + + { 0x0001639c , 0x00000000 }, //tx_prbs_mag + + { 0x000163a0 , 0x00000001 }, //tx_prbs_seed_i + + { 0x000163a4 , 0x00000001 }, //tx_prbs_seed_q + + { 0x000163a8 , 0x00000000 }, //cmac_dc_cancel + + { 0x000163ac , 0x00000000 }, //cmac_dc_offset + + { 0x000163b0 , 0x00000000 }, //cmac_corr + + { 0x000163b4 , 0x00000000 }, //cmac_power + + { 0x000163b8 , 0x00000000 }, //cmac_cross_corr + + { 0x000163bc , 0x00000000 }, //cmac_i2q2 + + { 0x000163c0 , 0x000000a0 }, //cmac_power_hpf + + { 0x000163c4 , 0x000c0000 }, //rxdac_set1 + + { 0x000163c8 , 0x14021402 }, //rxdac_set2 + + { 0x000163cc , 0x00001402 }, //rxdac_long_shift + + { 0x000163d0 , 0x00000000 }, //cmac_results_i + + { 0x000163d4 , 0x00000000 }, //cmac_results_q + + { 0x00016400 , 0x36db6db6 }, //ch1_rxrf_bias1 + + { 0x00016404 , 0x6db6db40 }, //ch1_rxrf_bias2 + + { 0x00016408 , 0x73f00000 }, //ch1_rxrf_gainstages + + { 0x0001640c , 0x00000000 }, //ch1_rxrf_agc + + { 0x00016440 , 0x7f80fff8 }, //ch1_txrf1 + + { 0x00016444 , 0x03b6d2db }, //ch1_txrf2 + + { 0x00016448 , 0x24927266 }, //ch1_txrf3 + + { 0x0001644c , 0x000f0278 }, //ch1_txrf4 + + { 0x00016450 , 0x6db6db6c }, //ch1_txrf5 + + { 0x00016454 , 0x6db60000 }, //ch1_txrf6 + + { 0x00016500 , 0x04cb0001 }, //ch1_rxtx1 + + { 0x00016504 , 0xfff80000 }, //ch1_rxtx2 + + { 0x00016508 , 0x00080010 }, //ch1_rxtx3 + + { 0x0001650c , 0x00000000 }, //ch1_rxtx4 + + { 0x00016540 , 0x50804008 }, //ch1_bb1 + + { 0x00016544 , 0x01884080 }, //ch1_bb2 + + { 0x00016548 , 0x000080c0 }, //ch1_bb3 + + { 0x00016780 , 0x00000000 }, //ch1_rbist_cntrl + + { 0x00016784 , 0x00000000 }, //ch1_tx_dc_offset + + { 0x00016788 , 0x00800700 }, //ch1_tx_tonegen0 + + { 0x0001678c , 0x00800700 }, //ch1_tx_tonegen1 + + { 0x00016790 , 0x00800700 }, //ch1_tx_lftonegen0 + + { 0x00016794 , 0x00000000 }, //ch1_tx_linear_ramp_i + + { 0x00016798 , 0x00000000 }, //ch1_tx_linear_ramp_q + + { 0x0001679c , 0x00000000 }, //ch1_tx_prbs_mag + + { 0x000167a0 , 0x00000001 }, //ch1_tx_prbs_seed_i + + { 0x000167a4 , 0x00000001 }, //ch1_tx_prbs_seed_q + + { 0x000167a8 , 0x00000000 }, //ch1_cmac_dc_cancel + + { 0x000167ac , 0x00000000 }, //ch1_cmac_dc_offset + + { 0x000167b0 , 0x00000000 }, //ch1_cmac_corr + + { 0x000167b4 , 0x00000000 }, //ch1_cmac_power + + { 0x000167b8 , 0x00000000 }, //ch1_cmac_cross_corr + + { 0x000167bc , 0x00000000 }, //ch1_cmac_i2q2 + + { 0x000167c0 , 0x000000a0 }, //ch1_cmac_power_hpf + + { 0x000167c4 , 0x000c0000 }, //ch1_rxdac_set1 + + { 0x000167c8 , 0x14021402 }, //ch1_rxdac_set2 + + { 0x000167cc , 0x00001402 }, //ch1_rxdac_long_shift + + { 0x000167d0 , 0x00000000 }, //ch1_cmac_results_i + + { 0x000167d4 , 0x00000000 }, //ch1_cmac_results_q + +}; + + + +static const u_int32_t ar9340_wasp_1p0_radio_core_40M[][2] = { + + { 0x0001609c , 0x02566f3a }, //synth8 (beta4 -> beta6 change) + + { 0x000160ac , 0xa4647c00 }, //synth12 (beta4 -> beta6 change) + + { 0x000160b0 , 0x01885f5a }, //synth13 (beta4 -> beta6 change) + + { 0x00008244 , 0x0010f400 }, // MAC_PCU_SLP32_MODE + + { 0x0000824c , 0x0001e800 }, // MAC_PCU_SLP32_INC +}; + + + +static const u_int32_t ar9340Common_rx_gain_table_merlin_2p0[][2] = { + +/* Addr allmodes */ + + { 0x0000a000 , 0x02000101 }, + + { 0x0000a004 , 0x02000102 }, + + { 0x0000a008 , 0x02000103 }, + + { 0x0000a00c , 0x02000104 }, + + { 0x0000a010 , 0x02000200 }, + + { 0x0000a014 , 0x02000201 }, + + { 0x0000a018 , 0x02000202 }, + + { 0x0000a01c , 0x02000203 }, + + { 0x0000a020 , 0x02000204 }, + + { 0x0000a024 , 0x02000205 }, + + { 0x0000a028 , 0x02000208 }, + + { 0x0000a02c , 0x02000302 }, + + { 0x0000a030 , 0x02000303 }, + + { 0x0000a034 , 0x02000304 }, + + { 0x0000a038 , 0x02000400 }, + + { 0x0000a03c , 0x02010300 }, + + { 0x0000a040 , 0x02010301 }, + + { 0x0000a044 , 0x02010302 }, + + { 0x0000a048 , 0x02000500 }, + + { 0x0000a04c , 0x02010400 }, + + { 0x0000a050 , 0x02020300 }, + + { 0x0000a054 , 0x02020301 }, + + { 0x0000a058 , 0x02020302 }, + + { 0x0000a05c , 0x02020303 }, + + { 0x0000a060 , 0x02020400 }, + + { 0x0000a064 , 0x02030300 }, + + { 0x0000a068 , 0x02030301 }, + + { 0x0000a06c , 0x02030302 }, + + { 0x0000a070 , 0x02030303 }, + + { 0x0000a074 , 0x02030400 }, + + { 0x0000a078 , 0x02040300 }, + + { 0x0000a07c , 0x02040301 }, + + { 0x0000a080 , 0x02040302 }, + + { 0x0000a084 , 0x02040303 }, + + { 0x0000a088 , 0x02030500 }, + + { 0x0000a08c , 0x02040400 }, + + { 0x0000a090 , 0x02050203 }, + + { 0x0000a094 , 0x02050204 }, + + { 0x0000a098 , 0x02050205 }, + + { 0x0000a09c , 0x02040500 }, + + { 0x0000a0a0 , 0x02050301 }, + + { 0x0000a0a4 , 0x02050302 }, + + { 0x0000a0a8 , 0x02050303 }, + + { 0x0000a0ac , 0x02050400 }, + + { 0x0000a0b0 , 0x02050401 }, + + { 0x0000a0b4 , 0x02050402 }, + + { 0x0000a0b8 , 0x02050403 }, + + { 0x0000a0bc , 0x02050500 }, + + { 0x0000a0c0 , 0x02050501 }, + + { 0x0000a0c4 , 0x02050502 }, + + { 0x0000a0c8 , 0x02050503 }, + + { 0x0000a0cc , 0x02050504 }, + + { 0x0000a0d0 , 0x02050600 }, + + { 0x0000a0d4 , 0x02050601 }, + + { 0x0000a0d8 , 0x02050602 }, + + { 0x0000a0dc , 0x02050603 }, + + { 0x0000a0e0 , 0x02050604 }, + + { 0x0000a0e4 , 0x02050700 }, + + { 0x0000a0e8 , 0x02050701 }, + + { 0x0000a0ec , 0x02050702 }, + + { 0x0000a0f0 , 0x02050703 }, + + { 0x0000a0f4 , 0x02050704 }, + + { 0x0000a0f8 , 0x02050705 }, + + { 0x0000a0fc , 0x02050708 }, + + { 0x0000a100 , 0x02050709 }, + + { 0x0000a104 , 0x0205070a }, + + { 0x0000a108 , 0x0205070b }, + + { 0x0000a10c , 0x0205070c }, + + { 0x0000a110 , 0x0205070d }, + + { 0x0000a114 , 0x02050710 }, + + { 0x0000a118 , 0x02050711 }, + + { 0x0000a11c , 0x02050712 }, + + { 0x0000a120 , 0x02050713 }, + + { 0x0000a124 , 0x02050714 }, + + { 0x0000a128 , 0x02050715 }, + + { 0x0000a12c , 0x02050730 }, + + { 0x0000a130 , 0x02050731 }, + + { 0x0000a134 , 0x02050732 }, + + { 0x0000a138 , 0x02050733 }, + + { 0x0000a13c , 0x02050734 }, + + { 0x0000a140 , 0x02050735 }, + + { 0x0000a144 , 0x02050750 }, + + { 0x0000a148 , 0x02050751 }, + + { 0x0000a14c , 0x02050752 }, + + { 0x0000a150 , 0x02050753 }, + + { 0x0000a154 , 0x02050754 }, + + { 0x0000a158 , 0x02050755 }, + + { 0x0000a15c , 0x02050770 }, + + { 0x0000a160 , 0x02050771 }, + + { 0x0000a164 , 0x02050772 }, + + { 0x0000a168 , 0x02050773 }, + + { 0x0000a16c , 0x02050774 }, + + { 0x0000a170 , 0x02050775 }, + + { 0x0000a174 , 0x00000776 }, + + { 0x0000a178 , 0x00000776 }, + + { 0x0000a17c , 0x00000776 }, + + { 0x0000a180 , 0x00000776 }, + + { 0x0000a184 , 0x00000776 }, + + { 0x0000a188 , 0x00000776 }, + + { 0x0000a18c , 0x00000776 }, + + { 0x0000a190 , 0x00000776 }, + + { 0x0000a194 , 0x00000776 }, + + { 0x0000a198 , 0x00000776 }, + + { 0x0000a19c , 0x00000776 }, + + { 0x0000a1a0 , 0x00000776 }, + + { 0x0000a1a4 , 0x00000776 }, + + { 0x0000a1a8 , 0x00000776 }, + + { 0x0000a1ac , 0x00000776 }, + + { 0x0000a1b0 , 0x00000776 }, + + { 0x0000a1b4 , 0x00000776 }, + + { 0x0000a1b8 , 0x00000776 }, + + { 0x0000a1bc , 0x00000776 }, + + { 0x0000a1c0 , 0x00000776 }, + + { 0x0000a1c4 , 0x00000776 }, + + { 0x0000a1c8 , 0x00000776 }, + + { 0x0000a1cc , 0x00000776 }, + + { 0x0000a1d0 , 0x00000776 }, + + { 0x0000a1d4 , 0x00000776 }, + + { 0x0000a1d8 , 0x00000776 }, + + { 0x0000a1dc , 0x00000776 }, + + { 0x0000a1e0 , 0x00000776 }, + + { 0x0000a1e4 , 0x00000776 }, + + { 0x0000a1e8 , 0x00000776 }, + + { 0x0000a1ec , 0x00000776 }, + + { 0x0000a1f0 , 0x00000776 }, + + { 0x0000a1f4 , 0x00000776 }, + + { 0x0000a1f8 , 0x00000776 }, + + { 0x0000a1fc , 0x00000776 }, + + { 0x0000b000 , 0x02000101 }, + + { 0x0000b004 , 0x02000102 }, + + { 0x0000b008 , 0x02000103 }, + + { 0x0000b00c , 0x02000104 }, + + { 0x0000b010 , 0x02000200 }, + + { 0x0000b014 , 0x02000201 }, + + { 0x0000b018 , 0x02000202 }, + + { 0x0000b01c , 0x02000203 }, + + { 0x0000b020 , 0x02000204 }, + + { 0x0000b024 , 0x02000205 }, + + { 0x0000b028 , 0x02000208 }, + + { 0x0000b02c , 0x02000302 }, + + { 0x0000b030 , 0x02000303 }, + + { 0x0000b034 , 0x02000304 }, + + { 0x0000b038 , 0x02000400 }, + + { 0x0000b03c , 0x02010300 }, + + { 0x0000b040 , 0x02010301 }, + + { 0x0000b044 , 0x02010302 }, + + { 0x0000b048 , 0x02000500 }, + + { 0x0000b04c , 0x02010400 }, + + { 0x0000b050 , 0x02020300 }, + + { 0x0000b054 , 0x02020301 }, + + { 0x0000b058 , 0x02020302 }, + + { 0x0000b05c , 0x02020303 }, + + { 0x0000b060 , 0x02020400 }, + + { 0x0000b064 , 0x02030300 }, + + { 0x0000b068 , 0x02030301 }, + + { 0x0000b06c , 0x02030302 }, + + { 0x0000b070 , 0x02030303 }, + + { 0x0000b074 , 0x02030400 }, + + { 0x0000b078 , 0x02040300 }, + + { 0x0000b07c , 0x02040301 }, + + { 0x0000b080 , 0x02040302 }, + + { 0x0000b084 , 0x02040303 }, + + { 0x0000b088 , 0x02030500 }, + + { 0x0000b08c , 0x02040400 }, + + { 0x0000b090 , 0x02050203 }, + + { 0x0000b094 , 0x02050204 }, + + { 0x0000b098 , 0x02050205 }, + + { 0x0000b09c , 0x02040500 }, + + { 0x0000b0a0 , 0x02050301 }, + + { 0x0000b0a4 , 0x02050302 }, + + { 0x0000b0a8 , 0x02050303 }, + + { 0x0000b0ac , 0x02050400 }, + + { 0x0000b0b0 , 0x02050401 }, + + { 0x0000b0b4 , 0x02050402 }, + + { 0x0000b0b8 , 0x02050403 }, + + { 0x0000b0bc , 0x02050500 }, + + { 0x0000b0c0 , 0x02050501 }, + + { 0x0000b0c4 , 0x02050502 }, + + { 0x0000b0c8 , 0x02050503 }, + + { 0x0000b0cc , 0x02050504 }, + + { 0x0000b0d0 , 0x02050600 }, + + { 0x0000b0d4 , 0x02050601 }, + + { 0x0000b0d8 , 0x02050602 }, + + { 0x0000b0dc , 0x02050603 }, + + { 0x0000b0e0 , 0x02050604 }, + + { 0x0000b0e4 , 0x02050700 }, + + { 0x0000b0e8 , 0x02050701 }, + + { 0x0000b0ec , 0x02050702 }, + + { 0x0000b0f0 , 0x02050703 }, + + { 0x0000b0f4 , 0x02050704 }, + + { 0x0000b0f8 , 0x02050705 }, + + { 0x0000b0fc , 0x02050708 }, + + { 0x0000b100 , 0x02050709 }, + + { 0x0000b104 , 0x0205070a }, + + { 0x0000b108 , 0x0205070b }, + + { 0x0000b10c , 0x0205070c }, + + { 0x0000b110 , 0x0205070d }, + + { 0x0000b114 , 0x02050710 }, + + { 0x0000b118 , 0x02050711 }, + + { 0x0000b11c , 0x02050712 }, + + { 0x0000b120 , 0x02050713 }, + + { 0x0000b124 , 0x02050714 }, + + { 0x0000b128 , 0x02050715 }, + + { 0x0000b12c , 0x02050730 }, + + { 0x0000b130 , 0x02050731 }, + + { 0x0000b134 , 0x02050732 }, + + { 0x0000b138 , 0x02050733 }, + + { 0x0000b13c , 0x02050734 }, + + { 0x0000b140 , 0x02050735 }, + + { 0x0000b144 , 0x02050750 }, + + { 0x0000b148 , 0x02050751 }, + + { 0x0000b14c , 0x02050752 }, + + { 0x0000b150 , 0x02050753 }, + + { 0x0000b154 , 0x02050754 }, + + { 0x0000b158 , 0x02050755 }, + + { 0x0000b15c , 0x02050770 }, + + { 0x0000b160 , 0x02050771 }, + + { 0x0000b164 , 0x02050772 }, + + { 0x0000b168 , 0x02050773 }, + + { 0x0000b16c , 0x02050774 }, + + { 0x0000b170 , 0x02050775 }, + + { 0x0000b174 , 0x00000776 }, + + { 0x0000b178 , 0x00000776 }, + + { 0x0000b17c , 0x00000776 }, + + { 0x0000b180 , 0x00000776 }, + + { 0x0000b184 , 0x00000776 }, + + { 0x0000b188 , 0x00000776 }, + + { 0x0000b18c , 0x00000776 }, + + { 0x0000b190 , 0x00000776 }, + + { 0x0000b194 , 0x00000776 }, + + { 0x0000b198 , 0x00000776 }, + + { 0x0000b19c , 0x00000776 }, + + { 0x0000b1a0 , 0x00000776 }, + + { 0x0000b1a4 , 0x00000776 }, + + { 0x0000b1a8 , 0x00000776 }, + + { 0x0000b1ac , 0x00000776 }, + + { 0x0000b1b0 , 0x00000776 }, + + { 0x0000b1b4 , 0x00000776 }, + + { 0x0000b1b8 , 0x00000776 }, + + { 0x0000b1bc , 0x00000776 }, + + { 0x0000b1c0 , 0x00000776 }, + + { 0x0000b1c4 , 0x00000776 }, + + { 0x0000b1c8 , 0x00000776 }, + + { 0x0000b1cc , 0x00000776 }, + + { 0x0000b1d0 , 0x00000776 }, + + { 0x0000b1d4 , 0x00000776 }, + + { 0x0000b1d8 , 0x00000776 }, + + { 0x0000b1dc , 0x00000776 }, + + { 0x0000b1e0 , 0x00000776 }, + + { 0x0000b1e4 , 0x00000776 }, + + { 0x0000b1e8 , 0x00000776 }, + + { 0x0000b1ec , 0x00000776 }, + + { 0x0000b1f0 , 0x00000776 }, + + { 0x0000b1f4 , 0x00000776 }, + + { 0x0000b1f8 , 0x00000776 }, + + { 0x0000b1fc , 0x00000776 }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_mac_postamble[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_soc_postamble[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x00007010 , 0x00000023 , 0x00000023 , 0x00000023 , 0x00000023 }, + +}; + + + +static const u_int32_t ar9340_merlin_2p0_radio_core[][2] = { + +/* Addr common */ + + { 0x00007800 , 0x00040000 }, + + { 0x00007804 , 0xdb005012 }, + + { 0x00007808 , 0x04924914 }, + + { 0x0000780c , 0x21084210 }, + + { 0x00007810 , 0x6d801300 }, + + { 0x00007814 , 0x0019beff }, + + { 0x00007818 , 0x07e41000 }, + + { 0x0000781c , 0x00392000 }, + + { 0x00007820 , 0x92592480 }, + + { 0x00007824 , 0x00040000 }, + + { 0x00007828 , 0xdb005012 }, + + { 0x0000782c , 0x04924914 }, + + { 0x00007830 , 0x21084210 }, + + { 0x00007834 , 0x6d801300 }, + + { 0x00007838 , 0x0019beff }, + + { 0x0000783c , 0x07e40000 }, + + { 0x00007840 , 0x00392000 }, + + { 0x00007844 , 0x92592480 }, + + { 0x00007848 , 0x00100000 }, + + { 0x0000784c , 0x773f0567 }, + + { 0x00007850 , 0x54214514 }, + + { 0x00007854 , 0x12035828 }, + + { 0x00007858 , 0x92592692 }, + + { 0x0000785c , 0x00000000 }, + + { 0x00007860 , 0x56400000 }, + + { 0x00007864 , 0x0a8e370e }, + + { 0x00007868 , 0xc0102850 }, + + { 0x0000786c , 0x812d4000 }, + + { 0x00007870 , 0x807ec400 }, + + { 0x00007874 , 0x001b6db0 }, + + { 0x00007878 , 0x00376b63 }, + + { 0x0000787c , 0x06db6db6 }, + + { 0x00007880 , 0x006d8000 }, + + { 0x00007884 , 0xffeffffe }, + + { 0x00007888 , 0xffeffffe }, + + { 0x0000788c , 0x00010000 }, + + { 0x00007890 , 0x02060aeb }, + + { 0x00007894 , 0x5a108000 }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_baseband_postamble[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8011 , 0xd00a8011 }, + + { 0x00009820 , 0x206a022e , 0x206a022e , 0x206a022e , 0x206a022e }, + + { 0x00009824 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 }, + + { 0x00009828 , 0x06903081 , 0x06903081 , 0x09103881 , 0x09103881 }, + + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000119c , 0x0000119c }, + + { 0x00009c00 , 0x000000c4 , 0x000000c4 , 0x000000c4 , 0x000000c4 }, + + { 0x00009e00 , 0x0372111a , 0x0372111a , 0x037216a0 , 0x037216a0 }, + + { 0x00009e04 , 0x001c2020 , 0x001c2020 , 0x001c2020 , 0x001c2020 }, + + { 0x00009e0c , 0x6c4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + + { 0x00009e10 , 0x7ec88d2e , 0x7ec88d2e , 0x7ec88d2e , 0x7ec88d2e }, + + { 0x00009e14 , 0x37b95d5e , 0x37b9605e , 0x3379605e , 0x33795d5e }, + + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + + { 0x00009e2c , 0x0000001c , 0x0000001c , 0x00000021 , 0x00000021 }, + + { 0x00009e3c , 0xcf946220 , 0xcf946220 , 0xcf946222 , 0xcf946222 }, + + { 0x00009e44 , 0x02321e27 , 0x02321e27 , 0x02291e27 , 0x02291e27 }, + + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302012 , 0x50302012 }, + + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, + + { 0x0000a204 , 0x00003ec0 , 0x00003ec4 , 0x00003ec4 , 0x00003ec0 }, + + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + + { 0x0000a22c , 0x07e26a2f , 0x07e26a2f , 0x01026a2f , 0x01026a2f }, + + { 0x0000a230 , 0x0000000a , 0x00000014 , 0x00000016 , 0x0000000b }, + + { 0x0000a234 , 0x00000fff , 0x10000fff , 0x10000fff , 0x00000fff }, + + { 0x0000a238 , 0xffb81018 , 0xffb81018 , 0xffb81018 , 0xffb81018 }, + + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + + { 0x0000a260 , 0x0a021501 , 0x0a021501 , 0x3a021501 , 0x3a021501 }, + + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, + + { 0x0000a288 , 0x00000220 , 0x00000220 , 0x00000110 , 0x00000110 }, + + { 0x0000a28c , 0x00011111 , 0x00011111 , 0x00022222 , 0x00022222 }, + + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + + { 0x0000a2d0 , 0x00041983 , 0x00041983 , 0x00041982 , 0x00041982 }, + + { 0x0000a2d8 , 0x7999a83a , 0x7999a83a , 0x7999a83a , 0x7999a83a }, + + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a830 , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + + { 0x0000ae04 , 0x001c0000 , 0x001c0000 , 0x001c0000 , 0x001c0000 }, + + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000ae1c , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + + { 0x0000ae20 , 0x000001b5 , 0x000001b5 , 0x000001ce , 0x000001ce }, + + { 0x0000b284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_baseband_core[][2] = { + +/* Addr allmodes */ + + { 0x00009800 , 0xafe68e30 }, + + { 0x00009804 , 0xfd14e000 }, + + { 0x00009808 , 0x9c0a9f6b }, + + { 0x0000980c , 0x04900000 }, + + { 0x00009814 , 0x3280c00a }, + + { 0x00009818 , 0x00000000 }, + + { 0x0000981c , 0x00020028 }, + + { 0x00009834 , 0x6400a190 }, + + { 0x00009838 , 0x0108ecff }, + + { 0x0000983c , 0x14000600 }, + + { 0x00009880 , 0x201fff00 }, + + { 0x00009884 , 0x00001042 }, + + { 0x000098a4 , 0x00200400 }, + + { 0x000098b0 , 0x32840bbe }, + + { 0x000098d0 , 0x004b6a8e }, + + { 0x000098d4 , 0x00000820 }, + + { 0x000098dc , 0x00000000 }, + + { 0x000098f0 , 0x00000000 }, + + { 0x000098f4 , 0x00000000 }, + + { 0x00009c04 , 0xff55ff55 }, + + { 0x00009c08 , 0x0320ff55 }, + + { 0x00009c0c , 0x00000000 }, + + { 0x00009c10 , 0x00000000 }, + + { 0x00009c14 , 0x00046384 }, + + { 0x00009c18 , 0x05b6b440 }, + + { 0x00009c1c , 0x00b6b440 }, + + { 0x00009d00 , 0xc080a333 }, + + { 0x00009d04 , 0x40206c10 }, + + { 0x00009d08 , 0x009c4060 }, + + { 0x00009d0c , 0x9883800a }, + + { 0x00009d10 , 0x01834061 }, + + { 0x00009d14 , 0x00c0040b }, + + { 0x00009d18 , 0x00000000 }, + + { 0x00009e08 , 0x0038230c }, + + { 0x00009e24 , 0x990bb515 }, + + { 0x00009e28 , 0x0c6f0000 }, + + { 0x00009e30 , 0x06336f77 }, + + { 0x00009e34 , 0x6af6532f }, + + { 0x00009e38 , 0x0cc80c00 }, + + { 0x00009e40 , 0x0d261820 }, + + { 0x00009e4c , 0x00001004 }, + + { 0x00009e50 , 0x00ff03f1 }, + + { 0x00009e54 , 0x00000000 }, + + { 0x00009fc0 , 0x803e4788 }, + + { 0x00009fc4 , 0x0001efb5 }, + + { 0x00009fcc , 0x40000014 }, + + { 0x00009fd0 , 0x01193b93 }, + + { 0x0000a20c , 0x00000000 }, + + { 0x0000a220 , 0x00000000 }, + + { 0x0000a224 , 0x00000000 }, + + { 0x0000a228 , 0x10002310 }, + + { 0x0000a23c , 0x00000000 }, + + { 0x0000a244 , 0x0c000000 }, + + { 0x0000a2a0 , 0x00000001 }, + + { 0x0000a2c0 , 0x00000001 }, + + { 0x0000a2c8 , 0x00000000 }, + + { 0x0000a2cc , 0x18c43433 }, + + { 0x0000a2d4 , 0x00000000 }, + + { 0x0000a2ec , 0x00000000 }, + + { 0x0000a2f0 , 0x00000000 }, + + { 0x0000a2f4 , 0x00000000 }, + + { 0x0000a2f8 , 0x00000000 }, + + { 0x0000a344 , 0x00000000 }, + + { 0x0000a34c , 0x00000000 }, + + { 0x0000a350 , 0x0000a000 }, + + { 0x0000a364 , 0x00000000 }, + + { 0x0000a370 , 0x00000000 }, + + { 0x0000a390 , 0x00000001 }, + + { 0x0000a394 , 0x00000444 }, + + { 0x0000a398 , 0x00000000 }, + + { 0x0000a39c , 0x210d0401 }, + + { 0x0000a3a0 , 0xab9a7144 }, + + { 0x0000a3a4 , 0x00000000 }, + + { 0x0000a3a8 , 0xaaaaaaaa }, + + { 0x0000a3ac , 0x3c466478 }, + + { 0x0000a3c0 , 0x20202020 }, + + { 0x0000a3c4 , 0x22222220 }, + + { 0x0000a3c8 , 0x20200020 }, + + { 0x0000a3cc , 0x20202020 }, + + { 0x0000a3d0 , 0x20202020 }, + + { 0x0000a3d4 , 0x20202020 }, + + { 0x0000a3d8 , 0x20202020 }, + + { 0x0000a3dc , 0x20202020 }, + + { 0x0000a3e0 , 0x20202020 }, + + { 0x0000a3e4 , 0x20202020 }, + + { 0x0000a3e8 , 0x20202020 }, + + { 0x0000a3ec , 0x20202020 }, + + { 0x0000a3f0 , 0x00000000 }, + + { 0x0000a3f4 , 0x00000000 }, + + { 0x0000a3f8 , 0x0cdbd380 }, + + { 0x0000a3fc , 0x000f0f01 }, + + { 0x0000a400 , 0x8fa91f01 }, + + { 0x0000a404 , 0x00000000 }, + + { 0x0000a408 , 0x0e79e5c6 }, + + { 0x0000a40c , 0x00820820 }, + + { 0x0000a414 , 0x1ce739ce }, + + { 0x0000a418 , 0x2d001dce }, + + { 0x0000a41c , 0x1ce739ce }, + + { 0x0000a420 , 0x000001ce }, + + { 0x0000a424 , 0x1ce739ce }, + + { 0x0000a428 , 0x000001ce }, + + { 0x0000a42c , 0x1ce739ce }, + + { 0x0000a430 , 0x1ce739ce }, + + { 0x0000a434 , 0x00000000 }, + + { 0x0000a438 , 0x00001801 }, + + { 0x0000a43c , 0x00100000 }, + + { 0x0000a440 , 0x00000000 }, + + { 0x0000a444 , 0x00000000 }, + + { 0x0000a448 , 0x05000080 }, + + { 0x0000a44c , 0x00000001 }, + + { 0x0000a450 , 0x00010000 }, + + { 0x0000a458 , 0x00000000 }, + + { 0x0000a640 , 0x00000000 }, + + { 0x0000a644 , 0x3fad9d74 }, + + { 0x0000a648 , 0x0048060a }, + + { 0x0000a64c , 0x00003c37 }, + + { 0x0000a670 , 0x03020100 }, + + { 0x0000a674 , 0x09080504 }, + + { 0x0000a678 , 0x0d0c0b0a }, + + { 0x0000a67c , 0x13121110 }, + + { 0x0000a680 , 0x31301514 }, + + { 0x0000a684 , 0x35343332 }, + + { 0x0000a688 , 0x00000036 }, + + { 0x0000a690 , 0x00000838 }, + + { 0x0000a7c0 , 0x00000000 }, + + { 0x0000a7c4 , 0xfffffffc }, + + { 0x0000a7c8 , 0x00000000 }, + + { 0x0000a7cc , 0x00000000 }, + + { 0x0000a7d0 , 0x00000000 }, + + { 0x0000a7d4 , 0x00000004 }, + + { 0x0000a7dc , 0x00000000 }, + + { 0x0000a8d0 , 0x004b6a8e }, + + { 0x0000a8d4 , 0x00000820 }, + + { 0x0000a8dc , 0x00000000 }, + + { 0x0000a8f0 , 0x00000000 }, + + { 0x0000a8f4 , 0x00000000 }, + + { 0x0000b2d0 , 0x00000080 }, + + { 0x0000b2d4 , 0x00000000 }, + + { 0x0000b2ec , 0x00000000 }, + + { 0x0000b2f0 , 0x00000000 }, + + { 0x0000b2f4 , 0x00000000 }, + + { 0x0000b2f8 , 0x00000000 }, + + { 0x0000b408 , 0x0e79e5c0 }, + + { 0x0000b40c , 0x00820820 }, + + { 0x0000b420 , 0x00000000 }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_baseband_postamble_dfs_channel[][3] = { + + /* Addr 5G_HT20 5G_HT40 */ + + { 0x00009824 , 0x5ac668d0 , 0x5ac668d0 }, + + { 0x00009e0c , 0x6d4000e2 , 0x6d4000e2 }, + + { 0x00009e14 , 0x37b9625e , 0x37b9625e }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_mac_postamble_emulation[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 }, + + { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 }, + +}; + + + +static const u_int32_t ar9340Modes_high_power_tx_gain_table_wasp_1p0[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x0000a2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + + { 0x0000a2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + + { 0x0000a2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008501 , 0x02008501 }, + + { 0x0000a620 , 0x0300cc03 , 0x0300cc03 , 0x0280ca03 , 0x0280ca03 }, + + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + + { 0x0000a628 , 0x0300cc03 , 0x0300cc03 , 0x04014c04 , 0x04014c04 }, + + { 0x0000a62c , 0x03810c03 , 0x03810c03 , 0x04015005 , 0x04015005 }, + + { 0x0000a630 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000a634 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000a638 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000a63c , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000b2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + + { 0x0000b2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + + { 0x0000b2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + + { 0x0000a410 , 0x000050d8 , 0x000050d8 , 0x000050d9 , 0x000050d9 }, + + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + + { 0x0000a504 , 0x04002222 , 0x04002222 , 0x02000001 , 0x02000001 }, + + { 0x0000a508 , 0x09002421 , 0x09002421 , 0x05000003 , 0x05000003 }, + + { 0x0000a50c , 0x0d002621 , 0x0d002621 , 0x0a000005 , 0x0a000005 }, + + { 0x0000a510 , 0x13004620 , 0x13004620 , 0x0e000201 , 0x0e000201 }, + + { 0x0000a514 , 0x19004a20 , 0x19004a20 , 0x11000203 , 0x11000203 }, + + { 0x0000a518 , 0x1d004e20 , 0x1d004e20 , 0x14000401 , 0x14000401 }, + + { 0x0000a51c , 0x21005420 , 0x21005420 , 0x18000403 , 0x18000403 }, + + { 0x0000a520 , 0x26005e20 , 0x26005e20 , 0x1b000602 , 0x1b000602 }, + + { 0x0000a524 , 0x2b005e40 , 0x2b005e40 , 0x1f000802 , 0x1f000802 }, + + { 0x0000a528 , 0x2f005e42 , 0x2f005e42 , 0x21000620 , 0x21000620 }, + + { 0x0000a52c , 0x33005e44 , 0x33005e44 , 0x25000820 , 0x25000820 }, + + { 0x0000a530 , 0x38005e65 , 0x38005e65 , 0x29000822 , 0x29000822 }, + + { 0x0000a534 , 0x3c005e69 , 0x3c005e69 , 0x2d000824 , 0x2d000824 }, + + { 0x0000a538 , 0x40005e6b , 0x40005e6b , 0x30000828 , 0x30000828 }, + + { 0x0000a53c , 0x44005e6d , 0x44005e6d , 0x3400082a , 0x3400082a }, + + { 0x0000a540 , 0x49005e72 , 0x49005e72 , 0x38000849 , 0x38000849 }, + + { 0x0000a544 , 0x4e005eb2 , 0x4e005eb2 , 0x3b000a2c , 0x3b000a2c }, + + { 0x0000a548 , 0x53005f12 , 0x53005f12 , 0x3e000e2b , 0x3e000e2b }, + + { 0x0000a54c , 0x59025eb5 , 0x59025eb5 , 0x42000e2d , 0x42000e2d }, + + { 0x0000a550 , 0x5e025f12 , 0x5e025f12 , 0x4500124a , 0x4500124a }, + + { 0x0000a554 , 0x61027f12 , 0x61027f12 , 0x4900124c , 0x4900124c }, + + { 0x0000a558 , 0x6702bf12 , 0x6702bf12 , 0x4c00126c , 0x4c00126c }, + + { 0x0000a55c , 0x6b02bf14 , 0x6b02bf14 , 0x4f00128c , 0x4f00128c }, + + { 0x0000a560 , 0x6f02bf16 , 0x6f02bf16 , 0x52001290 , 0x52001290 }, + + { 0x0000a564 , 0x6f02bf16 , 0x6f02bf16 , 0x56001292 , 0x56001292 }, + + { 0x0000a568 , 0x6f02bf16 , 0x6f02bf16 , 0x56001292 , 0x56001292 }, + + { 0x0000a56c , 0x6f02bf16 , 0x6f02bf16 , 0x56001292 , 0x56001292 }, + + { 0x0000a570 , 0x6f02bf16 , 0x6f02bf16 , 0x56001292 , 0x56001292 }, + + { 0x0000a574 , 0x6f02bf16 , 0x6f02bf16 , 0x56001292 , 0x56001292 }, + + { 0x0000a578 , 0x6f02bf16 , 0x6f02bf16 , 0x56001292 , 0x56001292 }, + + { 0x0000a57c , 0x6f02bf16 , 0x6f02bf16 , 0x56001292 , 0x56001292 }, + + { 0x0000a580 , 0x00802220 , 0x00802220 , 0x00800000 , 0x00800000 }, + + { 0x0000a584 , 0x04802222 , 0x04802222 , 0x02800001 , 0x02800001 }, + + { 0x0000a588 , 0x09802421 , 0x09802421 , 0x05800003 , 0x05800003 }, + + { 0x0000a58c , 0x0d802621 , 0x0d802621 , 0x0a800005 , 0x0a800005 }, + + { 0x0000a590 , 0x13804620 , 0x13804620 , 0x0e800201 , 0x0e800201 }, + + { 0x0000a594 , 0x19804a20 , 0x19804a20 , 0x11800203 , 0x11800203 }, + + { 0x0000a598 , 0x1d804e20 , 0x1d804e20 , 0x14800401 , 0x14800401 }, + + { 0x0000a59c , 0x21805420 , 0x21805420 , 0x18800403 , 0x18800403 }, + + { 0x0000a5a0 , 0x26805e20 , 0x26805e20 , 0x1b800602 , 0x1b800602 }, + + { 0x0000a5a4 , 0x2b805e40 , 0x2b805e40 , 0x1f800802 , 0x1f800802 }, + + { 0x0000a5a8 , 0x2f805e42 , 0x2f805e42 , 0x21800620 , 0x21800620 }, + + { 0x0000a5ac , 0x33805e44 , 0x33805e44 , 0x25800820 , 0x25800820 }, + + { 0x0000a5b0 , 0x38805e65 , 0x38805e65 , 0x29800822 , 0x29800822 }, + + { 0x0000a5b4 , 0x3c805e69 , 0x3c805e69 , 0x2d800824 , 0x2d800824 }, + + { 0x0000a5b8 , 0x40805e6b , 0x40805e6b , 0x30800828 , 0x30800828 }, + + { 0x0000a5bc , 0x44805e6d , 0x44805e6d , 0x3480082a , 0x3480082a }, + + { 0x0000a5c0 , 0x49805e72 , 0x49805e72 , 0x38800849 , 0x38800849 }, + + { 0x0000a5c4 , 0x4e805eb2 , 0x4e805eb2 , 0x3b800a2c , 0x3b800a2c }, + + { 0x0000a5c8 , 0x53805f12 , 0x53805f12 , 0x3e800e2b , 0x3e800e2b }, + + { 0x0000a5cc , 0x59825eb2 , 0x59825eb2 , 0x42800e2d , 0x42800e2d }, + + { 0x0000a5d0 , 0x5e825f12 , 0x5e825f12 , 0x4580124a , 0x4580124a }, + + { 0x0000a5d4 , 0x61827f12 , 0x61827f12 , 0x4980124c , 0x4980124c }, + + { 0x0000a5d8 , 0x6782bf12 , 0x6782bf12 , 0x4c80126c , 0x4c80126c }, + + { 0x0000a5dc , 0x6b82bf14 , 0x6b82bf14 , 0x4f80128c , 0x4f80128c }, + + { 0x0000a5e0 , 0x6f82bf16 , 0x6f82bf16 , 0x52801290 , 0x52801290 }, + + { 0x0000a5e4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801292 , 0x56801292 }, + + { 0x0000a5e8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801292 , 0x56801292 }, + + { 0x0000a5ec , 0x6f82bf16 , 0x6f82bf16 , 0x56801292 , 0x56801292 }, + + { 0x0000a5f0 , 0x6f82bf16 , 0x6f82bf16 , 0x56801292 , 0x56801292 }, + + { 0x0000a5f4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801292 , 0x56801292 }, + + { 0x0000a5f8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801292 , 0x56801292 }, + + { 0x0000a5fc , 0x6f82bf16 , 0x6f82bf16 , 0x56801292 , 0x56801292 }, + + { 0x00016044 , 0x056db2db , 0x056db2db , 0x022492db , 0x022492db }, + + { 0x00016048 , 0x24925266 , 0x24925266 , 0x24925266 , 0x24925266 }, + + { 0x00016444 , 0x056db2db , 0x056db2db , 0x022492db , 0x022492db }, + + { 0x00016448 , 0x24925266 , 0x24925266 , 0x24925266 , 0x24925266 }, + +}; + + + +static const u_int32_t ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x0000a2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + + { 0x0000a2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + + { 0x0000a2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + + { 0x0000a410 , 0x000050d8 , 0x000050d8 , 0x000050d9 , 0x000050d9 }, + + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + + { 0x0000a504 , 0x04002222 , 0x04002222 , 0x04000002 , 0x04000002 }, + + { 0x0000a508 , 0x09002421 , 0x09002421 , 0x08000004 , 0x08000004 }, + + { 0x0000a50c , 0x0d002621 , 0x0d002621 , 0x0b000200 , 0x0b000200 }, + + { 0x0000a510 , 0x13004620 , 0x13004620 , 0x0f000202 , 0x0f000202 }, + + { 0x0000a514 , 0x19004a20 , 0x19004a20 , 0x11000400 , 0x11000400 }, + + { 0x0000a518 , 0x1d004e20 , 0x1d004e20 , 0x15000402 , 0x15000402 }, + + { 0x0000a51c , 0x21005420 , 0x21005420 , 0x19000404 , 0x19000404 }, + + { 0x0000a520 , 0x26005e20 , 0x26005e20 , 0x1b000603 , 0x1b000603 }, + + { 0x0000a524 , 0x2b005e40 , 0x2b005e40 , 0x1f000a02 , 0x1f000a02 }, + + { 0x0000a528 , 0x2f005e42 , 0x2f005e42 , 0x23000a04 , 0x23000a04 }, + + { 0x0000a52c , 0x33005e44 , 0x33005e44 , 0x26000a20 , 0x26000a20 }, + + { 0x0000a530 , 0x38005e65 , 0x38005e65 , 0x2a000e20 , 0x2a000e20 }, + + { 0x0000a534 , 0x3c005e69 , 0x3c005e69 , 0x2e000e22 , 0x2e000e22 }, + + { 0x0000a538 , 0x40005e6b , 0x40005e6b , 0x31000e24 , 0x31000e24 }, + + { 0x0000a53c , 0x44005e6d , 0x44005e6d , 0x34001640 , 0x34001640 }, + + { 0x0000a540 , 0x49005e72 , 0x49005e72 , 0x38001660 , 0x38001660 }, + + { 0x0000a544 , 0x4e005eb2 , 0x4e005eb2 , 0x3b001861 , 0x3b001861 }, + + { 0x0000a548 , 0x53005f12 , 0x53005f12 , 0x3e001a81 , 0x3e001a81 }, + + { 0x0000a54c , 0x59025eb2 , 0x59025eb2 , 0x42001a83 , 0x42001a83 }, + + { 0x0000a550 , 0x5e025f12 , 0x5e025f12 , 0x44001c84 , 0x44001c84 }, + + { 0x0000a554 , 0x61027f12 , 0x61027f12 , 0x48001ce3 , 0x48001ce3 }, + + { 0x0000a558 , 0x6702bf12 , 0x6702bf12 , 0x4c001ce5 , 0x4c001ce5 }, + + { 0x0000a55c , 0x6b02bf14 , 0x6b02bf14 , 0x50001ce9 , 0x50001ce9 }, + + { 0x0000a560 , 0x6f02bf16 , 0x6f02bf16 , 0x54001ceb , 0x54001ceb }, + + { 0x0000a564 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a568 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a56c , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a570 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a574 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a578 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a57c , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a580 , 0x00802220 , 0x00802220 , 0x00800000 , 0x00800000 }, + + { 0x0000a584 , 0x04802222 , 0x04802222 , 0x04800002 , 0x04800002 }, + + { 0x0000a588 , 0x09802421 , 0x09802421 , 0x08800004 , 0x08800004 }, + + { 0x0000a58c , 0x0d802621 , 0x0d802621 , 0x0b800200 , 0x0b800200 }, + + { 0x0000a590 , 0x13804620 , 0x13804620 , 0x0f800202 , 0x0f800202 }, + + { 0x0000a594 , 0x19804a20 , 0x19804a20 , 0x11800400 , 0x11800400 }, + + { 0x0000a598 , 0x1d804e20 , 0x1d804e20 , 0x15800402 , 0x15800402 }, + + { 0x0000a59c , 0x21805420 , 0x21805420 , 0x19800404 , 0x19800404 }, + + { 0x0000a5a0 , 0x26805e20 , 0x26805e20 , 0x1b800603 , 0x1b800603 }, + + { 0x0000a5a4 , 0x2b805e40 , 0x2b805e40 , 0x1f800a02 , 0x1f800a02 }, + + { 0x0000a5a8 , 0x2f805e42 , 0x2f805e42 , 0x23800a04 , 0x23800a04 }, + + { 0x0000a5ac , 0x33805e44 , 0x33805e44 , 0x26800a20 , 0x26800a20 }, + + { 0x0000a5b0 , 0x38805e65 , 0x38805e65 , 0x2a800e20 , 0x2a800e20 }, + + { 0x0000a5b4 , 0x3c805e69 , 0x3c805e69 , 0x2e800e22 , 0x2e800e22 }, + + { 0x0000a5b8 , 0x40805e6b , 0x40805e6b , 0x31800e24 , 0x31800e24 }, + + { 0x0000a5bc , 0x44805e6d , 0x44805e6d , 0x34801640 , 0x34801640 }, + + { 0x0000a5c0 , 0x49805e72 , 0x49805e72 , 0x38801660 , 0x38801660 }, + + { 0x0000a5c4 , 0x4e805eb2 , 0x4e805eb2 , 0x3b801861 , 0x3b801861 }, + + { 0x0000a5c8 , 0x53805f12 , 0x53805f12 , 0x3e801a81 , 0x3e801a81 }, + + { 0x0000a5cc , 0x59825eb2 , 0x59825eb2 , 0x42801a83 , 0x42801a83 }, + + { 0x0000a5d0 , 0x5e825f12 , 0x5e825f12 , 0x44801c84 , 0x44801c84 }, + + { 0x0000a5d4 , 0x61827f12 , 0x61827f12 , 0x48801ce3 , 0x48801ce3 }, + + { 0x0000a5d8 , 0x6782bf12 , 0x6782bf12 , 0x4c801ce5 , 0x4c801ce5 }, + + { 0x0000a5dc , 0x6b82bf14 , 0x6b82bf14 , 0x50801ce9 , 0x50801ce9 }, + + { 0x0000a5e0 , 0x6f82bf16 , 0x6f82bf16 , 0x54801ceb , 0x54801ceb }, + + { 0x0000a5e4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5e8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5ec , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5f0 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5f4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5f8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5fc , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a610 , 0x00804000 , 0x00804000 , 0x00000000 , 0x00000000 }, + + { 0x0000a614 , 0x00804201 , 0x00804201 , 0x01404000 , 0x01404000 }, + + { 0x0000a618 , 0x0280c802 , 0x0280c802 , 0x01404501 , 0x01404501 }, + + { 0x0000a61c , 0x0280ca03 , 0x0280ca03 , 0x02008501 , 0x02008501 }, + + { 0x0000a620 , 0x04c15104 , 0x04c15104 , 0x0280ca03 , 0x0280ca03 }, + + { 0x0000a624 , 0x04c15305 , 0x04c15305 , 0x03010c04 , 0x03010c04 }, + + { 0x0000a628 , 0x04c15305 , 0x04c15305 , 0x04014c04 , 0x04014c04 }, + + { 0x0000a62c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + + { 0x0000a630 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + + { 0x0000a634 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + + { 0x0000a638 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + + { 0x0000a63c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + + { 0x0000b2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + + { 0x0000b2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + + { 0x0000b2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + + { 0x00016044 , 0x03b6d2e4 , 0x03b6d2e4 , 0x03b6d2e4 , 0x03b6d2e4 }, + + { 0x00016048 , 0x8e481666 , 0x8e481666 , 0x8e481266 , 0x8e481266 }, + + { 0x00016280 , 0x01000015 , 0x01000015 , 0x01001015 , 0x01001015 }, + + { 0x00016444 , 0x03b6d2e4 , 0x03b6d2e4 , 0x03b6d2e4 , 0x03b6d2e4 }, + + { 0x00016448 , 0x8e481666 , 0x8e481666 , 0x8e481266 , 0x8e481266 }, + +}; + + + +static const u_int32_t ar9340_modes_ub124_tx_gain_table_wasp_1p0[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 }, + + { 0x00009820 , 0x206a022e , 0x206a022e , 0x206a00ae , 0x206a00ae }, + + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000059c , 0x0000059c }, + + { 0x00009e10 , 0x7ec88d2e , 0x7ec88d2e , 0x7ec82d2e , 0x7ec82d2e }, + + { 0x0000a2dc , 0xfef5d402 , 0xfef5d402 , 0xfdab5b52 , 0xfdab5b52 }, + + { 0x0000a2e0 , 0xfe896600 , 0xfe896600 , 0xfd339c84 , 0xfd339c84 }, + + { 0x0000a2e4 , 0xff01f800 , 0xff01f800 , 0xfec3e000 , 0xfec3e000 }, + + { 0x0000a2e8 , 0xfffe0000 , 0xfffe0000 , 0xfffc0000 , 0xfffc0000 }, + + { 0x0000a410 , 0x000050d8 , 0x000050d8 , 0x000050d9 , 0x000050d9 }, + + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + + { 0x0000a504 , 0x04002222 , 0x04002222 , 0x04000002 , 0x04000002 }, + + { 0x0000a508 , 0x09002421 , 0x09002421 , 0x08000004 , 0x08000004 }, + + { 0x0000a50c , 0x0d002621 , 0x0d002621 , 0x0b000200 , 0x0b000200 }, + + { 0x0000a510 , 0x13004620 , 0x13004620 , 0x0f000202 , 0x0f000202 }, + + { 0x0000a514 , 0x19004a20 , 0x19004a20 , 0x11000400 , 0x11000400 }, + + { 0x0000a518 , 0x1d004e20 , 0x1d004e20 , 0x15000402 , 0x15000402 }, + + { 0x0000a51c , 0x21005420 , 0x21005420 , 0x19000404 , 0x19000404 }, + + { 0x0000a520 , 0x26005e20 , 0x26005e20 , 0x1b000603 , 0x1b000603 }, + + { 0x0000a524 , 0x2b005e40 , 0x2b005e40 , 0x1f000a02 , 0x1f000a02 }, + + { 0x0000a528 , 0x2f005e42 , 0x2f005e42 , 0x23000a04 , 0x23000a04 }, + + { 0x0000a52c , 0x33005e44 , 0x33005e44 , 0x26000a20 , 0x26000a20 }, + + { 0x0000a530 , 0x38005e65 , 0x38005e65 , 0x2a000e20 , 0x2a000e20 }, + + { 0x0000a534 , 0x3c005e69 , 0x3c005e69 , 0x2e000e22 , 0x2e000e22 }, + + { 0x0000a538 , 0x40005e6b , 0x40005e6b , 0x31000e24 , 0x31000e24 }, + + { 0x0000a53c , 0x44005e6d , 0x44005e6d , 0x34001640 , 0x34001640 }, + + { 0x0000a540 , 0x49005e72 , 0x49005e72 , 0x38001660 , 0x38001660 }, + + { 0x0000a544 , 0x4e005eb2 , 0x4e005eb2 , 0x3b001861 , 0x3b001861 }, + + { 0x0000a548 , 0x53005f12 , 0x53005f12 , 0x3e001a81 , 0x3e001a81 }, + + { 0x0000a54c , 0x59025eb5 , 0x59025eb5 , 0x42001a83 , 0x42001a83 }, + + { 0x0000a550 , 0x5e025f12 , 0x5e025f12 , 0x44001c84 , 0x44001c84 }, + + { 0x0000a554 , 0x61027f12 , 0x61027f12 , 0x48001ce3 , 0x48001ce3 }, + + { 0x0000a558 , 0x6702bf12 , 0x6702bf12 , 0x4c001ce5 , 0x4c001ce5 }, + + { 0x0000a55c , 0x6b02bf14 , 0x6b02bf14 , 0x50001ce9 , 0x50001ce9 }, + + { 0x0000a560 , 0x6f02bf16 , 0x6f02bf16 , 0x54001ceb , 0x54001ceb }, + + { 0x0000a564 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a568 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a56c , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a570 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a574 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a578 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a57c , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + + { 0x0000a580 , 0x00802220 , 0x00802220 , 0x00800000 , 0x00800000 }, + + { 0x0000a584 , 0x04802222 , 0x04802222 , 0x04800002 , 0x04800002 }, + + { 0x0000a588 , 0x09802421 , 0x09802421 , 0x08800004 , 0x08800004 }, + + { 0x0000a58c , 0x0d802621 , 0x0d802621 , 0x0b800200 , 0x0b800200 }, + + { 0x0000a590 , 0x13804620 , 0x13804620 , 0x0f800202 , 0x0f800202 }, + + { 0x0000a594 , 0x19804a20 , 0x19804a20 , 0x11800400 , 0x11800400 }, + + { 0x0000a598 , 0x1d804e20 , 0x1d804e20 , 0x15800402 , 0x15800402 }, + + { 0x0000a59c , 0x21805420 , 0x21805420 , 0x19800404 , 0x19800404 }, + + { 0x0000a5a0 , 0x26805e20 , 0x26805e20 , 0x1b800603 , 0x1b800603 }, + + { 0x0000a5a4 , 0x2b805e40 , 0x2b805e40 , 0x1f800a02 , 0x1f800a02 }, + + { 0x0000a5a8 , 0x2f805e42 , 0x2f805e42 , 0x23800a04 , 0x23800a04 }, + + { 0x0000a5ac , 0x33805e44 , 0x33805e44 , 0x26800a20 , 0x26800a20 }, + + { 0x0000a5b0 , 0x38805e65 , 0x38805e65 , 0x2a800e20 , 0x2a800e20 }, + + { 0x0000a5b4 , 0x3c805e69 , 0x3c805e69 , 0x2e800e22 , 0x2e800e22 }, + + { 0x0000a5b8 , 0x40805e6b , 0x40805e6b , 0x31800e24 , 0x31800e24 }, + + { 0x0000a5bc , 0x44805e6d , 0x44805e6d , 0x34801640 , 0x34801640 }, + + { 0x0000a5c0 , 0x49805e72 , 0x49805e72 , 0x38801660 , 0x38801660 }, + + { 0x0000a5c4 , 0x4e805eb2 , 0x4e805eb2 , 0x3b801861 , 0x3b801861 }, + + { 0x0000a5c8 , 0x53805f12 , 0x53805f12 , 0x3e801a81 , 0x3e801a81 }, + + { 0x0000a5cc , 0x59825eb2 , 0x59825eb2 , 0x42801a83 , 0x42801a83 }, + + { 0x0000a5d0 , 0x5e825f12 , 0x5e825f12 , 0x44801c84 , 0x44801c84 }, + + { 0x0000a5d4 , 0x61827f12 , 0x61827f12 , 0x48801ce3 , 0x48801ce3 }, + + { 0x0000a5d8 , 0x6782bf12 , 0x6782bf12 , 0x4c801ce5 , 0x4c801ce5 }, + + { 0x0000a5dc , 0x6b82bf14 , 0x6b82bf14 , 0x50801ce9 , 0x50801ce9 }, + + { 0x0000a5e0 , 0x6f82bf16 , 0x6f82bf16 , 0x54801ceb , 0x54801ceb }, + + { 0x0000a5e4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5e8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5ec , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5f0 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5f4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5f8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x0000a5fc , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + + { 0x00016044 , 0x03b6d2e4 , 0x03b6d2e4 , 0x03b6d2e4 , 0x03b6d2e4 }, + + { 0x00016048 , 0x8e480086 , 0x8e480086 , 0x8e480086 , 0x8e480086 }, + + { 0x00016444 , 0x03b6d2e4 , 0x03b6d2e4 , 0x03b6d2e4 , 0x03b6d2e4 }, + + { 0x00016448 , 0x8e480086 , 0x8e480086 , 0x8e480086 , 0x8e480086 }, + + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a610 , 0x00804000 , 0x00804000 , 0x00000000 , 0x00000000 }, + + { 0x0000a614 , 0x00804201 , 0x00804201 , 0x01404000 , 0x01404000 }, + + { 0x0000a618 , 0x0280c802 , 0x0280c802 , 0x01404501 , 0x01404501 }, + + { 0x0000a61c , 0x0280ca03 , 0x0280ca03 , 0x02008501 , 0x02008501 }, + + { 0x0000a620 , 0x04c15104 , 0x04c15104 , 0x0280ca03 , 0x0280ca03 }, + + { 0x0000a624 , 0x04c15305 , 0x04c15305 , 0x03010c04 , 0x03010c04 }, + + { 0x0000a628 , 0x04c15305 , 0x04c15305 , 0x04014c04 , 0x04014c04 }, + + { 0x0000a62c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + + { 0x0000a630 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + + { 0x0000a634 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + + { 0x0000a638 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + + { 0x0000a63c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + + { 0x0000b2dc , 0xfef5d402 , 0xfef5d402 , 0xfdab5b52 , 0xfdab5b52 }, + + { 0x0000b2e0 , 0xfe896600 , 0xfe896600 , 0xfd339c84 , 0xfd339c84 }, + + { 0x0000b2e4 , 0xff01f800 , 0xff01f800 , 0xfec3e000 , 0xfec3e000 }, + + { 0x0000b2e8 , 0xfffe0000 , 0xfffe0000 , 0xfffc0000 , 0xfffc0000 }, + +}; + + + + + +static const u_int32_t ar9340Common_rx_gain_table_wasp_1p0[][2] = { + +/* Addr allmodes */ + + { 0x0000a000 , 0x00010000 }, + + { 0x0000a004 , 0x00030002 }, + + { 0x0000a008 , 0x00050004 }, + + { 0x0000a00c , 0x00810080 }, + + { 0x0000a010 , 0x00830082 }, + + { 0x0000a014 , 0x01810180 }, + + { 0x0000a018 , 0x01830182 }, + + { 0x0000a01c , 0x01850184 }, + + { 0x0000a020 , 0x01890188 }, + + { 0x0000a024 , 0x018b018a }, + + { 0x0000a028 , 0x018d018c }, + + { 0x0000a02c , 0x01910190 }, + + { 0x0000a030 , 0x01930192 }, + + { 0x0000a034 , 0x01950194 }, + + { 0x0000a038 , 0x038a0196 }, + + { 0x0000a03c , 0x038c038b }, + + { 0x0000a040 , 0x0390038d }, + + { 0x0000a044 , 0x03920391 }, + + { 0x0000a048 , 0x03940393 }, + + { 0x0000a04c , 0x03960395 }, + + { 0x0000a050 , 0x00000000 }, + + { 0x0000a054 , 0x00000000 }, + + { 0x0000a058 , 0x00000000 }, + + { 0x0000a05c , 0x00000000 }, + + { 0x0000a060 , 0x00000000 }, + + { 0x0000a064 , 0x00000000 }, + + { 0x0000a068 , 0x00000000 }, + + { 0x0000a06c , 0x00000000 }, + + { 0x0000a070 , 0x00000000 }, + + { 0x0000a074 , 0x00000000 }, + + { 0x0000a078 , 0x00000000 }, + + { 0x0000a07c , 0x00000000 }, + + { 0x0000a080 , 0x22222229 }, + + { 0x0000a084 , 0x1d1d1d1d }, + + { 0x0000a088 , 0x1d1d1d1d }, + + { 0x0000a08c , 0x1d1d1d1d }, + + { 0x0000a090 , 0x171d1d1d }, + + { 0x0000a094 , 0x11111717 }, + + { 0x0000a098 , 0x00030311 }, + + { 0x0000a09c , 0x00000000 }, + + { 0x0000a0a0 , 0x00000000 }, + + { 0x0000a0a4 , 0x00000000 }, + + { 0x0000a0a8 , 0x00000000 }, + + { 0x0000a0ac , 0x00000000 }, + + { 0x0000a0b0 , 0x00000000 }, + + { 0x0000a0b4 , 0x00000000 }, + + { 0x0000a0b8 , 0x00000000 }, + + { 0x0000a0bc , 0x00000000 }, + + { 0x0000a0c0 , 0x001f0000 }, + + { 0x0000a0c4 , 0x01000101 }, + + { 0x0000a0c8 , 0x011e011f }, + + { 0x0000a0cc , 0x011c011d }, + + { 0x0000a0d0 , 0x02030204 }, + + { 0x0000a0d4 , 0x02010202 }, + + { 0x0000a0d8 , 0x021f0200 }, + + { 0x0000a0dc , 0x0302021e }, + + { 0x0000a0e0 , 0x03000301 }, + + { 0x0000a0e4 , 0x031e031f }, + + { 0x0000a0e8 , 0x0402031d }, + + { 0x0000a0ec , 0x04000401 }, + + { 0x0000a0f0 , 0x041e041f }, + + { 0x0000a0f4 , 0x0502041d }, + + { 0x0000a0f8 , 0x05000501 }, + + { 0x0000a0fc , 0x051e051f }, + + { 0x0000a100 , 0x06010602 }, + + { 0x0000a104 , 0x061f0600 }, + + { 0x0000a108 , 0x061d061e }, + + { 0x0000a10c , 0x07020703 }, + + { 0x0000a110 , 0x07000701 }, + + { 0x0000a114 , 0x00000000 }, + + { 0x0000a118 , 0x00000000 }, + + { 0x0000a11c , 0x00000000 }, + + { 0x0000a120 , 0x00000000 }, + + { 0x0000a124 , 0x00000000 }, + + { 0x0000a128 , 0x00000000 }, + + { 0x0000a12c , 0x00000000 }, + + { 0x0000a130 , 0x00000000 }, + + { 0x0000a134 , 0x00000000 }, + + { 0x0000a138 , 0x00000000 }, + + { 0x0000a13c , 0x00000000 }, + + { 0x0000a140 , 0x001f0000 }, + + { 0x0000a144 , 0x01000101 }, + + { 0x0000a148 , 0x011e011f }, + + { 0x0000a14c , 0x011c011d }, + + { 0x0000a150 , 0x02030204 }, + + { 0x0000a154 , 0x02010202 }, + + { 0x0000a158 , 0x021f0200 }, + + { 0x0000a15c , 0x0302021e }, + + { 0x0000a160 , 0x03000301 }, + + { 0x0000a164 , 0x031e031f }, + + { 0x0000a168 , 0x0402031d }, + + { 0x0000a16c , 0x04000401 }, + + { 0x0000a170 , 0x041e041f }, + + { 0x0000a174 , 0x0502041d }, + + { 0x0000a178 , 0x05000501 }, + + { 0x0000a17c , 0x051e051f }, + + { 0x0000a180 , 0x06010602 }, + + { 0x0000a184 , 0x061f0600 }, + + { 0x0000a188 , 0x061d061e }, + + { 0x0000a18c , 0x07020703 }, + + { 0x0000a190 , 0x07000701 }, + + { 0x0000a194 , 0x00000000 }, + + { 0x0000a198 , 0x00000000 }, + + { 0x0000a19c , 0x00000000 }, + + { 0x0000a1a0 , 0x00000000 }, + + { 0x0000a1a4 , 0x00000000 }, + + { 0x0000a1a8 , 0x00000000 }, + + { 0x0000a1ac , 0x00000000 }, + + { 0x0000a1b0 , 0x00000000 }, + + { 0x0000a1b4 , 0x00000000 }, + + { 0x0000a1b8 , 0x00000000 }, + + { 0x0000a1bc , 0x00000000 }, + + { 0x0000a1c0 , 0x00000000 }, + + { 0x0000a1c4 , 0x00000000 }, + + { 0x0000a1c8 , 0x00000000 }, + + { 0x0000a1cc , 0x00000000 }, + + { 0x0000a1d0 , 0x00000000 }, + + { 0x0000a1d4 , 0x00000000 }, + + { 0x0000a1d8 , 0x00000000 }, + + { 0x0000a1dc , 0x00000000 }, + + { 0x0000a1e0 , 0x00000000 }, + + { 0x0000a1e4 , 0x00000000 }, + + { 0x0000a1e8 , 0x00000000 }, + + { 0x0000a1ec , 0x00000000 }, + + { 0x0000a1f0 , 0x00000396 }, + + { 0x0000a1f4 , 0x00000396 }, + + { 0x0000a1f8 , 0x00000396 }, + + { 0x0000a1fc , 0x00000196 }, + + { 0x0000b000 , 0x00010000 }, + + { 0x0000b004 , 0x00030002 }, + + { 0x0000b008 , 0x00050004 }, + + { 0x0000b00c , 0x00810080 }, + + { 0x0000b010 , 0x00830082 }, + + { 0x0000b014 , 0x01810180 }, + + { 0x0000b018 , 0x01830182 }, + + { 0x0000b01c , 0x01850184 }, + + { 0x0000b020 , 0x02810280 }, + + { 0x0000b024 , 0x02830282 }, + + { 0x0000b028 , 0x02850284 }, + + { 0x0000b02c , 0x02890288 }, + + { 0x0000b030 , 0x028b028a }, + + { 0x0000b034 , 0x0388028c }, + + { 0x0000b038 , 0x038a0389 }, + + { 0x0000b03c , 0x038c038b }, + + { 0x0000b040 , 0x0390038d }, + + { 0x0000b044 , 0x03920391 }, + + { 0x0000b048 , 0x03940393 }, + + { 0x0000b04c , 0x03960395 }, + + { 0x0000b050 , 0x00000000 }, + + { 0x0000b054 , 0x00000000 }, + + { 0x0000b058 , 0x00000000 }, + + { 0x0000b05c , 0x00000000 }, + + { 0x0000b060 , 0x00000000 }, + + { 0x0000b064 , 0x00000000 }, + + { 0x0000b068 , 0x00000000 }, + + { 0x0000b06c , 0x00000000 }, + + { 0x0000b070 , 0x00000000 }, + + { 0x0000b074 , 0x00000000 }, + + { 0x0000b078 , 0x00000000 }, + + { 0x0000b07c , 0x00000000 }, + + { 0x0000b080 , 0x23232323 }, + + { 0x0000b084 , 0x21232323 }, + + { 0x0000b088 , 0x19191c1e }, + + { 0x0000b08c , 0x12141417 }, + + { 0x0000b090 , 0x07070e0e }, + + { 0x0000b094 , 0x03030305 }, + + { 0x0000b098 , 0x00000003 }, + + { 0x0000b09c , 0x00000000 }, + + { 0x0000b0a0 , 0x00000000 }, + + { 0x0000b0a4 , 0x00000000 }, + + { 0x0000b0a8 , 0x00000000 }, + + { 0x0000b0ac , 0x00000000 }, + + { 0x0000b0b0 , 0x00000000 }, + + { 0x0000b0b4 , 0x00000000 }, + + { 0x0000b0b8 , 0x00000000 }, + + { 0x0000b0bc , 0x00000000 }, + + { 0x0000b0c0 , 0x003f0020 }, + + { 0x0000b0c4 , 0x00400041 }, + + { 0x0000b0c8 , 0x0140005f }, + + { 0x0000b0cc , 0x0160015f }, + + { 0x0000b0d0 , 0x017e017f }, + + { 0x0000b0d4 , 0x02410242 }, + + { 0x0000b0d8 , 0x025f0240 }, + + { 0x0000b0dc , 0x027f0260 }, + + { 0x0000b0e0 , 0x0341027e }, + + { 0x0000b0e4 , 0x035f0340 }, + + { 0x0000b0e8 , 0x037f0360 }, + + { 0x0000b0ec , 0x04400441 }, + + { 0x0000b0f0 , 0x0460045f }, + + { 0x0000b0f4 , 0x0541047f }, + + { 0x0000b0f8 , 0x055f0540 }, + + { 0x0000b0fc , 0x057f0560 }, + + { 0x0000b100 , 0x06400641 }, + + { 0x0000b104 , 0x0660065f }, + + { 0x0000b108 , 0x067e067f }, + + { 0x0000b10c , 0x07410742 }, + + { 0x0000b110 , 0x075f0740 }, + + { 0x0000b114 , 0x077f0760 }, + + { 0x0000b118 , 0x07800781 }, + + { 0x0000b11c , 0x07a0079f }, + + { 0x0000b120 , 0x07c107bf }, + + { 0x0000b124 , 0x000007c0 }, + + { 0x0000b128 , 0x00000000 }, + + { 0x0000b12c , 0x00000000 }, + + { 0x0000b130 , 0x00000000 }, + + { 0x0000b134 , 0x00000000 }, + + { 0x0000b138 , 0x00000000 }, + + { 0x0000b13c , 0x00000000 }, + + { 0x0000b140 , 0x003f0020 }, + + { 0x0000b144 , 0x00400041 }, + + { 0x0000b148 , 0x0140005f }, + + { 0x0000b14c , 0x0160015f }, + + { 0x0000b150 , 0x017e017f }, + + { 0x0000b154 , 0x02410242 }, + + { 0x0000b158 , 0x025f0240 }, + + { 0x0000b15c , 0x027f0260 }, + + { 0x0000b160 , 0x0341027e }, + + { 0x0000b164 , 0x035f0340 }, + + { 0x0000b168 , 0x037f0360 }, + + { 0x0000b16c , 0x04400441 }, + + { 0x0000b170 , 0x0460045f }, + + { 0x0000b174 , 0x0541047f }, + + { 0x0000b178 , 0x055f0540 }, + + { 0x0000b17c , 0x057f0560 }, + + { 0x0000b180 , 0x06400641 }, + + { 0x0000b184 , 0x0660065f }, + + { 0x0000b188 , 0x067e067f }, + + { 0x0000b18c , 0x07410742 }, + + { 0x0000b190 , 0x075f0740 }, + + { 0x0000b194 , 0x077f0760 }, + + { 0x0000b198 , 0x07800781 }, + + { 0x0000b19c , 0x07a0079f }, + + { 0x0000b1a0 , 0x07c107bf }, + + { 0x0000b1a4 , 0x000007c0 }, + + { 0x0000b1a8 , 0x00000000 }, + + { 0x0000b1ac , 0x00000000 }, + + { 0x0000b1b0 , 0x00000000 }, + + { 0x0000b1b4 , 0x00000000 }, + + { 0x0000b1b8 , 0x00000000 }, + + { 0x0000b1bc , 0x00000000 }, + + { 0x0000b1c0 , 0x00000000 }, + + { 0x0000b1c4 , 0x00000000 }, + + { 0x0000b1c8 , 0x00000000 }, + + { 0x0000b1cc , 0x00000000 }, + + { 0x0000b1d0 , 0x00000000 }, + + { 0x0000b1d4 , 0x00000000 }, + + { 0x0000b1d8 , 0x00000000 }, + + { 0x0000b1dc , 0x00000000 }, + + { 0x0000b1e0 , 0x00000000 }, + + { 0x0000b1e4 , 0x00000000 }, + + { 0x0000b1e8 , 0x00000000 }, + + { 0x0000b1ec , 0x00000000 }, + + { 0x0000b1f0 , 0x00000396 }, + + { 0x0000b1f4 , 0x00000396 }, + + { 0x0000b1f8 , 0x00000396 }, + + { 0x0000b1fc , 0x00000196 }, + +}; + + + +static const u_int32_t ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + + + + + { 0x0000a2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + + { 0x0000a2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + + { 0x0000a2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x16000402 , 0x16000402 }, + + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3f001861 , 0x3f001861 }, + + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x43001a81 , 0x43001a81 }, + + { 0x0000a54c , 0x5c02486b , 0x5c02486b , 0x47001a83 , 0x47001a83 }, + + { 0x0000a550 , 0x61024a6c , 0x61024a6c , 0x4a001c84 , 0x4a001c84 }, + + { 0x0000a554 , 0x66026a6c , 0x66026a6c , 0x4e001ce3 , 0x4e001ce3 }, + + { 0x0000a558 , 0x6b026e6c , 0x6b026e6c , 0x52001ce5 , 0x52001ce5 }, + + { 0x0000a55c , 0x7002708c , 0x7002708c , 0x56001ce9 , 0x56001ce9 }, + + { 0x0000a560 , 0x7302b08a , 0x7302b08a , 0x5a001ceb , 0x5a001ceb }, + + { 0x0000a564 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a568 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a56c , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a570 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a574 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a578 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a57c , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x12800400 , 0x12800400 }, + + { 0x0000a598 , 0x21820220 , 0x21820220 , 0x16800402 , 0x16800402 }, + + { 0x0000a59c , 0x27820223 , 0x27820223 , 0x19800404 , 0x19800404 }, + + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1c800603 , 0x1c800603 }, + + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x21800a02 , 0x21800a02 }, + + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x25800a04 , 0x25800a04 }, + + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x28800a20 , 0x28800a20 }, + + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2c800e20 , 0x2c800e20 }, + + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x30800e22 , 0x30800e22 }, + + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x34800e24 , 0x34800e24 }, + + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x38801640 , 0x38801640 }, + + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x3c801660 , 0x3c801660 }, + + { 0x0000a5c4 , 0x5382266c , 0x5382266c , 0x3f801861 , 0x3f801861 }, + + { 0x0000a5c8 , 0x5782286c , 0x5782286c , 0x43801a81 , 0x43801a81 }, + + { 0x0000a5cc , 0x5c84286b , 0x5c84286b , 0x47801a83 , 0x47801a83 }, + + { 0x0000a5d0 , 0x61842a6c , 0x61842a6c , 0x4a801c84 , 0x4a801c84 }, + + { 0x0000a5d4 , 0x66862a6c , 0x66862a6c , 0x4e801ce3 , 0x4e801ce3 }, + + { 0x0000a5d8 , 0x6b862e6c , 0x6b862e6c , 0x52801ce5 , 0x52801ce5 }, + + { 0x0000a5dc , 0x7086308c , 0x7086308c , 0x56801ce9 , 0x56801ce9 }, + + { 0x0000a5e0 , 0x738a308a , 0x738a308a , 0x5a801ceb , 0x5a801ceb }, + + { 0x0000a5e4 , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5e8 , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5ec , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5f0 , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5f4 , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5f8 , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a5fc , 0x778a308c , 0x778a308c , 0x5d801eec , 0x5d801eec }, + + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008501 , 0x02008501 }, + + { 0x0000a620 , 0x0300cc03 , 0x0300cc03 , 0x0280ca03 , 0x0280ca03 }, + + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + + { 0x0000a628 , 0x0300cc03 , 0x0300cc03 , 0x04014c04 , 0x04014c04 }, + + { 0x0000a62c , 0x03810c03 , 0x03810c03 , 0x04015005 , 0x04015005 }, + + { 0x0000a630 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000a634 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000a638 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000a63c , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000b2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + + { 0x0000b2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + + { 0x0000b2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + + { 0x00016044 , 0x056db2db , 0x056db2db , 0x056db2db , 0x056db2db }, + + { 0x00016048 , 0x24925666 , 0x24925666 , 0x24925266 , 0x24925266 }, + + { 0x00016280 , 0x01000015 , 0x01000015 , 0x01001015 , 0x01001015 }, + + { 0x00016288 , 0xf0318000 , 0xf0318000 , 0xf0318000 , 0xf0318000 }, //top3 + + { 0x00016444 , 0x056db2db , 0x056db2db , 0x056db2db , 0x056db2db }, + + { 0x00016448 , 0x24925666 , 0x24925666 , 0x24925266 , 0x24925266 }, + +}; + + + +static const u_int32_t ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + + + + + { 0x0000a2dc , 0x0380c7fc , 0x0380c7fc , 0x03eaac5a , 0x03eaac5a }, + + { 0x0000a2e0 , 0x0000f800 , 0x0000f800 , 0x03f330ac , 0x03f330ac }, + + { 0x0000a2e4 , 0x03ff0000 , 0x03ff0000 , 0x03fc3f00 , 0x03fc3f00 }, + + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ffc000 , 0x03ffc000 }, + + { 0x0000a394 , 0x00000444 , 0x00000444 , 0x00000404 , 0x00000404 }, + + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x02000001 , 0x02000001 }, + + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x05000003 , 0x05000003 }, + + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0a000005 , 0x0a000005 }, + + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0e000201 , 0x0e000201 }, + + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x11000203 , 0x11000203 }, + + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x14000401 , 0x14000401 }, + + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x18000403 , 0x18000403 }, + + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1b000602 , 0x1b000602 }, + + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x1f000802 , 0x1f000802 }, + + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x21000620 , 0x21000620 }, + + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x25000820 , 0x25000820 }, + + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x29000822 , 0x29000822 }, + + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x2d000824 , 0x2d000824 }, + + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x30000828 , 0x30000828 }, + + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x3400082a , 0x3400082a }, + + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x38000849 , 0x38000849 }, + + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3b000a2c , 0x3b000a2c }, + + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x3e000e2b , 0x3e000e2b }, + + { 0x0000a54c , 0x5c02486b , 0x5c02486b , 0x42000e2d , 0x42000e2d }, + + { 0x0000a550 , 0x61024a6c , 0x61024a6c , 0x4500124a , 0x4500124a }, + + { 0x0000a554 , 0x66026a6c , 0x66026a6c , 0x4900124c , 0x4900124c }, + + { 0x0000a558 , 0x6b026e6c , 0x6b026e6c , 0x4c00126c , 0x4c00126c }, + + { 0x0000a55c , 0x7002708c , 0x7002708c , 0x4f00128c , 0x4f00128c }, + + { 0x0000a560 , 0x7302b08a , 0x7302b08a , 0x52001290 , 0x52001290 }, + + { 0x0000a564 , 0x7702b08c , 0x7702b08c , 0x56001292 , 0x56001292 }, + + { 0x0000a568 , 0x7702b08c , 0x7702b08c , 0x56001292 , 0x56001292 }, + + { 0x0000a56c , 0x7702b08c , 0x7702b08c , 0x56001292 , 0x56001292 }, + + { 0x0000a570 , 0x7702b08c , 0x7702b08c , 0x56001292 , 0x56001292 }, + + { 0x0000a574 , 0x7702b08c , 0x7702b08c , 0x56001292 , 0x56001292 }, + + { 0x0000a578 , 0x7702b08c , 0x7702b08c , 0x56001292 , 0x56001292 }, + + { 0x0000a57c , 0x7702b08c , 0x7702b08c , 0x56001292 , 0x56001292 }, + + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x02800001 , 0x02800001 }, + + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x05800003 , 0x05800003 }, + + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0a800005 , 0x0a800005 }, + + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0e800201 , 0x0e800201 }, + + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x11800203 , 0x11800203 }, + + { 0x0000a598 , 0x21820220 , 0x21820220 , 0x14800401 , 0x14800401 }, + + { 0x0000a59c , 0x27820223 , 0x27820223 , 0x18800403 , 0x18800403 }, + + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1b800602 , 0x1b800602 }, + + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x1f800802 , 0x1f800802 }, + + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x21800620 , 0x21800620 }, + + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x25800820 , 0x25800820 }, + + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x29800822 , 0x29800822 }, + + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x2d800824 , 0x2d800824 }, + + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x30800828 , 0x30800828 }, + + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x3480082a , 0x3480082a }, + + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x38800849 , 0x38800849 }, + + { 0x0000a5c4 , 0x5382266c , 0x5382266c , 0x3b800a2c , 0x3b800a2c }, + + { 0x0000a5c8 , 0x5782286c , 0x5782286c , 0x3e800e2b , 0x3e800e2b }, + + { 0x0000a5cc , 0x5c84286b , 0x5c84286b , 0x42800e2d , 0x42800e2d }, + + { 0x0000a5d0 , 0x61842a6c , 0x61842a6c , 0x4580124a , 0x4580124a }, + + { 0x0000a5d4 , 0x66862a6c , 0x66862a6c , 0x4980124c , 0x4980124c }, + + { 0x0000a5d8 , 0x6b862e6c , 0x6b862e6c , 0x4c80126c , 0x4c80126c }, + + { 0x0000a5dc , 0x7086308c , 0x7086308c , 0x4f80128c , 0x4f80128c }, + + { 0x0000a5e0 , 0x738a308a , 0x738a308a , 0x52801290 , 0x52801290 }, + + { 0x0000a5e4 , 0x778a308c , 0x778a308c , 0x56801292 , 0x56801292 }, + + { 0x0000a5e8 , 0x778a308c , 0x778a308c , 0x56801292 , 0x56801292 }, + + { 0x0000a5ec , 0x778a308c , 0x778a308c , 0x56801292 , 0x56801292 }, + + { 0x0000a5f0 , 0x778a308c , 0x778a308c , 0x56801292 , 0x56801292 }, + + { 0x0000a5f4 , 0x778a308c , 0x778a308c , 0x56801292 , 0x56801292 }, + + { 0x0000a5f8 , 0x778a308c , 0x778a308c , 0x56801292 , 0x56801292 }, + + { 0x0000a5fc , 0x778a308c , 0x778a308c , 0x56801292 , 0x56801292 }, + + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404501 , 0x01404501 }, + + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x01404501 , 0x01404501 }, + + { 0x0000a620 , 0x0300cc03 , 0x0300cc03 , 0x03c0cf02 , 0x03c0cf02 }, + + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03c0cf03 , 0x03c0cf03 }, + + { 0x0000a628 , 0x0300cc03 , 0x0300cc03 , 0x04011004 , 0x04011004 }, + + { 0x0000a62c , 0x03810c03 , 0x03810c03 , 0x05419405 , 0x05419405 }, + + { 0x0000a630 , 0x03810e04 , 0x03810e04 , 0x05419506 , 0x05419506 }, + + { 0x0000a634 , 0x03810e04 , 0x03810e04 , 0x05419506 , 0x05419506 }, + + { 0x0000a638 , 0x03810e04 , 0x03810e04 , 0x05419506 , 0x05419506 }, + + { 0x0000a63c , 0x03810e04 , 0x03810e04 , 0x05419506 , 0x05419506 }, + + { 0x0000b2dc , 0x0380c7fc , 0x0380c7fc , 0x03eaac5a , 0x03eaac5a }, + + { 0x0000b2e0 , 0x0000f800 , 0x0000f800 , 0x03f330ac , 0x03f330ac }, + + { 0x0000b2e4 , 0x03ff0000 , 0x03ff0000 , 0x03fc3f00 , 0x03fc3f00 }, + + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ffc000 , 0x03ffc000 }, + + { 0x00016044 , 0x022492db , 0x022492db , 0x022492db , 0x022492db }, + + { 0x00016048 , 0x24925666 , 0x24925666 , 0x24925266 , 0x24925266 }, + + { 0x00016280 , 0x01000015 , 0x01000015 , 0x01001015 , 0x01001015 }, + + { 0x00016288 , 0xf0318000 , 0xf0318000 , 0xf0318000 , 0xf0318000 }, //top3 + + { 0x00016444 , 0x022492db , 0x022492db , 0x022492db , 0x022492db }, + + { 0x00016448 , 0x24925666 , 0x24925666 , 0x24925266 , 0x24925266 }, + +}; + + + +static const u_int32_t ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x0000a2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + + { 0x0000a2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + + { 0x0000a2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x11000400 , 0x11000400 }, + + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x15000402 , 0x15000402 }, + + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1b000603 , 0x1b000603 }, + + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x1f000a02 , 0x1f000a02 }, + + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x23000a04 , 0x23000a04 }, + + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x26000a20 , 0x26000a20 }, + + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2a000e20 , 0x2a000e20 }, + + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x2e000e22 , 0x2e000e22 }, + + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x31000e24 , 0x31000e24 }, + + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x34001640 , 0x34001640 }, + + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x38001660 , 0x38001660 }, + + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3b001861 , 0x3b001861 }, + + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x3e001a81 , 0x3e001a81 }, + + { 0x0000a54c , 0x5c02486b , 0x5c02486b , 0x42001a83 , 0x42001a83 }, + + { 0x0000a550 , 0x61024a6c , 0x61024a6c , 0x44001c84 , 0x44001c84 }, + + { 0x0000a554 , 0x66026a6c , 0x66026a6c , 0x48001ce3 , 0x48001ce3 }, + + { 0x0000a558 , 0x6b026e6c , 0x6b026e6c , 0x4c001ce5 , 0x4c001ce5 }, + + { 0x0000a55c , 0x7002708c , 0x7002708c , 0x50001ce9 , 0x50001ce9 }, + + { 0x0000a560 , 0x7302b08a , 0x7302b08a , 0x54001ceb , 0x54001ceb }, + + { 0x0000a564 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + + { 0x0000a568 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + + { 0x0000a56c , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + + { 0x0000a570 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + + { 0x0000a574 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + + { 0x0000a578 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + + { 0x0000a57c , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x11800400 , 0x11800400 }, + + { 0x0000a598 , 0x21820220 , 0x21820220 , 0x15800402 , 0x15800402 }, + + { 0x0000a59c , 0x27820223 , 0x27820223 , 0x19800404 , 0x19800404 }, + + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1b800603 , 0x1b800603 }, + + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x1f800a02 , 0x1f800a02 }, + + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x23800a04 , 0x23800a04 }, + + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x26800a20 , 0x26800a20 }, + + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2a800e20 , 0x2a800e20 }, + + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x2e800e22 , 0x2e800e22 }, + + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x31800e24 , 0x31800e24 }, + + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x34801640 , 0x34801640 }, + + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x38801660 , 0x38801660 }, + + { 0x0000a5c4 , 0x5382266c , 0x5382266c , 0x3b801861 , 0x3b801861 }, + + { 0x0000a5c8 , 0x5782286c , 0x5782286c , 0x3e801a81 , 0x3e801a81 }, + + { 0x0000a5cc , 0x5c84286b , 0x5c84286b , 0x42801a83 , 0x42801a83 }, + + { 0x0000a5d0 , 0x61842a6c , 0x61842a6c , 0x44801c84 , 0x44801c84 }, + + { 0x0000a5d4 , 0x66862a6c , 0x66862a6c , 0x48801ce3 , 0x48801ce3 }, + + { 0x0000a5d8 , 0x6b862e6c , 0x6b862e6c , 0x4c801ce5 , 0x4c801ce5 }, + + { 0x0000a5dc , 0x7086308c , 0x7086308c , 0x50801ce9 , 0x50801ce9 }, + + { 0x0000a5e0 , 0x738a308a , 0x738a308a , 0x54801ceb , 0x54801ceb }, + + { 0x0000a5e4 , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + + { 0x0000a5e8 , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + + { 0x0000a5ec , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + + { 0x0000a5f0 , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + + { 0x0000a5f4 , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + + { 0x0000a5f8 , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + + { 0x0000a5fc , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008501 , 0x02008501 }, + + { 0x0000a620 , 0x0300cc03 , 0x0300cc03 , 0x0280ca03 , 0x0280ca03 }, + + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + + { 0x0000a628 , 0x0300cc03 , 0x0300cc03 , 0x04014c04 , 0x04014c04 }, + + { 0x0000a62c , 0x03810c03 , 0x03810c03 , 0x04015005 , 0x04015005 }, + + { 0x0000a630 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000a634 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000a638 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000a63c , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + + { 0x0000b2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + + { 0x0000b2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + + { 0x0000b2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + + { 0x00016044 , 0x056db2db , 0x056db2db , 0x03b6d2e4 , 0x03b6d2e4 }, + + { 0x00016048 , 0x24925666 , 0x24925666 , 0x8e481266 , 0x8e481266 }, + + { 0x00016280 , 0x01000015 , 0x01000015 , 0x01001015 , 0x01001015 }, + + { 0x00016288 , 0x30318000 , 0x30318000 , 0x00318000 , 0x00318000 }, //top3 + + { 0x00016444 , 0x056db2db , 0x056db2db , 0x03b6d2e4 , 0x03b6d2e4 }, + + { 0x00016448 , 0x24925666 , 0x24925666 , 0x8e481266 , 0x8e481266 }, + +}; + +static const u_int32_t ar9340Modes_cus227_tx_gain_table_wasp_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2c022220 , 0x2c022220 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x30022222 , 0x30022222 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x35022225 , 0x35022225 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x3b02222a , 0x3b02222a , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x3f02222c , 0x3f02222c , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x5c02486b , 0x5c02486b , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x61024a6c , 0x61024a6c , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x66026a6c , 0x66026a6c , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x6b026e6c , 0x6b026e6c , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x7002708c , 0x7002708c , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x7302b08a , 0x7302b08a , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x11800400 , 0x11800400 }, + { 0x0000a598 , 0x21820220 , 0x21820220 , 0x15800402 , 0x15800402 }, + { 0x0000a59c , 0x27820223 , 0x27820223 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1b800603 , 0x1b800603 }, + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x1f800a02 , 0x1f800a02 }, + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x23800a04 , 0x23800a04 }, + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x26800a20 , 0x26800a20 }, + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2a800e20 , 0x2a800e20 }, + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x2e800e22 , 0x2e800e22 }, + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x31800e24 , 0x31800e24 }, + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x34801640 , 0x34801640 }, + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x38801660 , 0x38801660 }, + { 0x0000a5c4 , 0x5382266c , 0x5382266c , 0x3b801861 , 0x3b801861 }, + { 0x0000a5c8 , 0x5782286c , 0x5782286c , 0x3e801a81 , 0x3e801a81 }, + { 0x0000a5cc , 0x5c84286b , 0x5c84286b , 0x42801a83 , 0x42801a83 }, + { 0x0000a5d0 , 0x61842a6c , 0x61842a6c , 0x44801c84 , 0x44801c84 }, + { 0x0000a5d4 , 0x66862a6c , 0x66862a6c , 0x48801ce3 , 0x48801ce3 }, + { 0x0000a5d8 , 0x6b862e6c , 0x6b862e6c , 0x4c801ce5 , 0x4c801ce5 }, + { 0x0000a5dc , 0x7086308c , 0x7086308c , 0x50801ce9 , 0x50801ce9 }, + { 0x0000a5e0 , 0x738a308a , 0x738a308a , 0x54801ceb , 0x54801ceb }, + { 0x0000a5e4 , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + { 0x0000a5e8 , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + { 0x0000a5ec , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + { 0x0000a5f0 , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + { 0x0000a5f4 , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + { 0x0000a5f8 , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + { 0x0000a5fc , 0x778a308c , 0x778a308c , 0x56801eec , 0x56801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0300cc03 , 0x0300cc03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x0300cc03 , 0x0300cc03 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03810c03 , 0x03810c03 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x056db2db , 0x056db2db , 0x03b6d2e4 , 0x03b6d2e4 }, + { 0x00016048 , 0x24925666 , 0x24925666 , 0x8e481266 , 0x8e481266 }, + { 0x00016280 , 0x01000015 , 0x01000015 , 0x01001015 , 0x01001015 }, + { 0x00016288 , 0x30318000 , 0x30318000 , 0x00318000 , 0x00318000 }, //top3 + { 0x00016444 , 0x056db2db , 0x056db2db , 0x03b6d2e4 , 0x03b6d2e4 }, + { 0x00016448 , 0x24925666 , 0x24925666 , 0x8e481266 , 0x8e481266 }, + { 0x0000a3a4 , 0x00000011 , 0x00000011 , 0x00000011 , 0x00000011 }, + { 0x0000a3a8 , 0x3c3c3c3c , 0x3c3c3c3c , 0x3c3c3c3c , 0x3c3c3c3c }, + { 0x0000a3ac , 0x30303030 , 0x30303030 , 0x30303030 , 0x30303030 }, + }; + +static const u_int32_t ar9340_wasp_1p0_mac_core[][2] = { + +/* Addr allmodes */ + + { 0x00000008 , 0x00000000 }, + + { 0x00000030 , 0x00020085 }, + + { 0x00000034 , 0x00000005 }, + + { 0x00000040 , 0x00000000 }, + + { 0x00000044 , 0x00000000 }, + + { 0x00000048 , 0x00000008 }, + + { 0x0000004c , 0x00000010 }, + + { 0x00000050 , 0x00000000 }, + + { 0x00001040 , 0x002ffc0f }, + + { 0x00001044 , 0x002ffc0f }, + + { 0x00001048 , 0x002ffc0f }, + + { 0x0000104c , 0x002ffc0f }, + + { 0x00001050 , 0x002ffc0f }, + + { 0x00001054 , 0x002ffc0f }, + + { 0x00001058 , 0x002ffc0f }, + + { 0x0000105c , 0x002ffc0f }, + + { 0x00001060 , 0x002ffc0f }, + + { 0x00001064 , 0x002ffc0f }, + + { 0x000010f0 , 0x00000100 }, + + { 0x00001270 , 0x00000000 }, + + { 0x000012b0 , 0x00000000 }, + + { 0x000012f0 , 0x00000000 }, + + { 0x0000143c , 0x00000000 }, + + { 0x0000147c , 0x00000000 }, + + { 0x00008000 , 0x00000000 }, + + { 0x00008004 , 0x00000000 }, + + { 0x00008008 , 0x00000000 }, + + { 0x0000800c , 0x00000000 }, + + { 0x00008010 , 0x00080800 }, + + { 0x00008018 , 0x00000000 }, + + { 0x00008020 , 0x00000000 }, + + { 0x00008038 , 0x00000000 }, + + { 0x0000803c , 0x00000000 }, + + { 0x00008040 , 0x00000000 }, + + { 0x00008044 , 0x00000000 }, + + { 0x00008048 , 0x00000000 }, + + { 0x0000804c , 0xffffffff }, + + { 0x00008054 , 0x00000000 }, + + { 0x00008058 , 0x00000000 }, + + { 0x0000805c , 0x000fc78f }, + + { 0x00008060 , 0x0000000f }, + + { 0x00008064 , 0x00000000 }, + + { 0x00008070 , 0x00000310 }, + + { 0x00008074 , 0x00000020 }, + + { 0x00008078 , 0x00000000 }, + + { 0x0000809c , 0x0000000f }, + + { 0x000080a0 , 0x00000000 }, + + { 0x000080a4 , 0x02ff0000 }, + + { 0x000080a8 , 0x0e070605 }, + + { 0x000080ac , 0x0000000d }, + + { 0x000080b0 , 0x00000000 }, + + { 0x000080b4 , 0x00000000 }, + + { 0x000080b8 , 0x00000000 }, + + { 0x000080bc , 0x00000000 }, + + { 0x000080c0 , 0x2a800000 }, + + { 0x000080c4 , 0x06900168 }, + + { 0x000080c8 , 0x13881c22 }, + + { 0x000080cc , 0x01f40000 }, + + { 0x000080d0 , 0x00252500 }, + + { 0x000080d4 , 0x00a00000 }, + + { 0x000080d8 , 0x00400000 }, + + { 0x000080dc , 0x00000000 }, + + { 0x000080e0 , 0xffffffff }, + + { 0x000080e4 , 0x0000ffff }, + + { 0x000080e8 , 0x3f3f3f3f }, + + { 0x000080ec , 0x00000000 }, + + { 0x000080f0 , 0x00000000 }, + + { 0x000080f4 , 0x00000000 }, + + { 0x000080fc , 0x00020000 }, + + { 0x00008100 , 0x00000000 }, + + { 0x00008108 , 0x00000052 }, + + { 0x0000810c , 0x00000000 }, + + { 0x00008110 , 0x00000000 }, + + { 0x00008114 , 0x000007ff }, + + { 0x00008118 , 0x000000aa }, + + { 0x0000811c , 0x00003210 }, + + { 0x00008124 , 0x00000000 }, + + { 0x00008128 , 0x00000000 }, + + { 0x0000812c , 0x00000000 }, + + { 0x00008130 , 0x00000000 }, + + { 0x00008134 , 0x00000000 }, + + { 0x00008138 , 0x00000000 }, + + { 0x0000813c , 0x0000ffff }, + + { 0x00008144 , 0xffffffff }, + + { 0x00008168 , 0x00000000 }, + + { 0x0000816c , 0x00000000 }, + + { 0x00008170 , 0x18486200 }, + + { 0x00008174 , 0x33332210 }, + + { 0x00008178 , 0x00000000 }, + + { 0x0000817c , 0x00020000 }, + + { 0x000081c0 , 0x00000000 }, + + { 0x000081c4 , 0x33332210 }, + + { 0x000081c8 , 0x00000000 }, + + { 0x000081cc , 0x00000000 }, + + { 0x000081d4 , 0x00000000 }, + + { 0x000081ec , 0x00000000 }, + + { 0x000081f0 , 0x00000000 }, + + { 0x000081f4 , 0x00000000 }, + + { 0x000081f8 , 0x00000000 }, + + { 0x000081fc , 0x00000000 }, + + { 0x00008240 , 0x00100000 }, + + { 0x00008244 , 0x0010f3d7 }, + + { 0x00008248 , 0x00000800 }, + + { 0x0000824c , 0x0001e7ae }, + + { 0x00008250 , 0x00000000 }, + + { 0x00008254 , 0x00000000 }, + + { 0x00008258 , 0x00000000 }, + + { 0x0000825c , 0x40000000 }, + + { 0x00008260 , 0x00080922 }, + + { 0x00008264 , 0x9d400010 }, + + { 0x00008268 , 0xffffffff }, + + { 0x0000826c , 0x0000ffff }, + + { 0x00008270 , 0x00000000 }, + + { 0x00008274 , 0x40000000 }, + + { 0x00008278 , 0x003e4180 }, + + { 0x0000827c , 0x00000004 }, + + { 0x00008284 , 0x0000002c }, + + { 0x00008288 , 0x0000002c }, + + { 0x0000828c , 0x000000ff }, + + { 0x00008294 , 0x00000000 }, + + { 0x00008298 , 0x00000000 }, + + { 0x0000829c , 0x00000000 }, + + { 0x00008300 , 0x00000140 }, + + { 0x00008314 , 0x00000000 }, + + { 0x0000831c , 0x0000010d }, + + { 0x00008328 , 0x00000000 }, + + { 0x0000832c , 0x00000007 }, + + { 0x00008330 , 0x00000302 }, + + { 0x00008334 , 0x00000700 }, + + { 0x00008338 , 0x00ff0000 }, + + { 0x0000833c , 0x02400000 }, + + { 0x00008340 , 0x000107ff }, + + { 0x00008344 , 0xaa48105b }, + + { 0x00008348 , 0x008f0000 }, + + { 0x0000835c , 0x00000000 }, + + { 0x00008360 , 0xffffffff }, + + { 0x00008364 , 0xffffffff }, + + { 0x00008368 , 0x00000000 }, + + { 0x00008370 , 0x00000000 }, + + { 0x00008374 , 0x000000ff }, + + { 0x00008378 , 0x00000000 }, + + { 0x0000837c , 0x00000000 }, + + { 0x00008380 , 0xffffffff }, + + { 0x00008384 , 0xffffffff }, + + { 0x00008390 , 0xffffffff }, + + { 0x00008394 , 0xffffffff }, + + { 0x00008398 , 0x00000000 }, + + { 0x0000839c , 0x00000000 }, + + { 0x000083a0 , 0x00000000 }, + + { 0x000083a4 , 0x0000fa14 }, + + { 0x000083a8 , 0x000f0c00 }, + + { 0x000083ac , 0x33332210 }, + + { 0x000083b0 , 0x33332210 }, + + { 0x000083b4 , 0x33332210 }, + + { 0x000083b8 , 0x33332210 }, + + { 0x000083bc , 0x00000000 }, + + { 0x000083c0 , 0x00000000 }, + + { 0x000083c4 , 0x00000000 }, + + { 0x000083c8 , 0x00000000 }, + + { 0x000083cc , 0x00000200 }, + + { 0x000083d0 , 0x000101ff }, + +}; + + + +static const u_int32_t ar9340Common_wo_xlna_rx_gain_table_wasp_1p0[][2] = { + +/* Addr allmodes */ + + { 0x0000a000 , 0x00010000 }, + + { 0x0000a004 , 0x00030002 }, + + { 0x0000a008 , 0x00050004 }, + + { 0x0000a00c , 0x00810080 }, + + { 0x0000a010 , 0x00830082 }, + + { 0x0000a014 , 0x01810180 }, + + { 0x0000a018 , 0x01830182 }, + + { 0x0000a01c , 0x01850184 }, + + { 0x0000a020 , 0x01890188 }, + + { 0x0000a024 , 0x018b018a }, + + { 0x0000a028 , 0x018d018c }, + + { 0x0000a02c , 0x03820190 }, + + { 0x0000a030 , 0x03840383 }, + + { 0x0000a034 , 0x03880385 }, + + { 0x0000a038 , 0x038a0389 }, + + { 0x0000a03c , 0x038c038b }, + + { 0x0000a040 , 0x0390038d }, + + { 0x0000a044 , 0x03920391 }, + + { 0x0000a048 , 0x03940393 }, + + { 0x0000a04c , 0x03960395 }, + + { 0x0000a050 , 0x00000000 }, + + { 0x0000a054 , 0x00000000 }, + + { 0x0000a058 , 0x00000000 }, + + { 0x0000a05c , 0x00000000 }, + + { 0x0000a060 , 0x00000000 }, + + { 0x0000a064 , 0x00000000 }, + + { 0x0000a068 , 0x00000000 }, + + { 0x0000a06c , 0x00000000 }, + + { 0x0000a070 , 0x00000000 }, + + { 0x0000a074 , 0x00000000 }, + + { 0x0000a078 , 0x00000000 }, + + { 0x0000a07c , 0x00000000 }, + + { 0x0000a080 , 0x29292929 }, + + { 0x0000a084 , 0x29292929 }, + + { 0x0000a088 , 0x29292929 }, + + { 0x0000a08c , 0x29292929 }, + + { 0x0000a090 , 0x22292929 }, + + { 0x0000a094 , 0x1d1d2222 }, + + { 0x0000a098 , 0x0c111117 }, + + { 0x0000a09c , 0x00030303 }, + + { 0x0000a0a0 , 0x00000000 }, + + { 0x0000a0a4 , 0x00000000 }, + + { 0x0000a0a8 , 0x00000000 }, + + { 0x0000a0ac , 0x00000000 }, + + { 0x0000a0b0 , 0x00000000 }, + + { 0x0000a0b4 , 0x00000000 }, + + { 0x0000a0b8 , 0x00000000 }, + + { 0x0000a0bc , 0x00000000 }, + + { 0x0000a0c0 , 0x001f0000 }, + + { 0x0000a0c4 , 0x01000101 }, + + { 0x0000a0c8 , 0x011e011f }, + + { 0x0000a0cc , 0x011c011d }, + + { 0x0000a0d0 , 0x02030204 }, + + { 0x0000a0d4 , 0x02010202 }, + + { 0x0000a0d8 , 0x021f0200 }, + + { 0x0000a0dc , 0x0302021e }, + + { 0x0000a0e0 , 0x03000301 }, + + { 0x0000a0e4 , 0x031e031f }, + + { 0x0000a0e8 , 0x0402031d }, + + { 0x0000a0ec , 0x04000401 }, + + { 0x0000a0f0 , 0x041e041f }, + + { 0x0000a0f4 , 0x0502041d }, + + { 0x0000a0f8 , 0x05000501 }, + + { 0x0000a0fc , 0x051e051f }, + + { 0x0000a100 , 0x06010602 }, + + { 0x0000a104 , 0x061f0600 }, + + { 0x0000a108 , 0x061d061e }, + + { 0x0000a10c , 0x07020703 }, + + { 0x0000a110 , 0x07000701 }, + + { 0x0000a114 , 0x00000000 }, + + { 0x0000a118 , 0x00000000 }, + + { 0x0000a11c , 0x00000000 }, + + { 0x0000a120 , 0x00000000 }, + + { 0x0000a124 , 0x00000000 }, + + { 0x0000a128 , 0x00000000 }, + + { 0x0000a12c , 0x00000000 }, + + { 0x0000a130 , 0x00000000 }, + + { 0x0000a134 , 0x00000000 }, + + { 0x0000a138 , 0x00000000 }, + + { 0x0000a13c , 0x00000000 }, + + { 0x0000a140 , 0x001f0000 }, + + { 0x0000a144 , 0x01000101 }, + + { 0x0000a148 , 0x011e011f }, + + { 0x0000a14c , 0x011c011d }, + + { 0x0000a150 , 0x02030204 }, + + { 0x0000a154 , 0x02010202 }, + + { 0x0000a158 , 0x021f0200 }, + + { 0x0000a15c , 0x0302021e }, + + { 0x0000a160 , 0x03000301 }, + + { 0x0000a164 , 0x031e031f }, + + { 0x0000a168 , 0x0402031d }, + + { 0x0000a16c , 0x04000401 }, + + { 0x0000a170 , 0x041e041f }, + + { 0x0000a174 , 0x0502041d }, + + { 0x0000a178 , 0x05000501 }, + + { 0x0000a17c , 0x051e051f }, + + { 0x0000a180 , 0x06010602 }, + + { 0x0000a184 , 0x061f0600 }, + + { 0x0000a188 , 0x061d061e }, + + { 0x0000a18c , 0x07020703 }, + + { 0x0000a190 , 0x07000701 }, + + { 0x0000a194 , 0x00000000 }, + + { 0x0000a198 , 0x00000000 }, + + { 0x0000a19c , 0x00000000 }, + + { 0x0000a1a0 , 0x00000000 }, + + { 0x0000a1a4 , 0x00000000 }, + + { 0x0000a1a8 , 0x00000000 }, + + { 0x0000a1ac , 0x00000000 }, + + { 0x0000a1b0 , 0x00000000 }, + + { 0x0000a1b4 , 0x00000000 }, + + { 0x0000a1b8 , 0x00000000 }, + + { 0x0000a1bc , 0x00000000 }, + + { 0x0000a1c0 , 0x00000000 }, + + { 0x0000a1c4 , 0x00000000 }, + + { 0x0000a1c8 , 0x00000000 }, + + { 0x0000a1cc , 0x00000000 }, + + { 0x0000a1d0 , 0x00000000 }, + + { 0x0000a1d4 , 0x00000000 }, + + { 0x0000a1d8 , 0x00000000 }, + + { 0x0000a1dc , 0x00000000 }, + + { 0x0000a1e0 , 0x00000000 }, + + { 0x0000a1e4 , 0x00000000 }, + + { 0x0000a1e8 , 0x00000000 }, + + { 0x0000a1ec , 0x00000000 }, + + { 0x0000a1f0 , 0x00000396 }, + + { 0x0000a1f4 , 0x00000396 }, + + { 0x0000a1f8 , 0x00000396 }, + + { 0x0000a1fc , 0x00000196 }, + + { 0x0000b000 , 0x00010000 }, + + { 0x0000b004 , 0x00030002 }, + + { 0x0000b008 , 0x00050004 }, + + { 0x0000b00c , 0x00810080 }, + + { 0x0000b010 , 0x00830082 }, + + { 0x0000b014 , 0x01810180 }, + + { 0x0000b018 , 0x01830182 }, + + { 0x0000b01c , 0x01850184 }, + + { 0x0000b020 , 0x02810280 }, + + { 0x0000b024 , 0x02830282 }, + + { 0x0000b028 , 0x02850284 }, + + { 0x0000b02c , 0x02890288 }, + + { 0x0000b030 , 0x028b028a }, + + { 0x0000b034 , 0x0388028c }, + + { 0x0000b038 , 0x038a0389 }, + + { 0x0000b03c , 0x038c038b }, + + { 0x0000b040 , 0x0390038d }, + + { 0x0000b044 , 0x03920391 }, + + { 0x0000b048 , 0x03940393 }, + + { 0x0000b04c , 0x03960395 }, + + { 0x0000b050 , 0x00000000 }, + + { 0x0000b054 , 0x00000000 }, + + { 0x0000b058 , 0x00000000 }, + + { 0x0000b05c , 0x00000000 }, + + { 0x0000b060 , 0x00000000 }, + + { 0x0000b064 , 0x00000000 }, + + { 0x0000b068 , 0x00000000 }, + + { 0x0000b06c , 0x00000000 }, + + { 0x0000b070 , 0x00000000 }, + + { 0x0000b074 , 0x00000000 }, + + { 0x0000b078 , 0x00000000 }, + + { 0x0000b07c , 0x00000000 }, + + { 0x0000b080 , 0x32323232 }, + + { 0x0000b084 , 0x2f2f3232 }, + + { 0x0000b088 , 0x23282a2d }, + + { 0x0000b08c , 0x1c1e2123 }, + + { 0x0000b090 , 0x14171919 }, + + { 0x0000b094 , 0x0e0e1214 }, + + { 0x0000b098 , 0x03050707 }, + + { 0x0000b09c , 0x00030303 }, + + { 0x0000b0a0 , 0x00000000 }, + + { 0x0000b0a4 , 0x00000000 }, + + { 0x0000b0a8 , 0x00000000 }, + + { 0x0000b0ac , 0x00000000 }, + + { 0x0000b0b0 , 0x00000000 }, + + { 0x0000b0b4 , 0x00000000 }, + + { 0x0000b0b8 , 0x00000000 }, + + { 0x0000b0bc , 0x00000000 }, + + { 0x0000b0c0 , 0x003f0020 }, + + { 0x0000b0c4 , 0x00400041 }, + + { 0x0000b0c8 , 0x0140005f }, + + { 0x0000b0cc , 0x0160015f }, + + { 0x0000b0d0 , 0x017e017f }, + + { 0x0000b0d4 , 0x02410242 }, + + { 0x0000b0d8 , 0x025f0240 }, + + { 0x0000b0dc , 0x027f0260 }, + + { 0x0000b0e0 , 0x0341027e }, + + { 0x0000b0e4 , 0x035f0340 }, + + { 0x0000b0e8 , 0x037f0360 }, + + { 0x0000b0ec , 0x04400441 }, + + { 0x0000b0f0 , 0x0460045f }, + + { 0x0000b0f4 , 0x0541047f }, + + { 0x0000b0f8 , 0x055f0540 }, + + { 0x0000b0fc , 0x057f0560 }, + + { 0x0000b100 , 0x06400641 }, + + { 0x0000b104 , 0x0660065f }, + + { 0x0000b108 , 0x067e067f }, + + { 0x0000b10c , 0x07410742 }, + + { 0x0000b110 , 0x075f0740 }, + + { 0x0000b114 , 0x077f0760 }, + + { 0x0000b118 , 0x07800781 }, + + { 0x0000b11c , 0x07a0079f }, + + { 0x0000b120 , 0x07c107bf }, + + { 0x0000b124 , 0x000007c0 }, + + { 0x0000b128 , 0x00000000 }, + + { 0x0000b12c , 0x00000000 }, + + { 0x0000b130 , 0x00000000 }, + + { 0x0000b134 , 0x00000000 }, + + { 0x0000b138 , 0x00000000 }, + + { 0x0000b13c , 0x00000000 }, + + { 0x0000b140 , 0x003f0020 }, + + { 0x0000b144 , 0x00400041 }, + + { 0x0000b148 , 0x0140005f }, + + { 0x0000b14c , 0x0160015f }, + + { 0x0000b150 , 0x017e017f }, + + { 0x0000b154 , 0x02410242 }, + + { 0x0000b158 , 0x025f0240 }, + + { 0x0000b15c , 0x027f0260 }, + + { 0x0000b160 , 0x0341027e }, + + { 0x0000b164 , 0x035f0340 }, + + { 0x0000b168 , 0x037f0360 }, + + { 0x0000b16c , 0x04400441 }, + + { 0x0000b170 , 0x0460045f }, + + { 0x0000b174 , 0x0541047f }, + + { 0x0000b178 , 0x055f0540 }, + + { 0x0000b17c , 0x057f0560 }, + + { 0x0000b180 , 0x06400641 }, + + { 0x0000b184 , 0x0660065f }, + + { 0x0000b188 , 0x067e067f }, + + { 0x0000b18c , 0x07410742 }, + + { 0x0000b190 , 0x075f0740 }, + + { 0x0000b194 , 0x077f0760 }, + + { 0x0000b198 , 0x07800781 }, + + { 0x0000b19c , 0x07a0079f }, + + { 0x0000b1a0 , 0x07c107bf }, + + { 0x0000b1a4 , 0x000007c0 }, + + { 0x0000b1a8 , 0x00000000 }, + + { 0x0000b1ac , 0x00000000 }, + + { 0x0000b1b0 , 0x00000000 }, + + { 0x0000b1b4 , 0x00000000 }, + + { 0x0000b1b8 , 0x00000000 }, + + { 0x0000b1bc , 0x00000000 }, + + { 0x0000b1c0 , 0x00000000 }, + + { 0x0000b1c4 , 0x00000000 }, + + { 0x0000b1c8 , 0x00000000 }, + + { 0x0000b1cc , 0x00000000 }, + + { 0x0000b1d0 , 0x00000000 }, + + { 0x0000b1d4 , 0x00000000 }, + + { 0x0000b1d8 , 0x00000000 }, + + { 0x0000b1dc , 0x00000000 }, + + { 0x0000b1e0 , 0x00000000 }, + + { 0x0000b1e4 , 0x00000000 }, + + { 0x0000b1e8 , 0x00000000 }, + + { 0x0000b1ec , 0x00000000 }, + + { 0x0000b1f0 , 0x00000396 }, + + { 0x0000b1f4 , 0x00000396 }, + + { 0x0000b1f8 , 0x00000396 }, + + { 0x0000b1fc , 0x00000196 }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_tx_gain_table_baseband_postamble_emulation[][5] = { + +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + + { 0x0000a410 , 0x000000d5 , 0x000000d5 , 0x000000d5 , 0x000000d5 }, + + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + + { 0x0000a504 , 0x00004002 , 0x00004002 , 0x00004002 , 0x00004002 }, + + { 0x0000a508 , 0x00008004 , 0x00008004 , 0x00008004 , 0x00008004 }, + + { 0x0000a510 , 0x0001000c , 0x0001000c , 0x0001000c , 0x0001000c }, + + { 0x0000a514 , 0x0001420b , 0x0001420b , 0x0001420b , 0x0001420b }, + + { 0x0000a518 , 0x0001824a , 0x0001824a , 0x0001824a , 0x0001824a }, + + { 0x0000a51c , 0x0001c44a , 0x0001c44a , 0x0001c44a , 0x0001c44a }, + + { 0x0000a520 , 0x0002064a , 0x0002064a , 0x0002064a , 0x0002064a }, + + { 0x0000a524 , 0x0002484a , 0x0002484a , 0x0002484a , 0x0002484a }, + + { 0x0000a528 , 0x00028a4a , 0x00028a4a , 0x00028a4a , 0x00028a4a }, + + { 0x0000a52c , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a }, + + { 0x0000a530 , 0x00030e4a , 0x00030e4a , 0x00030e4a , 0x00030e4a }, + + { 0x0000a534 , 0x00034e8a , 0x00034e8a , 0x00034e8a , 0x00034e8a }, + +}; + + + +static const u_int32_t ar9340_wasp_1p0_soc_preamble[][2] = { + +/* Addr allmodes */ + + { 0x00007008 , 0x00000000 }, + + { 0x00007020 , 0x00000000 }, + + { 0x00007034 , 0x00000002 }, + + { 0x00007038 , 0x000004c2 }, + +}; + + + + + diff --git a/hal/ar9300/ar9485.ini b/hal/ar9300/ar9485.ini new file mode 100644 index 000000000000..45ef37a0da0d --- /dev/null +++ b/hal/ar9300/ar9485.ini @@ -0,0 +1,1419 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +static const u_int32_t ar9485Common_poseidon1_0[][2] = { +/* Addr allmodes */ + { 0x00007010 , 0x00000022 }, + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000004c2 }, +}; + +static const u_int32_t ar9485_poseidon1_0_mac_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, +}; + +static const u_int32_t ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x10212e5e }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0000580c }, +}; + +static const u_int32_t ar9485Common_wo_xlna_rx_gain_poseidon1_0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00060005 }, + { 0x0000a004 , 0x00810080 }, + { 0x0000a008 , 0x00830082 }, + { 0x0000a00c , 0x00850084 }, + { 0x0000a010 , 0x01820181 }, + { 0x0000a014 , 0x01840183 }, + { 0x0000a018 , 0x01880185 }, + { 0x0000a01c , 0x018a0189 }, + { 0x0000a020 , 0x02850284 }, + { 0x0000a024 , 0x02890288 }, + { 0x0000a028 , 0x028b028a }, + { 0x0000a02c , 0x03850384 }, + { 0x0000a030 , 0x03890388 }, + { 0x0000a034 , 0x038b038a }, + { 0x0000a038 , 0x038d038c }, + { 0x0000a03c , 0x03910390 }, + { 0x0000a040 , 0x03930392 }, + { 0x0000a044 , 0x03950394 }, + { 0x0000a048 , 0x00000396 }, + { 0x0000a04c , 0x00000000 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x28282828 }, + { 0x0000a084 , 0x28282828 }, + { 0x0000a088 , 0x28282828 }, + { 0x0000a08c , 0x28282828 }, + { 0x0000a090 , 0x28282828 }, + { 0x0000a094 , 0x24242428 }, + { 0x0000a098 , 0x171e1e1e }, + { 0x0000a09c , 0x02020b0b }, + { 0x0000a0a0 , 0x02020202 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x22072208 }, + { 0x0000a0c4 , 0x22052206 }, + { 0x0000a0c8 , 0x22032204 }, + { 0x0000a0cc , 0x22012202 }, + { 0x0000a0d0 , 0x221f2200 }, + { 0x0000a0d4 , 0x221d221e }, + { 0x0000a0d8 , 0x33023303 }, + { 0x0000a0dc , 0x33003301 }, + { 0x0000a0e0 , 0x331e331f }, + { 0x0000a0e4 , 0x4402331d }, + { 0x0000a0e8 , 0x44004401 }, + { 0x0000a0ec , 0x441e441f }, + { 0x0000a0f0 , 0x55025503 }, + { 0x0000a0f4 , 0x55005501 }, + { 0x0000a0f8 , 0x551e551f }, + { 0x0000a0fc , 0x6602551d }, + { 0x0000a100 , 0x66006601 }, + { 0x0000a104 , 0x661e661f }, + { 0x0000a108 , 0x7703661d }, + { 0x0000a10c , 0x77017702 }, + { 0x0000a110 , 0x00007700 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x111f1100 }, + { 0x0000a148 , 0x111d111e }, + { 0x0000a14c , 0x111b111c }, + { 0x0000a150 , 0x22032204 }, + { 0x0000a154 , 0x22012202 }, + { 0x0000a158 , 0x221f2200 }, + { 0x0000a15c , 0x221d221e }, + { 0x0000a160 , 0x33013302 }, + { 0x0000a164 , 0x331f3300 }, + { 0x0000a168 , 0x4402331e }, + { 0x0000a16c , 0x44004401 }, + { 0x0000a170 , 0x441e441f }, + { 0x0000a174 , 0x55015502 }, + { 0x0000a178 , 0x551f5500 }, + { 0x0000a17c , 0x6602551e }, + { 0x0000a180 , 0x66006601 }, + { 0x0000a184 , 0x661e661f }, + { 0x0000a188 , 0x7703661d }, + { 0x0000a18c , 0x77017702 }, + { 0x0000a190 , 0x00007700 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000296 }, +}; + +static const u_int32_t ar9485Modes_high_power_tx_gain_poseidon1_0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000002 , 0x00000002 , 0x00000002 , 0x00000002 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d8 , 0x000050d8 }, + { 0x0000a458 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x21000603 , 0x21000603 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x25000605 , 0x25000605 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2a000a03 , 0x2a000a03 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2c000a04 , 0x2c000a04 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x34000e20 , 0x34000e20 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x35000e21 , 0x35000e21 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x43000e62 , 0x43000e62 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x45000e63 , 0x45000e63 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x49000e65 , 0x49000e65 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4b000e66 , 0x4b000e66 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4d001645 , 0x4d001645 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x51001865 , 0x51001865 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x55001a86 , 0x55001a86 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x57001ce9 , 0x57001ce9 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000b500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b504 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b508 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b50c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b510 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b514 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b518 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b51c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b520 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b524 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b528 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b52c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b530 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b534 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b538 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b53c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b540 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b544 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b548 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b54c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b550 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b554 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b558 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b55c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b560 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b564 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b568 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b56c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b570 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b574 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b578 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b57c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00016044 , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db }, + { 0x00016048 , 0x6c924260 , 0x6c924260 , 0x6c924260 , 0x6c924260 }, +}; + +static const u_int32_t ar9485_poseidon1_0[][2] = { +/* Addr allmodes */ + { 0x0000a580 , 0x00000000 }, + { 0x0000a584 , 0x00000000 }, + { 0x0000a588 , 0x00000000 }, + { 0x0000a58c , 0x00000000 }, + { 0x0000a590 , 0x00000000 }, + { 0x0000a594 , 0x00000000 }, + { 0x0000a598 , 0x00000000 }, + { 0x0000a59c , 0x00000000 }, + { 0x0000a5a0 , 0x00000000 }, + { 0x0000a5a4 , 0x00000000 }, + { 0x0000a5a8 , 0x00000000 }, + { 0x0000a5ac , 0x00000000 }, + { 0x0000a5b0 , 0x00000000 }, + { 0x0000a5b4 , 0x00000000 }, + { 0x0000a5b8 , 0x00000000 }, + { 0x0000a5bc , 0x00000000 }, +}; + +static const u_int32_t ar9485_poseidon1_0_mac_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00000030 , 0x00020085 }, + { 0x00000044 , 0x00000008 }, + { 0x0000805c , 0xffffc7ff }, + { 0x00008344 , 0xaa4a105b }, +}; + +static const u_int32_t ar9485_poseidon1_0_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e3c , 0xcf946221 , 0xcf946221 , 0xcf946221 , 0xcf946221 }, + { 0x00009e44 , 0x005c0000 , 0x005c0000 , 0x005c0000 , 0x005c0000 }, + { 0x0000a2d8 , 0x7999a800 , 0x7999a800 , 0x7999a80c , 0x7999a80c }, +}; + +static const u_int32_t ar9485_poseidon1_0_radio_core[][2] = { +/* Addr allmodes */ + { 0x00016000 , 0x36db6db6 }, + { 0x00016004 , 0x6db6db40 }, + { 0x00016008 , 0x73800000 }, + { 0x0001600c , 0x00000000 }, + { 0x00016040 , 0x7f80fff8 }, + { 0x0001604c , 0x000f0278 }, + { 0x00016050 , 0x4db6db8c }, + { 0x00016054 , 0x6db60000 }, + { 0x00016080 , 0x00080000 }, + { 0x00016084 , 0x0e48048c }, + { 0x00016088 , 0x14214514 }, + { 0x0001608c , 0x119f081e }, + { 0x00016090 , 0x24926490 }, + { 0x00016098 , 0xd28b3330 }, + { 0x000160a0 , 0xc2108ffe }, + { 0x000160a4 , 0x812fc370 }, + { 0x000160a8 , 0x423c8000 }, + { 0x000160b4 , 0x92480040 }, + { 0x000160c0 , 0x006db6db }, + { 0x000160c4 , 0x0186db60 }, + { 0x000160c8 , 0x6db6db6c }, + { 0x000160cc , 0x6de6fbe0 }, + { 0x000160d0 , 0xf7dfcf3c }, + { 0x00016100 , 0x04cb0001 }, + { 0x00016104 , 0xfff80015 }, + { 0x00016108 , 0x00080010 }, + { 0x00016144 , 0x01884080 }, + { 0x00016148 , 0x00008040 }, + { 0x00016240 , 0x08400000 }, + { 0x00016244 , 0x1bf90f00 }, + { 0x00016248 , 0x00000000 }, + { 0x0001624c , 0x00000000 }, + { 0x00016280 , 0x01000015 }, + { 0x00016284 , 0x00d30000 }, + { 0x00016288 , 0x00318000 }, + { 0x0001628c , 0x50000000 }, + { 0x00016290 , 0x4b96210f }, + { 0x00016380 , 0x00000000 }, + { 0x00016384 , 0x00000000 }, + { 0x00016388 , 0x00800700 }, + { 0x0001638c , 0x00800700 }, + { 0x00016390 , 0x00800700 }, + { 0x00016394 , 0x00000000 }, + { 0x00016398 , 0x00000000 }, + { 0x0001639c , 0x00000000 }, + { 0x000163a0 , 0x00000001 }, + { 0x000163a4 , 0x00000001 }, + { 0x000163a8 , 0x00000000 }, + { 0x000163ac , 0x00000000 }, + { 0x000163b0 , 0x00000000 }, + { 0x000163b4 , 0x00000000 }, + { 0x000163b8 , 0x00000000 }, + { 0x000163bc , 0x00000000 }, + { 0x000163c0 , 0x000000a0 }, + { 0x000163c4 , 0x000c0000 }, + { 0x000163c8 , 0x14021402 }, + { 0x000163cc , 0x00001402 }, + { 0x000163d0 , 0x00000000 }, + { 0x000163d4 , 0x00000000 }, + { 0x00016c40 , 0x13188278 }, + { 0x00016c44 , 0x12000000 }, +}; + +static const u_int32_t ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000002 , 0x00000002 , 0x00000002 , 0x00000002 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d8 , 0x000050d8 }, + { 0x0000a458 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x21000603 , 0x21000603 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x25000605 , 0x25000605 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2a000a03 , 0x2a000a03 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2c000a04 , 0x2c000a04 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x34000e20 , 0x34000e20 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x35000e21 , 0x35000e21 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x43000e62 , 0x43000e62 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x45000e63 , 0x45000e63 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x49000e65 , 0x49000e65 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4b000e66 , 0x4b000e66 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4d001645 , 0x4d001645 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x51001865 , 0x51001865 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x55001a86 , 0x55001a86 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x57001ce9 , 0x57001ce9 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000b500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b504 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b508 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b50c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b510 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b514 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b518 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b51c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b520 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b524 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b528 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b52c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b530 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b534 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b538 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b53c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b540 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b544 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b548 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b54c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b550 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b554 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b558 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b55c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b560 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b564 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b568 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b56c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b570 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b574 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b578 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b57c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00016044 , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db }, + { 0x00016048 , 0x6c924260 , 0x6c924260 , 0x6c924260 , 0x6c924260 }, +}; + +static const u_int32_t ar9485_130nm_radio_emulation[][2] = { +/* Addr common */ + { 0x00007800 , 0x00040000 }, + { 0x00007804 , 0xdb005012 }, + { 0x00007808 , 0x04924914 }, + { 0x0000780c , 0x21084210 }, + { 0x00007810 , 0x6d801300 }, + { 0x00007814 , 0x0019beff }, + { 0x00007818 , 0x07e41000 }, + { 0x0000781c , 0x00392000 }, + { 0x00007820 , 0x92592480 }, + { 0x00007824 , 0x00040000 }, + { 0x00007828 , 0xdb005012 }, + { 0x0000782c , 0x04924914 }, + { 0x00007830 , 0x21084210 }, + { 0x00007834 , 0x6d801300 }, + { 0x00007838 , 0x0019beff }, + { 0x0000783c , 0x07e40000 }, + { 0x00007840 , 0x00392000 }, + { 0x00007844 , 0x92592480 }, + { 0x00007848 , 0x00100000 }, + { 0x0000784c , 0x773f0567 }, + { 0x00007850 , 0x54214514 }, + { 0x00007854 , 0x12035828 }, + { 0x00007858 , 0x92592692 }, + { 0x0000785c , 0x00000000 }, + { 0x00007860 , 0x52802000 }, + { 0x00007864 , 0x0a8e370e }, + { 0x00007868 , 0xc0102850 }, + { 0x0000786c , 0x812d4000 }, + { 0x00007870 , 0x807ec400 }, + { 0x00007874 , 0x001b6db0 }, + { 0x00007878 , 0x00376b63 }, + { 0x0000787c , 0x06db6db6 }, + { 0x00007880 , 0x006d8000 }, + { 0x00007884 , 0xffeffffe }, + { 0x00007888 , 0xffeffffe }, + { 0x0000788c , 0x00010000 }, + { 0x00007890 , 0x02060aeb }, + { 0x00007894 , 0x5a108000 }, +}; + +static const u_int32_t ar9485_poseidon1_0_baseband_core[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009804 , 0xfd14e000 }, + { 0x00009808 , 0x9c0a8f6b }, + { 0x0000980c , 0x04800000 }, + { 0x00009814 , 0x9280c00a }, + { 0x00009818 , 0x00000000 }, + { 0x0000981c , 0x00020028 }, + { 0x00009834 , 0x5f3ca3de }, + { 0x00009838 , 0x0108ecff }, + { 0x0000983c , 0x14750600 }, + { 0x00009880 , 0x201fff00 }, + { 0x00009884 , 0x00001042 }, + { 0x000098a4 , 0x00200400 }, + { 0x000098b0 , 0x52440bbe }, + { 0x000098d0 , 0x004b6a8e }, + { 0x000098d4 , 0x00000820 }, + { 0x000098dc , 0x00000000 }, + { 0x000098f0 , 0x00000000 }, + { 0x000098f4 , 0x00000000 }, + { 0x00009c04 , 0x00000000 }, + { 0x00009c08 , 0x03200000 }, + { 0x00009c0c , 0x00000000 }, + { 0x00009c10 , 0x00000000 }, + { 0x00009c14 , 0x00046384 }, + { 0x00009c18 , 0x05b6b440 }, + { 0x00009c1c , 0x00b6b440 }, + { 0x00009d00 , 0xc080a333 }, + { 0x00009d04 , 0x40206c10 }, + { 0x00009d08 , 0x009c4060 }, + { 0x00009d0c , 0x1883800a }, + { 0x00009d10 , 0x01834061 }, + { 0x00009d14 , 0x00c00400 }, + { 0x00009d18 , 0x00000000 }, + { 0x00009d1c , 0x00000000 }, + { 0x00009e08 , 0x0038233c }, + { 0x00009e24 , 0x9927b515 }, + { 0x00009e28 , 0x12ef0200 }, + { 0x00009e30 , 0x06336f77 }, + { 0x00009e34 , 0x6af6532f }, + { 0x00009e38 , 0x0cc80c00 }, + { 0x00009e40 , 0x0d261820 }, + { 0x00009e4c , 0x00001004 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009fc0 , 0x80be4788 }, + { 0x00009fc4 , 0x0001efb5 }, + { 0x00009fcc , 0x40000014 }, + { 0x0000a20c , 0x00000000 }, + { 0x0000a210 , 0x00000000 }, + { 0x0000a220 , 0x00000000 }, + { 0x0000a224 , 0x00000000 }, + { 0x0000a228 , 0x10002310 }, + { 0x0000a23c , 0x00000000 }, + { 0x0000a244 , 0x0c000000 }, + { 0x0000a2a0 , 0x00000001 }, + { 0x0000a2c0 , 0x00000001 }, + { 0x0000a2c8 , 0x00000000 }, + { 0x0000a2cc , 0x18c43433 }, + { 0x0000a2d4 , 0x00000000 }, + { 0x0000a2dc , 0x00000000 }, + { 0x0000a2e0 , 0x00000000 }, + { 0x0000a2e4 , 0x00000000 }, + { 0x0000a2e8 , 0x00000000 }, + { 0x0000a2ec , 0x00000000 }, + { 0x0000a2f0 , 0x00000000 }, + { 0x0000a2f4 , 0x00000000 }, + { 0x0000a2f8 , 0x00000000 }, + { 0x0000a344 , 0x00000000 }, + { 0x0000a34c , 0x00000000 }, + { 0x0000a350 , 0x0000a000 }, + { 0x0000a364 , 0x00000000 }, + { 0x0000a370 , 0x00000000 }, + { 0x0000a390 , 0x00000001 }, + { 0x0000a394 , 0x00000444 }, + { 0x0000a398 , 0x001f0e0f }, + { 0x0000a39c , 0x0075393f }, + { 0x0000a3a0 , 0xb79f6427 }, + { 0x0000a3a4 , 0x000000ff }, + { 0x0000a3a8 , 0x3b3b3b3b }, + { 0x0000a3ac , 0x2f2f2f2f }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a3c8 , 0x20200020 }, + { 0x0000a3cc , 0x20202020 }, + { 0x0000a3d0 , 0x20202020 }, + { 0x0000a3d4 , 0x20202020 }, + { 0x0000a3d8 , 0x20202020 }, + { 0x0000a3dc , 0x20202020 }, + { 0x0000a3e0 , 0x20202020 }, + { 0x0000a3e4 , 0x20202020 }, + { 0x0000a3e8 , 0x20202020 }, + { 0x0000a3ec , 0x20202020 }, + { 0x0000a3f0 , 0x00000000 }, + { 0x0000a3f4 , 0x00000006 }, + { 0x0000a3f8 , 0x0cdbd380 }, + { 0x0000a3fc , 0x000f0f01 }, + { 0x0000a400 , 0x8fa91f01 }, + { 0x0000a404 , 0x00000000 }, + { 0x0000a408 , 0x0e79e5c6 }, + { 0x0000a40c , 0x00820820 }, + { 0x0000a414 , 0x1ce739cf }, + { 0x0000a418 , 0x2d0019ce }, + { 0x0000a41c , 0x1ce739ce }, + { 0x0000a420 , 0x000001ce }, + { 0x0000a424 , 0x1ce739ce }, + { 0x0000a428 , 0x000001ce }, + { 0x0000a42c , 0x1ce739ce }, + { 0x0000a430 , 0x1ce739ce }, + { 0x0000a434 , 0x00000000 }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a43c , 0x00000000 }, + { 0x0000a440 , 0x00000000 }, + { 0x0000a444 , 0x00000000 }, + { 0x0000a448 , 0x04000000 }, + { 0x0000a44c , 0x00000001 }, + { 0x0000a450 , 0x00010000 }, + { 0x0000a5c4 , 0xbfad9d74 }, + { 0x0000a5c8 , 0x0048060a }, + { 0x0000a5cc , 0x00000637 }, + { 0x0000a760 , 0x03020100 }, + { 0x0000a764 , 0x09080504 }, + { 0x0000a768 , 0x0d0c0b0a }, + { 0x0000a76c , 0x13121110 }, + { 0x0000a770 , 0x31301514 }, + { 0x0000a774 , 0x35343332 }, + { 0x0000a778 , 0x00000036 }, + { 0x0000a780 , 0x00000838 }, + { 0x0000a7c0 , 0x00000000 }, + { 0x0000a7c4 , 0xfffffffc }, + { 0x0000a7c8 , 0x00000000 }, + { 0x0000a7cc , 0x00000000 }, + { 0x0000a7d0 , 0x00000000 }, + { 0x0000a7d4 , 0x00000004 }, + { 0x0000a7dc , 0x00000000 }, +}; + +static const u_int32_t ar9485_modes_green_ob_db_tx_gain_poseidon1_0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000003 , 0x00000003 , 0x00000003 , 0x00000003 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d8 , 0x000050d8 }, + { 0x0000a458 , 0x80000000 , 0x80000000 , 0x80000000 , 0x80000000 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000006 , 0x00000006 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x03000201 , 0x03000201 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x06000203 , 0x06000203 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0a000401 , 0x0a000401 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x0e000403 , 0x0e000403 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x12000405 , 0x12000405 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x15000604 , 0x15000604 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x18000605 , 0x18000605 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x1c000a04 , 0x1c000a04 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x21000a06 , 0x21000a06 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x29000a24 , 0x29000a24 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2f000e21 , 0x2f000e21 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x33000e21 , 0x33000e21 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x39000e23 , 0x39000e23 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x43000e62 , 0x43000e62 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x45000e63 , 0x45000e63 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x49000e65 , 0x49000e65 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4b000e66 , 0x4b000e66 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4d001645 , 0x4d001645 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x51001865 , 0x51001865 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x55001a86 , 0x55001a86 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x57001ce9 , 0x57001ce9 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000b500 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b504 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b508 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b50c , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b510 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b514 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b518 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b51c , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b520 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b524 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b528 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b52c , 0x0000002a , 0x0000002a , 0x0000002a , 0x0000002a }, + { 0x0000b530 , 0x0000003a , 0x0000003a , 0x0000003a , 0x0000003a }, + { 0x0000b534 , 0x0000004a , 0x0000004a , 0x0000004a , 0x0000004a }, + { 0x0000b538 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b53c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b540 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b544 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b548 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b54c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b550 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b554 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b558 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b55c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b560 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b564 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b568 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b56c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b570 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b574 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b578 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b57c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x00016044 , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db }, + { 0x00016048 , 0x6c924260 , 0x6c924260 , 0x6c924260 , 0x6c924260 }, +}; + +static const u_int32_t ar9485Modes_high_ob_db_tx_gain_poseidon1_0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000002 , 0x00000002 , 0x00000002 , 0x00000002 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d8 , 0x000050d8 }, + { 0x0000a458 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x21000603 , 0x21000603 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x25000605 , 0x25000605 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2a000a03 , 0x2a000a03 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2c000a04 , 0x2c000a04 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x34000e20 , 0x34000e20 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x35000e21 , 0x35000e21 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x43000e62 , 0x43000e62 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x45000e63 , 0x45000e63 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x49000e65 , 0x49000e65 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4b000e66 , 0x4b000e66 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4d001645 , 0x4d001645 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x51001865 , 0x51001865 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x55001a86 , 0x55001a86 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x57001ce9 , 0x57001ce9 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000b500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b504 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b508 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b50c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b510 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b514 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b518 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b51c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b520 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b524 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b528 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b52c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b530 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b534 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b538 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b53c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b540 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b544 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b548 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b54c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b550 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b554 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b558 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b55c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b560 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b564 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b568 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b56c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b570 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b574 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b578 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b57c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00016044 , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db }, + { 0x00016048 , 0x6c924260 , 0x6c924260 , 0x6c924260 , 0x6c924260 }, +}; + +static const u_int32_t ar9485Common_rx_gain_poseidon1_0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x01800082 }, + { 0x0000a014 , 0x01820181 }, + { 0x0000a018 , 0x01840183 }, + { 0x0000a01c , 0x01880185 }, + { 0x0000a020 , 0x018a0189 }, + { 0x0000a024 , 0x02850284 }, + { 0x0000a028 , 0x02890288 }, + { 0x0000a02c , 0x03850384 }, + { 0x0000a030 , 0x03890388 }, + { 0x0000a034 , 0x038b038a }, + { 0x0000a038 , 0x038d038c }, + { 0x0000a03c , 0x03910390 }, + { 0x0000a040 , 0x03930392 }, + { 0x0000a044 , 0x03950394 }, + { 0x0000a048 , 0x00000396 }, + { 0x0000a04c , 0x00000000 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x28282828 }, + { 0x0000a084 , 0x28282828 }, + { 0x0000a088 , 0x28282828 }, + { 0x0000a08c , 0x28282828 }, + { 0x0000a090 , 0x28282828 }, + { 0x0000a094 , 0x21212128 }, + { 0x0000a098 , 0x171c1c1c }, + { 0x0000a09c , 0x02020212 }, + { 0x0000a0a0 , 0x00000202 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x111f1100 }, + { 0x0000a0c8 , 0x111d111e }, + { 0x0000a0cc , 0x111b111c }, + { 0x0000a0d0 , 0x22032204 }, + { 0x0000a0d4 , 0x22012202 }, + { 0x0000a0d8 , 0x221f2200 }, + { 0x0000a0dc , 0x221d221e }, + { 0x0000a0e0 , 0x33013302 }, + { 0x0000a0e4 , 0x331f3300 }, + { 0x0000a0e8 , 0x4402331e }, + { 0x0000a0ec , 0x44004401 }, + { 0x0000a0f0 , 0x441e441f }, + { 0x0000a0f4 , 0x55015502 }, + { 0x0000a0f8 , 0x551f5500 }, + { 0x0000a0fc , 0x6602551e }, + { 0x0000a100 , 0x66006601 }, + { 0x0000a104 , 0x661e661f }, + { 0x0000a108 , 0x7703661d }, + { 0x0000a10c , 0x77017702 }, + { 0x0000a110 , 0x00007700 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x111f1100 }, + { 0x0000a148 , 0x111d111e }, + { 0x0000a14c , 0x111b111c }, + { 0x0000a150 , 0x22032204 }, + { 0x0000a154 , 0x22012202 }, + { 0x0000a158 , 0x221f2200 }, + { 0x0000a15c , 0x221d221e }, + { 0x0000a160 , 0x33013302 }, + { 0x0000a164 , 0x331f3300 }, + { 0x0000a168 , 0x4402331e }, + { 0x0000a16c , 0x44004401 }, + { 0x0000a170 , 0x441e441f }, + { 0x0000a174 , 0x55015502 }, + { 0x0000a178 , 0x551f5500 }, + { 0x0000a17c , 0x6602551e }, + { 0x0000a180 , 0x66006601 }, + { 0x0000a184 , 0x661e661f }, + { 0x0000a188 , 0x7703661d }, + { 0x0000a18c , 0x77017702 }, + { 0x0000a190 , 0x00007700 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000296 }, +}; + +static const u_int32_t ar9485Common_rx_gain_poseidon1_0_emulation[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x02000101 }, + { 0x0000a004 , 0x02000102 }, + { 0x0000a008 , 0x02000103 }, + { 0x0000a00c , 0x02000104 }, + { 0x0000a010 , 0x02000200 }, + { 0x0000a014 , 0x02000201 }, + { 0x0000a018 , 0x02000202 }, + { 0x0000a01c , 0x02000203 }, + { 0x0000a020 , 0x02000204 }, + { 0x0000a024 , 0x02000205 }, + { 0x0000a028 , 0x02000208 }, + { 0x0000a02c , 0x02000302 }, + { 0x0000a030 , 0x02000303 }, + { 0x0000a034 , 0x02000304 }, + { 0x0000a038 , 0x02000400 }, + { 0x0000a03c , 0x02010300 }, + { 0x0000a040 , 0x02010301 }, + { 0x0000a044 , 0x02010302 }, + { 0x0000a048 , 0x02000500 }, + { 0x0000a04c , 0x02010400 }, + { 0x0000a050 , 0x02020300 }, + { 0x0000a054 , 0x02020301 }, + { 0x0000a058 , 0x02020302 }, + { 0x0000a05c , 0x02020303 }, + { 0x0000a060 , 0x02020400 }, + { 0x0000a064 , 0x02030300 }, + { 0x0000a068 , 0x02030301 }, + { 0x0000a06c , 0x02030302 }, + { 0x0000a070 , 0x02030303 }, + { 0x0000a074 , 0x02030400 }, + { 0x0000a078 , 0x02040300 }, + { 0x0000a07c , 0x02040301 }, + { 0x0000a080 , 0x02040302 }, + { 0x0000a084 , 0x02040303 }, + { 0x0000a088 , 0x02030500 }, + { 0x0000a08c , 0x02040400 }, + { 0x0000a090 , 0x02050203 }, + { 0x0000a094 , 0x02050204 }, + { 0x0000a098 , 0x02050205 }, + { 0x0000a09c , 0x02040500 }, + { 0x0000a0a0 , 0x02050301 }, + { 0x0000a0a4 , 0x02050302 }, + { 0x0000a0a8 , 0x02050303 }, + { 0x0000a0ac , 0x02050400 }, + { 0x0000a0b0 , 0x02050401 }, + { 0x0000a0b4 , 0x02050402 }, + { 0x0000a0b8 , 0x02050403 }, + { 0x0000a0bc , 0x02050500 }, + { 0x0000a0c0 , 0x02050501 }, + { 0x0000a0c4 , 0x02050502 }, + { 0x0000a0c8 , 0x02050503 }, + { 0x0000a0cc , 0x02050504 }, + { 0x0000a0d0 , 0x02050600 }, + { 0x0000a0d4 , 0x02050601 }, + { 0x0000a0d8 , 0x02050602 }, + { 0x0000a0dc , 0x02050603 }, + { 0x0000a0e0 , 0x02050604 }, + { 0x0000a0e4 , 0x02050700 }, + { 0x0000a0e8 , 0x02050701 }, + { 0x0000a0ec , 0x02050702 }, + { 0x0000a0f0 , 0x02050703 }, + { 0x0000a0f4 , 0x02050704 }, + { 0x0000a0f8 , 0x02050705 }, + { 0x0000a0fc , 0x02050708 }, + { 0x0000a100 , 0x02050709 }, + { 0x0000a104 , 0x0205070a }, + { 0x0000a108 , 0x0205070b }, + { 0x0000a10c , 0x0205070c }, + { 0x0000a110 , 0x0205070d }, + { 0x0000a114 , 0x02050710 }, + { 0x0000a118 , 0x02050711 }, + { 0x0000a11c , 0x02050712 }, + { 0x0000a120 , 0x02050713 }, + { 0x0000a124 , 0x02050714 }, + { 0x0000a128 , 0x02050715 }, + { 0x0000a12c , 0x02050730 }, + { 0x0000a130 , 0x02050731 }, + { 0x0000a134 , 0x02050732 }, + { 0x0000a138 , 0x02050733 }, + { 0x0000a13c , 0x02050734 }, + { 0x0000a140 , 0x02050735 }, + { 0x0000a144 , 0x02050750 }, + { 0x0000a148 , 0x02050751 }, + { 0x0000a14c , 0x02050752 }, + { 0x0000a150 , 0x02050753 }, + { 0x0000a154 , 0x02050754 }, + { 0x0000a158 , 0x02050755 }, + { 0x0000a15c , 0x02050770 }, + { 0x0000a160 , 0x02050771 }, + { 0x0000a164 , 0x02050772 }, + { 0x0000a168 , 0x02050773 }, + { 0x0000a16c , 0x02050774 }, + { 0x0000a170 , 0x02050775 }, + { 0x0000a174 , 0x00000776 }, + { 0x0000a178 , 0x00000776 }, + { 0x0000a17c , 0x00000776 }, + { 0x0000a180 , 0x00000776 }, + { 0x0000a184 , 0x00000776 }, + { 0x0000a188 , 0x00000776 }, + { 0x0000a18c , 0x00000776 }, + { 0x0000a190 , 0x00000776 }, + { 0x0000a194 , 0x00000776 }, + { 0x0000a198 , 0x00000776 }, + { 0x0000a19c , 0x00000776 }, + { 0x0000a1a0 , 0x00000776 }, + { 0x0000a1a4 , 0x00000776 }, + { 0x0000a1a8 , 0x00000776 }, + { 0x0000a1ac , 0x00000776 }, + { 0x0000a1b0 , 0x00000776 }, + { 0x0000a1b4 , 0x00000776 }, + { 0x0000a1b8 , 0x00000776 }, + { 0x0000a1bc , 0x00000776 }, + { 0x0000a1c0 , 0x00000776 }, + { 0x0000a1c4 , 0x00000776 }, + { 0x0000a1c8 , 0x00000776 }, + { 0x0000a1cc , 0x00000776 }, + { 0x0000a1d0 , 0x00000776 }, + { 0x0000a1d4 , 0x00000776 }, + { 0x0000a1d8 , 0x00000776 }, + { 0x0000a1dc , 0x00000776 }, + { 0x0000a1e0 , 0x00000776 }, + { 0x0000a1e4 , 0x00000776 }, + { 0x0000a1e8 , 0x00000776 }, + { 0x0000a1ec , 0x00000776 }, + { 0x0000a1f0 , 0x00000776 }, + { 0x0000a1f4 , 0x00000776 }, + { 0x0000a1f8 , 0x00000776 }, + { 0x0000a1fc , 0x00000776 }, +}; + +static const u_int32_t ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x10253e5e }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0000580c }, +}; + +static const u_int32_t ar9485_fast_clock_poseidon1_0_baseband_postamble[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00009e00 , 0x03721821 , 0x03721821 }, + { 0x0000a230 , 0x0000400b , 0x00004016 }, + { 0x0000a254 , 0x00000898 , 0x00001130 }, +}; + +static const u_int32_t ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484[][2] = { +/* Addr allmodes */ + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x6f7f0301 }, + { 0x0000a3a0 , 0xca9228ee }, +}; + +static const u_int32_t ar9485_poseidon1_0_soc_preamble[][2] = { +/* Addr allmodes */ + { 0x00004014 , 0xba280400 }, + { 0x00004090 , 0x00aa10aa }, + { 0x000040a4 , 0x00a0c9c9 }, + { 0x00007010 , 0x00000022 }, + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000004c2 }, + { 0x00007048 , 0x00000002 }, +}; + +static const u_int32_t ar9485_poseidon1_0_baseband_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 }, + { 0x00009820 , 0x206a002e , 0x206a002e , 0x206a002e , 0x206a002e }, + { 0x00009824 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 }, + { 0x00009828 , 0x06903081 , 0x06903081 , 0x06903881 , 0x06903881 }, + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000059c , 0x0000059c }, + { 0x00009c00 , 0x00000044 , 0x00000044 , 0x00000044 , 0x00000044 }, + { 0x00009e00 , 0x0372161e , 0x0372161e , 0x037216a0 , 0x037216a0 }, + { 0x00009e04 , 0x00182020 , 0x00182020 , 0x00182020 , 0x00182020 }, + { 0x00009e0c , 0x6c4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + { 0x00009e10 , 0x7ec88d2e , 0x7ec88d2e , 0x7ec80d2e , 0x7ec80d2e }, + { 0x00009e14 , 0x31395d5e , 0x3139605e , 0x3139605e , 0x31395d5e }, + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + { 0x00009e2c , 0x0000001c , 0x0000001c , 0x00000021 , 0x00000021 }, + { 0x00009e3c , 0xcf946220 , 0xcf946220 , 0xcf946222 , 0xcf946222 }, + { 0x00009e44 , 0x02321e27 , 0x02321e27 , 0x02282324 , 0x02282324 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302010 , 0x50302010 }, + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, + { 0x0000a204 , 0x01303fc0 , 0x01303fc4 , 0x01303fc4 , 0x01303fc0 }, + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + { 0x0000a230 , 0x0000400a , 0x00004014 , 0x00004016 , 0x0000400b }, + { 0x0000a234 , 0x10000fff , 0x10000fff , 0x10000fff , 0x10000fff }, + { 0x0000a238 , 0xffb81018 , 0xffb81018 , 0xffb81018 , 0xffb81018 }, + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a260 , 0x3a021501 , 0x3a021501 , 0x3a021501 , 0x3a021501 }, + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x000002a0 , 0x000002a0 }, + { 0x0000a288 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a28c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2d0 , 0x00071981 , 0x00071981 , 0x00071982 , 0x00071982 }, + { 0x0000a2d8 , 0xf999a83a , 0xf999a83a , 0xf999a83a , 0xf999a83a }, + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000be04 , 0x00802020 , 0x00802020 , 0x00802020 , 0x00802020 }, + { 0x0000be18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +}; + +static const u_int32_t ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x10252e5e }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0000580c }, +}; + +static const u_int32_t ar9485_poseidon1_0_mac_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 }, + { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 }, +}; + +static const u_int32_t ar9485_poseidon1_0_baseband_core_emulation[][2] = { +/* Addr allmodes */ + { 0x0000a344 , 0x00000010 }, +}; + +static const u_int32_t ar9485Modes_low_ob_db_tx_gain_poseidon1_0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000002 , 0x00000002 , 0x00000002 , 0x00000002 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d8 , 0x000050d8 }, + { 0x0000a458 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x21000603 , 0x21000603 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x25000605 , 0x25000605 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2a000a03 , 0x2a000a03 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2c000a04 , 0x2c000a04 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x34000e20 , 0x34000e20 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x35000e21 , 0x35000e21 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x43000e62 , 0x43000e62 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x45000e63 , 0x45000e63 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x49000e65 , 0x49000e65 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4b000e66 , 0x4b000e66 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4d001645 , 0x4d001645 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x51001865 , 0x51001865 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x55001a86 , 0x55001a86 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x57001ce9 , 0x57001ce9 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000b500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b504 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b508 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b50c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b510 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b514 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b518 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b51c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b520 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b524 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b528 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b52c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b530 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b534 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b538 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b53c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b540 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b544 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b548 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b54c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b550 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b554 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b558 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b55c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b560 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b564 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b568 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b56c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b570 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b574 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b578 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b57c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00016044 , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db }, + { 0x00016048 , 0x6c924260 , 0x6c924260 , 0x6c924260 , 0x6c924260 }, +}; + +static const u_int32_t ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x10213e5e }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0000580c }, +}; + +static const u_int32_t ar9485_poseidon1_0_radio_postamble[][2] = { +/* Addr allmodes */ + { 0x0001609c , 0x0b283f31 }, + { 0x000160ac , 0x24611800 }, + { 0x000160b0 , 0x03284f3e }, + { 0x0001610c , 0x00170000 }, + { 0x00016140 , 0x10804008 }, +}; + +static const u_int32_t ar9485_poseidon1_0_mac_core[][2] = { +/* Addr allmodes */ + { 0x00000008 , 0x00000000 }, + { 0x00000030 , 0x00020085 }, + { 0x00000034 , 0x00000005 }, + { 0x00000040 , 0x00000000 }, + { 0x00000044 , 0x00000000 }, + { 0x00000048 , 0x00000008 }, + { 0x0000004c , 0x00000010 }, + { 0x00000050 , 0x00000000 }, + { 0x00001040 , 0x002ffc0f }, + { 0x00001044 , 0x002ffc0f }, + { 0x00001048 , 0x002ffc0f }, + { 0x0000104c , 0x002ffc0f }, + { 0x00001050 , 0x002ffc0f }, + { 0x00001054 , 0x002ffc0f }, + { 0x00001058 , 0x002ffc0f }, + { 0x0000105c , 0x002ffc0f }, + { 0x00001060 , 0x002ffc0f }, + { 0x00001064 , 0x002ffc0f }, + { 0x000010f0 , 0x00000100 }, + { 0x00001270 , 0x00000000 }, + { 0x000012b0 , 0x00000000 }, + { 0x000012f0 , 0x00000000 }, + { 0x0000143c , 0x00000000 }, + { 0x0000147c , 0x00000000 }, + { 0x00008000 , 0x00000000 }, + { 0x00008004 , 0x00000000 }, + { 0x00008008 , 0x00000000 }, + { 0x0000800c , 0x00000000 }, + { 0x00008018 , 0x00000000 }, + { 0x00008020 , 0x00000000 }, + { 0x00008038 , 0x00000000 }, + { 0x0000803c , 0x00000000 }, + { 0x00008040 , 0x00000000 }, + { 0x00008044 , 0x00000000 }, + { 0x00008048 , 0x00000000 }, + { 0x0000804c , 0xffffffff }, + { 0x00008054 , 0x00000000 }, + { 0x00008058 , 0x00000000 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008060 , 0x0000000f }, + { 0x00008064 , 0x00000000 }, + { 0x00008070 , 0x00000310 }, + { 0x00008074 , 0x00000020 }, + { 0x00008078 , 0x00000000 }, + { 0x0000809c , 0x0000000f }, + { 0x000080a0 , 0x00000000 }, + { 0x000080a4 , 0x02ff0000 }, + { 0x000080a8 , 0x0e070605 }, + { 0x000080ac , 0x0000000d }, + { 0x000080b0 , 0x00000000 }, + { 0x000080b4 , 0x00000000 }, + { 0x000080b8 , 0x00000000 }, + { 0x000080bc , 0x00000000 }, + { 0x000080c0 , 0x2a800000 }, + { 0x000080c4 , 0x06900168 }, + { 0x000080c8 , 0x13881c20 }, + { 0x000080cc , 0x01f40000 }, + { 0x000080d0 , 0x00252500 }, + { 0x000080d4 , 0x00a00000 }, + { 0x000080d8 , 0x00400000 }, + { 0x000080dc , 0x00000000 }, + { 0x000080e0 , 0xffffffff }, + { 0x000080e4 , 0x0000ffff }, + { 0x000080e8 , 0x3f3f3f3f }, + { 0x000080ec , 0x00000000 }, + { 0x000080f0 , 0x00000000 }, + { 0x000080f4 , 0x00000000 }, + { 0x000080fc , 0x00020000 }, + { 0x00008100 , 0x00000000 }, + { 0x00008108 , 0x00000052 }, + { 0x0000810c , 0x00000000 }, + { 0x00008110 , 0x00000000 }, + { 0x00008114 , 0x000007ff }, + { 0x00008118 , 0x000000aa }, + { 0x0000811c , 0x00003210 }, + { 0x00008124 , 0x00000000 }, + { 0x00008128 , 0x00000000 }, + { 0x0000812c , 0x00000000 }, + { 0x00008130 , 0x00000000 }, + { 0x00008134 , 0x00000000 }, + { 0x00008138 , 0x00000000 }, + { 0x0000813c , 0x0000ffff }, + { 0x00008144 , 0xffffffff }, + { 0x00008168 , 0x00000000 }, + { 0x0000816c , 0x00000000 }, + { 0x00008170 , 0x18486200 }, + { 0x00008174 , 0x33332210 }, + { 0x00008178 , 0x00000000 }, + { 0x0000817c , 0x00020000 }, + { 0x000081c0 , 0x00000000 }, + { 0x000081c4 , 0x33332210 }, + { 0x000081d4 , 0x00000000 }, + { 0x000081ec , 0x00000000 }, + { 0x000081f0 , 0x00000000 }, + { 0x000081f4 , 0x00000000 }, + { 0x000081f8 , 0x00000000 }, + { 0x000081fc , 0x00000000 }, + { 0x00008240 , 0x00100000 }, + { 0x00008244 , 0x0010f400 }, + { 0x00008248 , 0x00000800 }, + { 0x0000824c , 0x0001e800 }, + { 0x00008250 , 0x00000000 }, + { 0x00008254 , 0x00000000 }, + { 0x00008258 , 0x00000000 }, + { 0x0000825c , 0x40000000 }, + { 0x00008260 , 0x00080922 }, + { 0x00008264 , 0x9ca00010 }, + { 0x00008268 , 0xffffffff }, + { 0x0000826c , 0x0000ffff }, + { 0x00008270 , 0x00000000 }, + { 0x00008274 , 0x40000000 }, + { 0x00008278 , 0x003e4180 }, + { 0x0000827c , 0x00000004 }, + { 0x00008284 , 0x0000002c }, + { 0x00008288 , 0x0000002c }, + { 0x0000828c , 0x000000ff }, + { 0x00008294 , 0x00000000 }, + { 0x00008298 , 0x00000000 }, + { 0x0000829c , 0x00000000 }, + { 0x00008300 , 0x00000140 }, + { 0x00008314 , 0x00000000 }, + { 0x0000831c , 0x0000010d }, + { 0x00008328 , 0x00000000 }, + { 0x0000832c , 0x00000007 }, + { 0x00008330 , 0x00000302 }, + { 0x00008334 , 0x00000700 }, + { 0x00008338 , 0x00ff0000 }, + { 0x0000833c , 0x02400000 }, + { 0x00008340 , 0x000107ff }, + { 0x00008344 , 0xa248105b }, + { 0x00008348 , 0x008f0000 }, + { 0x0000835c , 0x00000000 }, + { 0x00008360 , 0xffffffff }, + { 0x00008364 , 0xffffffff }, + { 0x00008368 , 0x00000000 }, + { 0x00008370 , 0x00000000 }, + { 0x00008374 , 0x000000ff }, + { 0x00008378 , 0x00000000 }, + { 0x0000837c , 0x00000000 }, + { 0x00008380 , 0xffffffff }, + { 0x00008384 , 0xffffffff }, + { 0x00008390 , 0xffffffff }, + { 0x00008394 , 0xffffffff }, + { 0x00008398 , 0x00000000 }, + { 0x0000839c , 0x00000000 }, + { 0x000083a0 , 0x00000000 }, + { 0x000083a4 , 0x0000fa14 }, + { 0x000083a8 , 0x000f0c00 }, + { 0x000083ac , 0x33332210 }, + { 0x000083b0 , 0x33332210 }, + { 0x000083b4 , 0x33332210 }, + { 0x000083b8 , 0x33332210 }, + { 0x000083bc , 0x00000000 }, + { 0x000083c0 , 0x00000000 }, + { 0x000083c4 , 0x00000000 }, + { 0x000083c8 , 0x00000000 }, + { 0x000083cc , 0x00000200 }, + { 0x000083d0 , 0x000301ff }, +}; + diff --git a/hal/ar9300/ar9485_1_1.ini b/hal/ar9300/ar9485_1_1.ini new file mode 100644 index 000000000000..e21a6a3022b5 --- /dev/null +++ b/hal/ar9300/ar9485_1_1.ini @@ -0,0 +1,1292 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +static const u_int32_t ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000003 , 0x00000003 , 0x00000003 , 0x00000003 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d8 , 0x000050d8 }, + { 0x0000a458 , 0x80000000 , 0x80000000 , 0x80000000 , 0x80000000 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000006 , 0x00000006 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x03000201 , 0x03000201 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x07000203 , 0x07000203 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0a000401 , 0x0a000401 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x0e000403 , 0x0e000403 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x12000405 , 0x12000405 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x14000406 , 0x14000406 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1800040a , 0x1800040a }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x1c000460 , 0x1c000460 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x22000463 , 0x22000463 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x26000465 , 0x26000465 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2e0006e0 , 0x2e0006e0 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x310006e0 , 0x310006e0 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x330006e0 , 0x330006e0 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x3e0008e3 , 0x3e0008e3 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x410008e5 , 0x410008e5 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x430008e6 , 0x430008e6 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4a0008ec , 0x4a0008ec }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4e0008f1 , 0x4e0008f1 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x520008f3 , 0x520008f3 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x54000eed , 0x54000eed }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x58000ef1 , 0x58000ef1 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5c000ef3 , 0x5c000ef3 }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x60000ef5 , 0x60000ef5 }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x62000ef6 , 0x62000ef6 }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x62000ef6 , 0x62000ef6 }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x62000ef6 , 0x62000ef6 }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x62000ef6 , 0x62000ef6 }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x62000ef6 , 0x62000ef6 }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x62000ef6 , 0x62000ef6 }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x62000ef6 , 0x62000ef6 }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x62000ef6 , 0x62000ef6 }, + { 0x0000b500 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b504 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b508 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b50c , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b510 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b514 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b518 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b51c , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b520 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b524 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b528 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b52c , 0x0000002a , 0x0000002a , 0x0000002a , 0x0000002a }, + { 0x0000b530 , 0x0000003a , 0x0000003a , 0x0000003a , 0x0000003a }, + { 0x0000b534 , 0x0000004a , 0x0000004a , 0x0000004a , 0x0000004a }, + { 0x0000b538 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b53c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b540 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b544 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b548 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b54c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b550 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b554 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b558 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b55c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b560 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b564 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b568 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b56c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b570 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b574 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b578 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b57c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x00016044 , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db }, + { 0x00016048 , 0x6c924260 , 0x6c924260 , 0x6c924260 , 0x6c924260 }, +}; + +static const u_int32_t ar9485_poseidon1_1_mac_core[][2] = { +/* Addr allmodes */ + { 0x00000008 , 0x00000000 }, + { 0x00000030 , 0x00020085 }, + { 0x00000034 , 0x00000005 }, + { 0x00000040 , 0x00000000 }, + { 0x00000044 , 0x00000000 }, + { 0x00000048 , 0x00000008 }, + { 0x0000004c , 0x00000010 }, + { 0x00000050 , 0x00000000 }, + { 0x00001040 , 0x002ffc0f }, + { 0x00001044 , 0x002ffc0f }, + { 0x00001048 , 0x002ffc0f }, + { 0x0000104c , 0x002ffc0f }, + { 0x00001050 , 0x002ffc0f }, + { 0x00001054 , 0x002ffc0f }, + { 0x00001058 , 0x002ffc0f }, + { 0x0000105c , 0x002ffc0f }, + { 0x00001060 , 0x002ffc0f }, + { 0x00001064 , 0x002ffc0f }, + { 0x000010f0 , 0x00000100 }, + { 0x00001270 , 0x00000000 }, + { 0x000012b0 , 0x00000000 }, + { 0x000012f0 , 0x00000000 }, + { 0x0000143c , 0x00000000 }, + { 0x0000147c , 0x00000000 }, + { 0x00008000 , 0x00000000 }, + { 0x00008004 , 0x00000000 }, + { 0x00008008 , 0x00000000 }, + { 0x0000800c , 0x00000000 }, + { 0x00008018 , 0x00000000 }, + { 0x00008020 , 0x00000000 }, + { 0x00008038 , 0x00000000 }, + { 0x0000803c , 0x00000000 }, + { 0x00008040 , 0x00000000 }, + { 0x00008044 , 0x00000000 }, + { 0x00008048 , 0x00000000 }, + { 0x0000804c , 0xffffffff }, + { 0x00008054 , 0x00000000 }, + { 0x00008058 , 0x00000000 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008060 , 0x0000000f }, + { 0x00008064 , 0x00000000 }, + { 0x00008070 , 0x00000310 }, + { 0x00008074 , 0x00000020 }, + { 0x00008078 , 0x00000000 }, + { 0x0000809c , 0x0000000f }, + { 0x000080a0 , 0x00000000 }, + { 0x000080a4 , 0x02ff0000 }, + { 0x000080a8 , 0x0e070605 }, + { 0x000080ac , 0x0000000d }, + { 0x000080b0 , 0x00000000 }, + { 0x000080b4 , 0x00000000 }, + { 0x000080b8 , 0x00000000 }, + { 0x000080bc , 0x00000000 }, + { 0x000080c0 , 0x2a800000 }, + { 0x000080c4 , 0x06900168 }, + { 0x000080c8 , 0x13881c22 }, + { 0x000080cc , 0x01f40000 }, + { 0x000080d0 , 0x00252500 }, + { 0x000080d4 , 0x00a00000 }, + { 0x000080d8 , 0x00400000 }, + { 0x000080dc , 0x00000000 }, + { 0x000080e0 , 0xffffffff }, + { 0x000080e4 , 0x0000ffff }, + { 0x000080e8 , 0x3f3f3f3f }, + { 0x000080ec , 0x00000000 }, + { 0x000080f0 , 0x00000000 }, + { 0x000080f4 , 0x00000000 }, + { 0x000080fc , 0x00020000 }, + { 0x00008100 , 0x00000000 }, + { 0x00008108 , 0x00000052 }, + { 0x0000810c , 0x00000000 }, + { 0x00008110 , 0x00000000 }, + { 0x00008114 , 0x000007ff }, + { 0x00008118 , 0x000000aa }, + { 0x0000811c , 0x00003210 }, + { 0x00008124 , 0x00000000 }, + { 0x00008128 , 0x00000000 }, + { 0x0000812c , 0x00000000 }, + { 0x00008130 , 0x00000000 }, + { 0x00008134 , 0x00000000 }, + { 0x00008138 , 0x00000000 }, + { 0x0000813c , 0x0000ffff }, + { 0x00008144 , 0xffffffff }, + { 0x00008168 , 0x00000000 }, + { 0x0000816c , 0x00000000 }, + { 0x00008170 , 0x18486200 }, + { 0x00008174 , 0x33332210 }, + { 0x00008178 , 0x00000000 }, + { 0x0000817c , 0x00020000 }, + { 0x000081c0 , 0x00000000 }, + { 0x000081c4 , 0x33332210 }, + { 0x000081d4 , 0x00000000 }, + { 0x000081ec , 0x00000000 }, + { 0x000081f0 , 0x00000000 }, + { 0x000081f4 , 0x00000000 }, + { 0x000081f8 , 0x00000000 }, + { 0x000081fc , 0x00000000 }, + { 0x00008240 , 0x00100000 }, + { 0x00008244 , 0x0010f400 }, + { 0x00008248 , 0x00000800 }, + { 0x0000824c , 0x0001e800 }, + { 0x00008250 , 0x00000000 }, + { 0x00008254 , 0x00000000 }, + { 0x00008258 , 0x00000000 }, + { 0x0000825c , 0x40000000 }, + { 0x00008260 , 0x00080922 }, + { 0x00008264 , 0x9ca00010 }, + { 0x00008268 , 0xffffffff }, + { 0x0000826c , 0x0000ffff }, + { 0x00008270 , 0x00000000 }, + { 0x00008274 , 0x40000000 }, + { 0x00008278 , 0x003e4180 }, + { 0x0000827c , 0x00000004 }, + { 0x00008284 , 0x0000002c }, + { 0x00008288 , 0x0000002c }, + { 0x0000828c , 0x000000ff }, + { 0x00008294 , 0x00000000 }, + { 0x00008298 , 0x00000000 }, + { 0x0000829c , 0x00000000 }, + { 0x00008300 , 0x00000140 }, + { 0x00008314 , 0x00000000 }, + { 0x0000831c , 0x0000010d }, + { 0x00008328 , 0x00000000 }, + { 0x0000832c , 0x00000007 }, + { 0x00008330 , 0x00000302 }, + { 0x00008334 , 0x00000700 }, + { 0x00008338 , 0x00ff0000 }, + { 0x0000833c , 0x02400000 }, + { 0x00008340 , 0x000107ff }, + { 0x00008344 , 0xa248105b }, + { 0x00008348 , 0x008f0000 }, + { 0x0000835c , 0x00000000 }, + { 0x00008360 , 0xffffffff }, + { 0x00008364 , 0xffffffff }, + { 0x00008368 , 0x00000000 }, + { 0x00008370 , 0x00000000 }, + { 0x00008374 , 0x000000ff }, + { 0x00008378 , 0x00000000 }, + { 0x0000837c , 0x00000000 }, + { 0x00008380 , 0xffffffff }, + { 0x00008384 , 0xffffffff }, + { 0x00008390 , 0xffffffff }, + { 0x00008394 , 0xffffffff }, + { 0x00008398 , 0x00000000 }, + { 0x0000839c , 0x00000000 }, + { 0x000083a0 , 0x00000000 }, + { 0x000083a4 , 0x0000fa14 }, + { 0x000083a8 , 0x000f0c00 }, + { 0x000083ac , 0x33332210 }, + { 0x000083b0 , 0x33332210 }, + { 0x000083b4 , 0x33332210 }, + { 0x000083b8 , 0x33332210 }, + { 0x000083bc , 0x00000000 }, + { 0x000083c0 , 0x00000000 }, + { 0x000083c4 , 0x00000000 }, + { 0x000083c8 , 0x00000000 }, + { 0x000083cc , 0x00000200 }, + { 0x000083d0 , 0x000301ff }, +}; + +static const u_int32_t ar9485_poseidon1_1_baseband_core[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009804 , 0xfd14e000 }, + { 0x00009808 , 0x9c0a8f6b }, + { 0x0000980c , 0x04800000 }, + { 0x00009814 , 0x9280c00a }, + { 0x00009818 , 0x00000000 }, + { 0x0000981c , 0x00020028 }, + { 0x00009834 , 0x5f3ca3de }, + { 0x00009838 , 0x0108ecff }, + { 0x0000983c , 0x14750600 }, + { 0x00009880 , 0x201fff00 }, + { 0x00009884 , 0x00001042 }, + { 0x000098a4 , 0x00200400 }, + { 0x000098b0 , 0x52440bbe }, + { 0x000098d0 , 0x004b6a8e }, + { 0x000098d4 , 0x00000820 }, + { 0x000098dc , 0x00000000 }, + { 0x000098f0 , 0x00000000 }, + { 0x000098f4 , 0x00000000 }, + { 0x00009c04 , 0x00000000 }, + { 0x00009c08 , 0x03200000 }, + { 0x00009c0c , 0x00000000 }, + { 0x00009c10 , 0x00000000 }, + { 0x00009c14 , 0x00046384 }, + { 0x00009c18 , 0x05b6b440 }, + { 0x00009c1c , 0x00b6b440 }, + { 0x00009d00 , 0xc080a333 }, + { 0x00009d04 , 0x40206c10 }, + { 0x00009d08 , 0x009c4060 }, + { 0x00009d0c , 0x1883800a }, + { 0x00009d10 , 0x01834061 }, + { 0x00009d14 , 0x00c00400 }, + { 0x00009d18 , 0x00000000 }, + { 0x00009d1c , 0x00000000 }, + { 0x00009e08 , 0x0038233c }, + { 0x00009e24 , 0x992bb515 }, + { 0x00009e28 , 0x12ef0200 }, + { 0x00009e30 , 0x06336f77 }, + { 0x00009e34 , 0x6af6532f }, + { 0x00009e38 , 0x0cc80c00 }, + { 0x00009e40 , 0x0d261820 }, + { 0x00009e4c , 0x00001004 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009fc0 , 0x80be4788 }, + { 0x00009fc4 , 0x0001efb5 }, + { 0x00009fcc , 0x40000014 }, + { 0x0000a20c , 0x00000000 }, + { 0x0000a210 , 0x00000000 }, + { 0x0000a220 , 0x00000000 }, + { 0x0000a224 , 0x00000000 }, + { 0x0000a228 , 0x10002310 }, + { 0x0000a23c , 0x00000000 }, + { 0x0000a244 , 0x0c000000 }, + { 0x0000a2a0 , 0x00000001 }, + { 0x0000a2c0 , 0x00000001 }, + { 0x0000a2c8 , 0x00000000 }, + { 0x0000a2cc , 0x18c43433 }, + { 0x0000a2d4 , 0x00000000 }, + { 0x0000a2dc , 0x00000000 }, + { 0x0000a2e0 , 0x00000000 }, + { 0x0000a2e4 , 0x00000000 }, + { 0x0000a2e8 , 0x00000000 }, + { 0x0000a2ec , 0x00000000 }, + { 0x0000a2f0 , 0x00000000 }, + { 0x0000a2f4 , 0x00000000 }, + { 0x0000a2f8 , 0x00000000 }, + { 0x0000a344 , 0x00000000 }, + { 0x0000a34c , 0x00000000 }, + { 0x0000a350 , 0x0000a000 }, + { 0x0000a364 , 0x00000000 }, + { 0x0000a370 , 0x00000000 }, + { 0x0000a390 , 0x00000001 }, + { 0x0000a394 , 0x00000444 }, + { 0x0000a398 , 0x001f0e0f }, + { 0x0000a39c , 0x0075393f }, + { 0x0000a3a0 , 0xb79f6427 }, + { 0x0000a3a4 , 0x000000ff }, + { 0x0000a3a8 , 0x3b3b3b3b }, + { 0x0000a3ac , 0x2f2f2f2f }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a3c8 , 0x20200020 }, + { 0x0000a3cc , 0x20202020 }, + { 0x0000a3d0 , 0x20202020 }, + { 0x0000a3d4 , 0x20202020 }, + { 0x0000a3d8 , 0x20202020 }, + { 0x0000a3dc , 0x20202020 }, + { 0x0000a3e0 , 0x20202020 }, + { 0x0000a3e4 , 0x20202020 }, + { 0x0000a3e8 , 0x20202020 }, + { 0x0000a3ec , 0x20202020 }, + { 0x0000a3f0 , 0x00000000 }, + { 0x0000a3f4 , 0x00000006 }, + { 0x0000a3f8 , 0x0cdbd380 }, + { 0x0000a3fc , 0x000f0f01 }, + { 0x0000a400 , 0x8fa91f01 }, + { 0x0000a404 , 0x00000000 }, + { 0x0000a408 , 0x0e79e5c6 }, + { 0x0000a40c , 0x00820820 }, + { 0x0000a414 , 0x1ce739cf }, + { 0x0000a418 , 0x2d0021ce }, + { 0x0000a41c , 0x1ce739ce }, + { 0x0000a420 , 0x000001ce }, + { 0x0000a424 , 0x1ce739ce }, + { 0x0000a428 , 0x000001ce }, + { 0x0000a42c , 0x1ce739ce }, + { 0x0000a430 , 0x1ce739ce }, + { 0x0000a434 , 0x00000000 }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a43c , 0x00000000 }, + { 0x0000a440 , 0x00000000 }, + { 0x0000a444 , 0x00000000 }, + { 0x0000a448 , 0x04000000 }, + { 0x0000a44c , 0x00000001 }, + { 0x0000a450 , 0x00010000 }, + { 0x0000a5c4 , 0xbfad9d74 }, + { 0x0000a5c8 , 0x0048060a }, + { 0x0000a5cc , 0x00000637 }, + { 0x0000a760 , 0x03020100 }, + { 0x0000a764 , 0x09080504 }, + { 0x0000a768 , 0x0d0c0b0a }, + { 0x0000a76c , 0x13121110 }, + { 0x0000a770 , 0x31301514 }, + { 0x0000a774 , 0x35343332 }, + { 0x0000a778 , 0x00000036 }, + { 0x0000a780 , 0x00000838 }, + { 0x0000a7c0 , 0x00000000 }, + { 0x0000a7c4 , 0xfffffffc }, + { 0x0000a7c8 , 0x00000000 }, + { 0x0000a7cc , 0x00000000 }, + { 0x0000a7d0 , 0x00000000 }, + { 0x0000a7d4 , 0x00000004 }, + { 0x0000a7dc , 0x00000000 }, +}; + +static const u_int32_t ar9485Common_poseidon1_1[][2] = { +/* Addr allmodes */ + { 0x00007010 , 0x00000022 }, + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000004c2 }, +}; + +static const u_int32_t ar9485_poseidon1_1_baseband_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 , 0xd00a8005 }, + { 0x00009820 , 0x206a002e , 0x206a002e , 0x206a002e , 0x206a002e }, + { 0x00009824 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 }, + { 0x00009828 , 0x06903081 , 0x06903081 , 0x06903881 , 0x06903881 }, + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000059c , 0x0000059c }, + { 0x00009c00 , 0x00000044 , 0x00000044 , 0x00000044 , 0x00000044 }, + { 0x00009e00 , 0x0372161e , 0x0372161e , 0x037216a0 , 0x037216a0 }, + { 0x00009e04 , 0x00182020 , 0x00182020 , 0x00182020 , 0x00182020 }, + { 0x00009e0c , 0x6c4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + { 0x00009e10 , 0x7ec88d2e , 0x7ec88d2e , 0x7ec80d2e , 0x7ec80d2e }, + { 0x00009e14 , 0x31395d5e , 0x3139605e , 0x3139605e , 0x31395d5e }, + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + { 0x00009e2c , 0x0000411c , 0x0000411c , 0x00004121 , 0x00004121 }, + { 0x00009e3c , 0xcf946220 , 0xcf946220 , 0xcf946222 , 0xcf946222 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302010 , 0x50302010 }, + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, + { 0x0000a204 , 0x01303fc0 , 0x01303fc4 , 0x01303fc4 , 0x01303fc0 }, + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + { 0x0000a230 , 0x0000400a , 0x00004014 , 0x00004016 , 0x0000400b }, + { 0x0000a234 , 0x10000fff , 0x10000fff , 0x10000fff , 0x10000fff }, + { 0x0000a238 , 0xffb81018 , 0xffb81018 , 0xffb81018 , 0xffb81018 }, + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a260 , 0x3a021501 , 0x3a021501 , 0x3a021501 , 0x3a021501 }, + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x000002a0 , 0x000002a0 }, + { 0x0000a288 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a28c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2d0 , 0x00071981 , 0x00071981 , 0x00071982 , 0x00071982 }, + { 0x0000a2d8 , 0xf999a83a , 0xf999a83a , 0xf999a83a , 0xf999a83a }, + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000be04 , 0x00802020 , 0x00802020 , 0x00802020 , 0x00802020 }, + { 0x0000be18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +}; + +static const u_int32_t ar9485_modes_high_ob_db_tx_gain_poseidon1_1[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000002 , 0x00000002 , 0x00000002 , 0x00000002 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d8 , 0x000050d8 }, + { 0x0000a458 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x21000603 , 0x21000603 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x25000605 , 0x25000605 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2a000a03 , 0x2a000a03 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2c000a04 , 0x2c000a04 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x34000e20 , 0x34000e20 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x35000e21 , 0x35000e21 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x43000e62 , 0x43000e62 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x45000e63 , 0x45000e63 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x49000e65 , 0x49000e65 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4b000e66 , 0x4b000e66 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4d001645 , 0x4d001645 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x51001865 , 0x51001865 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x55001a86 , 0x55001a86 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x57001ce9 , 0x57001ce9 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000b500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b504 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b508 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b50c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b510 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b514 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b518 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b51c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b520 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b524 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b528 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b52c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b530 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b534 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b538 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b53c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b540 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b544 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b548 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b54c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b550 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b554 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b558 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b55c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b560 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b564 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b568 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b56c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b570 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b574 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b578 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b57c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00016044 , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db }, + { 0x00016048 , 0x6c924260 , 0x6c924260 , 0x6c924260 , 0x6c924260 }, +}; + +static const u_int32_t ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000002 , 0x00000002 , 0x00000002 , 0x00000002 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d8 , 0x000050d8 }, + { 0x0000a458 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x21000603 , 0x21000603 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x25000605 , 0x25000605 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2a000a03 , 0x2a000a03 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2c000a04 , 0x2c000a04 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x34000e20 , 0x34000e20 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x35000e21 , 0x35000e21 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x43000e62 , 0x43000e62 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x45000e63 , 0x45000e63 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x49000e65 , 0x49000e65 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4b000e66 , 0x4b000e66 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4d001645 , 0x4d001645 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x51001865 , 0x51001865 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x55001a86 , 0x55001a86 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x57001ce9 , 0x57001ce9 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000b500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b504 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b508 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b50c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b510 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b514 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b518 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b51c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b520 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b524 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b528 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b52c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b530 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b534 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b538 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b53c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b540 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b544 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b548 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b54c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b550 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b554 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b558 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b55c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b560 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b564 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b568 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b56c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b570 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b574 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b578 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b57c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00016044 , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db }, + { 0x00016048 , 0x6c924260 , 0x6c924260 , 0x6c924260 , 0x6c924260 }, +}; + +static const u_int32_t ar9485_poseidon1_1_radio_postamble[][2] = { +/* Addr allmodes */ + { 0x0001609c , 0x0b283f31 }, + { 0x000160ac , 0x24611800 }, + { 0x000160b0 , 0x03284f3e }, + { 0x0001610c , 0x00170000 }, + { 0x00016140 , 0x50804008 }, +}; + +static const u_int32_t ar9485_poseidon1_1_mac_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, +}; + +static const u_int32_t ar9485_poseidon1_1_radio_core[][2] = { +/* Addr allmodes */ + { 0x00016000 , 0x36db6db6 }, + { 0x00016004 , 0x6db6db40 }, + { 0x00016008 , 0x73800000 }, + { 0x0001600c , 0x00000000 }, + { 0x00016040 , 0x7f80fff8 }, + { 0x0001604c , 0x000f0278 }, + { 0x00016050 , 0x4db6db8c }, + { 0x00016054 , 0x6db60000 }, + { 0x00016080 , 0x00080000 }, + { 0x00016084 , 0x0e48048c }, + { 0x00016088 , 0x14214514 }, + { 0x0001608c , 0x119f081e }, + { 0x00016090 , 0x24926490 }, + { 0x00016098 , 0xd28b3330 }, + { 0x000160a0 , 0xc2108ffe }, + { 0x000160a4 , 0x812fc370 }, + { 0x000160a8 , 0x423c8000 }, + { 0x000160b4 , 0x92480040 }, + { 0x000160c0 , 0x006db6db }, + { 0x000160c4 , 0x0186db60 }, + { 0x000160c8 , 0x6db6db6c }, + { 0x000160cc , 0x6de6fbe0 }, + { 0x000160d0 , 0xf7dfcf3c }, + { 0x00016100 , 0x04cb0001 }, + { 0x00016104 , 0xfff80015 }, + { 0x00016108 , 0x00080010 }, + { 0x00016144 , 0x01884080 }, + { 0x00016148 , 0x00008040 }, + { 0x00016240 , 0x08400000 }, + { 0x00016244 , 0x1bf90f00 }, + { 0x00016248 , 0x00000000 }, + { 0x0001624c , 0x00000000 }, + { 0x00016280 , 0x01000015 }, + { 0x00016284 , 0x00d30000 }, + { 0x00016288 , 0x00318000 }, + { 0x0001628c , 0x50000000 }, + { 0x00016290 , 0x4b96210f }, + { 0x00016380 , 0x00000000 }, + { 0x00016384 , 0x00000000 }, + { 0x00016388 , 0x00800700 }, + { 0x0001638c , 0x00800700 }, + { 0x00016390 , 0x00800700 }, + { 0x00016394 , 0x00000000 }, + { 0x00016398 , 0x00000000 }, + { 0x0001639c , 0x00000000 }, + { 0x000163a0 , 0x00000001 }, + { 0x000163a4 , 0x00000001 }, + { 0x000163a8 , 0x00000000 }, + { 0x000163ac , 0x00000000 }, + { 0x000163b0 , 0x00000000 }, + { 0x000163b4 , 0x00000000 }, + { 0x000163b8 , 0x00000000 }, + { 0x000163bc , 0x00000000 }, + { 0x000163c0 , 0x000000a0 }, + { 0x000163c4 , 0x000c0000 }, + { 0x000163c8 , 0x14021402 }, + { 0x000163cc , 0x00001402 }, + { 0x000163d0 , 0x00000000 }, + { 0x000163d4 , 0x00000000 }, + { 0x00016c40 , 0x13188278 }, + { 0x00016c44 , 0x12000000 }, +}; + +static const u_int32_t ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x18052e5e }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0000080c }, +}; + +static const u_int32_t ar9485_modes_high_power_tx_gain_poseidon1_1[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000002 , 0x00000002 , 0x00000002 , 0x00000002 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d8 , 0x000050d8 }, + { 0x0000a458 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x21000603 , 0x21000603 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x25000605 , 0x25000605 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2a000a03 , 0x2a000a03 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2c000a04 , 0x2c000a04 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x34000e20 , 0x34000e20 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x35000e21 , 0x35000e21 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x43000e62 , 0x43000e62 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x45000e63 , 0x45000e63 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x49000e65 , 0x49000e65 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4b000e66 , 0x4b000e66 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4d001645 , 0x4d001645 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x51001865 , 0x51001865 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x55001a86 , 0x55001a86 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x57001ce9 , 0x57001ce9 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000b500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b504 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b508 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b50c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b510 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b514 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b518 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b51c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b520 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b524 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b528 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b52c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b530 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b534 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b538 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b53c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b540 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b544 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b548 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b54c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b550 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b554 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b558 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b55c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b560 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b564 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b568 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b56c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b570 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b574 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b578 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b57c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00016044 , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db }, + { 0x00016048 , 0x6c924260 , 0x6c924260 , 0x6c924260 , 0x6c924260 }, +}; + +static const u_int32_t ar9485_poseidon1_1[][2] = { +/* Addr allmodes */ + { 0x0000a580 , 0x00000000 }, + { 0x0000a584 , 0x00000000 }, + { 0x0000a588 , 0x00000000 }, + { 0x0000a58c , 0x00000000 }, + { 0x0000a590 , 0x00000000 }, + { 0x0000a594 , 0x00000000 }, + { 0x0000a598 , 0x00000000 }, + { 0x0000a59c , 0x00000000 }, + { 0x0000a5a0 , 0x00000000 }, + { 0x0000a5a4 , 0x00000000 }, + { 0x0000a5a8 , 0x00000000 }, + { 0x0000a5ac , 0x00000000 }, + { 0x0000a5b0 , 0x00000000 }, + { 0x0000a5b4 , 0x00000000 }, + { 0x0000a5b8 , 0x00000000 }, + { 0x0000a5bc , 0x00000000 }, +}; + +static const u_int32_t ar9485_modes_green_ob_db_tx_gain_poseidon1_1[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000003 , 0x00000003 , 0x00000003 , 0x00000003 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d8 , 0x000050d8 }, + { 0x0000a458 , 0x80000000 , 0x80000000 , 0x80000000 , 0x80000000 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000006 , 0x00000006 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x03000201 , 0x03000201 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x06000203 , 0x06000203 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0a000401 , 0x0a000401 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x0e000403 , 0x0e000403 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x12000405 , 0x12000405 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x15000604 , 0x15000604 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x18000605 , 0x18000605 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x1c000a04 , 0x1c000a04 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x21000a06 , 0x21000a06 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x29000a24 , 0x29000a24 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2f000e21 , 0x2f000e21 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x31000e20 , 0x31000e20 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x33000e20 , 0x33000e20 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x43000e62 , 0x43000e62 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x45000e63 , 0x45000e63 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x49000e65 , 0x49000e65 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4b000e66 , 0x4b000e66 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4d001645 , 0x4d001645 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x51001865 , 0x51001865 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x55001a86 , 0x55001a86 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x57001ce9 , 0x57001ce9 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000b500 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b504 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b508 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b50c , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b510 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b514 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b518 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b51c , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b520 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b524 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b528 , 0x0000001a , 0x0000001a , 0x0000001a , 0x0000001a }, + { 0x0000b52c , 0x0000002a , 0x0000002a , 0x0000002a , 0x0000002a }, + { 0x0000b530 , 0x0000003a , 0x0000003a , 0x0000003a , 0x0000003a }, + { 0x0000b534 , 0x0000004a , 0x0000004a , 0x0000004a , 0x0000004a }, + { 0x0000b538 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b53c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b540 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b544 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b548 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b54c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b550 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b554 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b558 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b55c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b560 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b564 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b568 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b56c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b570 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b574 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b578 , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x0000b57c , 0x0000005b , 0x0000005b , 0x0000005b , 0x0000005b }, + { 0x00016044 , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db }, + { 0x00016048 , 0x6c924260 , 0x6c924260 , 0x6c924260 , 0x6c924260 }, +}; + +static const u_int32_t ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x18013e5e }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0000080c }, +}; + +static const u_int32_t ar9485_poseidon1_1_soc_preamble[][2] = { +/* Addr allmodes */ + { 0x00004014 , 0xba280400 }, + { 0x00004090 , 0x00aa10aa }, + { 0x000040a4 , 0x00a0c9c9 }, + { 0x00007010 , 0x00000022 }, + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000004c2 }, + { 0x00007048 , 0x00000002 }, +}; + +static const u_int32_t ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484[][2] = { +/* Addr allmodes */ + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x6f7f0301 }, + { 0x0000a3a0 , 0xca9228ee }, +}; + +static const u_int32_t ar9485_modes_low_ob_db_tx_gain_poseidon1_1[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x000098bc , 0x00000002 , 0x00000002 , 0x00000002 , 0x00000002 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d8 , 0x000050d8 }, + { 0x0000a458 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 }, + { 0x0000a510 , 0x17022e00 , 0x17022e00 , 0x11000202 , 0x11000202 }, + { 0x0000a514 , 0x1d000ec2 , 0x1d000ec2 , 0x15000400 , 0x15000400 }, + { 0x0000a518 , 0x25020ec0 , 0x25020ec0 , 0x19000402 , 0x19000402 }, + { 0x0000a51c , 0x2b020ec3 , 0x2b020ec3 , 0x1d000404 , 0x1d000404 }, + { 0x0000a520 , 0x2f001f04 , 0x2f001f04 , 0x21000603 , 0x21000603 }, + { 0x0000a524 , 0x35001fc4 , 0x35001fc4 , 0x25000605 , 0x25000605 }, + { 0x0000a528 , 0x3c022f04 , 0x3c022f04 , 0x2a000a03 , 0x2a000a03 }, + { 0x0000a52c , 0x41023e85 , 0x41023e85 , 0x2c000a04 , 0x2c000a04 }, + { 0x0000a530 , 0x48023ec6 , 0x48023ec6 , 0x34000e20 , 0x34000e20 }, + { 0x0000a534 , 0x4d023f01 , 0x4d023f01 , 0x35000e21 , 0x35000e21 }, + { 0x0000a538 , 0x53023f4b , 0x53023f4b , 0x43000e62 , 0x43000e62 }, + { 0x0000a53c , 0x5a027f09 , 0x5a027f09 , 0x45000e63 , 0x45000e63 }, + { 0x0000a540 , 0x5f027fc9 , 0x5f027fc9 , 0x49000e65 , 0x49000e65 }, + { 0x0000a544 , 0x6502feca , 0x6502feca , 0x4b000e66 , 0x4b000e66 }, + { 0x0000a548 , 0x6b02ff4a , 0x6b02ff4a , 0x4d001645 , 0x4d001645 }, + { 0x0000a54c , 0x7203feca , 0x7203feca , 0x51001865 , 0x51001865 }, + { 0x0000a550 , 0x7703ff0b , 0x7703ff0b , 0x55001a86 , 0x55001a86 }, + { 0x0000a554 , 0x7d06ffcb , 0x7d06ffcb , 0x57001ce9 , 0x57001ce9 }, + { 0x0000a558 , 0x8407ff0b , 0x8407ff0b , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a55c , 0x8907ffcb , 0x8907ffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a560 , 0x900fff0b , 0x900fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a564 , 0x960fffcb , 0x960fffcb , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a568 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a56c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a570 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a574 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a578 , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000a57c , 0x9c1fff0b , 0x9c1fff0b , 0x5e001eeb , 0x5e001eeb }, + { 0x0000b500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b504 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b508 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b50c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b510 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b514 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b518 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b51c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b520 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b524 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b528 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b52c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b530 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b534 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b538 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b53c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b540 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b544 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b548 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b54c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b550 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b554 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b558 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b55c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b560 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b564 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b568 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b56c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b570 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b574 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b578 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000b57c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00016044 , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db , 0x05d6b2db }, + { 0x00016048 , 0x6c924260 , 0x6c924260 , 0x6c924260 , 0x6c924260 }, +}; + +static const u_int32_t ar9485_fast_clock_poseidon1_1_baseband_postamble[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00009e00 , 0x03721821 , 0x03721821 }, + { 0x0000a230 , 0x0000400b , 0x00004016 }, + { 0x0000a254 , 0x00000898 , 0x00001130 }, +}; + +static const u_int32_t ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x18012e5e }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0000080c }, +}; + +static const u_int32_t ar9485_common_rx_gain_poseidon1_1[][2] = { +/* Addr allmodes */ + { 0x00009e44 , 0x02182324 }, + { 0x0000a000 , 0x00060005 }, + { 0x0000a004 , 0x00810080 }, + { 0x0000a008 , 0x00830082 }, + { 0x0000a00c , 0x00850084 }, + { 0x0000a010 , 0x01820181 }, + { 0x0000a014 , 0x01840183 }, + { 0x0000a018 , 0x01880185 }, + { 0x0000a01c , 0x018a0189 }, + { 0x0000a020 , 0x02850284 }, + { 0x0000a024 , 0x02890288 }, + { 0x0000a028 , 0x028b028a }, + { 0x0000a02c , 0x03850384 }, + { 0x0000a030 , 0x03890388 }, + { 0x0000a034 , 0x038b038a }, + { 0x0000a038 , 0x038d038c }, + { 0x0000a03c , 0x03910390 }, + { 0x0000a040 , 0x03930392 }, + { 0x0000a044 , 0x03950394 }, + { 0x0000a048 , 0x00000396 }, + { 0x0000a04c , 0x00000000 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x18181818 }, + { 0x0000a084 , 0x18181818 }, + { 0x0000a088 , 0x18181818 }, + { 0x0000a08c , 0x18181818 }, + { 0x0000a090 , 0x18181818 }, + { 0x0000a094 , 0x18181818 }, + { 0x0000a098 , 0x17181818 }, + { 0x0000a09c , 0x02020b0b }, + { 0x0000a0a0 , 0x02020202 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x22072208 }, + { 0x0000a0c4 , 0x22052206 }, + { 0x0000a0c8 , 0x22032204 }, + { 0x0000a0cc , 0x22012202 }, + { 0x0000a0d0 , 0x221f2200 }, + { 0x0000a0d4 , 0x221d221e }, + { 0x0000a0d8 , 0x33023303 }, + { 0x0000a0dc , 0x33003301 }, + { 0x0000a0e0 , 0x331e331f }, + { 0x0000a0e4 , 0x4402331d }, + { 0x0000a0e8 , 0x44004401 }, + { 0x0000a0ec , 0x441e441f }, + { 0x0000a0f0 , 0x55025503 }, + { 0x0000a0f4 , 0x55005501 }, + { 0x0000a0f8 , 0x551e551f }, + { 0x0000a0fc , 0x6602551d }, + { 0x0000a100 , 0x66006601 }, + { 0x0000a104 , 0x661e661f }, + { 0x0000a108 , 0x7703661d }, + { 0x0000a10c , 0x77017702 }, + { 0x0000a110 , 0x00007700 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x111f1100 }, + { 0x0000a148 , 0x111d111e }, + { 0x0000a14c , 0x111b111c }, + { 0x0000a150 , 0x22032204 }, + { 0x0000a154 , 0x22012202 }, + { 0x0000a158 , 0x221f2200 }, + { 0x0000a15c , 0x221d221e }, + { 0x0000a160 , 0x33013302 }, + { 0x0000a164 , 0x331f3300 }, + { 0x0000a168 , 0x4402331e }, + { 0x0000a16c , 0x44004401 }, + { 0x0000a170 , 0x441e441f }, + { 0x0000a174 , 0x55015502 }, + { 0x0000a178 , 0x551f5500 }, + { 0x0000a17c , 0x6602551e }, + { 0x0000a180 , 0x66006601 }, + { 0x0000a184 , 0x661e661f }, + { 0x0000a188 , 0x7703661d }, + { 0x0000a18c , 0x77017702 }, + { 0x0000a190 , 0x00007700 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000296 }, +}; + +static const u_int32_t ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1[][2] = { +/* Addr allmodes */ + { 0x00018c00 , 0x18053e5e }, + { 0x00018c04 , 0x000801d8 }, + { 0x00018c08 , 0x0000080c }, +}; + +static const u_int32_t ar9485_common_wo_xlna_rx_gain_poseidon1_1[][2] = { +/* Addr allmodes */ + { 0x00009e44 , 0x02282324 }, + { 0x0000a000 , 0x00060005 }, + { 0x0000a004 , 0x00810080 }, + { 0x0000a008 , 0x00830082 }, + { 0x0000a00c , 0x00850084 }, + { 0x0000a010 , 0x01820181 }, + { 0x0000a014 , 0x01840183 }, + { 0x0000a018 , 0x01880185 }, + { 0x0000a01c , 0x018a0189 }, + { 0x0000a020 , 0x02850284 }, + { 0x0000a024 , 0x02890288 }, + { 0x0000a028 , 0x028b028a }, + { 0x0000a02c , 0x03850384 }, + { 0x0000a030 , 0x03890388 }, + { 0x0000a034 , 0x038b038a }, + { 0x0000a038 , 0x038d038c }, + { 0x0000a03c , 0x03910390 }, + { 0x0000a040 , 0x03930392 }, + { 0x0000a044 , 0x03950394 }, + { 0x0000a048 , 0x00000396 }, + { 0x0000a04c , 0x00000000 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x28282828 }, + { 0x0000a084 , 0x28282828 }, + { 0x0000a088 , 0x28282828 }, + { 0x0000a08c , 0x28282828 }, + { 0x0000a090 , 0x28282828 }, + { 0x0000a094 , 0x24242428 }, + { 0x0000a098 , 0x171e1e1e }, + { 0x0000a09c , 0x02020b0b }, + { 0x0000a0a0 , 0x02020202 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x22072208 }, + { 0x0000a0c4 , 0x22052206 }, + { 0x0000a0c8 , 0x22032204 }, + { 0x0000a0cc , 0x22012202 }, + { 0x0000a0d0 , 0x221f2200 }, + { 0x0000a0d4 , 0x221d221e }, + { 0x0000a0d8 , 0x33023303 }, + { 0x0000a0dc , 0x33003301 }, + { 0x0000a0e0 , 0x331e331f }, + { 0x0000a0e4 , 0x4402331d }, + { 0x0000a0e8 , 0x44004401 }, + { 0x0000a0ec , 0x441e441f }, + { 0x0000a0f0 , 0x55025503 }, + { 0x0000a0f4 , 0x55005501 }, + { 0x0000a0f8 , 0x551e551f }, + { 0x0000a0fc , 0x6602551d }, + { 0x0000a100 , 0x66006601 }, + { 0x0000a104 , 0x661e661f }, + { 0x0000a108 , 0x7703661d }, + { 0x0000a10c , 0x77017702 }, + { 0x0000a110 , 0x00007700 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x111f1100 }, + { 0x0000a148 , 0x111d111e }, + { 0x0000a14c , 0x111b111c }, + { 0x0000a150 , 0x22032204 }, + { 0x0000a154 , 0x22012202 }, + { 0x0000a158 , 0x221f2200 }, + { 0x0000a15c , 0x221d221e }, + { 0x0000a160 , 0x33013302 }, + { 0x0000a164 , 0x331f3300 }, + { 0x0000a168 , 0x4402331e }, + { 0x0000a16c , 0x44004401 }, + { 0x0000a170 , 0x441e441f }, + { 0x0000a174 , 0x55015502 }, + { 0x0000a178 , 0x551f5500 }, + { 0x0000a17c , 0x6602551e }, + { 0x0000a180 , 0x66006601 }, + { 0x0000a184 , 0x661e661f }, + { 0x0000a188 , 0x7703661d }, + { 0x0000a18c , 0x77017702 }, + { 0x0000a190 , 0x00007700 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000296 }, +}; + diff --git a/hal/ar9300/ar955x.ini b/hal/ar9300/ar955x.ini new file mode 100644 index 000000000000..ee3b35bd5a8c --- /dev/null +++ b/hal/ar9300/ar955x.ini @@ -0,0 +1,1684 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#define INI_VERSION_AR955X "$Id: //depot/sw/qca_main/drivers/wlan_modules/hal/ar9300/ar955x.ini#2 $" +static const u_int32_t ar955x_scorpion_1p0_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e3c , 0xcfa10821 , 0xcfa10821 , 0xcfa10821 , 0xcfa10821 }, + { 0x00009e44 , 0x005c0000 , 0x005c0000 , 0x005c0000 , 0x005c0000 }, + { 0x0000a258 , 0x02020200 , 0x02020200 , 0x02020200 , 0x02020200 }, + { 0x0000a25c , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a28c , 0x00011111 , 0x00011111 , 0x00011111 , 0x00011111 }, + { 0x0000a2c4 , 0x00148d18 , 0x00148d18 , 0x00148d20 , 0x00148d20 }, + { 0x0000a2d8 , 0xf999a801 , 0xf999a801 , 0xf999a80d , 0xf999a80d }, + { 0x0000a50c , 0x0000c00a , 0x0000c00a , 0x0000c00a , 0x0000c00a }, + { 0x0000a538 , 0x00038e8c , 0x00038e8c , 0x00038e8c , 0x00038e8c }, + { 0x0000a53c , 0x0003cecc , 0x0003cecc , 0x0003cecc , 0x0003cecc }, + { 0x0000a540 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 }, + { 0x0000a544 , 0x00044edc , 0x00044edc , 0x00044edc , 0x00044edc }, + { 0x0000a548 , 0x00048ede , 0x00048ede , 0x00048ede , 0x00048ede }, + { 0x0000a54c , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e }, + { 0x0000a550 , 0x00050f5e , 0x00050f5e , 0x00050f5e , 0x00050f5e }, + { 0x0000a554 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000a558 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000a55c , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000a560 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000a564 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000a568 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000a56c , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000a570 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000a574 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000a578 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000a57c , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000be18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +}; + +static const u_int32_t ar955x_scorpion_1p0_radio_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00016098 , 0xd2dd5554 , 0xd2dd5554 , 0xd28b3330 , 0xd28b3330 }, + { 0x0001609c , 0x0a566f3a , 0x0a566f3a , 0x0a566f3a , 0x0a566f3a }, + { 0x000160ac , 0xa4647c00 , 0xa4647c00 , 0x24647c00 , 0x24647c00 }, + { 0x000160b0 , 0x01885f52 , 0x01885f52 , 0x01885f52 , 0x01885f52 }, + { 0x00016104 , 0xb7a00000 , 0xb7a00000 , 0xb7a00001 , 0xb7a00001 }, + { 0x0001610c , 0xc0000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016140 , 0x10804008 , 0x10804008 , 0x10804008 , 0x10804008 }, + { 0x00016504 , 0xb7a00000 , 0xb7a00000 , 0xb7a00001 , 0xb7a00001 }, + { 0x0001650c , 0xc0000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016540 , 0x10804008 , 0x10804008 , 0x10804008 , 0x10804008 }, + { 0x00016904 , 0xb7a00000 , 0xb7a00000 , 0xb7a00001 , 0xb7a00001 }, + { 0x0001690c , 0xc0000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016940 , 0x10804008 , 0x10804008 , 0x10804008 , 0x10804008 }, +}; + +static const u_int32_t ar955x_scorpion_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { +/* Addr allmodes */ + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x6f7f0301 }, + { 0x0000a3a0 , 0xca9228ee }, +}; + +static const u_int32_t ar955x_scorpion_1p0_baseband_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8011 , 0xd00a8011 }, + { 0x00009820 , 0x206a022e , 0x206a022e , 0x206a012e , 0x206a012e }, + { 0x00009824 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 }, + { 0x00009828 , 0x06903081 , 0x06903081 , 0x06903881 , 0x06903881 }, + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000119c , 0x0000119c }, + { 0x00009c00 , 0x000000c4 , 0x000000c4 , 0x000000c4 , 0x000000c4 }, + { 0x00009e00 , 0x0372111a , 0x0372111a , 0x037216a0 , 0x037216a0 }, + { 0x00009e04 , 0x001c2020 , 0x001c2020 , 0x001c2020 , 0x001c2020 }, + { 0x00009e0c , 0x6c4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + { 0x00009e10 , 0x7ec88d2e , 0x7ec88d2e , 0x7ec84d2e , 0x7ec84d2e }, + { 0x00009e14 , 0x37b95d5e , 0x37b9605e , 0x3379605e , 0x33795d5e }, + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + { 0x00009e2c , 0x0000001c , 0x0000001c , 0x00000021 , 0x00000021 }, + { 0x00009e3c , 0xcfa10820 , 0xcfa10820 , 0xcfa10822 , 0xcfa10822 }, + { 0x00009e44 , 0xfe321e27 , 0xfe321e27 , 0xfe291e27 , 0xfe291e27 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302012 , 0x50302012 }, + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, + { 0x0000a204 , 0x005c0ec0 , 0x005c0ec4 , 0x005c0ec4 , 0x005c0ec0 }, + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + { 0x0000a22c , 0x07e26a2f , 0x07e26a2f , 0x01026a2f , 0x01026a2f }, + { 0x0000a230 , 0x0000400a , 0x00004014 , 0x00004016 , 0x0000400b }, + { 0x0000a234 , 0x00000fff , 0x10000fff , 0x10000fff , 0x00000fff }, + { 0x0000a238 , 0xffb01018 , 0xffb01018 , 0xffb01018 , 0xffb01018 }, + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01010e0e , 0x01010e0e }, + { 0x0000a260 , 0x0a021501 , 0x0a021501 , 0x3a021501 , 0x3a021501 }, + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x00000010 , 0x00000010 }, + { 0x0000a288 , 0x00000110 , 0x00000110 , 0x00000110 , 0x00000110 }, + { 0x0000a28c , 0x00022222 , 0x00022222 , 0x00022222 , 0x00022222 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2cc , 0x18c50033 , 0x18c43433 , 0x18c41033 , 0x18c44c33 }, + { 0x0000a2d0 , 0x00041982 , 0x00041982 , 0x00041982 , 0x00041982 }, + { 0x0000a2d8 , 0x7999a83b , 0x7999a83b , 0x7999a83b , 0x7999a83b }, + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a830 , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae04 , 0x001c0000 , 0x001c0000 , 0x001c0000 , 0x001c0000 }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000ae1c , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae20 , 0x000001b5 , 0x000001b5 , 0x000001ce , 0x000001ce }, + { 0x0000b284 , 0x00000000 , 0x00000000 , 0x00000010 , 0x00000010 }, + { 0x0000b830 , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000be04 , 0x001c0000 , 0x001c0000 , 0x001c0000 , 0x001c0000 }, + { 0x0000be18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000be1c , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000be20 , 0x000001b5 , 0x000001b5 , 0x000001ce , 0x000001ce }, + { 0x0000c284 , 0x00000000 , 0x00000000 , 0x00000010 , 0x00000010 }, +}; + +static const u_int32_t ar955x_scorpion_1p0_radio_core[][2] = { +/* Addr allmodes */ + { 0x00016000 , 0x36db6db6 }, + { 0x00016004 , 0x6db6db40 }, + { 0x00016008 , 0x73f00000 }, + { 0x0001600c , 0x00000000 }, + { 0x00016040 , 0x7f80fff8 }, + { 0x0001604c , 0x76d005b5 }, + { 0x00016050 , 0x557cf031 }, + { 0x00016054 , 0x13449440 }, + { 0x00016058 , 0x0c51c92c }, + { 0x0001605c , 0x3db7fffc }, + { 0x00016060 , 0xfffffffc }, + { 0x00016064 , 0x000f0278 }, + { 0x00016068 , 0x6db6db6c }, + { 0x0001606c , 0x6db60000 }, + { 0x00016080 , 0x00080000 }, + { 0x00016084 , 0x0e48048c }, + { 0x00016088 , 0x14214514 }, + { 0x0001608c , 0x119f101e }, + { 0x00016090 , 0x24926490 }, + { 0x00016094 , 0x00000000 }, + { 0x000160a0 , 0x0a108ffe }, + { 0x000160a4 , 0x812fc370 }, + { 0x000160a8 , 0x423c8100 }, + { 0x000160b4 , 0x92480080 }, + { 0x000160c0 , 0x006db6d0 }, + { 0x000160c4 , 0x6db6db60 }, + { 0x000160c8 , 0x6db6db6c }, + { 0x000160cc , 0x01e6c000 }, + { 0x00016100 , 0x11999601 }, + { 0x00016108 , 0x00080010 }, + { 0x00016144 , 0x02084080 }, + { 0x00016148 , 0x00008040 }, + { 0x00016280 , 0x01800804 }, + { 0x00016284 , 0x00038dc5 }, + { 0x00016288 , 0x00000000 }, + { 0x0001628c , 0x00000040 }, + { 0x00016380 , 0x00000000 }, + { 0x00016384 , 0x00000000 }, + { 0x00016388 , 0x00400705 }, + { 0x0001638c , 0x00800700 }, + { 0x00016390 , 0x00800700 }, + { 0x00016394 , 0x00000000 }, + { 0x00016398 , 0x00000000 }, + { 0x0001639c , 0x00000000 }, + { 0x000163a0 , 0x00000001 }, + { 0x000163a4 , 0x00000001 }, + { 0x000163a8 , 0x00000000 }, + { 0x000163ac , 0x00000000 }, + { 0x000163b0 , 0x00000000 }, + { 0x000163b4 , 0x00000000 }, + { 0x000163b8 , 0x00000000 }, + { 0x000163bc , 0x00000000 }, + { 0x000163c0 , 0x000000a0 }, + { 0x000163c4 , 0x000c0000 }, + { 0x000163c8 , 0x14021402 }, + { 0x000163cc , 0x00001402 }, + { 0x000163d0 , 0x00000000 }, + { 0x000163d4 , 0x00000000 }, + { 0x00016400 , 0x36db6db6 }, + { 0x00016404 , 0x6db6db40 }, + { 0x00016408 , 0x73f00000 }, + { 0x0001640c , 0x00000000 }, + { 0x00016440 , 0x7f80fff8 }, + { 0x0001644c , 0x76d005b5 }, + { 0x00016450 , 0x557cf031 }, + { 0x00016454 , 0x13449440 }, + { 0x00016458 , 0x0c51c92c }, + { 0x0001645c , 0x3db7fffc }, + { 0x00016460 , 0xfffffffc }, + { 0x00016464 , 0x000f0278 }, + { 0x00016468 , 0x6db6db6c }, + { 0x0001646c , 0x6db60000 }, + { 0x00016500 , 0x11999601 }, + { 0x00016508 , 0x00080010 }, + { 0x00016544 , 0x02084080 }, + { 0x00016548 , 0x00008040 }, + { 0x00016780 , 0x00000000 }, + { 0x00016784 , 0x00000000 }, + { 0x00016788 , 0x00400705 }, + { 0x0001678c , 0x00800700 }, + { 0x00016790 , 0x00800700 }, + { 0x00016794 , 0x00000000 }, + { 0x00016798 , 0x00000000 }, + { 0x0001679c , 0x00000000 }, + { 0x000167a0 , 0x00000001 }, + { 0x000167a4 , 0x00000001 }, + { 0x000167a8 , 0x00000000 }, + { 0x000167ac , 0x00000000 }, + { 0x000167b0 , 0x00000000 }, + { 0x000167b4 , 0x00000000 }, + { 0x000167b8 , 0x00000000 }, + { 0x000167bc , 0x00000000 }, + { 0x000167c0 , 0x000000a0 }, + { 0x000167c4 , 0x000c0000 }, + { 0x000167c8 , 0x14021402 }, + { 0x000167cc , 0x00001402 }, + { 0x000167d0 , 0x00000000 }, + { 0x000167d4 , 0x00000000 }, + { 0x00016800 , 0x36db6db6 }, + { 0x00016804 , 0x6db6db40 }, + { 0x00016808 , 0x73f00000 }, + { 0x0001680c , 0x00000000 }, + { 0x00016840 , 0x7f80fff8 }, + { 0x0001684c , 0x76d005b5 }, + { 0x00016850 , 0x557cf031 }, + { 0x00016854 , 0x13449440 }, + { 0x00016858 , 0x0c51c92c }, + { 0x0001685c , 0x3db7fffc }, + { 0x00016860 , 0xfffffffc }, + { 0x00016864 , 0x000f0278 }, + { 0x00016868 , 0x6db6db6c }, + { 0x0001686c , 0x6db60000 }, + { 0x00016900 , 0x11999601 }, + { 0x00016908 , 0x00080010 }, + { 0x00016944 , 0x02084080 }, + { 0x00016948 , 0x00008040 }, + { 0x00016b80 , 0x00000000 }, + { 0x00016b84 , 0x00000000 }, + { 0x00016b88 , 0x00400705 }, + { 0x00016b8c , 0x00800700 }, + { 0x00016b90 , 0x00800700 }, + { 0x00016b94 , 0x00000000 }, + { 0x00016b98 , 0x00000000 }, + { 0x00016b9c , 0x00000000 }, + { 0x00016ba0 , 0x00000001 }, + { 0x00016ba4 , 0x00000001 }, + { 0x00016ba8 , 0x00000000 }, + { 0x00016bac , 0x00000000 }, + { 0x00016bb0 , 0x00000000 }, + { 0x00016bb4 , 0x00000000 }, + { 0x00016bb8 , 0x00000000 }, + { 0x00016bbc , 0x00000000 }, + { 0x00016bc0 , 0x000000a0 }, + { 0x00016bc4 , 0x000c0000 }, + { 0x00016bc8 , 0x14021402 }, + { 0x00016bcc , 0x00001402 }, + { 0x00016bd0 , 0x00000000 }, + { 0x00016bd4 , 0x00000000 }, +}; + +static const u_int32_t ar955xModes_xpa_tx_gain_table_scorpion_1p0[][9] = { +/* Addr 5G_low_HT20 5G_low_HT40 5G_medium_HT20 5G_medium_HT40 5G_high_HT20 5G_high_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xfffd5aaa , 0xfffd5aaa }, + { 0x0000a2e0 , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffe9ccc , 0xfffe9ccc }, + { 0x0000a2e4 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffffe0f0 , 0xffffe0f0 }, + { 0x0000a2e8 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xfffcff00 , 0xfffcff00 }, + { 0x0000a410 , 0x000050de , 0x000050de , 0x000050de , 0x000050de , 0x000050de , 0x000050de , 0x000050da , 0x000050da }, + { 0x0000a500 , 0x00000003 , 0x00000003 , 0x00000003 , 0x00000003 , 0x00000003 , 0x00000003 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x04000005 , 0x04000005 , 0x04000005 , 0x04000005 , 0x04000005 , 0x04000005 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x08000009 , 0x08000009 , 0x08000009 , 0x08000009 , 0x08000009 , 0x08000009 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x0c00000b , 0x0c00000b , 0x0c00000b , 0x0c00000b , 0x0c00000b , 0x0c00000b , 0x0c000006 , 0x0c000006 }, + { 0x0000a510 , 0x1000000d , 0x1000000d , 0x1000000d , 0x1000000d , 0x1000000d , 0x1000000d , 0x0f00000a , 0x0f00000a }, + { 0x0000a514 , 0x14000011 , 0x14000011 , 0x14000011 , 0x14000011 , 0x14000011 , 0x14000011 , 0x1300000c , 0x1300000c }, + { 0x0000a518 , 0x1700002b , 0x1700002b , 0x1700002b , 0x1700002b , 0x1600002b , 0x1600002b , 0x1700000e , 0x1700000e }, + { 0x0000a51c , 0x1b00002d , 0x1b00002d , 0x1b00002d , 0x1b00002d , 0x1a00002d , 0x1a00002d , 0x1b000064 , 0x1b000064 }, + { 0x0000a520 , 0x20000031 , 0x20000031 , 0x1f000031 , 0x1f000031 , 0x1e000031 , 0x1e000031 , 0x1f000242 , 0x1f000242 }, + { 0x0000a524 , 0x24000051 , 0x24000051 , 0x23000051 , 0x23000051 , 0x23000051 , 0x23000051 , 0x23000229 , 0x23000229 }, + { 0x0000a528 , 0x27000071 , 0x27000071 , 0x27000071 , 0x27000071 , 0x26000071 , 0x26000071 , 0x270002a2 , 0x270002a2 }, + { 0x0000a52c , 0x2b000092 , 0x2b000092 , 0x2b000092 , 0x2b000092 , 0x2b000092 , 0x2b000092 , 0x2c001203 , 0x2c001203 }, + { 0x0000a530 , 0x3000028c , 0x3000028c , 0x2f00028c , 0x2f00028c , 0x2e00028c , 0x2e00028c , 0x30001803 , 0x30001803 }, + { 0x0000a534 , 0x34000290 , 0x34000290 , 0x33000290 , 0x33000290 , 0x32000290 , 0x32000290 , 0x33000881 , 0x33000881 }, + { 0x0000a538 , 0x37000292 , 0x37000292 , 0x36000292 , 0x36000292 , 0x35000292 , 0x35000292 , 0x38001809 , 0x38001809 }, + { 0x0000a53c , 0x3b02028d , 0x3b02028d , 0x3a02028d , 0x3a02028d , 0x3902028d , 0x3902028d , 0x3a000814 , 0x3a000814 }, + { 0x0000a540 , 0x3f020291 , 0x3f020291 , 0x3e020291 , 0x3e020291 , 0x3d020291 , 0x3d020291 , 0x3f001a0c , 0x3f001a0c }, + { 0x0000a544 , 0x44020490 , 0x44020490 , 0x43020490 , 0x43020490 , 0x42020490 , 0x42020490 , 0x43001a0e , 0x43001a0e }, + { 0x0000a548 , 0x48020492 , 0x48020492 , 0x47020492 , 0x47020492 , 0x46020492 , 0x46020492 , 0x46001812 , 0x46001812 }, + { 0x0000a54c , 0x4c020692 , 0x4c020692 , 0x4b020692 , 0x4b020692 , 0x4a020692 , 0x4a020692 , 0x49001884 , 0x49001884 }, + { 0x0000a550 , 0x50020892 , 0x50020892 , 0x4f020892 , 0x4f020892 , 0x4e020892 , 0x4e020892 , 0x4d001e84 , 0x4d001e84 }, + { 0x0000a554 , 0x53040891 , 0x53040891 , 0x53040891 , 0x53040891 , 0x52040891 , 0x52040891 , 0x50001e69 , 0x50001e69 }, + { 0x0000a558 , 0x58040893 , 0x58040893 , 0x57040893 , 0x57040893 , 0x56040893 , 0x56040893 , 0x550006f4 , 0x550006f4 }, + { 0x0000a55c , 0x5c0408b4 , 0x5c0408b4 , 0x5a0408b4 , 0x5a0408b4 , 0x5a0408b4 , 0x5a0408b4 , 0x59000ad3 , 0x59000ad3 }, + { 0x0000a560 , 0x610408b6 , 0x610408b6 , 0x5e0408b6 , 0x5e0408b6 , 0x5e0408b6 , 0x5e0408b6 , 0x5e000ad5 , 0x5e000ad5 }, + { 0x0000a564 , 0x670408f6 , 0x670408f6 , 0x620408f6 , 0x620408f6 , 0x620408f6 , 0x620408f6 , 0x61001ced , 0x61001ced }, + { 0x0000a568 , 0x6a040cf6 , 0x6a040cf6 , 0x66040cf6 , 0x66040cf6 , 0x66040cf6 , 0x66040cf6 , 0x660018d4 , 0x660018d4 }, + { 0x0000a56c , 0x6d040d76 , 0x6d040d76 , 0x6a040d76 , 0x6a040d76 , 0x6a040d76 , 0x6a040d76 , 0x660018d4 , 0x660018d4 }, + { 0x0000a570 , 0x70060db6 , 0x70060db6 , 0x6e060db6 , 0x6e060db6 , 0x6e060db6 , 0x6e060db6 , 0x660018d4 , 0x660018d4 }, + { 0x0000a574 , 0x730a0df6 , 0x730a0df6 , 0x720a0df6 , 0x720a0df6 , 0x720a0df6 , 0x720a0df6 , 0x660018d4 , 0x660018d4 }, + { 0x0000a578 , 0x770a13f6 , 0x770a13f6 , 0x760a13f6 , 0x760a13f6 , 0x760a13f6 , 0x760a13f6 , 0x660018d4 , 0x660018d4 }, + { 0x0000a57c , 0x770a13f6 , 0x770a13f6 , 0x760a13f6 , 0x760a13f6 , 0x760a13f6 , 0x760a13f6 , 0x660018d4 , 0x660018d4 }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x02c04b01 , 0x02c04b01 , 0x02c04b01 , 0x02c04b01 , 0x02c04b01 , 0x02c04b01 , 0x03804000 , 0x03804000 }, + { 0x0000a610 , 0x04008b01 , 0x04008b01 , 0x04008b01 , 0x04008b01 , 0x03c08b01 , 0x03c08b01 , 0x0300ca02 , 0x0300ca02 }, + { 0x0000a614 , 0x05811403 , 0x05811403 , 0x05411303 , 0x05411303 , 0x05411303 , 0x05411303 , 0x00000e04 , 0x00000e04 }, + { 0x0000a618 , 0x05811604 , 0x05811604 , 0x05411504 , 0x05411504 , 0x05411504 , 0x05411504 , 0x03014000 , 0x03014000 }, + { 0x0000a61c , 0x05811604 , 0x05811604 , 0x05411504 , 0x05411504 , 0x05411504 , 0x05411504 , 0x00000000 , 0x00000000 }, + { 0x0000a620 , 0x05811604 , 0x05811604 , 0x05411504 , 0x05411504 , 0x05411504 , 0x05411504 , 0x00000000 , 0x00000000 }, + { 0x0000a624 , 0x05811604 , 0x05811604 , 0x05411504 , 0x05411504 , 0x05411504 , 0x05411504 , 0x03014000 , 0x03014000 }, + { 0x0000a628 , 0x05811604 , 0x05811604 , 0x05411504 , 0x05411504 , 0x05411504 , 0x05411504 , 0x03804c05 , 0x03804c05 }, + { 0x0000a62c , 0x06815604 , 0x06815604 , 0x06415504 , 0x06415504 , 0x06015504 , 0x06015504 , 0x0701de06 , 0x0701de06 }, + { 0x0000a630 , 0x07819a05 , 0x07819a05 , 0x07419905 , 0x07419905 , 0x07019805 , 0x07019805 , 0x07819c07 , 0x07819c07 }, + { 0x0000a634 , 0x07819e06 , 0x07819e06 , 0x07419d06 , 0x07419d06 , 0x07019C06 , 0x07019C06 , 0x0701dc07 , 0x0701dc07 }, + { 0x0000a638 , 0x07819e06 , 0x07819e06 , 0x07419d06 , 0x07419d06 , 0x07019C06 , 0x07019C06 , 0x0701dc07 , 0x0701dc07 }, + { 0x0000a63c , 0x07819e06 , 0x07819e06 , 0x07419d06 , 0x07419d06 , 0x07019C06 , 0x07019C06 , 0x0701dc07 , 0x0701dc07 }, + { 0x0000b2dc , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xfffd5aaa , 0xfffd5aaa }, + { 0x0000b2e0 , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffe9ccc , 0xfffe9ccc }, + { 0x0000b2e4 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffffe0f0 , 0xffffe0f0 }, + { 0x0000b2e8 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xfffcff00 , 0xfffcff00 }, + { 0x0000c2dc , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xffff6aaa , 0xfffd5aaa , 0xfffd5aaa }, + { 0x0000c2e0 , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffdcccc , 0xfffe9ccc , 0xfffe9ccc }, + { 0x0000c2e4 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffe3b0f0 , 0xffffe0f0 , 0xffffe0f0 }, + { 0x0000c2e8 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xffffff00 , 0xfffcff00 , 0xfffcff00 }, + { 0x00016044 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x010002d4 , 0x010002d4 }, + { 0x00016048 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 }, + { 0x00016280 , 0x01801e84 , 0x01801e84 , 0x01801e84 , 0x01801e84 , 0x01801e84 , 0x01801e84 , 0x01808e84 , 0x01808e84 }, + { 0x00016444 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x010002d4 , 0x010002d4 }, + { 0x00016448 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 }, + { 0x00016844 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x010002d4 , 0x010002d4 }, + { 0x00016848 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 }, +}; + +static const u_int32_t ar955x_scorpion_1p0_mac_core[][2] = { +/* Addr allmodes */ + { 0x00000008 , 0x00000000 }, + { 0x00000030 , 0x00020085 }, + { 0x00000034 , 0x00000005 }, + { 0x00000040 , 0x00000000 }, + { 0x00000044 , 0x00000000 }, + { 0x00000048 , 0x00000008 }, + { 0x0000004c , 0x00000010 }, + { 0x00000050 , 0x00000000 }, + { 0x00001040 , 0x002ffc0f }, + { 0x00001044 , 0x002ffc0f }, + { 0x00001048 , 0x002ffc0f }, + { 0x0000104c , 0x002ffc0f }, + { 0x00001050 , 0x002ffc0f }, + { 0x00001054 , 0x002ffc0f }, + { 0x00001058 , 0x002ffc0f }, + { 0x0000105c , 0x002ffc0f }, + { 0x00001060 , 0x002ffc0f }, + { 0x00001064 , 0x002ffc0f }, + { 0x000010f0 , 0x00000100 }, + { 0x00001270 , 0x00000000 }, + { 0x000012b0 , 0x00000000 }, + { 0x000012f0 , 0x00000000 }, + { 0x0000143c , 0x00000000 }, + { 0x0000147c , 0x00000000 }, + { 0x00008000 , 0x00000000 }, + { 0x00008004 , 0x00000000 }, + { 0x00008008 , 0x00000000 }, + { 0x0000800c , 0x00000000 }, + { 0x00008018 , 0x00000000 }, + { 0x00008020 , 0x00000000 }, + { 0x00008038 , 0x00000000 }, + { 0x0000803c , 0x00000000 }, + { 0x00008040 , 0x00000000 }, + { 0x00008044 , 0x00000000 }, + { 0x00008048 , 0x00000000 }, + { 0x0000804c , 0xffffffff }, + { 0x00008054 , 0x00000000 }, + { 0x00008058 , 0x00000000 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008060 , 0x0000000f }, + { 0x00008064 , 0x00000000 }, + { 0x00008070 , 0x00000310 }, + { 0x00008074 , 0x00000020 }, + { 0x00008078 , 0x00000000 }, + { 0x0000809c , 0x0000000f }, + { 0x000080a0 , 0x00000000 }, + { 0x000080a4 , 0x02ff0000 }, + { 0x000080a8 , 0x0e070605 }, + { 0x000080ac , 0x0000000d }, + { 0x000080b0 , 0x00000000 }, + { 0x000080b4 , 0x00000000 }, + { 0x000080b8 , 0x00000000 }, + { 0x000080bc , 0x00000000 }, + { 0x000080c0 , 0x2a800000 }, + { 0x000080c4 , 0x06900168 }, + { 0x000080c8 , 0x13881c22 }, + { 0x000080cc , 0x01f40000 }, + { 0x000080d0 , 0x00252500 }, + { 0x000080d4 , 0x00a00000 }, + { 0x000080d8 , 0x00400000 }, + { 0x000080dc , 0x00000000 }, + { 0x000080e0 , 0xffffffff }, + { 0x000080e4 , 0x0000ffff }, + { 0x000080e8 , 0x3f3f3f3f }, + { 0x000080ec , 0x00000000 }, + { 0x000080f0 , 0x00000000 }, + { 0x000080f4 , 0x00000000 }, + { 0x000080fc , 0x00020000 }, + { 0x00008100 , 0x00000000 }, + { 0x00008108 , 0x00000052 }, + { 0x0000810c , 0x00000000 }, + { 0x00008110 , 0x00000000 }, + { 0x00008114 , 0x000007ff }, + { 0x00008118 , 0x000000aa }, + { 0x0000811c , 0x00003210 }, + { 0x00008124 , 0x00000000 }, + { 0x00008128 , 0x00000000 }, + { 0x0000812c , 0x00000000 }, + { 0x00008130 , 0x00000000 }, + { 0x00008134 , 0x00000000 }, + { 0x00008138 , 0x00000000 }, + { 0x0000813c , 0x0000ffff }, + { 0x00008140 , 0x000000fe }, + { 0x00008144 , 0xffffffff }, + { 0x00008168 , 0x00000000 }, + { 0x0000816c , 0x00000000 }, + { 0x000081c0 , 0x00000000 }, + { 0x000081c4 , 0x33332210 }, + { 0x000081ec , 0x00000000 }, + { 0x000081f0 , 0x00000000 }, + { 0x000081f4 , 0x00000000 }, + { 0x000081f8 , 0x00000000 }, + { 0x000081fc , 0x00000000 }, + { 0x00008240 , 0x00100000 }, + { 0x00008244 , 0x0010f400 }, + { 0x00008248 , 0x00000800 }, + { 0x0000824c , 0x0001e800 }, + { 0x00008250 , 0x00000000 }, + { 0x00008254 , 0x00000000 }, + { 0x00008258 , 0x00000000 }, + { 0x0000825c , 0x40000000 }, + { 0x00008260 , 0x00080922 }, + { 0x00008264 , 0x9d400010 }, + { 0x00008268 , 0xffffffff }, + { 0x0000826c , 0x0000ffff }, + { 0x00008270 , 0x00000000 }, + { 0x00008274 , 0x40000000 }, + { 0x00008278 , 0x003e4180 }, + { 0x0000827c , 0x00000004 }, + { 0x00008284 , 0x0000002c }, + { 0x00008288 , 0x0000002c }, + { 0x0000828c , 0x000000ff }, + { 0x00008294 , 0x00000000 }, + { 0x00008298 , 0x00000000 }, + { 0x0000829c , 0x00000000 }, + { 0x00008300 , 0x00001d40 }, + { 0x00008314 , 0x00000000 }, + { 0x0000831c , 0x0000010d }, + { 0x00008328 , 0x00000000 }, + { 0x0000832c , 0x0000001f }, + { 0x00008330 , 0x00000302 }, + { 0x00008334 , 0x00000700 }, + { 0x00008338 , 0xffff0000 }, + { 0x0000833c , 0x02400000 }, + { 0x00008340 , 0x000107ff }, + { 0x00008344 , 0xaa48107b }, + { 0x00008348 , 0x008f0000 }, + { 0x0000835c , 0x00000000 }, + { 0x00008360 , 0xffffffff }, + { 0x00008364 , 0xffffffff }, + { 0x00008368 , 0x00000000 }, + { 0x00008370 , 0x00000000 }, + { 0x00008374 , 0x000000ff }, + { 0x00008378 , 0x00000000 }, + { 0x0000837c , 0x00000000 }, + { 0x00008380 , 0xffffffff }, + { 0x00008384 , 0xffffffff }, + { 0x00008390 , 0xffffffff }, + { 0x00008394 , 0xffffffff }, + { 0x00008398 , 0x00000000 }, + { 0x0000839c , 0x00000000 }, + { 0x000083a0 , 0x00000000 }, + { 0x000083a4 , 0x0000fa14 }, + { 0x000083a8 , 0x000f0c00 }, + { 0x000083ac , 0x33332210 }, + { 0x000083b0 , 0x33332210 }, + { 0x000083b4 , 0x33332210 }, + { 0x000083b8 , 0x33332210 }, + { 0x000083bc , 0x00000000 }, + { 0x000083c0 , 0x00000000 }, + { 0x000083c4 , 0x00000000 }, + { 0x000083c8 , 0x00000000 }, + { 0x000083cc , 0x00000200 }, + { 0x000083d0 , 0x8c7901ff }, +}; + +static const u_int32_t ar955xCommon_rx_gain_table_scorpion_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x01910190 }, + { 0x0000a030 , 0x01930192 }, + { 0x0000a034 , 0x01950194 }, + { 0x0000a038 , 0x038a0196 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x22222229 }, + { 0x0000a084 , 0x1d1d1d1d }, + { 0x0000a088 , 0x1d1d1d1d }, + { 0x0000a08c , 0x1d1d1d1d }, + { 0x0000a090 , 0x171d1d1d }, + { 0x0000a094 , 0x11111717 }, + { 0x0000a098 , 0x00030311 }, + { 0x0000a09c , 0x00000000 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x23232323 }, + { 0x0000b084 , 0x21232323 }, + { 0x0000b088 , 0x19191c1e }, + { 0x0000b08c , 0x12141417 }, + { 0x0000b090 , 0x07070e0e }, + { 0x0000b094 , 0x03030305 }, + { 0x0000b098 , 0x00000003 }, + { 0x0000b09c , 0x00000000 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar955x_scorpion_1p0_baseband_core[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009804 , 0xfd14e000 }, + { 0x00009808 , 0x9c0a9f6b }, + { 0x0000980c , 0x04900000 }, + { 0x00009814 , 0x0280c00a }, + { 0x00009818 , 0x00000000 }, + { 0x0000981c , 0x00020028 }, + { 0x00009834 , 0x6400a190 }, + { 0x00009838 , 0x0108ecff }, + { 0x0000983c , 0x14000600 }, + { 0x00009880 , 0x201fff00 }, + { 0x00009884 , 0x00001042 }, + { 0x000098a4 , 0x00200400 }, + { 0x000098b0 , 0x32840bbe }, + { 0x000098bc , 0x00000002 }, + { 0x000098d0 , 0x004b6a8e }, + { 0x000098d4 , 0x00000820 }, + { 0x000098dc , 0x00000000 }, + { 0x000098f0 , 0x00000000 }, + { 0x000098f4 , 0x00000000 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009c0c , 0x00000000 }, + { 0x00009c10 , 0x00000000 }, + { 0x00009c14 , 0x00046384 }, + { 0x00009c18 , 0x05b6b440 }, + { 0x00009c1c , 0x00b6b440 }, + { 0x00009d00 , 0xc080a333 }, + { 0x00009d04 , 0x40206c10 }, + { 0x00009d08 , 0x009c4060 }, + { 0x00009d0c , 0x9883800a }, + { 0x00009d10 , 0x01834061 }, + { 0x00009d14 , 0x00c0040b }, + { 0x00009d18 , 0x00000000 }, + { 0x00009e08 , 0x0038230c }, + { 0x00009e24 , 0x990bb515 }, + { 0x00009e28 , 0x0c6f0000 }, + { 0x00009e30 , 0x06336f77 }, + { 0x00009e34 , 0x6af6532f }, + { 0x00009e38 , 0x0cc80c00 }, + { 0x00009e40 , 0x0d261820 }, + { 0x00009e4c , 0x00001004 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009fc0 , 0x813e4788 }, + { 0x00009fc4 , 0x0001efb5 }, + { 0x00009fcc , 0x40000014 }, + { 0x00009fd0 , 0x01193b93 }, + { 0x0000a20c , 0x00000000 }, + { 0x0000a220 , 0x00000000 }, + { 0x0000a224 , 0x00000000 }, + { 0x0000a228 , 0x10002310 }, + { 0x0000a23c , 0x00000000 }, + { 0x0000a244 , 0x0c000000 }, + { 0x0000a248 , 0x00000140 }, + { 0x0000a2a0 , 0x00000007 }, + { 0x0000a2c0 , 0x00000007 }, + { 0x0000a2c8 , 0x00000000 }, + { 0x0000a2d4 , 0x00000000 }, + { 0x0000a2ec , 0x00000000 }, + { 0x0000a2f0 , 0x00000000 }, + { 0x0000a2f4 , 0x00000000 }, + { 0x0000a2f8 , 0x00000000 }, + { 0x0000a344 , 0x00000000 }, + { 0x0000a34c , 0x00000000 }, + { 0x0000a350 , 0x0000a000 }, + { 0x0000a364 , 0x00000000 }, + { 0x0000a370 , 0x00000000 }, + { 0x0000a390 , 0x00000001 }, + { 0x0000a394 , 0x00000444 }, + { 0x0000a398 , 0x1f020503 }, + { 0x0000a39c , 0x29180c03 }, + { 0x0000a3a0 , 0x9a8b6844 }, + { 0x0000a3a4 , 0x00000000 }, + { 0x0000a3a8 , 0xaaaaaaaa }, + { 0x0000a3ac , 0x3c466478 }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a3c8 , 0x20200020 }, + { 0x0000a3cc , 0x20202020 }, + { 0x0000a3d0 , 0x20202020 }, + { 0x0000a3d4 , 0x20202020 }, + { 0x0000a3d8 , 0x20202020 }, + { 0x0000a3dc , 0x20202020 }, + { 0x0000a3e0 , 0x20202020 }, + { 0x0000a3e4 , 0x20202020 }, + { 0x0000a3e8 , 0x20202020 }, + { 0x0000a3ec , 0x20202020 }, + { 0x0000a3f0 , 0x00000000 }, + { 0x0000a3f4 , 0x00000000 }, + { 0x0000a3f8 , 0x0c9bd380 }, + { 0x0000a3fc , 0x000f0f01 }, + { 0x0000a400 , 0x8fa91f01 }, + { 0x0000a404 , 0x00000000 }, + { 0x0000a408 , 0x0e79e5c6 }, + { 0x0000a40c , 0x00820820 }, + { 0x0000a414 , 0x1ce739ce }, + { 0x0000a418 , 0x2d001dce }, + { 0x0000a41c , 0x1ce739ce }, + { 0x0000a420 , 0x000001ce }, + { 0x0000a424 , 0x1ce739ce }, + { 0x0000a428 , 0x000001ce }, + { 0x0000a42c , 0x1ce739ce }, + { 0x0000a430 , 0x1ce739ce }, + { 0x0000a434 , 0x00000000 }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a43c , 0x00100000 }, + { 0x0000a444 , 0x00000000 }, + { 0x0000a448 , 0x05000080 }, + { 0x0000a44c , 0x00000001 }, + { 0x0000a450 , 0x00010000 }, + { 0x0000a458 , 0x00000000 }, + { 0x0000a644 , 0xbfad9d74 }, + { 0x0000a648 , 0x0048060a }, + { 0x0000a64c , 0x00003c37 }, + { 0x0000a670 , 0x03020100 }, + { 0x0000a674 , 0x09080504 }, + { 0x0000a678 , 0x0d0c0b0a }, + { 0x0000a67c , 0x13121110 }, + { 0x0000a680 , 0x31301514 }, + { 0x0000a684 , 0x35343332 }, + { 0x0000a688 , 0x00000036 }, + { 0x0000a690 , 0x00000838 }, + { 0x0000a7cc , 0x00000000 }, + { 0x0000a7d0 , 0x00000000 }, + { 0x0000a7d4 , 0x00000004 }, + { 0x0000a7dc , 0x00000000 }, + { 0x0000a8d0 , 0x004b6a8e }, + { 0x0000a8d4 , 0x00000820 }, + { 0x0000a8dc , 0x00000000 }, + { 0x0000a8f0 , 0x00000000 }, + { 0x0000a8f4 , 0x00000000 }, + { 0x0000b2d0 , 0x00000080 }, + { 0x0000b2d4 , 0x00000000 }, + { 0x0000b2ec , 0x00000000 }, + { 0x0000b2f0 , 0x00000000 }, + { 0x0000b2f4 , 0x00000000 }, + { 0x0000b2f8 , 0x00000000 }, + { 0x0000b408 , 0x0e79e5c0 }, + { 0x0000b40c , 0x00820820 }, + { 0x0000b420 , 0x00000000 }, + { 0x0000b8d0 , 0x004b6a8e }, + { 0x0000b8d4 , 0x00000820 }, + { 0x0000b8dc , 0x00000000 }, + { 0x0000b8f0 , 0x00000000 }, + { 0x0000b8f4 , 0x00000000 }, + { 0x0000c2d0 , 0x00000080 }, + { 0x0000c2d4 , 0x00000000 }, + { 0x0000c2ec , 0x00000000 }, + { 0x0000c2f0 , 0x00000000 }, + { 0x0000c2f4 , 0x00000000 }, + { 0x0000c2f8 , 0x00000000 }, + { 0x0000c408 , 0x0e79e5c0 }, + { 0x0000c40c , 0x00820820 }, + { 0x0000c420 , 0x00000000 }, +}; + +static const u_int32_t ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x03820190 }, + { 0x0000a030 , 0x03840383 }, + { 0x0000a034 , 0x03880385 }, + { 0x0000a038 , 0x038a0389 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x29292929 }, + { 0x0000a084 , 0x29292929 }, + { 0x0000a088 , 0x29292929 }, + { 0x0000a08c , 0x29292929 }, + { 0x0000a090 , 0x22292929 }, + { 0x0000a094 , 0x1d1d2222 }, + { 0x0000a098 , 0x0c111117 }, + { 0x0000a09c , 0x00030303 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x32323232 }, + { 0x0000b084 , 0x2f2f3232 }, + { 0x0000b088 , 0x23282a2d }, + { 0x0000b08c , 0x1c1e2123 }, + { 0x0000b090 , 0x14171919 }, + { 0x0000b094 , 0x0e0e1214 }, + { 0x0000b098 , 0x03050707 }, + { 0x0000b09c , 0x00030303 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar955x_scorpion_1p0_mac_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00000030 , 0x00020085 }, + { 0x00000044 , 0x00000008 }, + { 0x0000805c , 0xffffc7ff }, + { 0x00008344 , 0xaa4a105b }, +}; + +static const u_int32_t ar955x_scorpion_1p0_soc_preamble[][2] = { +/* Addr allmodes */ + { 0x00007000 , 0x00000000 }, + { 0x00007004 , 0x00000000 }, + { 0x00007008 , 0x00000000 }, + { 0x0000700c , 0x00000000 }, + { 0x0000701c , 0x00000000 }, + { 0x00007020 , 0x00000000 }, + { 0x00007024 , 0x00000000 }, + { 0x00007028 , 0x00000000 }, + { 0x0000702c , 0x00000000 }, + { 0x00007030 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000004c2 }, + { 0x00007048 , 0x00000000 }, +}; + +static const u_int32_t ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e44 , 0xfe321e27 , 0xfe321e27 , 0xfe291e27 , 0xfe291e27 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302012 , 0x50302012 }, +}; + +static const u_int32_t ar955x_scorpion_1p0_baseband_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafa68e30 }, + { 0x00009884 , 0x00002842 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009e50 , 0x00000000 }, + { 0x00009fcc , 0x00000014 }, + { 0x0000a344 , 0x00000010 }, + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x71733d01 }, + { 0x0000a3a0 , 0xd0ad5c12 }, + { 0x0000a3c0 , 0x22222220 }, + { 0x0000a3c4 , 0x22222222 }, + { 0x0000a404 , 0x00418a11 }, + { 0x0000a418 , 0x050001ce }, + { 0x0000a438 , 0x00001800 }, + { 0x0000a458 , 0x93444452 }, + { 0x0000a690 , 0x00000038 }, + { 0x0000b8dc , 0x00400000 }, +}; + +static const u_int32_t ar955x_scorpion_1p0_mac_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, +}; + +static const u_int32_t ar955xCommon_rx_gain_bounds_scorpion_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e44 , 0xfe321e27 , 0xfe321e27 , 0xfe291e27 , 0xfe291e27 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302018 , 0x50302018 }, +}; + +static const u_int32_t ar955x_scorpion_1p0_tx_gain_table_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000000d5 , 0x000000d5 , 0x000000d5 , 0x000000d5 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x00004002 , 0x00004002 , 0x00004002 , 0x00004002 }, + { 0x0000a508 , 0x00008004 , 0x00008004 , 0x00008004 , 0x00008004 }, + { 0x0000a510 , 0x0001000c , 0x0001000c , 0x0001000c , 0x0001000c }, + { 0x0000a514 , 0x0001420b , 0x0001420b , 0x0001420b , 0x0001420b }, + { 0x0000a518 , 0x0001824a , 0x0001824a , 0x0001824a , 0x0001824a }, + { 0x0000a51c , 0x0001c44a , 0x0001c44a , 0x0001c44a , 0x0001c44a }, + { 0x0000a520 , 0x0002064a , 0x0002064a , 0x0002064a , 0x0002064a }, + { 0x0000a524 , 0x0002484a , 0x0002484a , 0x0002484a , 0x0002484a }, + { 0x0000a528 , 0x00028a4a , 0x00028a4a , 0x00028a4a , 0x00028a4a }, + { 0x0000a52c , 0x00030e4a , 0x00030e4a , 0x00030e4a , 0x00030e4a }, + { 0x0000a530 , 0x00030e4a , 0x00030e4a , 0x00030e4a , 0x00030e4a }, + { 0x0000a534 , 0x00034e8a , 0x00034e8a , 0x00034e8a , 0x00034e8a }, +}; + +static const u_int32_t ar955x_scorpion_1p0_mac_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 }, + { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 }, +}; + +static const u_int32_t ar955x_scorpion_1p0_baseband_postamble_dfs_channel[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00009824 , 0x5ac668d0 , 0x5ac668d0 }, + { 0x00009e0c , 0x6d4000e2 , 0x6d4000e2 }, + { 0x00009e14 , 0x37b9625e , 0x37b9625e }, +}; + +static const u_int32_t ar955xModes_no_xpa_tx_gain_table_scorpion_1p0[][9] = { +/* Addr 5G_low_HT20 5G_low_HT40 5G_medium_HT20 5G_medium_HT40 5G_high_HT20 5G_high_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0xfffe5aaa , 0xfffe5aaa }, + { 0x0000a2e0 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0xfffe9ccc , 0xfffe9ccc }, + { 0x0000a2e4 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0xffffe0f0 , 0xffffe0f0 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0xffffef00 , 0xffffef00 }, + { 0x0000a410 , 0x000050d8 , 0x000050d8 , 0x000050d8 , 0x000050d8 , 0x000050d8 , 0x000050d8 , 0x000050d7 , 0x000050d7 }, + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00002220 , 0x00002220 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x04002222 , 0x04002222 , 0x04002222 , 0x04002222 , 0x04002222 , 0x04002222 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x09002421 , 0x09002421 , 0x09002421 , 0x09002421 , 0x09002421 , 0x09002421 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x0d002621 , 0x0d002621 , 0x0d002621 , 0x0d002621 , 0x0d002621 , 0x0d002621 , 0x0b000006 , 0x0b000006 }, + { 0x0000a510 , 0x13004620 , 0x13004620 , 0x13004620 , 0x13004620 , 0x13004620 , 0x13004620 , 0x0f00000a , 0x0f00000a }, + { 0x0000a514 , 0x19004a20 , 0x19004a20 , 0x19004a20 , 0x19004a20 , 0x19004a20 , 0x19004a20 , 0x1300000c , 0x1300000c }, + { 0x0000a518 , 0x1d004e20 , 0x1d004e20 , 0x1d004e20 , 0x1d004e20 , 0x1d004e20 , 0x1d004e20 , 0x1700000e , 0x1700000e }, + { 0x0000a51c , 0x21005420 , 0x21005420 , 0x21005420 , 0x21005420 , 0x21005420 , 0x21005420 , 0x1b000012 , 0x1b000012 }, + { 0x0000a520 , 0x26005e20 , 0x26005e20 , 0x26005e20 , 0x26005e20 , 0x26005e20 , 0x26005e20 , 0x1f00004a , 0x1f00004a }, + { 0x0000a524 , 0x2b005e40 , 0x2b005e40 , 0x2b005e40 , 0x2b005e40 , 0x2b005e40 , 0x2b005e40 , 0x23000244 , 0x23000244 }, + { 0x0000a528 , 0x2f005e42 , 0x2f005e42 , 0x2f005e42 , 0x2f005e42 , 0x2f005e42 , 0x2f005e42 , 0x2700022b , 0x2700022b }, + { 0x0000a52c , 0x33005e44 , 0x33005e44 , 0x33005e44 , 0x33005e44 , 0x33005e44 , 0x33005e44 , 0x2b000625 , 0x2b000625 }, + { 0x0000a530 , 0x38005e65 , 0x38005e65 , 0x38005e65 , 0x38005e65 , 0x38005e65 , 0x38005e65 , 0x2f001006 , 0x2f001006 }, + { 0x0000a534 , 0x3c005e69 , 0x3c005e69 , 0x3c005e69 , 0x3c005e69 , 0x3c005e69 , 0x3c005e69 , 0x330008a0 , 0x330008a0 }, + { 0x0000a538 , 0x40005e6b , 0x40005e6b , 0x40005e6b , 0x40005e6b , 0x40005e6b , 0x40005e6b , 0x37000a2a , 0x37000a2a }, + { 0x0000a53c , 0x44005e6d , 0x44005e6d , 0x44005e6d , 0x44005e6d , 0x44005e6d , 0x44005e6d , 0x3b001c23 , 0x3b001c23 }, + { 0x0000a540 , 0x49005e72 , 0x49005e72 , 0x49005e72 , 0x49005e72 , 0x49005e72 , 0x49005e72 , 0x3f0014a0 , 0x3f0014a0 }, + { 0x0000a544 , 0x4e005eb2 , 0x4e005eb2 , 0x4e005eb2 , 0x4e005eb2 , 0x4e005eb2 , 0x4e005eb2 , 0x43001882 , 0x43001882 }, + { 0x0000a548 , 0x53005f12 , 0x53005f12 , 0x53005f12 , 0x53005f12 , 0x53005f12 , 0x53005f12 , 0x47001ca2 , 0x47001ca2 }, + { 0x0000a54c , 0x59025eb2 , 0x59025eb2 , 0x59025eb2 , 0x59025eb2 , 0x59025eb2 , 0x59025eb2 , 0x4b001ec3 , 0x4b001ec3 }, + { 0x0000a550 , 0x5e025f12 , 0x5e025f12 , 0x5e025f12 , 0x5e025f12 , 0x5e025f12 , 0x5e025f12 , 0x4f00148c , 0x4f00148c }, + { 0x0000a554 , 0x61027f12 , 0x61027f12 , 0x61027f12 , 0x61027f12 , 0x61027f12 , 0x61027f12 , 0x53001c6e , 0x53001c6e }, + { 0x0000a558 , 0x6702bf12 , 0x6702bf12 , 0x6702bf12 , 0x6702bf12 , 0x6702bf12 , 0x6702bf12 , 0x57001c92 , 0x57001c92 }, + { 0x0000a55c , 0x6b02bf14 , 0x6b02bf14 , 0x6b02bf14 , 0x6b02bf14 , 0x6b02bf14 , 0x6b02bf14 , 0x5c001af6 , 0x5c001af6 }, + { 0x0000a560 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x5c001af6 , 0x5c001af6 }, + { 0x0000a564 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x5c001af6 , 0x5c001af6 }, + { 0x0000a568 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x5c001af6 , 0x5c001af6 }, + { 0x0000a56c , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x5c001af6 , 0x5c001af6 }, + { 0x0000a570 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x5c001af6 , 0x5c001af6 }, + { 0x0000a574 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x5c001af6 , 0x5c001af6 }, + { 0x0000a578 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x5c001af6 , 0x5c001af6 }, + { 0x0000a57c , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x6f02bf16 , 0x5c001af6 , 0x5c001af6 }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00804000 , 0x00804000 , 0x00804000 , 0x00804000 , 0x00804000 , 0x00804000 , 0x04005001 , 0x04005001 }, + { 0x0000a614 , 0x00804201 , 0x00804201 , 0x00804201 , 0x00804201 , 0x00804201 , 0x00804201 , 0x03808e02 , 0x03808e02 }, + { 0x0000a618 , 0x0280c802 , 0x0280c802 , 0x0280c802 , 0x0280c802 , 0x0280c802 , 0x0280c802 , 0x0300c000 , 0x0300c000 }, + { 0x0000a61c , 0x0280ca03 , 0x0280ca03 , 0x0280ca03 , 0x0280ca03 , 0x0280ca03 , 0x0280ca03 , 0x03808e02 , 0x03808e02 }, + { 0x0000a620 , 0x04c15104 , 0x04c15104 , 0x04c15104 , 0x04c15104 , 0x04c15104 , 0x04c15104 , 0x03410c03 , 0x03410c03 }, + { 0x0000a624 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04014c03 , 0x04014c03 }, + { 0x0000a628 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x05818d04 , 0x05818d04 }, + { 0x0000a62c , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x0801cd04 , 0x0801cd04 }, + { 0x0000a630 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x0801e007 , 0x0801e007 }, + { 0x0000a634 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x0801e007 , 0x0801e007 }, + { 0x0000a638 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x0801e007 , 0x0801e007 }, + { 0x0000a63c , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x04c15305 , 0x0801e007 , 0x0801e007 }, + { 0x0000b2dc , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0xfffe5aaa , 0xfffe5aaa }, + { 0x0000b2e0 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0xfffe9ccc , 0xfffe9ccc }, + { 0x0000b2e4 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0xffffe0f0 , 0xffffe0f0 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0xffffef00 , 0xffffef00 }, + { 0x0000c2dc , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0x01feee00 , 0xfffe5aaa , 0xfffe5aaa }, + { 0x0000c2e0 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0x0000f000 , 0xfffe9ccc , 0xfffe9ccc }, + { 0x0000c2e4 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0x01ff0000 , 0xffffe0f0 , 0xffffe0f0 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 , 0xffffef00 , 0xffffef00 }, + { 0x00016044 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x054922d4 , 0x054922d4 }, + { 0x00016048 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 }, + { 0x00016444 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x054922d4 , 0x054922d4 }, + { 0x00016448 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 }, + { 0x00016844 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x056db2d4 , 0x054922d4 , 0x054922d4 }, + { 0x00016848 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 , 0x66482401 }, +}; + +static const u_int32_t ar955x_scorpion_1p0_soc_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00007010 , 0x00000023 , 0x00000023 , 0x00000023 , 0x00000023 }, +}; + +static const u_int32_t ar955xModes_fast_clock_scorpion_1p0[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00001030 , 0x00000268 , 0x000004d0 }, + { 0x00001070 , 0x0000018c , 0x00000318 }, + { 0x000010b0 , 0x00000fd0 , 0x00001fa0 }, + { 0x00008014 , 0x044c044c , 0x08980898 }, + { 0x0000801c , 0x148ec02b , 0x148ec057 }, + { 0x00008318 , 0x000044c0 , 0x00008980 }, + { 0x00009e00 , 0x0372131c , 0x0372131c }, + { 0x0000a230 , 0x0000400b , 0x00004016 }, + { 0x0000a254 , 0x00000898 , 0x00001130 }, +}; + +static const u_int32_t ar955xCommon_rx_gain_table_merlin_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x02000101 }, + { 0x0000a004 , 0x02000102 }, + { 0x0000a008 , 0x02000103 }, + { 0x0000a00c , 0x02000104 }, + { 0x0000a010 , 0x02000200 }, + { 0x0000a014 , 0x02000201 }, + { 0x0000a018 , 0x02000202 }, + { 0x0000a01c , 0x02000203 }, + { 0x0000a020 , 0x02000204 }, + { 0x0000a024 , 0x02000205 }, + { 0x0000a028 , 0x02000208 }, + { 0x0000a02c , 0x02000302 }, + { 0x0000a030 , 0x02000303 }, + { 0x0000a034 , 0x02000304 }, + { 0x0000a038 , 0x02000400 }, + { 0x0000a03c , 0x02010300 }, + { 0x0000a040 , 0x02010301 }, + { 0x0000a044 , 0x02010302 }, + { 0x0000a048 , 0x02000500 }, + { 0x0000a04c , 0x02010400 }, + { 0x0000a050 , 0x02020300 }, + { 0x0000a054 , 0x02020301 }, + { 0x0000a058 , 0x02020302 }, + { 0x0000a05c , 0x02020303 }, + { 0x0000a060 , 0x02020400 }, + { 0x0000a064 , 0x02030300 }, + { 0x0000a068 , 0x02030301 }, + { 0x0000a06c , 0x02030302 }, + { 0x0000a070 , 0x02030303 }, + { 0x0000a074 , 0x02030400 }, + { 0x0000a078 , 0x02040300 }, + { 0x0000a07c , 0x02040301 }, + { 0x0000a080 , 0x02040302 }, + { 0x0000a084 , 0x02040303 }, + { 0x0000a088 , 0x02030500 }, + { 0x0000a08c , 0x02040400 }, + { 0x0000a090 , 0x02050203 }, + { 0x0000a094 , 0x02050204 }, + { 0x0000a098 , 0x02050205 }, + { 0x0000a09c , 0x02040500 }, + { 0x0000a0a0 , 0x02050301 }, + { 0x0000a0a4 , 0x02050302 }, + { 0x0000a0a8 , 0x02050303 }, + { 0x0000a0ac , 0x02050400 }, + { 0x0000a0b0 , 0x02050401 }, + { 0x0000a0b4 , 0x02050402 }, + { 0x0000a0b8 , 0x02050403 }, + { 0x0000a0bc , 0x02050500 }, + { 0x0000a0c0 , 0x02050501 }, + { 0x0000a0c4 , 0x02050502 }, + { 0x0000a0c8 , 0x02050503 }, + { 0x0000a0cc , 0x02050504 }, + { 0x0000a0d0 , 0x02050600 }, + { 0x0000a0d4 , 0x02050601 }, + { 0x0000a0d8 , 0x02050602 }, + { 0x0000a0dc , 0x02050603 }, + { 0x0000a0e0 , 0x02050604 }, + { 0x0000a0e4 , 0x02050700 }, + { 0x0000a0e8 , 0x02050701 }, + { 0x0000a0ec , 0x02050702 }, + { 0x0000a0f0 , 0x02050703 }, + { 0x0000a0f4 , 0x02050704 }, + { 0x0000a0f8 , 0x02050705 }, + { 0x0000a0fc , 0x02050708 }, + { 0x0000a100 , 0x02050709 }, + { 0x0000a104 , 0x0205070a }, + { 0x0000a108 , 0x0205070b }, + { 0x0000a10c , 0x0205070c }, + { 0x0000a110 , 0x0205070d }, + { 0x0000a114 , 0x02050710 }, + { 0x0000a118 , 0x02050711 }, + { 0x0000a11c , 0x02050712 }, + { 0x0000a120 , 0x02050713 }, + { 0x0000a124 , 0x02050714 }, + { 0x0000a128 , 0x02050715 }, + { 0x0000a12c , 0x02050730 }, + { 0x0000a130 , 0x02050731 }, + { 0x0000a134 , 0x02050732 }, + { 0x0000a138 , 0x02050733 }, + { 0x0000a13c , 0x02050734 }, + { 0x0000a140 , 0x02050735 }, + { 0x0000a144 , 0x02050750 }, + { 0x0000a148 , 0x02050751 }, + { 0x0000a14c , 0x02050752 }, + { 0x0000a150 , 0x02050753 }, + { 0x0000a154 , 0x02050754 }, + { 0x0000a158 , 0x02050755 }, + { 0x0000a15c , 0x02050770 }, + { 0x0000a160 , 0x02050771 }, + { 0x0000a164 , 0x02050772 }, + { 0x0000a168 , 0x02050773 }, + { 0x0000a16c , 0x02050774 }, + { 0x0000a170 , 0x02050775 }, + { 0x0000a174 , 0x00000776 }, + { 0x0000a178 , 0x00000776 }, + { 0x0000a17c , 0x00000776 }, + { 0x0000a180 , 0x00000776 }, + { 0x0000a184 , 0x00000776 }, + { 0x0000a188 , 0x00000776 }, + { 0x0000a18c , 0x00000776 }, + { 0x0000a190 , 0x00000776 }, + { 0x0000a194 , 0x00000776 }, + { 0x0000a198 , 0x00000776 }, + { 0x0000a19c , 0x00000776 }, + { 0x0000a1a0 , 0x00000776 }, + { 0x0000a1a4 , 0x00000776 }, + { 0x0000a1a8 , 0x00000776 }, + { 0x0000a1ac , 0x00000776 }, + { 0x0000a1b0 , 0x00000776 }, + { 0x0000a1b4 , 0x00000776 }, + { 0x0000a1b8 , 0x00000776 }, + { 0x0000a1bc , 0x00000776 }, + { 0x0000a1c0 , 0x00000776 }, + { 0x0000a1c4 , 0x00000776 }, + { 0x0000a1c8 , 0x00000776 }, + { 0x0000a1cc , 0x00000776 }, + { 0x0000a1d0 , 0x00000776 }, + { 0x0000a1d4 , 0x00000776 }, + { 0x0000a1d8 , 0x00000776 }, + { 0x0000a1dc , 0x00000776 }, + { 0x0000a1e0 , 0x00000776 }, + { 0x0000a1e4 , 0x00000776 }, + { 0x0000a1e8 , 0x00000776 }, + { 0x0000a1ec , 0x00000776 }, + { 0x0000a1f0 , 0x00000776 }, + { 0x0000a1f4 , 0x00000776 }, + { 0x0000a1f8 , 0x00000776 }, + { 0x0000a1fc , 0x00000776 }, + { 0x0000b000 , 0x02000101 }, + { 0x0000b004 , 0x02000102 }, + { 0x0000b008 , 0x02000103 }, + { 0x0000b00c , 0x02000104 }, + { 0x0000b010 , 0x02000200 }, + { 0x0000b014 , 0x02000201 }, + { 0x0000b018 , 0x02000202 }, + { 0x0000b01c , 0x02000203 }, + { 0x0000b020 , 0x02000204 }, + { 0x0000b024 , 0x02000205 }, + { 0x0000b028 , 0x02000208 }, + { 0x0000b02c , 0x02000302 }, + { 0x0000b030 , 0x02000303 }, + { 0x0000b034 , 0x02000304 }, + { 0x0000b038 , 0x02000400 }, + { 0x0000b03c , 0x02010300 }, + { 0x0000b040 , 0x02010301 }, + { 0x0000b044 , 0x02010302 }, + { 0x0000b048 , 0x02000500 }, + { 0x0000b04c , 0x02010400 }, + { 0x0000b050 , 0x02020300 }, + { 0x0000b054 , 0x02020301 }, + { 0x0000b058 , 0x02020302 }, + { 0x0000b05c , 0x02020303 }, + { 0x0000b060 , 0x02020400 }, + { 0x0000b064 , 0x02030300 }, + { 0x0000b068 , 0x02030301 }, + { 0x0000b06c , 0x02030302 }, + { 0x0000b070 , 0x02030303 }, + { 0x0000b074 , 0x02030400 }, + { 0x0000b078 , 0x02040300 }, + { 0x0000b07c , 0x02040301 }, + { 0x0000b080 , 0x02040302 }, + { 0x0000b084 , 0x02040303 }, + { 0x0000b088 , 0x02030500 }, + { 0x0000b08c , 0x02040400 }, + { 0x0000b090 , 0x02050203 }, + { 0x0000b094 , 0x02050204 }, + { 0x0000b098 , 0x02050205 }, + { 0x0000b09c , 0x02040500 }, + { 0x0000b0a0 , 0x02050301 }, + { 0x0000b0a4 , 0x02050302 }, + { 0x0000b0a8 , 0x02050303 }, + { 0x0000b0ac , 0x02050400 }, + { 0x0000b0b0 , 0x02050401 }, + { 0x0000b0b4 , 0x02050402 }, + { 0x0000b0b8 , 0x02050403 }, + { 0x0000b0bc , 0x02050500 }, + { 0x0000b0c0 , 0x02050501 }, + { 0x0000b0c4 , 0x02050502 }, + { 0x0000b0c8 , 0x02050503 }, + { 0x0000b0cc , 0x02050504 }, + { 0x0000b0d0 , 0x02050600 }, + { 0x0000b0d4 , 0x02050601 }, + { 0x0000b0d8 , 0x02050602 }, + { 0x0000b0dc , 0x02050603 }, + { 0x0000b0e0 , 0x02050604 }, + { 0x0000b0e4 , 0x02050700 }, + { 0x0000b0e8 , 0x02050701 }, + { 0x0000b0ec , 0x02050702 }, + { 0x0000b0f0 , 0x02050703 }, + { 0x0000b0f4 , 0x02050704 }, + { 0x0000b0f8 , 0x02050705 }, + { 0x0000b0fc , 0x02050708 }, + { 0x0000b100 , 0x02050709 }, + { 0x0000b104 , 0x0205070a }, + { 0x0000b108 , 0x0205070b }, + { 0x0000b10c , 0x0205070c }, + { 0x0000b110 , 0x0205070d }, + { 0x0000b114 , 0x02050710 }, + { 0x0000b118 , 0x02050711 }, + { 0x0000b11c , 0x02050712 }, + { 0x0000b120 , 0x02050713 }, + { 0x0000b124 , 0x02050714 }, + { 0x0000b128 , 0x02050715 }, + { 0x0000b12c , 0x02050730 }, + { 0x0000b130 , 0x02050731 }, + { 0x0000b134 , 0x02050732 }, + { 0x0000b138 , 0x02050733 }, + { 0x0000b13c , 0x02050734 }, + { 0x0000b140 , 0x02050735 }, + { 0x0000b144 , 0x02050750 }, + { 0x0000b148 , 0x02050751 }, + { 0x0000b14c , 0x02050752 }, + { 0x0000b150 , 0x02050753 }, + { 0x0000b154 , 0x02050754 }, + { 0x0000b158 , 0x02050755 }, + { 0x0000b15c , 0x02050770 }, + { 0x0000b160 , 0x02050771 }, + { 0x0000b164 , 0x02050772 }, + { 0x0000b168 , 0x02050773 }, + { 0x0000b16c , 0x02050774 }, + { 0x0000b170 , 0x02050775 }, + { 0x0000b174 , 0x00000776 }, + { 0x0000b178 , 0x00000776 }, + { 0x0000b17c , 0x00000776 }, + { 0x0000b180 , 0x00000776 }, + { 0x0000b184 , 0x00000776 }, + { 0x0000b188 , 0x00000776 }, + { 0x0000b18c , 0x00000776 }, + { 0x0000b190 , 0x00000776 }, + { 0x0000b194 , 0x00000776 }, + { 0x0000b198 , 0x00000776 }, + { 0x0000b19c , 0x00000776 }, + { 0x0000b1a0 , 0x00000776 }, + { 0x0000b1a4 , 0x00000776 }, + { 0x0000b1a8 , 0x00000776 }, + { 0x0000b1ac , 0x00000776 }, + { 0x0000b1b0 , 0x00000776 }, + { 0x0000b1b4 , 0x00000776 }, + { 0x0000b1b8 , 0x00000776 }, + { 0x0000b1bc , 0x00000776 }, + { 0x0000b1c0 , 0x00000776 }, + { 0x0000b1c4 , 0x00000776 }, + { 0x0000b1c8 , 0x00000776 }, + { 0x0000b1cc , 0x00000776 }, + { 0x0000b1d0 , 0x00000776 }, + { 0x0000b1d4 , 0x00000776 }, + { 0x0000b1d8 , 0x00000776 }, + { 0x0000b1dc , 0x00000776 }, + { 0x0000b1e0 , 0x00000776 }, + { 0x0000b1e4 , 0x00000776 }, + { 0x0000b1e8 , 0x00000776 }, + { 0x0000b1ec , 0x00000776 }, + { 0x0000b1f0 , 0x00000776 }, + { 0x0000b1f4 , 0x00000776 }, + { 0x0000b1f8 , 0x00000776 }, + { 0x0000b1fc , 0x00000776 }, +}; + diff --git a/hal/ar9300/ar9580.ini b/hal/ar9300/ar9580.ini new file mode 100644 index 000000000000..32124dbdfbc2 --- /dev/null +++ b/hal/ar9300/ar9580.ini @@ -0,0 +1,2219 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + + + + + + + + + +static const u_int32_t ar9300_ar9580_1p0_baseband_postamble_dfs_channel[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00009824 , 0x5ac668d0 , 0x5ac668d0 }, + { 0x00009e0c , 0x6d4000e2 , 0x6d4000e2 }, + { 0x00009e14 , 0x37b9625e , 0x37b9625e }, +}; + +static const u_int32_t ar9300Modes_fast_clock_ar9580_1p0[][3] = { +/* Addr 5G_HT20 5G_HT40 */ + { 0x00001030 , 0x00000268 , 0x000004d0 }, + { 0x00001070 , 0x0000018c , 0x00000318 }, + { 0x000010b0 , 0x00000fd0 , 0x00001fa0 }, + { 0x00008014 , 0x044c044c , 0x08980898 }, + { 0x0000801c , 0x148ec02b , 0x148ec057 }, + { 0x00008318 , 0x000044c0 , 0x00008980 }, + { 0x00009e00 , 0x0372131c , 0x0372131c }, + { 0x0000a230 , 0x0000000b , 0x00000016 }, + { 0x0000a254 , 0x00000898 , 0x00001130 }, +}; + +static const u_int32_t ar9300_ar9580_1p0_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e3c , 0xcf946221 , 0xcf946221 , 0xcf946221 , 0xcf946221 }, + { 0x00009e44 , 0x005c0000 , 0x005c0000 , 0x005c0000 , 0x005c0000 }, + { 0x0000a258 , 0x02020200 , 0x02020200 , 0x02020200 , 0x02020200 }, + { 0x0000a25c , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a28c , 0x00011111 , 0x00011111 , 0x00011111 , 0x00011111 }, + { 0x0000a2c4 , 0x00148d18 , 0x00148d18 , 0x00148d20 , 0x00148d20 }, + { 0x0000a2d8 , 0xf999a801 , 0xf999a801 , 0xf999a80d , 0xf999a80d }, + { 0x0000a50c , 0x0000c00a , 0x0000c00a , 0x0000c00a , 0x0000c00a }, + { 0x0000a538 , 0x00038e8c , 0x00038e8c , 0x00038e8c , 0x00038e8c }, + { 0x0000a53c , 0x0003cecc , 0x0003cecc , 0x0003cecc , 0x0003cecc }, + { 0x0000a540 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 , 0x00040ed4 }, + { 0x0000a544 , 0x00044edc , 0x00044edc , 0x00044edc , 0x00044edc }, + { 0x0000a548 , 0x00048ede , 0x00048ede , 0x00048ede , 0x00048ede }, + { 0x0000a54c , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e , 0x0004cf1e }, + { 0x0000a550 , 0x00050f5e , 0x00050f5e , 0x00050f5e , 0x00050f5e }, + { 0x0000a554 , 0x00054f9e , 0x00054f9e , 0x00054f9e , 0x00054f9e }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000be18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, +}; + +static const u_int32_t ar9300_ar9580_1p0_radio_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0001609c , 0x0dd08f29 , 0x0dd08f29 , 0x0b283f31 , 0x0b283f31 }, + { 0x000160ac , 0xa4653c00 , 0xa4653c00 , 0x24652800 , 0x24652800 }, + { 0x000160b0 , 0x03284f3e , 0x03284f3e , 0x05d08f20 , 0x05d08f20 }, + { 0x0001610c , 0xc8000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016140 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, + { 0x0001650c , 0xc8000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016540 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, + { 0x0001690c , 0xc8000000 , 0xc0000000 , 0xc0000000 , 0xc0000000 }, + { 0x00016940 , 0x10804008 , 0x10804008 , 0x50804008 , 0x50804008 }, +}; + +static const u_int32_t ar9300_ar9580_1p0_baseband_core[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafe68e30 }, + { 0x00009804 , 0xfd14e000 }, + { 0x00009808 , 0x9c0a9f6b }, + { 0x0000980c , 0x04900000 }, + { 0x00009814 , 0x3280c00a }, + { 0x00009818 , 0x00000000 }, + { 0x0000981c , 0x00020028 }, + { 0x00009834 , 0x6400a190 }, + { 0x00009838 , 0x0108ecff }, + { 0x0000983c , 0x14000600 }, + { 0x00009880 , 0x201fff00 }, + { 0x00009884 , 0x00001042 }, + { 0x000098a4 , 0x00200400 }, + { 0x000098b0 , 0x32840bbe }, + { 0x000098d0 , 0x004b6a8e }, + { 0x000098d4 , 0x00000820 }, + { 0x000098dc , 0x00000000 }, + { 0x000098f0 , 0x00000000 }, + { 0x000098f4 , 0x00000000 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009c0c , 0x00000000 }, + { 0x00009c10 , 0x00000000 }, + { 0x00009c14 , 0x00046384 }, + { 0x00009c18 , 0x05b6b440 }, + { 0x00009c1c , 0x00b6b440 }, + { 0x00009d00 , 0xc080a333 }, + { 0x00009d04 , 0x40206c10 }, + { 0x00009d08 , 0x009c4060 }, + { 0x00009d0c , 0x9883800a }, + { 0x00009d10 , 0x01834061 }, + { 0x00009d14 , 0x00c0040b }, + { 0x00009d18 , 0x00000000 }, + { 0x00009e08 , 0x0038230c }, + { 0x00009e24 , 0x990bb515 }, + { 0x00009e28 , 0x0c6f0000 }, + { 0x00009e30 , 0x06336f77 }, + { 0x00009e34 , 0x6af6532f }, + { 0x00009e38 , 0x0cc80c00 }, + { 0x00009e40 , 0x0d261820 }, + { 0x00009e4c , 0x00001004 }, + { 0x00009e50 , 0x00ff03f1 }, + { 0x00009e54 , 0x00000000 }, + { 0x00009fc0 , 0x803e4788 }, + { 0x00009fc4 , 0x0001efb5 }, + { 0x00009fcc , 0x40000014 }, + { 0x00009fd0 , 0x01193b93 }, + { 0x0000a20c , 0x00000000 }, + { 0x0000a220 , 0x00000000 }, + { 0x0000a224 , 0x00000000 }, + { 0x0000a228 , 0x10002310 }, + { 0x0000a23c , 0x00000000 }, + { 0x0000a244 , 0x0c000000 }, + { 0x0000a2a0 , 0x00000001 }, + { 0x0000a2c0 , 0x00000001 }, + { 0x0000a2c8 , 0x00000000 }, + { 0x0000a2cc , 0x18c43433 }, + { 0x0000a2d4 , 0x00000000 }, + { 0x0000a2ec , 0x00000000 }, + { 0x0000a2f0 , 0x00000000 }, + { 0x0000a2f4 , 0x00000000 }, + { 0x0000a2f8 , 0x00000000 }, + { 0x0000a344 , 0x00000000 }, + { 0x0000a34c , 0x00000000 }, + { 0x0000a350 , 0x0000a000 }, + { 0x0000a364 , 0x00000000 }, + { 0x0000a370 , 0x00000000 }, + { 0x0000a390 , 0x00000001 }, + { 0x0000a394 , 0x00000444 }, + { 0x0000a398 , 0x001f0e0f }, + { 0x0000a39c , 0x0075393f }, + { 0x0000a3a0 , 0xb79f6427 }, + { 0x0000a3a4 , 0x00000000 }, + { 0x0000a3a8 , 0xaaaaaaaa }, + { 0x0000a3ac , 0x3c466478 }, + { 0x0000a3c0 , 0x20202020 }, + { 0x0000a3c4 , 0x22222220 }, + { 0x0000a3c8 , 0x20200020 }, + { 0x0000a3cc , 0x20202020 }, + { 0x0000a3d0 , 0x20202020 }, + { 0x0000a3d4 , 0x20202020 }, + { 0x0000a3d8 , 0x20202020 }, + { 0x0000a3dc , 0x20202020 }, + { 0x0000a3e0 , 0x20202020 }, + { 0x0000a3e4 , 0x20202020 }, + { 0x0000a3e8 , 0x20202020 }, + { 0x0000a3ec , 0x20202020 }, + { 0x0000a3f0 , 0x00000000 }, + { 0x0000a3f4 , 0x00000000 }, + { 0x0000a3f8 , 0x0c9bd380 }, + { 0x0000a3fc , 0x000f0f01 }, + { 0x0000a400 , 0x8fa91f01 }, + { 0x0000a404 , 0x00000000 }, + { 0x0000a408 , 0x0e79e5c6 }, + { 0x0000a40c , 0x00820820 }, + { 0x0000a414 , 0x1ce739ce }, + { 0x0000a418 , 0x2d001dce }, + { 0x0000a41c , 0x1ce739ce }, + { 0x0000a420 , 0x000001ce }, + { 0x0000a424 , 0x1ce739ce }, + { 0x0000a428 , 0x000001ce }, + { 0x0000a42c , 0x1ce739ce }, + { 0x0000a430 , 0x1ce739ce }, + { 0x0000a434 , 0x00000000 }, + { 0x0000a438 , 0x00001801 }, + { 0x0000a43c , 0x00100000 }, + { 0x0000a440 , 0x00000000 }, + { 0x0000a444 , 0x00000000 }, + { 0x0000a448 , 0x05000080 }, + { 0x0000a44c , 0x00000001 }, + { 0x0000a450 , 0x00010000 }, + { 0x0000a458 , 0x00000000 }, + { 0x0000a640 , 0x00000000 }, + { 0x0000a644 , 0x3fad9d74 }, + { 0x0000a648 , 0x0048060a }, + { 0x0000a64c , 0x00003c37 }, + { 0x0000a670 , 0x03020100 }, + { 0x0000a674 , 0x09080504 }, + { 0x0000a678 , 0x0d0c0b0a }, + { 0x0000a67c , 0x13121110 }, + { 0x0000a680 , 0x31301514 }, + { 0x0000a684 , 0x35343332 }, + { 0x0000a688 , 0x00000036 }, + { 0x0000a690 , 0x00000838 }, + { 0x0000a7c0 , 0x00000000 }, + { 0x0000a7c4 , 0xfffffffc }, + { 0x0000a7c8 , 0x00000000 }, + { 0x0000a7cc , 0x00000000 }, + { 0x0000a7d0 , 0x00000000 }, + { 0x0000a7d4 , 0x00000004 }, + { 0x0000a7dc , 0x00000000 }, + { 0x0000a8d0 , 0x004b6a8e }, + { 0x0000a8d4 , 0x00000820 }, + { 0x0000a8dc , 0x00000000 }, + { 0x0000a8f0 , 0x00000000 }, + { 0x0000a8f4 , 0x00000000 }, + { 0x0000b2d0 , 0x00000080 }, + { 0x0000b2d4 , 0x00000000 }, + { 0x0000b2ec , 0x00000000 }, + { 0x0000b2f0 , 0x00000000 }, + { 0x0000b2f4 , 0x00000000 }, + { 0x0000b2f8 , 0x00000000 }, + { 0x0000b408 , 0x0e79e5c0 }, + { 0x0000b40c , 0x00820820 }, + { 0x0000b420 , 0x00000000 }, + { 0x0000b8d0 , 0x004b6a8e }, + { 0x0000b8d4 , 0x00000820 }, + { 0x0000b8dc , 0x00000000 }, + { 0x0000b8f0 , 0x00000000 }, + { 0x0000b8f4 , 0x00000000 }, + { 0x0000c2d0 , 0x00000080 }, + { 0x0000c2d4 , 0x00000000 }, + { 0x0000c2ec , 0x00000000 }, + { 0x0000c2f0 , 0x00000000 }, + { 0x0000c2f4 , 0x00000000 }, + { 0x0000c2f8 , 0x00000000 }, + { 0x0000c408 , 0x0e79e5c0 }, + { 0x0000c40c , 0x00820820 }, + { 0x0000c420 , 0x00000000 }, +}; + +static const u_int32_t ar9300_ar9580_1p0_mac_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00001030 , 0x00000230 , 0x00000460 , 0x000002c0 , 0x00000160 }, + { 0x00001070 , 0x00000168 , 0x000002d0 , 0x00000318 , 0x0000018c }, + { 0x000010b0 , 0x00000e60 , 0x00001cc0 , 0x00007c70 , 0x00003e38 }, + { 0x00008014 , 0x03e803e8 , 0x07d007d0 , 0x10801600 , 0x08400b00 }, + { 0x0000801c , 0x128d8027 , 0x128d804f , 0x12e00057 , 0x12e0002b }, + { 0x00008120 , 0x08f04800 , 0x08f04800 , 0x08f04810 , 0x08f04810 }, + { 0x000081d0 , 0x00003210 , 0x00003210 , 0x0000320a , 0x0000320a }, + { 0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 }, +}; + +static const u_int32_t ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5c02486b , 0x5c02486b , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x61024a6c , 0x61024a6c , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x66026a6c , 0x66026a6c , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x6b026e6c , 0x6b026e6c , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x7002708c , 0x7002708c , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x7302b08a , 0x7302b08a , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x12800400 , 0x12800400 }, + { 0x0000a598 , 0x21802220 , 0x21802220 , 0x16800402 , 0x16800402 }, + { 0x0000a59c , 0x27802223 , 0x27802223 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1c800603 , 0x1c800603 }, + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x21800a02 , 0x21800a02 }, + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x25800a04 , 0x25800a04 }, + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x28800a20 , 0x28800a20 }, + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2c800e20 , 0x2c800e20 }, + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x30800e22 , 0x30800e22 }, + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x34800e24 , 0x34800e24 }, + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x38801640 , 0x38801640 }, + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x3c801660 , 0x3c801660 }, + { 0x0000a5c4 , 0x5382266c , 0x5382266c , 0x3f801861 , 0x3f801861 }, + { 0x0000a5c8 , 0x5782286c , 0x5782286c , 0x43801a81 , 0x43801a81 }, + { 0x0000a5cc , 0x5c82486b , 0x5c82486b , 0x47801a83 , 0x47801a83 }, + { 0x0000a5d0 , 0x61824a6c , 0x61824a6c , 0x4a801c84 , 0x4a801c84 }, + { 0x0000a5d4 , 0x66826a6c , 0x66826a6c , 0x4e801ce3 , 0x4e801ce3 }, + { 0x0000a5d8 , 0x6b826e6c , 0x6b826e6c , 0x52801ce5 , 0x52801ce5 }, + { 0x0000a5dc , 0x7082708c , 0x7082708c , 0x56801ce9 , 0x56801ce9 }, + { 0x0000a5e0 , 0x7382b08a , 0x7382b08a , 0x5a801ceb , 0x5a801ceb }, + { 0x0000a5e4 , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5e8 , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5ec , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f0 , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f4 , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f8 , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5fc , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0300cc03 , 0x0300cc03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x0300cc03 , 0x0300cc03 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03810c03 , 0x03810c03 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x66480001 , 0x66480001 , 0x66480001 , 0x66480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x66480001 , 0x66480001 , 0x66480001 , 0x66480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x66480001 , 0x66480001 , 0x66480001 , 0x66480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300Modes_high_power_tx_gain_table_ar9580_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x15000028 , 0x15000028 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1b00002b , 0x1b00002b , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x1f020028 , 0x1f020028 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x2502002b , 0x2502002b , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2a04002a , 0x2a04002a , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2e06002a , 0x2e06002a , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x3302202d , 0x3302202d , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3804202c , 0x3804202c , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3c06202c , 0x3c06202c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4108202d , 0x4108202d , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4506402d , 0x4506402d , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4906222d , 0x4906222d , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4d062231 , 0x4d062231 , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x50082231 , 0x50082231 , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5608422e , 0x5608422e , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5e08442e , 0x5e08442e , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x620a4431 , 0x620a4431 , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x640a4432 , 0x640a4432 , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x680a4434 , 0x680a4434 , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x6c0a6434 , 0x6c0a6434 , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x6f0a6633 , 0x6f0a6633 , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x15800028 , 0x15800028 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1b80002b , 0x1b80002b , 0x12800400 , 0x12800400 }, + { 0x0000a598 , 0x1f820028 , 0x1f820028 , 0x16800402 , 0x16800402 }, + { 0x0000a59c , 0x2582002b , 0x2582002b , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2a84002a , 0x2a84002a , 0x1c800603 , 0x1c800603 }, + { 0x0000a5a4 , 0x2e86002a , 0x2e86002a , 0x21800a02 , 0x21800a02 }, + { 0x0000a5a8 , 0x3382202d , 0x3382202d , 0x25800a04 , 0x25800a04 }, + { 0x0000a5ac , 0x3884202c , 0x3884202c , 0x28800a20 , 0x28800a20 }, + { 0x0000a5b0 , 0x3c86202c , 0x3c86202c , 0x2c800e20 , 0x2c800e20 }, + { 0x0000a5b4 , 0x4188202d , 0x4188202d , 0x30800e22 , 0x30800e22 }, + { 0x0000a5b8 , 0x4586402d , 0x4586402d , 0x34800e24 , 0x34800e24 }, + { 0x0000a5bc , 0x4986222d , 0x4986222d , 0x38801640 , 0x38801640 }, + { 0x0000a5c0 , 0x4d862231 , 0x4d862231 , 0x3c801660 , 0x3c801660 }, + { 0x0000a5c4 , 0x50882231 , 0x50882231 , 0x3f801861 , 0x3f801861 }, + { 0x0000a5c8 , 0x5688422e , 0x5688422e , 0x43801a81 , 0x43801a81 }, + { 0x0000a5cc , 0x5a88442e , 0x5a88442e , 0x47801a83 , 0x47801a83 }, + { 0x0000a5d0 , 0x5e8a4431 , 0x5e8a4431 , 0x4a801c84 , 0x4a801c84 }, + { 0x0000a5d4 , 0x648a4432 , 0x648a4432 , 0x4e801ce3 , 0x4e801ce3 }, + { 0x0000a5d8 , 0x688a4434 , 0x688a4434 , 0x52801ce5 , 0x52801ce5 }, + { 0x0000a5dc , 0x6c8a6434 , 0x6c8a6434 , 0x56801ce9 , 0x56801ce9 }, + { 0x0000a5e0 , 0x6f8a6633 , 0x6f8a6633 , 0x5a801ceb , 0x5a801ceb }, + { 0x0000a5e4 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5e8 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5ec , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f0 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f4 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f8 , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a5fc , 0x738c6634 , 0x738c6634 , 0x5d801eec , 0x5d801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01804601 , 0x01804601 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01804601 , 0x01804601 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x01804601 , 0x01804601 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x03408d02 , 0x03408d02 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x03410d04 , 0x03410d04 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x65240001 , 0x65240001 , 0x66480001 , 0x66480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016288 , 0x05a2040a , 0x05a2040a , 0x05a20408 , 0x05a20408 }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x65240001 , 0x65240001 , 0x66480001 , 0x66480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x65240001 , 0x65240001 , 0x66480001 , 0x66480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300Common_rx_gain_table_merlin_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x02000101 }, + { 0x0000a004 , 0x02000102 }, + { 0x0000a008 , 0x02000103 }, + { 0x0000a00c , 0x02000104 }, + { 0x0000a010 , 0x02000200 }, + { 0x0000a014 , 0x02000201 }, + { 0x0000a018 , 0x02000202 }, + { 0x0000a01c , 0x02000203 }, + { 0x0000a020 , 0x02000204 }, + { 0x0000a024 , 0x02000205 }, + { 0x0000a028 , 0x02000208 }, + { 0x0000a02c , 0x02000302 }, + { 0x0000a030 , 0x02000303 }, + { 0x0000a034 , 0x02000304 }, + { 0x0000a038 , 0x02000400 }, + { 0x0000a03c , 0x02010300 }, + { 0x0000a040 , 0x02010301 }, + { 0x0000a044 , 0x02010302 }, + { 0x0000a048 , 0x02000500 }, + { 0x0000a04c , 0x02010400 }, + { 0x0000a050 , 0x02020300 }, + { 0x0000a054 , 0x02020301 }, + { 0x0000a058 , 0x02020302 }, + { 0x0000a05c , 0x02020303 }, + { 0x0000a060 , 0x02020400 }, + { 0x0000a064 , 0x02030300 }, + { 0x0000a068 , 0x02030301 }, + { 0x0000a06c , 0x02030302 }, + { 0x0000a070 , 0x02030303 }, + { 0x0000a074 , 0x02030400 }, + { 0x0000a078 , 0x02040300 }, + { 0x0000a07c , 0x02040301 }, + { 0x0000a080 , 0x02040302 }, + { 0x0000a084 , 0x02040303 }, + { 0x0000a088 , 0x02030500 }, + { 0x0000a08c , 0x02040400 }, + { 0x0000a090 , 0x02050203 }, + { 0x0000a094 , 0x02050204 }, + { 0x0000a098 , 0x02050205 }, + { 0x0000a09c , 0x02040500 }, + { 0x0000a0a0 , 0x02050301 }, + { 0x0000a0a4 , 0x02050302 }, + { 0x0000a0a8 , 0x02050303 }, + { 0x0000a0ac , 0x02050400 }, + { 0x0000a0b0 , 0x02050401 }, + { 0x0000a0b4 , 0x02050402 }, + { 0x0000a0b8 , 0x02050403 }, + { 0x0000a0bc , 0x02050500 }, + { 0x0000a0c0 , 0x02050501 }, + { 0x0000a0c4 , 0x02050502 }, + { 0x0000a0c8 , 0x02050503 }, + { 0x0000a0cc , 0x02050504 }, + { 0x0000a0d0 , 0x02050600 }, + { 0x0000a0d4 , 0x02050601 }, + { 0x0000a0d8 , 0x02050602 }, + { 0x0000a0dc , 0x02050603 }, + { 0x0000a0e0 , 0x02050604 }, + { 0x0000a0e4 , 0x02050700 }, + { 0x0000a0e8 , 0x02050701 }, + { 0x0000a0ec , 0x02050702 }, + { 0x0000a0f0 , 0x02050703 }, + { 0x0000a0f4 , 0x02050704 }, + { 0x0000a0f8 , 0x02050705 }, + { 0x0000a0fc , 0x02050708 }, + { 0x0000a100 , 0x02050709 }, + { 0x0000a104 , 0x0205070a }, + { 0x0000a108 , 0x0205070b }, + { 0x0000a10c , 0x0205070c }, + { 0x0000a110 , 0x0205070d }, + { 0x0000a114 , 0x02050710 }, + { 0x0000a118 , 0x02050711 }, + { 0x0000a11c , 0x02050712 }, + { 0x0000a120 , 0x02050713 }, + { 0x0000a124 , 0x02050714 }, + { 0x0000a128 , 0x02050715 }, + { 0x0000a12c , 0x02050730 }, + { 0x0000a130 , 0x02050731 }, + { 0x0000a134 , 0x02050732 }, + { 0x0000a138 , 0x02050733 }, + { 0x0000a13c , 0x02050734 }, + { 0x0000a140 , 0x02050735 }, + { 0x0000a144 , 0x02050750 }, + { 0x0000a148 , 0x02050751 }, + { 0x0000a14c , 0x02050752 }, + { 0x0000a150 , 0x02050753 }, + { 0x0000a154 , 0x02050754 }, + { 0x0000a158 , 0x02050755 }, + { 0x0000a15c , 0x02050770 }, + { 0x0000a160 , 0x02050771 }, + { 0x0000a164 , 0x02050772 }, + { 0x0000a168 , 0x02050773 }, + { 0x0000a16c , 0x02050774 }, + { 0x0000a170 , 0x02050775 }, + { 0x0000a174 , 0x00000776 }, + { 0x0000a178 , 0x00000776 }, + { 0x0000a17c , 0x00000776 }, + { 0x0000a180 , 0x00000776 }, + { 0x0000a184 , 0x00000776 }, + { 0x0000a188 , 0x00000776 }, + { 0x0000a18c , 0x00000776 }, + { 0x0000a190 , 0x00000776 }, + { 0x0000a194 , 0x00000776 }, + { 0x0000a198 , 0x00000776 }, + { 0x0000a19c , 0x00000776 }, + { 0x0000a1a0 , 0x00000776 }, + { 0x0000a1a4 , 0x00000776 }, + { 0x0000a1a8 , 0x00000776 }, + { 0x0000a1ac , 0x00000776 }, + { 0x0000a1b0 , 0x00000776 }, + { 0x0000a1b4 , 0x00000776 }, + { 0x0000a1b8 , 0x00000776 }, + { 0x0000a1bc , 0x00000776 }, + { 0x0000a1c0 , 0x00000776 }, + { 0x0000a1c4 , 0x00000776 }, + { 0x0000a1c8 , 0x00000776 }, + { 0x0000a1cc , 0x00000776 }, + { 0x0000a1d0 , 0x00000776 }, + { 0x0000a1d4 , 0x00000776 }, + { 0x0000a1d8 , 0x00000776 }, + { 0x0000a1dc , 0x00000776 }, + { 0x0000a1e0 , 0x00000776 }, + { 0x0000a1e4 , 0x00000776 }, + { 0x0000a1e8 , 0x00000776 }, + { 0x0000a1ec , 0x00000776 }, + { 0x0000a1f0 , 0x00000776 }, + { 0x0000a1f4 , 0x00000776 }, + { 0x0000a1f8 , 0x00000776 }, + { 0x0000a1fc , 0x00000776 }, + { 0x0000b000 , 0x02000101 }, + { 0x0000b004 , 0x02000102 }, + { 0x0000b008 , 0x02000103 }, + { 0x0000b00c , 0x02000104 }, + { 0x0000b010 , 0x02000200 }, + { 0x0000b014 , 0x02000201 }, + { 0x0000b018 , 0x02000202 }, + { 0x0000b01c , 0x02000203 }, + { 0x0000b020 , 0x02000204 }, + { 0x0000b024 , 0x02000205 }, + { 0x0000b028 , 0x02000208 }, + { 0x0000b02c , 0x02000302 }, + { 0x0000b030 , 0x02000303 }, + { 0x0000b034 , 0x02000304 }, + { 0x0000b038 , 0x02000400 }, + { 0x0000b03c , 0x02010300 }, + { 0x0000b040 , 0x02010301 }, + { 0x0000b044 , 0x02010302 }, + { 0x0000b048 , 0x02000500 }, + { 0x0000b04c , 0x02010400 }, + { 0x0000b050 , 0x02020300 }, + { 0x0000b054 , 0x02020301 }, + { 0x0000b058 , 0x02020302 }, + { 0x0000b05c , 0x02020303 }, + { 0x0000b060 , 0x02020400 }, + { 0x0000b064 , 0x02030300 }, + { 0x0000b068 , 0x02030301 }, + { 0x0000b06c , 0x02030302 }, + { 0x0000b070 , 0x02030303 }, + { 0x0000b074 , 0x02030400 }, + { 0x0000b078 , 0x02040300 }, + { 0x0000b07c , 0x02040301 }, + { 0x0000b080 , 0x02040302 }, + { 0x0000b084 , 0x02040303 }, + { 0x0000b088 , 0x02030500 }, + { 0x0000b08c , 0x02040400 }, + { 0x0000b090 , 0x02050203 }, + { 0x0000b094 , 0x02050204 }, + { 0x0000b098 , 0x02050205 }, + { 0x0000b09c , 0x02040500 }, + { 0x0000b0a0 , 0x02050301 }, + { 0x0000b0a4 , 0x02050302 }, + { 0x0000b0a8 , 0x02050303 }, + { 0x0000b0ac , 0x02050400 }, + { 0x0000b0b0 , 0x02050401 }, + { 0x0000b0b4 , 0x02050402 }, + { 0x0000b0b8 , 0x02050403 }, + { 0x0000b0bc , 0x02050500 }, + { 0x0000b0c0 , 0x02050501 }, + { 0x0000b0c4 , 0x02050502 }, + { 0x0000b0c8 , 0x02050503 }, + { 0x0000b0cc , 0x02050504 }, + { 0x0000b0d0 , 0x02050600 }, + { 0x0000b0d4 , 0x02050601 }, + { 0x0000b0d8 , 0x02050602 }, + { 0x0000b0dc , 0x02050603 }, + { 0x0000b0e0 , 0x02050604 }, + { 0x0000b0e4 , 0x02050700 }, + { 0x0000b0e8 , 0x02050701 }, + { 0x0000b0ec , 0x02050702 }, + { 0x0000b0f0 , 0x02050703 }, + { 0x0000b0f4 , 0x02050704 }, + { 0x0000b0f8 , 0x02050705 }, + { 0x0000b0fc , 0x02050708 }, + { 0x0000b100 , 0x02050709 }, + { 0x0000b104 , 0x0205070a }, + { 0x0000b108 , 0x0205070b }, + { 0x0000b10c , 0x0205070c }, + { 0x0000b110 , 0x0205070d }, + { 0x0000b114 , 0x02050710 }, + { 0x0000b118 , 0x02050711 }, + { 0x0000b11c , 0x02050712 }, + { 0x0000b120 , 0x02050713 }, + { 0x0000b124 , 0x02050714 }, + { 0x0000b128 , 0x02050715 }, + { 0x0000b12c , 0x02050730 }, + { 0x0000b130 , 0x02050731 }, + { 0x0000b134 , 0x02050732 }, + { 0x0000b138 , 0x02050733 }, + { 0x0000b13c , 0x02050734 }, + { 0x0000b140 , 0x02050735 }, + { 0x0000b144 , 0x02050750 }, + { 0x0000b148 , 0x02050751 }, + { 0x0000b14c , 0x02050752 }, + { 0x0000b150 , 0x02050753 }, + { 0x0000b154 , 0x02050754 }, + { 0x0000b158 , 0x02050755 }, + { 0x0000b15c , 0x02050770 }, + { 0x0000b160 , 0x02050771 }, + { 0x0000b164 , 0x02050772 }, + { 0x0000b168 , 0x02050773 }, + { 0x0000b16c , 0x02050774 }, + { 0x0000b170 , 0x02050775 }, + { 0x0000b174 , 0x00000776 }, + { 0x0000b178 , 0x00000776 }, + { 0x0000b17c , 0x00000776 }, + { 0x0000b180 , 0x00000776 }, + { 0x0000b184 , 0x00000776 }, + { 0x0000b188 , 0x00000776 }, + { 0x0000b18c , 0x00000776 }, + { 0x0000b190 , 0x00000776 }, + { 0x0000b194 , 0x00000776 }, + { 0x0000b198 , 0x00000776 }, + { 0x0000b19c , 0x00000776 }, + { 0x0000b1a0 , 0x00000776 }, + { 0x0000b1a4 , 0x00000776 }, + { 0x0000b1a8 , 0x00000776 }, + { 0x0000b1ac , 0x00000776 }, + { 0x0000b1b0 , 0x00000776 }, + { 0x0000b1b4 , 0x00000776 }, + { 0x0000b1b8 , 0x00000776 }, + { 0x0000b1bc , 0x00000776 }, + { 0x0000b1c0 , 0x00000776 }, + { 0x0000b1c4 , 0x00000776 }, + { 0x0000b1c8 , 0x00000776 }, + { 0x0000b1cc , 0x00000776 }, + { 0x0000b1d0 , 0x00000776 }, + { 0x0000b1d4 , 0x00000776 }, + { 0x0000b1d8 , 0x00000776 }, + { 0x0000b1dc , 0x00000776 }, + { 0x0000b1e0 , 0x00000776 }, + { 0x0000b1e4 , 0x00000776 }, + { 0x0000b1e8 , 0x00000776 }, + { 0x0000b1ec , 0x00000776 }, + { 0x0000b1f0 , 0x00000776 }, + { 0x0000b1f4 , 0x00000776 }, + { 0x0000b1f8 , 0x00000776 }, + { 0x0000b1fc , 0x00000776 }, +}; + +static const u_int32_t ar9300_modes_type5_tx_gain_table_ar9580_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x15000028 , 0x15000028 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1b00002b , 0x1b00002b , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x1f020028 , 0x1f020028 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x2502002b , 0x2502002b , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2a04002a , 0x2a04002a , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2e06002a , 0x2e06002a , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x3302202d , 0x3302202d , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3804202c , 0x3804202c , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3c06202c , 0x3c06202c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4108202d , 0x4108202d , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4506402d , 0x4506402d , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4906222d , 0x4906222d , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4d062231 , 0x4d062231 , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x50082231 , 0x50082231 , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5608422e , 0x5608422e , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5e08442e , 0x5e08442e , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x620a4431 , 0x620a4431 , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x640a4432 , 0x640a4432 , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x680a4434 , 0x680a4434 , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x6c0a6434 , 0x6c0a6434 , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x6f0a6633 , 0x6f0a6633 , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01804601 , 0x01804601 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01804601 , 0x01804601 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x01804601 , 0x01804601 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x03408d02 , 0x03408d02 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x03410d04 , 0x03410d04 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x65240001 , 0x65240001 , 0x66480001 , 0x66480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x65240001 , 0x65240001 , 0x66480001 , 0x66480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x65240001 , 0x65240001 , 0x66480001 , 0x66480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5c02486b , 0x5c02486b , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x61024a6c , 0x61024a6c , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x66026a6c , 0x66026a6c , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x6b026e6c , 0x6b026e6c , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x7002708c , 0x7002708c , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x7302b08a , 0x7302b08a , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x7702b08c , 0x7702b08c , 0x5d001eec , 0x5d001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x12800400 , 0x12800400 }, + { 0x0000a598 , 0x21802220 , 0x21802220 , 0x16800402 , 0x16800402 }, + { 0x0000a59c , 0x27802223 , 0x27802223 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1c800603 , 0x1c800603 }, + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x21800a02 , 0x21800a02 }, + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x25800a04 , 0x25800a04 }, + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x28800a20 , 0x28800a20 }, + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2c800e20 , 0x2c800e20 }, + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x30800e22 , 0x30800e22 }, + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x34800e24 , 0x34800e24 }, + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x38801640 , 0x38801640 }, + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x3c801660 , 0x3c801660 }, + { 0x0000a5c4 , 0x5382266c , 0x5382266c , 0x3f801861 , 0x3f801861 }, + { 0x0000a5c8 , 0x5782286c , 0x5782286c , 0x43801a81 , 0x43801a81 }, + { 0x0000a5cc , 0x5c82486b , 0x5c82486b , 0x47801a83 , 0x47801a83 }, + { 0x0000a5d0 , 0x61824a6c , 0x61824a6c , 0x4a801c84 , 0x4a801c84 }, + { 0x0000a5d4 , 0x66826a6c , 0x66826a6c , 0x4e801ce3 , 0x4e801ce3 }, + { 0x0000a5d8 , 0x6b826e6c , 0x6b826e6c , 0x52801ce5 , 0x52801ce5 }, + { 0x0000a5dc , 0x7082708c , 0x7082708c , 0x56801ce9 , 0x56801ce9 }, + { 0x0000a5e0 , 0x7382b08a , 0x7382b08a , 0x5a801ceb , 0x5a801ceb }, + { 0x0000a5e4 , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5e8 , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5ec , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f0 , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f4 , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5f8 , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a5fc , 0x7782b08c , 0x7782b08c , 0x5d801eec , 0x5d801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0300cc03 , 0x0300cc03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x0300cc03 , 0x0300cc03 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03810c03 , 0x03810c03 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x62480001 , 0x62480001 , 0x62480001 , 0x62480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x62480001 , 0x62480001 , 0x62480001 , 0x62480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x62480001 , 0x62480001 , 0x62480001 , 0x62480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { +/* Addr allmodes */ + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x6f7f0301 }, + { 0x0000a3a0 , 0xca9228ee }, +}; + +static const u_int32_t ar9300_ar9580_1p0_mac_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00008014 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 , 0x10f810f8 }, + { 0x0000801c , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 , 0x0e8d8017 }, +}; + +static const u_int32_t ar9200_merlin_1p0_radio_core[][2] = { +/* Addr common */ + { 0x00007800 , 0x00040000 }, + { 0x00007804 , 0xdb005012 }, + { 0x00007808 , 0x04924914 }, + { 0x0000780c , 0x21084210 }, + { 0x00007810 , 0x6d801300 }, + { 0x00007814 , 0x0019beff }, + { 0x00007818 , 0x07e41000 }, + { 0x0000781c , 0x00392000 }, + { 0x00007820 , 0x92592480 }, + { 0x00007824 , 0x00040000 }, + { 0x00007828 , 0xdb005012 }, + { 0x0000782c , 0x04924914 }, + { 0x00007830 , 0x21084210 }, + { 0x00007834 , 0x6d801300 }, + { 0x00007838 , 0x0019beff }, + { 0x0000783c , 0x07e40000 }, + { 0x00007840 , 0x00392000 }, + { 0x00007844 , 0x92592480 }, + { 0x00007848 , 0x00100000 }, + { 0x0000784c , 0x773f0567 }, + { 0x00007850 , 0x54214514 }, + { 0x00007854 , 0x12035828 }, + { 0x00007858 , 0x92592692 }, + { 0x0000785c , 0x00000000 }, + { 0x00007860 , 0x56400000 }, + { 0x00007864 , 0x0a8e370e }, + { 0x00007868 , 0xc0102850 }, + { 0x0000786c , 0x812d4000 }, + { 0x00007870 , 0x807ec400 }, + { 0x00007874 , 0x001b6db0 }, + { 0x00007878 , 0x00376b63 }, + { 0x0000787c , 0x06db6db6 }, + { 0x00007880 , 0x006d8000 }, + { 0x00007884 , 0xffeffffe }, + { 0x00007888 , 0xffeffffe }, + { 0x0000788c , 0x00010000 }, + { 0x00007890 , 0x02060aeb }, + { 0x00007894 , 0x5a108000 }, +}; + +static const u_int32_t ar9300_ar9580_1p0_tx_gain_table_baseband_postamble_emulation[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a410 , 0x000000d5 , 0x000000d5 , 0x000000d5 , 0x000000d5 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x00004002 , 0x00004002 , 0x00004002 , 0x00004002 }, + { 0x0000a508 , 0x00008004 , 0x00008004 , 0x00008004 , 0x00008004 }, + { 0x0000a510 , 0x0001000c , 0x0001000c , 0x0001000c , 0x0001000c }, + { 0x0000a514 , 0x0001420b , 0x0001420b , 0x0001420b , 0x0001420b }, + { 0x0000a518 , 0x0001824a , 0x0001824a , 0x0001824a , 0x0001824a }, + { 0x0000a51c , 0x0001c44a , 0x0001c44a , 0x0001c44a , 0x0001c44a }, + { 0x0000a520 , 0x0002064a , 0x0002064a , 0x0002064a , 0x0002064a }, + { 0x0000a524 , 0x0002484a , 0x0002484a , 0x0002484a , 0x0002484a }, + { 0x0000a528 , 0x00028a4a , 0x00028a4a , 0x00028a4a , 0x00028a4a }, + { 0x0000a52c , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a , 0x0002cc4a }, + { 0x0000a530 , 0x00030e4a , 0x00030e4a , 0x00030e4a , 0x00030e4a }, + { 0x0000a534 , 0x00034e8a , 0x00034e8a , 0x00034e8a , 0x00034e8a }, +}; + +static const u_int32_t ar9300_ar9580_1p0_mac_core[][2] = { +/* Addr allmodes */ + { 0x00000008 , 0x00000000 }, + { 0x00000030 , 0x00020085 }, + { 0x00000034 , 0x00000005 }, + { 0x00000040 , 0x00000000 }, + { 0x00000044 , 0x00000000 }, + { 0x00000048 , 0x00000008 }, + { 0x0000004c , 0x00000010 }, + { 0x00000050 , 0x00000000 }, + { 0x00001040 , 0x002ffc0f }, + { 0x00001044 , 0x002ffc0f }, + { 0x00001048 , 0x002ffc0f }, + { 0x0000104c , 0x002ffc0f }, + { 0x00001050 , 0x002ffc0f }, + { 0x00001054 , 0x002ffc0f }, + { 0x00001058 , 0x002ffc0f }, + { 0x0000105c , 0x002ffc0f }, + { 0x00001060 , 0x002ffc0f }, + { 0x00001064 , 0x002ffc0f }, + { 0x000010f0 , 0x00000100 }, + { 0x00001270 , 0x00000000 }, + { 0x000012b0 , 0x00000000 }, + { 0x000012f0 , 0x00000000 }, + { 0x0000143c , 0x00000000 }, + { 0x0000147c , 0x00000000 }, + { 0x00008000 , 0x00000000 }, + { 0x00008004 , 0x00000000 }, + { 0x00008008 , 0x00000000 }, + { 0x0000800c , 0x00000000 }, + { 0x00008018 , 0x00000000 }, + { 0x00008020 , 0x00000000 }, + { 0x00008038 , 0x00000000 }, + { 0x0000803c , 0x00000000 }, + { 0x00008040 , 0x00000000 }, + { 0x00008044 , 0x00000000 }, + { 0x00008048 , 0x00000000 }, + { 0x0000804c , 0xffffffff }, + { 0x00008054 , 0x00000000 }, + { 0x00008058 , 0x00000000 }, + { 0x0000805c , 0x000fc78f }, + { 0x00008060 , 0x0000000f }, + { 0x00008064 , 0x00000000 }, + { 0x00008070 , 0x00000310 }, + { 0x00008074 , 0x00000020 }, + { 0x00008078 , 0x00000000 }, + { 0x0000809c , 0x0000000f }, + { 0x000080a0 , 0x00000000 }, + { 0x000080a4 , 0x02ff0000 }, + { 0x000080a8 , 0x0e070605 }, + { 0x000080ac , 0x0000000d }, + { 0x000080b0 , 0x00000000 }, + { 0x000080b4 , 0x00000000 }, + { 0x000080b8 , 0x00000000 }, + { 0x000080bc , 0x00000000 }, + { 0x000080c0 , 0x2a800000 }, + { 0x000080c4 , 0x06900168 }, + { 0x000080c8 , 0x13881c22 }, + { 0x000080cc , 0x01f40000 }, + { 0x000080d0 , 0x00252500 }, + { 0x000080d4 , 0x00a00000 }, + { 0x000080d8 , 0x00400000 }, + { 0x000080dc , 0x00000000 }, + { 0x000080e0 , 0xffffffff }, + { 0x000080e4 , 0x0000ffff }, + { 0x000080e8 , 0x3f3f3f3f }, + { 0x000080ec , 0x00000000 }, + { 0x000080f0 , 0x00000000 }, + { 0x000080f4 , 0x00000000 }, + { 0x000080fc , 0x00020000 }, + { 0x00008100 , 0x00000000 }, + { 0x00008108 , 0x00000052 }, + { 0x0000810c , 0x00000000 }, + { 0x00008110 , 0x00000000 }, + { 0x00008114 , 0x000007ff }, + { 0x00008118 , 0x000000aa }, + { 0x0000811c , 0x00003210 }, + { 0x00008124 , 0x00000000 }, + { 0x00008128 , 0x00000000 }, + { 0x0000812c , 0x00000000 }, + { 0x00008130 , 0x00000000 }, + { 0x00008134 , 0x00000000 }, + { 0x00008138 , 0x00000000 }, + { 0x0000813c , 0x0000ffff }, + { 0x00008144 , 0xffffffff }, + { 0x00008168 , 0x00000000 }, + { 0x0000816c , 0x00000000 }, + { 0x000081c0 , 0x00000000 }, + { 0x000081c4 , 0x33332210 }, + { 0x000081ec , 0x00000000 }, + { 0x000081f0 , 0x00000000 }, + { 0x000081f4 , 0x00000000 }, + { 0x000081f8 , 0x00000000 }, + { 0x000081fc , 0x00000000 }, + { 0x00008240 , 0x00100000 }, + { 0x00008244 , 0x0010f400 }, + { 0x00008248 , 0x00000800 }, + { 0x0000824c , 0x0001e800 }, + { 0x00008250 , 0x00000000 }, + { 0x00008254 , 0x00000000 }, + { 0x00008258 , 0x00000000 }, + { 0x0000825c , 0x40000000 }, + { 0x00008260 , 0x00080922 }, + { 0x00008264 , 0x9bc00010 }, + { 0x00008268 , 0xffffffff }, + { 0x0000826c , 0x0000ffff }, + { 0x00008270 , 0x00000000 }, + { 0x00008274 , 0x40000000 }, + { 0x00008278 , 0x003e4180 }, + { 0x0000827c , 0x00000004 }, + { 0x00008284 , 0x0000002c }, + { 0x00008288 , 0x0000002c }, + { 0x0000828c , 0x000000ff }, + { 0x00008294 , 0x00000000 }, + { 0x00008298 , 0x00000000 }, + { 0x0000829c , 0x00000000 }, + { 0x00008300 , 0x00000140 }, + { 0x00008314 , 0x00000000 }, + { 0x0000831c , 0x0000010d }, + { 0x00008328 , 0x00000000 }, + { 0x0000832c , 0x00000007 }, + { 0x00008330 , 0x00000302 }, + { 0x00008334 , 0x00000700 }, + { 0x00008338 , 0x00ff0000 }, + { 0x0000833c , 0x02400000 }, + { 0x00008340 , 0x000107ff }, + { 0x00008344 , 0xaa48105b }, + { 0x00008348 , 0x008f0000 }, + { 0x0000835c , 0x00000000 }, + { 0x00008360 , 0xffffffff }, + { 0x00008364 , 0xffffffff }, + { 0x00008368 , 0x00000000 }, + { 0x00008370 , 0x00000000 }, + { 0x00008374 , 0x000000ff }, + { 0x00008378 , 0x00000000 }, + { 0x0000837c , 0x00000000 }, + { 0x00008380 , 0xffffffff }, + { 0x00008384 , 0xffffffff }, + { 0x00008390 , 0xffffffff }, + { 0x00008394 , 0xffffffff }, + { 0x00008398 , 0x00000000 }, + { 0x0000839c , 0x00000000 }, + { 0x000083a0 , 0x00000000 }, + { 0x000083a4 , 0x0000fa14 }, + { 0x000083a8 , 0x000f0c00 }, + { 0x000083ac , 0x33332210 }, + { 0x000083b0 , 0x33332210 }, + { 0x000083b4 , 0x33332210 }, + { 0x000083b8 , 0x33332210 }, + { 0x000083bc , 0x00000000 }, + { 0x000083c0 , 0x00000000 }, + { 0x000083c4 , 0x00000000 }, + { 0x000083c8 , 0x00000000 }, + { 0x000083cc , 0x00000200 }, + { 0x000083d0 , 0x000301ff }, +}; + +static const u_int32_t ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x16000220 , 0x16000220 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1c000223 , 0x1c000223 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x21002220 , 0x21002220 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x27002223 , 0x27002223 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2b022220 , 0x2b022220 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x2f022222 , 0x2f022222 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x34022225 , 0x34022225 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x3a02222a , 0x3a02222a , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x3e02222c , 0x3e02222c , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x4202242a , 0x4202242a , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x4702244a , 0x4702244a , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x4b02244c , 0x4b02244c , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x4e02246c , 0x4e02246c , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x5302266c , 0x5302266c , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x5702286c , 0x5702286c , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x5c02486b , 0x5c02486b , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x61024a6c , 0x61024a6c , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x66026a6c , 0x66026a6c , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x6b026e6c , 0x6b026e6c , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x7002708c , 0x7002708c , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x7302b08a , 0x7302b08a , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x7702b08c , 0x7702b08c , 0x56001eec , 0x56001eec }, + { 0x0000a580 , 0x00800000 , 0x00800000 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x06800003 , 0x06800003 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x0a800020 , 0x0a800020 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x10800023 , 0x10800023 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x16800220 , 0x16800220 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x1c800223 , 0x1c800223 , 0x11800400 , 0x11800400 }, + { 0x0000a598 , 0x21802220 , 0x21802220 , 0x15800402 , 0x15800402 }, + { 0x0000a59c , 0x27802223 , 0x27802223 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x2b822220 , 0x2b822220 , 0x1b800603 , 0x1b800603 }, + { 0x0000a5a4 , 0x2f822222 , 0x2f822222 , 0x1f800a02 , 0x1f800a02 }, + { 0x0000a5a8 , 0x34822225 , 0x34822225 , 0x23800a04 , 0x23800a04 }, + { 0x0000a5ac , 0x3a82222a , 0x3a82222a , 0x26800a20 , 0x26800a20 }, + { 0x0000a5b0 , 0x3e82222c , 0x3e82222c , 0x2a800e20 , 0x2a800e20 }, + { 0x0000a5b4 , 0x4282242a , 0x4282242a , 0x2e800e22 , 0x2e800e22 }, + { 0x0000a5b8 , 0x4782244a , 0x4782244a , 0x31800e24 , 0x31800e24 }, + { 0x0000a5bc , 0x4b82244c , 0x4b82244c , 0x34801640 , 0x34801640 }, + { 0x0000a5c0 , 0x4e82246c , 0x4e82246c , 0x38801660 , 0x38801660 }, + { 0x0000a5c4 , 0x5382266c , 0x5382266c , 0x3b801861 , 0x3b801861 }, + { 0x0000a5c8 , 0x5782286c , 0x5782286c , 0x3e801a81 , 0x3e801a81 }, + { 0x0000a5cc , 0x5c82486b , 0x5c82486b , 0x42801a83 , 0x42801a83 }, + { 0x0000a5d0 , 0x61824a6c , 0x61824a6c , 0x44801c84 , 0x44801c84 }, + { 0x0000a5d4 , 0x66826a6c , 0x66826a6c , 0x48801ce3 , 0x48801ce3 }, + { 0x0000a5d8 , 0x6b826e6c , 0x6b826e6c , 0x4c801ce5 , 0x4c801ce5 }, + { 0x0000a5dc , 0x7082708c , 0x7082708c , 0x50801ce9 , 0x50801ce9 }, + { 0x0000a5e0 , 0x7382b08a , 0x7382b08a , 0x54801ceb , 0x54801ceb }, + { 0x0000a5e4 , 0x7782b08c , 0x7782b08c , 0x56801eec , 0x56801eec }, + { 0x0000a5e8 , 0x7782b08c , 0x7782b08c , 0x56801eec , 0x56801eec }, + { 0x0000a5ec , 0x7782b08c , 0x7782b08c , 0x56801eec , 0x56801eec }, + { 0x0000a5f0 , 0x7782b08c , 0x7782b08c , 0x56801eec , 0x56801eec }, + { 0x0000a5f4 , 0x7782b08c , 0x7782b08c , 0x56801eec , 0x56801eec }, + { 0x0000a5f8 , 0x7782b08c , 0x7782b08c , 0x56801eec , 0x56801eec }, + { 0x0000a5fc , 0x7782b08c , 0x7782b08c , 0x56801eec , 0x56801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01404000 , 0x01404000 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01404501 , 0x01404501 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x02008802 , 0x02008802 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x0300cc03 , 0x0300cc03 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x0300cc03 , 0x0300cc03 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03810c03 , 0x03810c03 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03810e04 , 0x03810e04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x0380c7fc , 0x0380c7fc , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0000f800 , 0x0000f800 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03ff0000 , 0x03ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016048 , 0x66480001 , 0x66480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016448 , 0x66480001 , 0x66480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016848 , 0x66480001 , 0x66480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300_ar9580_1p0_mac_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00000030 , 0x00020085 }, + { 0x00000044 , 0x00000008 }, + { 0x0000805c , 0xffffc7ff }, + { 0x00008344 , 0xaa4a105b }, +}; + +static const u_int32_t ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x03820190 }, + { 0x0000a030 , 0x03840383 }, + { 0x0000a034 , 0x03880385 }, + { 0x0000a038 , 0x038a0389 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x29292929 }, + { 0x0000a084 , 0x29292929 }, + { 0x0000a088 , 0x29292929 }, + { 0x0000a08c , 0x29292929 }, + { 0x0000a090 , 0x22292929 }, + { 0x0000a094 , 0x1d1d2222 }, + { 0x0000a098 , 0x0c111117 }, + { 0x0000a09c , 0x00030303 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x32323232 }, + { 0x0000b084 , 0x2f2f3232 }, + { 0x0000b088 , 0x23282a2d }, + { 0x0000b08c , 0x1c1e2123 }, + { 0x0000b090 , 0x14171919 }, + { 0x0000b094 , 0x0e0e1214 }, + { 0x0000b098 , 0x03050707 }, + { 0x0000b09c , 0x00030303 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar9300_ar9580_1p0_soc_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00007010 , 0x00000023 , 0x00000023 , 0x00000023 , 0x00000023 }, +}; + +static const u_int32_t ar9300_modes_type6_tx_gain_table_ar9580_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d9 , 0x000050d9 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x06000003 , 0x06000003 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x0a000020 , 0x0a000020 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x10000023 , 0x10000023 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x15000028 , 0x15000028 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x1b00002b , 0x1b00002b , 0x12000400 , 0x12000400 }, + { 0x0000a518 , 0x1f020028 , 0x1f020028 , 0x16000402 , 0x16000402 }, + { 0x0000a51c , 0x2502002b , 0x2502002b , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x2a04002a , 0x2a04002a , 0x1c000603 , 0x1c000603 }, + { 0x0000a524 , 0x2e06002a , 0x2e06002a , 0x21000a02 , 0x21000a02 }, + { 0x0000a528 , 0x3302202d , 0x3302202d , 0x25000a04 , 0x25000a04 }, + { 0x0000a52c , 0x3804202c , 0x3804202c , 0x28000a20 , 0x28000a20 }, + { 0x0000a530 , 0x3c06202c , 0x3c06202c , 0x2c000e20 , 0x2c000e20 }, + { 0x0000a534 , 0x4108202d , 0x4108202d , 0x30000e22 , 0x30000e22 }, + { 0x0000a538 , 0x4506402d , 0x4506402d , 0x34000e24 , 0x34000e24 }, + { 0x0000a53c , 0x4906222d , 0x4906222d , 0x38001640 , 0x38001640 }, + { 0x0000a540 , 0x4d062231 , 0x4d062231 , 0x3c001660 , 0x3c001660 }, + { 0x0000a544 , 0x50082231 , 0x50082231 , 0x3f001861 , 0x3f001861 }, + { 0x0000a548 , 0x5608422e , 0x5608422e , 0x43001a81 , 0x43001a81 }, + { 0x0000a54c , 0x5e08442e , 0x5e08442e , 0x47001a83 , 0x47001a83 }, + { 0x0000a550 , 0x620a4431 , 0x620a4431 , 0x4a001c84 , 0x4a001c84 }, + { 0x0000a554 , 0x640a4432 , 0x640a4432 , 0x4e001ce3 , 0x4e001ce3 }, + { 0x0000a558 , 0x680a4434 , 0x680a4434 , 0x52001ce5 , 0x52001ce5 }, + { 0x0000a55c , 0x6c0a6434 , 0x6c0a6434 , 0x56001ce9 , 0x56001ce9 }, + { 0x0000a560 , 0x6f0a6633 , 0x6f0a6633 , 0x5a001ceb , 0x5a001ceb }, + { 0x0000a564 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a568 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a56c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a570 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a574 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a578 , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a57c , 0x730c6634 , 0x730c6634 , 0x5d001eec , 0x5d001eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x01804601 , 0x01804601 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x01804601 , 0x01804601 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x01804601 , 0x01804601 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x01804601 , 0x01804601 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x03408d02 , 0x03408d02 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x0300cc03 , 0x0300cc03 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x03410d04 , 0x03410d04 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x03410d04 , 0x03410d04 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x000cfff0 , 0x000cfff0 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x000f0000 , 0x000f0000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x03f00000 , 0x03f00000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016048 , 0x61200001 , 0x61200001 , 0x66480001 , 0x66480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016448 , 0x61200001 , 0x61200001 , 0x66480001 , 0x66480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x012492d4 , 0x012492d4 , 0x012492d4 , 0x012492d4 }, + { 0x00016848 , 0x61200001 , 0x61200001 , 0x66480001 , 0x66480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x0000a2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000a2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000a2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000a2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000a410 , 0x000050d4 , 0x000050d4 , 0x000050d9 , 0x000050d9 }, + { 0x0000a500 , 0x00002220 , 0x00002220 , 0x00000000 , 0x00000000 }, + { 0x0000a504 , 0x04002222 , 0x04002222 , 0x04000002 , 0x04000002 }, + { 0x0000a508 , 0x09002421 , 0x09002421 , 0x08000004 , 0x08000004 }, + { 0x0000a50c , 0x0d002621 , 0x0d002621 , 0x0b000200 , 0x0b000200 }, + { 0x0000a510 , 0x13004620 , 0x13004620 , 0x0f000202 , 0x0f000202 }, + { 0x0000a514 , 0x19004a20 , 0x19004a20 , 0x11000400 , 0x11000400 }, + { 0x0000a518 , 0x1d004e20 , 0x1d004e20 , 0x15000402 , 0x15000402 }, + { 0x0000a51c , 0x21005420 , 0x21005420 , 0x19000404 , 0x19000404 }, + { 0x0000a520 , 0x26005e20 , 0x26005e20 , 0x1b000603 , 0x1b000603 }, + { 0x0000a524 , 0x2b005e40 , 0x2b005e40 , 0x1f000a02 , 0x1f000a02 }, + { 0x0000a528 , 0x2f005e42 , 0x2f005e42 , 0x23000a04 , 0x23000a04 }, + { 0x0000a52c , 0x33005e44 , 0x33005e44 , 0x26000a20 , 0x26000a20 }, + { 0x0000a530 , 0x38005e65 , 0x38005e65 , 0x2a000e20 , 0x2a000e20 }, + { 0x0000a534 , 0x3c005e69 , 0x3c005e69 , 0x2e000e22 , 0x2e000e22 }, + { 0x0000a538 , 0x40005e6b , 0x40005e6b , 0x31000e24 , 0x31000e24 }, + { 0x0000a53c , 0x44005e6d , 0x44005e6d , 0x34001640 , 0x34001640 }, + { 0x0000a540 , 0x49005e72 , 0x49005e72 , 0x38001660 , 0x38001660 }, + { 0x0000a544 , 0x4e005eb2 , 0x4e005eb2 , 0x3b001861 , 0x3b001861 }, + { 0x0000a548 , 0x53005f12 , 0x53005f12 , 0x3e001a81 , 0x3e001a81 }, + { 0x0000a54c , 0x59025eb2 , 0x59025eb2 , 0x42001a83 , 0x42001a83 }, + { 0x0000a550 , 0x5e025f12 , 0x5e025f12 , 0x44001c84 , 0x44001c84 }, + { 0x0000a554 , 0x61027f12 , 0x61027f12 , 0x48001ce3 , 0x48001ce3 }, + { 0x0000a558 , 0x6702bf12 , 0x6702bf12 , 0x4c001ce5 , 0x4c001ce5 }, + { 0x0000a55c , 0x6b02bf14 , 0x6b02bf14 , 0x50001ce9 , 0x50001ce9 }, + { 0x0000a560 , 0x6f02bf16 , 0x6f02bf16 , 0x54001ceb , 0x54001ceb }, + { 0x0000a564 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a568 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a56c , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a570 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a574 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a578 , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a57c , 0x6f02bf16 , 0x6f02bf16 , 0x56001eec , 0x56001eec }, + { 0x0000a580 , 0x00802220 , 0x00802220 , 0x00800000 , 0x00800000 }, + { 0x0000a584 , 0x04802222 , 0x04802222 , 0x04800002 , 0x04800002 }, + { 0x0000a588 , 0x09802421 , 0x09802421 , 0x08800004 , 0x08800004 }, + { 0x0000a58c , 0x0d802621 , 0x0d802621 , 0x0b800200 , 0x0b800200 }, + { 0x0000a590 , 0x13804620 , 0x13804620 , 0x0f800202 , 0x0f800202 }, + { 0x0000a594 , 0x19804a20 , 0x19804a20 , 0x11800400 , 0x11800400 }, + { 0x0000a598 , 0x1d804e20 , 0x1d804e20 , 0x15800402 , 0x15800402 }, + { 0x0000a59c , 0x21805420 , 0x21805420 , 0x19800404 , 0x19800404 }, + { 0x0000a5a0 , 0x26805e20 , 0x26805e20 , 0x1b800603 , 0x1b800603 }, + { 0x0000a5a4 , 0x2b805e40 , 0x2b805e40 , 0x1f800a02 , 0x1f800a02 }, + { 0x0000a5a8 , 0x2f805e42 , 0x2f805e42 , 0x23800a04 , 0x23800a04 }, + { 0x0000a5ac , 0x33805e44 , 0x33805e44 , 0x26800a20 , 0x26800a20 }, + { 0x0000a5b0 , 0x38805e65 , 0x38805e65 , 0x2a800e20 , 0x2a800e20 }, + { 0x0000a5b4 , 0x3c805e69 , 0x3c805e69 , 0x2e800e22 , 0x2e800e22 }, + { 0x0000a5b8 , 0x40805e6b , 0x40805e6b , 0x31800e24 , 0x31800e24 }, + { 0x0000a5bc , 0x44805e6d , 0x44805e6d , 0x34801640 , 0x34801640 }, + { 0x0000a5c0 , 0x49805e72 , 0x49805e72 , 0x38801660 , 0x38801660 }, + { 0x0000a5c4 , 0x4e805eb2 , 0x4e805eb2 , 0x3b801861 , 0x3b801861 }, + { 0x0000a5c8 , 0x53805f12 , 0x53805f12 , 0x3e801a81 , 0x3e801a81 }, + { 0x0000a5cc , 0x59825eb2 , 0x59825eb2 , 0x42801a83 , 0x42801a83 }, + { 0x0000a5d0 , 0x5e825f12 , 0x5e825f12 , 0x44801c84 , 0x44801c84 }, + { 0x0000a5d4 , 0x61827f12 , 0x61827f12 , 0x48801ce3 , 0x48801ce3 }, + { 0x0000a5d8 , 0x6782bf12 , 0x6782bf12 , 0x4c801ce5 , 0x4c801ce5 }, + { 0x0000a5dc , 0x6b82bf14 , 0x6b82bf14 , 0x50801ce9 , 0x50801ce9 }, + { 0x0000a5e0 , 0x6f82bf16 , 0x6f82bf16 , 0x54801ceb , 0x54801ceb }, + { 0x0000a5e4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5e8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5ec , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5f0 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5f4 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5f8 , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a5fc , 0x6f82bf16 , 0x6f82bf16 , 0x56801eec , 0x56801eec }, + { 0x0000a600 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a604 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a608 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a60c , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a610 , 0x00804000 , 0x00804000 , 0x00000000 , 0x00000000 }, + { 0x0000a614 , 0x00804201 , 0x00804201 , 0x01404000 , 0x01404000 }, + { 0x0000a618 , 0x0280c802 , 0x0280c802 , 0x01404501 , 0x01404501 }, + { 0x0000a61c , 0x0280ca03 , 0x0280ca03 , 0x02008501 , 0x02008501 }, + { 0x0000a620 , 0x04c15104 , 0x04c15104 , 0x0280ca03 , 0x0280ca03 }, + { 0x0000a624 , 0x04c15305 , 0x04c15305 , 0x03010c04 , 0x03010c04 }, + { 0x0000a628 , 0x04c15305 , 0x04c15305 , 0x04014c04 , 0x04014c04 }, + { 0x0000a62c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a630 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a634 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a638 , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000a63c , 0x04c15305 , 0x04c15305 , 0x04015005 , 0x04015005 }, + { 0x0000b2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000b2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000b2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000b2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x0000c2dc , 0x01feee00 , 0x01feee00 , 0x03aaa352 , 0x03aaa352 }, + { 0x0000c2e0 , 0x0000f000 , 0x0000f000 , 0x03ccc584 , 0x03ccc584 }, + { 0x0000c2e4 , 0x01ff0000 , 0x01ff0000 , 0x03f0f800 , 0x03f0f800 }, + { 0x0000c2e8 , 0x00000000 , 0x00000000 , 0x03ff0000 , 0x03ff0000 }, + { 0x00016044 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016048 , 0x8e480001 , 0x8e480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016068 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016444 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016448 , 0x8e480001 , 0x8e480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016468 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, + { 0x00016844 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 , 0x056db2e4 }, + { 0x00016848 , 0x8e480001 , 0x8e480001 , 0x8e480001 , 0x8e480001 }, + { 0x00016868 , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c , 0x6db6db6c }, +}; + +static const u_int32_t ar9300_ar9580_1p0_soc_preamble[][2] = { +/* Addr allmodes */ + { 0x000040a4 , 0x00a0c1c9 }, + { 0x00007008 , 0x00000000 }, + { 0x00007020 , 0x00000000 }, + { 0x00007034 , 0x00000002 }, + { 0x00007038 , 0x000004c2 }, + { 0x00007048 , 0x00000008 }, +}; + +static const u_int32_t ar9300_common_rx_gain_table_ar9580_1p0[][2] = { +/* Addr allmodes */ + { 0x0000a000 , 0x00010000 }, + { 0x0000a004 , 0x00030002 }, + { 0x0000a008 , 0x00050004 }, + { 0x0000a00c , 0x00810080 }, + { 0x0000a010 , 0x00830082 }, + { 0x0000a014 , 0x01810180 }, + { 0x0000a018 , 0x01830182 }, + { 0x0000a01c , 0x01850184 }, + { 0x0000a020 , 0x01890188 }, + { 0x0000a024 , 0x018b018a }, + { 0x0000a028 , 0x018d018c }, + { 0x0000a02c , 0x01910190 }, + { 0x0000a030 , 0x01930192 }, + { 0x0000a034 , 0x01950194 }, + { 0x0000a038 , 0x038a0196 }, + { 0x0000a03c , 0x038c038b }, + { 0x0000a040 , 0x0390038d }, + { 0x0000a044 , 0x03920391 }, + { 0x0000a048 , 0x03940393 }, + { 0x0000a04c , 0x03960395 }, + { 0x0000a050 , 0x00000000 }, + { 0x0000a054 , 0x00000000 }, + { 0x0000a058 , 0x00000000 }, + { 0x0000a05c , 0x00000000 }, + { 0x0000a060 , 0x00000000 }, + { 0x0000a064 , 0x00000000 }, + { 0x0000a068 , 0x00000000 }, + { 0x0000a06c , 0x00000000 }, + { 0x0000a070 , 0x00000000 }, + { 0x0000a074 , 0x00000000 }, + { 0x0000a078 , 0x00000000 }, + { 0x0000a07c , 0x00000000 }, + { 0x0000a080 , 0x22222229 }, + { 0x0000a084 , 0x1d1d1d1d }, + { 0x0000a088 , 0x1d1d1d1d }, + { 0x0000a08c , 0x1d1d1d1d }, + { 0x0000a090 , 0x171d1d1d }, + { 0x0000a094 , 0x11111717 }, + { 0x0000a098 , 0x00030311 }, + { 0x0000a09c , 0x00000000 }, + { 0x0000a0a0 , 0x00000000 }, + { 0x0000a0a4 , 0x00000000 }, + { 0x0000a0a8 , 0x00000000 }, + { 0x0000a0ac , 0x00000000 }, + { 0x0000a0b0 , 0x00000000 }, + { 0x0000a0b4 , 0x00000000 }, + { 0x0000a0b8 , 0x00000000 }, + { 0x0000a0bc , 0x00000000 }, + { 0x0000a0c0 , 0x001f0000 }, + { 0x0000a0c4 , 0x01000101 }, + { 0x0000a0c8 , 0x011e011f }, + { 0x0000a0cc , 0x011c011d }, + { 0x0000a0d0 , 0x02030204 }, + { 0x0000a0d4 , 0x02010202 }, + { 0x0000a0d8 , 0x021f0200 }, + { 0x0000a0dc , 0x0302021e }, + { 0x0000a0e0 , 0x03000301 }, + { 0x0000a0e4 , 0x031e031f }, + { 0x0000a0e8 , 0x0402031d }, + { 0x0000a0ec , 0x04000401 }, + { 0x0000a0f0 , 0x041e041f }, + { 0x0000a0f4 , 0x0502041d }, + { 0x0000a0f8 , 0x05000501 }, + { 0x0000a0fc , 0x051e051f }, + { 0x0000a100 , 0x06010602 }, + { 0x0000a104 , 0x061f0600 }, + { 0x0000a108 , 0x061d061e }, + { 0x0000a10c , 0x07020703 }, + { 0x0000a110 , 0x07000701 }, + { 0x0000a114 , 0x00000000 }, + { 0x0000a118 , 0x00000000 }, + { 0x0000a11c , 0x00000000 }, + { 0x0000a120 , 0x00000000 }, + { 0x0000a124 , 0x00000000 }, + { 0x0000a128 , 0x00000000 }, + { 0x0000a12c , 0x00000000 }, + { 0x0000a130 , 0x00000000 }, + { 0x0000a134 , 0x00000000 }, + { 0x0000a138 , 0x00000000 }, + { 0x0000a13c , 0x00000000 }, + { 0x0000a140 , 0x001f0000 }, + { 0x0000a144 , 0x01000101 }, + { 0x0000a148 , 0x011e011f }, + { 0x0000a14c , 0x011c011d }, + { 0x0000a150 , 0x02030204 }, + { 0x0000a154 , 0x02010202 }, + { 0x0000a158 , 0x021f0200 }, + { 0x0000a15c , 0x0302021e }, + { 0x0000a160 , 0x03000301 }, + { 0x0000a164 , 0x031e031f }, + { 0x0000a168 , 0x0402031d }, + { 0x0000a16c , 0x04000401 }, + { 0x0000a170 , 0x041e041f }, + { 0x0000a174 , 0x0502041d }, + { 0x0000a178 , 0x05000501 }, + { 0x0000a17c , 0x051e051f }, + { 0x0000a180 , 0x06010602 }, + { 0x0000a184 , 0x061f0600 }, + { 0x0000a188 , 0x061d061e }, + { 0x0000a18c , 0x07020703 }, + { 0x0000a190 , 0x07000701 }, + { 0x0000a194 , 0x00000000 }, + { 0x0000a198 , 0x00000000 }, + { 0x0000a19c , 0x00000000 }, + { 0x0000a1a0 , 0x00000000 }, + { 0x0000a1a4 , 0x00000000 }, + { 0x0000a1a8 , 0x00000000 }, + { 0x0000a1ac , 0x00000000 }, + { 0x0000a1b0 , 0x00000000 }, + { 0x0000a1b4 , 0x00000000 }, + { 0x0000a1b8 , 0x00000000 }, + { 0x0000a1bc , 0x00000000 }, + { 0x0000a1c0 , 0x00000000 }, + { 0x0000a1c4 , 0x00000000 }, + { 0x0000a1c8 , 0x00000000 }, + { 0x0000a1cc , 0x00000000 }, + { 0x0000a1d0 , 0x00000000 }, + { 0x0000a1d4 , 0x00000000 }, + { 0x0000a1d8 , 0x00000000 }, + { 0x0000a1dc , 0x00000000 }, + { 0x0000a1e0 , 0x00000000 }, + { 0x0000a1e4 , 0x00000000 }, + { 0x0000a1e8 , 0x00000000 }, + { 0x0000a1ec , 0x00000000 }, + { 0x0000a1f0 , 0x00000396 }, + { 0x0000a1f4 , 0x00000396 }, + { 0x0000a1f8 , 0x00000396 }, + { 0x0000a1fc , 0x00000196 }, + { 0x0000b000 , 0x00010000 }, + { 0x0000b004 , 0x00030002 }, + { 0x0000b008 , 0x00050004 }, + { 0x0000b00c , 0x00810080 }, + { 0x0000b010 , 0x00830082 }, + { 0x0000b014 , 0x01810180 }, + { 0x0000b018 , 0x01830182 }, + { 0x0000b01c , 0x01850184 }, + { 0x0000b020 , 0x02810280 }, + { 0x0000b024 , 0x02830282 }, + { 0x0000b028 , 0x02850284 }, + { 0x0000b02c , 0x02890288 }, + { 0x0000b030 , 0x028b028a }, + { 0x0000b034 , 0x0388028c }, + { 0x0000b038 , 0x038a0389 }, + { 0x0000b03c , 0x038c038b }, + { 0x0000b040 , 0x0390038d }, + { 0x0000b044 , 0x03920391 }, + { 0x0000b048 , 0x03940393 }, + { 0x0000b04c , 0x03960395 }, + { 0x0000b050 , 0x00000000 }, + { 0x0000b054 , 0x00000000 }, + { 0x0000b058 , 0x00000000 }, + { 0x0000b05c , 0x00000000 }, + { 0x0000b060 , 0x00000000 }, + { 0x0000b064 , 0x00000000 }, + { 0x0000b068 , 0x00000000 }, + { 0x0000b06c , 0x00000000 }, + { 0x0000b070 , 0x00000000 }, + { 0x0000b074 , 0x00000000 }, + { 0x0000b078 , 0x00000000 }, + { 0x0000b07c , 0x00000000 }, + { 0x0000b080 , 0x23232323 }, + { 0x0000b084 , 0x21232323 }, + { 0x0000b088 , 0x19191c1e }, + { 0x0000b08c , 0x12141417 }, + { 0x0000b090 , 0x07070e0e }, + { 0x0000b094 , 0x03030305 }, + { 0x0000b098 , 0x00000003 }, + { 0x0000b09c , 0x00000000 }, + { 0x0000b0a0 , 0x00000000 }, + { 0x0000b0a4 , 0x00000000 }, + { 0x0000b0a8 , 0x00000000 }, + { 0x0000b0ac , 0x00000000 }, + { 0x0000b0b0 , 0x00000000 }, + { 0x0000b0b4 , 0x00000000 }, + { 0x0000b0b8 , 0x00000000 }, + { 0x0000b0bc , 0x00000000 }, + { 0x0000b0c0 , 0x003f0020 }, + { 0x0000b0c4 , 0x00400041 }, + { 0x0000b0c8 , 0x0140005f }, + { 0x0000b0cc , 0x0160015f }, + { 0x0000b0d0 , 0x017e017f }, + { 0x0000b0d4 , 0x02410242 }, + { 0x0000b0d8 , 0x025f0240 }, + { 0x0000b0dc , 0x027f0260 }, + { 0x0000b0e0 , 0x0341027e }, + { 0x0000b0e4 , 0x035f0340 }, + { 0x0000b0e8 , 0x037f0360 }, + { 0x0000b0ec , 0x04400441 }, + { 0x0000b0f0 , 0x0460045f }, + { 0x0000b0f4 , 0x0541047f }, + { 0x0000b0f8 , 0x055f0540 }, + { 0x0000b0fc , 0x057f0560 }, + { 0x0000b100 , 0x06400641 }, + { 0x0000b104 , 0x0660065f }, + { 0x0000b108 , 0x067e067f }, + { 0x0000b10c , 0x07410742 }, + { 0x0000b110 , 0x075f0740 }, + { 0x0000b114 , 0x077f0760 }, + { 0x0000b118 , 0x07800781 }, + { 0x0000b11c , 0x07a0079f }, + { 0x0000b120 , 0x07c107bf }, + { 0x0000b124 , 0x000007c0 }, + { 0x0000b128 , 0x00000000 }, + { 0x0000b12c , 0x00000000 }, + { 0x0000b130 , 0x00000000 }, + { 0x0000b134 , 0x00000000 }, + { 0x0000b138 , 0x00000000 }, + { 0x0000b13c , 0x00000000 }, + { 0x0000b140 , 0x003f0020 }, + { 0x0000b144 , 0x00400041 }, + { 0x0000b148 , 0x0140005f }, + { 0x0000b14c , 0x0160015f }, + { 0x0000b150 , 0x017e017f }, + { 0x0000b154 , 0x02410242 }, + { 0x0000b158 , 0x025f0240 }, + { 0x0000b15c , 0x027f0260 }, + { 0x0000b160 , 0x0341027e }, + { 0x0000b164 , 0x035f0340 }, + { 0x0000b168 , 0x037f0360 }, + { 0x0000b16c , 0x04400441 }, + { 0x0000b170 , 0x0460045f }, + { 0x0000b174 , 0x0541047f }, + { 0x0000b178 , 0x055f0540 }, + { 0x0000b17c , 0x057f0560 }, + { 0x0000b180 , 0x06400641 }, + { 0x0000b184 , 0x0660065f }, + { 0x0000b188 , 0x067e067f }, + { 0x0000b18c , 0x07410742 }, + { 0x0000b190 , 0x075f0740 }, + { 0x0000b194 , 0x077f0760 }, + { 0x0000b198 , 0x07800781 }, + { 0x0000b19c , 0x07a0079f }, + { 0x0000b1a0 , 0x07c107bf }, + { 0x0000b1a4 , 0x000007c0 }, + { 0x0000b1a8 , 0x00000000 }, + { 0x0000b1ac , 0x00000000 }, + { 0x0000b1b0 , 0x00000000 }, + { 0x0000b1b4 , 0x00000000 }, + { 0x0000b1b8 , 0x00000000 }, + { 0x0000b1bc , 0x00000000 }, + { 0x0000b1c0 , 0x00000000 }, + { 0x0000b1c4 , 0x00000000 }, + { 0x0000b1c8 , 0x00000000 }, + { 0x0000b1cc , 0x00000000 }, + { 0x0000b1d0 , 0x00000000 }, + { 0x0000b1d4 , 0x00000000 }, + { 0x0000b1d8 , 0x00000000 }, + { 0x0000b1dc , 0x00000000 }, + { 0x0000b1e0 , 0x00000000 }, + { 0x0000b1e4 , 0x00000000 }, + { 0x0000b1e8 , 0x00000000 }, + { 0x0000b1ec , 0x00000000 }, + { 0x0000b1f0 , 0x00000396 }, + { 0x0000b1f4 , 0x00000396 }, + { 0x0000b1f8 , 0x00000396 }, + { 0x0000b1fc , 0x00000196 }, +}; + +static const u_int32_t ar9300_ar9580_1p0_radio_core[][2] = { +/* Addr allmodes */ + { 0x00016000 , 0x36db6db6 }, + { 0x00016004 , 0x6db6db40 }, + { 0x00016008 , 0x73f00000 }, + { 0x0001600c , 0x00000000 }, + { 0x00016040 , 0x7f80fff8 }, + { 0x0001604c , 0x76d005b5 }, + { 0x00016050 , 0x556cf031 }, + { 0x00016054 , 0x13449440 }, + { 0x00016058 , 0x0c51c92c }, + { 0x0001605c , 0x3db7fffc }, + { 0x00016060 , 0xfffffffc }, + { 0x00016064 , 0x000f0278 }, + { 0x0001606c , 0x6db60000 }, + { 0x00016080 , 0x00000000 }, + { 0x00016084 , 0x0e48048c }, + { 0x00016088 , 0x54214514 }, + { 0x0001608c , 0x119f481e }, + { 0x00016090 , 0x24926490 }, + { 0x00016098 , 0xd2888888 }, + { 0x000160a0 , 0x0a108ffe }, + { 0x000160a4 , 0x812fc370 }, + { 0x000160a8 , 0x423c8000 }, + { 0x000160b4 , 0x92480080 }, + { 0x000160c0 , 0x00adb6d0 }, + { 0x000160c4 , 0x6db6db60 }, + { 0x000160c8 , 0x6db6db6c }, + { 0x000160cc , 0x01e6c000 }, + { 0x00016100 , 0x3fffbe01 }, + { 0x00016104 , 0xfff80000 }, + { 0x00016108 , 0x00080010 }, + { 0x00016144 , 0x02084080 }, + { 0x00016148 , 0x00000000 }, + { 0x00016280 , 0x058a0001 }, + { 0x00016284 , 0x3d840208 }, + { 0x00016288 , 0x05a20408 }, + { 0x0001628c , 0x00038c07 }, + { 0x00016290 , 0x00000004 }, + { 0x00016294 , 0x458a214f }, + { 0x00016380 , 0x00000000 }, + { 0x00016384 , 0x00000000 }, + { 0x00016388 , 0x00800700 }, + { 0x0001638c , 0x00800700 }, + { 0x00016390 , 0x00800700 }, + { 0x00016394 , 0x00000000 }, + { 0x00016398 , 0x00000000 }, + { 0x0001639c , 0x00000000 }, + { 0x000163a0 , 0x00000001 }, + { 0x000163a4 , 0x00000001 }, + { 0x000163a8 , 0x00000000 }, + { 0x000163ac , 0x00000000 }, + { 0x000163b0 , 0x00000000 }, + { 0x000163b4 , 0x00000000 }, + { 0x000163b8 , 0x00000000 }, + { 0x000163bc , 0x00000000 }, + { 0x000163c0 , 0x000000a0 }, + { 0x000163c4 , 0x000c0000 }, + { 0x000163c8 , 0x14021402 }, + { 0x000163cc , 0x00001402 }, + { 0x000163d0 , 0x00000000 }, + { 0x000163d4 , 0x00000000 }, + { 0x00016400 , 0x36db6db6 }, + { 0x00016404 , 0x6db6db40 }, + { 0x00016408 , 0x73f00000 }, + { 0x0001640c , 0x00000000 }, + { 0x00016440 , 0x7f80fff8 }, + { 0x0001644c , 0x76d005b5 }, + { 0x00016450 , 0x556cf031 }, + { 0x00016454 , 0x13449440 }, + { 0x00016458 , 0x0c51c92c }, + { 0x0001645c , 0x3db7fffc }, + { 0x00016460 , 0xfffffffc }, + { 0x00016464 , 0x000f0278 }, + { 0x0001646c , 0x6db60000 }, + { 0x00016500 , 0x3fffbe01 }, + { 0x00016504 , 0xfff80000 }, + { 0x00016508 , 0x00080010 }, + { 0x00016544 , 0x02084080 }, + { 0x00016548 , 0x00000000 }, + { 0x00016780 , 0x00000000 }, + { 0x00016784 , 0x00000000 }, + { 0x00016788 , 0x00800700 }, + { 0x0001678c , 0x00800700 }, + { 0x00016790 , 0x00800700 }, + { 0x00016794 , 0x00000000 }, + { 0x00016798 , 0x00000000 }, + { 0x0001679c , 0x00000000 }, + { 0x000167a0 , 0x00000001 }, + { 0x000167a4 , 0x00000001 }, + { 0x000167a8 , 0x00000000 }, + { 0x000167ac , 0x00000000 }, + { 0x000167b0 , 0x00000000 }, + { 0x000167b4 , 0x00000000 }, + { 0x000167b8 , 0x00000000 }, + { 0x000167bc , 0x00000000 }, + { 0x000167c0 , 0x000000a0 }, + { 0x000167c4 , 0x000c0000 }, + { 0x000167c8 , 0x14021402 }, + { 0x000167cc , 0x00001402 }, + { 0x000167d0 , 0x00000000 }, + { 0x000167d4 , 0x00000000 }, + { 0x00016800 , 0x36db6db6 }, + { 0x00016804 , 0x6db6db40 }, + { 0x00016808 , 0x73f00000 }, + { 0x0001680c , 0x00000000 }, + { 0x00016840 , 0x7f80fff8 }, + { 0x0001684c , 0x76d005b5 }, + { 0x00016850 , 0x556cf031 }, + { 0x00016854 , 0x13449440 }, + { 0x00016858 , 0x0c51c92c }, + { 0x0001685c , 0x3db7fffc }, + { 0x00016860 , 0xfffffffc }, + { 0x00016864 , 0x000f0278 }, + { 0x0001686c , 0x6db60000 }, + { 0x00016900 , 0x3fffbe01 }, + { 0x00016904 , 0xfff80000 }, + { 0x00016908 , 0x00080010 }, + { 0x00016944 , 0x02084080 }, + { 0x00016948 , 0x00000000 }, + { 0x00016b80 , 0x00000000 }, + { 0x00016b84 , 0x00000000 }, + { 0x00016b88 , 0x00800700 }, + { 0x00016b8c , 0x00800700 }, + { 0x00016b90 , 0x00800700 }, + { 0x00016b94 , 0x00000000 }, + { 0x00016b98 , 0x00000000 }, + { 0x00016b9c , 0x00000000 }, + { 0x00016ba0 , 0x00000001 }, + { 0x00016ba4 , 0x00000001 }, + { 0x00016ba8 , 0x00000000 }, + { 0x00016bac , 0x00000000 }, + { 0x00016bb0 , 0x00000000 }, + { 0x00016bb4 , 0x00000000 }, + { 0x00016bb8 , 0x00000000 }, + { 0x00016bbc , 0x00000000 }, + { 0x00016bc0 , 0x000000a0 }, + { 0x00016bc4 , 0x000c0000 }, + { 0x00016bc8 , 0x14021402 }, + { 0x00016bcc , 0x00001402 }, + { 0x00016bd0 , 0x00000000 }, + { 0x00016bd4 , 0x00000000 }, +}; + +static const u_int32_t ar9300_ar9580_1p0_baseband_core_emulation[][2] = { +/* Addr allmodes */ + { 0x00009800 , 0xafa68e30 }, + { 0x00009884 , 0x00002842 }, + { 0x00009c04 , 0xff55ff55 }, + { 0x00009c08 , 0x0320ff55 }, + { 0x00009e50 , 0x00000000 }, + { 0x00009fcc , 0x00000014 }, + { 0x0000a344 , 0x00000010 }, + { 0x0000a398 , 0x00000000 }, + { 0x0000a39c , 0x71733d01 }, + { 0x0000a3a0 , 0xd0ad5c12 }, + { 0x0000a3c0 , 0x22222220 }, + { 0x0000a3c4 , 0x22222222 }, + { 0x0000a404 , 0x00418a11 }, + { 0x0000a418 , 0x050001ce }, + { 0x0000a438 , 0x00001800 }, + { 0x0000a458 , 0x01444452 }, + { 0x0000a690 , 0x00000038 }, + { 0x0000b8dc , 0x00400000 }, +}; + +static const u_int32_t ar9300_ar9580_1p0_baseband_postamble[][5] = { +/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + { 0x00009810 , 0xd00a8005 , 0xd00a8005 , 0xd00a8011 , 0xd00a8011 }, + { 0x00009820 , 0x206a022e , 0x206a022e , 0x206a012e , 0x206a012e }, + { 0x00009824 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 , 0x5ac640d0 }, + { 0x00009828 , 0x06903081 , 0x06903081 , 0x06903881 , 0x06903881 }, + { 0x0000982c , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 , 0x05eea6d4 }, + { 0x00009830 , 0x0000059c , 0x0000059c , 0x0000119c , 0x0000119c }, + { 0x00009c00 , 0x000000c4 , 0x000000c4 , 0x000000c4 , 0x000000c4 }, + { 0x00009e00 , 0x0372111a , 0x0372111a , 0x037216a0 , 0x037216a0 }, + { 0x00009e04 , 0x001c2020 , 0x001c2020 , 0x001c2020 , 0x001c2020 }, + { 0x00009e0c , 0x6c4000e2 , 0x6d4000e2 , 0x6d4000e2 , 0x6c4000e2 }, + { 0x00009e10 , 0x7ec88d2e , 0x7ec88d2e , 0x7ec84d2e , 0x7ec84d2e }, + { 0x00009e14 , 0x37b95d5e , 0x37b9605e , 0x3379605e , 0x33795d5e }, + { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x00009e1c , 0x0001cf9c , 0x0001cf9c , 0x00021f9c , 0x00021f9c }, + { 0x00009e20 , 0x000003b5 , 0x000003b5 , 0x000003ce , 0x000003ce }, + { 0x00009e2c , 0x0000001c , 0x0000001c , 0x00000021 , 0x00000021 }, + { 0x00009e3c , 0xcf946220 , 0xcf946220 , 0xcf946222 , 0xcf946222 }, + { 0x00009e44 , 0x02321e27 , 0x02321e27 , 0x02291e27 , 0x02291e27 }, + { 0x00009e48 , 0x5030201a , 0x5030201a , 0x50302012 , 0x50302012 }, + { 0x00009fc8 , 0x0003f000 , 0x0003f000 , 0x0001a000 , 0x0001a000 }, + { 0x0000a204 , 0x000036c0 , 0x000036c4 , 0x000036c4 , 0x000036c0 }, + { 0x0000a208 , 0x00000104 , 0x00000104 , 0x00000004 , 0x00000004 }, + { 0x0000a22c , 0x07e26a2f , 0x07e26a2f , 0x01026a2f , 0x01026a2f }, + { 0x0000a230 , 0x0000000a , 0x00000014 , 0x00000016 , 0x0000000b }, + { 0x0000a234 , 0x00000fff , 0x10000fff , 0x10000fff , 0x00000fff }, + { 0x0000a238 , 0xffb01018 , 0xffb01018 , 0xffb01018 , 0xffb01018 }, + { 0x0000a250 , 0x00000000 , 0x00000000 , 0x00000210 , 0x00000108 }, + { 0x0000a254 , 0x000007d0 , 0x00000fa0 , 0x00001130 , 0x00000898 }, + { 0x0000a258 , 0x02020002 , 0x02020002 , 0x02020002 , 0x02020002 }, + { 0x0000a25c , 0x01000e0e , 0x01000e0e , 0x01000e0e , 0x01000e0e }, + { 0x0000a260 , 0x0a021501 , 0x0a021501 , 0x3a021501 , 0x3a021501 }, + { 0x0000a264 , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e }, + { 0x0000a280 , 0x00000007 , 0x00000007 , 0x0000000b , 0x0000000b }, + { 0x0000a284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, + { 0x0000a288 , 0x00000110 , 0x00000110 , 0x00000110 , 0x00000110 }, + { 0x0000a28c , 0x00022222 , 0x00022222 , 0x00022222 , 0x00022222 }, + { 0x0000a2c4 , 0x00158d18 , 0x00158d18 , 0x00158d18 , 0x00158d18 }, + { 0x0000a2d0 , 0x00041983 , 0x00041983 , 0x00041981 , 0x00041982 }, + { 0x0000a2d8 , 0x7999a83b , 0x7999a83b , 0x7999a83b , 0x7999a83b }, + { 0x0000a358 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000a830 , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae04 , 0x001c0000 , 0x001c0000 , 0x001c0000 , 0x001c0000 }, + { 0x0000ae18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000ae1c , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000ae20 , 0x000001b5 , 0x000001b5 , 0x000001ce , 0x000001ce }, + { 0x0000b284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, + { 0x0000b830 , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000be04 , 0x001c0000 , 0x001c0000 , 0x001c0000 , 0x001c0000 }, + { 0x0000be18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 }, + { 0x0000be1c , 0x0000019c , 0x0000019c , 0x0000019c , 0x0000019c }, + { 0x0000be20 , 0x000001b5 , 0x000001b5 , 0x000001ce , 0x000001ce }, + { 0x0000c284 , 0x00000000 , 0x00000000 , 0x00000150 , 0x00000150 }, +}; + +/* PCIE-PHY programming array */ +static const u_int32_t ar9300PciePhy_clkreq_enable_L1_ar9580_1p0[][2] = { +{0x00004040, 0x0835365e}, +{0x00004040, 0x0008003b}, +{0x00004044, 0x00000000}, +}; + +/* PCIE-PHY programming array */ +static const u_int32_t ar9300PciePhy_clkreq_disable_L1_ar9580_1p0[][2] = { +{0x00004040, 0x0831365e}, +{0x00004040, 0x0008003b}, +{0x00004044, 0x00000000}, +}; + +/* PCIE-PHY programming array */ +static const u_int32_t ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0[][2] = { +{0x00004040, 0x0831265e}, +{0x00004040, 0x0008003b}, +{0x00004044, 0x00000000}, +}; + diff --git a/hal/ar9300/eeprom.diff b/hal/ar9300/eeprom.diff new file mode 100644 index 000000000000..4fbedb67bb62 --- /dev/null +++ b/hal/ar9300/eeprom.diff @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +diff --git a/hal/ar9300/ar9300_eeprom.c b/hal/ar9300/ar9300_eeprom.c +index 2fe5506..628026f 100644 +--- a/hal/ar9300/ar9300_eeprom.c ++++ b/hal/ar9300/ar9300_eeprom.c +@@ -342,6 +342,8 @@ ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi + int status = 0; + u_int32_t addr; + ++ //ath_hal_printf(ah, "%s: reading offset 0x%x\n", __func__, off); ++ + addr = (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah))? + OTP_MEM_START_ADDRESS_WASP : OTP_MEM_START_ADDRESS; + if (!is_wifi) { +@@ -372,6 +374,7 @@ ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi + addr = BTOTP_STATUS1_EFUSE_READ_DATA; + } + *data = OS_REG_READ(ah, addr); ++ //ath_hal_printf(ah, "%s: data=0x%x\n", __func__, *data); + return AH_TRUE; + } + +@@ -603,6 +606,8 @@ ar9300_eeprom_attach(struct ath_hal *ah) + systime_t current_system_time = OS_GET_TIMESTAMP(); + #endif + #endif ++ ++ ath_hal_printf(ah, "%s: starting\n", __func__); + ahp->try_dram = 1; + ahp->try_eeprom = 1; + ahp->try_otp = 1; +@@ -679,10 +684,14 @@ ar9300_eeprom_attach(struct ath_hal *ah) + #endif + #endif + ++ ath_hal_printf(ah, "%s: calling ar9300_fill_eeprom\n", __func__); + if (!ar9300_fill_eeprom(ah)) { + return HAL_EIO; + } + ++ ath_hal_printf(ah, "%s: calibration data type = %d\n", __func__, ++ AH9300(ah)->calibration_data_source); ++ + return HAL_OK; + /* return ar9300_check_eeprom(ah); */ + #endif +@@ -704,6 +713,7 @@ ar9300_eeprom_attach(struct ath_hal *ah) + ahp->ah_eeprom.mac_addr[4] = 0xD0; + ahp->ah_eeprom.mac_addr[5] = 0x00; + #endif ++ ath_hal_printf(ah, "%s: %s:%d\n", __func__, __FILE__, __LINE__); + return HAL_OK; + #else + #if ATH_DRIVER_SIM +@@ -764,13 +774,17 @@ ar9300_eeprom_attach(struct ath_hal *ah) + return HAL_OK; + } + #endif ++ ath_hal_printf(ah, "%s: %s:%d\n", __func__, __FILE__, __LINE__); + if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { + ahp->try_eeprom = 0; + } + ++ ath_hal_printf(ah, "%s: %s:%d\n", __func__, __FILE__, __LINE__); + if (!ar9300_eeprom_restore(ah)) { ++ ath_hal_printf(ah, "%s: %s:%d\n", __func__, __FILE__, __LINE__); + return HAL_EIO; + } ++ ath_hal_printf(ah, "%s: %s:%d\n", __func__, __FILE__, __LINE__); + return HAL_OK; + #endif + #endif +@@ -3743,6 +3757,12 @@ ar9300_calibration_data_read_otp(struct ath_hal *ah, long address, + unsigned long byte_addr; + u_int32_t svalue; + ++ ath_hal_printf(ah, "%s: called: address=%d, many=%d, is_wifi=%d\n", ++ __func__, ++ (int) address, ++ many, ++ is_wifi); ++ + if (((address) < 0) || ((address + many) > 0x400)) { + return AH_FALSE; + } +@@ -3802,6 +3822,8 @@ ar9300_calibration_data_read_array(struct ath_hal *ah, int address, + { + int it; + ++ ath_hal_printf(ah, "%s: address=%d, many=%d\n", __func__, address, many); ++ + for (it = 0; it < many; it++) { + (void)ar9300_calibration_data_read(ah, address - it, buffer + it, 1); + } +@@ -4001,13 +4023,24 @@ ar9300_eeprom_restore_internal_address(struct ath_hal *ah, + int restored; + u_int16_t checksum, mchecksum; + ++ ath_hal_printf(ah, "%s: called, cptr=0x%x, mdata_size=%d, blank=%d\n", ++ __func__, cptr, mdata_size, blank); ++ + restored = 0; + for (it = 0; it < MSTATE; it++) { + (void) ar9300_calibration_data_read_array( + ah, cptr, word, compression_header_length); ++ ath_hal_printf(ah, "%s: word = 0x%x, 0x%x, 0x%x, 0x%x\n", ++ __func__, ++ word[0], ++ word[1], ++ word[2], ++ word[3]); + if (word[0] == blank && word[1] == blank && word[2] == blank && word[3] == blank) + { +- break; ++ ath_hal_printf(ah, "%s: word=blank, skipping\n", __func__); ++ cptr -= compression_header_length; ++ continue; + } + ar9300_compression_header_unpack( + word, &code, &reference, &length, &major, &minor); +@@ -4143,19 +4176,18 @@ static int + ar9300_eeprom_restore_from_dram(struct ath_hal *ah, ar9300_eeprom_t *mptr, + int mdata_size) + { +-#if 0 + struct ath_hal_9300 *ahp = AH9300(ah); + char *cal_ptr; +-#endif + ++#if 0 + /* cal data in flash / DRAM isn't currently supported */ + ath_hal_printf(ah, "%s: Cal data from DRAM isn't supported\n", + __func__); + + return -1; ++#endif + + #ifndef WIN32 +-#if 0 + HALASSERT(mdata_size > 0); + + /* if cal_in_flash is true, the address sent by LMAC to HAL +@@ -4164,14 +4196,17 @@ ar9300_eeprom_restore_from_dram(struct ath_hal *ah, ar9300_eeprom_t *mptr, + if(ar9300_eep_data_in_flash(ah)) + return -1; + ++#if 0 + /* check if LMAC sent DRAM address is valid */ + if (!(uintptr_t)(AH_PRIVATE(ah)->ah_st)) { + return -1; + } ++#endif + + /* When calibration data is from host, Host will copy the + compressed data to the predefined DRAM location saved at ah->ah_st */ + ath_hal_printf(ah, "Restoring Cal data from DRAM\n"); ++#if 0 + #ifdef __NetBSD__ + ahp->ah_cal_mem = OS_REMAP(ah, (uintptr_t)(AH_PRIVATE(ah)->ah_st), + HOST_CALDATA_SIZE); +@@ -4184,6 +4219,20 @@ ar9300_eeprom_restore_from_dram(struct ath_hal *ah, ar9300_eeprom_t *mptr, + HALDEBUG(ah, HAL_DEBUG_EEPROM,"%s: can't remap dram region\n", __func__); + return -1; + } ++#endif ++ ++ /* ++ * The atheros HAL passes in this buffer anyway, and we copy things ++ * into it. However, the FreeBSD driver doesn't supply this ++ * particular memory. So, let's just assume attach/detach will ++ * provide us with a 16 kilobyte buffer for now, and hope the whole ++ * OTP path works. ++ */ ++ if (! ahp->ah_cal_mem) { ++ ath_hal_printf(ah, "%s: FreeBSD: ah_cal_mem isn't set\n", __func__); ++ return -1; ++ } ++ + cal_ptr = &((char *)(ahp->ah_cal_mem))[AR9300_FLASH_CAL_START_OFFSET]; + OS_MEMCPY(mptr, cal_ptr, mdata_size); + +@@ -4201,7 +4250,6 @@ ar9300_eeprom_restore_from_dram(struct ath_hal *ah, ar9300_eeprom_t *mptr, + } + + return mdata_size; +-#endif + #else + return -1; + #endif +@@ -4290,6 +4338,11 @@ ar9300_eeprom_restore_from_flash(struct ath_hal *ah, ar9300_eeprom_t *mptr, + } + + #endif ++ ath_hal_printf(ah, "%s: eeprom version=%d, template version=%d\n", ++ __func__, ++ (int) mptr->eeprom_version, ++ (int) mptr->template_version); ++ + if (mptr->eeprom_version == 0xff || + mptr->template_version == 0xff || + mptr->eeprom_version == 0 || +@@ -4321,10 +4374,11 @@ ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, + + nptr = -1; + +- if ((AH9300(ah)->calibration_data_try == calibration_data_none || ++ if (0 && (AH9300(ah)->calibration_data_try == calibration_data_none || + AH9300(ah)->calibration_data_try == calibration_data_dram) && + AH9300(ah)->try_dram && nptr < 0) + { ++ ath_hal_printf(ah, "%s: trying dram\n", __func__); + AH9300(ah)->calibration_data_source = calibration_data_dram; + AH9300(ah)->calibration_data_source_address = 0; + nptr = ar9300_eeprom_restore_from_dram(ah, mptr, mdata_size); +@@ -4334,7 +4388,7 @@ ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, + } + } + +- if ((AH9300(ah)->calibration_data_try == calibration_data_none || ++ if (0 && (AH9300(ah)->calibration_data_try == calibration_data_none || + AH9300(ah)->calibration_data_try == calibration_data_eeprom) && + AH9300(ah)->try_eeprom && nptr < 0) + { +@@ -4343,6 +4397,7 @@ ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, + * base_address=0x3ff where we used to write the data + */ + AH9300(ah)->calibration_data_source = calibration_data_eeprom; ++ ath_hal_printf(ah, "%s: trying eeprom\n", __func__); + if (AH9300(ah)->calibration_data_try_address != 0) { + AH9300(ah)->calibration_data_source_address = + AH9300(ah)->calibration_data_try_address; +@@ -4374,7 +4429,7 @@ ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, + * ##### should be an ifdef test for any AP usage, + * either in driver or in nart + */ +- if ((AH9300(ah)->calibration_data_try == calibration_data_none || ++ if (0 && (AH9300(ah)->calibration_data_try == calibration_data_none || + AH9300(ah)->calibration_data_try == calibration_data_flash) && + AH9300(ah)->try_flash && nptr < 0) + { +@@ -4388,10 +4443,17 @@ ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, + } + } + ++ /* XXX FreeBSD? */ ++ AH9300(ah)->calibration_data_try = calibration_data_otp; ++ AH9300(ah)->calibration_data_try_address = 0x2ff; ++ + if ((AH9300(ah)->calibration_data_try == calibration_data_none || + AH9300(ah)->calibration_data_try == calibration_data_otp) && + AH9300(ah)->try_otp && nptr < 0) + { ++ ath_hal_printf(ah, "%s: trying OTP, try_address=0x%x\n", ++ __func__, ++ AH9300(ah)->calibration_data_try_address); + AH9300(ah)->calibration_data_source = calibration_data_otp; + if (AH9300(ah)->calibration_data_try_address != 0) { + AH9300(ah)->calibration_data_source_address = +@@ -4526,6 +4588,8 @@ ar9300_eeprom_restore(struct ath_hal *ah) + int mdata_size; + HAL_BOOL status = AH_FALSE; + ++ ath_hal_printf(ah, "%s: called\n", __func__); ++ + mptr = &ahp->ah_eeprom; + mdata_size = ar9300_eeprom_struct_size(); + diff --git a/hal/ar9300/osprey_reg_map.h b/hal/ar9300/osprey_reg_map.h new file mode 100644 index 000000000000..dff59004947a --- /dev/null +++ b/hal/ar9300/osprey_reg_map.h @@ -0,0 +1,3193 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* */ +/* File: /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/osprey_reg_map.h*/ +/* Creator: yli */ +/* Time: Wednesday Jan 6, 2010 [2:09:02 pm] */ +/* */ +/* Path: /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top */ +/* Arguments: /cad/denali/blueprint/3.7//Linux/blueprint -codegen */ +/* /trees/yli/yli-dev/chips/osprey/2.0/env/blueprint/ath_ansic.codegen*/ +/* -ath_ansic -Wdesc -I */ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top -I */ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint -I */ +/* /trees/yli/yli-dev/chips/osprey/2.0/env/blueprint -I */ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig -odir */ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top -eval */ +/* {$INCLUDE_SYSCONFIG_FILES=1} -eval */ +/* $WAR_EV58615_for_ansic_codegen=1 osprey_reg.rdl */ +/* */ +/* Sources: /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/emulation_misc.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/amba_mac/svd/blueprint/svd_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/merlin2_0_radio_reg_map.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/host_intf/rtl/blueprint/efuse_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/ip/pcie_axi/blueprint/DWC_pcie_ep.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/apb_analog/analog_intf_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/rtc/blueprint/rtc_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/DWC_pcie_dbi_axi_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/host_intf/rtl/blueprint/host_intf_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/bb/blueprint/bb_reg_map.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/efuse_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/osprey_pcieconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/osprey_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/merlin2_0_radio_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/amba_mac/blueprint/rtc_sync_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/analog_intf_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/svd_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/osprey_radio_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/host_intf_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/env/blueprint/ath_ansic.pm*/ +/* /cad/local/lib/perl/Pinfo.pm */ +/* */ +/* Blueprint: 3.7 (Fri Oct 5 10:32:33 PDT 2007) */ +/* Machine: artemis */ +/* OS: Linux 2.6.9-78.0.5.ELlargesmp */ +/* Description: */ +/* */ +/*This Register Map contains the complete register set for OSPREY. */ +/* */ +/* Copyright (C) 2010 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ +/* */ + + +#ifndef __REG_OSPREY_REG_MAP_H__ +#define __REG_OSPREY_REG_MAP_H__ + +#include "osprey_reg_map_macro.h" +#include "poseidon_reg_map_macro.h" + +struct mac_dma_reg { + volatile char pad__0[0x8]; /* 0x0 - 0x8 */ + volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */ + volatile char pad__1[0x8]; /* 0xc - 0x14 */ + volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */ + volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */ + volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */ + volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */ + volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */ + volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */ + volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */ + volatile u_int32_t MAC_DMA_TXCFG; /* 0x30 - 0x34 */ + volatile u_int32_t MAC_DMA_RXCFG; /* 0x34 - 0x38 */ + volatile u_int32_t MAC_DMA_RXJLA; /* 0x38 - 0x3c */ + volatile char pad__2[0x4]; /* 0x3c - 0x40 */ + volatile u_int32_t MAC_DMA_MIBC; /* 0x40 - 0x44 */ + volatile u_int32_t MAC_DMA_TOPS; /* 0x44 - 0x48 */ + volatile u_int32_t MAC_DMA_RXNPTO; /* 0x48 - 0x4c */ + volatile u_int32_t MAC_DMA_TXNPTO; /* 0x4c - 0x50 */ + volatile u_int32_t MAC_DMA_RPGTO; /* 0x50 - 0x54 */ + volatile char pad__3[0x4]; /* 0x54 - 0x58 */ + volatile u_int32_t MAC_DMA_MACMISC; /* 0x58 - 0x5c */ + volatile u_int32_t MAC_DMA_INTER; /* 0x5c - 0x60 */ + volatile u_int32_t MAC_DMA_DATABUF; /* 0x60 - 0x64 */ + volatile u_int32_t MAC_DMA_GTT; /* 0x64 - 0x68 */ + volatile u_int32_t MAC_DMA_GTTM; /* 0x68 - 0x6c */ + volatile u_int32_t MAC_DMA_CST; /* 0x6c - 0x70 */ + volatile u_int32_t MAC_DMA_RXDP_SIZE; /* 0x70 - 0x74 */ + volatile u_int32_t MAC_DMA_RX_QUEUE_HP_RXDP; /* 0x74 - 0x78 */ + volatile u_int32_t MAC_DMA_RX_QUEUE_LP_RXDP; /* 0x78 - 0x7c */ + volatile char pad__4[0x4]; /* 0x7c - 0x80 */ + volatile u_int32_t MAC_DMA_ISR_P; /* 0x80 - 0x84 */ + volatile u_int32_t MAC_DMA_ISR_S0; /* 0x84 - 0x88 */ + volatile u_int32_t MAC_DMA_ISR_S1; /* 0x88 - 0x8c */ + volatile u_int32_t MAC_DMA_ISR_S2; /* 0x8c - 0x90 */ + volatile u_int32_t MAC_DMA_ISR_S3; /* 0x90 - 0x94 */ + volatile u_int32_t MAC_DMA_ISR_S4; /* 0x94 - 0x98 */ + volatile u_int32_t MAC_DMA_ISR_S5; /* 0x98 - 0x9c */ + /* Jupiter */ + volatile u_int32_t MAC_DMA_ISR_S6; /* 0x9c - 0xa0 */ + volatile u_int32_t MAC_DMA_IMR_P; /* 0xa0 - 0xa4 */ + volatile u_int32_t MAC_DMA_IMR_S0; /* 0xa4 - 0xa8 */ + volatile u_int32_t MAC_DMA_IMR_S1; /* 0xa8 - 0xac */ + volatile u_int32_t MAC_DMA_IMR_S2; /* 0xac - 0xb0 */ + volatile u_int32_t MAC_DMA_IMR_S3; /* 0xb0 - 0xb4 */ + volatile u_int32_t MAC_DMA_IMR_S4; /* 0xb4 - 0xb8 */ + volatile u_int32_t MAC_DMA_IMR_S5; /* 0xb8 - 0xbc */ + /* Jupiter */ + volatile u_int32_t MAC_DMA_IMR_S6; /* 0xbc - 0xc0 */ + volatile u_int32_t MAC_DMA_ISR_P_RAC; /* 0xc0 - 0xc4 */ + volatile u_int32_t MAC_DMA_ISR_S0_S; /* 0xc4 - 0xc8 */ + volatile u_int32_t MAC_DMA_ISR_S1_S; /* 0xc8 - 0xcc */ + /* Jupiter */ + volatile u_int32_t MAC_DMA_ISR_S6_S; /* 0xcc - 0xd0 */ + volatile u_int32_t MAC_DMA_ISR_S2_S; /* 0xd0 - 0xd4 */ + volatile u_int32_t MAC_DMA_ISR_S3_S; /* 0xd4 - 0xd8 */ + volatile u_int32_t MAC_DMA_ISR_S4_S; /* 0xd8 - 0xdc */ + volatile u_int32_t MAC_DMA_ISR_S5_S; /* 0xdc - 0xe0 */ + volatile u_int32_t MAC_DMA_DMADBG_0; /* 0xe0 - 0xe4 */ + volatile u_int32_t MAC_DMA_DMADBG_1; /* 0xe4 - 0xe8 */ + volatile u_int32_t MAC_DMA_DMADBG_2; /* 0xe8 - 0xec */ + volatile u_int32_t MAC_DMA_DMADBG_3; /* 0xec - 0xf0 */ + volatile u_int32_t MAC_DMA_DMADBG_4; /* 0xf0 - 0xf4 */ + volatile u_int32_t MAC_DMA_DMADBG_5; /* 0xf4 - 0xf8 */ + volatile u_int32_t MAC_DMA_DMADBG_6; /* 0xf8 - 0xfc */ + volatile u_int32_t MAC_DMA_DMADBG_7; /* 0xfc - 0x100 */ + volatile u_int32_t MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0; + /* 0x100 - 0x104 */ + volatile u_int32_t MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8; + /* 0x104 - 0x108 */ +}; + +struct mac_qcu_reg { + volatile char pad__0[0x800]; /* 0x0 - 0x800 */ + volatile u_int32_t MAC_QCU_TXDP[10]; /* 0x800 - 0x828 */ + volatile char pad__1[0x8]; /* 0x828 - 0x830 */ + volatile u_int32_t MAC_QCU_STATUS_RING_START; /* 0x830 - 0x834 */ + volatile u_int32_t MAC_QCU_STATUS_RING_END; /* 0x834 - 0x838 */ + volatile u_int32_t MAC_QCU_STATUS_RING_CURRENT; /* 0x838 - 0x83c */ + volatile char pad__2[0x4]; /* 0x83c - 0x840 */ + volatile u_int32_t MAC_QCU_TXE; /* 0x840 - 0x844 */ + volatile char pad__3[0x3c]; /* 0x844 - 0x880 */ + volatile u_int32_t MAC_QCU_TXD; /* 0x880 - 0x884 */ + volatile char pad__4[0x3c]; /* 0x884 - 0x8c0 */ + volatile u_int32_t MAC_QCU_CBR[10]; /* 0x8c0 - 0x8e8 */ + volatile char pad__5[0x18]; /* 0x8e8 - 0x900 */ + volatile u_int32_t MAC_QCU_RDYTIME[10]; /* 0x900 - 0x928 */ + volatile char pad__6[0x18]; /* 0x928 - 0x940 */ + volatile u_int32_t MAC_QCU_ONESHOT_ARM_SC; /* 0x940 - 0x944 */ + volatile char pad__7[0x3c]; /* 0x944 - 0x980 */ + volatile u_int32_t MAC_QCU_ONESHOT_ARM_CC; /* 0x980 - 0x984 */ + volatile char pad__8[0x3c]; /* 0x984 - 0x9c0 */ + volatile u_int32_t MAC_QCU_MISC[10]; /* 0x9c0 - 0x9e8 */ + volatile char pad__9[0x18]; /* 0x9e8 - 0xa00 */ + volatile u_int32_t MAC_QCU_CNT[10]; /* 0xa00 - 0xa28 */ + volatile char pad__10[0x18]; /* 0xa28 - 0xa40 */ + volatile u_int32_t MAC_QCU_RDYTIME_SHDN; /* 0xa40 - 0xa44 */ + volatile u_int32_t MAC_QCU_DESC_CRC_CHK; /* 0xa44 - 0xa48 */ + /* Jupiter_20 */ + volatile u_int32_t MAC_QCU_EOL; /* 0xa48 - 0xa4c */ +}; + +struct mac_dcu_reg { + volatile char pad__0[0x1000]; /* 0x0 - 0x1000 */ + volatile u_int32_t MAC_DCU_QCUMASK[10]; /* 0x1000 - 0x1028 */ + volatile char pad__1[0x8]; /* 0x1028 - 0x1030 */ + volatile u_int32_t MAC_DCU_GBL_IFS_SIFS; /* 0x1030 - 0x1034 */ + volatile char pad__2[0x4]; /* 0x1034 - 0x1038 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU0_31_0; /* 0x1038 - 0x103c */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU8_31_0; /* 0x103c - 0x1040 */ + volatile u_int32_t MAC_DCU_LCL_IFS[10]; /* 0x1040 - 0x1068 */ + volatile char pad__3[0x8]; /* 0x1068 - 0x1070 */ + volatile u_int32_t MAC_DCU_GBL_IFS_SLOT; /* 0x1070 - 0x1074 */ + volatile char pad__4[0x4]; /* 0x1074 - 0x1078 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU0_63_32; /* 0x1078 - 0x107c */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU8_63_32; /* 0x107c - 0x1080 */ + volatile u_int32_t MAC_DCU_RETRY_LIMIT[10]; /* 0x1080 - 0x10a8 */ + volatile char pad__5[0x8]; /* 0x10a8 - 0x10b0 */ + volatile u_int32_t MAC_DCU_GBL_IFS_EIFS; /* 0x10b0 - 0x10b4 */ + volatile char pad__6[0x4]; /* 0x10b4 - 0x10b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU0_95_64; /* 0x10b8 - 0x10bc */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU8_95_64; /* 0x10bc - 0x10c0 */ + volatile u_int32_t MAC_DCU_CHANNEL_TIME[10]; /* 0x10c0 - 0x10e8 */ + volatile char pad__7[0x8]; /* 0x10e8 - 0x10f0 */ + volatile u_int32_t MAC_DCU_GBL_IFS_MISC; /* 0x10f0 - 0x10f4 */ + volatile char pad__8[0x4]; /* 0x10f4 - 0x10f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU0_127_96; + /* 0x10f8 - 0x10fc */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU8_127_96; + /* 0x10fc - 0x1100 */ + volatile u_int32_t MAC_DCU_MISC[10]; /* 0x1100 - 0x1128 */ + volatile char pad__9[0x10]; /* 0x1128 - 0x1138 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU1_31_0; /* 0x1138 - 0x113c */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU9_31_0; /* 0x113c - 0x1140 */ + volatile u_int32_t MAC_DCU_SEQ; /* 0x1140 - 0x1144 */ + volatile char pad__10[0x34]; /* 0x1144 - 0x1178 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU1_63_32; /* 0x1178 - 0x117c */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU9_63_32; /* 0x117c - 0x1180 */ + volatile char pad__11[0x38]; /* 0x1180 - 0x11b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU1_95_64; /* 0x11b8 - 0x11bc */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU9_95_64; /* 0x11bc - 0x11c0 */ + volatile char pad__12[0x38]; /* 0x11c0 - 0x11f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU1_127_96; + /* 0x11f8 - 0x11fc */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU9_127_96; + /* 0x11fc - 0x1200 */ + volatile char pad__13[0x38]; /* 0x1200 - 0x1238 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU2_31_0; /* 0x1238 - 0x123c */ + volatile char pad__14[0x34]; /* 0x123c - 0x1270 */ + volatile u_int32_t MAC_DCU_PAUSE; /* 0x1270 - 0x1274 */ + volatile char pad__15[0x4]; /* 0x1274 - 0x1278 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU2_63_32; /* 0x1278 - 0x127c */ + volatile char pad__16[0x34]; /* 0x127c - 0x12b0 */ + volatile u_int32_t MAC_DCU_WOW_KACFG; /* 0x12b0 - 0x12b4 */ + volatile char pad__17[0x4]; /* 0x12b4 - 0x12b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU2_95_64; /* 0x12b8 - 0x12bc */ + volatile char pad__18[0x34]; /* 0x12bc - 0x12f0 */ + volatile u_int32_t MAC_DCU_TXSLOT; /* 0x12f0 - 0x12f4 */ + volatile char pad__19[0x4]; /* 0x12f4 - 0x12f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU2_127_96; + /* 0x12f8 - 0x12fc */ + volatile char pad__20[0x3c]; /* 0x12fc - 0x1338 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU3_31_0; /* 0x1338 - 0x133c */ + volatile char pad__21[0x3c]; /* 0x133c - 0x1378 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU3_63_32; /* 0x1378 - 0x137c */ + volatile char pad__22[0x3c]; /* 0x137c - 0x13b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU3_95_64; /* 0x13b8 - 0x13bc */ + volatile char pad__23[0x3c]; /* 0x13bc - 0x13f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU3_127_96; + /* 0x13f8 - 0x13fc */ + volatile char pad__24[0x3c]; /* 0x13fc - 0x1438 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU4_31_0; /* 0x1438 - 0x143c */ + volatile u_int32_t MAC_DCU_TXFILTER_CLEAR; /* 0x143c - 0x1440 */ + volatile char pad__25[0x38]; /* 0x1440 - 0x1478 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU4_63_32; /* 0x1478 - 0x147c */ + volatile u_int32_t MAC_DCU_TXFILTER_SET; /* 0x147c - 0x1480 */ + volatile char pad__26[0x38]; /* 0x1480 - 0x14b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU4_95_64; /* 0x14b8 - 0x14bc */ + volatile char pad__27[0x3c]; /* 0x14bc - 0x14f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU4_127_96; + /* 0x14f8 - 0x14fc */ + volatile char pad__28[0x3c]; /* 0x14fc - 0x1538 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU5_31_0; /* 0x1538 - 0x153c */ + volatile char pad__29[0x3c]; /* 0x153c - 0x1578 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU5_63_32; /* 0x1578 - 0x157c */ + volatile char pad__30[0x3c]; /* 0x157c - 0x15b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU5_95_64; /* 0x15b8 - 0x15bc */ + volatile char pad__31[0x3c]; /* 0x15bc - 0x15f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU5_127_96; + /* 0x15f8 - 0x15fc */ + volatile char pad__32[0x3c]; /* 0x15fc - 0x1638 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU6_31_0; /* 0x1638 - 0x163c */ + volatile char pad__33[0x3c]; /* 0x163c - 0x1678 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU6_63_32; /* 0x1678 - 0x167c */ + volatile char pad__34[0x3c]; /* 0x167c - 0x16b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU6_95_64; /* 0x16b8 - 0x16bc */ + volatile char pad__35[0x3c]; /* 0x16bc - 0x16f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU6_127_96; + /* 0x16f8 - 0x16fc */ + volatile char pad__36[0x3c]; /* 0x16fc - 0x1738 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU7_31_0; /* 0x1738 - 0x173c */ + volatile char pad__37[0x3c]; /* 0x173c - 0x1778 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU7_63_32; /* 0x1778 - 0x177c */ + volatile char pad__38[0x3c]; /* 0x177c - 0x17b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU7_95_64; /* 0x17b8 - 0x17bc */ + volatile char pad__39[0x3c]; /* 0x17bc - 0x17f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU7_127_96; + /* 0x17f8 - 0x17fc */ +}; + +struct host_intf_reg { + volatile char pad__0[0x4000]; /* 0x0 - 0x4000 */ + volatile u_int32_t HOST_INTF_RESET_CONTROL; /* 0x4000 - 0x4004 */ + volatile u_int32_t HOST_INTF_WORK_AROUND; /* 0x4004 - 0x4008 */ + volatile u_int32_t HOST_INTF_PM_STATE; /* 0x4008 - 0x400c */ + volatile u_int32_t HOST_INTF_CXPL_DEBUG_INFOL; /* 0x400c - 0x4010 */ + volatile u_int32_t HOST_INTF_CXPL_DEBUG_INFOH; /* 0x4010 - 0x4014 */ + volatile u_int32_t HOST_INTF_PM_CTRL; /* 0x4014 - 0x4018 */ + volatile u_int32_t HOST_INTF_TIMEOUT; /* 0x4018 - 0x401c */ + volatile u_int32_t HOST_INTF_EEPROM_CTRL; /* 0x401c - 0x4020 */ + volatile u_int32_t HOST_INTF_SREV; /* 0x4020 - 0x4024 */ + volatile char pad__1[0x4]; /* 0x4024 - 0x4028 */ + volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE; /* 0x4028 - 0x402c */ + volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE; /* 0x402c - 0x4030 */ + volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK; /* 0x4030 - 0x4034 */ + volatile u_int32_t HOST_INTF_INTR_SYNC_MASK; /* 0x4034 - 0x4038 */ + volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE; /* 0x4038 - 0x403c */ + volatile u_int32_t HOST_INTF_INTR_ASYNC_ENABLE; /* 0x403c - 0x4040 */ + volatile u_int32_t HOST_INTF_PCIE_PHY_RW; /* 0x4040 - 0x4044 */ + volatile u_int32_t HOST_INTF_PCIE_PHY_LOAD; /* 0x4044 - 0x4048 */ + volatile u_int32_t HOST_INTF_GPIO_OUT; /* 0x4048 - 0x404c */ + volatile u_int32_t HOST_INTF_GPIO_IN; /* 0x404c - 0x4050 */ + volatile u_int32_t HOST_INTF_GPIO_OE; /* 0x4050 - 0x4054 */ + volatile u_int32_t HOST_INTF_GPIO_OE1; /* 0x4054 - 0x4058 */ + volatile u_int32_t HOST_INTF_GPIO_INTR_POLAR; /* 0x4058 - 0x405c */ + volatile u_int32_t HOST_INTF_GPIO_INPUT_VALUE; /* 0x405c - 0x4060 */ + volatile u_int32_t HOST_INTF_GPIO_INPUT_MUX1; /* 0x4060 - 0x4064 */ + volatile u_int32_t HOST_INTF_GPIO_INPUT_MUX2; /* 0x4064 - 0x4068 */ + volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX1; /* 0x4068 - 0x406c */ + volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX2; /* 0x406c - 0x4070 */ + volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX3; /* 0x4070 - 0x4074 */ + volatile u_int32_t HOST_INTF_GPIO_INPUT_STATE; /* 0x4074 - 0x4078 */ + volatile u_int32_t HOST_INTF_SPARE; /* 0x4078 - 0x407c */ + volatile u_int32_t HOST_INTF_PCIE_CORE_RST_EN; /* 0x407c - 0x4080 */ + volatile u_int32_t HOST_INTF_CLKRUN; /* 0x4080 - 0x4084 */ + volatile u_int32_t HOST_INTF_EEPROM_STS; /* 0x4084 - 0x4088 */ + volatile u_int32_t HOST_INTF_OBS_CTRL; /* 0x4088 - 0x408c */ + volatile u_int32_t HOST_INTF_RFSILENT; /* 0x408c - 0x4090 */ + volatile u_int32_t HOST_INTF_GPIO_PDPU; /* 0x4090 - 0x4094 */ + volatile u_int32_t HOST_INTF_GPIO_PDPU1; /* 0x4094 - 0x4098 */ + volatile u_int32_t HOST_INTF_GPIO_DS; /* 0x4098 - 0x409c */ + volatile u_int32_t HOST_INTF_GPIO_DS1; /* 0x409c - 0x40a0 */ + volatile u_int32_t HOST_INTF_MISC; /* 0x40a0 - 0x40a4 */ + volatile u_int32_t HOST_INTF_PCIE_MSI; /* 0x40a4 - 0x40a8 */ + volatile char pad__2[0x8]; /* 0x40a8 - 0x40b0 */ + volatile u_int32_t HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ; + /* 0x40b0 - 0x40b4 */ + volatile u_int32_t HOST_INTF_MAC_TDMA_CCA_CNTL; /* 0x40b4 - 0x40b8 */ + volatile u_int32_t HOST_INTF_MAC_TXAPSYNC; /* 0x40b8 - 0x40bc */ + volatile u_int32_t HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR; + /* 0x40bc - 0x40c0 */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_CAUSE; + /* 0x40c0 - 0x40c4 */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_ENABLE; + /* 0x40c4 - 0x40c8 */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_MASK; + /* 0x40c8 - 0x40cc */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_MASK; + /* 0x40cc - 0x40d0 */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE; + /* 0x40d0 - 0x40d4 */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE; + /* 0x40d4 - 0x40d8 */ + volatile u_int32_t HOST_INTF_OTP; /* 0x40d8 - 0x40dc */ + volatile char pad__3[0x4]; /* 0x40dc - 0x40e0 */ + volatile u_int32_t PCIE_CO_ERR_CTR0; /* 0x40e0 - 0x40e4 */ + volatile u_int32_t PCIE_CO_ERR_CTR1; /* 0x40e4 - 0x40e8 */ + volatile u_int32_t PCIE_CO_ERR_CTR_CTRL; /* 0x40e8 - 0x40ec */ + /* Poseidon, Jupiter */ + volatile u_int32_t AXI_INTERCONNECT_CTRL; /* 0x40ec - 0x40f0 */ + /* Jupiter */ + volatile u_int32_t PCIE_AXI_BRIDGE_CTRL; /* 0x40f0 - 0x40f4 */ +}; + +struct emulation_misc_regs { + volatile char pad__0[0x4f00]; /* 0x0 - 0x4f00 */ + volatile u_int32_t FPGA_PHY_LAYER_REVID; /* 0x4f00 - 0x4f04 */ + volatile u_int32_t FPGA_LINK_LAYER_REVID; /* 0x4f04 - 0x4f08 */ + volatile u_int32_t FPGA_REG1; /* 0x4f08 - 0x4f0c */ + volatile u_int32_t FPGA_REG2; /* 0x4f0c - 0x4f10 */ + volatile u_int32_t FPGA_REG3; /* 0x4f10 - 0x4f14 */ + volatile u_int32_t FPGA_REG4; /* 0x4f14 - 0x4f18 */ + volatile u_int32_t FPGA_REG5; /* 0x4f18 - 0x4f1c */ + volatile u_int32_t FPGA_REG6; /* 0x4f1c - 0x4f20 */ + volatile u_int32_t FPGA_REG7; /* 0x4f20 - 0x4f24 */ + volatile u_int32_t FPGA_REG8; /* 0x4f24 - 0x4f28 */ + volatile u_int32_t FPGA_REG9; /* 0x4f28 - 0x4f2c */ + volatile u_int32_t FPGA_REG10; /* 0x4f2c - 0x4f30 */ + /* Aphrodite-start */ + volatile u_int32_t FPGA_REG11; /* 0x4f30 - 0x4f34 */ + volatile u_int32_t FPGA_REG12; /* 0x4f34 - 0x4f38 */ + volatile u_int32_t FPGA_REG13; /* 0x4f38 - 0x4f3c */ + volatile u_int32_t FPGA_REG14; /* 0x4f3c - 0x4f40 */ + /* Aphrodite-end */ +}; + +struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_0 { + volatile u_int32_t ID; /* 0x0 - 0x4 */ + volatile u_int32_t STS_CMD_RGSTR; /* 0x4 - 0x8 */ + volatile u_int32_t CLS_REV_ID; /* 0x8 - 0xc */ + volatile u_int32_t BIST_HEAD_LAT_CACH; /* 0xc - 0x10 */ + volatile u_int32_t BAS_ADR_0; /* 0x10 - 0x14 */ + volatile u_int32_t BAS_ADR_1; /* 0x14 - 0x18 */ + volatile u_int32_t BAS_ADR_2; /* 0x18 - 0x1c */ + volatile u_int32_t BAS_ADR_3; /* 0x1c - 0x20 */ + volatile u_int32_t BAS_ADR_4; /* 0x20 - 0x24 */ + volatile u_int32_t BAS_ADR_5; /* 0x24 - 0x28 */ + volatile u_int32_t CRD_CIS_PTR; /* 0x28 - 0x2c */ + volatile u_int32_t Sub_VenID; /* 0x2c - 0x30 */ + volatile u_int32_t EXP_ROM_ADDR; /* 0x30 - 0x34 */ + volatile u_int32_t CAPPTR; /* 0x34 - 0x38 */ + volatile u_int32_t RESERVE2; /* 0x38 - 0x3c */ + volatile u_int32_t LAT_INT; /* 0x3c - 0x40 */ +}; + +struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_1 { + volatile u_int32_t CFG_PWR_CAP; /* 0x0 - 0x4 */ + volatile u_int32_t PWR_CSR; /* 0x4 - 0x8 */ +}; + +struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_2 { + volatile u_int32_t MSG_CTR; /* 0x0 - 0x4 */ + volatile u_int32_t MSI_L32; /* 0x4 - 0x8 */ + volatile u_int32_t MSI_U32; /* 0x8 - 0xc */ + volatile u_int32_t MSI_DATA; /* 0xc - 0x10 */ +}; + +struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_3 { + volatile u_int32_t PCIE_CAP; /* 0x0 - 0x4 */ + volatile u_int32_t DEV_CAP; /* 0x4 - 0x8 */ + volatile u_int32_t DEV_STS_CTRL; /* 0x8 - 0xc */ + volatile u_int32_t LNK_CAP; /* 0xc - 0x10 */ + volatile u_int32_t LNK_STS_CTRL; /* 0x10 - 0x14 */ + volatile u_int32_t SLT_CAP; /* 0x14 - 0x18 */ + volatile u_int32_t SLT_STS_CTRL; /* 0x18 - 0x1c */ +}; + +struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_5 { + volatile u_int32_t VPD_CAP; /* 0x0 - 0x4 */ + volatile u_int32_t VPD_DATA; /* 0x4 - 0x8 */ +}; + +struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_6 { + volatile u_int32_t PCIE_EN_CAP_AER; /* 0x0 - 0x4 */ + volatile u_int32_t UN_ERR_ST_R; /* 0x4 - 0x8 */ + volatile u_int32_t UN_ERR_MS_R; /* 0x8 - 0xc */ + volatile u_int32_t UN_ERR_SV_R; /* 0xc - 0x10 */ + volatile u_int32_t CO_ERR_ST_R; /* 0x10 - 0x14 */ + volatile u_int32_t CO_ERR_MS_R; /* 0x14 - 0x18 */ + volatile u_int32_t ADERR_CAP_CR; /* 0x18 - 0x1c */ + volatile u_int32_t HD_L_R0; /* 0x1c - 0x20 */ + volatile u_int32_t HD_L_R4; /* 0x20 - 0x24 */ + volatile u_int32_t HD_L_R8; /* 0x24 - 0x28 */ + volatile u_int32_t HD_L_R12; /* 0x28 - 0x2c */ +}; + +struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_7 { + volatile u_int32_t PCIE_EN_CAP_VC; /* 0x0 - 0x4 */ + volatile u_int32_t PVC_CAP_R1; /* 0x4 - 0x8 */ + volatile u_int32_t P_CAP_R2; /* 0x8 - 0xc */ + volatile u_int32_t PVC_STS_CTRL; /* 0xc - 0x10 */ + volatile u_int32_t VC_CAP_R; /* 0x10 - 0x14 */ + volatile u_int32_t VC_CTL_R; /* 0x14 - 0x18 */ + volatile u_int32_t VC_STS_RSV; /* 0x18 - 0x1c */ + volatile u_int32_t VCR_CAP_R1; /* 0x1c - 0x20 */ + volatile u_int32_t VCR_CTRL_R1; /* 0x20 - 0x24 */ + volatile u_int32_t VCR_STS_R1; /* 0x24 - 0x28 */ +}; + +struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_7_Jupiter { + volatile u_int32_t PCIE_EN_CAP_VC; /* 0x0 - 0x4 */ + volatile u_int32_t PVC_CAP_R1; /* 0x4 - 0x8 */ + volatile u_int32_t P_CAP_R2; /* 0x8 - 0xc */ + volatile u_int32_t PVC_STS_CTRL; /* 0xc - 0x10 */ + volatile u_int32_t VC_CAP_R; /* 0x10 - 0x14 */ + volatile u_int32_t VC_CTL_R; /* 0x14 - 0x18 */ + volatile u_int32_t VC_STS_RSV; /* 0x18 - 0x1c */ +}; + +struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_8 { + volatile u_int32_t DEV_EN_CAP; /* 0x0 - 0x4 */ + volatile u_int32_t SN_R1; /* 0x4 - 0x8 */ + volatile u_int32_t SN_R2; /* 0x8 - 0xc */ +}; + +struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_9 { + volatile u_int32_t LAT_REL_TIM; /* 0x0 - 0x4 */ + volatile u_int32_t OT_MSG_R; /* 0x4 - 0x8 */ + volatile u_int32_t PT_LNK_R; /* 0x8 - 0xc */ + volatile u_int32_t ACk_FREQ_R; /* 0xc - 0x10 */ + volatile u_int32_t PT_LNK_CTRL_R; /* 0x10 - 0x14 */ + volatile u_int32_t LN_SKW_R; /* 0x14 - 0x18 */ + volatile u_int32_t SYMB_N_R; /* 0x18 - 0x1c */ + volatile u_int32_t SYMB_T_R; /* 0x1c - 0x20 */ + volatile u_int32_t FL_MSK_R2; /* 0x20 - 0x24 */ + volatile char pad__0[0x4]; /* 0x24 - 0x28 */ + volatile u_int32_t DB_R0; /* 0x28 - 0x2c */ + volatile u_int32_t DB_R1; /* 0x2c - 0x30 */ + volatile u_int32_t TR_P_STS_R; /* 0x30 - 0x34 */ + volatile u_int32_t TR_NP_STS_R; /* 0x34 - 0x38 */ + volatile u_int32_t TR_C_STS_R; /* 0x38 - 0x3c */ + volatile u_int32_t Q_STS_R; /* 0x3c - 0x40 */ + volatile u_int32_t VC_TR_A_R1; /* 0x40 - 0x44 */ + volatile u_int32_t VC_TR_A_R2; /* 0x44 - 0x48 */ + volatile u_int32_t VC0_PR_Q_C; /* 0x48 - 0x4c */ + volatile u_int32_t VC0_NPR_Q_C; /* 0x4c - 0x50 */ + volatile u_int32_t VC0_CR_Q_C; /* 0x50 - 0x54 */ + volatile u_int32_t VC1_PR_Q_C; /* 0x54 - 0x58 */ + volatile u_int32_t VC1_NPR_Q_C; /* 0x58 - 0x5c */ + volatile u_int32_t VC1_CR_Q_C; /* 0x5c - 0x60 */ + volatile u_int32_t VC2_PR_Q_C; /* 0x60 - 0x64 */ + volatile u_int32_t VC2_NPR_Q_C; /* 0x64 - 0x68 */ + volatile u_int32_t VC2_CR_Q_C; /* 0x68 - 0x6c */ + volatile u_int32_t VC3_PR_Q_C; /* 0x6c - 0x70 */ + volatile u_int32_t VC3_NPR_Q_C; /* 0x70 - 0x74 */ + volatile u_int32_t VC3_CR_Q_C; /* 0x74 - 0x78 */ + volatile u_int32_t VC4_PR_Q_C; /* 0x78 - 0x7c */ + volatile u_int32_t VC4_NPR_Q_C; /* 0x7c - 0x80 */ + volatile u_int32_t VC4_CR_Q_C; /* 0x80 - 0x84 */ + volatile u_int32_t VC5_PR_Q_C; /* 0x84 - 0x88 */ + volatile u_int32_t VC5_NPR_Q_C; /* 0x88 - 0x8c */ + volatile u_int32_t VC5_CR_Q_C; /* 0x8c - 0x90 */ + volatile u_int32_t VC6_PR_Q_C; /* 0x90 - 0x94 */ + volatile u_int32_t VC6_NPR_Q_C; /* 0x94 - 0x98 */ + volatile u_int32_t VC6_CR_Q_C; /* 0x98 - 0x9c */ + volatile u_int32_t VC7_PR_Q_C; /* 0x9c - 0xa0 */ + volatile u_int32_t VC7_NPR_Q_C; /* 0xa0 - 0xa4 */ + volatile u_int32_t VC7_CR_Q_C; /* 0xa4 - 0xa8 */ + volatile u_int32_t VC0_PB_D; /* 0xa8 - 0xac */ + volatile u_int32_t VC0_NPB_D; /* 0xac - 0xb0 */ + volatile u_int32_t VC0_CB_D; /* 0xb0 - 0xb4 */ + volatile u_int32_t VC1_PB_D; /* 0xb4 - 0xb8 */ + volatile u_int32_t VC1_NPB_D; /* 0xb8 - 0xbc */ + volatile u_int32_t VC1_CB_D; /* 0xbc - 0xc0 */ + volatile u_int32_t VC2_PB_D; /* 0xc0 - 0xc4 */ + volatile u_int32_t VC2_NPB_D; /* 0xc4 - 0xc8 */ + volatile u_int32_t VC2_CB_D; /* 0xc8 - 0xcc */ + volatile u_int32_t VC3_PB_D; /* 0xcc - 0xd0 */ + volatile u_int32_t VC3_NPB_D; /* 0xd0 - 0xd4 */ + volatile u_int32_t VC3_CB_D; /* 0xd4 - 0xd8 */ + volatile u_int32_t VC4_PB_D; /* 0xd8 - 0xdc */ + volatile u_int32_t VC4_NPB_D; /* 0xdc - 0xe0 */ + volatile u_int32_t VC4_CB_D; /* 0xe0 - 0xe4 */ + volatile u_int32_t VC5_PB_D; /* 0xe4 - 0xe8 */ + volatile u_int32_t VC5_NPB_D; /* 0xe8 - 0xec */ + volatile u_int32_t VC5_CB_D; /* 0xec - 0xf0 */ + volatile u_int32_t VC6_PB_D; /* 0xf0 - 0xf4 */ + volatile u_int32_t VC6_NPB_D; /* 0xf4 - 0xf8 */ + volatile u_int32_t VC6_CB_D; /* 0xf8 - 0xfc */ + volatile u_int32_t VC7_PB_D; /* 0xfc - 0x100 */ + volatile u_int32_t VC7_NPB_D; /* 0x100 - 0x104 */ + volatile u_int32_t VC7_CB_D; /* 0x104 - 0x108 */ + volatile char pad__1[0x4]; /* 0x108 - 0x10c */ + volatile u_int32_t GEN2; /* 0x10c - 0x110 */ + volatile u_int32_t PHY_STS_R; /* 0x110 - 0x114 */ + volatile u_int32_t PHY_CTRL_R; /* 0x114 - 0x118 */ +}; + +struct DWC_pcie_dbi_axi { + volatile char pad__0[0x5000]; /* 0x0 - 0x5000 */ + struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_0 DWC_pcie_dbi_axi_0; + /* 0x5000 - 0x5040 */ + struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_1 DWC_pcie_dbi_axi_1; + /* 0x5040 - 0x5048 */ + volatile char pad__1[0x8]; /* 0x5048 - 0x5050 */ + struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_2 DWC_pcie_dbi_axi_2; + /* 0x5050 - 0x5060 */ + volatile char pad__2[0x10]; /* 0x5060 - 0x5070 */ + struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_3 DWC_pcie_dbi_axi_3; + /* 0x5070 - 0x508c */ + volatile char pad__3[0x44]; /* 0x508c - 0x50d0 */ + struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_5 DWC_pcie_dbi_axi_5; + /* 0x50d0 - 0x50d8 */ + volatile char pad__4[0x28]; /* 0x50d8 - 0x5100 */ + struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_6 DWC_pcie_dbi_axi_6; + /* 0x5100 - 0x512c */ + volatile char pad__5[0x14]; /* 0x512c - 0x5140 */ + union { + struct { + struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_7 DWC_pcie_dbi_axi_7; + /* 0x5140 - 0x5168 */ + volatile char pad__1[0x198]; /* 0x5168 - 0x5300 */ + struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_8 DWC_pcie_dbi_axi_8; + /* 0x5300 - 0x530c */ + volatile char pad__2[0x3f4]; /* 0x530c - 0x5700 */ + } Osprey; + + struct pcie_dbi_axi { + struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_7_Jupiter DWC_pcie_dbi_axi_7; + /* 0x5140 - 0x515c */ + volatile char pad__1[0x4]; /* 0x515c - 0x5160 */ + struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_8 DWC_pcie_dbi_axi_8; + /* 0x5160 - 0x516c */ + volatile char pad__2[0x594]; /* 0x516c - 0x5700 */ + } Jupiter; + } overlay_0x5140; /* 0x5140 - 0x5700 */ + struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_9 DWC_pcie_dbi_axi_9; + /* 0x5700 - 0x5818 */ +}; + +struct rtc_reg { + volatile char pad__0[0x7000]; /* 0x0 - 0x7000 */ + volatile u_int32_t RESET_CONTROL; /* 0x7000 - 0x7004 */ + volatile u_int32_t XTAL_CONTROL; /* 0x7004 - 0x7008 */ + volatile u_int32_t REG_CONTROL0; /* 0x7008 - 0x700c */ + volatile u_int32_t REG_CONTROL1; /* 0x700c - 0x7010 */ + volatile u_int32_t QUADRATURE; /* 0x7010 - 0x7014 */ + volatile u_int32_t PLL_CONTROL; /* 0x7014 - 0x7018 */ + volatile u_int32_t PLL_SETTLE; /* 0x7018 - 0x701c */ + volatile u_int32_t XTAL_SETTLE; /* 0x701c - 0x7020 */ + volatile u_int32_t CLOCK_OUT; /* 0x7020 - 0x7024 */ + volatile u_int32_t BIAS_OVERRIDE; /* 0x7024 - 0x7028 */ + volatile u_int32_t RESET_CAUSE; /* 0x7028 - 0x702c */ + volatile u_int32_t SYSTEM_SLEEP; /* 0x702c - 0x7030 */ + volatile u_int32_t MAC_SLEEP_CONTROL; /* 0x7030 - 0x7034 */ + volatile u_int32_t KEEP_AWAKE; /* 0x7034 - 0x7038 */ + volatile u_int32_t DERIVED_RTC_CLK; /* 0x7038 - 0x703c */ + volatile u_int32_t PLL_CONTROL2; /* 0x703c - 0x7040 */ +}; + +struct rtc_sync_reg { + volatile char pad__0[0x7040]; /* 0x0 - 0x7040 */ + volatile u_int32_t RTC_SYNC_RESET; /* 0x7040 - 0x7044 */ + volatile u_int32_t RTC_SYNC_STATUS; /* 0x7044 - 0x7048 */ + volatile u_int32_t RTC_SYNC_DERIVED; /* 0x7048 - 0x704c */ + volatile u_int32_t RTC_SYNC_FORCE_WAKE; /* 0x704c - 0x7050 */ + volatile u_int32_t RTC_SYNC_INTR_CAUSE; /* 0x7050 - 0x7054 */ + volatile u_int32_t RTC_SYNC_INTR_ENABLE; /* 0x7054 - 0x7058 */ + volatile u_int32_t RTC_SYNC_INTR_MASK; /* 0x7058 - 0x705c */ +}; + +struct merlin2_0_radio_reg_map { + volatile char pad__0[0x7800]; /* 0x0 - 0x7800 */ + volatile u_int32_t RXTXBB1_CH1; /* 0x7800 - 0x7804 */ + volatile u_int32_t RXTXBB2_CH1; /* 0x7804 - 0x7808 */ + volatile u_int32_t RXTXBB3_CH1; /* 0x7808 - 0x780c */ + volatile u_int32_t RXTXBB4_CH1; /* 0x780c - 0x7810 */ + volatile u_int32_t RF2G1_CH1; /* 0x7810 - 0x7814 */ + volatile u_int32_t RF2G2_CH1; /* 0x7814 - 0x7818 */ + volatile u_int32_t RF5G1_CH1; /* 0x7818 - 0x781c */ + volatile u_int32_t RF5G2_CH1; /* 0x781c - 0x7820 */ + volatile u_int32_t RF5G3_CH1; /* 0x7820 - 0x7824 */ + volatile u_int32_t RXTXBB1_CH0; /* 0x7824 - 0x7828 */ + volatile u_int32_t RXTXBB2_CH0; /* 0x7828 - 0x782c */ + volatile u_int32_t RXTXBB3_CH0; /* 0x782c - 0x7830 */ + volatile u_int32_t RXTXBB4_CH0; /* 0x7830 - 0x7834 */ + volatile u_int32_t RF5G1_CH0; /* 0x7834 - 0x7838 */ + volatile u_int32_t RF5G2_CH0; /* 0x7838 - 0x783c */ + volatile u_int32_t RF5G3_CH0; /* 0x783c - 0x7840 */ + volatile u_int32_t RF2G1_CH0; /* 0x7840 - 0x7844 */ + volatile u_int32_t RF2G2_CH0; /* 0x7844 - 0x7848 */ + volatile u_int32_t SYNTH1; /* 0x7848 - 0x784c */ + volatile u_int32_t SYNTH2; /* 0x784c - 0x7850 */ + volatile u_int32_t SYNTH3; /* 0x7850 - 0x7854 */ + volatile u_int32_t SYNTH4; /* 0x7854 - 0x7858 */ + volatile u_int32_t SYNTH5; /* 0x7858 - 0x785c */ + volatile u_int32_t SYNTH6; /* 0x785c - 0x7860 */ + volatile u_int32_t SYNTH7; /* 0x7860 - 0x7864 */ + volatile u_int32_t SYNTH8; /* 0x7864 - 0x7868 */ + volatile u_int32_t SYNTH9; /* 0x7868 - 0x786c */ + volatile u_int32_t SYNTH10; /* 0x786c - 0x7870 */ + volatile u_int32_t SYNTH11; /* 0x7870 - 0x7874 */ + volatile u_int32_t BIAS1; /* 0x7874 - 0x7878 */ + volatile u_int32_t BIAS2; /* 0x7878 - 0x787c */ + volatile u_int32_t BIAS3; /* 0x787c - 0x7880 */ + volatile u_int32_t BIAS4; /* 0x7880 - 0x7884 */ + volatile u_int32_t GAIN0; /* 0x7884 - 0x7888 */ + volatile u_int32_t GAIN1; /* 0x7888 - 0x788c */ + volatile u_int32_t TOP0; /* 0x788c - 0x7890 */ + volatile u_int32_t TOP1; /* 0x7890 - 0x7894 */ + volatile u_int32_t TOP2; /* 0x7894 - 0x7898 */ + volatile u_int32_t TOP3; /* 0x7898 - 0x789c */ +}; + +struct analog_intf_reg_csr { + volatile char pad__0[0x7900]; /* 0x0 - 0x7900 */ + volatile u_int32_t SW_OVERRIDE; /* 0x7900 - 0x7904 */ + volatile u_int32_t SIN_VAL; /* 0x7904 - 0x7908 */ + volatile u_int32_t SW_SCLK; /* 0x7908 - 0x790c */ + volatile u_int32_t SW_CNTL; /* 0x790c - 0x7910 */ +}; + +struct mac_pcu_reg { + volatile char pad__0[0x8000]; /* 0x0 - 0x8000 */ + volatile u_int32_t MAC_PCU_STA_ADDR_L32; /* 0x8000 - 0x8004 */ + volatile u_int32_t MAC_PCU_STA_ADDR_U16; /* 0x8004 - 0x8008 */ + volatile u_int32_t MAC_PCU_BSSID_L32; /* 0x8008 - 0x800c */ + volatile u_int32_t MAC_PCU_BSSID_U16; /* 0x800c - 0x8010 */ + volatile u_int32_t MAC_PCU_BCN_RSSI_AVE; /* 0x8010 - 0x8014 */ + volatile u_int32_t MAC_PCU_ACK_CTS_TIMEOUT; /* 0x8014 - 0x8018 */ + volatile u_int32_t MAC_PCU_BCN_RSSI_CTL; /* 0x8018 - 0x801c */ + volatile u_int32_t MAC_PCU_USEC_LATENCY; /* 0x801c - 0x8020 */ + volatile u_int32_t MAC_PCU_RESET_TSF; /* 0x8020 - 0x8024 */ + volatile char pad__1[0x14]; /* 0x8024 - 0x8038 */ + volatile u_int32_t MAC_PCU_MAX_CFP_DUR; /* 0x8038 - 0x803c */ + volatile u_int32_t MAC_PCU_RX_FILTER; /* 0x803c - 0x8040 */ + volatile u_int32_t MAC_PCU_MCAST_FILTER_L32; /* 0x8040 - 0x8044 */ + volatile u_int32_t MAC_PCU_MCAST_FILTER_U32; /* 0x8044 - 0x8048 */ + volatile u_int32_t MAC_PCU_DIAG_SW; /* 0x8048 - 0x804c */ + volatile u_int32_t MAC_PCU_TSF_L32; /* 0x804c - 0x8050 */ + volatile u_int32_t MAC_PCU_TSF_U32; /* 0x8050 - 0x8054 */ + volatile u_int32_t MAC_PCU_TST_ADDAC; /* 0x8054 - 0x8058 */ + volatile u_int32_t MAC_PCU_DEF_ANTENNA; /* 0x8058 - 0x805c */ + volatile u_int32_t MAC_PCU_AES_MUTE_MASK_0; /* 0x805c - 0x8060 */ + volatile u_int32_t MAC_PCU_AES_MUTE_MASK_1; /* 0x8060 - 0x8064 */ + volatile u_int32_t MAC_PCU_GATED_CLKS; /* 0x8064 - 0x8068 */ + volatile u_int32_t MAC_PCU_OBS_BUS_2; /* 0x8068 - 0x806c */ + volatile u_int32_t MAC_PCU_OBS_BUS_1; /* 0x806c - 0x8070 */ + volatile u_int32_t MAC_PCU_DYM_MIMO_PWR_SAVE; /* 0x8070 - 0x8074 */ + volatile u_int32_t MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB; + /* 0x8074 - 0x8078 */ + volatile u_int32_t MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB; + /* 0x8078 - 0x807c */ + volatile char pad__2[0x4]; /* 0x807c - 0x8080 */ + volatile u_int32_t MAC_PCU_LAST_BEACON_TSF; /* 0x8080 - 0x8084 */ + volatile u_int32_t MAC_PCU_NAV; /* 0x8084 - 0x8088 */ + volatile u_int32_t MAC_PCU_RTS_SUCCESS_CNT; /* 0x8088 - 0x808c */ + volatile u_int32_t MAC_PCU_RTS_FAIL_CNT; /* 0x808c - 0x8090 */ + volatile u_int32_t MAC_PCU_ACK_FAIL_CNT; /* 0x8090 - 0x8094 */ + volatile u_int32_t MAC_PCU_FCS_FAIL_CNT; /* 0x8094 - 0x8098 */ + volatile u_int32_t MAC_PCU_BEACON_CNT; /* 0x8098 - 0x809c */ + volatile u_int32_t MAC_PCU_TDMA_SLOT_ALERT_CNTL; + /* 0x809c - 0x80a0 */ + volatile u_int32_t MAC_PCU_BASIC_SET; /* 0x80a0 - 0x80a4 */ + volatile u_int32_t MAC_PCU_MGMT_SEQ; /* 0x80a4 - 0x80a8 */ + volatile u_int32_t MAC_PCU_BF_RPT1; /* 0x80a8 - 0x80ac */ + volatile u_int32_t MAC_PCU_BF_RPT2; /* 0x80ac - 0x80b0 */ + volatile u_int32_t MAC_PCU_TX_ANT_1; /* 0x80b0 - 0x80b4 */ + volatile u_int32_t MAC_PCU_TX_ANT_2; /* 0x80b4 - 0x80b8 */ + volatile u_int32_t MAC_PCU_TX_ANT_3; /* 0x80b8 - 0x80bc */ + volatile u_int32_t MAC_PCU_TX_ANT_4; /* 0x80bc - 0x80c0 */ + volatile u_int32_t MAC_PCU_XRMODE; /* 0x80c0 - 0x80c4 */ + volatile u_int32_t MAC_PCU_XRDEL; /* 0x80c4 - 0x80c8 */ + volatile u_int32_t MAC_PCU_XRTO; /* 0x80c8 - 0x80cc */ + volatile u_int32_t MAC_PCU_XRCRP; /* 0x80cc - 0x80d0 */ + volatile u_int32_t MAC_PCU_XRSTMP; /* 0x80d0 - 0x80d4 */ + volatile u_int32_t MAC_PCU_SLP1; /* 0x80d4 - 0x80d8 */ + volatile u_int32_t MAC_PCU_SLP2; /* 0x80d8 - 0x80dc */ + volatile u_int32_t MAC_PCU_SELF_GEN_DEFAULT; /* 0x80dc - 0x80e0 */ + volatile u_int32_t MAC_PCU_ADDR1_MASK_L32; /* 0x80e0 - 0x80e4 */ + volatile u_int32_t MAC_PCU_ADDR1_MASK_U16; /* 0x80e4 - 0x80e8 */ + volatile u_int32_t MAC_PCU_TPC; /* 0x80e8 - 0x80ec */ + volatile u_int32_t MAC_PCU_TX_FRAME_CNT; /* 0x80ec - 0x80f0 */ + volatile u_int32_t MAC_PCU_RX_FRAME_CNT; /* 0x80f0 - 0x80f4 */ + volatile u_int32_t MAC_PCU_RX_CLEAR_CNT; /* 0x80f4 - 0x80f8 */ + volatile u_int32_t MAC_PCU_CYCLE_CNT; /* 0x80f8 - 0x80fc */ + volatile u_int32_t MAC_PCU_QUIET_TIME_1; /* 0x80fc - 0x8100 */ + volatile u_int32_t MAC_PCU_QUIET_TIME_2; /* 0x8100 - 0x8104 */ + volatile char pad__3[0x4]; /* 0x8104 - 0x8108 */ + volatile u_int32_t MAC_PCU_QOS_NO_ACK; /* 0x8108 - 0x810c */ + volatile u_int32_t MAC_PCU_PHY_ERROR_MASK; /* 0x810c - 0x8110 */ + volatile u_int32_t MAC_PCU_XRLAT; /* 0x8110 - 0x8114 */ + volatile u_int32_t MAC_PCU_RXBUF; /* 0x8114 - 0x8118 */ + volatile u_int32_t MAC_PCU_MIC_QOS_CONTROL; /* 0x8118 - 0x811c */ + volatile u_int32_t MAC_PCU_MIC_QOS_SELECT; /* 0x811c - 0x8120 */ + volatile u_int32_t MAC_PCU_MISC_MODE; /* 0x8120 - 0x8124 */ + volatile u_int32_t MAC_PCU_FILTER_OFDM_CNT; /* 0x8124 - 0x8128 */ + volatile u_int32_t MAC_PCU_FILTER_CCK_CNT; /* 0x8128 - 0x812c */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_1; /* 0x812c - 0x8130 */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_1_MASK; /* 0x8130 - 0x8134 */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_2; /* 0x8134 - 0x8138 */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_2_MASK; /* 0x8138 - 0x813c */ + volatile u_int32_t MAC_PCU_TSF_THRESHOLD; /* 0x813c - 0x8140 */ + volatile char pad__4[0x4]; /* 0x8140 - 0x8144 */ + volatile u_int32_t MAC_PCU_PHY_ERROR_EIFS_MASK; /* 0x8144 - 0x8148 */ + volatile char pad__5[0x20]; /* 0x8148 - 0x8168 */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_3; /* 0x8168 - 0x816c */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_3_MASK; /* 0x816c - 0x8170 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_MODE; /* 0x8170 - 0x8174 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_WL_WEIGHTS0; + /* 0x8174 - 0x8178 */ + volatile u_int32_t MAC_PCU_HCF_TIMEOUT; /* 0x8178 - 0x817c */ + volatile u_int32_t MAC_PCU_BLUETOOTH_MODE2; /* 0x817c - 0x8180 */ + volatile u_int32_t MAC_PCU_GENERIC_TIMERS2[16]; /* 0x8180 - 0x81c0 */ + volatile u_int32_t MAC_PCU_GENERIC_TIMERS2_MODE; + /* 0x81c0 - 0x81c4 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_WL_WEIGHTS1; + /* 0x81c4 - 0x81c8 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE; + /* 0x81c8 - 0x81cc */ + volatile u_int32_t MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY; + /* 0x81cc - 0x81d0 */ + volatile u_int32_t MAC_PCU_TXSIFS; /* 0x81d0 - 0x81d4 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_MODE3; /* 0x81d4 - 0x81d8 */ + volatile char pad__6[0x14]; /* 0x81d8 - 0x81ec */ + volatile u_int32_t MAC_PCU_TXOP_X; /* 0x81ec - 0x81f0 */ + volatile u_int32_t MAC_PCU_TXOP_0_3; /* 0x81f0 - 0x81f4 */ + volatile u_int32_t MAC_PCU_TXOP_4_7; /* 0x81f4 - 0x81f8 */ + volatile u_int32_t MAC_PCU_TXOP_8_11; /* 0x81f8 - 0x81fc */ + volatile u_int32_t MAC_PCU_TXOP_12_15; /* 0x81fc - 0x8200 */ + volatile u_int32_t MAC_PCU_GENERIC_TIMERS[16]; /* 0x8200 - 0x8240 */ + volatile u_int32_t MAC_PCU_GENERIC_TIMERS_MODE; /* 0x8240 - 0x8244 */ + volatile u_int32_t MAC_PCU_SLP32_MODE; /* 0x8244 - 0x8248 */ + volatile u_int32_t MAC_PCU_SLP32_WAKE; /* 0x8248 - 0x824c */ + volatile u_int32_t MAC_PCU_SLP32_INC; /* 0x824c - 0x8250 */ + volatile u_int32_t MAC_PCU_SLP_MIB1; /* 0x8250 - 0x8254 */ + volatile u_int32_t MAC_PCU_SLP_MIB2; /* 0x8254 - 0x8258 */ + volatile u_int32_t MAC_PCU_SLP_MIB3; /* 0x8258 - 0x825c */ + volatile u_int32_t MAC_PCU_WOW1; /* 0x825c - 0x8260 */ + volatile u_int32_t MAC_PCU_WOW2; /* 0x8260 - 0x8264 */ + volatile u_int32_t MAC_PCU_LOGIC_ANALYZER; /* 0x8264 - 0x8268 */ + volatile u_int32_t MAC_PCU_LOGIC_ANALYZER_32L; /* 0x8268 - 0x826c */ + volatile u_int32_t MAC_PCU_LOGIC_ANALYZER_16U; /* 0x826c - 0x8270 */ + volatile u_int32_t MAC_PCU_WOW3_BEACON_FAIL; /* 0x8270 - 0x8274 */ + volatile u_int32_t MAC_PCU_WOW3_BEACON; /* 0x8274 - 0x8278 */ + volatile u_int32_t MAC_PCU_WOW3_KEEP_ALIVE; /* 0x8278 - 0x827c */ + volatile u_int32_t MAC_PCU_WOW_KA; /* 0x827c - 0x8280 */ + volatile char pad__7[0x4]; /* 0x8280 - 0x8284 */ + volatile u_int32_t PCU_1US; /* 0x8284 - 0x8288 */ + volatile u_int32_t PCU_KA; /* 0x8288 - 0x828c */ + volatile u_int32_t WOW_EXACT; /* 0x828c - 0x8290 */ + volatile char pad__8[0x4]; /* 0x8290 - 0x8294 */ + volatile u_int32_t PCU_WOW4; /* 0x8294 - 0x8298 */ + volatile u_int32_t PCU_WOW5; /* 0x8298 - 0x829c */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_MASK_CONT; + /* 0x829c - 0x82a0 */ + volatile char pad__9[0x60]; /* 0x82a0 - 0x8300 */ + volatile u_int32_t MAC_PCU_AZIMUTH_MODE; /* 0x8300 - 0x8304 */ + volatile char pad__10[0x10]; /* 0x8304 - 0x8314 */ + volatile u_int32_t MAC_PCU_AZIMUTH_TIME_STAMP; /* 0x8314 - 0x8318 */ + volatile u_int32_t MAC_PCU_20_40_MODE; /* 0x8318 - 0x831c */ + volatile u_int32_t MAC_PCU_H_XFER_TIMEOUT; /* 0x831c - 0x8320 */ + volatile char pad__11[0x8]; /* 0x8320 - 0x8328 */ + volatile u_int32_t MAC_PCU_RX_CLEAR_DIFF_CNT; /* 0x8328 - 0x832c */ + volatile u_int32_t MAC_PCU_SELF_GEN_ANTENNA_MASK; + /* 0x832c - 0x8330 */ + volatile u_int32_t MAC_PCU_BA_BAR_CONTROL; /* 0x8330 - 0x8334 */ + volatile u_int32_t MAC_PCU_LEGACY_PLCP_SPOOF; /* 0x8334 - 0x8338 */ + volatile u_int32_t MAC_PCU_PHY_ERROR_MASK_CONT; /* 0x8338 - 0x833c */ + volatile u_int32_t MAC_PCU_TX_TIMER; /* 0x833c - 0x8340 */ + volatile u_int32_t MAC_PCU_TXBUF_CTRL; /* 0x8340 - 0x8344 */ + volatile u_int32_t MAC_PCU_MISC_MODE2; /* 0x8344 - 0x8348 */ + volatile u_int32_t MAC_PCU_ALT_AES_MUTE_MASK; /* 0x8348 - 0x834c */ + volatile u_int32_t MAC_PCU_WOW6; /* 0x834c - 0x8350 */ + volatile u_int32_t ASYNC_FIFO_REG1; /* 0x8350 - 0x8354 */ + volatile u_int32_t ASYNC_FIFO_REG2; /* 0x8354 - 0x8358 */ + volatile u_int32_t ASYNC_FIFO_REG3; /* 0x8358 - 0x835c */ + volatile u_int32_t MAC_PCU_WOW5; /* 0x835c - 0x8360 */ + volatile u_int32_t MAC_PCU_WOW_LENGTH1; /* 0x8360 - 0x8364 */ + volatile u_int32_t MAC_PCU_WOW_LENGTH2; /* 0x8364 - 0x8368 */ + volatile u_int32_t WOW_PATTERN_MATCH_LESS_THAN_256_BYTES; + /* 0x8368 - 0x836c */ + volatile char pad__12[0x4]; /* 0x836c - 0x8370 */ + volatile u_int32_t MAC_PCU_WOW4; /* 0x8370 - 0x8374 */ + volatile u_int32_t WOW2_EXACT; /* 0x8374 - 0x8378 */ + volatile u_int32_t PCU_WOW6; /* 0x8378 - 0x837c */ + volatile u_int32_t PCU_WOW7; /* 0x837c - 0x8380 */ + volatile u_int32_t MAC_PCU_WOW_LENGTH3; /* 0x8380 - 0x8384 */ + volatile u_int32_t MAC_PCU_WOW_LENGTH4; /* 0x8384 - 0x8388 */ + volatile u_int32_t MAC_PCU_LOCATION_MODE_CONTROL; + /* 0x8388 - 0x838c */ + volatile u_int32_t MAC_PCU_LOCATION_MODE_TIMER; /* 0x838c - 0x8390 */ + volatile u_int32_t MAC_PCU_TSF2_L32; /* 0x8390 - 0x8394 */ + volatile u_int32_t MAC_PCU_TSF2_U32; /* 0x8394 - 0x8398 */ + volatile u_int32_t MAC_PCU_BSSID2_L32; /* 0x8398 - 0x839c */ + volatile u_int32_t MAC_PCU_BSSID2_U16; /* 0x839c - 0x83a0 */ + volatile u_int32_t MAC_PCU_DIRECT_CONNECT; /* 0x83a0 - 0x83a4 */ + volatile u_int32_t MAC_PCU_TID_TO_AC; /* 0x83a4 - 0x83a8 */ + volatile u_int32_t MAC_PCU_HP_QUEUE; /* 0x83a8 - 0x83ac */ + volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS0; + /* 0x83ac - 0x83b0 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS1; + /* 0x83b0 - 0x83b4 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS2; + /* 0x83b4 - 0x83b8 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS3; + /* 0x83b8 - 0x83bc */ + volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT0; /* 0x83bc - 0x83c0 */ + volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT1; /* 0x83c0 - 0x83c4 */ + volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT2; /* 0x83c4 - 0x83c8 */ + volatile u_int32_t MAC_PCU_HW_BCN_PROC1; /* 0x83c8 - 0x83cc */ + volatile u_int32_t MAC_PCU_HW_BCN_PROC2; /* 0x83cc - 0x83d0 */ + volatile u_int32_t MAC_PCU_MISC_MODE3; /* 0x83d0 - 0x83d4 */ + /* Jupiter */ + volatile u_int32_t MAC_PCU_FILTER_RSSI_AVE; /* 0x83d4 - 0x83d8 */ + /* Jupiter */ + volatile u_int32_t MAC_PCU_GENERIC_TIMERS_TSF_SEL; + /* 0x83d8 - 0x83dc */ + /* Jupiter */ + volatile u_int32_t MAC_PCU_BEACON2_CNT; /* 0x83dc - 0x83e0 */ + /* Jupiter */ + volatile u_int32_t MAC_PCU_LAST_BEACON2_TSF; /* 0x83e0 - 0x83e4 */ + /* Jupiter */ + volatile u_int32_t MAC_PCU_BMISS_TIMEOUT; /* 0x83e4 - 0x83e8 */ + /* Jupiter */ + volatile u_int32_t MAC_PCU_BMISS2_TIMEOUT; /* 0x83e8 - 0x83ec */ + /* Jupiter */ + volatile u_int32_t MAC_PCU_SLP3; /* 0x83ec - 0x83f0 */ + /* Jupiter */ + volatile u_int32_t MAC_PCU_BCN_RSSI_CTL2; /* 0x83f0 - 0x83f4 */ + /* Jupiter */ + volatile u_int32_t MAC_PCU_PHY_ERROR_AIFS_MASK; /* 0x83f4 - 0x83f8 */ + /* Jupiter_20 */ + volatile u_int32_t MAC_PCU_TBD_FILTER; /* 0x83f8 - 0x83fc */ + /* Jupiter_20 */ + volatile u_int32_t MAC_PCU_MISC_MODE4; /* 0x83fc - 0x8400 */ + volatile u_int32_t MAC_PCU_TXBUF_BA[64]; /* 0x8400 - 0x8500 */ + /* Jupiter_20 */ + volatile u_int32_t MAC_PCU_SLP4; /* 0x8500 - 0x8504 */ + volatile char pad__13[0x2fc]; /* 0x8504 - 0x8800 */ + volatile u_int32_t MAC_PCU_KEY_CACHE[1024]; /* 0x8800 - 0x9800 */ + volatile char pad__14[0x4800]; /* 0x9800 - 0xe000 */ + volatile u_int32_t MAC_PCU_BUF[2048]; /* 0xe000 - 0x10000 */ +}; + +struct chn_reg_map { + volatile u_int32_t BB_timing_controls_1; /* 0x0 - 0x4 */ + volatile u_int32_t BB_timing_controls_2; /* 0x4 - 0x8 */ + volatile u_int32_t BB_timing_controls_3; /* 0x8 - 0xc */ + volatile u_int32_t BB_timing_control_4; /* 0xc - 0x10 */ + volatile u_int32_t BB_timing_control_5; /* 0x10 - 0x14 */ + volatile u_int32_t BB_timing_control_6; /* 0x14 - 0x18 */ + volatile u_int32_t BB_timing_control_11; /* 0x18 - 0x1c */ + volatile u_int32_t BB_spur_mask_controls; /* 0x1c - 0x20 */ + volatile u_int32_t BB_find_signal_low; /* 0x20 - 0x24 */ + volatile u_int32_t BB_sfcorr; /* 0x24 - 0x28 */ + volatile u_int32_t BB_self_corr_low; /* 0x28 - 0x2c */ + volatile u_int32_t BB_ext_chan_scorr_thr; /* 0x2c - 0x30 */ + volatile u_int32_t BB_ext_chan_pwr_thr_2_b0; /* 0x30 - 0x34 */ + volatile u_int32_t BB_radar_detection; /* 0x34 - 0x38 */ + volatile u_int32_t BB_radar_detection_2; /* 0x38 - 0x3c */ + volatile u_int32_t BB_extension_radar; /* 0x3c - 0x40 */ + volatile char pad__0[0x40]; /* 0x40 - 0x80 */ + volatile u_int32_t BB_multichain_control; /* 0x80 - 0x84 */ + volatile u_int32_t BB_per_chain_csd; /* 0x84 - 0x88 */ + volatile char pad__1[0x18]; /* 0x88 - 0xa0 */ + volatile u_int32_t BB_tx_crc; /* 0xa0 - 0xa4 */ + volatile u_int32_t BB_tstdac_constant; /* 0xa4 - 0xa8 */ + volatile u_int32_t BB_spur_report_b0; /* 0xa8 - 0xac */ + volatile char pad__2[0x4]; /* 0xac - 0xb0 */ + volatile u_int32_t BB_txiqcal_control_3; /* 0xb0 - 0xb4 */ + volatile char pad__3[0x8]; /* 0xb4 - 0xbc */ + /* Poseidon, Jupiter */ + volatile u_int32_t BB_green_tx_control_1; /* 0xbc - 0xc0 */ + volatile u_int32_t BB_iq_adc_meas_0_b0; /* 0xc0 - 0xc4 */ + volatile u_int32_t BB_iq_adc_meas_1_b0; /* 0xc4 - 0xc8 */ + volatile u_int32_t BB_iq_adc_meas_2_b0; /* 0xc8 - 0xcc */ + volatile u_int32_t BB_iq_adc_meas_3_b0; /* 0xcc - 0xd0 */ + volatile u_int32_t BB_tx_phase_ramp_b0; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_adc_gain_dc_corr_b0; /* 0xd4 - 0xd8 */ + volatile char pad__4[0x4]; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_rx_iq_corr_b0; /* 0xdc - 0xe0 */ + volatile char pad__5[0x4]; /* 0xe0 - 0xe4 */ + volatile u_int32_t BB_paprd_am2am_mask; /* 0xe4 - 0xe8 */ + volatile u_int32_t BB_paprd_am2pm_mask; /* 0xe8 - 0xec */ + volatile u_int32_t BB_paprd_ht40_mask; /* 0xec - 0xf0 */ + volatile u_int32_t BB_paprd_ctrl0_b0; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_paprd_ctrl1_b0; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_pa_gain123_b0; /* 0xf8 - 0xfc */ + volatile u_int32_t BB_pa_gain45_b0; /* 0xfc - 0x100 */ + volatile u_int32_t BB_paprd_pre_post_scale_0_b0; + /* 0x100 - 0x104 */ + volatile u_int32_t BB_paprd_pre_post_scale_1_b0; + /* 0x104 - 0x108 */ + volatile u_int32_t BB_paprd_pre_post_scale_2_b0; + /* 0x108 - 0x10c */ + volatile u_int32_t BB_paprd_pre_post_scale_3_b0; + /* 0x10c - 0x110 */ + volatile u_int32_t BB_paprd_pre_post_scale_4_b0; + /* 0x110 - 0x114 */ + volatile u_int32_t BB_paprd_pre_post_scale_5_b0; + /* 0x114 - 0x118 */ + volatile u_int32_t BB_paprd_pre_post_scale_6_b0; + /* 0x118 - 0x11c */ + volatile u_int32_t BB_paprd_pre_post_scale_7_b0; + /* 0x11c - 0x120 */ + volatile u_int32_t BB_paprd_mem_tab_b0[120]; /* 0x120 - 0x300 */ + volatile u_int32_t BB_chan_info_chan_tab_b0[60]; + /* 0x300 - 0x3f0 */ + /* Jupiter_20 */ + volatile u_int32_t BB_chn_tables_intf_addr; /* 0x3f0 - 0x3f4 */ + /* Jupiter_20 */ + volatile u_int32_t BB_chn_tables_intf_data; /* 0x3f4 - 0x3f8 */ +}; + +struct mrc_reg_map { + volatile u_int32_t BB_timing_control_3a; /* 0x0 - 0x4 */ + volatile u_int32_t BB_ldpc_cntl1; /* 0x4 - 0x8 */ + volatile u_int32_t BB_ldpc_cntl2; /* 0x8 - 0xc */ + volatile u_int32_t BB_pilot_spur_mask; /* 0xc - 0x10 */ + volatile u_int32_t BB_chan_spur_mask; /* 0x10 - 0x14 */ + volatile u_int32_t BB_short_gi_delta_slope; /* 0x14 - 0x18 */ + volatile u_int32_t BB_ml_cntl1; /* 0x18 - 0x1c */ + volatile u_int32_t BB_ml_cntl2; /* 0x1c - 0x20 */ + volatile u_int32_t BB_tstadc; /* 0x20 - 0x24 */ +}; + +struct bbb_reg_map { + volatile u_int32_t BB_bbb_rx_ctrl_1; /* 0x0 - 0x4 */ + volatile u_int32_t BB_bbb_rx_ctrl_2; /* 0x4 - 0x8 */ + volatile u_int32_t BB_bbb_rx_ctrl_3; /* 0x8 - 0xc */ + volatile u_int32_t BB_bbb_rx_ctrl_4; /* 0xc - 0x10 */ + volatile u_int32_t BB_bbb_rx_ctrl_5; /* 0x10 - 0x14 */ + volatile u_int32_t BB_bbb_rx_ctrl_6; /* 0x14 - 0x18 */ + volatile u_int32_t BB_force_clken_cck; /* 0x18 - 0x1c */ + /* Poseidon, Jupiter_10 */ + volatile u_int32_t BB_bb_reg_page_control; /* 0x1c - 0x20 */ +}; + +struct agc_reg_map { + volatile u_int32_t BB_settling_time; /* 0x0 - 0x4 */ + volatile u_int32_t BB_gain_force_max_gains_b0; /* 0x4 - 0x8 */ + volatile u_int32_t BB_gains_min_offsets; /* 0x8 - 0xc */ + volatile u_int32_t BB_desired_sigsize; /* 0xc - 0x10 */ + volatile u_int32_t BB_find_signal; /* 0x10 - 0x14 */ + volatile u_int32_t BB_agc; /* 0x14 - 0x18 */ + volatile u_int32_t BB_ext_atten_switch_ctl_b0; /* 0x18 - 0x1c */ + volatile u_int32_t BB_cca_b0; /* 0x1c - 0x20 */ + volatile u_int32_t BB_cca_ctrl_2_b0; /* 0x20 - 0x24 */ + volatile u_int32_t BB_restart; /* 0x24 - 0x28 */ + volatile u_int32_t BB_multichain_gain_ctrl; /* 0x28 - 0x2c */ + volatile u_int32_t BB_ext_chan_pwr_thr_1; /* 0x2c - 0x30 */ + volatile u_int32_t BB_ext_chan_detect_win; /* 0x30 - 0x34 */ + volatile u_int32_t BB_pwr_thr_20_40_det; /* 0x34 - 0x38 */ + volatile u_int32_t BB_rifs_srch; /* 0x38 - 0x3c */ + volatile u_int32_t BB_peak_det_ctrl_1; /* 0x3c - 0x40 */ + volatile u_int32_t BB_peak_det_ctrl_2; /* 0x40 - 0x44 */ + volatile u_int32_t BB_rx_gain_bounds_1; /* 0x44 - 0x48 */ + volatile u_int32_t BB_rx_gain_bounds_2; /* 0x48 - 0x4c */ + volatile u_int32_t BB_peak_det_cal_ctrl; /* 0x4c - 0x50 */ + volatile u_int32_t BB_agc_dig_dc_ctrl; /* 0x50 - 0x54 */ + volatile u_int32_t BB_bt_coex_1; /* 0x54 - 0x58 */ + /* Poseidon, Jupiter */ + volatile u_int32_t BB_bt_coex_2; /* 0x58 - 0x5c */ + /* Poseidon, Jupiter */ + volatile u_int32_t BB_bt_coex_3; /* 0x5c - 0x60 */ + /* Poseidon, Jupiter */ + volatile u_int32_t BB_bt_coex_4; /* 0x60 - 0x64 */ + /* Poseidon, Jupiter */ + volatile u_int32_t BB_bt_coex_5; /* 0x64 - 0x68 */ + /* Jupiter_20 */ + volatile u_int32_t BB_redpwr_ctrl_1; /* 0x68 - 0x6c */ + /* Jupiter_20 */ + volatile u_int32_t BB_redpwr_ctrl_2; /* 0x6c - 0x70 */ + volatile char pad__0[0x110]; /* 0x70 - 0x180 */ + volatile u_int32_t BB_rssi_b0; /* 0x180 - 0x184 */ + volatile u_int32_t BB_spur_est_cck_report_b0; /* 0x184 - 0x188 */ + volatile u_int32_t BB_agc_dig_dc_status_i_b0; /* 0x188 - 0x18c */ + volatile u_int32_t BB_agc_dig_dc_status_q_b0; /* 0x18c - 0x190 */ + /* Poseidon, Jupiter */ + volatile u_int32_t BB_dc_cal_status_b0; /* 0x190 - 0x194 */ + volatile char pad__1[0x2c]; /* 0x194 - 0x1c0 */ + volatile u_int32_t BB_bbb_sig_detect; /* 0x1c0 - 0x1c4 */ + volatile u_int32_t BB_bbb_dagc_ctrl; /* 0x1c4 - 0x1c8 */ + volatile u_int32_t BB_iqcorr_ctrl_cck; /* 0x1c8 - 0x1cc */ + volatile u_int32_t BB_cck_spur_mit; /* 0x1cc - 0x1d0 */ + /* Not Poseidon */ + volatile u_int32_t BB_mrc_cck_ctrl; /* 0x1d0 - 0x1d4 */ + /* Jupiter_20 */ + volatile u_int32_t BB_cck_blocker_det; /* 0x1d4 - 0x1d8 */ + volatile char pad__2[0x28]; /* 0x1d8 - 0x200 */ + volatile u_int32_t BB_rx_ocgain[128]; /* 0x200 - 0x400 */ +}; + +struct sm_reg_map { + volatile u_int32_t BB_D2_chip_id; /* 0x0 - 0x4 */ + volatile u_int32_t BB_gen_controls; /* 0x4 - 0x8 */ + volatile u_int32_t BB_modes_select; /* 0x8 - 0xc */ + volatile u_int32_t BB_active; /* 0xc - 0x10 */ + /* Poseidon, Jupiter_10 */ + volatile u_int32_t BB_bb_reg_page; /* 0x10 - 0x14 */ + volatile char pad__0[0xc]; /* 0x14 - 0x20 */ + volatile u_int32_t BB_vit_spur_mask_A; /* 0x20 - 0x24 */ + volatile u_int32_t BB_vit_spur_mask_B; /* 0x24 - 0x28 */ + volatile u_int32_t BB_spectral_scan; /* 0x28 - 0x2c */ + volatile u_int32_t BB_radar_bw_filter; /* 0x2c - 0x30 */ + volatile u_int32_t BB_search_start_delay; /* 0x30 - 0x34 */ + volatile u_int32_t BB_max_rx_length; /* 0x34 - 0x38 */ + volatile u_int32_t BB_frame_control; /* 0x38 - 0x3c */ + volatile u_int32_t BB_rfbus_request; /* 0x3c - 0x40 */ + volatile u_int32_t BB_rfbus_grant; /* 0x40 - 0x44 */ + volatile u_int32_t BB_rifs; /* 0x44 - 0x48 */ + /* Jupiter */ + volatile u_int32_t BB_spectral_scan_2; /* 0x48 - 0x4c */ + volatile char pad__1[0x4]; /* 0x4c - 0x50 */ + volatile u_int32_t BB_rx_clear_delay; /* 0x50 - 0x54 */ + volatile u_int32_t BB_analog_power_on_time; /* 0x54 - 0x58 */ + volatile u_int32_t BB_tx_timing_1; /* 0x58 - 0x5c */ + volatile u_int32_t BB_tx_timing_2; /* 0x5c - 0x60 */ + volatile u_int32_t BB_tx_timing_3; /* 0x60 - 0x64 */ + volatile u_int32_t BB_xpa_timing_control; /* 0x64 - 0x68 */ + volatile char pad__2[0x18]; /* 0x68 - 0x80 */ + volatile u_int32_t BB_misc_pa_control; /* 0x80 - 0x84 */ + volatile u_int32_t BB_switch_table_chn_b0; /* 0x84 - 0x88 */ + volatile u_int32_t BB_switch_table_com1; /* 0x88 - 0x8c */ + volatile u_int32_t BB_switch_table_com2; /* 0x8c - 0x90 */ + volatile char pad__3[0x10]; /* 0x90 - 0xa0 */ + volatile u_int32_t BB_multichain_enable; /* 0xa0 - 0xa4 */ + volatile char pad__4[0x1c]; /* 0xa4 - 0xc0 */ + volatile u_int32_t BB_cal_chain_mask; /* 0xc0 - 0xc4 */ + volatile u_int32_t BB_agc_control; /* 0xc4 - 0xc8 */ + volatile u_int32_t BB_iq_adc_cal_mode; /* 0xc8 - 0xcc */ + volatile u_int32_t BB_fcal_1; /* 0xcc - 0xd0 */ + volatile u_int32_t BB_fcal_2_b0; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_dft_tone_ctrl_b0; /* 0xd4 - 0xd8 */ + volatile u_int32_t BB_cl_cal_ctrl; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_cl_map_0_b0; /* 0xdc - 0xe0 */ + volatile u_int32_t BB_cl_map_1_b0; /* 0xe0 - 0xe4 */ + volatile u_int32_t BB_cl_map_2_b0; /* 0xe4 - 0xe8 */ + volatile u_int32_t BB_cl_map_3_b0; /* 0xe8 - 0xec */ + volatile u_int32_t BB_cl_map_pal_0_b0; /* 0xec - 0xf0 */ + volatile u_int32_t BB_cl_map_pal_1_b0; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_cl_map_pal_2_b0; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_cl_map_pal_3_b0; /* 0xf8 - 0xfc */ + volatile char pad__5[0x4]; /* 0xfc - 0x100 */ + volatile u_int32_t BB_cl_tab_b0[16]; /* 0x100 - 0x140 */ + volatile u_int32_t BB_synth_control; /* 0x140 - 0x144 */ + volatile u_int32_t BB_addac_clk_select; /* 0x144 - 0x148 */ + volatile u_int32_t BB_pll_cntl; /* 0x148 - 0x14c */ + volatile u_int32_t BB_analog_swap; /* 0x14c - 0x150 */ + volatile u_int32_t BB_addac_parallel_control; /* 0x150 - 0x154 */ + volatile char pad__6[0x4]; /* 0x154 - 0x158 */ + volatile u_int32_t BB_force_analog; /* 0x158 - 0x15c */ + volatile char pad__7[0x4]; /* 0x15c - 0x160 */ + volatile u_int32_t BB_test_controls; /* 0x160 - 0x164 */ + volatile u_int32_t BB_test_controls_status; /* 0x164 - 0x168 */ + volatile u_int32_t BB_tstdac; /* 0x168 - 0x16c */ + volatile u_int32_t BB_channel_status; /* 0x16c - 0x170 */ + volatile u_int32_t BB_chaninfo_ctrl; /* 0x170 - 0x174 */ + volatile u_int32_t BB_chan_info_noise_pwr; /* 0x174 - 0x178 */ + volatile u_int32_t BB_chan_info_gain_diff; /* 0x178 - 0x17c */ + volatile u_int32_t BB_chan_info_fine_timing; /* 0x17c - 0x180 */ + volatile u_int32_t BB_chan_info_gain_b0; /* 0x180 - 0x184 */ + volatile char pad__8[0xc]; /* 0x184 - 0x190 */ + volatile u_int32_t BB_scrambler_seed; /* 0x190 - 0x194 */ + volatile u_int32_t BB_bbb_tx_ctrl; /* 0x194 - 0x198 */ + volatile u_int32_t BB_bbb_txfir_0; /* 0x198 - 0x19c */ + volatile u_int32_t BB_bbb_txfir_1; /* 0x19c - 0x1a0 */ + volatile u_int32_t BB_bbb_txfir_2; /* 0x1a0 - 0x1a4 */ + volatile u_int32_t BB_heavy_clip_ctrl; /* 0x1a4 - 0x1a8 */ + volatile u_int32_t BB_heavy_clip_20; /* 0x1a8 - 0x1ac */ + volatile u_int32_t BB_heavy_clip_40; /* 0x1ac - 0x1b0 */ + volatile u_int32_t BB_illegal_tx_rate; /* 0x1b0 - 0x1b4 */ + volatile char pad__9[0xc]; /* 0x1b4 - 0x1c0 */ + volatile u_int32_t BB_powertx_rate1; /* 0x1c0 - 0x1c4 */ + volatile u_int32_t BB_powertx_rate2; /* 0x1c4 - 0x1c8 */ + volatile u_int32_t BB_powertx_rate3; /* 0x1c8 - 0x1cc */ + volatile u_int32_t BB_powertx_rate4; /* 0x1cc - 0x1d0 */ + volatile u_int32_t BB_powertx_rate5; /* 0x1d0 - 0x1d4 */ + volatile u_int32_t BB_powertx_rate6; /* 0x1d4 - 0x1d8 */ + volatile u_int32_t BB_powertx_rate7; /* 0x1d8 - 0x1dc */ + volatile u_int32_t BB_powertx_rate8; /* 0x1dc - 0x1e0 */ + volatile u_int32_t BB_powertx_rate9; /* 0x1e0 - 0x1e4 */ + volatile u_int32_t BB_powertx_rate10; /* 0x1e4 - 0x1e8 */ + volatile u_int32_t BB_powertx_rate11; /* 0x1e8 - 0x1ec */ + volatile u_int32_t BB_powertx_rate12; /* 0x1ec - 0x1f0 */ + volatile u_int32_t BB_powertx_max; /* 0x1f0 - 0x1f4 */ + volatile u_int32_t BB_powertx_sub; /* 0x1f4 - 0x1f8 */ + volatile u_int32_t BB_tpc_1; /* 0x1f8 - 0x1fc */ + volatile u_int32_t BB_tpc_2; /* 0x1fc - 0x200 */ + volatile u_int32_t BB_tpc_3; /* 0x200 - 0x204 */ + volatile u_int32_t BB_tpc_4_b0; /* 0x204 - 0x208 */ + volatile u_int32_t BB_tpc_5_b0; /* 0x208 - 0x20c */ + volatile u_int32_t BB_tpc_6_b0; /* 0x20c - 0x210 */ + volatile u_int32_t BB_tpc_7; /* 0x210 - 0x214 */ + volatile u_int32_t BB_tpc_8; /* 0x214 - 0x218 */ + volatile u_int32_t BB_tpc_9; /* 0x218 - 0x21c */ + volatile u_int32_t BB_tpc_10; /* 0x21c - 0x220 */ + volatile u_int32_t BB_tpc_11_b0; /* 0x220 - 0x224 */ + volatile u_int32_t BB_tpc_12; /* 0x224 - 0x228 */ + volatile u_int32_t BB_tpc_13; /* 0x228 - 0x22c */ + volatile u_int32_t BB_tpc_14; /* 0x22c - 0x230 */ + volatile u_int32_t BB_tpc_15; /* 0x230 - 0x234 */ + volatile u_int32_t BB_tpc_16; /* 0x234 - 0x238 */ + volatile u_int32_t BB_tpc_17; /* 0x238 - 0x23c */ + volatile u_int32_t BB_tpc_18; /* 0x23c - 0x240 */ + volatile u_int32_t BB_tpc_19; /* 0x240 - 0x244 */ + volatile u_int32_t BB_tpc_20; /* 0x244 - 0x248 */ + volatile u_int32_t BB_therm_adc_1; /* 0x248 - 0x24c */ + volatile u_int32_t BB_therm_adc_2; /* 0x24c - 0x250 */ + volatile u_int32_t BB_therm_adc_3; /* 0x250 - 0x254 */ + volatile u_int32_t BB_therm_adc_4; /* 0x254 - 0x258 */ + volatile u_int32_t BB_tx_forced_gain; /* 0x258 - 0x25c */ + volatile char pad__10[0x24]; /* 0x25c - 0x280 */ + volatile u_int32_t BB_pdadc_tab_b0[32]; /* 0x280 - 0x300 */ + volatile u_int32_t BB_tx_gain_tab_1; /* 0x300 - 0x304 */ + volatile u_int32_t BB_tx_gain_tab_2; /* 0x304 - 0x308 */ + volatile u_int32_t BB_tx_gain_tab_3; /* 0x308 - 0x30c */ + volatile u_int32_t BB_tx_gain_tab_4; /* 0x30c - 0x310 */ + volatile u_int32_t BB_tx_gain_tab_5; /* 0x310 - 0x314 */ + volatile u_int32_t BB_tx_gain_tab_6; /* 0x314 - 0x318 */ + volatile u_int32_t BB_tx_gain_tab_7; /* 0x318 - 0x31c */ + volatile u_int32_t BB_tx_gain_tab_8; /* 0x31c - 0x320 */ + volatile u_int32_t BB_tx_gain_tab_9; /* 0x320 - 0x324 */ + volatile u_int32_t BB_tx_gain_tab_10; /* 0x324 - 0x328 */ + volatile u_int32_t BB_tx_gain_tab_11; /* 0x328 - 0x32c */ + volatile u_int32_t BB_tx_gain_tab_12; /* 0x32c - 0x330 */ + volatile u_int32_t BB_tx_gain_tab_13; /* 0x330 - 0x334 */ + volatile u_int32_t BB_tx_gain_tab_14; /* 0x334 - 0x338 */ + volatile u_int32_t BB_tx_gain_tab_15; /* 0x338 - 0x33c */ + volatile u_int32_t BB_tx_gain_tab_16; /* 0x33c - 0x340 */ + volatile u_int32_t BB_tx_gain_tab_17; /* 0x340 - 0x344 */ + volatile u_int32_t BB_tx_gain_tab_18; /* 0x344 - 0x348 */ + volatile u_int32_t BB_tx_gain_tab_19; /* 0x348 - 0x34c */ + volatile u_int32_t BB_tx_gain_tab_20; /* 0x34c - 0x350 */ + volatile u_int32_t BB_tx_gain_tab_21; /* 0x350 - 0x354 */ + volatile u_int32_t BB_tx_gain_tab_22; /* 0x354 - 0x358 */ + volatile u_int32_t BB_tx_gain_tab_23; /* 0x358 - 0x35c */ + volatile u_int32_t BB_tx_gain_tab_24; /* 0x35c - 0x360 */ + volatile u_int32_t BB_tx_gain_tab_25; /* 0x360 - 0x364 */ + volatile u_int32_t BB_tx_gain_tab_26; /* 0x364 - 0x368 */ + volatile u_int32_t BB_tx_gain_tab_27; /* 0x368 - 0x36c */ + volatile u_int32_t BB_tx_gain_tab_28; /* 0x36c - 0x370 */ + volatile u_int32_t BB_tx_gain_tab_29; /* 0x370 - 0x374 */ + volatile u_int32_t BB_tx_gain_tab_30; /* 0x374 - 0x378 */ + volatile u_int32_t BB_tx_gain_tab_31; /* 0x378 - 0x37c */ + volatile u_int32_t BB_tx_gain_tab_32; /* 0x37c - 0x380 */ + union { + struct { + volatile u_int32_t BB_tx_gain_tab_pal_1; /* 0x380 - 0x384 */ + volatile u_int32_t BB_tx_gain_tab_pal_2; /* 0x384 - 0x388 */ + volatile u_int32_t BB_tx_gain_tab_pal_3; /* 0x388 - 0x38c */ + volatile u_int32_t BB_tx_gain_tab_pal_4; /* 0x38c - 0x390 */ + volatile u_int32_t BB_tx_gain_tab_pal_5; /* 0x390 - 0x394 */ + volatile u_int32_t BB_tx_gain_tab_pal_6; /* 0x394 - 0x398 */ + volatile u_int32_t BB_tx_gain_tab_pal_7; /* 0x398 - 0x39c */ + volatile u_int32_t BB_tx_gain_tab_pal_8; /* 0x39c - 0x3a0 */ + volatile u_int32_t BB_tx_gain_tab_pal_9; /* 0x3a0 - 0x3a4 */ + volatile u_int32_t BB_tx_gain_tab_pal_10; /* 0x3a4 - 0x3a8 */ + volatile u_int32_t BB_tx_gain_tab_pal_11; /* 0x3a8 - 0x3ac */ + volatile u_int32_t BB_tx_gain_tab_pal_12; /* 0x3ac - 0x3b0 */ + volatile u_int32_t BB_tx_gain_tab_pal_13; /* 0x3b0 - 0x3b4 */ + volatile u_int32_t BB_tx_gain_tab_pal_14; /* 0x3b4 - 0x3b8 */ + volatile u_int32_t BB_tx_gain_tab_pal_15; /* 0x3b8 - 0x3bc */ + volatile u_int32_t BB_tx_gain_tab_pal_16; /* 0x3bc - 0x3c0 */ + volatile u_int32_t BB_tx_gain_tab_pal_17; /* 0x3c0 - 0x3c4 */ + volatile u_int32_t BB_tx_gain_tab_pal_18; /* 0x3c4 - 0x3c8 */ + volatile u_int32_t BB_tx_gain_tab_pal_19; /* 0x3c8 - 0x3cc */ + volatile u_int32_t BB_tx_gain_tab_pal_20; /* 0x3cc - 0x3d0 */ + volatile u_int32_t BB_tx_gain_tab_pal_21; /* 0x3d0 - 0x3d4 */ + volatile u_int32_t BB_tx_gain_tab_pal_22; /* 0x3d4 - 0x3d8 */ + volatile u_int32_t BB_tx_gain_tab_pal_23; /* 0x3d8 - 0x3dc */ + volatile u_int32_t BB_tx_gain_tab_pal_24; /* 0x3dc - 0x3e0 */ + volatile u_int32_t BB_tx_gain_tab_pal_25; /* 0x3e0 - 0x3e4 */ + volatile u_int32_t BB_tx_gain_tab_pal_26; /* 0x3e4 - 0x3e8 */ + volatile u_int32_t BB_tx_gain_tab_pal_27; /* 0x3e8 - 0x3ec */ + volatile u_int32_t BB_tx_gain_tab_pal_28; /* 0x3ec - 0x3f0 */ + volatile u_int32_t BB_tx_gain_tab_pal_29; /* 0x3f0 - 0x3f4 */ + volatile u_int32_t BB_tx_gain_tab_pal_30; /* 0x3f4 - 0x3f8 */ + volatile u_int32_t BB_tx_gain_tab_pal_31; /* 0x3f8 - 0x3fc */ + volatile u_int32_t BB_tx_gain_tab_pal_32; /* 0x3fc - 0x400 */ + volatile u_int32_t BB_caltx_gain_set_0; /* 0x400 - 0x404 */ + volatile u_int32_t BB_caltx_gain_set_2; /* 0x404 - 0x408 */ + volatile u_int32_t BB_caltx_gain_set_4; /* 0x408 - 0x40c */ + volatile u_int32_t BB_caltx_gain_set_6; /* 0x40c - 0x410 */ + volatile u_int32_t BB_caltx_gain_set_8; /* 0x410 - 0x414 */ + volatile u_int32_t BB_caltx_gain_set_10; /* 0x414 - 0x418 */ + volatile u_int32_t BB_caltx_gain_set_12; /* 0x418 - 0x41c */ + volatile u_int32_t BB_caltx_gain_set_14; /* 0x41c - 0x420 */ + volatile u_int32_t BB_caltx_gain_set_16; /* 0x420 - 0x424 */ + volatile u_int32_t BB_caltx_gain_set_18; /* 0x424 - 0x428 */ + volatile u_int32_t BB_caltx_gain_set_20; /* 0x428 - 0x42c */ + volatile u_int32_t BB_caltx_gain_set_22; /* 0x42c - 0x430 */ + volatile u_int32_t BB_caltx_gain_set_24; /* 0x430 - 0x434 */ + volatile u_int32_t BB_caltx_gain_set_26; /* 0x434 - 0x438 */ + volatile u_int32_t BB_caltx_gain_set_28; /* 0x438 - 0x43c */ + volatile u_int32_t BB_caltx_gain_set_30; /* 0x43c - 0x440 */ + volatile u_int32_t BB_txiqcal_start; /* 0x440 - 0x444 */ + volatile u_int32_t BB_txiqcal_control_0; /* 0x444 - 0x448 */ + volatile u_int32_t BB_txiqcal_control_1; /* 0x448 - 0x44c */ + volatile u_int32_t BB_txiqcal_control_2; /* 0x44c - 0x450 */ + volatile u_int32_t BB_txiq_corr_coeff_01_b0; /* 0x450 - 0x454 */ + volatile u_int32_t BB_txiq_corr_coeff_23_b0; /* 0x454 - 0x458 */ + volatile u_int32_t BB_txiq_corr_coeff_45_b0; /* 0x458 - 0x45c */ + volatile u_int32_t BB_txiq_corr_coeff_67_b0; /* 0x45c - 0x460 */ + volatile u_int32_t BB_txiq_corr_coeff_89_b0; /* 0x460 - 0x464 */ + volatile u_int32_t BB_txiq_corr_coeff_ab_b0; /* 0x464 - 0x468 */ + volatile u_int32_t BB_txiq_corr_coeff_cd_b0; /* 0x468 - 0x46c */ + volatile u_int32_t BB_txiq_corr_coeff_ef_b0; /* 0x46c - 0x470 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_0; /* 0x470 - 0x474 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_4; /* 0x474 - 0x478 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_8; /* 0x478 - 0x47c */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_12; /* 0x47c - 0x480 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_16; /* 0x480 - 0x484 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_20; /* 0x484 - 0x488 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_24; /* 0x488 - 0x48c */ + volatile u_int32_t BB_txiqcal_status_b0; /* 0x48c - 0x490 */ + volatile u_int32_t BB_paprd_trainer_cntl1; /* 0x490 - 0x494 */ + volatile u_int32_t BB_paprd_trainer_cntl2; /* 0x494 - 0x498 */ + volatile u_int32_t BB_paprd_trainer_cntl3; /* 0x498 - 0x49c */ + volatile u_int32_t BB_paprd_trainer_cntl4; /* 0x49c - 0x4a0 */ + volatile u_int32_t BB_paprd_trainer_stat1; /* 0x4a0 - 0x4a4 */ + volatile u_int32_t BB_paprd_trainer_stat2; /* 0x4a4 - 0x4a8 */ + volatile u_int32_t BB_paprd_trainer_stat3; /* 0x4a8 - 0x4ac */ + volatile char pad__11[0x114]; /* 0x4ac - 0x5c0 */ + } Osprey; + struct { + volatile u_int32_t BB_caltx_gain_set_0; /* 0x380 - 0x384 */ + volatile u_int32_t BB_caltx_gain_set_2; /* 0x384 - 0x388 */ + volatile u_int32_t BB_caltx_gain_set_4; /* 0x388 - 0x38c */ + volatile u_int32_t BB_caltx_gain_set_6; /* 0x38c - 0x390 */ + volatile u_int32_t BB_caltx_gain_set_8; /* 0x390 - 0x394 */ + volatile u_int32_t BB_caltx_gain_set_10; /* 0x394 - 0x398 */ + volatile u_int32_t BB_caltx_gain_set_12; /* 0x398 - 0x39c */ + volatile u_int32_t BB_caltx_gain_set_14; /* 0x39c - 0x3a0 */ + volatile u_int32_t BB_caltx_gain_set_16; /* 0x3a0 - 0x3a4 */ + volatile u_int32_t BB_caltx_gain_set_18; /* 0x3a4 - 0x3a8 */ + volatile u_int32_t BB_caltx_gain_set_20; /* 0x3a8 - 0x3ac */ + volatile u_int32_t BB_caltx_gain_set_22; /* 0x3ac - 0x3b0 */ + volatile u_int32_t BB_caltx_gain_set_24; /* 0x3b0 - 0x3b4 */ + volatile u_int32_t BB_caltx_gain_set_26; /* 0x3b4 - 0x3b8 */ + volatile u_int32_t BB_caltx_gain_set_28; /* 0x3b8 - 0x3bc */ + volatile u_int32_t BB_caltx_gain_set_30; /* 0x3bc - 0x3c0 */ + volatile char pad__11[0x4]; /* 0x3c0 - 0x3c4 */ + volatile u_int32_t BB_txiqcal_control_0; /* 0x3c4 - 0x3c8 */ + volatile u_int32_t BB_txiqcal_control_1; /* 0x3c8 - 0x3cc */ + volatile u_int32_t BB_txiqcal_control_2; /* 0x3cc - 0x3d0 */ + volatile u_int32_t BB_txiq_corr_coeff_01_b0; /* 0x3d0 - 0x3d4 */ + volatile u_int32_t BB_txiq_corr_coeff_23_b0; /* 0x3d4 - 0x3d8 */ + volatile u_int32_t BB_txiq_corr_coeff_45_b0; /* 0x3d8 - 0x3dc */ + volatile u_int32_t BB_txiq_corr_coeff_67_b0; /* 0x3dc - 0x3e0 */ + volatile u_int32_t BB_txiq_corr_coeff_89_b0; /* 0x3e0 - 0x3e4 */ + volatile u_int32_t BB_txiq_corr_coeff_ab_b0; /* 0x3e4 - 0x3e8 */ + volatile u_int32_t BB_txiq_corr_coeff_cd_b0; /* 0x3e8 - 0x3ec */ + volatile u_int32_t BB_txiq_corr_coeff_ef_b0; /* 0x3ec - 0x3f0 */ + volatile u_int32_t BB_txiqcal_status_b0; /* 0x3f0 - 0x3f4 */ + volatile char pad__12[0x16c]; /* 0x3f4 - 0x560 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_0; /* 0x560 - 0x564 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_4; /* 0x564 - 0x568 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_8; /* 0x568 - 0x56c */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_12; /* 0x56c - 0x570 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_16; /* 0x570 - 0x574 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_20; /* 0x574 - 0x578 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_24; /* 0x578 - 0x57c */ + volatile char pad__13[0x4]; /* 0x57c - 0x580 */ + volatile u_int32_t BB_paprd_trainer_cntl1; /* 0x580 - 0x584 */ + volatile u_int32_t BB_paprd_trainer_cntl2; /* 0x584 - 0x588 */ + volatile u_int32_t BB_paprd_trainer_cntl3; /* 0x588 - 0x58c */ + volatile u_int32_t BB_paprd_trainer_cntl4; /* 0x58c - 0x590 */ + volatile u_int32_t BB_paprd_trainer_stat1; /* 0x590 - 0x594 */ + volatile u_int32_t BB_paprd_trainer_stat2; /* 0x594 - 0x598 */ + volatile u_int32_t BB_paprd_trainer_stat3; /* 0x598 - 0x59c */ + volatile char pad__14[0x24]; /* 0x59c - 0x5c0 */ + } Poseidon; + struct { + volatile char pad__11[0x80]; /* 0x380 - 0x400 */ + /* 0x400 - 0x4b0 same as Osprey - start */ + volatile u_int32_t BB_caltx_gain_set_0; /* 0x400 - 0x404 */ + volatile u_int32_t BB_caltx_gain_set_2; /* 0x404 - 0x408 */ + volatile u_int32_t BB_caltx_gain_set_4; /* 0x408 - 0x40c */ + volatile u_int32_t BB_caltx_gain_set_6; /* 0x40c - 0x410 */ + volatile u_int32_t BB_caltx_gain_set_8; /* 0x410 - 0x414 */ + volatile u_int32_t BB_caltx_gain_set_10; /* 0x414 - 0x418 */ + volatile u_int32_t BB_caltx_gain_set_12; /* 0x418 - 0x41c */ + volatile u_int32_t BB_caltx_gain_set_14; /* 0x41c - 0x420 */ + volatile u_int32_t BB_caltx_gain_set_16; /* 0x420 - 0x424 */ + volatile u_int32_t BB_caltx_gain_set_18; /* 0x424 - 0x428 */ + volatile u_int32_t BB_caltx_gain_set_20; /* 0x428 - 0x42c */ + volatile u_int32_t BB_caltx_gain_set_22; /* 0x42c - 0x430 */ + volatile u_int32_t BB_caltx_gain_set_24; /* 0x430 - 0x434 */ + volatile u_int32_t BB_caltx_gain_set_26; /* 0x434 - 0x438 */ + volatile u_int32_t BB_caltx_gain_set_28; /* 0x438 - 0x43c */ + volatile u_int32_t BB_caltx_gain_set_30; /* 0x43c - 0x440 */ + volatile char pad__12[0x4]; /* 0x440 - 0x444 */ + volatile u_int32_t BB_txiqcal_control_0; /* 0x444 - 0x448 */ + volatile u_int32_t BB_txiqcal_control_1; /* 0x448 - 0x44c */ + volatile u_int32_t BB_txiqcal_control_2; /* 0x44c - 0x450 */ + volatile u_int32_t BB_txiq_corr_coeff_01_b0; /* 0x450 - 0x454 */ + volatile u_int32_t BB_txiq_corr_coeff_23_b0; /* 0x454 - 0x458 */ + volatile u_int32_t BB_txiq_corr_coeff_45_b0; /* 0x458 - 0x45c */ + volatile u_int32_t BB_txiq_corr_coeff_67_b0; /* 0x45c - 0x460 */ + volatile u_int32_t BB_txiq_corr_coeff_89_b0; /* 0x460 - 0x464 */ + volatile u_int32_t BB_txiq_corr_coeff_ab_b0; /* 0x464 - 0x468 */ + volatile u_int32_t BB_txiq_corr_coeff_cd_b0; /* 0x468 - 0x46c */ + volatile u_int32_t BB_txiq_corr_coeff_ef_b0; /* 0x46c - 0x470 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_0; /* 0x470 - 0x474 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_4; /* 0x474 - 0x478 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_8; /* 0x478 - 0x47c */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_12; /* 0x47c - 0x480 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_16; /* 0x480 - 0x484 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_20; /* 0x484 - 0x488 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_24; /* 0x488 - 0x48c */ + volatile u_int32_t BB_txiqcal_status_b0; /* 0x48c - 0x490 */ + volatile u_int32_t BB_paprd_trainer_cntl1; /* 0x490 - 0x494 */ + volatile u_int32_t BB_paprd_trainer_cntl2; /* 0x494 - 0x498 */ + volatile u_int32_t BB_paprd_trainer_cntl3; /* 0x498 - 0x49c */ + volatile u_int32_t BB_paprd_trainer_cntl4; /* 0x49c - 0x4a0 */ + volatile u_int32_t BB_paprd_trainer_stat1; /* 0x4a0 - 0x4a4 */ + volatile u_int32_t BB_paprd_trainer_stat2; /* 0x4a4 - 0x4a8 */ + volatile u_int32_t BB_paprd_trainer_stat3; /* 0x4a8 - 0x4ac */ + volatile char pad__13[0x4]; /* 0x4ac - 0x4b0 */ + /* 0x400 - 0x4b0 same as Osprey - end */ + volatile u_int32_t BB_aic_ctrl_0_b0; /* 0x4b0 - 0x4b4 */ + volatile u_int32_t BB_aic_ctrl_1_b0; /* 0x4b4 - 0x4b8 */ + volatile u_int32_t BB_aic_ctrl_2_b0; /* 0x4b8 - 0x4bc */ + volatile u_int32_t BB_aic_ctrl_3_b0; /* 0x4bc - 0x4c0 */ + volatile u_int32_t BB_aic_stat_0_b0; /* 0x4c0 - 0x4c4 */ + volatile u_int32_t BB_aic_stat_1_b0; /* 0x4c4 - 0x4c8 */ + volatile char pad__14[0xf8]; /* 0x4c8 - 0x5c0 */ + } Jupiter_10; + struct { + volatile u_int32_t BB_rtt_ctrl; /* 0x380 - 0x384 */ + volatile u_int32_t BB_rtt_table_sw_intf_b0; /* 0x384 - 0x388 */ + volatile u_int32_t BB_rtt_table_sw_intf_1_b0; /* 0x388 - 0x38c */ + volatile char pad__11[0x74]; /* 0x38c - 0x400 */ + /* 0x400 - 0x4b0 same as Osprey - start */ + volatile u_int32_t BB_caltx_gain_set_0; /* 0x400 - 0x404 */ + volatile u_int32_t BB_caltx_gain_set_2; /* 0x404 - 0x408 */ + volatile u_int32_t BB_caltx_gain_set_4; /* 0x408 - 0x40c */ + volatile u_int32_t BB_caltx_gain_set_6; /* 0x40c - 0x410 */ + volatile u_int32_t BB_caltx_gain_set_8; /* 0x410 - 0x414 */ + volatile u_int32_t BB_caltx_gain_set_10; /* 0x414 - 0x418 */ + volatile u_int32_t BB_caltx_gain_set_12; /* 0x418 - 0x41c */ + volatile u_int32_t BB_caltx_gain_set_14; /* 0x41c - 0x420 */ + volatile u_int32_t BB_caltx_gain_set_16; /* 0x420 - 0x424 */ + volatile u_int32_t BB_caltx_gain_set_18; /* 0x424 - 0x428 */ + volatile u_int32_t BB_caltx_gain_set_20; /* 0x428 - 0x42c */ + volatile u_int32_t BB_caltx_gain_set_22; /* 0x42c - 0x430 */ + volatile u_int32_t BB_caltx_gain_set_24; /* 0x430 - 0x434 */ + volatile u_int32_t BB_caltx_gain_set_26; /* 0x434 - 0x438 */ + volatile u_int32_t BB_caltx_gain_set_28; /* 0x438 - 0x43c */ + volatile u_int32_t BB_caltx_gain_set_30; /* 0x43c - 0x440 */ + volatile char pad__12[0x4]; /* 0x440 - 0x444 */ + volatile u_int32_t BB_txiqcal_control_0; /* 0x444 - 0x448 */ + volatile u_int32_t BB_txiqcal_control_1; /* 0x448 - 0x44c */ + volatile u_int32_t BB_txiqcal_control_2; /* 0x44c - 0x450 */ + volatile u_int32_t BB_txiq_corr_coeff_01_b0; /* 0x450 - 0x454 */ + volatile u_int32_t BB_txiq_corr_coeff_23_b0; /* 0x454 - 0x458 */ + volatile u_int32_t BB_txiq_corr_coeff_45_b0; /* 0x458 - 0x45c */ + volatile u_int32_t BB_txiq_corr_coeff_67_b0; /* 0x45c - 0x460 */ + volatile u_int32_t BB_txiq_corr_coeff_89_b0; /* 0x460 - 0x464 */ + volatile u_int32_t BB_txiq_corr_coeff_ab_b0; /* 0x464 - 0x468 */ + volatile u_int32_t BB_txiq_corr_coeff_cd_b0; /* 0x468 - 0x46c */ + volatile u_int32_t BB_txiq_corr_coeff_ef_b0; /* 0x46c - 0x470 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_0; /* 0x470 - 0x474 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_4; /* 0x474 - 0x478 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_8; /* 0x478 - 0x47c */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_12; /* 0x47c - 0x480 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_16; /* 0x480 - 0x484 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_20; /* 0x484 - 0x488 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_24; /* 0x488 - 0x48c */ + volatile u_int32_t BB_txiqcal_status_b0; /* 0x48c - 0x490 */ + volatile u_int32_t BB_paprd_trainer_cntl1; /* 0x490 - 0x494 */ + volatile u_int32_t BB_paprd_trainer_cntl2; /* 0x494 - 0x498 */ + volatile u_int32_t BB_paprd_trainer_cntl3; /* 0x498 - 0x49c */ + volatile u_int32_t BB_paprd_trainer_cntl4; /* 0x49c - 0x4a0 */ + volatile u_int32_t BB_paprd_trainer_stat1; /* 0x4a0 - 0x4a4 */ + volatile u_int32_t BB_paprd_trainer_stat2; /* 0x4a4 - 0x4a8 */ + volatile u_int32_t BB_paprd_trainer_stat3; /* 0x4a8 - 0x4ac */ + volatile char pad__13[0x4]; /* 0x4ac - 0x4b0 */ + /* 0x400 - 0x4b0 same as Osprey - end */ + volatile u_int32_t BB_aic_ctrl_0_b0; /* 0x4b0 - 0x4b4 */ + volatile u_int32_t BB_aic_ctrl_1_b0; /* 0x4b4 - 0x4b8 */ + volatile u_int32_t BB_aic_ctrl_2_b0; /* 0x4b8 - 0x4bc */ + volatile u_int32_t BB_aic_ctrl_3_b0; /* 0x4bc - 0x4c0 */ + volatile u_int32_t BB_aic_ctrl_4_b0; /* 0x4c0 - 0x4c4 */ + volatile u_int32_t BB_aic_stat_0_b0; /* 0x4c4 - 0x4c8 */ + volatile u_int32_t BB_aic_stat_1_b0; /* 0x4c8 - 0x4cc */ + volatile u_int32_t BB_aic_stat_2_b0; /* 0x4cc - 0x4d0 */ + volatile char pad__14[0xf0]; /* 0x4d0 - 0x5c0 */ + } Jupiter_20; + } overlay_0xa580; + volatile u_int32_t BB_panic_watchdog_status; /* 0x5c0 - 0x5c4 */ + volatile u_int32_t BB_panic_watchdog_ctrl_1; /* 0x5c4 - 0x5c8 */ + volatile u_int32_t BB_panic_watchdog_ctrl_2; /* 0x5c8 - 0x5cc */ + volatile u_int32_t BB_bluetooth_cntl; /* 0x5cc - 0x5d0 */ + volatile u_int32_t BB_phyonly_warm_reset; /* 0x5d0 - 0x5d4 */ + volatile u_int32_t BB_phyonly_control; /* 0x5d4 - 0x5d8 */ + volatile char pad__12[0x4]; /* 0x5d8 - 0x5dc */ + volatile u_int32_t BB_eco_ctrl; /* 0x5dc - 0x5e0 */ + volatile char pad__13[0x10]; /* 0x5e0 - 0x5f0 */ + /* Jupiter */ + volatile u_int32_t BB_tables_intf_addr_b0; /* 0x5f0 - 0x5f4 */ + /* Jupiter */ + volatile u_int32_t BB_tables_intf_data_b0; /* 0x5f4 - 0x5f8 */ +}; + +struct chn1_reg_map { + volatile u_int32_t BB_dummy_DONOTACCESS1; /* 0x0 - 0x4 */ + volatile char pad__0[0x2c]; /* 0x4 - 0x30 */ + volatile u_int32_t BB_ext_chan_pwr_thr_2_b1; /* 0x30 - 0x34 */ + volatile char pad__1[0x74]; /* 0x34 - 0xa8 */ + volatile u_int32_t BB_spur_report_b1; /* 0xa8 - 0xac */ + volatile char pad__2[0x14]; /* 0xac - 0xc0 */ + volatile u_int32_t BB_iq_adc_meas_0_b1; /* 0xc0 - 0xc4 */ + volatile u_int32_t BB_iq_adc_meas_1_b1; /* 0xc4 - 0xc8 */ + volatile u_int32_t BB_iq_adc_meas_2_b1; /* 0xc8 - 0xcc */ + volatile u_int32_t BB_iq_adc_meas_3_b1; /* 0xcc - 0xd0 */ + volatile u_int32_t BB_tx_phase_ramp_b1; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_adc_gain_dc_corr_b1; /* 0xd4 - 0xd8 */ + volatile char pad__3[0x4]; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_rx_iq_corr_b1; /* 0xdc - 0xe0 */ + volatile char pad__4[0x10]; /* 0xe0 - 0xf0 */ + volatile u_int32_t BB_paprd_ctrl0_b1; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_paprd_ctrl1_b1; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_pa_gain123_b1; /* 0xf8 - 0xfc */ + volatile u_int32_t BB_pa_gain45_b1; /* 0xfc - 0x100 */ + volatile u_int32_t BB_paprd_pre_post_scale_0_b1; + /* 0x100 - 0x104 */ + volatile u_int32_t BB_paprd_pre_post_scale_1_b1; + /* 0x104 - 0x108 */ + volatile u_int32_t BB_paprd_pre_post_scale_2_b1; + /* 0x108 - 0x10c */ + volatile u_int32_t BB_paprd_pre_post_scale_3_b1; + /* 0x10c - 0x110 */ + volatile u_int32_t BB_paprd_pre_post_scale_4_b1; + /* 0x110 - 0x114 */ + volatile u_int32_t BB_paprd_pre_post_scale_5_b1; + /* 0x114 - 0x118 */ + volatile u_int32_t BB_paprd_pre_post_scale_6_b1; + /* 0x118 - 0x11c */ + volatile u_int32_t BB_paprd_pre_post_scale_7_b1; + /* 0x11c - 0x120 */ + volatile u_int32_t BB_paprd_mem_tab_b1[120]; /* 0x120 - 0x300 */ + volatile u_int32_t BB_chan_info_chan_tab_b1[60]; + /* 0x300 - 0x3f0 */ + /* Jupiter_20 */ + volatile u_int32_t BB_chn1_tables_intf_addr; /* 0x3f0 - 0x3f4 */ + /* Jupiter_20 */ + volatile u_int32_t BB_chn1_tables_intf_data; /* 0x3f4 - 0x3f8 */ +}; + +struct chn_ext_reg_map { + volatile u_int32_t BB_paprd_pre_post_scale_0_1_b0; + /* 0x0 - 0x4 */ + volatile u_int32_t BB_paprd_pre_post_scale_1_1_b0; + /* 0x4 - 0x8 */ + volatile u_int32_t BB_paprd_pre_post_scale_2_1_b0; + /* 0x8 - 0xc */ + volatile u_int32_t BB_paprd_pre_post_scale_3_1_b0; + /* 0xc - 0x10 */ + volatile u_int32_t BB_paprd_pre_post_scale_4_1_b0; + /* 0x10 - 0x14 */ + volatile u_int32_t BB_paprd_pre_post_scale_5_1_b0; + /* 0x14 - 0x18 */ + volatile u_int32_t BB_paprd_pre_post_scale_6_1_b0; + /* 0x18 - 0x1c */ + volatile u_int32_t BB_paprd_pre_post_scale_7_1_b0; + /* 0x1c - 0x20 */ + volatile u_int32_t BB_paprd_pre_post_scale_0_2_b0; + /* 0x20 - 0x24 */ + volatile u_int32_t BB_paprd_pre_post_scale_1_2_b0; + /* 0x24 - 0x28 */ + volatile u_int32_t BB_paprd_pre_post_scale_2_2_b0; + /* 0x28 - 0x2c */ + volatile u_int32_t BB_paprd_pre_post_scale_3_2_b0; + /* 0x2c - 0x30 */ + volatile u_int32_t BB_paprd_pre_post_scale_4_2_b0; + /* 0x30 - 0x34 */ + volatile u_int32_t BB_paprd_pre_post_scale_5_2_b0; + /* 0x34 - 0x38 */ + volatile u_int32_t BB_paprd_pre_post_scale_6_2_b0; + /* 0x38 - 0x3c */ + volatile u_int32_t BB_paprd_pre_post_scale_7_2_b0; + /* 0x3c - 0x40 */ + volatile u_int32_t BB_paprd_pre_post_scale_0_3_b0; + /* 0x40 - 0x44 */ + volatile u_int32_t BB_paprd_pre_post_scale_1_3_b0; + /* 0x44 - 0x48 */ + volatile u_int32_t BB_paprd_pre_post_scale_2_3_b0; + /* 0x48 - 0x4c */ + volatile u_int32_t BB_paprd_pre_post_scale_3_3_b0; + /* 0x4c - 0x50 */ + volatile u_int32_t BB_paprd_pre_post_scale_4_3_b0; + /* 0x50 - 0x54 */ + volatile u_int32_t BB_paprd_pre_post_scale_5_3_b0; + /* 0x54 - 0x58 */ + volatile u_int32_t BB_paprd_pre_post_scale_6_3_b0; + /* 0x58 - 0x5c */ + volatile u_int32_t BB_paprd_pre_post_scale_7_3_b0; + /* 0x5c - 0x60 */ + volatile u_int32_t BB_paprd_pre_post_scale_0_4_b0; + /* 0x60 - 0x64 */ + volatile u_int32_t BB_paprd_pre_post_scale_1_4_b0; + /* 0x64 - 0x68 */ + volatile u_int32_t BB_paprd_pre_post_scale_2_4_b0; + /* 0x68 - 0x6c */ + volatile u_int32_t BB_paprd_pre_post_scale_3_4_b0; + /* 0x6c - 0x70 */ + volatile u_int32_t BB_paprd_pre_post_scale_4_4_b0; + /* 0x70 - 0x74 */ + volatile u_int32_t BB_paprd_pre_post_scale_5_4_b0; + /* 0x74 - 0x78 */ + volatile u_int32_t BB_paprd_pre_post_scale_6_4_b0; + /* 0x78 - 0x7c */ + volatile u_int32_t BB_paprd_pre_post_scale_7_4_b0; + /* 0x7c - 0x80 */ + volatile u_int32_t BB_paprd_power_at_am2am_cal_b0; + /* 0x80 - 0x84 */ + volatile u_int32_t BB_paprd_valid_obdb_b0; /* 0x84 - 0x88 */ + volatile char pad__0[0x374]; /* 0x88 - 0x3fc */ + volatile u_int32_t BB_chn_ext_dummy_2; /* 0x3fc - 0x400 */ +}; + +struct sm_ext_reg_map { + volatile u_int32_t BB_sm_ext_dummy1; /* 0x0 - 0x4 */ + volatile char pad__0[0x2fc]; /* 0x4 - 0x300 */ + volatile u_int32_t BB_green_tx_gain_tab_1; /* 0x300 - 0x304 */ + volatile u_int32_t BB_green_tx_gain_tab_2; /* 0x304 - 0x308 */ + volatile u_int32_t BB_green_tx_gain_tab_3; /* 0x308 - 0x30c */ + volatile u_int32_t BB_green_tx_gain_tab_4; /* 0x30c - 0x310 */ + volatile u_int32_t BB_green_tx_gain_tab_5; /* 0x310 - 0x314 */ + volatile u_int32_t BB_green_tx_gain_tab_6; /* 0x314 - 0x318 */ + volatile u_int32_t BB_green_tx_gain_tab_7; /* 0x318 - 0x31c */ + volatile u_int32_t BB_green_tx_gain_tab_8; /* 0x31c - 0x320 */ + volatile u_int32_t BB_green_tx_gain_tab_9; /* 0x320 - 0x324 */ + volatile u_int32_t BB_green_tx_gain_tab_10; /* 0x324 - 0x328 */ + volatile u_int32_t BB_green_tx_gain_tab_11; /* 0x328 - 0x32c */ + volatile u_int32_t BB_green_tx_gain_tab_12; /* 0x32c - 0x330 */ + volatile u_int32_t BB_green_tx_gain_tab_13; /* 0x330 - 0x334 */ + volatile u_int32_t BB_green_tx_gain_tab_14; /* 0x334 - 0x338 */ + volatile u_int32_t BB_green_tx_gain_tab_15; /* 0x338 - 0x33c */ + volatile u_int32_t BB_green_tx_gain_tab_16; /* 0x33c - 0x340 */ + volatile u_int32_t BB_green_tx_gain_tab_17; /* 0x340 - 0x344 */ + volatile u_int32_t BB_green_tx_gain_tab_18; /* 0x344 - 0x348 */ + volatile u_int32_t BB_green_tx_gain_tab_19; /* 0x348 - 0x34c */ + volatile u_int32_t BB_green_tx_gain_tab_20; /* 0x34c - 0x350 */ + volatile u_int32_t BB_green_tx_gain_tab_21; /* 0x350 - 0x354 */ + volatile u_int32_t BB_green_tx_gain_tab_22; /* 0x354 - 0x358 */ + volatile u_int32_t BB_green_tx_gain_tab_23; /* 0x358 - 0x35c */ + volatile u_int32_t BB_green_tx_gain_tab_24; /* 0x35c - 0x360 */ + volatile u_int32_t BB_green_tx_gain_tab_25; /* 0x360 - 0x364 */ + volatile u_int32_t BB_green_tx_gain_tab_26; /* 0x364 - 0x368 */ + volatile u_int32_t BB_green_tx_gain_tab_27; /* 0x368 - 0x36c */ + volatile u_int32_t BB_green_tx_gain_tab_28; /* 0x36c - 0x370 */ + volatile u_int32_t BB_green_tx_gain_tab_29; /* 0x370 - 0x374 */ + volatile u_int32_t BB_green_tx_gain_tab_30; /* 0x374 - 0x378 */ + volatile u_int32_t BB_green_tx_gain_tab_31; /* 0x378 - 0x37c */ + volatile u_int32_t BB_green_tx_gain_tab_32; /* 0x37c - 0x380 */ + volatile char pad__1[0x27c]; /* 0x380 - 0x5fc */ + volatile u_int32_t BB_sm_ext_dummy2; /* 0x5fc - 0x600 */ +}; + +struct agc1_reg_map { + volatile u_int32_t BB_dummy_DONOTACCESS3; /* 0x0 - 0x4 */ + volatile u_int32_t BB_gain_force_max_gains_b1; /* 0x4 - 0x8 */ + volatile char pad__0[0x10]; /* 0x8 - 0x18 */ + volatile u_int32_t BB_ext_atten_switch_ctl_b1; /* 0x18 - 0x1c */ + /* Not Poseidon */ + volatile u_int32_t BB_cca_b1; /* 0x1c - 0x20 */ + /* Not Poseidon */ + volatile u_int32_t BB_cca_ctrl_2_b1; /* 0x20 - 0x24 */ + volatile char pad__1[0x15c]; /* 0x24 - 0x180 */ + volatile u_int32_t BB_rssi_b1; /* 0x180 - 0x184 */ + /* Not Poseidon */ + volatile u_int32_t BB_spur_est_cck_report_b1; /* 0x184 - 0x188 */ + /* Not Poseidon */ + volatile u_int32_t BB_agc_dig_dc_status_i_b1; /* 0x188 - 0x18c */ + /* Not Poseidon */ + volatile u_int32_t BB_agc_dig_dc_status_q_b1; /* 0x18c - 0x190 */ + /* Jupiter */ + volatile u_int32_t BB_dc_cal_status_b1; /* 0x190 - 0x194 */ + volatile char pad__2[0x6c]; /* 0x194 - 0x200 */ + volatile u_int32_t BB_rx_ocgain2[128]; /* 0x200 - 0x400 */ +}; + +struct sm1_reg_map { + volatile u_int32_t BB_dummy_DONOTACCESS5; /* 0x0 - 0x4 */ + volatile char pad__0[0x80]; /* 0x4 - 0x84 */ + volatile u_int32_t BB_switch_table_chn_b1; /* 0x84 - 0x88 */ + volatile char pad__1[0x48]; /* 0x88 - 0xd0 */ + volatile u_int32_t BB_fcal_2_b1; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_dft_tone_ctrl_b1; /* 0xd4 - 0xd8 */ + volatile char pad__2[0x4]; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_cl_map_0_b1; /* 0xdc - 0xe0 */ + volatile u_int32_t BB_cl_map_1_b1; /* 0xe0 - 0xe4 */ + volatile u_int32_t BB_cl_map_2_b1; /* 0xe4 - 0xe8 */ + volatile u_int32_t BB_cl_map_3_b1; /* 0xe8 - 0xec */ + volatile u_int32_t BB_cl_map_pal_0_b1; /* 0xec - 0xf0 */ + volatile u_int32_t BB_cl_map_pal_1_b1; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_cl_map_pal_2_b1; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_cl_map_pal_3_b1; /* 0xf8 - 0xfc */ + volatile char pad__3[0x4]; /* 0xfc - 0x100 */ + volatile u_int32_t BB_cl_tab_b1[16]; /* 0x100 - 0x140 */ + volatile char pad__4[0x40]; /* 0x140 - 0x180 */ + volatile u_int32_t BB_chan_info_gain_b1; /* 0x180 - 0x184 */ + volatile char pad__5[0x80]; /* 0x184 - 0x204 */ + volatile u_int32_t BB_tpc_4_b1; /* 0x204 - 0x208 */ + volatile u_int32_t BB_tpc_5_b1; /* 0x208 - 0x20c */ + volatile u_int32_t BB_tpc_6_b1; /* 0x20c - 0x210 */ + volatile char pad__6[0x10]; /* 0x210 - 0x220 */ + volatile u_int32_t BB_tpc_11_b1; /* 0x220 - 0x224 */ + volatile char pad__7[0x1c]; /* 0x224 - 0x240 */ + union { + volatile u_int32_t BB_pdadc_tab_b1[32]; /* 0x240 - 0x2c0 */ + struct { + volatile u_int32_t BB_tpc_19_b1; /* 0x240 - 0x244 */ + volatile u_int32_t pad__7_1[31]; /* 0x244 - 0x2c0 */ + volatile char pad__8[0x190]; /* 0x2c0 - 0x450 */ + } Scorpion; + struct { + volatile u_int32_t BB_pdadc_tab_b1[32]; /* 0x240 - 0x2c0 */ + volatile char pad__8[0x190]; /* 0x2c0 - 0x450 */ + } Osprey; + struct { + volatile u_int32_t BB_tpc_19_b1; /* 0x240 - 0x244 */ + volatile char pad__8[0x3c]; /* 0x244 - 0x280 */ + volatile u_int32_t BB_pdadc_tab_b1[32]; /* 0x280 - 0x300 */ + volatile char pad__9[0x84]; /* 0x300 - 0x384 */ + volatile u_int32_t BB_rtt_table_sw_intf_b1; /* 0x384 - 0x388 */ + volatile u_int32_t BB_rtt_table_sw_intf_1_b1; /* 0x388 - 0x38c */ + volatile char pad__10[0xc4]; /* 0x38c - 0x450 */ + } Jupiter_20; + } overlay_b440; + volatile u_int32_t BB_txiq_corr_coeff_01_b1; /* 0x450 - 0x454 */ + volatile u_int32_t BB_txiq_corr_coeff_23_b1; /* 0x454 - 0x458 */ + volatile u_int32_t BB_txiq_corr_coeff_45_b1; /* 0x458 - 0x45c */ + volatile u_int32_t BB_txiq_corr_coeff_67_b1; /* 0x45c - 0x460 */ + volatile u_int32_t BB_txiq_corr_coeff_89_b1; /* 0x460 - 0x464 */ + volatile u_int32_t BB_txiq_corr_coeff_ab_b1; /* 0x464 - 0x468 */ + volatile u_int32_t BB_txiq_corr_coeff_cd_b1; /* 0x468 - 0x46c */ + volatile u_int32_t BB_txiq_corr_coeff_ef_b1; /* 0x46c - 0x470 */ + volatile char pad__9[0x1c]; /* 0x470 - 0x48c */ + volatile u_int32_t BB_txiqcal_status_b1; /* 0x48c - 0x490 */ + volatile char pad__10[0x20]; /* 0x490 - 0x4b0 */ + union { + struct { + volatile char pad__11[0x150]; /* 0x4b0 - 0x600 */ + } Osprey; + struct { + volatile u_int32_t BB_aic_ctrl_0_b1; /* 0x4b0 - 0x4b4 */ + volatile u_int32_t BB_aic_ctrl_1_b1; /* 0x4b4 - 0x4b8 */ + volatile char pad__11[0x8]; /* 0x4b8 - 0x4c0 */ + volatile u_int32_t BB_aic_stat_0_b1; /* 0x4c0 - 0x4c4 */ + volatile u_int32_t BB_aic_stat_1_b1; /* 0x4c4 - 0x4c8 */ + volatile char pad__12[0x128]; /* 0x4c8 - 0x5f0 */ + volatile u_int32_t BB_tables_intf_addr_b1; /* 0x5f0 - 0x5f4 */ + volatile u_int32_t BB_tables_intf_data_b1; /* 0x5f4 - 0x5f8 */ + volatile char pad__13[0x8]; /* 0x5f8 - 0x600 */ + } Jupiter_10; + struct { + volatile u_int32_t BB_aic_ctrl_0_b1; /* 0x4b0 - 0x4b4 */ + volatile u_int32_t BB_aic_ctrl_1_b1; /* 0x4b4 - 0x4b8 */ + volatile char pad__11[0x8]; /* 0x4b8 - 0x4c0 */ + volatile u_int32_t BB_aic_ctrl_4_b1; /* 0x4c0 - 0x4c4 */ + volatile u_int32_t BB_aic_stat_0_b1; /* 0x4c4 - 0x4c8 */ + volatile u_int32_t BB_aic_stat_1_b1; /* 0x4c8 - 0x4cc */ + volatile u_int32_t BB_aic_stat_2_b1; /* 0x4cc - 0x4d0 */ + volatile char pad__12[0x120]; /* 0x4d0 - 0x5f0 */ + volatile u_int32_t BB_tables_intf_addr_b1; /* 0x5f0 - 0x5f4 */ + volatile u_int32_t BB_tables_intf_data_b1; /* 0x5f4 - 0x5f8 */ + volatile char pad__13[0x8]; /* 0x5f8 - 0x600 */ + } Jupiter_20; + } overlay_0x4b0; +}; + +struct chn2_reg_map { + volatile u_int32_t BB_dummy_DONOTACCESS2; /* 0x0 - 0x4 */ + volatile char pad__0[0x2c]; /* 0x4 - 0x30 */ + volatile u_int32_t BB_ext_chan_pwr_thr_2_b2; /* 0x30 - 0x34 */ + volatile char pad__1[0x74]; /* 0x34 - 0xa8 */ + volatile u_int32_t BB_spur_report_b2; /* 0xa8 - 0xac */ + volatile char pad__2[0x14]; /* 0xac - 0xc0 */ + volatile u_int32_t BB_iq_adc_meas_0_b2; /* 0xc0 - 0xc4 */ + volatile u_int32_t BB_iq_adc_meas_1_b2; /* 0xc4 - 0xc8 */ + volatile u_int32_t BB_iq_adc_meas_2_b2; /* 0xc8 - 0xcc */ + volatile u_int32_t BB_iq_adc_meas_3_b2; /* 0xcc - 0xd0 */ + volatile u_int32_t BB_tx_phase_ramp_b2; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_adc_gain_dc_corr_b2; /* 0xd4 - 0xd8 */ + volatile char pad__3[0x4]; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_rx_iq_corr_b2; /* 0xdc - 0xe0 */ + volatile char pad__4[0x10]; /* 0xe0 - 0xf0 */ + volatile u_int32_t BB_paprd_ctrl0_b2; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_paprd_ctrl1_b2; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_pa_gain123_b2; /* 0xf8 - 0xfc */ + volatile u_int32_t BB_pa_gain45_b2; /* 0xfc - 0x100 */ + volatile u_int32_t BB_paprd_pre_post_scale_0_b2; + /* 0x100 - 0x104 */ + volatile u_int32_t BB_paprd_pre_post_scale_1_b2; + /* 0x104 - 0x108 */ + volatile u_int32_t BB_paprd_pre_post_scale_2_b2; + /* 0x108 - 0x10c */ + volatile u_int32_t BB_paprd_pre_post_scale_3_b2; + /* 0x10c - 0x110 */ + volatile u_int32_t BB_paprd_pre_post_scale_4_b2; + /* 0x110 - 0x114 */ + volatile u_int32_t BB_paprd_pre_post_scale_5_b2; + /* 0x114 - 0x118 */ + volatile u_int32_t BB_paprd_pre_post_scale_6_b2; + /* 0x118 - 0x11c */ + volatile u_int32_t BB_paprd_pre_post_scale_7_b2; + /* 0x11c - 0x120 */ + volatile u_int32_t BB_paprd_mem_tab_b2[120]; /* 0x120 - 0x300 */ + volatile u_int32_t BB_chan_info_chan_tab_b2[60]; + /* 0x300 - 0x3f0 */ +}; + +struct agc2_reg_map { + volatile u_int32_t BB_dummy_DONOTACCESS4; /* 0x0 - 0x4 */ + volatile u_int32_t BB_gain_force_max_gains_b2; /* 0x4 - 0x8 */ + volatile char pad__0[0x10]; /* 0x8 - 0x18 */ + volatile u_int32_t BB_ext_atten_switch_ctl_b2; /* 0x18 - 0x1c */ + volatile u_int32_t BB_cca_b2; /* 0x1c - 0x20 */ + volatile u_int32_t BB_cca_ctrl_2_b2; /* 0x20 - 0x24 */ + volatile char pad__1[0x15c]; /* 0x24 - 0x180 */ + volatile u_int32_t BB_rssi_b2; /* 0x180 - 0x184 */ + volatile char pad__2[0x4]; /* 0x184 - 0x188 */ + volatile u_int32_t BB_agc_dig_dc_status_i_b2; /* 0x188 - 0x18c */ + volatile u_int32_t BB_agc_dig_dc_status_q_b2; /* 0x18c - 0x190 */ +}; + +struct sm2_reg_map { + volatile u_int32_t BB_dummy_DONOTACCESS6; /* 0x0 - 0x4 */ + volatile char pad__0[0x80]; /* 0x4 - 0x84 */ + volatile u_int32_t BB_switch_table_chn_b2; /* 0x84 - 0x88 */ + volatile char pad__1[0x48]; /* 0x88 - 0xd0 */ + volatile u_int32_t BB_fcal_2_b2; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_dft_tone_ctrl_b2; /* 0xd4 - 0xd8 */ + volatile char pad__2[0x4]; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_cl_map_0_b2; /* 0xdc - 0xe0 */ + volatile u_int32_t BB_cl_map_1_b2; /* 0xe0 - 0xe4 */ + volatile u_int32_t BB_cl_map_2_b2; /* 0xe4 - 0xe8 */ + volatile u_int32_t BB_cl_map_3_b2; /* 0xe8 - 0xec */ + volatile u_int32_t BB_cl_map_pal_0_b2; /* 0xec - 0xf0 */ + volatile u_int32_t BB_cl_map_pal_1_b2; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_cl_map_pal_2_b2; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_cl_map_pal_3_b2; /* 0xf8 - 0xfc */ + volatile char pad__3[0x4]; /* 0xfc - 0x100 */ + volatile u_int32_t BB_cl_tab_b2[16]; /* 0x100 - 0x140 */ + volatile char pad__4[0x40]; /* 0x140 - 0x180 */ + volatile u_int32_t BB_chan_info_gain_b2; /* 0x180 - 0x184 */ + volatile char pad__5[0x80]; /* 0x184 - 0x204 */ + volatile u_int32_t BB_tpc_4_b2; /* 0x204 - 0x208 */ + volatile u_int32_t BB_tpc_5_b2; /* 0x208 - 0x20c */ + volatile u_int32_t BB_tpc_6_b2; /* 0x20c - 0x210 */ + volatile char pad__6[0x10]; /* 0x210 - 0x220 */ + volatile u_int32_t BB_tpc_11_b2; /* 0x220 - 0x224 */ + volatile char pad__7[0x1c]; /* 0x224 - 0x240 */ + union { + volatile u_int32_t BB_pdadc_tab_b2[32]; /* 0x240 - 0x2c0 */ + struct { + volatile u_int32_t BB_tpc_19_b2; /* 0x240 - 0x244 */ + volatile u_int32_t pad__7_1[31]; /* 0x244 - 0x2c0 */ + } Scorpion; + } overlay_c440; + volatile char pad__8[0x190]; /* 0x2c0 - 0x450 */ + volatile u_int32_t BB_txiq_corr_coeff_01_b2; /* 0x450 - 0x454 */ + volatile u_int32_t BB_txiq_corr_coeff_23_b2; /* 0x454 - 0x458 */ + volatile u_int32_t BB_txiq_corr_coeff_45_b2; /* 0x458 - 0x45c */ + volatile u_int32_t BB_txiq_corr_coeff_67_b2; /* 0x45c - 0x460 */ + volatile u_int32_t BB_txiq_corr_coeff_89_b2; /* 0x460 - 0x464 */ + volatile u_int32_t BB_txiq_corr_coeff_ab_b2; /* 0x464 - 0x468 */ + volatile u_int32_t BB_txiq_corr_coeff_cd_b2; /* 0x468 - 0x46c */ + volatile u_int32_t BB_txiq_corr_coeff_ef_b2; /* 0x46c - 0x470 */ + volatile char pad__9[0x1c]; /* 0x470 - 0x48c */ + volatile u_int32_t BB_txiqcal_status_b2; /* 0x48c - 0x490 */ + volatile char pad__10[0x16c]; /* 0x490 - 0x5fc */ + volatile u_int32_t BB_dummy_sm2; /* 0x5fc - 0x600 */ +}; + +struct chn3_reg_map { + volatile u_int32_t BB_dummy1[256]; /* 0x0 - 0x400 */ +}; + +struct agc3_reg_map { + volatile u_int32_t BB_dummy; /* 0x0 - 0x4 */ + volatile char pad__0[0x17c]; /* 0x4 - 0x180 */ + volatile u_int32_t BB_rssi_b3; /* 0x180 - 0x184 */ +}; + +struct sm3_reg_map { + volatile u_int32_t BB_dummy2[384]; /* 0x0 - 0x600 */ +}; + +struct bb_reg_map { + volatile char pad__0[0x9800]; /* 0x0 - 0x9800 */ + struct chn_reg_map bb_chn_reg_map; /* 0x9800 - 0x9bf8 */ + volatile char pad__1[0x8]; /* 0x9bf8 - 0x9c00 */ + struct mrc_reg_map bb_mrc_reg_map; /* 0x9c00 - 0x9c24 */ + volatile char pad__2[0xdc]; /* 0x9c24 - 0x9d00 */ + struct bbb_reg_map bb_bbb_reg_map; /* 0x9d00 - 0x9d20 */ + volatile char pad__3[0xe0]; /* 0x9d20 - 0x9e00 */ + struct agc_reg_map bb_agc_reg_map; /* 0x9e00 - 0xa200 */ + struct sm_reg_map bb_sm_reg_map; /* 0xa200 - 0xa7f8 */ + volatile char pad__4[0x8]; /* 0xa7f8 - 0xa800 */ + union { + struct { + struct chn1_reg_map bb_chn1_reg_map; /* 0xa800 - 0xabf8 */ + volatile char pad__5[0x208]; /* 0xabf8 - 0xae00 */ + struct agc1_reg_map bb_agc1_reg_map; /* 0xae00 - 0xb200 */ + struct sm1_reg_map bb_sm1_reg_map; /* 0xb200 - 0xb800 */ + struct chn2_reg_map bb_chn2_reg_map; /* 0xb800 - 0xbbf0 */ + volatile char pad__6[0x210]; /* 0xbbf0 - 0xbe00 */ + struct agc2_reg_map bb_agc2_reg_map; /* 0xbe00 - 0xbf90 */ + volatile char pad__7[0x270]; /* 0xbf90 - 0xc200 */ + struct sm2_reg_map bb_sm2_reg_map; /* 0xc200 - 0xc800 */ + } Osprey; + struct { + struct chn_ext_reg_map bb_chn_ext_reg_map; /* 0xa800 - 0xac00 */ + volatile char pad__5[0x600]; /* 0xac00 - 0xb200 */ + struct sm_ext_reg_map bb_sm_ext_reg_map; /* 0xb200 - 0xb800 */ + volatile char pad__6[0x600]; /* 0xb800 - 0xbe00 */ + struct agc1_reg_map bb_agc1_reg_map; /* 0xbe00 - 0xc1fc */ + volatile char pad__7[0x4]; /* 0xc1fc - 0xc200 */ + struct sm1_reg_map bb_sm1_reg_map; /* 0xc200 - 0xc800 */ + } Poseidon; + } overlay_0xa800; + struct chn3_reg_map bb_chn3_reg_map; /* 0xc800 - 0xcc00 */ + volatile char pad__8[0x200]; /* 0xcc00 - 0xce00 */ + struct agc3_reg_map bb_agc3_reg_map; /* 0xce00 - 0xcf84 */ + volatile char pad__9[0x27c]; /* 0xcf84 - 0xd200 */ + struct sm3_reg_map bb_sm3_reg_map; /* 0xd200 - 0xd800 */ +}; + +struct svd_reg { + volatile char pad__0[0x10000]; /* 0x0 - 0x10000 */ + volatile u_int32_t TXBF_DBG; /* 0x10000 - 0x10004 */ + volatile u_int32_t TXBF; /* 0x10004 - 0x10008 */ + volatile u_int32_t TXBF_TIMER; /* 0x10008 - 0x1000c */ + volatile u_int32_t TXBF_SW; /* 0x1000c - 0x10010 */ + volatile u_int32_t TXBF_SM; /* 0x10010 - 0x10014 */ + volatile u_int32_t TXBF1_CNTL; /* 0x10014 - 0x10018 */ + volatile u_int32_t TXBF2_CNTL; /* 0x10018 - 0x1001c */ + volatile u_int32_t TXBF3_CNTL; /* 0x1001c - 0x10020 */ + volatile u_int32_t TXBF4_CNTL; /* 0x10020 - 0x10024 */ + volatile u_int32_t TXBF5_CNTL; /* 0x10024 - 0x10028 */ + volatile u_int32_t TXBF6_CNTL; /* 0x10028 - 0x1002c */ + volatile u_int32_t TXBF7_CNTL; /* 0x1002c - 0x10030 */ + volatile u_int32_t TXBF8_CNTL; /* 0x10030 - 0x10034 */ + volatile char pad__1[0xfcc]; /* 0x10034 - 0x11000 */ + volatile u_int32_t RC0[118]; /* 0x11000 - 0x111d8 */ + volatile char pad__2[0x28]; /* 0x111d8 - 0x11200 */ + volatile u_int32_t RC1[118]; /* 0x11200 - 0x113d8 */ + volatile char pad__3[0x28]; /* 0x113d8 - 0x11400 */ + volatile u_int32_t SVD_MEM0[114]; /* 0x11400 - 0x115c8 */ + volatile char pad__4[0x38]; /* 0x115c8 - 0x11600 */ + volatile u_int32_t SVD_MEM1[114]; /* 0x11600 - 0x117c8 */ + volatile char pad__5[0x38]; /* 0x117c8 - 0x11800 */ + volatile u_int32_t SVD_MEM2[114]; /* 0x11800 - 0x119c8 */ + volatile char pad__6[0x38]; /* 0x119c8 - 0x11a00 */ + volatile u_int32_t SVD_MEM3[114]; /* 0x11a00 - 0x11bc8 */ + volatile char pad__7[0x38]; /* 0x11bc8 - 0x11c00 */ + volatile u_int32_t SVD_MEM4[114]; /* 0x11c00 - 0x11dc8 */ + volatile char pad__8[0x638]; /* 0x11dc8 - 0x12400 */ + volatile u_int32_t CVCACHE[512]; /* 0x12400 - 0x12c00 */ +}; + +struct efuse_reg_WLAN { + volatile char pad__0[0x14000]; /* 0x0 - 0x14000 */ + volatile u_int32_t OTP_MEM[256]; /* 0x14000 - 0x14400 */ + volatile char pad__1[0x1b00]; /* 0x14400 - 0x15f00 */ + volatile u_int32_t OTP_INTF0; /* 0x15f00 - 0x15f04 */ + volatile u_int32_t OTP_INTF1; /* 0x15f04 - 0x15f08 */ + volatile u_int32_t OTP_INTF2; /* 0x15f08 - 0x15f0c */ + volatile u_int32_t OTP_INTF3; /* 0x15f0c - 0x15f10 */ + volatile u_int32_t OTP_INTF4; /* 0x15f10 - 0x15f14 */ + volatile u_int32_t OTP_INTF5; /* 0x15f14 - 0x15f18 */ + volatile u_int32_t OTP_STATUS0; /* 0x15f18 - 0x15f1c */ + volatile u_int32_t OTP_STATUS1; /* 0x15f1c - 0x15f20 */ + volatile u_int32_t OTP_INTF6; /* 0x15f20 - 0x15f24 */ + volatile u_int32_t OTP_LDO_CONTROL; /* 0x15f24 - 0x15f28 */ + volatile u_int32_t OTP_LDO_POWER_GOOD; /* 0x15f28 - 0x15f2c */ + volatile u_int32_t OTP_LDO_STATUS; /* 0x15f2c - 0x15f30 */ + volatile u_int32_t OTP_VDDQ_HOLD_TIME; /* 0x15f30 - 0x15f34 */ + volatile u_int32_t OTP_PGENB_SETUP_HOLD_TIME; /* 0x15f34 - 0x15f38 */ + volatile u_int32_t OTP_STROBE_PULSE_INTERVAL; /* 0x15f38 - 0x15f3c */ + volatile u_int32_t OTP_CSB_ADDR_LOAD_SETUP_HOLD; + /* 0x15f3c - 0x15f40 */ +}; + +struct radio65_reg { + volatile char pad__0[0x16000]; /* 0x0 - 0x16000 */ + volatile u_int32_t ch0_RXRF_BIAS1; /* 0x16000 - 0x16004 */ + volatile u_int32_t ch0_RXRF_BIAS2; /* 0x16004 - 0x16008 */ + volatile u_int32_t ch0_RXRF_GAINSTAGES; /* 0x16008 - 0x1600c */ + volatile u_int32_t ch0_RXRF_AGC; /* 0x1600c - 0x16010 */ + /* Jupiter */ + volatile u_int32_t ch0_RXRF_BIAS3; /* 0x16010 - 0x16014 */ + volatile char pad__1[0x2c]; /* 0x16014 - 0x16040 */ + volatile u_int32_t ch0_TXRF1; /* 0x16040 - 0x16044 */ + volatile u_int32_t ch0_TXRF2; /* 0x16044 - 0x16048 */ + volatile u_int32_t ch0_TXRF3; /* 0x16048 - 0x1604c */ + volatile u_int32_t ch0_TXRF4; /* 0x1604c - 0x16050 */ + volatile u_int32_t ch0_TXRF5; /* 0x16050 - 0x16054 */ + volatile u_int32_t ch0_TXRF6; /* 0x16054 - 0x16058 */ + /* Not Poseidon */ + volatile u_int32_t ch0_TXRF7; /* 0x16058 - 0x1605c */ + /* Not Poseidon */ + volatile u_int32_t ch0_TXRF8; /* 0x1605c - 0x16060 */ + /* Not Poseidon */ + volatile u_int32_t ch0_TXRF9; /* 0x16060 - 0x16064 */ + /* Not Poseidon */ + volatile u_int32_t ch0_TXRF10; /* 0x16064 - 0x16068 */ + /* Not Poseidon */ + volatile u_int32_t ch0_TXRF11; /* 0x16068 - 0x1606c */ + /* Not Poseidon */ + volatile u_int32_t ch0_TXRF12; /* 0x1606c - 0x16070 */ + volatile char pad__2[0x10]; /* 0x16070 - 0x16080 */ + volatile u_int32_t ch0_SYNTH1; /* 0x16080 - 0x16084 */ + volatile u_int32_t ch0_SYNTH2; /* 0x16084 - 0x16088 */ + volatile u_int32_t ch0_SYNTH3; /* 0x16088 - 0x1608c */ + volatile u_int32_t ch0_SYNTH4; /* 0x1608c - 0x16090 */ + volatile u_int32_t ch0_SYNTH5; /* 0x16090 - 0x16094 */ + volatile u_int32_t ch0_SYNTH6; /* 0x16094 - 0x16098 */ + volatile u_int32_t ch0_SYNTH7; /* 0x16098 - 0x1609c */ + volatile u_int32_t ch0_SYNTH8; /* 0x1609c - 0x160a0 */ + volatile u_int32_t ch0_SYNTH9; /* 0x160a0 - 0x160a4 */ + volatile u_int32_t ch0_SYNTH10; /* 0x160a4 - 0x160a8 */ + volatile u_int32_t ch0_SYNTH11; /* 0x160a8 - 0x160ac */ + volatile u_int32_t ch0_SYNTH12; /* 0x160ac - 0x160b0 */ + volatile u_int32_t ch0_SYNTH13; /* 0x160b0 - 0x160b4 */ + volatile u_int32_t ch0_SYNTH14; /* 0x160b4 - 0x160b8 */ + /* Jupiter */ + volatile u_int32_t ch0_SYNTH15; /* 0x160b8 - 0x160bc */ + /* Jupiter */ + volatile u_int32_t ch0_SYNTH16; /* 0x160bc - 0x160c0 */ + volatile u_int32_t ch0_BIAS1; /* 0x160c0 - 0x160c4 */ + volatile u_int32_t ch0_BIAS2; /* 0x160c4 - 0x160c8 */ + volatile u_int32_t ch0_BIAS3; /* 0x160c8 - 0x160cc */ + volatile u_int32_t ch0_BIAS4; /* 0x160cc - 0x160d0 */ + /* Poseidon */ + volatile u_int32_t ch0_BIAS5; /* 0x160d0 - 0x160d4 */ + volatile char pad__3[0x2c]; /* 0x160d4 - 0x16100 */ + volatile u_int32_t ch0_RXTX1; /* 0x16100 - 0x16104 */ + volatile u_int32_t ch0_RXTX2; /* 0x16104 - 0x16108 */ + volatile u_int32_t ch0_RXTX3; /* 0x16108 - 0x1610c */ + volatile u_int32_t ch0_RXTX4; /* 0x1610c - 0x16110 */ + /* Jupiter */ + volatile u_int32_t ch0_RXTX5; /* 0x16110 - 0x16114 */ + volatile char pad__4[0x2c]; /* 0x16114 - 0x16140 */ + volatile u_int32_t ch0_BB1; /* 0x16140 - 0x16144 */ + volatile u_int32_t ch0_BB2; /* 0x16144 - 0x16148 */ + volatile u_int32_t ch0_BB3; /* 0x16148 - 0x1614c */ + volatile char pad__6[0x34]; /* 0x1614c - 0x16180 */ + union { + struct { + volatile u_int32_t ch0_pll_cntl; /* 0x16180 - 0x16184 */ + volatile u_int32_t ch0_pll_mode; /* 0x16184 - 0x16188 */ + volatile u_int32_t ch0_bb_dpll3; /* 0x16188 - 0x1618c */ + volatile u_int32_t ch0_bb_dpll4; /* 0x1618c - 0x16190 */ + volatile char pad__6_1[0xf0]; /* 0x16190 - 0x16280 */ + volatile u_int32_t ch0_PLLCLKMODA; /* 0x16280 - 0x16284 */ + volatile u_int32_t ch0_PLLCLKMODA2; /* 0x16284 - 0x16288 */ + volatile u_int32_t ch0_TOP; /* 0x16288 - 0x1628c */ + volatile u_int32_t ch0_TOP2; /* 0x1628c - 0x16290 */ + volatile u_int32_t ch0_THERM; /* 0x16290 - 0x16294 */ + volatile u_int32_t ch0_XTAL; /* 0x16294 - 0x16298 */ + volatile char pad__7[0xe8]; /* 0x16298 - 0x16380 */ + } Osprey; + struct { + volatile u_int32_t ch0_BB_DPLL1; /* 0x16180 - 0x16184 */ + volatile u_int32_t ch0_BB_DPLL2; /* 0x16184 - 0x16188 */ + volatile u_int32_t ch0_BB_DPLL3; /* 0x16188 - 0x1618c */ + volatile u_int32_t ch0_BB_DPLL4; /* 0x1618c - 0x16190 */ + volatile char pad__7[0xb0]; /* 0x16190 - 0x16240 */ + volatile u_int32_t ch0_DDR_DPLL1; /* 0x16240 - 0x16244 */ + volatile u_int32_t ch0_DDR_DPLL2; /* 0x16244 - 0x16248 */ + volatile u_int32_t ch0_DDR_DPLL3; /* 0x16248 - 0x1624c */ + volatile u_int32_t ch0_DDR_DPLL4; /* 0x1624c - 0x16250 */ + volatile char pad__8[0x30]; /* 0x16250 - 0x16280 */ + volatile u_int32_t ch0_TOP; /* 0x16280 - 0x16284 */ + volatile u_int32_t ch0_TOP2; /* 0x16284 - 0x16288 */ + volatile u_int32_t ch0_TOP3; /* 0x16288 - 0x1628c */ + volatile u_int32_t ch0_THERM; /* 0x1628c - 0x16290 */ + volatile u_int32_t ch0_XTAL; /* 0x16290 - 0x16294 */ + volatile char pad__9[0xec]; /* 0x16294 - 0x16380 */ + } Poseidon; + struct { + volatile char pad__6_1[0x100]; /* 0x16180 - 0x16280 */ + volatile u_int32_t ch0_PLLCLKMODA1; /* 0x16280 - 0x16284 */ + volatile u_int32_t ch0_PLLCLKMODA2; /* 0x16284 - 0x16288 */ + volatile u_int32_t ch0_PLLCLKMODA3; /* 0x16288 - 0x1628c */ + volatile u_int32_t ch0_TOP1; /* 0x1628c - 0x16290 */ + volatile u_int32_t ch0_TOP2; /* 0x16290 - 0x16294 */ + volatile u_int32_t ch0_THERM; /* 0x16294 - 0x16298 */ + volatile u_int32_t ch0_XTAL; /* 0x16298 - 0x1629c */ + volatile char pad__7[0xa4]; /* 0x1629c - 0x16340 */ + volatile u_int32_t ch0_PMU1; /* 0x16340 - 0x16344 */ + volatile u_int32_t ch0_PMU2; /* 0x16344 - 0x16348 */ + volatile u_int32_t ch0_PMU3; /* 0x16348 - 0x1634c */ + volatile char pad__8[0x34]; /* 0x1634c - 0x16380 */ + } Jupiter; + struct { + volatile u_int32_t ch0_DPLL; /* 0x16180 - 0x16184 */ + volatile u_int32_t ch0_DPLL2; /* 0x16184 - 0x16188 */ + volatile u_int32_t ch0_DPLL3; /* 0x16188 - 0x1618c */ + volatile u_int32_t ch0_DPLL4; /* 0x1618c - 0x16190 */ + volatile u_int32_t ch0_DPLL5; /* 0x16190 - 0x16194 */ + volatile char pad__6[0xec]; /* 0x16194 - 0x16280 */ + volatile u_int32_t ch0_PLLCLKMODA1; /* 0x16280 - 0x16284 */ + volatile u_int32_t ch0_PLLCLKMODA2; /* 0x16284 - 0x16288 */ + volatile u_int32_t ch0_PLLCLKMODA3; /* 0x16288 - 0x1628c */ + volatile u_int32_t ch0_TOP1; /* 0x1628c - 0x16290 */ + volatile u_int32_t ch0_TOP2; /* 0x16290 - 0x16294 */ + volatile u_int32_t ch0_THERM; /* 0x16294 - 0x16298 */ + volatile u_int32_t ch0_XTAL; /* 0x16298 - 0x1629c */ + volatile char pad__7[0xa4]; /* 0x1629c - 0x16340 */ + volatile u_int32_t ch0_PMU1; /* 0x16340 - 0x16344 */ + volatile u_int32_t ch0_PMU2; /* 0x16344 - 0x16348 */ + volatile char pad__8[0x38]; /* 0x16348 - 0x16380 */ + } Aphrodite; + } overlay_0x16180; + volatile u_int32_t ch0_rbist_cntrl; /* 0x16380 - 0x16384 */ + volatile u_int32_t ch0_tx_dc_offset; /* 0x16384 - 0x16388 */ + volatile u_int32_t ch0_tx_tonegen0; /* 0x16388 - 0x1638c */ + volatile u_int32_t ch0_tx_tonegen1; /* 0x1638c - 0x16390 */ + volatile u_int32_t ch0_tx_lftonegen0; /* 0x16390 - 0x16394 */ + volatile u_int32_t ch0_tx_linear_ramp_i; /* 0x16394 - 0x16398 */ + volatile u_int32_t ch0_tx_linear_ramp_q; /* 0x16398 - 0x1639c */ + volatile u_int32_t ch0_tx_prbs_mag; /* 0x1639c - 0x163a0 */ + volatile u_int32_t ch0_tx_prbs_seed_i; /* 0x163a0 - 0x163a4 */ + volatile u_int32_t ch0_tx_prbs_seed_q; /* 0x163a4 - 0x163a8 */ + volatile u_int32_t ch0_cmac_dc_cancel; /* 0x163a8 - 0x163ac */ + volatile u_int32_t ch0_cmac_dc_offset; /* 0x163ac - 0x163b0 */ + volatile u_int32_t ch0_cmac_corr; /* 0x163b0 - 0x163b4 */ + volatile u_int32_t ch0_cmac_power; /* 0x163b4 - 0x163b8 */ + volatile u_int32_t ch0_cmac_cross_corr; /* 0x163b8 - 0x163bc */ + volatile u_int32_t ch0_cmac_i2q2; /* 0x163bc - 0x163c0 */ + volatile u_int32_t ch0_cmac_power_hpf; /* 0x163c0 - 0x163c4 */ + volatile u_int32_t ch0_rxdac_set1; /* 0x163c4 - 0x163c8 */ + volatile u_int32_t ch0_rxdac_set2; /* 0x163c8 - 0x163cc */ + volatile u_int32_t ch0_rxdac_long_shift; /* 0x163cc - 0x163d0 */ + volatile u_int32_t ch0_cmac_results_i; /* 0x163d0 - 0x163d4 */ + volatile u_int32_t ch0_cmac_results_q; /* 0x163d4 - 0x163d8 */ + volatile char pad__8[0x28]; /* 0x163d8 - 0x16400 */ + volatile u_int32_t ch1_RXRF_BIAS1; /* 0x16400 - 0x16404 */ + volatile u_int32_t ch1_RXRF_BIAS2; /* 0x16404 - 0x16408 */ + volatile u_int32_t ch1_RXRF_GAINSTAGES; /* 0x16408 - 0x1640c */ + volatile u_int32_t ch1_RXRF_AGC; /* 0x1640c - 0x16410 */ + /* Jupiter */ + volatile u_int32_t ch1_RXRF_BIAS3; /* 0x16410 - 0x16414 */ + volatile char pad__9[0x2c]; /* 0x16414 - 0x16440 */ + volatile u_int32_t ch1_TXRF1; /* 0x16440 - 0x16444 */ + volatile u_int32_t ch1_TXRF2; /* 0x16444 - 0x16448 */ + volatile u_int32_t ch1_TXRF3; /* 0x16448 - 0x1644c */ + volatile u_int32_t ch1_TXRF4; /* 0x1644c - 0x16450 */ + volatile u_int32_t ch1_TXRF5; /* 0x16450 - 0x16454 */ + volatile u_int32_t ch1_TXRF6; /* 0x16454 - 0x16458 */ + volatile u_int32_t ch1_TXRF7; /* 0x16458 - 0x1645c */ + volatile u_int32_t ch1_TXRF8; /* 0x1645c - 0x16460 */ + volatile u_int32_t ch1_TXRF9; /* 0x16460 - 0x16464 */ + volatile u_int32_t ch1_TXRF10; /* 0x16464 - 0x16468 */ + volatile u_int32_t ch1_TXRF11; /* 0x16468 - 0x1646c */ + volatile u_int32_t ch1_TXRF12; /* 0x1646c - 0x16470 */ + volatile char pad__10[0x90]; /* 0x16470 - 0x16500 */ + volatile u_int32_t ch1_RXTX1; /* 0x16500 - 0x16504 */ + volatile u_int32_t ch1_RXTX2; /* 0x16504 - 0x16508 */ + volatile u_int32_t ch1_RXTX3; /* 0x16508 - 0x1650c */ + volatile u_int32_t ch1_RXTX4; /* 0x1650c - 0x16510 */ + /* Jupiter */ + volatile u_int32_t ch1_RXTX5; /* 0x16510 - 0x16514 */ + volatile char pad__11[0x2c]; /* 0x16514 - 0x16540 */ + volatile u_int32_t ch1_BB1; /* 0x16540 - 0x16544 */ + volatile u_int32_t ch1_BB2; /* 0x16544 - 0x16548 */ + volatile u_int32_t ch1_BB3; /* 0x16548 - 0x1654c */ + volatile char pad__12[0x234]; /* 0x1654c - 0x16780 */ + volatile u_int32_t ch1_rbist_cntrl; /* 0x16780 - 0x16784 */ + volatile u_int32_t ch1_tx_dc_offset; /* 0x16784 - 0x16788 */ + volatile u_int32_t ch1_tx_tonegen0; /* 0x16788 - 0x1678c */ + volatile u_int32_t ch1_tx_tonegen1; /* 0x1678c - 0x16790 */ + volatile u_int32_t ch1_tx_lftonegen0; /* 0x16790 - 0x16794 */ + volatile u_int32_t ch1_tx_linear_ramp_i; /* 0x16794 - 0x16798 */ + volatile u_int32_t ch1_tx_linear_ramp_q; /* 0x16798 - 0x1679c */ + volatile u_int32_t ch1_tx_prbs_mag; /* 0x1679c - 0x167a0 */ + volatile u_int32_t ch1_tx_prbs_seed_i; /* 0x167a0 - 0x167a4 */ + volatile u_int32_t ch1_tx_prbs_seed_q; /* 0x167a4 - 0x167a8 */ + volatile u_int32_t ch1_cmac_dc_cancel; /* 0x167a8 - 0x167ac */ + volatile u_int32_t ch1_cmac_dc_offset; /* 0x167ac - 0x167b0 */ + volatile u_int32_t ch1_cmac_corr; /* 0x167b0 - 0x167b4 */ + volatile u_int32_t ch1_cmac_power; /* 0x167b4 - 0x167b8 */ + volatile u_int32_t ch1_cmac_cross_corr; /* 0x167b8 - 0x167bc */ + volatile u_int32_t ch1_cmac_i2q2; /* 0x167bc - 0x167c0 */ + volatile u_int32_t ch1_cmac_power_hpf; /* 0x167c0 - 0x167c4 */ + volatile u_int32_t ch1_rxdac_set1; /* 0x167c4 - 0x167c8 */ + volatile u_int32_t ch1_rxdac_set2; /* 0x167c8 - 0x167cc */ + volatile u_int32_t ch1_rxdac_long_shift; /* 0x167cc - 0x167d0 */ + volatile u_int32_t ch1_cmac_results_i; /* 0x167d0 - 0x167d4 */ + volatile u_int32_t ch1_cmac_results_q; /* 0x167d4 - 0x167d8 */ + volatile char pad__13[0x28]; /* 0x167d8 - 0x16800 */ + volatile u_int32_t ch2_RXRF_BIAS1; /* 0x16800 - 0x16804 */ + volatile u_int32_t ch2_RXRF_BIAS2; /* 0x16804 - 0x16808 */ + volatile u_int32_t ch2_RXRF_GAINSTAGES; /* 0x16808 - 0x1680c */ + volatile u_int32_t ch2_RXRF_AGC; /* 0x1680c - 0x16810 */ + volatile char pad__14[0x30]; /* 0x16810 - 0x16840 */ + volatile u_int32_t ch2_TXRF1; /* 0x16840 - 0x16844 */ + volatile u_int32_t ch2_TXRF2; /* 0x16844 - 0x16848 */ + volatile u_int32_t ch2_TXRF3; /* 0x16848 - 0x1684c */ + volatile u_int32_t ch2_TXRF4; /* 0x1684c - 0x16850 */ + volatile u_int32_t ch2_TXRF5; /* 0x16850 - 0x16854 */ + volatile u_int32_t ch2_TXRF6; /* 0x16854 - 0x16858 */ + volatile u_int32_t ch2_TXRF7; /* 0x16858 - 0x1685c */ + volatile u_int32_t ch2_TXRF8; /* 0x1685c - 0x16860 */ + volatile u_int32_t ch2_TXRF9; /* 0x16860 - 0x16864 */ + volatile u_int32_t ch2_TXRF10; /* 0x16864 - 0x16868 */ + volatile u_int32_t ch2_TXRF11; /* 0x16868 - 0x1686c */ + volatile u_int32_t ch2_TXRF12; /* 0x1686c - 0x16870 */ + volatile char pad__15[0x90]; /* 0x16870 - 0x16900 */ + volatile u_int32_t ch2_RXTX1; /* 0x16900 - 0x16904 */ + volatile u_int32_t ch2_RXTX2; /* 0x16904 - 0x16908 */ + volatile u_int32_t ch2_RXTX3; /* 0x16908 - 0x1690c */ + volatile u_int32_t ch2_RXTX4; /* 0x1690c - 0x16910 */ + volatile char pad__16[0x30]; /* 0x16910 - 0x16940 */ + volatile u_int32_t ch2_BB1; /* 0x16940 - 0x16944 */ + volatile u_int32_t ch2_BB2; /* 0x16944 - 0x16948 */ + volatile u_int32_t ch2_BB3; /* 0x16948 - 0x1694c */ + volatile char pad__17[0x234]; /* 0x1694c - 0x16b80 */ + volatile u_int32_t ch2_rbist_cntrl; /* 0x16b80 - 0x16b84 */ + volatile u_int32_t ch2_tx_dc_offset; /* 0x16b84 - 0x16b88 */ + volatile u_int32_t ch2_tx_tonegen0; /* 0x16b88 - 0x16b8c */ + volatile u_int32_t ch2_tx_tonegen1; /* 0x16b8c - 0x16b90 */ + volatile u_int32_t ch2_tx_lftonegen0; /* 0x16b90 - 0x16b94 */ + volatile u_int32_t ch2_tx_linear_ramp_i; /* 0x16b94 - 0x16b98 */ + volatile u_int32_t ch2_tx_linear_ramp_q; /* 0x16b98 - 0x16b9c */ + volatile u_int32_t ch2_tx_prbs_mag; /* 0x16b9c - 0x16ba0 */ + volatile u_int32_t ch2_tx_prbs_seed_i; /* 0x16ba0 - 0x16ba4 */ + volatile u_int32_t ch2_tx_prbs_seed_q; /* 0x16ba4 - 0x16ba8 */ + volatile u_int32_t ch2_cmac_dc_cancel; /* 0x16ba8 - 0x16bac */ + volatile u_int32_t ch2_cmac_dc_offset; /* 0x16bac - 0x16bb0 */ + volatile u_int32_t ch2_cmac_corr; /* 0x16bb0 - 0x16bb4 */ + volatile u_int32_t ch2_cmac_power; /* 0x16bb4 - 0x16bb8 */ + volatile u_int32_t ch2_cmac_cross_corr; /* 0x16bb8 - 0x16bbc */ + volatile u_int32_t ch2_cmac_i2q2; /* 0x16bbc - 0x16bc0 */ + volatile u_int32_t ch2_cmac_power_hpf; /* 0x16bc0 - 0x16bc4 */ + volatile u_int32_t ch2_rxdac_set1; /* 0x16bc4 - 0x16bc8 */ + volatile u_int32_t ch2_rxdac_set2; /* 0x16bc8 - 0x16bcc */ + volatile u_int32_t ch2_rxdac_long_shift; /* 0x16bcc - 0x16bd0 */ + volatile u_int32_t ch2_cmac_results_i; /* 0x16bd0 - 0x16bd4 */ + volatile u_int32_t ch2_cmac_results_q; /* 0x16bd4 - 0x16bd8 */ + volatile char pad__18[0x4c4a8]; /* 0x16bd8 - 0x63080 */ + /* Jupiter-start */ + volatile u_int32_t chbt_SYNTH1; /* 0x63080 - 0x63084 */ + volatile u_int32_t chbt_SYNTH2; /* 0x63084 - 0x63088 */ + volatile u_int32_t chbt_SYNTH3; /* 0x63088 - 0x6308c */ + volatile u_int32_t chbt_SYNTH4; /* 0x6308c - 0x63090 */ + volatile u_int32_t chbt_SYNTH5; /* 0x63090 - 0x63094 */ + volatile u_int32_t chbt_SYNTH6; /* 0x63094 - 0x63098 */ + volatile u_int32_t chbt_SYNTH7; /* 0x63098 - 0x6309c */ + volatile u_int32_t chbt_SYNTH8; /* 0x6309c - 0x630a0 */ + volatile char pad__19[0x20]; /* 0x630a0 - 0x630c0 */ + volatile u_int32_t chbt_BIAS1; /* 0x630c0 - 0x630c4 */ + volatile u_int32_t chbt_BIAS2; /* 0x630c4 - 0x630c8 */ + volatile u_int32_t chbt_BIAS3; /* 0x630c8 - 0x630cc */ + volatile u_int32_t chbt_BIAS4; /* 0x630cc - 0x630d0 */ + volatile u_int32_t chbt_BIAS5; /* 0x630d0 - 0x630d4 */ + volatile char pad__20[0x2c]; /* 0x630d4 - 0x63100 */ + volatile u_int32_t chbt_TOP1; /* 0x63100 - 0x63104 */ + volatile u_int32_t chbt_TOP2; /* 0x63104 - 0x63108 */ + volatile u_int32_t chbt_TOP3; /* 0x63108 - 0x6310c */ + volatile u_int32_t chbt_TOP4; /* 0x6310c - 0x63110 */ + volatile u_int32_t chbt_TOP5; /* 0x63110 - 0x63114 */ + volatile u_int32_t chbt_TOP6; /* 0x63114 - 0x63118 */ + volatile u_int32_t chbt_TOP7; /* 0x63118 - 0x6311c */ + volatile u_int32_t chbt_TOP8; /* 0x6311c - 0x63120 */ + volatile u_int32_t chbt_TOP9; /* 0x63120 - 0x63124 */ + volatile u_int32_t chbt_TOP10; /* 0x63124 - 0x63128 */ + volatile char pad__21[0x158]; /* 0x63128 - 0x63280 */ + volatile u_int32_t chbt_CLK1; /* 0x63280 - 0x63284 */ + volatile u_int32_t chbt_CLK2; /* 0x63284 - 0x63288 */ + volatile u_int32_t chbt_CLK3; /* 0x63288 - 0x6328c */ + volatile char pad__22[0xb4]; /* 0x6328c - 0x63340 */ + volatile u_int32_t chbt_PMU1; /* 0x63340 - 0x63344 */ + volatile u_int32_t chbt_PMU2; /* 0x63344 - 0x63348 */ + /* Jupiter-end */ + /* Aphrodite-start */ + volatile char pad__23[0x38]; /* 0x63348 - 0x63380 */ + volatile u_int32_t chbt_rbist_cntrl; /* 0x63380 - 0x63384 */ + volatile u_int32_t chbt_tx_dc_offset; /* 0x63384 - 0x63388 */ + volatile u_int32_t chbt_tx_tonegen0; /* 0x63388 - 0x6338c */ + volatile u_int32_t chbt_tx_tonegen1; /* 0x6338c - 0x63390 */ + volatile u_int32_t chbt_tx_lftonegen0; /* 0x63390 - 0x63394 */ + volatile u_int32_t chbt_tx_linear_ramp_i; /* 0x63394 - 0x63398 */ + volatile u_int32_t chbt_tx_linear_ramp_q; /* 0x63398 - 0x6339c */ + volatile u_int32_t chbt_tx_prbs_mag; /* 0x6339c - 0x633a0 */ + volatile u_int32_t chbt_tx_prbs_seed_i; /* 0x633a0 - 0x633a4 */ + volatile u_int32_t chbt_tx_prbs_seed_q; /* 0x633a4 - 0x633a8 */ + volatile u_int32_t chbt_cmac_dc_cancel; /* 0x633a8 - 0x633ac */ + volatile u_int32_t chbt_cmac_dc_offset; /* 0x633ac - 0x633b0 */ + volatile u_int32_t chbt_cmac_corr; /* 0x633b0 - 0x633b4 */ + volatile u_int32_t chbt_cmac_power; /* 0x633b4 - 0x633b8 */ + volatile u_int32_t chbt_cmac_cross_corr; /* 0x633b8 - 0x633bc */ + volatile u_int32_t chbt_cmac_i2q2; /* 0x633bc - 0x633c0 */ + volatile u_int32_t chbt_cmac_power_hpf; /* 0x633c0 - 0x633c4 */ + volatile u_int32_t chbt_rxdac_set1; /* 0x633c4 - 0x633c8 */ + volatile u_int32_t chbt_rxdac_set2; /* 0x633c8 - 0x633cc */ + volatile u_int32_t chbt_rxdac_long_shift; /* 0x633cc - 0x633d0 */ + volatile u_int32_t chbt_cmac_results_i; /* 0x633d0 - 0x633d4 */ + volatile u_int32_t chbt_cmac_results_q; /* 0x633d4 - 0x633d8 */ + /* Aphrodite-end */ +}; + +struct pcie_phy_reg_csr { + volatile char pad__0[0x18c00]; /* 0x0 - 0x18c00 */ + volatile u_int32_t pcie_phy_reg_1; /* 0x18c00 - 0x18c04 */ + volatile u_int32_t pcie_phy_reg_2; /* 0x18c04 - 0x18c08 */ + volatile u_int32_t pcie_phy_reg_3; /* 0x18c08 - 0x18c0c */ +}; + +struct pmu_reg { + volatile char pad__0[0x16c40]; /* 0x0 - 0x16c40 */ + volatile u_int32_t ch0_PMU1; /* 0x16c40 - 0x16c44 */ + volatile u_int32_t ch0_PMU2; /* 0x16c44 - 0x16c48 */ +}; + +struct wlan_coex_reg { + volatile char pad__0[0x1800]; /* 0x0 - 0x1800 */ + volatile u_int32_t MCI_COMMAND0; /* 0x1800 - 0x1804 */ + volatile u_int32_t MCI_COMMAND1; /* 0x1804 - 0x1808 */ + volatile u_int32_t MCI_COMMAND2; /* 0x1808 - 0x180c */ + volatile u_int32_t MCI_RX_CTRL; /* 0x180c - 0x1810 */ + volatile u_int32_t MCI_TX_CTRL; /* 0x1810 - 0x1814 */ + volatile u_int32_t MCI_MSG_ATTRIBUTES_TABLE; /* 0x1814 - 0x1818 */ + volatile u_int32_t MCI_SCHD_TABLE_0; /* 0x1818 - 0x181c */ + volatile u_int32_t MCI_SCHD_TABLE_1; /* 0x181c - 0x1820 */ + volatile u_int32_t MCI_GPM_0; /* 0x1820 - 0x1824 */ + volatile u_int32_t MCI_GPM_1; /* 0x1824 - 0x1828 */ + volatile u_int32_t MCI_INTERRUPT_RAW; /* 0x1828 - 0x182c */ + volatile u_int32_t MCI_INTERRUPT_EN; /* 0x182c - 0x1830 */ + volatile u_int32_t MCI_REMOTE_CPU_INT; /* 0x1830 - 0x1834 */ + volatile u_int32_t MCI_REMOTE_CPU_INT_EN; /* 0x1834 - 0x1838 */ + volatile u_int32_t MCI_INTERRUPT_RX_MSG_RAW; /* 0x1838 - 0x183c */ + volatile u_int32_t MCI_INTERRUPT_RX_MSG_EN; /* 0x183c - 0x1840 */ + volatile u_int32_t MCI_CPU_INT; /* 0x1840 - 0x1844 */ + volatile u_int32_t MCI_RX_STATUS; /* 0x1844 - 0x1848 */ + volatile u_int32_t MCI_CONT_STATUS; /* 0x1848 - 0x184c */ + volatile u_int32_t MCI_BT_PRI0; /* 0x184c - 0x1850 */ + volatile u_int32_t MCI_BT_PRI1; /* 0x1850 - 0x1854 */ + volatile u_int32_t MCI_BT_PRI2; /* 0x1854 - 0x1858 */ + volatile u_int32_t MCI_BT_PRI3; /* 0x1858 - 0x185c */ + volatile u_int32_t MCI_BT_PRI; /* 0x185c - 0x1860 */ + volatile u_int32_t MCI_WL_FREQ0; /* 0x1860 - 0x1864 */ + volatile u_int32_t MCI_WL_FREQ1; /* 0x1864 - 0x1868 */ + volatile u_int32_t MCI_WL_FREQ2; /* 0x1868 - 0x186c */ + volatile u_int32_t MCI_GAIN; /* 0x186c - 0x1870 */ + volatile u_int32_t MCI_WBTIMER1; /* 0x1870 - 0x1874 */ + volatile u_int32_t MCI_WBTIMER2; /* 0x1874 - 0x1878 */ + volatile u_int32_t MCI_WBTIMER3; /* 0x1878 - 0x187c */ + volatile u_int32_t MCI_WBTIMER4; /* 0x187c - 0x1880 */ + volatile u_int32_t MCI_MAXGAIN; /* 0x1880 - 0x1884 */ + volatile u_int32_t MCI_HW_SCHD_TBL_CTL; /* 0x1884 - 0x1888 */ + volatile u_int32_t MCI_HW_SCHD_TBL_D0; /* 0x1888 - 0x188c */ + volatile u_int32_t MCI_HW_SCHD_TBL_D1; /* 0x188c - 0x1890 */ + volatile u_int32_t MCI_HW_SCHD_TBL_D2; /* 0x1890 - 0x1894 */ + volatile u_int32_t MCI_HW_SCHD_TBL_D3; /* 0x1894 - 0x1898 */ + volatile u_int32_t MCI_TX_PAYLOAD0; /* 0x1898 - 0x189c */ + volatile u_int32_t MCI_TX_PAYLOAD1; /* 0x189c - 0x18a0 */ + volatile u_int32_t MCI_TX_PAYLOAD2; /* 0x18a0 - 0x18a4 */ + volatile u_int32_t MCI_TX_PAYLOAD3; /* 0x18a4 - 0x18a8 */ + volatile u_int32_t BTCOEX_WBTIMER; /* 0x18a8 - 0x18ac */ + volatile u_int32_t BTCOEX_CTRL; /* 0x18ac - 0x18b0 */ + volatile u_int32_t BTCOEX_WL_WEIGHTS0; /* 0x18b0 - 0x18b4 */ + volatile u_int32_t BTCOEX_WL_WEIGHTS1; /* 0x18b4 - 0x18b8 */ + volatile u_int32_t BTCOEX_WL_WEIGHTS2; /* 0x18b8 - 0x18bc */ + volatile u_int32_t BTCOEX_WL_WEIGHTS3; /* 0x18bc - 0x18c0 */ + volatile u_int32_t BTCOEX_MAX_TXPWR[8]; /* 0x18c0 - 0x18e0 */ + volatile char pad__1[0x60]; /* 0x18e0 - 0x1940 */ + volatile u_int32_t BTCOEX_WL_LNA; /* 0x1940 - 0x1944 */ + volatile u_int32_t BTCOEX_RFGAIN_CTRL; /* 0x1944 - 0x1948 */ + volatile u_int32_t BTCOEX_CTRL2; /* 0x1948 - 0x194c */ + volatile u_int32_t BTCOEX_RC; /* 0x194c - 0x1950 */ + volatile u_int32_t BTCOEX_MAX_RFGAIN[16]; /* 0x1950 - 0x1990 */ + volatile char pad__2[0xc0]; /* 0x1990 - 0x1a50 */ + volatile u_int32_t BTCOEX_DBG; /* 0x1a50 - 0x1a54 */ + volatile u_int32_t MCI_LAST_HW_MSG_HDR; /* 0x1a54 - 0x1a58 */ + volatile u_int32_t MCI_LAST_HW_MSG_BDY; /* 0x1a58 - 0x1a5c */ + volatile u_int32_t MCI_SCHD_TABLE_2; /* 0x1a5c - 0x1a60 */ + volatile u_int32_t BTCOEX_CTRL3; /* 0x1a60 - 0x1a64 */ + /* Aphrodite-start */ + volatile u_int32_t BTCOEX_WL_LNADIV; /* 0x1a64 - 0x1a68 */ + volatile u_int32_t BTCOEX_TXTX_RANGE; /* 0x1a68 - 0x1a6c */ + volatile u_int32_t MCI_INTERRUPT_1_RAW; /* 0x1a6c - 0x1a70 */ + volatile u_int32_t MCI_INTERRUPT_1_EN; /* 0x1a70 - 0x1a74 */ + volatile u_int32_t MCI_EV_MISC; /* 0x1a74 - 0x1a78 */ + volatile u_int32_t MCI_DBG_CNT_CTRL; /* 0x1a78 - 0x1a7c */ + volatile u_int32_t MCI_DBG_CNT1; /* 0x1a7c - 0x1a80 */ + volatile u_int32_t MCI_DBG_CNT2; /* 0x1a80 - 0x1a84 */ + volatile u_int32_t MCI_DBG_CNT3; /* 0x1a84 - 0x1a88 */ + volatile u_int32_t MCI_DBG_CNT4; /* 0x1a88 - 0x1a8c */ + volatile u_int32_t MCI_DBG_CNT5; /* 0x1a8c - 0x1a90 */ + volatile u_int32_t MCI_DBG_CNT6; /* 0x1a90 - 0x1a94 */ + volatile u_int32_t MCI_DBG_CNT7; /* 0x1a94 - 0x1a98 */ + volatile u_int32_t MCI_DBG_CNT8; /* 0x1a98 - 0x1a9c */ + volatile u_int32_t MCI_DBG_CNT9; /* 0x1a9c - 0x1aa0 */ + volatile u_int32_t MCI_DBG_CNT10; /* 0x1aa0 - 0x1aa4 */ + volatile u_int32_t MCI_DBG_CNT11; /* 0x1aa4 - 0x1aa8 */ + volatile u_int32_t MCI_DBG_CNT12; /* 0x1aa8 - 0x1aac */ + volatile u_int32_t MCI_DBG_CNT13; /* 0x1aac - 0x1ab0 */ + volatile u_int32_t MCI_DBG_CNT14; /* 0x1ab0 - 0x1ab4 */ + volatile u_int32_t MCI_DBG_CNT15; /* 0x1ab4 - 0x1ab8 */ + volatile u_int32_t MCI_DBG_CNT16; /* 0x1ab8 - 0x1abc */ + volatile u_int32_t MCI_DBG_CNT17; /* 0x1abc - 0x1ac0 */ + volatile u_int32_t MCI_DBG_CNT18; /* 0x1ac0 - 0x1ac4 */ + volatile u_int32_t MCI_DBG_CNT19; /* 0x1ac4 - 0x1ac8 */ + /* Aphrodite-end */ +}; + +struct uart1_reg_csr { + volatile u_int32_t UART_DATA; /* 0x0 - 0x4 */ + volatile u_int32_t UART_CONTROL; /* 0x4 - 0x8 */ + volatile u_int32_t UART_CLKDIV; /* 0x8 - 0xc */ + volatile u_int32_t UART_INT; /* 0xc - 0x10 */ + volatile u_int32_t UART_INT_EN; /* 0x10 - 0x14 */ +}; + +struct wlan_bt_glb_reg_pcie { + volatile char pad__0[0x20000]; /* 0x0 - 0x20000 */ + volatile u_int32_t GLB_GPIO_CONTROL; /* 0x20000 - 0x20004 */ + volatile u_int32_t GLB_WLAN_WOW_STATUS; /* 0x20004 - 0x20008 */ + volatile u_int32_t GLB_WLAN_WOW_ENABLE; /* 0x20008 - 0x2000c */ + volatile u_int32_t GLB_EMB_CPU_WOW_STATUS; /* 0x2000c - 0x20010 */ + volatile u_int32_t GLB_EMB_CPU_WOW_ENABLE; /* 0x20010 - 0x20014 */ + volatile u_int32_t GLB_MBOX_CONTROL_STATUS; /* 0x20014 - 0x20018 */ + volatile u_int32_t GLB_SW_WOW_CONTROL; /* 0x20018 - 0x2001c */ + volatile u_int32_t GLB_APB_TIMEOUT; /* 0x2001c - 0x20020 */ + volatile u_int32_t GLB_OTP_LDO_CONTROL; /* 0x20020 - 0x20024 */ + volatile u_int32_t GLB_OTP_LDO_POWER_GOOD; /* 0x20024 - 0x20028 */ + volatile u_int32_t GLB_OTP_LDO_STATUS; /* 0x20028 - 0x2002c */ + volatile u_int32_t GLB_SWREG_DISCONT_MODE; /* 0x2002c - 0x20030 */ + volatile u_int32_t GLB_BT_GPIO_REMAP_OUT_CONTROL0; + /* 0x20030 - 0x20034 */ + volatile u_int32_t GLB_BT_GPIO_REMAP_OUT_CONTROL1; + /* 0x20034 - 0x20038 */ + volatile u_int32_t GLB_BT_GPIO_REMAP_IN_CONTROL0; + /* 0x20038 - 0x2003c */ + volatile u_int32_t GLB_BT_GPIO_REMAP_IN_CONTROL1; + /* 0x2003c - 0x20040 */ + volatile u_int32_t GLB_BT_GPIO_REMAP_IN_CONTROL2; + /* 0x20040 - 0x20044 */ + union { + struct { + volatile char pad__1[0xc]; /* 0x20044 - 0x20050 */ + volatile u_int32_t GLB_SCRATCH[16]; /* 0x20050 - 0x20090 */ + volatile char pad__2[0x370]; /* 0x20090 - 0x20400 */ + } Jupiter_10; + struct { + volatile u_int32_t GLB_CONTROL; /* 0x20044 - 0x20048 */ + volatile u_int32_t GLB_STATUS; /* 0x20048 - 0x2004c */ + volatile u_int32_t GLB_SCRATCH[16]; /* 0x2004c - 0x2008c */ + volatile char pad__1[0x354]; /* 0x2008c - 0x203e0 */ + struct uart1_reg_csr shared_uart1; /* 0x203e0 - 0x203f4 */ + volatile char pad__2[0xc]; /* 0x203f4 - 0x20400 */ + } Jupiter_20; + struct { + volatile u_int32_t GLB_CONTROL; /* 0x20044 - 0x20048 */ + volatile u_int32_t GLB_STATUS; /* 0x20048 - 0x2004c */ + volatile char pad__1[0x4]; /* 0x2004c - 0x20050 */ + volatile u_int32_t GLB_SCRATCH[16]; /* 0x20050 - 0x20090 */ + volatile char pad__2[0x70]; /* 0x20090 - 0x20100 */ + volatile u_int32_t PLLOSC_CTRL; /* 0x20100 - 0x20104 */ + volatile u_int32_t PLLOSC_CFG; /* 0x20104 - 0x20108 */ + volatile char pad__3[0x4]; /* 0x20108 - 0x2010c */ + volatile u_int32_t INNOP_MEM_CONTROL; /* 0x2010c - 0x20110 */ + volatile u_int32_t USB_CONFIG; /* 0x20110 - 0x20114 */ + volatile u_int32_t USB_SPARE32; /* 0x20114 - 0x20118 */ + volatile u_int32_t PCIE_AHB_BRIDGE_CFG; /* 0x20118 - 0x2011c */ + volatile u_int32_t PCIE_AHB_BRIDGE_CTRL; /* 0x2011c - 0x20120 */ + volatile u_int32_t OPTIONAL_CTL_REG; /* 0x20120 - 0x20124 */ + volatile u_int32_t PCIE_PWR_CTRL_REG; /* 0x20124 - 0x20128 */ + volatile char pad__4[0x4]; /* 0x20128 - 0x2012c */ + volatile u_int32_t USBDEV_CLK_CTL_REG; /* 0x2012c - 0x20130 */ + volatile u_int32_t UHOST_DEBUG_FSM; /* 0x20130 - 0x20134 */ + volatile u_int32_t BRIDGE_DEBUG_FSM; /* 0x20134 - 0x20138 */ + volatile u_int32_t BRIDGE_DEBUG_PTR; /* 0x20138 - 0x2013c */ + volatile u_int32_t BRIDGE_DEBUG_CLIENT_LOG0; /* 0x2013c - 0x20140 */ + volatile u_int32_t BRIDGE_DEBUG_CLIENT_LOG1; /* 0x20140 - 0x20144 */ + volatile u_int32_t BRIDGE_DEBUG_CLIENT_LOG2; /* 0x20144 - 0x20148 */ + volatile char pad__5[0x298]; /* 0x20148 - 0x203e0 */ + volatile u_int32_t GLB_UART[8]; /* 0x203e0 - 0x20400 */ + } Aphrodite; + } overlay_0x20044; +}; + +struct jupiter_reg_map__rtc_reg_csr { + volatile u_int32_t RESET_CONTROL; /* 0x0 - 0x4 */ + volatile u_int32_t PLL_SETTLE; /* 0x4 - 0x8 */ + volatile u_int32_t VDD_SETTLE; /* 0x8 - 0xc */ + volatile u_int32_t PWR_CONTROL; /* 0xc - 0x10 */ + volatile u_int32_t XTAL_SETTLE; /* 0x10 - 0x14 */ + volatile u_int32_t RTC_CLOCK; /* 0x14 - 0x18 */ + volatile u_int32_t CORE_CLOCK; /* 0x18 - 0x1c */ + volatile u_int32_t CLKBOOT; /* 0x1c - 0x20 */ + volatile u_int32_t UART_CLOCK; /* 0x20 - 0x24 */ + volatile u_int32_t SI_CLOCK; /* 0x24 - 0x28 */ + volatile u_int32_t CLOCK_CONTROL; /* 0x28 - 0x2c */ + volatile u_int32_t WDT_CONTROL; /* 0x2c - 0x30 */ + volatile u_int32_t WDT_STATUS; /* 0x30 - 0x34 */ + volatile u_int32_t WDT; /* 0x34 - 0x38 */ + volatile u_int32_t WDT_COUNT; /* 0x38 - 0x3c */ + volatile u_int32_t WDT_RESET; /* 0x3c - 0x40 */ + volatile u_int32_t RTC_INT_STATUS; /* 0x40 - 0x44 */ + volatile u_int32_t INT_SRC_MAPPING; /* 0x44 - 0x48 */ + volatile u_int32_t UART_SI_GPIO_INT_STATUS; /* 0x48 - 0x4c */ + volatile u_int32_t LF_TIMER0; /* 0x4c - 0x50 */ + volatile u_int32_t LF_TIMER_COUNT0; /* 0x50 - 0x54 */ + volatile u_int32_t LF_TIMER_CONTROL0; /* 0x54 - 0x58 */ + volatile u_int32_t LF_TIMER_STATUS0; /* 0x58 - 0x5c */ + volatile u_int32_t LF_TIMER1; /* 0x5c - 0x60 */ + volatile u_int32_t LF_TIMER_COUNT1; /* 0x60 - 0x64 */ + volatile u_int32_t LF_TIMER_CONTROL1; /* 0x64 - 0x68 */ + volatile u_int32_t LF_TIMER_STATUS1; /* 0x68 - 0x6c */ + volatile u_int32_t RESET_CAUSE; /* 0x6c - 0x70 */ + volatile u_int32_t SYSTEM_SLEEP; /* 0x70 - 0x74 */ + volatile u_int32_t KEEP_AWAKE; /* 0x74 - 0x78 */ + volatile u_int32_t LPO_CAL; /* 0x78 - 0x7c */ + volatile u_int32_t OBS_CLOCK; /* 0x7c - 0x80 */ + volatile u_int32_t CHIP_REV; /* 0x80 - 0x84 */ + volatile u_int32_t PWR_ON_TIME; /* 0x84 - 0x88 */ + volatile u_int32_t PWD_TIME; /* 0x88 - 0x8c */ + volatile u_int32_t USB_SUSPEND_POWER_REG; /* 0x8c - 0x90 */ + volatile u_int32_t USB_SUSPEND_WAKEUP_COUNTER_REG; + /* 0x90 - 0x94 */ + volatile u_int32_t LPO_STEP_CFG; /* 0x94 - 0x98 */ + volatile u_int32_t LPO_FAST_CYL; /* 0x98 - 0x9c */ + volatile u_int32_t LPO_LPO1; /* 0x9c - 0xa0 */ + volatile u_int32_t LPO_LPO2; /* 0xa0 - 0xa4 */ + volatile u_int32_t LPO_INT_RAW; /* 0xa4 - 0xa8 */ + volatile u_int32_t LPO_N1TARGET; /* 0xa8 - 0xac */ + volatile u_int32_t LPO_N2TARGET; /* 0xac - 0xb0 */ + volatile u_int32_t LPO_DN1_MULT; /* 0xb0 - 0xb4 */ + volatile u_int32_t LPO_DN2_MULT; /* 0xb4 - 0xb8 */ + volatile u_int32_t LPO_NTARGET_MIN; /* 0xb8 - 0xbc */ + volatile u_int32_t LPO_NTARGET_MAX; /* 0xbc - 0xc0 */ + volatile u_int32_t LPO_N1TARGET_DEBUG; /* 0xc0 - 0xc4 */ + volatile u_int32_t LPO_N2TARGET_DEBUG; /* 0xc4 - 0xc8 */ + volatile u_int32_t OTP; /* 0xc8 - 0xcc */ + volatile u_int32_t OTP_STATUS; /* 0xcc - 0xd0 */ + volatile u_int32_t USB_PHY_TEST; /* 0xd0 - 0xd4 */ + volatile u_int32_t USB_PHY_CONFIG; /* 0xd4 - 0xd8 */ + volatile u_int32_t ADDAC_CLOCK_PHASE; /* 0xd8 - 0xdc */ + volatile u_int32_t THERM_CONTROL; /* 0xdc - 0xe0 */ + volatile u_int32_t THERM_TRIGGER_INTERVAL1; /* 0xe0 - 0xe4 */ + volatile u_int32_t THERM_TRIGGER_INTERVAL2; /* 0xe4 - 0xe8 */ + volatile u_int32_t THERM_CORRECTION; /* 0xe8 - 0xec */ + volatile u_int32_t THERM_CORRECTION_VALUE1; /* 0xec - 0xf0 */ + volatile u_int32_t THERM_CORRECTION_VALUE2; /* 0xf0 - 0xf4 */ + volatile u_int32_t PLL_CONTROL; /* 0xf4 - 0xf8 */ + volatile u_int32_t VDD12D_SENSE; /* 0xf8 - 0xfc */ + volatile u_int32_t RBIAS; /* 0xfc - 0x100 */ + volatile u_int32_t THERM_CONTROL_VAL; /* 0x100 - 0x104 */ + volatile u_int32_t PLL_OSC_CONTROL; /* 0x104 - 0x108 */ + volatile u_int32_t AHB_ERR_INT; /* 0x108 - 0x10c */ + volatile u_int32_t INT_P2_EN; /* 0x10c - 0x110 */ + volatile u_int32_t XTAL_CLOCK; /* 0x110 - 0x114 */ + volatile u_int32_t CHIP_MODES; /* 0x114 - 0x118 */ + volatile u_int32_t XTAL_FREQ; /* 0x118 - 0x11c */ + volatile u_int32_t DEBUGGER_RESET; /* 0x11c - 0x120 */ + volatile u_int32_t LPO_3_2K_CLK; /* 0x120 - 0x124 */ + volatile u_int32_t LPO1_CLK_DEBUG; /* 0x124 - 0x128 */ + volatile u_int32_t LPO2_CLK_DEBUG; /* 0x128 - 0x12c */ + volatile u_int32_t ADDR_CHECK; /* 0x12c - 0x130 */ + volatile u_int32_t RTC_DUMMY; /* 0x130 - 0x134 */ +}; + +struct jupiter_reg_map__vmc_reg_csr { + volatile u_int32_t BANK0_ADDR; /* 0x0 - 0x4 */ + volatile u_int32_t BANK1_ADDR; /* 0x4 - 0x8 */ + volatile u_int32_t BANK_CONFIG; /* 0x8 - 0xc */ + volatile u_int32_t MC_BCAM_CONFLICT_ERROR; /* 0xc - 0x10 */ + volatile char pad__0[0x10]; /* 0x10 - 0x20 */ + volatile u_int32_t MC_BCAM_COMPARE[128]; /* 0x20 - 0x220 */ + volatile u_int32_t MC_BCAM_VALID[128]; /* 0x220 - 0x420 */ + volatile u_int32_t MC_BCAM_TARGET[128]; /* 0x420 - 0x620 */ +}; + +struct jupiter_reg_map__apb_map_csr__uart_reg_csr { + volatile u_int32_t UART_DATA; /* 0x0 - 0x4 */ + volatile u_int32_t UART_CONTROL; /* 0x4 - 0x8 */ + volatile u_int32_t UART_CLKDIV; /* 0x8 - 0xc */ + volatile u_int32_t UART_INT; /* 0xc - 0x10 */ + volatile u_int32_t UART_INT_EN; /* 0x10 - 0x14 */ +}; + +struct jupiter_reg_map__si_reg_csr { + volatile u_int32_t SI_CONFIG; /* 0x0 - 0x4 */ + volatile u_int32_t SI_CS; /* 0x4 - 0x8 */ + volatile u_int32_t SI_TX_DATA0; /* 0x8 - 0xc */ + volatile u_int32_t SI_TX_DATA1; /* 0xc - 0x10 */ + volatile u_int32_t SI_RX_DATA0; /* 0x10 - 0x14 */ + volatile u_int32_t SI_RX_DATA1; /* 0x14 - 0x18 */ +}; + +struct jupiter_reg_map__gpio_reg_csr { + volatile u_int32_t GPIO_OUT; /* 0x0 - 0x4 */ + volatile u_int32_t GPIO_OUT_W1TS; /* 0x4 - 0x8 */ + volatile u_int32_t GPIO_OUT_W1TC; /* 0x8 - 0xc */ + volatile u_int32_t GPIO_ENABLE; /* 0xc - 0x10 */ + volatile u_int32_t GPIO_ENABLE_W1TS; /* 0x10 - 0x14 */ + volatile u_int32_t GPIO_ENABLE_W1TC; /* 0x14 - 0x18 */ + volatile u_int32_t GPIO_IN; /* 0x18 - 0x1c */ + volatile u_int32_t GPIO_STATUS; /* 0x1c - 0x20 */ + volatile u_int32_t GPIO_STATUS_W1TS; /* 0x20 - 0x24 */ + volatile u_int32_t GPIO_STATUS_W1TC; /* 0x24 - 0x28 */ + volatile u_int32_t GPIO_INT_ENABLE; /* 0x28 - 0x2c */ + volatile u_int32_t GPIO_INT_ENABLE_W1TS; /* 0x2c - 0x30 */ + volatile u_int32_t GPIO_INT_ENABLE_W1TC; /* 0x30 - 0x34 */ + volatile u_int32_t GPIO_PIN0; /* 0x34 - 0x38 */ + volatile u_int32_t GPIO_PIN1; /* 0x38 - 0x3c */ + volatile u_int32_t GPIO_PIN2; /* 0x3c - 0x40 */ + volatile u_int32_t GPIO_PIN3; /* 0x40 - 0x44 */ + volatile u_int32_t GPIO_PIN4; /* 0x44 - 0x48 */ + volatile u_int32_t GPIO_PIN5; /* 0x48 - 0x4c */ + volatile u_int32_t GPIO_PIN6; /* 0x4c - 0x50 */ + volatile u_int32_t GPIO_PIN7; /* 0x50 - 0x54 */ + volatile u_int32_t GPIO_PIN8; /* 0x54 - 0x58 */ + volatile u_int32_t GPIO_PIN9; /* 0x58 - 0x5c */ + volatile u_int32_t GPIO_PIN10; /* 0x5c - 0x60 */ + volatile u_int32_t GPIO_PIN11; /* 0x60 - 0x64 */ + volatile u_int32_t GPIO_PIN12; /* 0x64 - 0x68 */ + volatile u_int32_t GPIO_PIN13; /* 0x68 - 0x6c */ + volatile u_int32_t GPIO_PIN14; /* 0x6c - 0x70 */ + volatile u_int32_t GPIO_PIN15; /* 0x70 - 0x74 */ + volatile u_int32_t GPIO_PIN16; /* 0x74 - 0x78 */ + volatile u_int32_t GPIO_PIN17; /* 0x78 - 0x7c */ + volatile u_int32_t GPIO_PIN18; /* 0x7c - 0x80 */ + volatile u_int32_t GPIO_PIN19; /* 0x80 - 0x84 */ + volatile u_int32_t SIGMA_DELTA; /* 0x84 - 0x88 */ + volatile u_int32_t DEBUG_CONTROL; /* 0x88 - 0x8c */ + volatile u_int32_t DEBUG_INPUT_SEL; /* 0x8c - 0x90 */ + volatile u_int32_t DEBUG_PIN_SEL; /* 0x90 - 0x94 */ + volatile u_int32_t DEBUG_OBS_BUS; /* 0x94 - 0x98 */ +}; + +struct jupiter_reg_map__mbox_reg_csr { + volatile u_int32_t MBOX_FIFO[4]; /* 0x0 - 0x10 */ + volatile u_int32_t MBOX_FIFO_STATUS; /* 0x10 - 0x14 */ + volatile u_int32_t MBOX_DMA_POLICY; /* 0x14 - 0x18 */ + volatile u_int32_t MBOX0_DMA_RX_DESCRIPTOR_BASE; + /* 0x18 - 0x1c */ + volatile u_int32_t MBOX0_DMA_RX_CONTROL; /* 0x1c - 0x20 */ + volatile u_int32_t MBOX0_DMA_TX_DESCRIPTOR_BASE; + /* 0x20 - 0x24 */ + volatile u_int32_t MBOX0_DMA_TX_CONTROL; /* 0x24 - 0x28 */ + volatile u_int32_t MBOX1_DMA_RX_DESCRIPTOR_BASE; + /* 0x28 - 0x2c */ + volatile u_int32_t MBOX1_DMA_RX_CONTROL; /* 0x2c - 0x30 */ + volatile u_int32_t MBOX1_DMA_TX_DESCRIPTOR_BASE; + /* 0x30 - 0x34 */ + volatile u_int32_t MBOX1_DMA_TX_CONTROL; /* 0x34 - 0x38 */ + volatile u_int32_t MBOX2_DMA_RX_DESCRIPTOR_BASE; + /* 0x38 - 0x3c */ + volatile u_int32_t MBOX2_DMA_RX_CONTROL; /* 0x3c - 0x40 */ + volatile u_int32_t MBOX2_DMA_TX_DESCRIPTOR_BASE; + /* 0x40 - 0x44 */ + volatile u_int32_t MBOX2_DMA_TX_CONTROL; /* 0x44 - 0x48 */ + volatile u_int32_t MBOX3_DMA_RX_DESCRIPTOR_BASE; + /* 0x48 - 0x4c */ + volatile u_int32_t MBOX3_DMA_RX_CONTROL; /* 0x4c - 0x50 */ + volatile u_int32_t MBOX3_DMA_TX_DESCRIPTOR_BASE; + /* 0x50 - 0x54 */ + volatile u_int32_t MBOX3_DMA_TX_CONTROL; /* 0x54 - 0x58 */ + volatile u_int32_t FIFO_TIMEOUT; /* 0x58 - 0x5c */ + volatile u_int32_t MBOX_INT_STATUS; /* 0x5c - 0x60 */ + volatile u_int32_t MBOX_INT_ENABLE; /* 0x60 - 0x64 */ + volatile u_int32_t MBOX_DEBUG; /* 0x64 - 0x68 */ + volatile u_int32_t MBOX_FIFO_RESET; /* 0x68 - 0x6c */ + volatile char pad__0[0x4]; /* 0x6c - 0x70 */ + volatile u_int32_t MBOX_TXFIFO_POP[4]; /* 0x70 - 0x80 */ + volatile u_int32_t HCI_FRAMER; /* 0x80 - 0x84 */ + volatile u_int32_t STEREO_CONFIG; /* 0x84 - 0x88 */ + volatile u_int32_t STEREO_CONFIG1; /* 0x88 - 0x8c */ + volatile u_int32_t STEREO_CONFIG2; /* 0x8c - 0x90 */ + volatile u_int32_t STEREO_VOLUME; /* 0x90 - 0x94 */ + volatile u_int32_t STEREO_DEBUG; /* 0x94 - 0x98 */ + volatile u_int32_t STEREO_CONFIG3; /* 0x98 - 0x9c */ +}; + +struct jupiter_reg_map__lc_dma_reg_csr { + volatile u_int32_t LC_DMA_MASTER; /* 0x0 - 0x4 */ + volatile u_int32_t LC_DMA_TX_CONTROL; /* 0x4 - 0x8 */ + volatile u_int32_t LC_DMA_RX_CONTROL; /* 0x8 - 0xc */ + volatile u_int32_t LC_DMA_TX_HW; /* 0xc - 0x10 */ + volatile u_int32_t LC_DMA_RX_HW; /* 0x10 - 0x14 */ + volatile u_int32_t LC_DMA_INT_STATUS; /* 0x14 - 0x18 */ + volatile u_int32_t LC_DMA_TX_STATUS; /* 0x18 - 0x1c */ + volatile u_int32_t LC_DMA_TX_STATUS_W1TC; /* 0x1c - 0x20 */ + volatile u_int32_t LC_DMA_TX_ENABLE; /* 0x20 - 0x24 */ + volatile u_int32_t LC_DMA_RX_STATUS; /* 0x24 - 0x28 */ + volatile u_int32_t LC_DMA_RX_STATUS_W1TC; /* 0x28 - 0x2c */ + volatile u_int32_t LC_DMA_RX_ENABLE; /* 0x2c - 0x30 */ + volatile u_int32_t LC_DMA_DEBUG; /* 0x30 - 0x34 */ +}; + +struct jupiter_reg_map__lc_reg_csr { + volatile u_int32_t LC_DEV_PARAM_DAC_L; /* 0x0 - 0x4 */ + volatile u_int32_t LC_DEV_PARAM_DAC_U; /* 0x4 - 0x8 */ + volatile u_int32_t LC_DEV_PARAM_BD_ADDR; /* 0x8 - 0xc */ + volatile u_int32_t LC_DEV_PARAM_FHS; /* 0xc - 0x10 */ + volatile u_int32_t LC_DEV_PARAM_CTL; /* 0x10 - 0x14 */ + volatile u_int32_t LC_DEV_PARAM_TIMING; /* 0x14 - 0x18 */ + volatile u_int32_t LC_DEV_PARAM_TIMING_1; /* 0x18 - 0x1c */ + volatile u_int32_t LC_MISC; /* 0x1c - 0x20 */ + volatile u_int32_t LC_DEV_PARAM_COMMAND1; /* 0x20 - 0x24 */ + volatile u_int32_t LC_DEV_PARAM_COMMAND2; /* 0x24 - 0x28 */ + volatile u_int32_t LC_DEV_PARAM_COMMAND3; /* 0x28 - 0x2c */ + volatile u_int32_t LC_DEV_PARAM_COMMAND4; /* 0x2c - 0x30 */ + volatile u_int32_t LC_DEV_PARAM_COMMAND5; /* 0x30 - 0x34 */ + volatile u_int32_t LC_DEV_PARAM_COMMAND6; /* 0x34 - 0x38 */ + volatile u_int32_t LC_DEV_PARAM_COMMAND7; /* 0x38 - 0x3c */ + volatile u_int32_t LC_DEV_PARAM_COMMAND8; /* 0x3c - 0x40 */ + volatile u_int32_t LC_DEV_PARAM_AC1_L; /* 0x40 - 0x44 */ + volatile u_int32_t LC_DEV_PARAM_AC1_U; /* 0x44 - 0x48 */ + volatile u_int32_t LC_DEV_PARAM_AC2_L; /* 0x48 - 0x4c */ + volatile u_int32_t LC_DEV_PARAM_AC2_U; /* 0x4c - 0x50 */ + volatile u_int32_t LC_DEV_PARAM_CLOCK_OFFSET; /* 0x50 - 0x54 */ + volatile u_int32_t LC_FREQUENCY; /* 0x54 - 0x58 */ + volatile u_int32_t LC_CH_ASSESS_1; /* 0x58 - 0x5c */ + volatile u_int32_t LC_CH_ASSESS_2; /* 0x5c - 0x60 */ + volatile u_int32_t LC_DEV_PARAM_ENCRYPTION_KEY0; + /* 0x60 - 0x64 */ + volatile u_int32_t LC_DEV_PARAM_ENCRYPTION_KEY1; + /* 0x64 - 0x68 */ + volatile u_int32_t LC_DEV_PARAM_ENCRYPTION_KEY2; + /* 0x68 - 0x6c */ + volatile u_int32_t LC_DEV_PARAM_ENCRYPTION_KEY3; + /* 0x6c - 0x70 */ + volatile u_int32_t LC_DEV_PARAM_TX_CONTROL; /* 0x70 - 0x74 */ + volatile u_int32_t LC_DEV_PARAM_RX_CONTROL; /* 0x74 - 0x78 */ + volatile u_int32_t LC_DEV_PARAM_RX_STATUS1; /* 0x78 - 0x7c */ + volatile u_int32_t LC_DEV_PARAM_RX_STATUS2; /* 0x7c - 0x80 */ + volatile char pad__0[0x4]; /* 0x80 - 0x84 */ + volatile u_int32_t LC_BT_CLOCK0; /* 0x84 - 0x88 */ + volatile u_int32_t LC_BT_CLOCK1; /* 0x88 - 0x8c */ + volatile u_int32_t LC_BT_CLOCK2; /* 0x8c - 0x90 */ + volatile u_int32_t LC_BT_CLOCK3; /* 0x90 - 0x94 */ + volatile u_int32_t LC_SYM_TIME0; /* 0x94 - 0x98 */ + volatile u_int32_t LC_SYM_TIME1; /* 0x98 - 0x9c */ + volatile u_int32_t LC_SYM_TIME2; /* 0x9c - 0xa0 */ + volatile u_int32_t LC_SYM_TIME3; /* 0xa0 - 0xa4 */ + volatile char pad__1[0x4]; /* 0xa4 - 0xa8 */ + volatile u_int32_t LC_ABORT; /* 0xa8 - 0xac */ + volatile u_int32_t LC_PRBS; /* 0xac - 0xb0 */ + volatile u_int32_t LC_LAST_CORR_HECOK; /* 0xb0 - 0xb4 */ + volatile char pad__2[0x4c]; /* 0xb4 - 0x100 */ + volatile u_int32_t LC_SM_AFH_TABLE[24]; /* 0x100 - 0x160 */ + volatile char pad__3[0x20]; /* 0x160 - 0x180 */ + volatile u_int32_t LC_SM_AFH_BITMAP_0; /* 0x180 - 0x184 */ + volatile u_int32_t LC_SM_AFH_BITMAP_1; /* 0x184 - 0x188 */ + volatile u_int32_t LC_SM_AFH_BITMAP_2; /* 0x188 - 0x18c */ + volatile u_int32_t LC_STAT0; /* 0x18c - 0x190 */ + volatile u_int32_t LC_STAT1; /* 0x190 - 0x194 */ + volatile u_int32_t LC_STAT2; /* 0x194 - 0x198 */ + volatile u_int32_t LC_STAT3; /* 0x198 - 0x19c */ + volatile u_int32_t LC_STAT4; /* 0x19c - 0x1a0 */ + volatile u_int32_t LC_STAT5; /* 0x1a0 - 0x1a4 */ + volatile u_int32_t LC_STAT6; /* 0x1a4 - 0x1a8 */ + volatile u_int32_t LC_STAT7; /* 0x1a8 - 0x1ac */ + volatile u_int32_t LC_STAT8; /* 0x1ac - 0x1b0 */ + volatile u_int32_t LC_STAT9; /* 0x1b0 - 0x1b4 */ + volatile char pad__4[0x14c]; /* 0x1b4 - 0x300 */ + volatile u_int32_t LC_INTERRUPT_RAW; /* 0x300 - 0x304 */ + volatile u_int32_t LC_INTERRUPT_EN; /* 0x304 - 0x308 */ + volatile u_int32_t LC_INTERRUPT_RX_STATUS; /* 0x308 - 0x30c */ + volatile u_int32_t LC_AUDIO_DATAPATH; /* 0x30c - 0x310 */ + volatile u_int32_t LC_VOICE_CHAN0; /* 0x310 - 0x314 */ + volatile u_int32_t LC_VOICE_CHAN1; /* 0x314 - 0x318 */ + volatile u_int32_t LC_VOICE_CHAN0_RX_ENERGY; /* 0x318 - 0x31c */ + volatile u_int32_t LC_VOICE_CHAN1_RX_ENERGY; /* 0x31c - 0x320 */ + volatile u_int32_t LC_VOICE_CHAN0_TX_ENERGY; /* 0x320 - 0x324 */ + volatile u_int32_t LC_VOICE_CHAN1_TX_ENERGY; /* 0x324 - 0x328 */ + volatile u_int32_t LC_VOICE_CHAN0_ZERO_CROSS; /* 0x328 - 0x32c */ + volatile u_int32_t LC_VOICE_CHAN1_ZERO_CROSS; /* 0x32c - 0x330 */ + volatile char pad__5[0xd0]; /* 0x330 - 0x400 */ + volatile u_int32_t LC_RX_CTRL_DATAPATH; /* 0x400 - 0x404 */ + volatile u_int32_t LC_DEBUG; /* 0x404 - 0x408 */ + volatile u_int32_t LC_TX_CTRL_DATAPATH; /* 0x408 - 0x40c */ + volatile u_int32_t LC_COMMAND9; /* 0x40c - 0x410 */ + volatile u_int32_t BT_CLOCK0_FREE_RUN; /* 0x410 - 0x414 */ + volatile u_int32_t BT_CLOCK1_FREE_RUN; /* 0x414 - 0x418 */ + volatile u_int32_t BT_CLOCK2_FREE_RUN; /* 0x418 - 0x41c */ + volatile u_int32_t BT_CLOCK3_FREE_RUN; /* 0x41c - 0x420 */ + volatile u_int32_t LC_DEV_PARAM_COMMAND10; /* 0x420 - 0x424 */ + volatile u_int32_t LC_DEV_PARAM_TIMING_2; /* 0x424 - 0x428 */ + volatile u_int32_t LC_DEV_PARAM_COMMAND11; /* 0x428 - 0x42c */ + volatile u_int32_t MCI_SUB_PRIORITY_TABLE_0; /* 0x42c - 0x430 */ + volatile u_int32_t MCI_SUB_PRIORITY_TABLE_1; /* 0x430 - 0x434 */ + volatile u_int32_t MCI_SUB_PRIORITY_TABLE_2; /* 0x434 - 0x438 */ + volatile u_int32_t MCI_SUB_PRIORITY_TABLE_3; /* 0x438 - 0x43c */ + volatile u_int32_t MCI_SUB_PRIORITY_TABLE_4; /* 0x43c - 0x440 */ + volatile u_int32_t MCI_COMMAND0; /* 0x440 - 0x444 */ + volatile u_int32_t MCI_COMMAND1; /* 0x444 - 0x448 */ + volatile u_int32_t MCI_COMMAND2; /* 0x448 - 0x44c */ + volatile u_int32_t MCI_RX_CTRL; /* 0x44c - 0x450 */ + volatile u_int32_t MCI_TX_CTRL; /* 0x450 - 0x454 */ + volatile u_int32_t MCI_MSG_ATTRIBUTES_TABLE; /* 0x454 - 0x458 */ + volatile u_int32_t MCI_SCHD_TABLE_0; /* 0x458 - 0x45c */ + volatile u_int32_t MCI_SCHD_TABLE_1; /* 0x45c - 0x460 */ + volatile u_int32_t MCI_GPM_0; /* 0x460 - 0x464 */ + volatile u_int32_t MCI_GPM_1; /* 0x464 - 0x468 */ + volatile u_int32_t MCI_INTERRUPT_RAW; /* 0x468 - 0x46c */ + volatile u_int32_t MCI_INTERRUPT_EN; /* 0x46c - 0x470 */ + volatile u_int32_t MCI_REMOTE_CPU_INT; /* 0x470 - 0x474 */ + volatile u_int32_t MCI_REMOTE_CPU_INT_EN; /* 0x474 - 0x478 */ + volatile u_int32_t MCI_INTERRUPT_RX_MSG_RAW; /* 0x478 - 0x47c */ + volatile u_int32_t MCI_INTERRUPT_RX_MSG_EN; /* 0x47c - 0x480 */ + volatile u_int32_t MCI_CPU_INT; /* 0x480 - 0x484 */ + volatile u_int32_t MCI_RX_STATUS; /* 0x484 - 0x488 */ + volatile u_int32_t WBTIMER; /* 0x488 - 0x48c */ + volatile u_int32_t WB_BTCLK_SYNC_PN0; /* 0x48c - 0x490 */ + volatile u_int32_t WB_BTCLK_SYNC_PN1; /* 0x490 - 0x494 */ + volatile u_int32_t WB_BTCLK_SYNC_PN2; /* 0x494 - 0x498 */ + volatile u_int32_t WB_BTCLK_SYNC_PN3; /* 0x498 - 0x49c */ + volatile u_int32_t LC_SERIAL; /* 0x49c - 0x4a0 */ + volatile u_int32_t LC_PHY_ERR; /* 0x4a0 - 0x4a4 */ + volatile u_int32_t LC_PHY_ERR_0; /* 0x4a4 - 0x4a8 */ + volatile u_int32_t LC_PHY_ERR_1; /* 0x4a8 - 0x4ac */ + volatile u_int32_t LC_PHY_ERR_2; /* 0x4ac - 0x4b0 */ + volatile u_int32_t LC_PHY_ERR_3; /* 0x4b0 - 0x4b4 */ + volatile u_int32_t LC_PHY_ERR_4; /* 0x4b4 - 0x4b8 */ + volatile u_int32_t LC_PHY_ERR_5; /* 0x4b8 - 0x4bc */ + volatile u_int32_t LC_SF_CTRL; /* 0x4bc - 0x4c0 */ + volatile u_int32_t LC_DUMMY; /* 0x4c0 - 0x4c4 */ + volatile u_int32_t LC_FOR_BQB; /* 0x4c4 - 0x4c8 */ + volatile u_int32_t SHARED_LNA_PARAM; /* 0x4c8 - 0x4cc */ + volatile u_int32_t LC_CHNASS0_SUB1; /* 0x4cc - 0x4d0 */ + volatile u_int32_t LC_CHNASS1_SUB1; /* 0x4d0 - 0x4d4 */ + volatile u_int32_t LC_CHNASS0_SUB2; /* 0x4d4 - 0x4d8 */ + volatile u_int32_t LC_CHNASS1_SUB2; /* 0x4d8 - 0x4dc */ + volatile u_int32_t LC_CHNASS0_SUB3; /* 0x4dc - 0x4e0 */ + volatile u_int32_t LC_CHNASS1_SUB3; /* 0x4e0 - 0x4e4 */ + volatile u_int32_t LC_CHNASS0_SUB4; /* 0x4e4 - 0x4e8 */ + volatile u_int32_t LC_CHNASS1_SUB4; /* 0x4e8 - 0x4ec */ + volatile u_int32_t LC_CHNASS0_SUB5; /* 0x4ec - 0x4f0 */ + volatile u_int32_t LC_CHNASS1_SUB5; /* 0x4f0 - 0x4f4 */ + volatile u_int32_t LC_CHNASS0_SUB6; /* 0x4f4 - 0x4f8 */ + volatile u_int32_t LC_CHNASS1_SUB6; /* 0x4f8 - 0x4fc */ + volatile u_int32_t LC_CHNASS0_SUB7; /* 0x4fc - 0x500 */ + volatile u_int32_t LC_CHNASS1_SUB7; /* 0x500 - 0x504 */ + volatile u_int32_t LC_LE; /* 0x504 - 0x508 */ + volatile u_int32_t MCI_SCHD_TABLE_2; /* 0x508 - 0x50c */ + volatile u_int32_t WB_BTCLK_SYNC_LE_PN0; /* 0x50c - 0x510 */ + volatile u_int32_t WB_BTCLK_SYNC_LE_PN1; /* 0x510 - 0x514 */ + volatile u_int32_t LC_TB_LLR; /* 0x514 - 0x518 */ + volatile u_int32_t LC_SYM_TIME0_FREE_RUN; /* 0x518 - 0x51c */ + volatile u_int32_t LC_SYM_TIME1_FREE_RUN; /* 0x51c - 0x520 */ + volatile u_int32_t LC_SYM_TIME2_FREE_RUN; /* 0x520 - 0x524 */ + volatile u_int32_t LC_SYM_TIME3_FREE_RUN; /* 0x524 - 0x528 */ + volatile u_int32_t WBTIMERCLK; /* 0x528 - 0x52c */ +}; + +struct jupiter_reg_map__synthBT_reg_csr { + volatile u_int32_t SYNTHBT1; /* 0x0 - 0x4 */ + volatile u_int32_t SYNTHBT2; /* 0x4 - 0x8 */ + volatile u_int32_t SYNTHBT3; /* 0x8 - 0xc */ + volatile u_int32_t SYNTHBT4; /* 0xc - 0x10 */ + volatile u_int32_t SYNTHBT5; /* 0x10 - 0x14 */ + volatile u_int32_t SYNTHBT6; /* 0x14 - 0x18 */ + volatile u_int32_t SYNTHBT7; /* 0x18 - 0x1c */ + volatile u_int32_t SYNTHBT8; /* 0x1c - 0x20 */ +}; + +struct jupiter_reg_map__BIASBT_reg_csr { + volatile u_int32_t BIASBT1; /* 0x0 - 0x4 */ + volatile u_int32_t BIASBT2; /* 0x4 - 0x8 */ + volatile u_int32_t BIASBT3; /* 0x8 - 0xc */ + volatile u_int32_t BIASBT4; /* 0xc - 0x10 */ + volatile u_int32_t BIASBT5; /* 0x10 - 0x14 */ +}; + +struct jupiter_reg_map__TOPBT_reg_csr { + volatile u_int32_t TOPBT1; /* 0x0 - 0x4 */ + volatile u_int32_t TOPBT2; /* 0x4 - 0x8 */ + volatile u_int32_t TOPBT3; /* 0x8 - 0xc */ + volatile u_int32_t TOPBT4; /* 0xc - 0x10 */ + volatile u_int32_t TOPBT5; /* 0x10 - 0x14 */ + volatile u_int32_t TOPBT6; /* 0x14 - 0x18 */ + volatile u_int32_t TOPBT7; /* 0x18 - 0x1c */ + volatile u_int32_t TOPBT8; /* 0x1c - 0x20 */ + volatile u_int32_t TOPBT9; /* 0x20 - 0x24 */ + volatile u_int32_t TOPBT10; /* 0x24 - 0x28 */ +}; + +struct jupiter_reg_map__CLK_reg_csr { + volatile u_int32_t CLK1; /* 0x0 - 0x4 */ + volatile u_int32_t CLK2; /* 0x4 - 0x8 */ + volatile u_int32_t CLK3; /* 0x8 - 0xc */ +}; + +struct jupiter_reg_map__analog_intf_athr_wlan_reg_csr { + volatile char pad__0[0x880]; /* 0x0 - 0x880 */ + struct jupiter_reg_map__synthBT_reg_csr synth_reg_map; + /* 0x880 - 0x8a0 */ + volatile char pad__1[0x20]; /* 0x8a0 - 0x8c0 */ + struct jupiter_reg_map__BIASBT_reg_csr BIAS_reg_map; + /* 0x8c0 - 0x8d4 */ + volatile char pad__2[0x2c]; /* 0x8d4 - 0x900 */ + struct jupiter_reg_map__TOPBT_reg_csr TOP_reg_map; + /* 0x900 - 0x928 */ + volatile char pad__3[0x158]; /* 0x928 - 0xa80 */ + struct jupiter_reg_map__CLK_reg_csr CLK_reg_map; + /* 0xa80 - 0xa8c */ +}; + +struct jupiter_reg_map__efuse_reg { + volatile u_int32_t OTP_MEM[128]; /* 0x0 - 0x200 */ + volatile char pad__0[0x1d00]; /* 0x200 - 0x1f00 */ + volatile u_int32_t OTP_INTF0; /* 0x1f00 - 0x1f04 */ + volatile u_int32_t OTP_INTF1; /* 0x1f04 - 0x1f08 */ + volatile u_int32_t OTP_INTF2; /* 0x1f08 - 0x1f0c */ + volatile u_int32_t OTP_INTF3; /* 0x1f0c - 0x1f10 */ + volatile u_int32_t OTP_INTF4; /* 0x1f10 - 0x1f14 */ + volatile u_int32_t OTP_INTF5; /* 0x1f14 - 0x1f18 */ + volatile u_int32_t OTP_STATUS0; /* 0x1f18 - 0x1f1c */ + volatile u_int32_t OTP_STATUS1; /* 0x1f1c - 0x1f20 */ + volatile u_int32_t OTP_INTF6; /* 0x1f20 - 0x1f24 */ + volatile u_int32_t OTP_LDO_CONTROL; /* 0x1f24 - 0x1f28 */ + volatile u_int32_t OTP_LDO_POWER_GOOD; /* 0x1f28 - 0x1f2c */ + volatile u_int32_t OTP_LDO_STATUS; /* 0x1f2c - 0x1f30 */ + volatile u_int32_t OTP_VDDQ_HOLD_TIME; /* 0x1f30 - 0x1f34 */ + volatile u_int32_t OTP_PGENB_SETUP_HOLD_TIME; /* 0x1f34 - 0x1f38 */ + volatile u_int32_t OTP_STROBE_PULSE_INTERVAL; /* 0x1f38 - 0x1f3c */ + volatile u_int32_t OTP_CSB_ADDR_LOAD_SETUP_HOLD; + /* 0x1f3c - 0x1f40 */ +}; + +struct jupiter_reg_map__modem_reg_csr { + volatile u_int32_t START_REG; /* 0x0 - 0x4 */ + volatile u_int32_t RX_STATUS; /* 0x4 - 0x8 */ + volatile u_int32_t AC1_L; /* 0x8 - 0xc */ + volatile u_int32_t AC1_U; /* 0xc - 0x10 */ + volatile u_int32_t AC2_L; /* 0x10 - 0x14 */ + volatile u_int32_t AC2_U; /* 0x14 - 0x18 */ + volatile u_int32_t TX_LATE; /* 0x18 - 0x1c */ + volatile u_int32_t RF_SYNTH; /* 0x1c - 0x20 */ + volatile u_int32_t RF_RX_CONTROL; /* 0x20 - 0x24 */ + volatile u_int32_t RF_TX_CONTROL; /* 0x24 - 0x28 */ + volatile u_int32_t RF_FORCE; /* 0x28 - 0x2c */ + volatile u_int32_t MODEM_CONTROL; /* 0x2c - 0x30 */ + volatile u_int32_t DC_FREQ_TRACK; /* 0x30 - 0x34 */ + volatile u_int32_t PSK_TRACK; /* 0x34 - 0x38 */ + volatile u_int32_t PSK_TRACK2; /* 0x38 - 0x3c */ + volatile u_int32_t DEMOD_CTRL1; /* 0x3c - 0x40 */ + volatile u_int32_t DEMOD_CTRL2; /* 0x40 - 0x44 */ + volatile u_int32_t CORR_PARAM1; /* 0x44 - 0x48 */ + volatile u_int32_t CORR_PARAM2; /* 0x48 - 0x4c */ + volatile u_int32_t RX_LFDATA; /* 0x4c - 0x50 */ + volatile u_int32_t ROT; /* 0x50 - 0x54 */ + volatile u_int32_t TX; /* 0x54 - 0x58 */ + volatile u_int32_t TX_GFSK1; /* 0x58 - 0x5c */ + volatile u_int32_t TX_GFSK2; /* 0x5c - 0x60 */ + volatile u_int32_t TX_POWER_CORR0; /* 0x60 - 0x64 */ + volatile u_int32_t TX_POWER_CORR1; /* 0x64 - 0x68 */ + volatile u_int32_t SYNTH_CHN0; /* 0x68 - 0x6c */ + volatile u_int32_t SYNTH_OFFSET; /* 0x6c - 0x70 */ + volatile u_int32_t MODEM_DEBUG; /* 0x70 - 0x74 */ + volatile u_int32_t AGC_BYPASS; /* 0x74 - 0x78 */ + volatile u_int32_t AGC_SAT; /* 0x78 - 0x7c */ + volatile u_int32_t AGC_DET1; /* 0x7c - 0x80 */ + volatile u_int32_t AGC_DET2; /* 0x80 - 0x84 */ + volatile u_int32_t AGC_GAIN1; /* 0x84 - 0x88 */ + volatile u_int32_t AGC_GAIN2; /* 0x88 - 0x8c */ + volatile u_int32_t AGC_LINEAR_BLK; /* 0x8c - 0x90 */ + volatile u_int32_t AGC_NONLIN_BLK; /* 0x90 - 0x94 */ + volatile u_int32_t AGC_MIN_POWER; /* 0x94 - 0x98 */ + volatile u_int32_t AGC_SLNA_SET0; /* 0x98 - 0x9c */ + volatile u_int32_t AGC_SLNA_SET1; /* 0x9c - 0xa0 */ + volatile u_int32_t AGC_SLNA_SET2; /* 0xa0 - 0xa4 */ + volatile u_int32_t AGC_SLNA_SET3; /* 0xa4 - 0xa8 */ + volatile u_int32_t AGC_GAIN1_LEAN; /* 0xa8 - 0xac */ + volatile u_int32_t MODEM_CTRL; /* 0xac - 0xb0 */ + volatile u_int32_t DEMOD_CTRL3; /* 0xb0 - 0xb4 */ + volatile u_int32_t DEMOD_CTRL4; /* 0xb4 - 0xb8 */ + volatile u_int32_t TX_GFSK3; /* 0xb8 - 0xbc */ + volatile u_int32_t LE_DEMOD; /* 0xbc - 0xc0 */ + volatile u_int32_t AGC_LE1; /* 0xc0 - 0xc4 */ + volatile u_int32_t AGC_LE2; /* 0xc4 - 0xc8 */ + volatile u_int32_t AGC_LE3; /* 0xc8 - 0xcc */ + volatile u_int32_t AGC_LE4; /* 0xcc - 0xd0 */ + volatile u_int32_t AGC_LE5; /* 0xd0 - 0xd4 */ + volatile u_int32_t AGC_LE6; /* 0xd4 - 0xd8 */ + volatile u_int32_t LE_FREQ; /* 0xd8 - 0xdc */ + volatile u_int32_t LE_BLOCKER; /* 0xdc - 0xe0 */ + volatile char pad__0[0x420]; /* 0xe0 - 0x500 */ + volatile u_int32_t AGC_GAIN_TABLE[128]; /* 0x500 - 0x700 */ + volatile u_int32_t TX_ULP_CNTRL; /* 0x700 - 0x704 */ + volatile u_int32_t SS_MANUAL1; /* 0x704 - 0x708 */ + volatile u_int32_t SS_MANUAL2; /* 0x708 - 0x70c */ + volatile u_int32_t SS_RADIO_CTRL; /* 0x70c - 0x710 */ + volatile u_int32_t PHY_ERR_CTRL1; /* 0x710 - 0x714 */ + volatile u_int32_t PHY_ERR_CTRL2; /* 0x714 - 0x718 */ + volatile u_int32_t PHY_ERR_CTRL3; /* 0x718 - 0x71c */ + volatile u_int32_t PHY_ERR_CTRL4; /* 0x71c - 0x720 */ + volatile u_int32_t PHY_ERR_STATUS; /* 0x720 - 0x724 */ + volatile u_int32_t RBIST_ENABLE_CONTROL; /* 0x724 - 0x728 */ + volatile u_int32_t RBIST_TX_DC; /* 0x728 - 0x72c */ + volatile u_int32_t RBIST_TX_TONE0; /* 0x72c - 0x730 */ + volatile u_int32_t RBIST_TX_TONE1; /* 0x730 - 0x734 */ + volatile u_int32_t RBIST_TX_TONE2; /* 0x734 - 0x738 */ + volatile u_int32_t RBIST_TX_RAMP_I; /* 0x738 - 0x73c */ + volatile u_int32_t RBIST_TX_RAMP_Q; /* 0x73c - 0x740 */ + volatile u_int32_t RBIST_TX_PRBS_MAG; /* 0x740 - 0x744 */ + volatile u_int32_t RBIST_TX_PRBS_SEED_I; /* 0x744 - 0x748 */ + volatile u_int32_t RBIST_TX_PRBS_SEED_Q; /* 0x748 - 0x74c */ + volatile u_int32_t RBIST_RX_DC_OFFSET; /* 0x74c - 0x750 */ + volatile u_int32_t RBIST_RX_DC_OFFSET_CANCEL; /* 0x750 - 0x754 */ + volatile u_int32_t RBIST_RX_DFT; /* 0x754 - 0x758 */ + volatile u_int32_t RBIST_RX_POWER; /* 0x758 - 0x75c */ + volatile u_int32_t RBIST_RX_IQ; /* 0x75c - 0x760 */ + volatile u_int32_t RBIST_RX_I2Q2; /* 0x760 - 0x764 */ + volatile u_int32_t RBIST_RX_HPF; /* 0x764 - 0x768 */ + volatile u_int32_t RBIST_RX_RESULT_Q; /* 0x768 - 0x76c */ + volatile u_int32_t RBIST_RX_RESULT_I; /* 0x76c - 0x770 */ + volatile u_int32_t CAL_EN; /* 0x770 - 0x774 */ + volatile u_int32_t CAL_CONFIG; /* 0x774 - 0x778 */ + volatile u_int32_t PASSIVE_RXIQ; /* 0x778 - 0x77c */ + volatile u_int32_t TX_CORR1; /* 0x77c - 0x780 */ + volatile u_int32_t TX_CORR2; /* 0x780 - 0x784 */ + volatile u_int32_t TX_CORR3; /* 0x784 - 0x788 */ + volatile u_int32_t TX_CORR4; /* 0x788 - 0x78c */ + volatile u_int32_t RX_IQCORR_0; /* 0x78c - 0x790 */ + volatile u_int32_t RX_IQCORR_1; /* 0x790 - 0x794 */ + volatile u_int32_t RX_IQCORR_2; /* 0x794 - 0x798 */ + volatile u_int32_t RX_IQCORR_3; /* 0x798 - 0x79c */ + volatile u_int32_t CAL_MEAS_I2_L; /* 0x79c - 0x7a0 */ + volatile u_int32_t CAL_MEAS_I2_U; /* 0x7a0 - 0x7a4 */ + volatile u_int32_t CAL_MEAS_IQ_L; /* 0x7a4 - 0x7a8 */ + volatile u_int32_t CAL_MEAS_IQ_U; /* 0x7a8 - 0x7ac */ + volatile u_int32_t CAL_MEAS_Q2_L; /* 0x7ac - 0x7b0 */ + volatile u_int32_t CAL_MEAS_Q2_U; /* 0x7b0 - 0x7b4 */ + volatile u_int32_t CAP_SFT_DEBUG; /* 0x7b4 - 0x7b8 */ + volatile u_int32_t RX_NOTCH_0; /* 0x7b8 - 0x7bc */ + volatile u_int32_t RX_NOTCH_1; /* 0x7bc - 0x7c0 */ + volatile u_int32_t RX_NOTCH_2; /* 0x7c0 - 0x7c4 */ + volatile u_int32_t RX_NOTCH_INDEX_0; /* 0x7c4 - 0x7c8 */ + volatile u_int32_t RX_NOTCH_INDEX_1; /* 0x7c8 - 0x7cc */ + volatile u_int32_t RX_NOTCH_INDEX_2; /* 0x7cc - 0x7d0 */ + volatile u_int32_t RX_NOTCH_INDEX_3; /* 0x7d0 - 0x7d4 */ + volatile u_int32_t RX_NOTCH_INDEX_4; /* 0x7d4 - 0x7d8 */ + volatile u_int32_t RX_NOTCH_INDEX_5; /* 0x7d8 - 0x7dc */ + volatile u_int32_t RX_NOTCH_INDEX_6; /* 0x7dc - 0x7e0 */ + volatile u_int32_t RX_NOTCH_INDEX_7; /* 0x7e0 - 0x7e4 */ + volatile u_int32_t RX_NOTCH_PARAMS_0; /* 0x7e4 - 0x7e8 */ + volatile u_int32_t RX_NOTCH_PARAMS_1; /* 0x7e8 - 0x7ec */ + volatile u_int32_t RX_NOTCH_PARAMS_2; /* 0x7ec - 0x7f0 */ + volatile u_int32_t RX_NOTCH_PARAMS_3; /* 0x7f0 - 0x7f4 */ + volatile u_int32_t RX_NOTCH_PARAMS_4; /* 0x7f4 - 0x7f8 */ + volatile u_int32_t RX_NOTCH_PARAMS_5; /* 0x7f8 - 0x7fc */ + volatile u_int32_t RX_NOTCH_PARAMS_6; /* 0x7fc - 0x800 */ + volatile u_int32_t CHNASS_CTRL; /* 0x800 - 0x804 */ + volatile u_int32_t CHNASS_SETUP_0; /* 0x804 - 0x808 */ + volatile u_int32_t CHNASS_SETUP_1; /* 0x808 - 0x80c */ + volatile u_int32_t CHNASS_SETUP_2; /* 0x80c - 0x810 */ + volatile u_int32_t CHNASS_SETUP_3; /* 0x810 - 0x814 */ + volatile u_int32_t CHNASS_RSSI_0; /* 0x814 - 0x818 */ + volatile u_int32_t CHNASS_RSSI_1; /* 0x818 - 0x81c */ + volatile u_int32_t SW_CTRL; /* 0x81c - 0x820 */ + volatile u_int32_t JUPITER_CTRL; /* 0x820 - 0x824 */ + volatile u_int32_t JUPITER_GAIN; /* 0x824 - 0x828 */ + volatile u_int32_t AGC_HIST_SETUP; /* 0x828 - 0x82c */ + volatile u_int32_t AGC_HIST_BANK_0; /* 0x82c - 0x830 */ + volatile u_int32_t AGC_HIST_BANK_1; /* 0x830 - 0x834 */ + volatile u_int32_t AGC_HIST_BANK_2; /* 0x834 - 0x838 */ + volatile u_int32_t AGC_HIST_BANK_3; /* 0x838 - 0x83c */ + volatile u_int32_t AGC_HIST_BANK_4; /* 0x83c - 0x840 */ + volatile u_int32_t SPARE; /* 0x840 - 0x844 */ +}; + +struct jupiter_reg_map__le_dma_reg_csr { + volatile u_int32_t LE_DMA_MASTER; /* 0x0 - 0x4 */ + volatile u_int32_t LE_DMA_TX_CONTROL; /* 0x4 - 0x8 */ + volatile u_int32_t LE_DMA_RX_CONTROL; /* 0x8 - 0xc */ + volatile u_int32_t LE_DMA_TX_HW; /* 0xc - 0x10 */ + volatile u_int32_t LE_DMA_RX_HW; /* 0x10 - 0x14 */ + volatile u_int32_t LE_DMA_INT_STATUS; /* 0x14 - 0x18 */ + volatile u_int32_t LE_DMA_TX_STATUS; /* 0x18 - 0x1c */ + volatile u_int32_t LE_DMA_TX_STATUS_W1TC; /* 0x1c - 0x20 */ + volatile u_int32_t LE_DMA_TX_ENABLE; /* 0x20 - 0x24 */ + volatile u_int32_t LE_DMA_RX_STATUS; /* 0x24 - 0x28 */ + volatile u_int32_t LE_DMA_RX_STATUS_W1TC; /* 0x28 - 0x2c */ + volatile u_int32_t LE_DMA_RX_ENABLE; /* 0x2c - 0x30 */ + volatile u_int32_t LE_DMA_DEBUG; /* 0x30 - 0x34 */ + volatile u_int32_t LE_DMA_DUMMY; /* 0x34 - 0x38 */ +}; + +struct jupiter_reg_map__le_reg_csr { + volatile u_int32_t LE_PUBLIC_ADDRESS_L; /* 0x0 - 0x4 */ + volatile u_int32_t LE_PUBLIC_ADDRESS_U; /* 0x4 - 0x8 */ + volatile u_int32_t LE_RANDOM_ADDRESS_L; /* 0x8 - 0xc */ + volatile u_int32_t LE_RANDOM_ADDRESS_U; /* 0xc - 0x10 */ + volatile u_int32_t LE_DEV_PARAM; /* 0x10 - 0x14 */ + volatile u_int32_t COMMAND1; /* 0x14 - 0x18 */ + volatile u_int32_t COMMAND2; /* 0x18 - 0x1c */ + volatile u_int32_t COMMAND3; /* 0x1c - 0x20 */ + volatile u_int32_t COMMAND4; /* 0x20 - 0x24 */ + volatile u_int32_t COMMAND5; /* 0x24 - 0x28 */ + volatile u_int32_t COMMAND6; /* 0x28 - 0x2c */ + volatile u_int32_t COMMAND7; /* 0x2c - 0x30 */ + volatile u_int32_t COMMAND8; /* 0x30 - 0x34 */ + volatile u_int32_t COMMAND9; /* 0x34 - 0x38 */ + volatile u_int32_t COMMAND10; /* 0x38 - 0x3c */ + volatile u_int32_t COMMAND11; /* 0x3c - 0x40 */ + volatile u_int32_t COMMAND12; /* 0x40 - 0x44 */ + volatile u_int32_t COMMAND13; /* 0x44 - 0x48 */ + volatile u_int32_t LE_ABORT; /* 0x48 - 0x4c */ + volatile u_int32_t LE_RX_STATUS1; /* 0x4c - 0x50 */ + volatile u_int32_t LE_RX_STATUS2; /* 0x50 - 0x54 */ + volatile u_int32_t LE_RX_STATUS3; /* 0x54 - 0x58 */ + volatile u_int32_t LE_RX_STATUS4; /* 0x58 - 0x5c */ + volatile u_int32_t LE_RX_STATUS5; /* 0x5c - 0x60 */ + volatile u_int32_t LE_RX_STATUS6; /* 0x60 - 0x64 */ + volatile u_int32_t LE_RX_STATUS7; /* 0x64 - 0x68 */ + volatile u_int32_t LE_RX_STATUS8; /* 0x68 - 0x6c */ + volatile u_int32_t LE_RX_STATUS9; /* 0x6c - 0x70 */ + volatile u_int32_t LE_INTERRUPT_EN; /* 0x70 - 0x74 */ + volatile u_int32_t LE_INTERRUPT; /* 0x74 - 0x78 */ + volatile u_int32_t LE_DATAPATH_CNTL; /* 0x78 - 0x7c */ + volatile u_int32_t LE_BT_CLOCK0; /* 0x7c - 0x80 */ + volatile u_int32_t LE_BT_CLOCK1; /* 0x80 - 0x84 */ + volatile u_int32_t LE_SYM_TIME0; /* 0x84 - 0x88 */ + volatile u_int32_t LE_SYM_TIME1; /* 0x88 - 0x8c */ + volatile u_int32_t LE_TIMER0; /* 0x8c - 0x90 */ + volatile u_int32_t LE_TIMER0_FRAME; /* 0x90 - 0x94 */ + volatile u_int32_t LE_TIMER1; /* 0x94 - 0x98 */ + volatile u_int32_t LE_TIMER1_FRAME; /* 0x98 - 0x9c */ + volatile u_int32_t LE_WL_TABLE[256]; /* 0x9c - 0x49c */ + volatile u_int32_t LE_TIM; /* 0x49c - 0x4a0 */ + volatile u_int32_t TX_ERROR_GENERATION; /* 0x4a0 - 0x4a4 */ + volatile u_int32_t LE_FREQ_MAP0; /* 0x4a4 - 0x4a8 */ + volatile u_int32_t LE_FREQ_MAP1; /* 0x4a8 - 0x4ac */ + volatile u_int32_t LE_FREQ_MAP2; /* 0x4ac - 0x4b0 */ + volatile u_int32_t LE_FREQ_MAP3; /* 0x4b0 - 0x4b4 */ + volatile u_int32_t LE_FREQ_MAP4; /* 0x4b4 - 0x4b8 */ + volatile u_int32_t LE_FREQ_MAP5; /* 0x4b8 - 0x4bc */ + volatile u_int32_t LE_FREQ_MAP6; /* 0x4bc - 0x4c0 */ + volatile u_int32_t LE_FREQ_MAP7; /* 0x4c0 - 0x4c4 */ + volatile u_int32_t LE_FREQ_MAP8; /* 0x4c4 - 0x4c8 */ + volatile u_int32_t LE_FREQ_MAP9; /* 0x4c8 - 0x4cc */ + volatile u_int32_t LE_DEBUG_CTRL; /* 0x4cc - 0x4d0 */ + volatile u_int32_t LE_DEBUG_OBS; /* 0x4d0 - 0x4d4 */ + volatile u_int32_t LE_PHY_ERR; /* 0x4d4 - 0x4d8 */ + volatile u_int32_t LE_PHY_ERR_0; /* 0x4d8 - 0x4dc */ + volatile u_int32_t LE_PHY_ERR_1; /* 0x4dc - 0x4e0 */ + volatile u_int32_t LE_PHY_ERR_2; /* 0x4e0 - 0x4e4 */ + volatile u_int32_t LE_PHY_ERR_3; /* 0x4e4 - 0x4e8 */ + volatile u_int32_t LE_PHY_ERR_4; /* 0x4e8 - 0x4ec */ + volatile u_int32_t LE_DUMMY; /* 0x4ec - 0x4f0 */ +}; + +struct jupiter_reg_map__apb_map_csr { + volatile char pad__0[0x4000]; /* 0x0 - 0x4000 */ + struct jupiter_reg_map__rtc_reg_csr rtc; /* 0x4000 - 0x4134 */ + volatile char pad__1[0x3ecc]; /* 0x4134 - 0x8000 */ + struct jupiter_reg_map__vmc_reg_csr vmc; /* 0x8000 - 0x8620 */ + volatile char pad__2[0x39e0]; /* 0x8620 - 0xc000 */ + struct jupiter_reg_map__apb_map_csr__uart_reg_csr uart; + /* 0xc000 - 0xc014 */ + volatile char pad__3[0x3fec]; /* 0xc014 - 0x10000 */ + struct jupiter_reg_map__si_reg_csr si; /* 0x10000 - 0x10018 */ + volatile char pad__4[0x3fe8]; /* 0x10018 - 0x14000 */ + struct jupiter_reg_map__gpio_reg_csr gpio; /* 0x14000 - 0x14098 */ + volatile char pad__5[0x3f68]; /* 0x14098 - 0x18000 */ + struct jupiter_reg_map__mbox_reg_csr mbox; /* 0x18000 - 0x1809c */ + volatile char pad__6[0x3f64]; /* 0x1809c - 0x1c000 */ + struct jupiter_reg_map__lc_dma_reg_csr lc_dma; /* 0x1c000 - 0x1c034 */ + volatile char pad__7[0x3fcc]; /* 0x1c034 - 0x20000 */ + struct jupiter_reg_map__lc_reg_csr lc; /* 0x20000 - 0x2052c */ + volatile char pad__8[0x2ad4]; /* 0x2052c - 0x23000 */ + struct jupiter_reg_map__analog_intf_athr_wlan_reg_csr analog; + /* 0x23000 - 0x23a90 */ + volatile char pad__9[0x570]; /* 0x23a90 - 0x24000 */ + struct jupiter_reg_map__efuse_reg efuse; /* 0x24000 - 0x25f40 */ + volatile char pad__10[0xc0]; /* 0x25f40 - 0x26000 */ + struct jupiter_reg_map__modem_reg_csr modem; /* 0x26000 - 0x26844 */ + volatile char pad__11[0x37bc]; /* 0x26844 - 0x2a000 */ + struct jupiter_reg_map__le_dma_reg_csr le_dma; /* 0x2a000 - 0x2a038 */ + volatile char pad__12[0x1fc8]; /* 0x2a038 - 0x2c000 */ + struct jupiter_reg_map__le_reg_csr le; /* 0x2c000 - 0x2c4f0 */ +}; + +struct bt_apb_reg { + volatile char pad__0[0x40000]; /* 0x0 - 0x40000 */ + struct jupiter_reg_map__apb_map_csr bt_apb_map_block; + /* 0x40000 - 0x6c800 */ +}; + +struct osprey_reg_map { + struct mac_dma_reg mac_dma_reg_block; /* 0x0 - 0x108 */ + volatile char pad__0; /* 0x108 - 0x0 */ + struct mac_qcu_reg mac_qcu_reg_block; /* 0x0 - 0x24c */ + volatile char pad__1; /* 0x24c - 0x0 */ + struct mac_dcu_reg mac_dcu_reg_block; /* 0x0 - 0x7fc */ + volatile char pad__2; /* 0x7fc - 0x0 */ + struct host_intf_reg host_intf_reg_block; /* 0x0 - 0xf4 */ + volatile char pad__3; /* 0xf4 - 0x0 */ + struct emulation_misc_regs emulation_misc_reg_block; + /* 0x0 - 0x30 */ + volatile char pad__4; /* Osprey: 0x30 - 0x0 */ + struct DWC_pcie_dbi_axi DWC_pcie_dbi_axi_block; /* Osprey: 0x0 - 0x818 */ + volatile char pad__5; /* 0x818 - 0x0 */ + struct rtc_reg rtc_reg_block; /* Osprey: 0x0 - 0x3c, Poseidon: 0x0 - 0x40 */ + volatile char pad__6; /* Osprey: 0x3c - 0x0, Poseidon: 0x40 - 0x0 */ + struct rtc_sync_reg rtc_sync_reg_block; /* 0x0 - 0x1c */ + volatile char pad__7; /* 0x1c - 0x0 */ + struct merlin2_0_radio_reg_map merlin2_0_radio_reg_map; + /* 0x0 - 0x9c */ + volatile char pad__8; /* 0x9c - 0x0 */ + struct analog_intf_reg_csr analog_intf_reg_csr_block; + /* 0x0 - 0x10 */ + volatile char pad__9; /* 0x10 - 0x0 */ + struct mac_pcu_reg mac_pcu_reg_block; /* 0x0 - 0x8000 */ + volatile char pad__10; /* 0x8000 - 0x0 */ + struct bb_reg_map bb_reg_block; /* 0x0 - 0x4000 */ + volatile char pad__11; /* 0x4000 - 0x0 */ + struct svd_reg svd_reg_block; /* 0x0 - 0x2c00 */ + volatile char pad__12; /* 0x2c00 - 0x0 */ + struct efuse_reg_WLAN efuse_reg_block; /* 0x0 - 0x1f40 */ + volatile char pad__13; /* 0x1f40 - 0x0 */ + struct radio65_reg radio65_reg_block; /* Osprey: 0x0 - 0xbd8, Poseidon: 0x0 - 0x3d8 */ + volatile char pad__14; /* Osprey: 0xbd8 - 0x0, Poseidon: 0x3d8 - 0x0 */ + struct pmu_reg pmu_reg_block; /* Osprey: 0x0 - 0x8 */ + volatile char pad__15; /* Osprey: 0x8 - 0x0 */ + struct pcie_phy_reg_csr pcie_phy_reg_block; /* 0x0 - 0xc */ + volatile char pad__16; /* 0xc - 0x0 */ + struct wlan_coex_reg wlan_coex_reg_block; /* 0x0 - 0x264 */ + volatile char pad__17; /* 0x264 - 0x0 */ + struct wlan_bt_glb_reg_pcie glb_reg_block; /* 0x0 - 0x400 */ + volatile char pad__18; /* 0x400 - 0x0 */ + struct bt_apb_reg bt_apb_reg_block; /* Jupiter: 0x0 - 0x2c800 */ +}; + +#endif /* __REG_OSPREY_REG_MAP_H__ */ diff --git a/hal/ar9300/osprey_reg_map_macro.h b/hal/ar9300/osprey_reg_map_macro.h new file mode 100644 index 000000000000..f58b99e2a998 --- /dev/null +++ b/hal/ar9300/osprey_reg_map_macro.h @@ -0,0 +1,83644 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* */ +/* File: /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/osprey_reg_map_macro.h*/ +/* Creator: yli */ +/* Time: Wednesday Jan 6, 2010 [2:09:02 pm] */ +/* */ +/* Path: /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top */ +/* Arguments: /cad/denali/blueprint/3.7//Linux/blueprint -codegen */ +/* /trees/yli/yli-dev/chips/osprey/2.0/env/blueprint/ath_ansic.codegen*/ +/* -ath_ansic -Wdesc -I */ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top -I */ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint -I */ +/* /trees/yli/yli-dev/chips/osprey/2.0/env/blueprint -I */ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig -odir */ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top -eval */ +/* {$INCLUDE_SYSCONFIG_FILES=1} -eval */ +/* $WAR_EV58615_for_ansic_codegen=1 osprey_reg.rdl */ +/* */ +/* Sources: /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/emulation_misc.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/amba_mac/svd/blueprint/svd_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/merlin2_0_radio_reg_map.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/host_intf/rtl/blueprint/efuse_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/ip/pcie_axi/blueprint/DWC_pcie_ep.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/apb_analog/analog_intf_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/rtc/blueprint/rtc_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/DWC_pcie_dbi_axi_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/host_intf/rtl/blueprint/host_intf_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/bb/blueprint/bb_reg_map.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/efuse_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/osprey_pcieconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/osprey_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/merlin2_0_radio_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/rtl/amba_mac/blueprint/rtc_sync_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/analog_intf_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/svd_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/osprey_radio_reg.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/host_intf_reg_sysconfig.rdl*/ +/* /trees/yli/yli-dev/chips/osprey/2.0/env/blueprint/ath_ansic.pm*/ +/* /cad/local/lib/perl/Pinfo.pm */ +/* */ +/* Blueprint: 3.7 (Fri Oct 5 10:32:33 PDT 2007) */ +/* Machine: artemis */ +/* OS: Linux 2.6.9-78.0.5.ELlargesmp */ +/* Description: */ +/* */ +/*This Register Map contains the complete register set for OSPREY. */ +/* */ +/* Copyright (C) 2010 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ +/* */ + + +#ifndef __REG_OSPREY_REG_MAP_MACRO_H__ +#define __REG_OSPREY_REG_MAP_MACRO_H__ + + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_CR */ +#ifndef __MAC_DMA_CR_MACRO__ +#define __MAC_DMA_CR_MACRO__ + +/* macros for field RXE_LP */ +#define MAC_DMA_CR__RXE_LP__SHIFT 2 +#define MAC_DMA_CR__RXE_LP__WIDTH 1 +#define MAC_DMA_CR__RXE_LP__MASK 0x00000004U +#define MAC_DMA_CR__RXE_LP__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define MAC_DMA_CR__RXE_LP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_DMA_CR__RXE_LP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field RXE_HP */ +#define MAC_DMA_CR__RXE_HP__SHIFT 3 +#define MAC_DMA_CR__RXE_HP__WIDTH 1 +#define MAC_DMA_CR__RXE_HP__MASK 0x00000008U +#define MAC_DMA_CR__RXE_HP__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define MAC_DMA_CR__RXE_HP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_DMA_CR__RXE_HP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field RXD */ +#define MAC_DMA_CR__RXD__SHIFT 5 +#define MAC_DMA_CR__RXD__WIDTH 1 +#define MAC_DMA_CR__RXD__MASK 0x00000020U +#define MAC_DMA_CR__RXD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define MAC_DMA_CR__RXD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) +#define MAC_DMA_CR__RXD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_DMA_CR__RXD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_DMA_CR__RXD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_DMA_CR__RXD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field SWI */ +#define MAC_DMA_CR__SWI__SHIFT 6 +#define MAC_DMA_CR__SWI__WIDTH 1 +#define MAC_DMA_CR__SWI__MASK 0x00000040U +#define MAC_DMA_CR__SWI__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define MAC_DMA_CR__SWI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_DMA_CR__SWI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) +#define MAC_DMA_CR__TYPE u_int32_t +#define MAC_DMA_CR__READ 0x0000006cU +#define MAC_DMA_CR__WRITE 0x0000006cU + +#endif /* __MAC_DMA_CR_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_CR */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_CR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_CFG */ +#ifndef __MAC_DMA_CFG_MACRO__ +#define __MAC_DMA_CFG_MACRO__ + +/* macros for field BE_MODE_XMIT_DESC */ +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__SHIFT 0 +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WIDTH 1 +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MASK 0x00000001U +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field BE_MODE_XMIT_DATA */ +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__SHIFT 1 +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WIDTH 1 +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MASK 0x00000002U +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field BE_MODE_RCV_DESC */ +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__SHIFT 2 +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__WIDTH 1 +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__MASK 0x00000004U +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field BE_MODE_RCV_DATA */ +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__SHIFT 3 +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__WIDTH 1 +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__MASK 0x00000008U +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BE_MODE_MMR */ +#define MAC_DMA_CFG__BE_MODE_MMR__SHIFT 4 +#define MAC_DMA_CFG__BE_MODE_MMR__WIDTH 1 +#define MAC_DMA_CFG__BE_MODE_MMR__MASK 0x00000010U +#define MAC_DMA_CFG__BE_MODE_MMR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_DMA_CFG__BE_MODE_MMR__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_DMA_CFG__BE_MODE_MMR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_DMA_CFG__BE_MODE_MMR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_DMA_CFG__BE_MODE_MMR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_DMA_CFG__BE_MODE_MMR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field ADHOC */ +#define MAC_DMA_CFG__ADHOC__SHIFT 5 +#define MAC_DMA_CFG__ADHOC__WIDTH 1 +#define MAC_DMA_CFG__ADHOC__MASK 0x00000020U +#define MAC_DMA_CFG__ADHOC__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define MAC_DMA_CFG__ADHOC__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) +#define MAC_DMA_CFG__ADHOC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_DMA_CFG__ADHOC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_DMA_CFG__ADHOC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_DMA_CFG__ADHOC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field PHY_OK */ +#define MAC_DMA_CFG__PHY_OK__SHIFT 8 +#define MAC_DMA_CFG__PHY_OK__WIDTH 1 +#define MAC_DMA_CFG__PHY_OK__MASK 0x00000100U +#define MAC_DMA_CFG__PHY_OK__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define MAC_DMA_CFG__PHY_OK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_DMA_CFG__PHY_OK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field EEPROM_BUSY */ +#define MAC_DMA_CFG__EEPROM_BUSY__SHIFT 9 +#define MAC_DMA_CFG__EEPROM_BUSY__WIDTH 1 +#define MAC_DMA_CFG__EEPROM_BUSY__MASK 0x00000200U +#define MAC_DMA_CFG__EEPROM_BUSY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_DMA_CFG__EEPROM_BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_DMA_CFG__EEPROM_BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field CLKGATE_DIS */ +#define MAC_DMA_CFG__CLKGATE_DIS__SHIFT 10 +#define MAC_DMA_CFG__CLKGATE_DIS__WIDTH 1 +#define MAC_DMA_CFG__CLKGATE_DIS__MASK 0x00000400U +#define MAC_DMA_CFG__CLKGATE_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_DMA_CFG__CLKGATE_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_DMA_CFG__CLKGATE_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_DMA_CFG__CLKGATE_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_DMA_CFG__CLKGATE_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_DMA_CFG__CLKGATE_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field HALT_REQ */ +#define MAC_DMA_CFG__HALT_REQ__SHIFT 11 +#define MAC_DMA_CFG__HALT_REQ__WIDTH 1 +#define MAC_DMA_CFG__HALT_REQ__MASK 0x00000800U +#define MAC_DMA_CFG__HALT_REQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_DMA_CFG__HALT_REQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_DMA_CFG__HALT_REQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_DMA_CFG__HALT_REQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_DMA_CFG__HALT_REQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_DMA_CFG__HALT_REQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field HALT_ACK */ +#define MAC_DMA_CFG__HALT_ACK__SHIFT 12 +#define MAC_DMA_CFG__HALT_ACK__WIDTH 1 +#define MAC_DMA_CFG__HALT_ACK__MASK 0x00001000U +#define MAC_DMA_CFG__HALT_ACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_DMA_CFG__HALT_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_DMA_CFG__HALT_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field REQ_Q_FULL_THRESHOLD */ +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__SHIFT 17 +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WIDTH 2 +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MASK 0x00060000U +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00060000U) >> 17) +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00060000U) +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((u_int32_t)(src) <<\ + 17) & 0x00060000U) +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00060000U))) + +/* macros for field MISSING_TX_INTR_FIX_ENABLE */ +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__SHIFT 19 +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WIDTH 1 +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MASK 0x00080000U +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) +#define MAC_DMA_CFG__TYPE u_int32_t +#define MAC_DMA_CFG__READ 0x000e1f3fU +#define MAC_DMA_CFG__WRITE 0x000e1f3fU + +#endif /* __MAC_DMA_CFG_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_CFG */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_CFG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXBUFPTR_THRESH */ +#ifndef __MAC_DMA_RXBUFPTR_THRESH_MACRO__ +#define __MAC_DMA_RXBUFPTR_THRESH_MACRO__ + +/* macros for field HP_DATA */ +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__SHIFT 0 +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WIDTH 4 +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MASK 0x0000000fU +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field LP_DATA */ +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__SHIFT 8 +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WIDTH 7 +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MASK 0x00007f00U +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007f00U) >> 8) +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00007f00U) +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00007f00U) +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00007f00U))) +#define MAC_DMA_RXBUFPTR_THRESH__TYPE u_int32_t +#define MAC_DMA_RXBUFPTR_THRESH__READ 0x00007f0fU +#define MAC_DMA_RXBUFPTR_THRESH__WRITE 0x00007f0fU + +#endif /* __MAC_DMA_RXBUFPTR_THRESH_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_RXBUFPTR_THRESH */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_RXBUFPTR_THRESH__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXDPPTR_THRESH */ +#ifndef __MAC_DMA_TXDPPTR_THRESH_MACRO__ +#define __MAC_DMA_TXDPPTR_THRESH_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_TXDPPTR_THRESH__DATA__SHIFT 0 +#define MAC_DMA_TXDPPTR_THRESH__DATA__WIDTH 4 +#define MAC_DMA_TXDPPTR_THRESH__DATA__MASK 0x0000000fU +#define MAC_DMA_TXDPPTR_THRESH__DATA__READ(src) (u_int32_t)(src) & 0x0000000fU +#define MAC_DMA_TXDPPTR_THRESH__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_DMA_TXDPPTR_THRESH__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_DMA_TXDPPTR_THRESH__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define MAC_DMA_TXDPPTR_THRESH__TYPE u_int32_t +#define MAC_DMA_TXDPPTR_THRESH__READ 0x0000000fU +#define MAC_DMA_TXDPPTR_THRESH__WRITE 0x0000000fU + +#endif /* __MAC_DMA_TXDPPTR_THRESH_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_TXDPPTR_THRESH */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_TXDPPTR_THRESH__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_MIRT */ +#ifndef __MAC_DMA_MIRT_MACRO__ +#define __MAC_DMA_MIRT_MACRO__ + +/* macros for field RATE_THRESH */ +#define MAC_DMA_MIRT__RATE_THRESH__SHIFT 0 +#define MAC_DMA_MIRT__RATE_THRESH__WIDTH 16 +#define MAC_DMA_MIRT__RATE_THRESH__MASK 0x0000ffffU +#define MAC_DMA_MIRT__RATE_THRESH__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_DMA_MIRT__RATE_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_DMA_MIRT__RATE_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_MIRT__RATE_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DMA_MIRT__TYPE u_int32_t +#define MAC_DMA_MIRT__READ 0x0000ffffU +#define MAC_DMA_MIRT__WRITE 0x0000ffffU + +#endif /* __MAC_DMA_MIRT_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_MIRT */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_MIRT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_GLOBAL_IER */ +#ifndef __MAC_DMA_GLOBAL_IER_MACRO__ +#define __MAC_DMA_GLOBAL_IER_MACRO__ + +/* macros for field ENABLE */ +#define MAC_DMA_GLOBAL_IER__ENABLE__SHIFT 0 +#define MAC_DMA_GLOBAL_IER__ENABLE__WIDTH 1 +#define MAC_DMA_GLOBAL_IER__ENABLE__MASK 0x00000001U +#define MAC_DMA_GLOBAL_IER__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_DMA_GLOBAL_IER__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_DMA_GLOBAL_IER__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_DMA_GLOBAL_IER__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_DMA_GLOBAL_IER__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DMA_GLOBAL_IER__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define MAC_DMA_GLOBAL_IER__TYPE u_int32_t +#define MAC_DMA_GLOBAL_IER__READ 0x00000001U +#define MAC_DMA_GLOBAL_IER__WRITE 0x00000001U + +#endif /* __MAC_DMA_GLOBAL_IER_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_GLOBAL_IER */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_GLOBAL_IER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT */ +#ifndef __MAC_DMA_TIMT_MACRO__ +#define __MAC_DMA_TIMT_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT__TYPE u_int32_t +#define MAC_DMA_TIMT__READ 0xffffffffU +#define MAC_DMA_TIMT__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_TIMT */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_TIMT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RIMT */ +#ifndef __MAC_DMA_RIMT_MACRO__ +#define __MAC_DMA_RIMT_MACRO__ + +/* macros for field RX_LAST_PKT_THRESH */ +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field RX_FIRST_PKT_THRESH */ +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_RIMT__TYPE u_int32_t +#define MAC_DMA_RIMT__READ 0xffffffffU +#define MAC_DMA_RIMT__WRITE 0xffffffffU + +#endif /* __MAC_DMA_RIMT_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_RIMT */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_RIMT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXCFG */ +#ifndef __MAC_DMA_TXCFG_MACRO__ +#define __MAC_DMA_TXCFG_MACRO__ + +/* macros for field DMA_SIZE */ +#define MAC_DMA_TXCFG__DMA_SIZE__SHIFT 0 +#define MAC_DMA_TXCFG__DMA_SIZE__WIDTH 3 +#define MAC_DMA_TXCFG__DMA_SIZE__MASK 0x00000007U +#define MAC_DMA_TXCFG__DMA_SIZE__READ(src) (u_int32_t)(src) & 0x00000007U +#define MAC_DMA_TXCFG__DMA_SIZE__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define MAC_DMA_TXCFG__DMA_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MAC_DMA_TXCFG__DMA_SIZE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field TRIGLVL */ +#define MAC_DMA_TXCFG__TRIGLVL__SHIFT 4 +#define MAC_DMA_TXCFG__TRIGLVL__WIDTH 6 +#define MAC_DMA_TXCFG__TRIGLVL__MASK 0x000003f0U +#define MAC_DMA_TXCFG__TRIGLVL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define MAC_DMA_TXCFG__TRIGLVL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define MAC_DMA_TXCFG__TRIGLVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define MAC_DMA_TXCFG__TRIGLVL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field JUMBO_EN */ +#define MAC_DMA_TXCFG__JUMBO_EN__SHIFT 10 +#define MAC_DMA_TXCFG__JUMBO_EN__WIDTH 1 +#define MAC_DMA_TXCFG__JUMBO_EN__MASK 0x00000400U +#define MAC_DMA_TXCFG__JUMBO_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_DMA_TXCFG__JUMBO_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_DMA_TXCFG__JUMBO_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_DMA_TXCFG__JUMBO_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_DMA_TXCFG__JUMBO_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_DMA_TXCFG__JUMBO_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field BCN_PAST_ATIM_DIS */ +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__SHIFT 11 +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WIDTH 1 +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MASK 0x00000800U +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field ATIM_DEFER_DIS */ +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__SHIFT 12 +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WIDTH 1 +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MASK 0x00001000U +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field RTCI_DIS */ +#define MAC_DMA_TXCFG__RTCI_DIS__SHIFT 14 +#define MAC_DMA_TXCFG__RTCI_DIS__WIDTH 1 +#define MAC_DMA_TXCFG__RTCI_DIS__MASK 0x00004000U +#define MAC_DMA_TXCFG__RTCI_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define MAC_DMA_TXCFG__RTCI_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define MAC_DMA_TXCFG__RTCI_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define MAC_DMA_TXCFG__RTCI_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define MAC_DMA_TXCFG__RTCI_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define MAC_DMA_TXCFG__RTCI_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field DIS_RETRY_UNDERRUN */ +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__SHIFT 17 +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WIDTH 1 +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MASK 0x00020000U +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field DIS_CW_INC_QUIET_COLL */ +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__SHIFT 18 +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WIDTH 1 +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MASK 0x00040000U +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) +#define MAC_DMA_TXCFG__TYPE u_int32_t +#define MAC_DMA_TXCFG__READ 0x00065ff7U +#define MAC_DMA_TXCFG__WRITE 0x00065ff7U + +#endif /* __MAC_DMA_TXCFG_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_TXCFG */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_TXCFG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXCFG */ +#ifndef __MAC_DMA_RXCFG_MACRO__ +#define __MAC_DMA_RXCFG_MACRO__ + +/* macros for field DMA_SIZE */ +#define MAC_DMA_RXCFG__DMA_SIZE__SHIFT 0 +#define MAC_DMA_RXCFG__DMA_SIZE__WIDTH 3 +#define MAC_DMA_RXCFG__DMA_SIZE__MASK 0x00000007U +#define MAC_DMA_RXCFG__DMA_SIZE__READ(src) (u_int32_t)(src) & 0x00000007U +#define MAC_DMA_RXCFG__DMA_SIZE__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define MAC_DMA_RXCFG__DMA_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MAC_DMA_RXCFG__DMA_SIZE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field ZERO_LEN_DMA_EN */ +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__SHIFT 3 +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WIDTH 2 +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MASK 0x00000018U +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000018U) >> 3) +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000018U) +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000018U) | (((u_int32_t)(src) <<\ + 3) & 0x00000018U) +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000018U))) + +/* macros for field JUMBO_EN */ +#define MAC_DMA_RXCFG__JUMBO_EN__SHIFT 5 +#define MAC_DMA_RXCFG__JUMBO_EN__WIDTH 1 +#define MAC_DMA_RXCFG__JUMBO_EN__MASK 0x00000020U +#define MAC_DMA_RXCFG__JUMBO_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_DMA_RXCFG__JUMBO_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_DMA_RXCFG__JUMBO_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_DMA_RXCFG__JUMBO_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_DMA_RXCFG__JUMBO_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_DMA_RXCFG__JUMBO_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field JUMBO_WRAP_EN */ +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__SHIFT 6 +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WIDTH 1 +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MASK 0x00000040U +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field SLEEP_RX_PEND_EN */ +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__SHIFT 7 +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WIDTH 1 +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MASK 0x00000080U +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) +#define MAC_DMA_RXCFG__TYPE u_int32_t +#define MAC_DMA_RXCFG__READ 0x000000ffU +#define MAC_DMA_RXCFG__WRITE 0x000000ffU + +#endif /* __MAC_DMA_RXCFG_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_RXCFG */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_RXCFG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXJLA */ +#ifndef __MAC_DMA_RXJLA_MACRO__ +#define __MAC_DMA_RXJLA_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_RXJLA__DATA__SHIFT 2 +#define MAC_DMA_RXJLA__DATA__WIDTH 30 +#define MAC_DMA_RXJLA__DATA__MASK 0xfffffffcU +#define MAC_DMA_RXJLA__DATA__READ(src) (((u_int32_t)(src) & 0xfffffffcU) >> 2) +#define MAC_DMA_RXJLA__TYPE u_int32_t +#define MAC_DMA_RXJLA__READ 0xfffffffcU + +#endif /* __MAC_DMA_RXJLA_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_RXJLA */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_RXJLA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_MIBC */ +#ifndef __MAC_DMA_MIBC_MACRO__ +#define __MAC_DMA_MIBC_MACRO__ + +/* macros for field WARNING */ +#define MAC_DMA_MIBC__WARNING__SHIFT 0 +#define MAC_DMA_MIBC__WARNING__WIDTH 1 +#define MAC_DMA_MIBC__WARNING__MASK 0x00000001U +#define MAC_DMA_MIBC__WARNING__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_DMA_MIBC__WARNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DMA_MIBC__WARNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field FREEZE */ +#define MAC_DMA_MIBC__FREEZE__SHIFT 1 +#define MAC_DMA_MIBC__FREEZE__WIDTH 1 +#define MAC_DMA_MIBC__FREEZE__MASK 0x00000002U +#define MAC_DMA_MIBC__FREEZE__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define MAC_DMA_MIBC__FREEZE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_DMA_MIBC__FREEZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_DMA_MIBC__FREEZE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_DMA_MIBC__FREEZE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_DMA_MIBC__FREEZE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field CLEAR */ +#define MAC_DMA_MIBC__CLEAR__SHIFT 2 +#define MAC_DMA_MIBC__CLEAR__WIDTH 1 +#define MAC_DMA_MIBC__CLEAR__MASK 0x00000004U +#define MAC_DMA_MIBC__CLEAR__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define MAC_DMA_MIBC__CLEAR__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define MAC_DMA_MIBC__CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_DMA_MIBC__CLEAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_DMA_MIBC__CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_DMA_MIBC__CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field STROBE */ +#define MAC_DMA_MIBC__STROBE__SHIFT 3 +#define MAC_DMA_MIBC__STROBE__WIDTH 1 +#define MAC_DMA_MIBC__STROBE__MASK 0x00000008U +#define MAC_DMA_MIBC__STROBE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define MAC_DMA_MIBC__STROBE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_DMA_MIBC__STROBE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define MAC_DMA_MIBC__TYPE u_int32_t +#define MAC_DMA_MIBC__READ 0x0000000fU +#define MAC_DMA_MIBC__WRITE 0x0000000fU + +#endif /* __MAC_DMA_MIBC_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_MIBC */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_MIBC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TOPS */ +#ifndef __MAC_DMA_TOPS_MACRO__ +#define __MAC_DMA_TOPS_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_DMA_TOPS__TIMEOUT__SHIFT 0 +#define MAC_DMA_TOPS__TIMEOUT__WIDTH 16 +#define MAC_DMA_TOPS__TIMEOUT__MASK 0x0000ffffU +#define MAC_DMA_TOPS__TIMEOUT__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_DMA_TOPS__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_DMA_TOPS__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TOPS__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DMA_TOPS__TYPE u_int32_t +#define MAC_DMA_TOPS__READ 0x0000ffffU +#define MAC_DMA_TOPS__WRITE 0x0000ffffU + +#endif /* __MAC_DMA_TOPS_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_TOPS */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_TOPS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXNPTO */ +#ifndef __MAC_DMA_RXNPTO_MACRO__ +#define __MAC_DMA_RXNPTO_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_DMA_RXNPTO__TIMEOUT__SHIFT 0 +#define MAC_DMA_RXNPTO__TIMEOUT__WIDTH 10 +#define MAC_DMA_RXNPTO__TIMEOUT__MASK 0x000003ffU +#define MAC_DMA_RXNPTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DMA_RXNPTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DMA_RXNPTO__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DMA_RXNPTO__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_DMA_RXNPTO__TYPE u_int32_t +#define MAC_DMA_RXNPTO__READ 0x000003ffU +#define MAC_DMA_RXNPTO__WRITE 0x000003ffU + +#endif /* __MAC_DMA_RXNPTO_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_RXNPTO */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_RXNPTO__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXNPTO */ +#ifndef __MAC_DMA_TXNPTO_MACRO__ +#define __MAC_DMA_TXNPTO_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_DMA_TXNPTO__TIMEOUT__SHIFT 0 +#define MAC_DMA_TXNPTO__TIMEOUT__WIDTH 10 +#define MAC_DMA_TXNPTO__TIMEOUT__MASK 0x000003ffU +#define MAC_DMA_TXNPTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DMA_TXNPTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DMA_TXNPTO__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DMA_TXNPTO__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field MASK */ +#define MAC_DMA_TXNPTO__MASK__SHIFT 10 +#define MAC_DMA_TXNPTO__MASK__WIDTH 10 +#define MAC_DMA_TXNPTO__MASK__MASK 0x000ffc00U +#define MAC_DMA_TXNPTO__MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define MAC_DMA_TXNPTO__MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define MAC_DMA_TXNPTO__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define MAC_DMA_TXNPTO__MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define MAC_DMA_TXNPTO__TYPE u_int32_t +#define MAC_DMA_TXNPTO__READ 0x000fffffU +#define MAC_DMA_TXNPTO__WRITE 0x000fffffU + +#endif /* __MAC_DMA_TXNPTO_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_TXNPTO */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_TXNPTO__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RPGTO */ +#ifndef __MAC_DMA_RPGTO_MACRO__ +#define __MAC_DMA_RPGTO_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_DMA_RPGTO__TIMEOUT__SHIFT 0 +#define MAC_DMA_RPGTO__TIMEOUT__WIDTH 10 +#define MAC_DMA_RPGTO__TIMEOUT__MASK 0x000003ffU +#define MAC_DMA_RPGTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DMA_RPGTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DMA_RPGTO__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DMA_RPGTO__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_DMA_RPGTO__TYPE u_int32_t +#define MAC_DMA_RPGTO__READ 0x000003ffU +#define MAC_DMA_RPGTO__WRITE 0x000003ffU + +#endif /* __MAC_DMA_RPGTO_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_RPGTO */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_RPGTO__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_MACMISC */ +#ifndef __MAC_DMA_MACMISC_MACRO__ +#define __MAC_DMA_MACMISC_MACRO__ + +/* macros for field FORCE_PCI_EXT */ +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__SHIFT 4 +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__WIDTH 1 +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__MASK 0x00000010U +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field DMA_OBS_MUXSEL */ +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__SHIFT 5 +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WIDTH 4 +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MASK 0x000001e0U +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001e0U) >> 5) +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000001e0U) +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000001e0U) +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000001e0U))) + +/* macros for field MISC_OBS_MUXSEL */ +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__SHIFT 9 +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WIDTH 3 +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MASK 0x00000e00U +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000e00U) >> 9) +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field MISC_F2_OBS_LOW_MUXSEL */ +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__SHIFT 12 +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WIDTH 3 +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MASK 0x00007000U +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007000U) >> 12) +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00007000U) +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field MISC_F2_OBS_HIGH_MUXSEL */ +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__SHIFT 15 +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WIDTH 3 +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MASK 0x00038000U +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00038000U) >> 15) +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00038000U) +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) +#define MAC_DMA_MACMISC__TYPE u_int32_t +#define MAC_DMA_MACMISC__READ 0x0003fff0U +#define MAC_DMA_MACMISC__WRITE 0x0003fff0U + +#endif /* __MAC_DMA_MACMISC_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_MACMISC */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_MACMISC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_INTER */ +#ifndef __MAC_DMA_INTER_MACRO__ +#define __MAC_DMA_INTER_MACRO__ + +/* macros for field REQ */ +#define MAC_DMA_INTER__REQ__SHIFT 0 +#define MAC_DMA_INTER__REQ__WIDTH 1 +#define MAC_DMA_INTER__REQ__MASK 0x00000001U +#define MAC_DMA_INTER__REQ__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_DMA_INTER__REQ__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_DMA_INTER__REQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_DMA_INTER__REQ__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define MAC_DMA_INTER__REQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DMA_INTER__REQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field MSI_RX_SRC */ +#define MAC_DMA_INTER__MSI_RX_SRC__SHIFT 1 +#define MAC_DMA_INTER__MSI_RX_SRC__WIDTH 2 +#define MAC_DMA_INTER__MSI_RX_SRC__MASK 0x00000006U +#define MAC_DMA_INTER__MSI_RX_SRC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000006U) >> 1) +#define MAC_DMA_INTER__MSI_RX_SRC__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000006U) +#define MAC_DMA_INTER__MSI_RX_SRC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((u_int32_t)(src) <<\ + 1) & 0x00000006U) +#define MAC_DMA_INTER__MSI_RX_SRC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000006U))) + +/* macros for field MSI_TX_SRC */ +#define MAC_DMA_INTER__MSI_TX_SRC__SHIFT 3 +#define MAC_DMA_INTER__MSI_TX_SRC__WIDTH 2 +#define MAC_DMA_INTER__MSI_TX_SRC__MASK 0x00000018U +#define MAC_DMA_INTER__MSI_TX_SRC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000018U) >> 3) +#define MAC_DMA_INTER__MSI_TX_SRC__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000018U) +#define MAC_DMA_INTER__MSI_TX_SRC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000018U) | (((u_int32_t)(src) <<\ + 3) & 0x00000018U) +#define MAC_DMA_INTER__MSI_TX_SRC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000018U))) +#define MAC_DMA_INTER__TYPE u_int32_t +#define MAC_DMA_INTER__READ 0x0000001fU +#define MAC_DMA_INTER__WRITE 0x0000001fU + +#endif /* __MAC_DMA_INTER_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_INTER */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_INTER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DATABUF */ +#ifndef __MAC_DMA_DATABUF_MACRO__ +#define __MAC_DMA_DATABUF_MACRO__ + +/* macros for field LEN */ +#define MAC_DMA_DATABUF__LEN__SHIFT 0 +#define MAC_DMA_DATABUF__LEN__WIDTH 12 +#define MAC_DMA_DATABUF__LEN__MASK 0x00000fffU +#define MAC_DMA_DATABUF__LEN__READ(src) (u_int32_t)(src) & 0x00000fffU +#define MAC_DMA_DATABUF__LEN__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) +#define MAC_DMA_DATABUF__LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define MAC_DMA_DATABUF__LEN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) +#define MAC_DMA_DATABUF__TYPE u_int32_t +#define MAC_DMA_DATABUF__READ 0x00000fffU +#define MAC_DMA_DATABUF__WRITE 0x00000fffU + +#endif /* __MAC_DMA_DATABUF_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_DATABUF */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_DATABUF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_GTT */ +#ifndef __MAC_DMA_GTT_MACRO__ +#define __MAC_DMA_GTT_MACRO__ + +/* macros for field COUNT */ +#define MAC_DMA_GTT__COUNT__SHIFT 0 +#define MAC_DMA_GTT__COUNT__WIDTH 16 +#define MAC_DMA_GTT__COUNT__MASK 0x0000ffffU +#define MAC_DMA_GTT__COUNT__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_DMA_GTT__COUNT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_DMA_GTT__COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_GTT__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU))) + +/* macros for field LIMIT */ +#define MAC_DMA_GTT__LIMIT__SHIFT 16 +#define MAC_DMA_GTT__LIMIT__WIDTH 16 +#define MAC_DMA_GTT__LIMIT__MASK 0xffff0000U +#define MAC_DMA_GTT__LIMIT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16) +#define MAC_DMA_GTT__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U) +#define MAC_DMA_GTT__LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_GTT__LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_GTT__TYPE u_int32_t +#define MAC_DMA_GTT__READ 0xffffffffU +#define MAC_DMA_GTT__WRITE 0xffffffffU + +#endif /* __MAC_DMA_GTT_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_GTT */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_GTT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_GTTM */ +#ifndef __MAC_DMA_GTTM_MACRO__ +#define __MAC_DMA_GTTM_MACRO__ + +/* macros for field USEC_STROBE */ +#define MAC_DMA_GTTM__USEC_STROBE__SHIFT 0 +#define MAC_DMA_GTTM__USEC_STROBE__WIDTH 1 +#define MAC_DMA_GTTM__USEC_STROBE__MASK 0x00000001U +#define MAC_DMA_GTTM__USEC_STROBE__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_DMA_GTTM__USEC_STROBE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_DMA_GTTM__USEC_STROBE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_DMA_GTTM__USEC_STROBE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_DMA_GTTM__USEC_STROBE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DMA_GTTM__USEC_STROBE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field IGNORE_CHAN_IDLE */ +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__SHIFT 1 +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WIDTH 1 +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MASK 0x00000002U +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field RESET_ON_CHAN_IDLE */ +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__SHIFT 2 +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WIDTH 1 +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MASK 0x00000004U +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field CST_USEC_STROBE */ +#define MAC_DMA_GTTM__CST_USEC_STROBE__SHIFT 3 +#define MAC_DMA_GTTM__CST_USEC_STROBE__WIDTH 1 +#define MAC_DMA_GTTM__CST_USEC_STROBE__MASK 0x00000008U +#define MAC_DMA_GTTM__CST_USEC_STROBE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_DMA_GTTM__CST_USEC_STROBE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_DMA_GTTM__CST_USEC_STROBE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_DMA_GTTM__CST_USEC_STROBE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_DMA_GTTM__CST_USEC_STROBE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_DMA_GTTM__CST_USEC_STROBE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field DISABLE_QCU_FR_ACTIVE_GTT */ +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__SHIFT 4 +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WIDTH 1 +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MASK 0x00000010U +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field DISABLE_QCU_FR_ACTIVE_BT */ +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__SHIFT 5 +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WIDTH 1 +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MASK 0x00000020U +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define MAC_DMA_GTTM__TYPE u_int32_t +#define MAC_DMA_GTTM__READ 0x0000003fU +#define MAC_DMA_GTTM__WRITE 0x0000003fU + +#endif /* __MAC_DMA_GTTM_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_GTTM */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_GTTM__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_CST */ +#ifndef __MAC_DMA_CST_MACRO__ +#define __MAC_DMA_CST_MACRO__ + +/* macros for field COUNT */ +#define MAC_DMA_CST__COUNT__SHIFT 0 +#define MAC_DMA_CST__COUNT__WIDTH 16 +#define MAC_DMA_CST__COUNT__MASK 0x0000ffffU +#define MAC_DMA_CST__COUNT__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_DMA_CST__COUNT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_DMA_CST__COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_CST__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU))) + +/* macros for field LIMIT */ +#define MAC_DMA_CST__LIMIT__SHIFT 16 +#define MAC_DMA_CST__LIMIT__WIDTH 16 +#define MAC_DMA_CST__LIMIT__MASK 0xffff0000U +#define MAC_DMA_CST__LIMIT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16) +#define MAC_DMA_CST__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U) +#define MAC_DMA_CST__LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_CST__LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_CST__TYPE u_int32_t +#define MAC_DMA_CST__READ 0xffffffffU +#define MAC_DMA_CST__WRITE 0xffffffffU + +#endif /* __MAC_DMA_CST_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_CST */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_CST__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXDP_SIZE */ +#ifndef __MAC_DMA_RXDP_SIZE_MACRO__ +#define __MAC_DMA_RXDP_SIZE_MACRO__ + +/* macros for field LP */ +#define MAC_DMA_RXDP_SIZE__LP__SHIFT 0 +#define MAC_DMA_RXDP_SIZE__LP__WIDTH 8 +#define MAC_DMA_RXDP_SIZE__LP__MASK 0x000000ffU +#define MAC_DMA_RXDP_SIZE__LP__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field HP */ +#define MAC_DMA_RXDP_SIZE__HP__SHIFT 8 +#define MAC_DMA_RXDP_SIZE__HP__WIDTH 5 +#define MAC_DMA_RXDP_SIZE__HP__MASK 0x00001f00U +#define MAC_DMA_RXDP_SIZE__HP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define MAC_DMA_RXDP_SIZE__TYPE u_int32_t +#define MAC_DMA_RXDP_SIZE__READ 0x00001fffU + +#endif /* __MAC_DMA_RXDP_SIZE_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_RXDP_SIZE */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_RXDP_SIZE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RX_QUEUE_HP_RXDP */ +#ifndef __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__ +#define __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__ + +/* macros for field ADDR */ +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__SHIFT 0 +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WIDTH 32 +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MASK 0xffffffffU +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_RX_QUEUE_HP_RXDP__TYPE u_int32_t +#define MAC_DMA_RX_QUEUE_HP_RXDP__READ 0xffffffffU +#define MAC_DMA_RX_QUEUE_HP_RXDP__WRITE 0xffffffffU + +#endif /* __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_RX_QUEUE_HP_RXDP */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_RX_QUEUE_HP_RXDP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RX_QUEUE_LP_RXDP */ +#ifndef __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__ +#define __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__ + +/* macros for field ADDR */ +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__SHIFT 0 +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WIDTH 32 +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MASK 0xffffffffU +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_RX_QUEUE_LP_RXDP__TYPE u_int32_t +#define MAC_DMA_RX_QUEUE_LP_RXDP__READ 0xffffffffU +#define MAC_DMA_RX_QUEUE_LP_RXDP__WRITE 0xffffffffU + +#endif /* __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_RX_QUEUE_LP_RXDP */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_RX_QUEUE_LP_RXDP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_P */ +#ifndef __MAC_DMA_ISR_P_MACRO__ +#define __MAC_DMA_ISR_P_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_P__DATA__SHIFT 0 +#define MAC_DMA_ISR_P__DATA__WIDTH 32 +#define MAC_DMA_ISR_P__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_P__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_P__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_P__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_P__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define MAC_DMA_ISR_P__TYPE u_int32_t +#define MAC_DMA_ISR_P__READ 0xffffffffU +#define MAC_DMA_ISR_P__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_P_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_P */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_P__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S0 */ +#ifndef __MAC_DMA_ISR_S0_MACRO__ +#define __MAC_DMA_ISR_S0_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S0__DATA__SHIFT 0 +#define MAC_DMA_ISR_S0__DATA__WIDTH 32 +#define MAC_DMA_ISR_S0__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S0__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S0__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S0__TYPE u_int32_t +#define MAC_DMA_ISR_S0__READ 0xffffffffU +#define MAC_DMA_ISR_S0__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S0_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S0 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S1 */ +#ifndef __MAC_DMA_ISR_S1_MACRO__ +#define __MAC_DMA_ISR_S1_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S1__DATA__SHIFT 0 +#define MAC_DMA_ISR_S1__DATA__WIDTH 32 +#define MAC_DMA_ISR_S1__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S1__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S1__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S1__TYPE u_int32_t +#define MAC_DMA_ISR_S1__READ 0xffffffffU +#define MAC_DMA_ISR_S1__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S1_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S1 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S2 */ +#ifndef __MAC_DMA_ISR_S2_MACRO__ +#define __MAC_DMA_ISR_S2_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S2__DATA__SHIFT 0 +#define MAC_DMA_ISR_S2__DATA__WIDTH 32 +#define MAC_DMA_ISR_S2__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S2__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S2__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S2__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S2__TYPE u_int32_t +#define MAC_DMA_ISR_S2__READ 0xffffffffU +#define MAC_DMA_ISR_S2__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S2_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S2 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S3 */ +#ifndef __MAC_DMA_ISR_S3_MACRO__ +#define __MAC_DMA_ISR_S3_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S3__DATA__SHIFT 0 +#define MAC_DMA_ISR_S3__DATA__WIDTH 32 +#define MAC_DMA_ISR_S3__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S3__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S3__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S3__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S3__TYPE u_int32_t +#define MAC_DMA_ISR_S3__READ 0xffffffffU +#define MAC_DMA_ISR_S3__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S3_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S3 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S4 */ +#ifndef __MAC_DMA_ISR_S4_MACRO__ +#define __MAC_DMA_ISR_S4_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S4__DATA__SHIFT 0 +#define MAC_DMA_ISR_S4__DATA__WIDTH 32 +#define MAC_DMA_ISR_S4__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S4__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S4__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S4__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S4__TYPE u_int32_t +#define MAC_DMA_ISR_S4__READ 0xffffffffU +#define MAC_DMA_ISR_S4__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S4_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S4 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S5 */ +#ifndef __MAC_DMA_ISR_S5_MACRO__ +#define __MAC_DMA_ISR_S5_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S5__DATA__SHIFT 0 +#define MAC_DMA_ISR_S5__DATA__WIDTH 32 +#define MAC_DMA_ISR_S5__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S5__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S5__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S5__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S5__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S5__TYPE u_int32_t +#define MAC_DMA_ISR_S5__READ 0xffffffffU +#define MAC_DMA_ISR_S5__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S5_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S5 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_P */ +#ifndef __MAC_DMA_IMR_P_MACRO__ +#define __MAC_DMA_IMR_P_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_P__MASK__SHIFT 0 +#define MAC_DMA_IMR_P__MASK__WIDTH 32 +#define MAC_DMA_IMR_P__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_P__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_P__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_P__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_P__MASK__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define MAC_DMA_IMR_P__TYPE u_int32_t +#define MAC_DMA_IMR_P__READ 0xffffffffU +#define MAC_DMA_IMR_P__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_P_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_IMR_P */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_IMR_P__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S0 */ +#ifndef __MAC_DMA_IMR_S0_MACRO__ +#define __MAC_DMA_IMR_S0_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_S0__MASK__SHIFT 0 +#define MAC_DMA_IMR_S0__MASK__WIDTH 32 +#define MAC_DMA_IMR_S0__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_S0__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S0__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S0__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S0__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S0__TYPE u_int32_t +#define MAC_DMA_IMR_S0__READ 0xffffffffU +#define MAC_DMA_IMR_S0__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S0_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_IMR_S0 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_IMR_S0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S1 */ +#ifndef __MAC_DMA_IMR_S1_MACRO__ +#define __MAC_DMA_IMR_S1_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_IMR_S1__DATA__SHIFT 0 +#define MAC_DMA_IMR_S1__DATA__WIDTH 32 +#define MAC_DMA_IMR_S1__DATA__MASK 0xffffffffU +#define MAC_DMA_IMR_S1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S1__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S1__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S1__TYPE u_int32_t +#define MAC_DMA_IMR_S1__READ 0xffffffffU +#define MAC_DMA_IMR_S1__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S1_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_IMR_S1 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_IMR_S1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S2 */ +#ifndef __MAC_DMA_IMR_S2_MACRO__ +#define __MAC_DMA_IMR_S2_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_S2__MASK__SHIFT 0 +#define MAC_DMA_IMR_S2__MASK__WIDTH 32 +#define MAC_DMA_IMR_S2__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_S2__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S2__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S2__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S2__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S2__TYPE u_int32_t +#define MAC_DMA_IMR_S2__READ 0xffffffffU +#define MAC_DMA_IMR_S2__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S2_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_IMR_S2 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_IMR_S2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S3 */ +#ifndef __MAC_DMA_IMR_S3_MACRO__ +#define __MAC_DMA_IMR_S3_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_S3__MASK__SHIFT 0 +#define MAC_DMA_IMR_S3__MASK__WIDTH 32 +#define MAC_DMA_IMR_S3__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_S3__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S3__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S3__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S3__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S3__TYPE u_int32_t +#define MAC_DMA_IMR_S3__READ 0xffffffffU +#define MAC_DMA_IMR_S3__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S3_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_IMR_S3 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_IMR_S3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S4 */ +#ifndef __MAC_DMA_IMR_S4_MACRO__ +#define __MAC_DMA_IMR_S4_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_S4__MASK__SHIFT 0 +#define MAC_DMA_IMR_S4__MASK__WIDTH 32 +#define MAC_DMA_IMR_S4__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_S4__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S4__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S4__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S4__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S4__TYPE u_int32_t +#define MAC_DMA_IMR_S4__READ 0xffffffffU +#define MAC_DMA_IMR_S4__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S4_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_IMR_S4 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_IMR_S4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S5 */ +#ifndef __MAC_DMA_IMR_S5_MACRO__ +#define __MAC_DMA_IMR_S5_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_S5__MASK__SHIFT 0 +#define MAC_DMA_IMR_S5__MASK__WIDTH 32 +#define MAC_DMA_IMR_S5__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_S5__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S5__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S5__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S5__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S5__TYPE u_int32_t +#define MAC_DMA_IMR_S5__READ 0xffffffffU +#define MAC_DMA_IMR_S5__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S5_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_IMR_S5 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_IMR_S5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_P_RAC */ +#ifndef __MAC_DMA_ISR_P_RAC_MACRO__ +#define __MAC_DMA_ISR_P_RAC_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_P_RAC__DATA__SHIFT 0 +#define MAC_DMA_ISR_P_RAC__DATA__WIDTH 32 +#define MAC_DMA_ISR_P_RAC__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_P_RAC__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_P_RAC__TYPE u_int32_t +#define MAC_DMA_ISR_P_RAC__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_P_RAC_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_P_RAC */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_P_RAC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S0_S */ +#ifndef __MAC_DMA_ISR_S0_S_MACRO__ +#define __MAC_DMA_ISR_S0_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S0_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S0_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S0_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S0_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S0_S__TYPE u_int32_t +#define MAC_DMA_ISR_S0_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S0_S_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S0_S */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S0_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S1_S */ +#ifndef __MAC_DMA_ISR_S1_S_MACRO__ +#define __MAC_DMA_ISR_S1_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S1_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S1_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S1_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S1_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S1_S__TYPE u_int32_t +#define MAC_DMA_ISR_S1_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S1_S_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S1_S */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S1_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S2_S */ +#ifndef __MAC_DMA_ISR_S2_S_MACRO__ +#define __MAC_DMA_ISR_S2_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S2_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S2_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S2_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S2_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S2_S__TYPE u_int32_t +#define MAC_DMA_ISR_S2_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S2_S_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S2_S */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S2_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S3_S */ +#ifndef __MAC_DMA_ISR_S3_S_MACRO__ +#define __MAC_DMA_ISR_S3_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S3_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S3_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S3_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S3_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S3_S__TYPE u_int32_t +#define MAC_DMA_ISR_S3_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S3_S_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S3_S */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S3_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S4_S */ +#ifndef __MAC_DMA_ISR_S4_S_MACRO__ +#define __MAC_DMA_ISR_S4_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S4_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S4_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S4_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S4_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S4_S__TYPE u_int32_t +#define MAC_DMA_ISR_S4_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S4_S_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S4_S */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S4_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S5_S */ +#ifndef __MAC_DMA_ISR_S5_S_MACRO__ +#define __MAC_DMA_ISR_S5_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S5_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S5_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S5_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S5_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S5_S__TYPE u_int32_t +#define MAC_DMA_ISR_S5_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S5_S_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_ISR_S5_S */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_ISR_S5_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_0 */ +#ifndef __MAC_DMA_DMADBG_0_MACRO__ +#define __MAC_DMA_DMADBG_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_0__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_0__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_0__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_0__TYPE u_int32_t +#define MAC_DMA_DMADBG_0__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_0_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_DMADBG_0 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_DMADBG_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_1 */ +#ifndef __MAC_DMA_DMADBG_1_MACRO__ +#define __MAC_DMA_DMADBG_1_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_1__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_1__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_1__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_1__TYPE u_int32_t +#define MAC_DMA_DMADBG_1__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_1_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_DMADBG_1 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_DMADBG_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_2 */ +#ifndef __MAC_DMA_DMADBG_2_MACRO__ +#define __MAC_DMA_DMADBG_2_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_2__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_2__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_2__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_2__TYPE u_int32_t +#define MAC_DMA_DMADBG_2__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_2_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_DMADBG_2 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_DMADBG_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_3 */ +#ifndef __MAC_DMA_DMADBG_3_MACRO__ +#define __MAC_DMA_DMADBG_3_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_3__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_3__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_3__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_3__TYPE u_int32_t +#define MAC_DMA_DMADBG_3__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_3_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_DMADBG_3 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_DMADBG_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_4 */ +#ifndef __MAC_DMA_DMADBG_4_MACRO__ +#define __MAC_DMA_DMADBG_4_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_4__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_4__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_4__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_4__TYPE u_int32_t +#define MAC_DMA_DMADBG_4__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_4_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_DMADBG_4 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_DMADBG_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_5 */ +#ifndef __MAC_DMA_DMADBG_5_MACRO__ +#define __MAC_DMA_DMADBG_5_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_5__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_5__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_5__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_5__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_5__TYPE u_int32_t +#define MAC_DMA_DMADBG_5__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_5_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_DMADBG_5 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_DMADBG_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_6 */ +#ifndef __MAC_DMA_DMADBG_6_MACRO__ +#define __MAC_DMA_DMADBG_6_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_6__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_6__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_6__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_6__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_6__TYPE u_int32_t +#define MAC_DMA_DMADBG_6__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_6_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_DMADBG_6 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_DMADBG_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_7 */ +#ifndef __MAC_DMA_DMADBG_7_MACRO__ +#define __MAC_DMA_DMADBG_7_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_7__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_7__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_7__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_7__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_7__TYPE u_int32_t +#define MAC_DMA_DMADBG_7__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_7_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_DMADBG_7 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_DMADBG_7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0 */ +#ifndef __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__ +#define __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__SHIFT 0 +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__WIDTH 32 +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__MASK 0xffffffffU +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__TYPE u_int32_t +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__READ 0xffffffffU + +#endif /* __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8 */ +#ifndef __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__ +#define __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__SHIFT 0 +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__WIDTH 8 +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__MASK 0x000000ffU +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__TYPE u_int32_t +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__READ 0x000000ffU + +#endif /* __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__ */ + + +/* macros for mac_dma_reg_block.MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8 */ +#define INST_MAC_DMA_REG_BLOCK__MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXDP */ +#ifndef __MAC_QCU_TXDP_MACRO__ +#define __MAC_QCU_TXDP_MACRO__ + +/* macros for field DATA */ +#define MAC_QCU_TXDP__DATA__SHIFT 0 +#define MAC_QCU_TXDP__DATA__WIDTH 32 +#define MAC_QCU_TXDP__DATA__MASK 0xffffffffU +#define MAC_QCU_TXDP__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_QCU_TXDP__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_QCU_TXDP__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_QCU_TXDP__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define MAC_QCU_TXDP__TYPE u_int32_t +#define MAC_QCU_TXDP__READ 0xffffffffU +#define MAC_QCU_TXDP__WRITE 0xffffffffU + +#endif /* __MAC_QCU_TXDP_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_TXDP */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_TXDP__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_START */ +#ifndef __MAC_QCU_STATUS_RING_START_MACRO__ +#define __MAC_QCU_STATUS_RING_START_MACRO__ + +/* macros for field ADDR */ +#define MAC_QCU_STATUS_RING_START__ADDR__SHIFT 0 +#define MAC_QCU_STATUS_RING_START__ADDR__WIDTH 32 +#define MAC_QCU_STATUS_RING_START__ADDR__MASK 0xffffffffU +#define MAC_QCU_STATUS_RING_START__ADDR__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_QCU_STATUS_RING_START__ADDR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_QCU_STATUS_RING_START__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_QCU_STATUS_RING_START__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_QCU_STATUS_RING_START__TYPE u_int32_t +#define MAC_QCU_STATUS_RING_START__READ 0xffffffffU +#define MAC_QCU_STATUS_RING_START__WRITE 0xffffffffU + +#endif /* __MAC_QCU_STATUS_RING_START_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_STATUS_RING_START */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_STATUS_RING_START__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_END */ +#ifndef __MAC_QCU_STATUS_RING_END_MACRO__ +#define __MAC_QCU_STATUS_RING_END_MACRO__ + +/* macros for field ADDR */ +#define MAC_QCU_STATUS_RING_END__ADDR__SHIFT 0 +#define MAC_QCU_STATUS_RING_END__ADDR__WIDTH 32 +#define MAC_QCU_STATUS_RING_END__ADDR__MASK 0xffffffffU +#define MAC_QCU_STATUS_RING_END__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_QCU_STATUS_RING_END__ADDR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_QCU_STATUS_RING_END__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_QCU_STATUS_RING_END__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_QCU_STATUS_RING_END__TYPE u_int32_t +#define MAC_QCU_STATUS_RING_END__READ 0xffffffffU +#define MAC_QCU_STATUS_RING_END__WRITE 0xffffffffU + +#endif /* __MAC_QCU_STATUS_RING_END_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_STATUS_RING_END */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_STATUS_RING_END__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_CURRENT */ +#ifndef __MAC_QCU_STATUS_RING_CURRENT_MACRO__ +#define __MAC_QCU_STATUS_RING_CURRENT_MACRO__ + +/* macros for field ADDRESS */ +#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__SHIFT 0 +#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__WIDTH 32 +#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__MASK 0xffffffffU +#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_QCU_STATUS_RING_CURRENT__TYPE u_int32_t +#define MAC_QCU_STATUS_RING_CURRENT__READ 0xffffffffU + +#endif /* __MAC_QCU_STATUS_RING_CURRENT_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_STATUS_RING_CURRENT */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_STATUS_RING_CURRENT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXE */ +#ifndef __MAC_QCU_TXE_MACRO__ +#define __MAC_QCU_TXE_MACRO__ + +/* macros for field DATA */ +#define MAC_QCU_TXE__DATA__SHIFT 0 +#define MAC_QCU_TXE__DATA__WIDTH 10 +#define MAC_QCU_TXE__DATA__MASK 0x000003ffU +#define MAC_QCU_TXE__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_QCU_TXE__TYPE u_int32_t +#define MAC_QCU_TXE__READ 0x000003ffU + +#endif /* __MAC_QCU_TXE_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_TXE */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_TXE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXD */ +#ifndef __MAC_QCU_TXD_MACRO__ +#define __MAC_QCU_TXD_MACRO__ + +/* macros for field DATA */ +#define MAC_QCU_TXD__DATA__SHIFT 0 +#define MAC_QCU_TXD__DATA__WIDTH 10 +#define MAC_QCU_TXD__DATA__MASK 0x000003ffU +#define MAC_QCU_TXD__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_QCU_TXD__DATA__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_QCU_TXD__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_QCU_TXD__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU))) +#define MAC_QCU_TXD__TYPE u_int32_t +#define MAC_QCU_TXD__READ 0x000003ffU +#define MAC_QCU_TXD__WRITE 0x000003ffU + +#endif /* __MAC_QCU_TXD_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_TXD */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_TXD__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_CBR */ +#ifndef __MAC_QCU_CBR_MACRO__ +#define __MAC_QCU_CBR_MACRO__ + +/* macros for field INTERVAL */ +#define MAC_QCU_CBR__INTERVAL__SHIFT 0 +#define MAC_QCU_CBR__INTERVAL__WIDTH 24 +#define MAC_QCU_CBR__INTERVAL__MASK 0x00ffffffU +#define MAC_QCU_CBR__INTERVAL__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_QCU_CBR__INTERVAL__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) +#define MAC_QCU_CBR__INTERVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_QCU_CBR__INTERVAL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) + +/* macros for field OVF_THRESH */ +#define MAC_QCU_CBR__OVF_THRESH__SHIFT 24 +#define MAC_QCU_CBR__OVF_THRESH__WIDTH 8 +#define MAC_QCU_CBR__OVF_THRESH__MASK 0xff000000U +#define MAC_QCU_CBR__OVF_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_QCU_CBR__OVF_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_QCU_CBR__OVF_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_QCU_CBR__OVF_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_QCU_CBR__TYPE u_int32_t +#define MAC_QCU_CBR__READ 0xffffffffU +#define MAC_QCU_CBR__WRITE 0xffffffffU + +#endif /* __MAC_QCU_CBR_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_CBR */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_CBR__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_RDYTIME */ +#ifndef __MAC_QCU_RDYTIME_MACRO__ +#define __MAC_QCU_RDYTIME_MACRO__ + +/* macros for field DURATION */ +#define MAC_QCU_RDYTIME__DURATION__SHIFT 0 +#define MAC_QCU_RDYTIME__DURATION__WIDTH 24 +#define MAC_QCU_RDYTIME__DURATION__MASK 0x00ffffffU +#define MAC_QCU_RDYTIME__DURATION__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_QCU_RDYTIME__DURATION__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) +#define MAC_QCU_RDYTIME__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_QCU_RDYTIME__DURATION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) + +/* macros for field EN */ +#define MAC_QCU_RDYTIME__EN__SHIFT 24 +#define MAC_QCU_RDYTIME__EN__WIDTH 1 +#define MAC_QCU_RDYTIME__EN__MASK 0x01000000U +#define MAC_QCU_RDYTIME__EN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define MAC_QCU_RDYTIME__EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_QCU_RDYTIME__EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_QCU_RDYTIME__EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_QCU_RDYTIME__EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_QCU_RDYTIME__EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define MAC_QCU_RDYTIME__TYPE u_int32_t +#define MAC_QCU_RDYTIME__READ 0x01ffffffU +#define MAC_QCU_RDYTIME__WRITE 0x01ffffffU + +#endif /* __MAC_QCU_RDYTIME_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_RDYTIME */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_RDYTIME__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_ONESHOT_ARM_SC */ +#ifndef __MAC_QCU_ONESHOT_ARM_SC_MACRO__ +#define __MAC_QCU_ONESHOT_ARM_SC_MACRO__ + +/* macros for field SET */ +#define MAC_QCU_ONESHOT_ARM_SC__SET__SHIFT 0 +#define MAC_QCU_ONESHOT_ARM_SC__SET__WIDTH 10 +#define MAC_QCU_ONESHOT_ARM_SC__SET__MASK 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_SC__SET__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_SC__SET__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define MAC_QCU_ONESHOT_ARM_SC__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_QCU_ONESHOT_ARM_SC__SET__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_QCU_ONESHOT_ARM_SC__TYPE u_int32_t +#define MAC_QCU_ONESHOT_ARM_SC__READ 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_SC__WRITE 0x000003ffU + +#endif /* __MAC_QCU_ONESHOT_ARM_SC_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_ONESHOT_ARM_SC */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_ONESHOT_ARM_SC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_ONESHOT_ARM_CC */ +#ifndef __MAC_QCU_ONESHOT_ARM_CC_MACRO__ +#define __MAC_QCU_ONESHOT_ARM_CC_MACRO__ + +/* macros for field CLEAR */ +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__SHIFT 0 +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WIDTH 10 +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MASK 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_QCU_ONESHOT_ARM_CC__TYPE u_int32_t +#define MAC_QCU_ONESHOT_ARM_CC__READ 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_CC__WRITE 0x000003ffU + +#endif /* __MAC_QCU_ONESHOT_ARM_CC_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_ONESHOT_ARM_CC */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_ONESHOT_ARM_CC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_MISC */ +#ifndef __MAC_QCU_MISC_MACRO__ +#define __MAC_QCU_MISC_MACRO__ + +/* macros for field FSP */ +#define MAC_QCU_MISC__FSP__SHIFT 0 +#define MAC_QCU_MISC__FSP__WIDTH 4 +#define MAC_QCU_MISC__FSP__MASK 0x0000000fU +#define MAC_QCU_MISC__FSP__READ(src) (u_int32_t)(src) & 0x0000000fU +#define MAC_QCU_MISC__FSP__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define MAC_QCU_MISC__FSP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_QCU_MISC__FSP__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) + +/* macros for field ONESHOT_EN */ +#define MAC_QCU_MISC__ONESHOT_EN__SHIFT 4 +#define MAC_QCU_MISC__ONESHOT_EN__WIDTH 1 +#define MAC_QCU_MISC__ONESHOT_EN__MASK 0x00000010U +#define MAC_QCU_MISC__ONESHOT_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_QCU_MISC__ONESHOT_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_QCU_MISC__ONESHOT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_QCU_MISC__ONESHOT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_QCU_MISC__ONESHOT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_QCU_MISC__ONESHOT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field CBR_EXP_INC_DIS_NOFR */ +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__SHIFT 5 +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WIDTH 1 +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MASK 0x00000020U +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field CBR_EXP_INC_DIS_NOBCNFR */ +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__SHIFT 6 +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WIDTH 1 +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MASK 0x00000040U +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field IS_BCN */ +#define MAC_QCU_MISC__IS_BCN__SHIFT 7 +#define MAC_QCU_MISC__IS_BCN__WIDTH 1 +#define MAC_QCU_MISC__IS_BCN__MASK 0x00000080U +#define MAC_QCU_MISC__IS_BCN__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define MAC_QCU_MISC__IS_BCN__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_QCU_MISC__IS_BCN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_QCU_MISC__IS_BCN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_QCU_MISC__IS_BCN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_QCU_MISC__IS_BCN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field CBR_EXP_INC_LIMIT */ +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__SHIFT 8 +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WIDTH 1 +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MASK 0x00000100U +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field TXE_CLR_ON_CBR_END */ +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__SHIFT 9 +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WIDTH 1 +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MASK 0x00000200U +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field MMR_CBR_EXP_CNT_CLR_EN */ +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__SHIFT 10 +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WIDTH 1 +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MASK 0x00000400U +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field FR_ABORT_REQ_EN */ +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__SHIFT 11 +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__WIDTH 1 +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__MASK 0x00000800U +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) +#define MAC_QCU_MISC__TYPE u_int32_t +#define MAC_QCU_MISC__READ 0x00000fffU +#define MAC_QCU_MISC__WRITE 0x00000fffU + +#endif /* __MAC_QCU_MISC_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_MISC */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_MISC__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_CNT */ +#ifndef __MAC_QCU_CNT_MACRO__ +#define __MAC_QCU_CNT_MACRO__ + +/* macros for field FR_PEND */ +#define MAC_QCU_CNT__FR_PEND__SHIFT 0 +#define MAC_QCU_CNT__FR_PEND__WIDTH 2 +#define MAC_QCU_CNT__FR_PEND__MASK 0x00000003U +#define MAC_QCU_CNT__FR_PEND__READ(src) (u_int32_t)(src) & 0x00000003U + +/* macros for field CBR_EXP */ +#define MAC_QCU_CNT__CBR_EXP__SHIFT 8 +#define MAC_QCU_CNT__CBR_EXP__WIDTH 8 +#define MAC_QCU_CNT__CBR_EXP__MASK 0x0000ff00U +#define MAC_QCU_CNT__CBR_EXP__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define MAC_QCU_CNT__TYPE u_int32_t +#define MAC_QCU_CNT__READ 0x0000ff03U + +#endif /* __MAC_QCU_CNT_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_CNT */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_CNT__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_RDYTIME_SHDN */ +#ifndef __MAC_QCU_RDYTIME_SHDN_MACRO__ +#define __MAC_QCU_RDYTIME_SHDN_MACRO__ + +/* macros for field SHUTDOWN */ +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__SHIFT 0 +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WIDTH 10 +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MASK 0x000003ffU +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_QCU_RDYTIME_SHDN__TYPE u_int32_t +#define MAC_QCU_RDYTIME_SHDN__READ 0x000003ffU +#define MAC_QCU_RDYTIME_SHDN__WRITE 0x000003ffU +#define MAC_QCU_RDYTIME_SHDN__WOCLR 0x000003ffU + +#endif /* __MAC_QCU_RDYTIME_SHDN_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_RDYTIME_SHDN */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_RDYTIME_SHDN__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_DESC_CRC_CHK */ +#ifndef __MAC_QCU_DESC_CRC_CHK_MACRO__ +#define __MAC_QCU_DESC_CRC_CHK_MACRO__ + +/* macros for field EN */ +#define MAC_QCU_DESC_CRC_CHK__EN__SHIFT 0 +#define MAC_QCU_DESC_CRC_CHK__EN__WIDTH 1 +#define MAC_QCU_DESC_CRC_CHK__EN__MASK 0x00000001U +#define MAC_QCU_DESC_CRC_CHK__EN__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_QCU_DESC_CRC_CHK__EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_QCU_DESC_CRC_CHK__EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_QCU_DESC_CRC_CHK__EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_QCU_DESC_CRC_CHK__EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_QCU_DESC_CRC_CHK__EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define MAC_QCU_DESC_CRC_CHK__TYPE u_int32_t +#define MAC_QCU_DESC_CRC_CHK__READ 0x00000001U +#define MAC_QCU_DESC_CRC_CHK__WRITE 0x00000001U + +#endif /* __MAC_QCU_DESC_CRC_CHK_MACRO__ */ + + +/* macros for mac_qcu_reg_block.MAC_QCU_DESC_CRC_CHK */ +#define INST_MAC_QCU_REG_BLOCK__MAC_QCU_DESC_CRC_CHK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_QCUMASK */ +#ifndef __MAC_DCU_QCUMASK_MACRO__ +#define __MAC_DCU_QCUMASK_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_QCUMASK__DATA__SHIFT 0 +#define MAC_DCU_QCUMASK__DATA__WIDTH 10 +#define MAC_DCU_QCUMASK__DATA__MASK 0x000003ffU +#define MAC_DCU_QCUMASK__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DCU_QCUMASK__DATA__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DCU_QCUMASK__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DCU_QCUMASK__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_DCU_QCUMASK__TYPE u_int32_t +#define MAC_DCU_QCUMASK__READ 0x000003ffU +#define MAC_DCU_QCUMASK__WRITE 0x000003ffU + +#endif /* __MAC_DCU_QCUMASK_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_QCUMASK */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_QCUMASK__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_SIFS */ +#ifndef __MAC_DCU_GBL_IFS_SIFS_MACRO__ +#define __MAC_DCU_GBL_IFS_SIFS_MACRO__ + +/* macros for field DURATION */ +#define MAC_DCU_GBL_IFS_SIFS__DURATION__SHIFT 0 +#define MAC_DCU_GBL_IFS_SIFS__DURATION__WIDTH 16 +#define MAC_DCU_GBL_IFS_SIFS__DURATION__MASK 0x0000ffffU +#define MAC_DCU_GBL_IFS_SIFS__DURATION__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DCU_GBL_IFS_SIFS__DURATION__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DCU_GBL_IFS_SIFS__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DCU_GBL_IFS_SIFS__DURATION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DCU_GBL_IFS_SIFS__TYPE u_int32_t +#define MAC_DCU_GBL_IFS_SIFS__READ 0x0000ffffU +#define MAC_DCU_GBL_IFS_SIFS__WRITE 0x0000ffffU + +#endif /* __MAC_DCU_GBL_IFS_SIFS_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_GBL_IFS_SIFS */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_GBL_IFS_SIFS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_DCU0_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU0_31_0__READ 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_31_0__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU0_31_0 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU0_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU8_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU8_31_0 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU8_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_LCL_IFS */ +#ifndef __MAC_DCU_LCL_IFS_MACRO__ +#define __MAC_DCU_LCL_IFS_MACRO__ + +/* macros for field CW_MIN */ +#define MAC_DCU_LCL_IFS__CW_MIN__SHIFT 0 +#define MAC_DCU_LCL_IFS__CW_MIN__WIDTH 10 +#define MAC_DCU_LCL_IFS__CW_MIN__MASK 0x000003ffU +#define MAC_DCU_LCL_IFS__CW_MIN__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DCU_LCL_IFS__CW_MIN__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DCU_LCL_IFS__CW_MIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DCU_LCL_IFS__CW_MIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field CW_MAX */ +#define MAC_DCU_LCL_IFS__CW_MAX__SHIFT 10 +#define MAC_DCU_LCL_IFS__CW_MAX__WIDTH 10 +#define MAC_DCU_LCL_IFS__CW_MAX__MASK 0x000ffc00U +#define MAC_DCU_LCL_IFS__CW_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define MAC_DCU_LCL_IFS__CW_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define MAC_DCU_LCL_IFS__CW_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define MAC_DCU_LCL_IFS__CW_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field AIFS */ +#define MAC_DCU_LCL_IFS__AIFS__SHIFT 20 +#define MAC_DCU_LCL_IFS__AIFS__WIDTH 8 +#define MAC_DCU_LCL_IFS__AIFS__MASK 0x0ff00000U +#define MAC_DCU_LCL_IFS__AIFS__READ(src) \ + (((u_int32_t)(src)\ + & 0x0ff00000U) >> 20) +#define MAC_DCU_LCL_IFS__AIFS__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x0ff00000U) +#define MAC_DCU_LCL_IFS__AIFS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x0ff00000U) +#define MAC_DCU_LCL_IFS__AIFS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x0ff00000U))) + +/* macros for field LONG_AIFS */ +#define MAC_DCU_LCL_IFS__LONG_AIFS__SHIFT 28 +#define MAC_DCU_LCL_IFS__LONG_AIFS__WIDTH 1 +#define MAC_DCU_LCL_IFS__LONG_AIFS__MASK 0x10000000U +#define MAC_DCU_LCL_IFS__LONG_AIFS__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_DCU_LCL_IFS__LONG_AIFS__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_DCU_LCL_IFS__LONG_AIFS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_DCU_LCL_IFS__LONG_AIFS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_DCU_LCL_IFS__LONG_AIFS__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_DCU_LCL_IFS__LONG_AIFS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) +#define MAC_DCU_LCL_IFS__TYPE u_int32_t +#define MAC_DCU_LCL_IFS__READ 0x1fffffffU +#define MAC_DCU_LCL_IFS__WRITE 0x1fffffffU + +#endif /* __MAC_DCU_LCL_IFS_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_LCL_IFS */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_LCL_IFS__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_SLOT */ +#ifndef __MAC_DCU_GBL_IFS_SLOT_MACRO__ +#define __MAC_DCU_GBL_IFS_SLOT_MACRO__ + +/* macros for field DURATION */ +#define MAC_DCU_GBL_IFS_SLOT__DURATION__SHIFT 0 +#define MAC_DCU_GBL_IFS_SLOT__DURATION__WIDTH 16 +#define MAC_DCU_GBL_IFS_SLOT__DURATION__MASK 0x0000ffffU +#define MAC_DCU_GBL_IFS_SLOT__DURATION__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DCU_GBL_IFS_SLOT__DURATION__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DCU_GBL_IFS_SLOT__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DCU_GBL_IFS_SLOT__DURATION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DCU_GBL_IFS_SLOT__TYPE u_int32_t +#define MAC_DCU_GBL_IFS_SLOT__READ 0x0000ffffU +#define MAC_DCU_GBL_IFS_SLOT__WRITE 0x0000ffffU + +#endif /* __MAC_DCU_GBL_IFS_SLOT_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_GBL_IFS_SLOT */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_GBL_IFS_SLOT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_DCU0_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU0_63_32__READ 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_63_32__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU0_63_32 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU0_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU8_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU8_63_32 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU8_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_RETRY_LIMIT */ +#ifndef __MAC_DCU_RETRY_LIMIT_MACRO__ +#define __MAC_DCU_RETRY_LIMIT_MACRO__ + +/* macros for field FRFL */ +#define MAC_DCU_RETRY_LIMIT__FRFL__SHIFT 0 +#define MAC_DCU_RETRY_LIMIT__FRFL__WIDTH 4 +#define MAC_DCU_RETRY_LIMIT__FRFL__MASK 0x0000000fU +#define MAC_DCU_RETRY_LIMIT__FRFL__READ(src) (u_int32_t)(src) & 0x0000000fU +#define MAC_DCU_RETRY_LIMIT__FRFL__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define MAC_DCU_RETRY_LIMIT__FRFL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_DCU_RETRY_LIMIT__FRFL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field SRFL */ +#define MAC_DCU_RETRY_LIMIT__SRFL__SHIFT 8 +#define MAC_DCU_RETRY_LIMIT__SRFL__WIDTH 6 +#define MAC_DCU_RETRY_LIMIT__SRFL__MASK 0x00003f00U +#define MAC_DCU_RETRY_LIMIT__SRFL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define MAC_DCU_RETRY_LIMIT__SRFL__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define MAC_DCU_RETRY_LIMIT__SRFL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define MAC_DCU_RETRY_LIMIT__SRFL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field SDFL */ +#define MAC_DCU_RETRY_LIMIT__SDFL__SHIFT 14 +#define MAC_DCU_RETRY_LIMIT__SDFL__WIDTH 6 +#define MAC_DCU_RETRY_LIMIT__SDFL__MASK 0x000fc000U +#define MAC_DCU_RETRY_LIMIT__SDFL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) +#define MAC_DCU_RETRY_LIMIT__SDFL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x000fc000U) +#define MAC_DCU_RETRY_LIMIT__SDFL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x000fc000U) +#define MAC_DCU_RETRY_LIMIT__SDFL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x000fc000U))) +#define MAC_DCU_RETRY_LIMIT__TYPE u_int32_t +#define MAC_DCU_RETRY_LIMIT__READ 0x000fff0fU +#define MAC_DCU_RETRY_LIMIT__WRITE 0x000fff0fU + +#endif /* __MAC_DCU_RETRY_LIMIT_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_RETRY_LIMIT */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_RETRY_LIMIT__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_EIFS */ +#ifndef __MAC_DCU_GBL_IFS_EIFS_MACRO__ +#define __MAC_DCU_GBL_IFS_EIFS_MACRO__ + +/* macros for field DURATION */ +#define MAC_DCU_GBL_IFS_EIFS__DURATION__SHIFT 0 +#define MAC_DCU_GBL_IFS_EIFS__DURATION__WIDTH 16 +#define MAC_DCU_GBL_IFS_EIFS__DURATION__MASK 0x0000ffffU +#define MAC_DCU_GBL_IFS_EIFS__DURATION__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DCU_GBL_IFS_EIFS__DURATION__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DCU_GBL_IFS_EIFS__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DCU_GBL_IFS_EIFS__DURATION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DCU_GBL_IFS_EIFS__TYPE u_int32_t +#define MAC_DCU_GBL_IFS_EIFS__READ 0x0000ffffU +#define MAC_DCU_GBL_IFS_EIFS__WRITE 0x0000ffffU + +#endif /* __MAC_DCU_GBL_IFS_EIFS_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_GBL_IFS_EIFS */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_GBL_IFS_EIFS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_DCU0_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU0_95_64__READ 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_95_64__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU0_95_64 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU0_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU8_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU8_95_64 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU8_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_CHANNEL_TIME */ +#ifndef __MAC_DCU_CHANNEL_TIME_MACRO__ +#define __MAC_DCU_CHANNEL_TIME_MACRO__ + +/* macros for field DURATION */ +#define MAC_DCU_CHANNEL_TIME__DURATION__SHIFT 0 +#define MAC_DCU_CHANNEL_TIME__DURATION__WIDTH 20 +#define MAC_DCU_CHANNEL_TIME__DURATION__MASK 0x000fffffU +#define MAC_DCU_CHANNEL_TIME__DURATION__READ(src) \ + (u_int32_t)(src)\ + & 0x000fffffU +#define MAC_DCU_CHANNEL_TIME__DURATION__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000fffffU) +#define MAC_DCU_CHANNEL_TIME__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffffU) | ((u_int32_t)(src) &\ + 0x000fffffU) +#define MAC_DCU_CHANNEL_TIME__DURATION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000fffffU))) + +/* macros for field ENABLE */ +#define MAC_DCU_CHANNEL_TIME__ENABLE__SHIFT 20 +#define MAC_DCU_CHANNEL_TIME__ENABLE__WIDTH 1 +#define MAC_DCU_CHANNEL_TIME__ENABLE__MASK 0x00100000U +#define MAC_DCU_CHANNEL_TIME__ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_DCU_CHANNEL_TIME__ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_DCU_CHANNEL_TIME__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_DCU_CHANNEL_TIME__ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_DCU_CHANNEL_TIME__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_DCU_CHANNEL_TIME__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) +#define MAC_DCU_CHANNEL_TIME__TYPE u_int32_t +#define MAC_DCU_CHANNEL_TIME__READ 0x001fffffU +#define MAC_DCU_CHANNEL_TIME__WRITE 0x001fffffU + +#endif /* __MAC_DCU_CHANNEL_TIME_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_CHANNEL_TIME */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_CHANNEL_TIME__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_MISC */ +#ifndef __MAC_DCU_GBL_IFS_MISC_MACRO__ +#define __MAC_DCU_GBL_IFS_MISC_MACRO__ + +/* macros for field LFSR_SLICE_SEL */ +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__SHIFT 0 +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WIDTH 3 +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MASK 0x00000007U +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field TURBO_MODE */ +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__SHIFT 3 +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MASK 0x00000008U +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field SIFS_DUR_USEC */ +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__SHIFT 4 +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WIDTH 6 +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MASK 0x000003f0U +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field ARB_DLY */ +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__SHIFT 20 +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WIDTH 2 +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MASK 0x00300000U +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00300000U) >> 20) +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00300000U) +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((u_int32_t)(src) <<\ + 20) & 0x00300000U) +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00300000U))) + +/* macros for field SIFS_RST_UNCOND */ +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__SHIFT 22 +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MASK 0x00400000U +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field AIFS_RST_UNCOND */ +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__SHIFT 23 +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MASK 0x00800000U +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field LFSR_SLICE_RANDOM_DIS */ +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__SHIFT 24 +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MASK 0x01000000U +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field CHAN_SLOT_WIN_DUR */ +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__SHIFT 25 +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WIDTH 2 +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MASK 0x06000000U +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field CHAN_SLOT_ALWAYS */ +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__SHIFT 27 +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MASK 0x08000000U +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field IGNORE_BACKOFF */ +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__SHIFT 28 +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MASK 0x10000000U +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) +#define MAC_DCU_GBL_IFS_MISC__TYPE u_int32_t +#define MAC_DCU_GBL_IFS_MISC__READ 0x1ff003ffU +#define MAC_DCU_GBL_IFS_MISC__WRITE 0x1ff003ffU + +#endif /* __MAC_DCU_GBL_IFS_MISC_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_GBL_IFS_MISC */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_GBL_IFS_MISC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_DCU0_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU0_127_96__READ 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_127_96__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU0_127_96 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU0_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU8_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU8_127_96 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU8_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_MISC */ +#ifndef __MAC_DCU_MISC_MACRO__ +#define __MAC_DCU_MISC_MACRO__ + +/* macros for field BKOFF_THRESH */ +#define MAC_DCU_MISC__BKOFF_THRESH__SHIFT 0 +#define MAC_DCU_MISC__BKOFF_THRESH__WIDTH 6 +#define MAC_DCU_MISC__BKOFF_THRESH__MASK 0x0000003fU +#define MAC_DCU_MISC__BKOFF_THRESH__READ(src) (u_int32_t)(src) & 0x0000003fU +#define MAC_DCU_MISC__BKOFF_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define MAC_DCU_MISC__BKOFF_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define MAC_DCU_MISC__BKOFF_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field SFC_RST_AT_TS_END_EN */ +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__SHIFT 6 +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WIDTH 1 +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MASK 0x00000040U +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field CW_RST_AT_TS_END_DIS */ +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__SHIFT 7 +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WIDTH 1 +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MASK 0x00000080U +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field FRAG_BURST_WAIT_QCU_EN */ +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__SHIFT 8 +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WIDTH 1 +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MASK 0x00000100U +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field FRAG_BURST_BKOFF_EN */ +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__SHIFT 9 +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WIDTH 1 +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MASK 0x00000200U +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field HCF_POLL_EN */ +#define MAC_DCU_MISC__HCF_POLL_EN__SHIFT 11 +#define MAC_DCU_MISC__HCF_POLL_EN__WIDTH 1 +#define MAC_DCU_MISC__HCF_POLL_EN__MASK 0x00000800U +#define MAC_DCU_MISC__HCF_POLL_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_DCU_MISC__HCF_POLL_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_DCU_MISC__HCF_POLL_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_DCU_MISC__HCF_POLL_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_DCU_MISC__HCF_POLL_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_DCU_MISC__HCF_POLL_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field BKOFF_PF */ +#define MAC_DCU_MISC__BKOFF_PF__SHIFT 12 +#define MAC_DCU_MISC__BKOFF_PF__WIDTH 1 +#define MAC_DCU_MISC__BKOFF_PF__MASK 0x00001000U +#define MAC_DCU_MISC__BKOFF_PF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_DCU_MISC__BKOFF_PF__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_DCU_MISC__BKOFF_PF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_DCU_MISC__BKOFF_PF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_DCU_MISC__BKOFF_PF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_DCU_MISC__BKOFF_PF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field VIRT_COLL_POLICY */ +#define MAC_DCU_MISC__VIRT_COLL_POLICY__SHIFT 14 +#define MAC_DCU_MISC__VIRT_COLL_POLICY__WIDTH 2 +#define MAC_DCU_MISC__VIRT_COLL_POLICY__MASK 0x0000c000U +#define MAC_DCU_MISC__VIRT_COLL_POLICY__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define MAC_DCU_MISC__VIRT_COLL_POLICY__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define MAC_DCU_MISC__VIRT_COLL_POLICY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define MAC_DCU_MISC__VIRT_COLL_POLICY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field IS_BCN */ +#define MAC_DCU_MISC__IS_BCN__SHIFT 16 +#define MAC_DCU_MISC__IS_BCN__WIDTH 1 +#define MAC_DCU_MISC__IS_BCN__MASK 0x00010000U +#define MAC_DCU_MISC__IS_BCN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_DCU_MISC__IS_BCN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_DCU_MISC__IS_BCN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_DCU_MISC__IS_BCN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_DCU_MISC__IS_BCN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_DCU_MISC__IS_BCN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field ARB_LOCKOUT_IF_EN */ +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__SHIFT 17 +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WIDTH 1 +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MASK 0x00020000U +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field LOCKOUT_GBL_EN */ +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__SHIFT 18 +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__WIDTH 1 +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__MASK 0x00040000U +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field LOCKOUT_IGNORE */ +#define MAC_DCU_MISC__LOCKOUT_IGNORE__SHIFT 19 +#define MAC_DCU_MISC__LOCKOUT_IGNORE__WIDTH 1 +#define MAC_DCU_MISC__LOCKOUT_IGNORE__MASK 0x00080000U +#define MAC_DCU_MISC__LOCKOUT_IGNORE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_DCU_MISC__LOCKOUT_IGNORE__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_DCU_MISC__LOCKOUT_IGNORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_DCU_MISC__LOCKOUT_IGNORE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_DCU_MISC__LOCKOUT_IGNORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_DCU_MISC__LOCKOUT_IGNORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field SEQNUM_FREEZE */ +#define MAC_DCU_MISC__SEQNUM_FREEZE__SHIFT 20 +#define MAC_DCU_MISC__SEQNUM_FREEZE__WIDTH 1 +#define MAC_DCU_MISC__SEQNUM_FREEZE__MASK 0x00100000U +#define MAC_DCU_MISC__SEQNUM_FREEZE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_DCU_MISC__SEQNUM_FREEZE__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_DCU_MISC__SEQNUM_FREEZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_DCU_MISC__SEQNUM_FREEZE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_DCU_MISC__SEQNUM_FREEZE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_DCU_MISC__SEQNUM_FREEZE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field POST_BKOFF_SKIP */ +#define MAC_DCU_MISC__POST_BKOFF_SKIP__SHIFT 21 +#define MAC_DCU_MISC__POST_BKOFF_SKIP__WIDTH 1 +#define MAC_DCU_MISC__POST_BKOFF_SKIP__MASK 0x00200000U +#define MAC_DCU_MISC__POST_BKOFF_SKIP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_DCU_MISC__POST_BKOFF_SKIP__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_DCU_MISC__POST_BKOFF_SKIP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_DCU_MISC__POST_BKOFF_SKIP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_DCU_MISC__POST_BKOFF_SKIP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_DCU_MISC__POST_BKOFF_SKIP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field VIRT_COLL_CW_INC_EN */ +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__SHIFT 22 +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WIDTH 1 +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MASK 0x00400000U +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field RETRY_ON_BLOWN_IFS_EN */ +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__SHIFT 23 +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WIDTH 1 +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MASK 0x00800000U +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field SIFS_BURST_CHAN_BUSY_IGNORE */ +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__SHIFT 24 +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WIDTH 1 +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MASK 0x01000000U +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define MAC_DCU_MISC__TYPE u_int32_t +#define MAC_DCU_MISC__READ 0x01ffdbffU +#define MAC_DCU_MISC__WRITE 0x01ffdbffU + +#endif /* __MAC_DCU_MISC_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_MISC */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_MISC__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU1_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU1_31_0 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU1_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU9_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU9_31_0 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU9_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_SEQ */ +#ifndef __MAC_DCU_SEQ_MACRO__ +#define __MAC_DCU_SEQ_MACRO__ + +/* macros for field NUM */ +#define MAC_DCU_SEQ__NUM__SHIFT 0 +#define MAC_DCU_SEQ__NUM__WIDTH 32 +#define MAC_DCU_SEQ__NUM__MASK 0xffffffffU +#define MAC_DCU_SEQ__NUM__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DCU_SEQ__NUM__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DCU_SEQ__NUM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_SEQ__NUM__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define MAC_DCU_SEQ__TYPE u_int32_t +#define MAC_DCU_SEQ__READ 0xffffffffU +#define MAC_DCU_SEQ__WRITE 0xffffffffU + +#endif /* __MAC_DCU_SEQ_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_SEQ */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_SEQ__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU1_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU1_63_32 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU1_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU9_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU9_63_32 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU9_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU1_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU1_95_64 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU1_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU9_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU9_95_64 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU9_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU1_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU1_127_96 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU1_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU9_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU9_127_96 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU9_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU2_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU2_31_0 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU2_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_PAUSE */ +#ifndef __MAC_DCU_PAUSE_MACRO__ +#define __MAC_DCU_PAUSE_MACRO__ + +/* macros for field REQUEST */ +#define MAC_DCU_PAUSE__REQUEST__SHIFT 0 +#define MAC_DCU_PAUSE__REQUEST__WIDTH 10 +#define MAC_DCU_PAUSE__REQUEST__MASK 0x000003ffU +#define MAC_DCU_PAUSE__REQUEST__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DCU_PAUSE__REQUEST__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DCU_PAUSE__REQUEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DCU_PAUSE__REQUEST__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field STATUS */ +#define MAC_DCU_PAUSE__STATUS__SHIFT 16 +#define MAC_DCU_PAUSE__STATUS__WIDTH 1 +#define MAC_DCU_PAUSE__STATUS__MASK 0x00010000U +#define MAC_DCU_PAUSE__STATUS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_DCU_PAUSE__STATUS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_DCU_PAUSE__STATUS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) +#define MAC_DCU_PAUSE__TYPE u_int32_t +#define MAC_DCU_PAUSE__READ 0x000103ffU +#define MAC_DCU_PAUSE__WRITE 0x000103ffU + +#endif /* __MAC_DCU_PAUSE_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_PAUSE */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_PAUSE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU2_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU2_63_32 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU2_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_WOW_KACFG */ +#ifndef __MAC_DCU_WOW_KACFG_MACRO__ +#define __MAC_DCU_WOW_KACFG_MACRO__ + +/* macros for field TX_EN */ +#define MAC_DCU_WOW_KACFG__TX_EN__SHIFT 0 +#define MAC_DCU_WOW_KACFG__TX_EN__WIDTH 1 +#define MAC_DCU_WOW_KACFG__TX_EN__MASK 0x00000001U +#define MAC_DCU_WOW_KACFG__TX_EN__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_DCU_WOW_KACFG__TX_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_DCU_WOW_KACFG__TX_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_DCU_WOW_KACFG__TX_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_DCU_WOW_KACFG__TX_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DCU_WOW_KACFG__TX_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field TIM_EN */ +#define MAC_DCU_WOW_KACFG__TIM_EN__SHIFT 1 +#define MAC_DCU_WOW_KACFG__TIM_EN__WIDTH 1 +#define MAC_DCU_WOW_KACFG__TIM_EN__MASK 0x00000002U +#define MAC_DCU_WOW_KACFG__TIM_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_DCU_WOW_KACFG__TIM_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_DCU_WOW_KACFG__TIM_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_DCU_WOW_KACFG__TIM_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_DCU_WOW_KACFG__TIM_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_DCU_WOW_KACFG__TIM_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field BCN_CNT */ +#define MAC_DCU_WOW_KACFG__BCN_CNT__SHIFT 4 +#define MAC_DCU_WOW_KACFG__BCN_CNT__WIDTH 8 +#define MAC_DCU_WOW_KACFG__BCN_CNT__MASK 0x00000ff0U +#define MAC_DCU_WOW_KACFG__BCN_CNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000ff0U) >> 4) +#define MAC_DCU_WOW_KACFG__BCN_CNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000ff0U) +#define MAC_DCU_WOW_KACFG__BCN_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000ff0U) | (((u_int32_t)(src) <<\ + 4) & 0x00000ff0U) +#define MAC_DCU_WOW_KACFG__BCN_CNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000ff0U))) + +/* macros for field RX_TIMEOUT_CNT */ +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__SHIFT 12 +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WIDTH 12 +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MASK 0x00fff000U +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fff000U) >> 12) +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00fff000U) +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fff000U) | (((u_int32_t)(src) <<\ + 12) & 0x00fff000U) +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00fff000U))) +#define MAC_DCU_WOW_KACFG__TYPE u_int32_t +#define MAC_DCU_WOW_KACFG__READ 0x00fffff3U +#define MAC_DCU_WOW_KACFG__WRITE 0x00fffff3U + +#endif /* __MAC_DCU_WOW_KACFG_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_WOW_KACFG */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_WOW_KACFG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU2_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU2_95_64 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU2_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXSLOT */ +#ifndef __MAC_DCU_TXSLOT_MACRO__ +#define __MAC_DCU_TXSLOT_MACRO__ + +/* macros for field MASK */ +#define MAC_DCU_TXSLOT__MASK__SHIFT 0 +#define MAC_DCU_TXSLOT__MASK__WIDTH 16 +#define MAC_DCU_TXSLOT__MASK__MASK 0x0000ffffU +#define MAC_DCU_TXSLOT__MASK__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_DCU_TXSLOT__MASK__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_DCU_TXSLOT__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DCU_TXSLOT__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DCU_TXSLOT__TYPE u_int32_t +#define MAC_DCU_TXSLOT__READ 0x0000ffffU +#define MAC_DCU_TXSLOT__WRITE 0x0000ffffU + +#endif /* __MAC_DCU_TXSLOT_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXSLOT */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXSLOT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU2_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU2_127_96 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU2_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU3_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU3_31_0 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU3_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU3_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU3_63_32 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU3_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU3_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU3_95_64 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU3_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU3_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU3_127_96 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU3_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU4_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU4_31_0 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU4_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_CLEAR */ +#ifndef __MAC_DCU_TXFILTER_CLEAR_MACRO__ +#define __MAC_DCU_TXFILTER_CLEAR_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_CLEAR__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_CLEAR__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_CLEAR__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_CLEAR__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DCU_TXFILTER_CLEAR__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DCU_TXFILTER_CLEAR__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_CLEAR__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_CLEAR__TYPE u_int32_t +#define MAC_DCU_TXFILTER_CLEAR__READ 0xffffffffU +#define MAC_DCU_TXFILTER_CLEAR__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_CLEAR_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_CLEAR */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_CLEAR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU4_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU4_63_32 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU4_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_SET */ +#ifndef __MAC_DCU_TXFILTER_SET_MACRO__ +#define __MAC_DCU_TXFILTER_SET_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_SET__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_SET__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_SET__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_SET__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DCU_TXFILTER_SET__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DCU_TXFILTER_SET__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_SET__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_SET__TYPE u_int32_t +#define MAC_DCU_TXFILTER_SET__READ 0xffffffffU +#define MAC_DCU_TXFILTER_SET__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_SET_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_SET */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_SET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU4_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU4_95_64 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU4_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU4_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU4_127_96 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU4_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU5_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU5_31_0 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU5_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU5_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU5_63_32 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU5_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU5_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU5_95_64 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU5_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU5_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU5_127_96 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU5_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU6_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU6_31_0 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU6_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU6_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU6_63_32 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU6_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU6_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU6_95_64 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU6_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU6_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU6_127_96 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU6_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU7_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU7_31_0 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU7_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU7_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU7_63_32 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU7_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU7_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU7_95_64 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU7_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU7_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_block.MAC_DCU_TXFILTER_DCU7_127_96 */ +#define INST_MAC_DCU_REG_BLOCK__MAC_DCU_TXFILTER_DCU7_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_RESET_CONTROL */ +#ifndef __HOST_INTF_RESET_CONTROL_MACRO__ +#define __HOST_INTF_RESET_CONTROL_MACRO__ + +/* macros for field AHB_RESET */ +#define HOST_INTF_RESET_CONTROL__AHB_RESET__SHIFT 0 +#define HOST_INTF_RESET_CONTROL__AHB_RESET__WIDTH 1 +#define HOST_INTF_RESET_CONTROL__AHB_RESET__MASK 0x00000001U +#define HOST_INTF_RESET_CONTROL__AHB_RESET__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define HOST_INTF_RESET_CONTROL__AHB_RESET__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define HOST_INTF_RESET_CONTROL__AHB_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define HOST_INTF_RESET_CONTROL__AHB_RESET__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define HOST_INTF_RESET_CONTROL__AHB_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_RESET_CONTROL__AHB_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field APB_RESET */ +#define HOST_INTF_RESET_CONTROL__APB_RESET__SHIFT 1 +#define HOST_INTF_RESET_CONTROL__APB_RESET__WIDTH 1 +#define HOST_INTF_RESET_CONTROL__APB_RESET__MASK 0x00000002U +#define HOST_INTF_RESET_CONTROL__APB_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define HOST_INTF_RESET_CONTROL__APB_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define HOST_INTF_RESET_CONTROL__APB_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define HOST_INTF_RESET_CONTROL__APB_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define HOST_INTF_RESET_CONTROL__APB_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define HOST_INTF_RESET_CONTROL__APB_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field LOCAL_RESET */ +#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__SHIFT 8 +#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__WIDTH 1 +#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__MASK 0x00000100U +#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) +#define HOST_INTF_RESET_CONTROL__TYPE u_int32_t +#define HOST_INTF_RESET_CONTROL__READ 0x00000103U +#define HOST_INTF_RESET_CONTROL__WRITE 0x00000103U + +#endif /* __HOST_INTF_RESET_CONTROL_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_RESET_CONTROL */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_RESET_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_WORK_AROUND */ +#ifndef __HOST_INTF_WORK_AROUND_MACRO__ +#define __HOST_INTF_WORK_AROUND_MACRO__ + +/* macros for field TS1_WA_EN */ +#define HOST_INTF_WORK_AROUND__TS1_WA_EN__SHIFT 0 +#define HOST_INTF_WORK_AROUND__TS1_WA_EN__WIDTH 1 +#define HOST_INTF_WORK_AROUND__TS1_WA_EN__MASK 0x00000001U +#define HOST_INTF_WORK_AROUND__TS1_WA_EN__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define HOST_INTF_WORK_AROUND__TS1_WA_EN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define HOST_INTF_WORK_AROUND__TS1_WA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define HOST_INTF_WORK_AROUND__TS1_WA_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define HOST_INTF_WORK_AROUND__TS1_WA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_WORK_AROUND__TS1_WA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field TS2_WA_EN */ +#define HOST_INTF_WORK_AROUND__TS2_WA_EN__SHIFT 1 +#define HOST_INTF_WORK_AROUND__TS2_WA_EN__WIDTH 1 +#define HOST_INTF_WORK_AROUND__TS2_WA_EN__MASK 0x00000002U +#define HOST_INTF_WORK_AROUND__TS2_WA_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define HOST_INTF_WORK_AROUND__TS2_WA_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define HOST_INTF_WORK_AROUND__TS2_WA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define HOST_INTF_WORK_AROUND__TS2_WA_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define HOST_INTF_WORK_AROUND__TS2_WA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define HOST_INTF_WORK_AROUND__TS2_WA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field RESET_SERDES_WA_EN */ +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__SHIFT 2 +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__WIDTH 1 +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__MASK 0x00000004U +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field GDATA_WA_EN */ +#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__SHIFT 3 +#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__WIDTH 1 +#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__MASK 0x00000008U +#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field NO_NAK_WA_EN */ +#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__SHIFT 4 +#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__WIDTH 1 +#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__MASK 0x00000010U +#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field FORCE_L1L0_DMA */ +#define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__SHIFT 9 +#define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__WIDTH 1 +#define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__MASK 0x00000200U +#define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field PCIE_COLD_RESET_OVRRD */ +#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__SHIFT 13 +#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__WIDTH 1 +#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__MASK 0x00002000U +#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field D3_TO_L1_DISABLE */ +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__SHIFT 14 +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__WIDTH 1 +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__MASK 0x00004000U +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field PCIERST_PORRST_SHORT */ +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__SHIFT 15 +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__WIDTH 1 +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__MASK 0x00008000U +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field D3_TO_L1_DISABLE_REAL */ +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__SHIFT 16 +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__WIDTH 1 +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__MASK 0x00010000U +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field ASPM_TIMER_BASED_L1_DISABLE */ +#define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__SHIFT 17 +#define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__WIDTH 1 +#define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__MASK 0x00020000U +#define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field PCIERST_PORRST_SW_CNTL */ +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__SHIFT 18 +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__WIDTH 1 +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__MASK 0x00040000U +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field PCIERST_PORRST_SHIFT */ +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__SHIFT 20 +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__WIDTH 1 +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__MASK 0x00100000U +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field PCIERST_PORRST_PHY */ +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__SHIFT 21 +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__WIDTH 1 +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__MASK 0x00200000U +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field PCIE_NFTS_CNTL_EN */ +#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__SHIFT 23 +#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__WIDTH 1 +#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__MASK 0x00800000U +#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field RESET_SERDES_WA_TIMEOUT */ +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__SHIFT 24 +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__WIDTH 8 +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__MASK 0xff000000U +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define HOST_INTF_WORK_AROUND__TYPE u_int32_t +#define HOST_INTF_WORK_AROUND__READ 0xffb7e21fU +#define HOST_INTF_WORK_AROUND__WRITE 0xffb7e21fU + +#endif /* __HOST_INTF_WORK_AROUND_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_WORK_AROUND */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_WORK_AROUND__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_PM_STATE */ +#ifndef __HOST_INTF_PM_STATE_MACRO__ +#define __HOST_INTF_PM_STATE_MACRO__ + +/* macros for field PCIE_PM_XTLH_BLOCK_TLP */ +#define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__SHIFT 0 +#define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__WIDTH 1 +#define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__MASK 0x00000001U +#define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PCIE_PM_CURNT_STATE */ +#define HOST_INTF_PM_STATE__PCIE_PM_CURNT_STATE__SHIFT 1 +#define HOST_INTF_PM_STATE__PCIE_PM_CURNT_STATE__WIDTH 3 +#define HOST_INTF_PM_STATE__PCIE_PM_CURNT_STATE__MASK 0x0000000eU +#define HOST_INTF_PM_STATE__PCIE_PM_CURNT_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) + +/* macros for field PCIE_PM_DSTATE */ +#define HOST_INTF_PM_STATE__PCIE_PM_DSTATE__SHIFT 4 +#define HOST_INTF_PM_STATE__PCIE_PM_DSTATE__WIDTH 3 +#define HOST_INTF_PM_STATE__PCIE_PM_DSTATE__MASK 0x00000070U +#define HOST_INTF_PM_STATE__PCIE_PM_DSTATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000070U) >> 4) + +/* macros for field PCIE_PM_PME_EN */ +#define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__SHIFT 7 +#define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__WIDTH 1 +#define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__MASK 0x00000080U +#define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field PCIE_PM_STATUS */ +#define HOST_INTF_PM_STATE__PCIE_PM_STATUS__SHIFT 8 +#define HOST_INTF_PM_STATE__PCIE_PM_STATUS__WIDTH 1 +#define HOST_INTF_PM_STATE__PCIE_PM_STATUS__MASK 0x00000100U +#define HOST_INTF_PM_STATE__PCIE_PM_STATUS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define HOST_INTF_PM_STATE__PCIE_PM_STATUS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define HOST_INTF_PM_STATE__PCIE_PM_STATUS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field PCIE_AUX_PM_EN */ +#define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__SHIFT 9 +#define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__WIDTH 1 +#define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__MASK 0x00000200U +#define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field PCIE_XMLH_LTSSM_STATE */ +#define HOST_INTF_PM_STATE__PCIE_XMLH_LTSSM_STATE__SHIFT 10 +#define HOST_INTF_PM_STATE__PCIE_XMLH_LTSSM_STATE__WIDTH 5 +#define HOST_INTF_PM_STATE__PCIE_XMLH_LTSSM_STATE__MASK 0x00007c00U +#define HOST_INTF_PM_STATE__PCIE_XMLH_LTSSM_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) + +/* macros for field CLKMISC_MULTI_PIPE_MODE_MAC */ +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__SHIFT 19 +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__WIDTH 1 +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__MASK 0x00080000U +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field CLKMISC_MULTI_PIPE_MODE_PHY */ +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__SHIFT 20 +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__WIDTH 1 +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__MASK 0x00100000U +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field CLKMISC_MULTI_PCIE_PHY_TEST */ +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__SHIFT 21 +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__WIDTH 1 +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__MASK 0x00200000U +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) +#define HOST_INTF_PM_STATE__TYPE u_int32_t +#define HOST_INTF_PM_STATE__READ 0x00387fffU + +#endif /* __HOST_INTF_PM_STATE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_PM_STATE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_PM_STATE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_CXPL_DEBUG_INFOL */ +#ifndef __HOST_INTF_CXPL_DEBUG_INFOL_MACRO__ +#define __HOST_INTF_CXPL_DEBUG_INFOL_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_CXPL_DEBUG_INFOL__DATA__SHIFT 0 +#define HOST_INTF_CXPL_DEBUG_INFOL__DATA__WIDTH 32 +#define HOST_INTF_CXPL_DEBUG_INFOL__DATA__MASK 0xffffffffU +#define HOST_INTF_CXPL_DEBUG_INFOL__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define HOST_INTF_CXPL_DEBUG_INFOL__TYPE u_int32_t +#define HOST_INTF_CXPL_DEBUG_INFOL__READ 0xffffffffU + +#endif /* __HOST_INTF_CXPL_DEBUG_INFOL_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_CXPL_DEBUG_INFOL */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_CXPL_DEBUG_INFOL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_CXPL_DEBUG_INFOH */ +#ifndef __HOST_INTF_CXPL_DEBUG_INFOH_MACRO__ +#define __HOST_INTF_CXPL_DEBUG_INFOH_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_CXPL_DEBUG_INFOH__DATA__SHIFT 0 +#define HOST_INTF_CXPL_DEBUG_INFOH__DATA__WIDTH 32 +#define HOST_INTF_CXPL_DEBUG_INFOH__DATA__MASK 0xffffffffU +#define HOST_INTF_CXPL_DEBUG_INFOH__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define HOST_INTF_CXPL_DEBUG_INFOH__TYPE u_int32_t +#define HOST_INTF_CXPL_DEBUG_INFOH__READ 0xffffffffU + +#endif /* __HOST_INTF_CXPL_DEBUG_INFOH_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_CXPL_DEBUG_INFOH */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_CXPL_DEBUG_INFOH__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_PM_CTRL */ +#ifndef __HOST_INTF_PM_CTRL_MACRO__ +#define __HOST_INTF_PM_CTRL_MACRO__ + +/* macros for field PCIE_PM_OVERRIDE */ +#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__SHIFT 0 +#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__WIDTH 1 +#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__MASK 0x00000001U +#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PCIE_PM_DELAY */ +#define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__SHIFT 2 +#define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__WIDTH 16 +#define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__MASK 0x0003fffcU +#define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fffcU) >> 2) +#define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0003fffcU) +#define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0003fffcU) +#define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0003fffcU))) + +/* macros for field PCIE_PM_DISABLE */ +#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__SHIFT 18 +#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__WIDTH 1 +#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__MASK 0x00040000U +#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field PCIE_ENTER_L1_EN */ +#define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__SHIFT 19 +#define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__WIDTH 1 +#define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__MASK 0x00080000U +#define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field PCIE_PME_DISABLE_CLK */ +#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__SHIFT 20 +#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__WIDTH 1 +#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__MASK 0x00100000U +#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field HOST_MAC_WOW_CLEAR */ +#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__SHIFT 21 +#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__WIDTH 1 +#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__MASK 0x00200000U +#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field HOST_PME_ENABLE */ +#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__SHIFT 22 +#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__WIDTH 1 +#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__MASK 0x00400000U +#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field PME_POWER_STATE_MASK */ +#define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__SHIFT 24 +#define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__WIDTH 4 +#define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__MASK 0x0f000000U +#define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) + +/* macros for field SYS_AUX_PWR_DET */ +#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__SHIFT 28 +#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__WIDTH 1 +#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__MASK 0x10000000U +#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PCIE_PWDBIAS_OVRD */ +#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__SHIFT 29 +#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__WIDTH 1 +#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__MASK 0x20000000U +#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PCIE_CLKREQ_OVRD */ +#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__SHIFT 30 +#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__WIDTH 1 +#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__MASK 0x40000000U +#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define HOST_INTF_PM_CTRL__TYPE u_int32_t +#define HOST_INTF_PM_CTRL__READ 0x7f7ffffdU +#define HOST_INTF_PM_CTRL__WRITE 0x7f7ffffdU + +#endif /* __HOST_INTF_PM_CTRL_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_PM_CTRL */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_PM_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_TIMEOUT */ +#ifndef __HOST_INTF_TIMEOUT_MACRO__ +#define __HOST_INTF_TIMEOUT_MACRO__ + +/* macros for field APB_TIMEOUT_VAL */ +#define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__SHIFT 0 +#define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__WIDTH 16 +#define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__MASK 0x0000ffffU +#define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field AXI_TIMEOUT_VAL */ +#define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__SHIFT 16 +#define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__WIDTH 16 +#define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__MASK 0xffff0000U +#define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define HOST_INTF_TIMEOUT__TYPE u_int32_t +#define HOST_INTF_TIMEOUT__READ 0xffffffffU +#define HOST_INTF_TIMEOUT__WRITE 0xffffffffU + +#endif /* __HOST_INTF_TIMEOUT_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_TIMEOUT */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_TIMEOUT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_EEPROM_CTRL */ +#ifndef __HOST_INTF_EEPROM_CTRL_MACRO__ +#define __HOST_INTF_EEPROM_CTRL_MACRO__ + +/* macros for field FAST_FLASH_MODE */ +#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__SHIFT 0 +#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__WIDTH 1 +#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__MASK 0x00000001U +#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field FORCE_RESET */ +#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__SHIFT 1 +#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__WIDTH 1 +#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__MASK 0x00000002U +#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field CLKDIV_RST_VAL */ +#define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__SHIFT 2 +#define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__WIDTH 6 +#define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__MASK 0x000000fcU +#define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000fcU) >> 2) +#define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x000000fcU) +#define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000fcU) | (((u_int32_t)(src) <<\ + 2) & 0x000000fcU) +#define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x000000fcU))) + +/* macros for field NOT_PRESENT */ +#define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__SHIFT 8 +#define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__WIDTH 1 +#define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__MASK 0x00000100U +#define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field IS_CORRUPT */ +#define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__SHIFT 9 +#define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__WIDTH 1 +#define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__MASK 0x00000200U +#define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field PROTECT */ +#define HOST_INTF_EEPROM_CTRL__PROTECT__SHIFT 10 +#define HOST_INTF_EEPROM_CTRL__PROTECT__WIDTH 16 +#define HOST_INTF_EEPROM_CTRL__PROTECT__MASK 0x03fffc00U +#define HOST_INTF_EEPROM_CTRL__PROTECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x03fffc00U) >> 10) +#define HOST_INTF_EEPROM_CTRL__TYPE u_int32_t +#define HOST_INTF_EEPROM_CTRL__READ 0x03ffffffU +#define HOST_INTF_EEPROM_CTRL__WRITE 0x03ffffffU + +#endif /* __HOST_INTF_EEPROM_CTRL_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_EEPROM_CTRL */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_EEPROM_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_SREV */ +#ifndef __HOST_INTF_SREV_MACRO__ +#define __HOST_INTF_SREV_MACRO__ + +/* macros for field MAC_ID */ +#define HOST_INTF_SREV__MAC_ID__SHIFT 0 +#define HOST_INTF_SREV__MAC_ID__WIDTH 32 +#define HOST_INTF_SREV__MAC_ID__MASK 0xffffffffU +#define HOST_INTF_SREV__MAC_ID__READ(src) (u_int32_t)(src) & 0xffffffffU +#define HOST_INTF_SREV__TYPE u_int32_t +#define HOST_INTF_SREV__READ 0xffffffffU + +#endif /* __HOST_INTF_SREV_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_SREV */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_SREV__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_SYNC_CAUSE */ +#ifndef __HOST_INTF_INTR_SYNC_CAUSE_MACRO__ +#define __HOST_INTF_INTR_SYNC_CAUSE_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_SYNC_CAUSE__DATA__SHIFT 0 +#define HOST_INTF_INTR_SYNC_CAUSE__DATA__WIDTH 32 +#define HOST_INTF_INTR_SYNC_CAUSE__DATA__MASK 0xffffffffU +#define HOST_INTF_INTR_SYNC_CAUSE__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define HOST_INTF_INTR_SYNC_CAUSE__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define HOST_INTF_INTR_SYNC_CAUSE__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define HOST_INTF_INTR_SYNC_CAUSE__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define HOST_INTF_INTR_SYNC_CAUSE__TYPE u_int32_t +#define HOST_INTF_INTR_SYNC_CAUSE__READ 0xffffffffU +#define HOST_INTF_INTR_SYNC_CAUSE__WRITE 0xffffffffU + +#endif /* __HOST_INTF_INTR_SYNC_CAUSE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_SYNC_CAUSE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_SYNC_CAUSE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_SYNC_ENABLE */ +#ifndef __HOST_INTF_INTR_SYNC_ENABLE_MACRO__ +#define __HOST_INTF_INTR_SYNC_ENABLE_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_SYNC_ENABLE__DATA__SHIFT 0 +#define HOST_INTF_INTR_SYNC_ENABLE__DATA__WIDTH 32 +#define HOST_INTF_INTR_SYNC_ENABLE__DATA__MASK 0xffffffffU +#define HOST_INTF_INTR_SYNC_ENABLE__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define HOST_INTF_INTR_SYNC_ENABLE__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define HOST_INTF_INTR_SYNC_ENABLE__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define HOST_INTF_INTR_SYNC_ENABLE__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define HOST_INTF_INTR_SYNC_ENABLE__TYPE u_int32_t +#define HOST_INTF_INTR_SYNC_ENABLE__READ 0xffffffffU +#define HOST_INTF_INTR_SYNC_ENABLE__WRITE 0xffffffffU + +#endif /* __HOST_INTF_INTR_SYNC_ENABLE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_SYNC_ENABLE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_SYNC_ENABLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_ASYNC_MASK */ +#ifndef __HOST_INTF_INTR_ASYNC_MASK_MACRO__ +#define __HOST_INTF_INTR_ASYNC_MASK_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_ASYNC_MASK__DATA__SHIFT 0 +#define HOST_INTF_INTR_ASYNC_MASK__DATA__WIDTH 32 +#define HOST_INTF_INTR_ASYNC_MASK__DATA__MASK 0xffffffffU +#define HOST_INTF_INTR_ASYNC_MASK__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define HOST_INTF_INTR_ASYNC_MASK__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define HOST_INTF_INTR_ASYNC_MASK__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define HOST_INTF_INTR_ASYNC_MASK__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define HOST_INTF_INTR_ASYNC_MASK__TYPE u_int32_t +#define HOST_INTF_INTR_ASYNC_MASK__READ 0xffffffffU +#define HOST_INTF_INTR_ASYNC_MASK__WRITE 0xffffffffU + +#endif /* __HOST_INTF_INTR_ASYNC_MASK_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_ASYNC_MASK */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_ASYNC_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_SYNC_MASK */ +#ifndef __HOST_INTF_INTR_SYNC_MASK_MACRO__ +#define __HOST_INTF_INTR_SYNC_MASK_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_SYNC_MASK__DATA__SHIFT 0 +#define HOST_INTF_INTR_SYNC_MASK__DATA__WIDTH 32 +#define HOST_INTF_INTR_SYNC_MASK__DATA__MASK 0xffffffffU +#define HOST_INTF_INTR_SYNC_MASK__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define HOST_INTF_INTR_SYNC_MASK__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define HOST_INTF_INTR_SYNC_MASK__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define HOST_INTF_INTR_SYNC_MASK__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define HOST_INTF_INTR_SYNC_MASK__TYPE u_int32_t +#define HOST_INTF_INTR_SYNC_MASK__READ 0xffffffffU +#define HOST_INTF_INTR_SYNC_MASK__WRITE 0xffffffffU + +#endif /* __HOST_INTF_INTR_SYNC_MASK_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_SYNC_MASK */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_SYNC_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_ASYNC_CAUSE */ +#ifndef __HOST_INTF_INTR_ASYNC_CAUSE_MACRO__ +#define __HOST_INTF_INTR_ASYNC_CAUSE_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_ASYNC_CAUSE__DATA__SHIFT 0 +#define HOST_INTF_INTR_ASYNC_CAUSE__DATA__WIDTH 32 +#define HOST_INTF_INTR_ASYNC_CAUSE__DATA__MASK 0xffffffffU +#define HOST_INTF_INTR_ASYNC_CAUSE__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define HOST_INTF_INTR_ASYNC_CAUSE__TYPE u_int32_t +#define HOST_INTF_INTR_ASYNC_CAUSE__READ 0xffffffffU + +#endif /* __HOST_INTF_INTR_ASYNC_CAUSE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_ASYNC_CAUSE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_ASYNC_CAUSE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_ASYNC_ENABLE */ +#ifndef __HOST_INTF_INTR_ASYNC_ENABLE_MACRO__ +#define __HOST_INTF_INTR_ASYNC_ENABLE_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_ASYNC_ENABLE__DATA__SHIFT 0 +#define HOST_INTF_INTR_ASYNC_ENABLE__DATA__WIDTH 32 +#define HOST_INTF_INTR_ASYNC_ENABLE__DATA__MASK 0xffffffffU +#define HOST_INTF_INTR_ASYNC_ENABLE__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define HOST_INTF_INTR_ASYNC_ENABLE__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define HOST_INTF_INTR_ASYNC_ENABLE__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define HOST_INTF_INTR_ASYNC_ENABLE__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define HOST_INTF_INTR_ASYNC_ENABLE__TYPE u_int32_t +#define HOST_INTF_INTR_ASYNC_ENABLE__READ 0xffffffffU +#define HOST_INTF_INTR_ASYNC_ENABLE__WRITE 0xffffffffU + +#endif /* __HOST_INTF_INTR_ASYNC_ENABLE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_ASYNC_ENABLE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_ASYNC_ENABLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_PCIE_PHY_RW */ +#ifndef __HOST_INTF_PCIE_PHY_RW_MACRO__ +#define __HOST_INTF_PCIE_PHY_RW_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_PCIE_PHY_RW__DATA__SHIFT 0 +#define HOST_INTF_PCIE_PHY_RW__DATA__WIDTH 32 +#define HOST_INTF_PCIE_PHY_RW__DATA__MASK 0xffffffffU +#define HOST_INTF_PCIE_PHY_RW__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define HOST_INTF_PCIE_PHY_RW__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define HOST_INTF_PCIE_PHY_RW__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define HOST_INTF_PCIE_PHY_RW__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define HOST_INTF_PCIE_PHY_RW__TYPE u_int32_t +#define HOST_INTF_PCIE_PHY_RW__READ 0xffffffffU +#define HOST_INTF_PCIE_PHY_RW__WRITE 0xffffffffU + +#endif /* __HOST_INTF_PCIE_PHY_RW_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_PCIE_PHY_RW */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_PCIE_PHY_RW__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_PCIE_PHY_LOAD */ +#ifndef __HOST_INTF_PCIE_PHY_LOAD_MACRO__ +#define __HOST_INTF_PCIE_PHY_LOAD_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_PCIE_PHY_LOAD__DATA__SHIFT 0 +#define HOST_INTF_PCIE_PHY_LOAD__DATA__WIDTH 32 +#define HOST_INTF_PCIE_PHY_LOAD__DATA__MASK 0xffffffffU +#define HOST_INTF_PCIE_PHY_LOAD__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define HOST_INTF_PCIE_PHY_LOAD__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define HOST_INTF_PCIE_PHY_LOAD__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define HOST_INTF_PCIE_PHY_LOAD__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define HOST_INTF_PCIE_PHY_LOAD__TYPE u_int32_t +#define HOST_INTF_PCIE_PHY_LOAD__READ 0xffffffffU +#define HOST_INTF_PCIE_PHY_LOAD__WRITE 0xffffffffU + +#endif /* __HOST_INTF_PCIE_PHY_LOAD_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_PCIE_PHY_LOAD */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_PCIE_PHY_LOAD__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_OUT */ +#ifndef __HOST_INTF_GPIO_OUT_MACRO__ +#define __HOST_INTF_GPIO_OUT_MACRO__ + +/* macros for field OUT */ +#define HOST_INTF_GPIO_OUT__OUT__SHIFT 0 +#define HOST_INTF_GPIO_OUT__OUT__WIDTH 17 +#define HOST_INTF_GPIO_OUT__OUT__MASK 0x0001ffffU +#define HOST_INTF_GPIO_OUT__OUT__READ(src) (u_int32_t)(src) & 0x0001ffffU +#define HOST_INTF_GPIO_OUT__OUT__WRITE(src) ((u_int32_t)(src) & 0x0001ffffU) +#define HOST_INTF_GPIO_OUT__OUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ffffU) | ((u_int32_t)(src) &\ + 0x0001ffffU) +#define HOST_INTF_GPIO_OUT__OUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0001ffffU))) +#define HOST_INTF_GPIO_OUT__TYPE u_int32_t +#define HOST_INTF_GPIO_OUT__READ 0x0001ffffU +#define HOST_INTF_GPIO_OUT__WRITE 0x0001ffffU + +#endif /* __HOST_INTF_GPIO_OUT_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_OUT */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_OUT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_IN */ +#ifndef __HOST_INTF_GPIO_IN_MACRO__ +#define __HOST_INTF_GPIO_IN_MACRO__ + +/* macros for field IN */ +#define HOST_INTF_GPIO_IN__IN__SHIFT 0 +#define HOST_INTF_GPIO_IN__IN__WIDTH 17 +#define HOST_INTF_GPIO_IN__IN__MASK 0x0001ffffU +#define HOST_INTF_GPIO_IN__IN__READ(src) (u_int32_t)(src) & 0x0001ffffU +#define HOST_INTF_GPIO_IN__TYPE u_int32_t +#define HOST_INTF_GPIO_IN__READ 0x0001ffffU + +#endif /* __HOST_INTF_GPIO_IN_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_IN */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_IN__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_OE */ +#ifndef __HOST_INTF_GPIO_OE_MACRO__ +#define __HOST_INTF_GPIO_OE_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_GPIO_OE__DATA__SHIFT 0 +#define HOST_INTF_GPIO_OE__DATA__WIDTH 32 +#define HOST_INTF_GPIO_OE__DATA__MASK 0xffffffffU +#define HOST_INTF_GPIO_OE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define HOST_INTF_GPIO_OE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define HOST_INTF_GPIO_OE__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define HOST_INTF_GPIO_OE__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define HOST_INTF_GPIO_OE__TYPE u_int32_t +#define HOST_INTF_GPIO_OE__READ 0xffffffffU +#define HOST_INTF_GPIO_OE__WRITE 0xffffffffU + +#endif /* __HOST_INTF_GPIO_OE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_OE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_OE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_OE1 */ +#ifndef __HOST_INTF_GPIO_OE1_MACRO__ +#define __HOST_INTF_GPIO_OE1_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_GPIO_OE1__DATA__SHIFT 0 +#define HOST_INTF_GPIO_OE1__DATA__WIDTH 2 +#define HOST_INTF_GPIO_OE1__DATA__MASK 0x00000003U +#define HOST_INTF_GPIO_OE1__DATA__READ(src) (u_int32_t)(src) & 0x00000003U +#define HOST_INTF_GPIO_OE1__DATA__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define HOST_INTF_GPIO_OE1__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define HOST_INTF_GPIO_OE1__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) +#define HOST_INTF_GPIO_OE1__TYPE u_int32_t +#define HOST_INTF_GPIO_OE1__READ 0x00000003U +#define HOST_INTF_GPIO_OE1__WRITE 0x00000003U + +#endif /* __HOST_INTF_GPIO_OE1_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_OE1 */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_OE1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_INTR_POLAR */ +#ifndef __HOST_INTF_GPIO_INTR_POLAR_MACRO__ +#define __HOST_INTF_GPIO_INTR_POLAR_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_GPIO_INTR_POLAR__DATA__SHIFT 0 +#define HOST_INTF_GPIO_INTR_POLAR__DATA__WIDTH 17 +#define HOST_INTF_GPIO_INTR_POLAR__DATA__MASK 0x0001ffffU +#define HOST_INTF_GPIO_INTR_POLAR__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x0001ffffU +#define HOST_INTF_GPIO_INTR_POLAR__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0001ffffU) +#define HOST_INTF_GPIO_INTR_POLAR__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ffffU) | ((u_int32_t)(src) &\ + 0x0001ffffU) +#define HOST_INTF_GPIO_INTR_POLAR__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0001ffffU))) +#define HOST_INTF_GPIO_INTR_POLAR__TYPE u_int32_t +#define HOST_INTF_GPIO_INTR_POLAR__READ 0x0001ffffU +#define HOST_INTF_GPIO_INTR_POLAR__WRITE 0x0001ffffU + +#endif /* __HOST_INTF_GPIO_INTR_POLAR_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_INTR_POLAR */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_INTR_POLAR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_INPUT_VALUE */ +#ifndef __HOST_INTF_GPIO_INPUT_VALUE_MACRO__ +#define __HOST_INTF_GPIO_INPUT_VALUE_MACRO__ + +/* macros for field RST_TSF_VAL */ +#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__SHIFT 0 +#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__MASK 0x00000001U +#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RST_AZM_TS_VAL */ +#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__SHIFT 1 +#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__MASK 0x00000002U +#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field BT_PRIORITY_VAL */ +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__SHIFT 2 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__MASK 0x00000004U +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field BT_FREQUENCY_VAL */ +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__SHIFT 3 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__MASK 0x00000008U +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BT_ACTIVE_VAL */ +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__SHIFT 4 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__MASK 0x00000010U +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field ATT_BUT_VAL */ +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__SHIFT 5 +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__MASK 0x00000020U +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field CLK25_VAL */ +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__SHIFT 6 +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__MASK 0x00000040U +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field RFSILENT_BB_L_VAL */ +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__SHIFT 7 +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__MASK 0x00000080U +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field GPIO_RST_TSF_ENABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__SHIFT 8 +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__MASK 0x00000100U +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field GPIO_RST_AZM_TS_ENABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__SHIFT 9 +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__MASK 0x00000200U +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field BT_PRIORITY_ENABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__SHIFT 10 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__MASK 0x00000400U +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field BT_FREQUENCY_ENABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__SHIFT 11 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__MASK 0x00000800U +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field BT_ACTIVE_ENABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__SHIFT 12 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__MASK 0x00001000U +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field ATT_BUT_ENABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__SHIFT 13 +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__MASK 0x00002000U +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field CLK25_ENABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__SHIFT 14 +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__MASK 0x00004000U +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field RFSILENT_BB_L_ENABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__SHIFT 15 +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__MASK 0x00008000U +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field RTC_RESET_OVRD_ENABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__SHIFT 16 +#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__MASK 0x00010000U +#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field DS_JTAG_DISABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__SHIFT 17 +#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__MASK 0x00020000U +#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field BT_PRIORITY_2_VAL */ +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__SHIFT 18 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__MASK 0x00040000U +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field BT_PRIORITY_2_ENABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__SHIFT 19 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__MASK 0x00080000U +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field BT_PRIORITY_3_VAL */ +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__SHIFT 20 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__MASK 0x00100000U +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field BT_PRIORITY_3_ENABLE */ +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__SHIFT 21 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__MASK 0x00200000U +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) +#define HOST_INTF_GPIO_INPUT_VALUE__TYPE u_int32_t +#define HOST_INTF_GPIO_INPUT_VALUE__READ 0x003fffffU +#define HOST_INTF_GPIO_INPUT_VALUE__WRITE 0x003fffffU + +#endif /* __HOST_INTF_GPIO_INPUT_VALUE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_INPUT_VALUE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_INPUT_VALUE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_INPUT_MUX1 */ +#ifndef __HOST_INTF_GPIO_INPUT_MUX1_MACRO__ +#define __HOST_INTF_GPIO_INPUT_MUX1_MACRO__ + +/* macros for field SEL_0 */ +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__SHIFT 0 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__WIDTH 4 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__MASK 0x0000000fU +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field SEL_1 */ +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__SHIFT 4 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__WIDTH 4 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__MASK 0x000000f0U +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field SEL_2 */ +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__SHIFT 8 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__WIDTH 4 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__MASK 0x00000f00U +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field SEL_3 */ +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__SHIFT 12 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__WIDTH 4 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__MASK 0x0000f000U +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field SEL_4 */ +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__SHIFT 16 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__WIDTH 4 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__MASK 0x000f0000U +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field SEL_5 */ +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__SHIFT 20 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__WIDTH 4 +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__MASK 0x00f00000U +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) +#define HOST_INTF_GPIO_INPUT_MUX1__TYPE u_int32_t +#define HOST_INTF_GPIO_INPUT_MUX1__READ 0x00ffffffU +#define HOST_INTF_GPIO_INPUT_MUX1__WRITE 0x00ffffffU + +#endif /* __HOST_INTF_GPIO_INPUT_MUX1_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_INPUT_MUX1 */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_INPUT_MUX1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_INPUT_MUX2 */ +#ifndef __HOST_INTF_GPIO_INPUT_MUX2_MACRO__ +#define __HOST_INTF_GPIO_INPUT_MUX2_MACRO__ + +/* macros for field SEL_6 */ +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__SHIFT 0 +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__WIDTH 4 +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__MASK 0x0000000fU +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field SEL_7 */ +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__SHIFT 4 +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__WIDTH 4 +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__MASK 0x000000f0U +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field SEL_8 */ +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__SHIFT 8 +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__WIDTH 4 +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__MASK 0x00000f00U +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field SEL_9 */ +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__SHIFT 12 +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__WIDTH 4 +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__MASK 0x0000f000U +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field SEL_10 */ +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__SHIFT 16 +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__WIDTH 4 +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__MASK 0x000f0000U +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) +#define HOST_INTF_GPIO_INPUT_MUX2__TYPE u_int32_t +#define HOST_INTF_GPIO_INPUT_MUX2__READ 0x000fffffU +#define HOST_INTF_GPIO_INPUT_MUX2__WRITE 0x000fffffU + +#endif /* __HOST_INTF_GPIO_INPUT_MUX2_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_INPUT_MUX2 */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_INPUT_MUX2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_OUTPUT_MUX1 */ +#ifndef __HOST_INTF_GPIO_OUTPUT_MUX1_MACRO__ +#define __HOST_INTF_GPIO_OUTPUT_MUX1_MACRO__ + +/* macros for field SEL_0 */ +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__SHIFT 0 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__MASK 0x0000001fU +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field SEL_1 */ +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__SHIFT 5 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__MASK 0x000003e0U +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field SEL_2 */ +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__SHIFT 10 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__MASK 0x00007c00U +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field SEL_3 */ +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__SHIFT 15 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__MASK 0x000f8000U +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field SEL_4 */ +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__SHIFT 20 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__MASK 0x01f00000U +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field SEL_5 */ +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__SHIFT 25 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__MASK 0x3e000000U +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define HOST_INTF_GPIO_OUTPUT_MUX1__TYPE u_int32_t +#define HOST_INTF_GPIO_OUTPUT_MUX1__READ 0x3fffffffU +#define HOST_INTF_GPIO_OUTPUT_MUX1__WRITE 0x3fffffffU + +#endif /* __HOST_INTF_GPIO_OUTPUT_MUX1_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_OUTPUT_MUX1 */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_OUTPUT_MUX1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_OUTPUT_MUX2 */ +#ifndef __HOST_INTF_GPIO_OUTPUT_MUX2_MACRO__ +#define __HOST_INTF_GPIO_OUTPUT_MUX2_MACRO__ + +/* macros for field SEL_6 */ +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__SHIFT 0 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__MASK 0x0000001fU +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field SEL_7 */ +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__SHIFT 5 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__MASK 0x000003e0U +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field SEL_8 */ +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__SHIFT 10 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__MASK 0x00007c00U +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field SEL_9 */ +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__SHIFT 15 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__MASK 0x000f8000U +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field SEL_10 */ +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__SHIFT 20 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__MASK 0x01f00000U +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field SEL_11 */ +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__SHIFT 25 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__MASK 0x3e000000U +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define HOST_INTF_GPIO_OUTPUT_MUX2__TYPE u_int32_t +#define HOST_INTF_GPIO_OUTPUT_MUX2__READ 0x3fffffffU +#define HOST_INTF_GPIO_OUTPUT_MUX2__WRITE 0x3fffffffU + +#endif /* __HOST_INTF_GPIO_OUTPUT_MUX2_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_OUTPUT_MUX2 */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_OUTPUT_MUX2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_OUTPUT_MUX3 */ +#ifndef __HOST_INTF_GPIO_OUTPUT_MUX3_MACRO__ +#define __HOST_INTF_GPIO_OUTPUT_MUX3_MACRO__ + +/* macros for field SEL_12 */ +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__SHIFT 0 +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__MASK 0x0000001fU +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field SEL_13 */ +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__SHIFT 5 +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__MASK 0x000003e0U +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field SEL_14 */ +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__SHIFT 10 +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__MASK 0x00007c00U +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field SEL_15 */ +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__SHIFT 15 +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__MASK 0x000f8000U +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field SEL_16 */ +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__SHIFT 20 +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__WIDTH 5 +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__MASK 0x01f00000U +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) +#define HOST_INTF_GPIO_OUTPUT_MUX3__TYPE u_int32_t +#define HOST_INTF_GPIO_OUTPUT_MUX3__READ 0x01ffffffU +#define HOST_INTF_GPIO_OUTPUT_MUX3__WRITE 0x01ffffffU + +#endif /* __HOST_INTF_GPIO_OUTPUT_MUX3_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_OUTPUT_MUX3 */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_OUTPUT_MUX3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_INPUT_STATE */ +#ifndef __HOST_INTF_GPIO_INPUT_STATE_MACRO__ +#define __HOST_INTF_GPIO_INPUT_STATE_MACRO__ + +/* macros for field ATT_LED */ +#define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__SHIFT 0 +#define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__MASK 0x00000001U +#define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PWR_LED */ +#define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__SHIFT 1 +#define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__MASK 0x00000002U +#define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field WAKE_N */ +#define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__SHIFT 2 +#define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__MASK 0x00000004U +#define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field LED_NETWORK_EN */ +#define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__SHIFT 3 +#define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__MASK 0x00000008U +#define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field LED_POWER_EN */ +#define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__SHIFT 4 +#define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__MASK 0x00000010U +#define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field RX_CLEAR_EXTERNAL */ +#define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__SHIFT 5 +#define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__MASK 0x00000020U +#define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field TX_FRAME */ +#define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__SHIFT 6 +#define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__MASK 0x00000040U +#define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field BB_RADIO_XLNAON */ +#define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__SHIFT 7 +#define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__WIDTH 1 +#define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__MASK 0x00000080U +#define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) +#define HOST_INTF_GPIO_INPUT_STATE__TYPE u_int32_t +#define HOST_INTF_GPIO_INPUT_STATE__READ 0x000000ffU + +#endif /* __HOST_INTF_GPIO_INPUT_STATE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_INPUT_STATE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_INPUT_STATE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_SPARE */ +#ifndef __HOST_INTF_SPARE_MACRO__ +#define __HOST_INTF_SPARE_MACRO__ + +/* macros for field SUPER_CONDOR_L1 */ +#define HOST_INTF_SPARE__SUPER_CONDOR_L1__SHIFT 0 +#define HOST_INTF_SPARE__SUPER_CONDOR_L1__WIDTH 32 +#define HOST_INTF_SPARE__SUPER_CONDOR_L1__MASK 0xffffffffU +#define HOST_INTF_SPARE__SUPER_CONDOR_L1__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define HOST_INTF_SPARE__SUPER_CONDOR_L1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define HOST_INTF_SPARE__SUPER_CONDOR_L1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define HOST_INTF_SPARE__SUPER_CONDOR_L1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define HOST_INTF_SPARE__TYPE u_int32_t +#define HOST_INTF_SPARE__READ 0xffffffffU +#define HOST_INTF_SPARE__WRITE 0xffffffffU + +#endif /* __HOST_INTF_SPARE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_SPARE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_SPARE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_PCIE_CORE_RST_EN */ +#ifndef __HOST_INTF_PCIE_CORE_RST_EN_MACRO__ +#define __HOST_INTF_PCIE_CORE_RST_EN_MACRO__ + +/* macros for field TRAINING_RST_EN */ +#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__SHIFT 0 +#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__WIDTH 1 +#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__MASK 0x00000001U +#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field XMLH_LINK_RST_EN */ +#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__SHIFT 1 +#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__WIDTH 1 +#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__MASK 0x00000002U +#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field RDLH_LINK_RST_EN */ +#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__SHIFT 2 +#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__WIDTH 1 +#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__MASK 0x00000004U +#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field LINK_REQ_RST_EN */ +#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__SHIFT 3 +#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__WIDTH 1 +#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__MASK 0x00000008U +#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define HOST_INTF_PCIE_CORE_RST_EN__TYPE u_int32_t +#define HOST_INTF_PCIE_CORE_RST_EN__READ 0x0000000fU +#define HOST_INTF_PCIE_CORE_RST_EN__WRITE 0x0000000fU + +#endif /* __HOST_INTF_PCIE_CORE_RST_EN_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_PCIE_CORE_RST_EN */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_PCIE_CORE_RST_EN__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_CLKRUN */ +#ifndef __HOST_INTF_CLKRUN_MACRO__ +#define __HOST_INTF_CLKRUN_MACRO__ + +/* macros for field FORCE */ +#define HOST_INTF_CLKRUN__FORCE__SHIFT 0 +#define HOST_INTF_CLKRUN__FORCE__WIDTH 1 +#define HOST_INTF_CLKRUN__FORCE__MASK 0x00000001U +#define HOST_INTF_CLKRUN__FORCE__READ(src) (u_int32_t)(src) & 0x00000001U +#define HOST_INTF_CLKRUN__FORCE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define HOST_INTF_CLKRUN__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define HOST_INTF_CLKRUN__FORCE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define HOST_INTF_CLKRUN__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_CLKRUN__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field CNT */ +#define HOST_INTF_CLKRUN__CNT__SHIFT 1 +#define HOST_INTF_CLKRUN__CNT__WIDTH 31 +#define HOST_INTF_CLKRUN__CNT__MASK 0xfffffffeU +#define HOST_INTF_CLKRUN__CNT__READ(src) \ + (((u_int32_t)(src)\ + & 0xfffffffeU) >> 1) +#define HOST_INTF_CLKRUN__CNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0xfffffffeU) +#define HOST_INTF_CLKRUN__CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffffffeU) | (((u_int32_t)(src) <<\ + 1) & 0xfffffffeU) +#define HOST_INTF_CLKRUN__CNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0xfffffffeU))) +#define HOST_INTF_CLKRUN__TYPE u_int32_t +#define HOST_INTF_CLKRUN__READ 0xffffffffU +#define HOST_INTF_CLKRUN__WRITE 0xffffffffU + +#endif /* __HOST_INTF_CLKRUN_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_CLKRUN */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_CLKRUN__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_EEPROM_STS */ +#ifndef __HOST_INTF_EEPROM_STS_MACRO__ +#define __HOST_INTF_EEPROM_STS_MACRO__ + +/* macros for field RD_DATA */ +#define HOST_INTF_EEPROM_STS__RD_DATA__SHIFT 0 +#define HOST_INTF_EEPROM_STS__RD_DATA__WIDTH 16 +#define HOST_INTF_EEPROM_STS__RD_DATA__MASK 0x0000ffffU +#define HOST_INTF_EEPROM_STS__RD_DATA__READ(src) (u_int32_t)(src) & 0x0000ffffU + +/* macros for field BUSY */ +#define HOST_INTF_EEPROM_STS__BUSY__SHIFT 16 +#define HOST_INTF_EEPROM_STS__BUSY__WIDTH 1 +#define HOST_INTF_EEPROM_STS__BUSY__MASK 0x00010000U +#define HOST_INTF_EEPROM_STS__BUSY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define HOST_INTF_EEPROM_STS__BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define HOST_INTF_EEPROM_STS__BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field BUSY_ACCESS */ +#define HOST_INTF_EEPROM_STS__BUSY_ACCESS__SHIFT 17 +#define HOST_INTF_EEPROM_STS__BUSY_ACCESS__WIDTH 1 +#define HOST_INTF_EEPROM_STS__BUSY_ACCESS__MASK 0x00020000U +#define HOST_INTF_EEPROM_STS__BUSY_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define HOST_INTF_EEPROM_STS__BUSY_ACCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define HOST_INTF_EEPROM_STS__BUSY_ACCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field MASK_ACCESS */ +#define HOST_INTF_EEPROM_STS__MASK_ACCESS__SHIFT 18 +#define HOST_INTF_EEPROM_STS__MASK_ACCESS__WIDTH 1 +#define HOST_INTF_EEPROM_STS__MASK_ACCESS__MASK 0x00040000U +#define HOST_INTF_EEPROM_STS__MASK_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define HOST_INTF_EEPROM_STS__MASK_ACCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define HOST_INTF_EEPROM_STS__MASK_ACCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) +#define HOST_INTF_EEPROM_STS__TYPE u_int32_t +#define HOST_INTF_EEPROM_STS__READ 0x0007ffffU + +#endif /* __HOST_INTF_EEPROM_STS_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_EEPROM_STS */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_EEPROM_STS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_OBS_CTRL */ +#ifndef __HOST_INTF_OBS_CTRL_MACRO__ +#define __HOST_INTF_OBS_CTRL_MACRO__ + +/* macros for field OBS_SEL */ +#define HOST_INTF_OBS_CTRL__OBS_SEL__SHIFT 0 +#define HOST_INTF_OBS_CTRL__OBS_SEL__WIDTH 4 +#define HOST_INTF_OBS_CTRL__OBS_SEL__MASK 0x0000000fU +#define HOST_INTF_OBS_CTRL__OBS_SEL__READ(src) (u_int32_t)(src) & 0x0000000fU +#define HOST_INTF_OBS_CTRL__OBS_SEL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define HOST_INTF_OBS_CTRL__OBS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define HOST_INTF_OBS_CTRL__OBS_SEL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field ANT_SEL */ +#define HOST_INTF_OBS_CTRL__ANT_SEL__SHIFT 4 +#define HOST_INTF_OBS_CTRL__ANT_SEL__WIDTH 2 +#define HOST_INTF_OBS_CTRL__ANT_SEL__MASK 0x00000030U +#define HOST_INTF_OBS_CTRL__ANT_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define HOST_INTF_OBS_CTRL__ANT_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define HOST_INTF_OBS_CTRL__ANT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define HOST_INTF_OBS_CTRL__ANT_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field OBS_MODE */ +#define HOST_INTF_OBS_CTRL__OBS_MODE__SHIFT 6 +#define HOST_INTF_OBS_CTRL__OBS_MODE__WIDTH 2 +#define HOST_INTF_OBS_CTRL__OBS_MODE__MASK 0x000000c0U +#define HOST_INTF_OBS_CTRL__OBS_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define HOST_INTF_OBS_CTRL__OBS_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define HOST_INTF_OBS_CTRL__OBS_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define HOST_INTF_OBS_CTRL__OBS_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) +#define HOST_INTF_OBS_CTRL__TYPE u_int32_t +#define HOST_INTF_OBS_CTRL__READ 0x000000ffU +#define HOST_INTF_OBS_CTRL__WRITE 0x000000ffU + +#endif /* __HOST_INTF_OBS_CTRL_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_OBS_CTRL */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_OBS_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_RFSILENT */ +#ifndef __HOST_INTF_RFSILENT_MACRO__ +#define __HOST_INTF_RFSILENT_MACRO__ + +/* macros for field FORCE */ +#define HOST_INTF_RFSILENT__FORCE__SHIFT 0 +#define HOST_INTF_RFSILENT__FORCE__WIDTH 1 +#define HOST_INTF_RFSILENT__FORCE__MASK 0x00000001U +#define HOST_INTF_RFSILENT__FORCE__READ(src) (u_int32_t)(src) & 0x00000001U +#define HOST_INTF_RFSILENT__FORCE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define HOST_INTF_RFSILENT__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define HOST_INTF_RFSILENT__FORCE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define HOST_INTF_RFSILENT__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_RFSILENT__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field INVERT */ +#define HOST_INTF_RFSILENT__INVERT__SHIFT 1 +#define HOST_INTF_RFSILENT__INVERT__WIDTH 1 +#define HOST_INTF_RFSILENT__INVERT__MASK 0x00000002U +#define HOST_INTF_RFSILENT__INVERT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define HOST_INTF_RFSILENT__INVERT__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define HOST_INTF_RFSILENT__INVERT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define HOST_INTF_RFSILENT__INVERT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define HOST_INTF_RFSILENT__INVERT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define HOST_INTF_RFSILENT__INVERT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field RTC_RESET_INVERT */ +#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__SHIFT 2 +#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__WIDTH 1 +#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__MASK 0x00000004U +#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define HOST_INTF_RFSILENT__TYPE u_int32_t +#define HOST_INTF_RFSILENT__READ 0x00000007U +#define HOST_INTF_RFSILENT__WRITE 0x00000007U + +#endif /* __HOST_INTF_RFSILENT_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_RFSILENT */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_RFSILENT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_PDPU */ +#ifndef __HOST_INTF_GPIO_PDPU_MACRO__ +#define __HOST_INTF_GPIO_PDPU_MACRO__ + +/* macros for field INT */ +#define HOST_INTF_GPIO_PDPU__INT__SHIFT 0 +#define HOST_INTF_GPIO_PDPU__INT__WIDTH 32 +#define HOST_INTF_GPIO_PDPU__INT__MASK 0xffffffffU +#define HOST_INTF_GPIO_PDPU__INT__READ(src) (u_int32_t)(src) & 0xffffffffU +#define HOST_INTF_GPIO_PDPU__INT__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define HOST_INTF_GPIO_PDPU__INT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define HOST_INTF_GPIO_PDPU__INT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define HOST_INTF_GPIO_PDPU__TYPE u_int32_t +#define HOST_INTF_GPIO_PDPU__READ 0xffffffffU +#define HOST_INTF_GPIO_PDPU__WRITE 0xffffffffU + +#endif /* __HOST_INTF_GPIO_PDPU_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_PDPU */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_PDPU__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_PDPU1 */ +#ifndef __HOST_INTF_GPIO_PDPU1_MACRO__ +#define __HOST_INTF_GPIO_PDPU1_MACRO__ + +/* macros for field INT */ +#define HOST_INTF_GPIO_PDPU1__INT__SHIFT 0 +#define HOST_INTF_GPIO_PDPU1__INT__WIDTH 2 +#define HOST_INTF_GPIO_PDPU1__INT__MASK 0x00000003U +#define HOST_INTF_GPIO_PDPU1__INT__READ(src) (u_int32_t)(src) & 0x00000003U +#define HOST_INTF_GPIO_PDPU1__INT__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define HOST_INTF_GPIO_PDPU1__INT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define HOST_INTF_GPIO_PDPU1__INT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) +#define HOST_INTF_GPIO_PDPU1__TYPE u_int32_t +#define HOST_INTF_GPIO_PDPU1__READ 0x00000003U +#define HOST_INTF_GPIO_PDPU1__WRITE 0x00000003U + +#endif /* __HOST_INTF_GPIO_PDPU1_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_PDPU1 */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_PDPU1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_DS */ +#ifndef __HOST_INTF_GPIO_DS_MACRO__ +#define __HOST_INTF_GPIO_DS_MACRO__ + +/* macros for field INT */ +#define HOST_INTF_GPIO_DS__INT__SHIFT 0 +#define HOST_INTF_GPIO_DS__INT__WIDTH 32 +#define HOST_INTF_GPIO_DS__INT__MASK 0xffffffffU +#define HOST_INTF_GPIO_DS__INT__READ(src) (u_int32_t)(src) & 0xffffffffU +#define HOST_INTF_GPIO_DS__INT__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define HOST_INTF_GPIO_DS__INT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define HOST_INTF_GPIO_DS__INT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define HOST_INTF_GPIO_DS__TYPE u_int32_t +#define HOST_INTF_GPIO_DS__READ 0xffffffffU +#define HOST_INTF_GPIO_DS__WRITE 0xffffffffU + +#endif /* __HOST_INTF_GPIO_DS_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_DS */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_DS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_GPIO_DS1 */ +#ifndef __HOST_INTF_GPIO_DS1_MACRO__ +#define __HOST_INTF_GPIO_DS1_MACRO__ + +/* macros for field INT */ +#define HOST_INTF_GPIO_DS1__INT__SHIFT 0 +#define HOST_INTF_GPIO_DS1__INT__WIDTH 2 +#define HOST_INTF_GPIO_DS1__INT__MASK 0x00000003U +#define HOST_INTF_GPIO_DS1__INT__READ(src) (u_int32_t)(src) & 0x00000003U +#define HOST_INTF_GPIO_DS1__INT__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define HOST_INTF_GPIO_DS1__INT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define HOST_INTF_GPIO_DS1__INT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) +#define HOST_INTF_GPIO_DS1__TYPE u_int32_t +#define HOST_INTF_GPIO_DS1__READ 0x00000003U +#define HOST_INTF_GPIO_DS1__WRITE 0x00000003U + +#endif /* __HOST_INTF_GPIO_DS1_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_GPIO_DS1 */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_GPIO_DS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_MISC */ +#ifndef __HOST_INTF_MISC_MACRO__ +#define __HOST_INTF_MISC_MACRO__ + +/* macros for field AT_SPEED_EN */ +#define HOST_INTF_MISC__AT_SPEED_EN__SHIFT 0 +#define HOST_INTF_MISC__AT_SPEED_EN__WIDTH 1 +#define HOST_INTF_MISC__AT_SPEED_EN__MASK 0x00000001U +#define HOST_INTF_MISC__AT_SPEED_EN__READ(src) (u_int32_t)(src) & 0x00000001U +#define HOST_INTF_MISC__AT_SPEED_EN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define HOST_INTF_MISC__AT_SPEED_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define HOST_INTF_MISC__AT_SPEED_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define HOST_INTF_MISC__AT_SPEED_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_MISC__AT_SPEED_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field OTP_DEBUG_MODE_SEL */ +#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__SHIFT 1 +#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__WIDTH 1 +#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__MASK 0x00000002U +#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field OTP_DEBUG_EFUSE_MEM_SEL */ +#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__SHIFT 2 +#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__WIDTH 1 +#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__MASK 0x00000004U +#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define HOST_INTF_MISC__TYPE u_int32_t +#define HOST_INTF_MISC__READ 0x00000007U +#define HOST_INTF_MISC__WRITE 0x00000007U + +#endif /* __HOST_INTF_MISC_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_MISC */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_MISC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_PCIE_MSI */ +#ifndef __HOST_INTF_PCIE_MSI_MACRO__ +#define __HOST_INTF_PCIE_MSI_MACRO__ + +/* macros for field INT_EN */ +#define HOST_INTF_PCIE_MSI__INT_EN__SHIFT 0 +#define HOST_INTF_PCIE_MSI__INT_EN__WIDTH 1 +#define HOST_INTF_PCIE_MSI__INT_EN__MASK 0x00000001U +#define HOST_INTF_PCIE_MSI__INT_EN__READ(src) (u_int32_t)(src) & 0x00000001U +#define HOST_INTF_PCIE_MSI__INT_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define HOST_INTF_PCIE_MSI__INT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define HOST_INTF_PCIE_MSI__INT_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define HOST_INTF_PCIE_MSI__INT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_PCIE_MSI__INT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field MULTI_MSI */ +#define HOST_INTF_PCIE_MSI__MULTI_MSI__SHIFT 1 +#define HOST_INTF_PCIE_MSI__MULTI_MSI__WIDTH 8 +#define HOST_INTF_PCIE_MSI__MULTI_MSI__MASK 0x000001feU +#define HOST_INTF_PCIE_MSI__MULTI_MSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) +#define HOST_INTF_PCIE_MSI__MULTI_MSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000001feU) +#define HOST_INTF_PCIE_MSI__MULTI_MSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((u_int32_t)(src) <<\ + 1) & 0x000001feU) +#define HOST_INTF_PCIE_MSI__MULTI_MSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000001feU))) + +/* macros for field INT_PENDING_ADDR */ +#define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__SHIFT 9 +#define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__WIDTH 16 +#define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__MASK 0x01fffe00U +#define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fffe00U) >> 9) +#define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x01fffe00U) +#define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fffe00U) | (((u_int32_t)(src) <<\ + 9) & 0x01fffe00U) +#define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x01fffe00U))) + +/* macros for field HW_DBI_WR_EN */ +#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__SHIFT 25 +#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__WIDTH 1 +#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__MASK 0x02000000U +#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field IRQ_PENDING */ +#define HOST_INTF_PCIE_MSI__IRQ_PENDING__SHIFT 26 +#define HOST_INTF_PCIE_MSI__IRQ_PENDING__WIDTH 4 +#define HOST_INTF_PCIE_MSI__IRQ_PENDING__MASK 0x3c000000U +#define HOST_INTF_PCIE_MSI__IRQ_PENDING__READ(src) \ + (((u_int32_t)(src)\ + & 0x3c000000U) >> 26) +#define HOST_INTF_PCIE_MSI__TYPE u_int32_t +#define HOST_INTF_PCIE_MSI__READ 0x3fffffffU +#define HOST_INTF_PCIE_MSI__WRITE 0x3fffffffU + +#endif /* __HOST_INTF_PCIE_MSI_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_PCIE_MSI */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_PCIE_MSI__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ */ +#ifndef __HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ_MACRO__ +#define __HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__SHIFT 0 +#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__WIDTH 24 +#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__MASK 0x00ffffffU +#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x00ffffffU +#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__TYPE u_int32_t +#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__READ 0x00ffffffU +#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__WRITE 0x00ffffffU + +#endif /* __HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_MAC_TDMA_CCA_CNTL */ +#ifndef __HOST_INTF_MAC_TDMA_CCA_CNTL_MACRO__ +#define __HOST_INTF_MAC_TDMA_CCA_CNTL_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__SHIFT 0 +#define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__WIDTH 2 +#define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__MASK 0x00000003U +#define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) +#define HOST_INTF_MAC_TDMA_CCA_CNTL__TYPE u_int32_t +#define HOST_INTF_MAC_TDMA_CCA_CNTL__READ 0x00000003U +#define HOST_INTF_MAC_TDMA_CCA_CNTL__WRITE 0x00000003U + +#endif /* __HOST_INTF_MAC_TDMA_CCA_CNTL_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_MAC_TDMA_CCA_CNTL */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_MAC_TDMA_CCA_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_MAC_TXAPSYNC */ +#ifndef __HOST_INTF_MAC_TXAPSYNC_MACRO__ +#define __HOST_INTF_MAC_TXAPSYNC_MACRO__ + +/* macros for field ENABLE */ +#define HOST_INTF_MAC_TXAPSYNC__ENABLE__SHIFT 0 +#define HOST_INTF_MAC_TXAPSYNC__ENABLE__WIDTH 1 +#define HOST_INTF_MAC_TXAPSYNC__ENABLE__MASK 0x00000001U +#define HOST_INTF_MAC_TXAPSYNC__ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define HOST_INTF_MAC_TXAPSYNC__ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define HOST_INTF_MAC_TXAPSYNC__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define HOST_INTF_MAC_TXAPSYNC__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define HOST_INTF_MAC_TXAPSYNC__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define HOST_INTF_MAC_TXAPSYNC__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define HOST_INTF_MAC_TXAPSYNC__TYPE u_int32_t +#define HOST_INTF_MAC_TXAPSYNC__READ 0x00000001U +#define HOST_INTF_MAC_TXAPSYNC__WRITE 0x00000001U + +#endif /* __HOST_INTF_MAC_TXAPSYNC_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_MAC_TXAPSYNC */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_MAC_TXAPSYNC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR */ +#ifndef __HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR_MACRO__ +#define __HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__SHIFT 0 +#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__WIDTH 16 +#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__MASK 0x0000ffffU +#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__TYPE u_int32_t +#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__READ 0x0000ffffU +#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__WRITE 0x0000ffffU + +#endif /* __HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_PRIORITY_SYNC_CAUSE */ +#ifndef __HOST_INTF_INTR_PRIORITY_SYNC_CAUSE_MACRO__ +#define __HOST_INTF_INTR_PRIORITY_SYNC_CAUSE_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__SHIFT 0 +#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__WIDTH 3 +#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__MASK 0x00000007U +#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) +#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__TYPE u_int32_t +#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__READ 0x00000007U +#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__WRITE 0x00000007U + +#endif /* __HOST_INTF_INTR_PRIORITY_SYNC_CAUSE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_PRIORITY_SYNC_CAUSE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_PRIORITY_SYNC_ENABLE */ +#ifndef __HOST_INTF_INTR_PRIORITY_SYNC_ENABLE_MACRO__ +#define __HOST_INTF_INTR_PRIORITY_SYNC_ENABLE_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__SHIFT 0 +#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__WIDTH 3 +#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__MASK 0x00000007U +#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) +#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__TYPE u_int32_t +#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__READ 0x00000007U +#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__WRITE 0x00000007U + +#endif /* __HOST_INTF_INTR_PRIORITY_SYNC_ENABLE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_PRIORITY_SYNC_ENABLE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_PRIORITY_ASYNC_MASK */ +#ifndef __HOST_INTF_INTR_PRIORITY_ASYNC_MASK_MACRO__ +#define __HOST_INTF_INTR_PRIORITY_ASYNC_MASK_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__SHIFT 0 +#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__WIDTH 3 +#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__MASK 0x00000007U +#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) +#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__TYPE u_int32_t +#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__READ 0x00000007U +#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__WRITE 0x00000007U + +#endif /* __HOST_INTF_INTR_PRIORITY_ASYNC_MASK_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_PRIORITY_ASYNC_MASK */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_PRIORITY_ASYNC_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_PRIORITY_SYNC_MASK */ +#ifndef __HOST_INTF_INTR_PRIORITY_SYNC_MASK_MACRO__ +#define __HOST_INTF_INTR_PRIORITY_SYNC_MASK_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__SHIFT 0 +#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__WIDTH 3 +#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__MASK 0x00000007U +#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) +#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__TYPE u_int32_t +#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__READ 0x00000007U +#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__WRITE 0x00000007U + +#endif /* __HOST_INTF_INTR_PRIORITY_SYNC_MASK_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_PRIORITY_SYNC_MASK */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_PRIORITY_SYNC_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE */ +#ifndef __HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE_MACRO__ +#define __HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE__DATA__SHIFT 0 +#define HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE__DATA__WIDTH 3 +#define HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE__DATA__MASK 0x00000007U +#define HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE__TYPE u_int32_t +#define HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE__READ 0x00000007U + +#endif /* __HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE */ +#ifndef __HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE_MACRO__ +#define __HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE_MACRO__ + +/* macros for field DATA */ +#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__SHIFT 0 +#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__WIDTH 3 +#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__MASK 0x00000007U +#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) +#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__TYPE u_int32_t +#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__READ 0x00000007U +#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__WRITE 0x00000007U + +#endif /* __HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::HOST_INTF_OTP */ +#ifndef __HOST_INTF_OTP_MACRO__ +#define __HOST_INTF_OTP_MACRO__ + +/* macros for field BOND_OPTION */ +#define HOST_INTF_OTP__BOND_OPTION__SHIFT 0 +#define HOST_INTF_OTP__BOND_OPTION__WIDTH 32 +#define HOST_INTF_OTP__BOND_OPTION__MASK 0xffffffffU +#define HOST_INTF_OTP__BOND_OPTION__READ(src) (u_int32_t)(src) & 0xffffffffU +#define HOST_INTF_OTP__TYPE u_int32_t +#define HOST_INTF_OTP__READ 0xffffffffU + +#endif /* __HOST_INTF_OTP_MACRO__ */ + + +/* macros for host_intf_reg_block.HOST_INTF_OTP */ +#define INST_HOST_INTF_REG_BLOCK__HOST_INTF_OTP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCIE_CO_ERR_CTR0 */ +#ifndef __PCIE_CO_ERR_CTR0_MACRO__ +#define __PCIE_CO_ERR_CTR0_MACRO__ + +/* macros for field RCVD_ERR */ +#define PCIE_CO_ERR_CTR0__RCVD_ERR__SHIFT 0 +#define PCIE_CO_ERR_CTR0__RCVD_ERR__WIDTH 8 +#define PCIE_CO_ERR_CTR0__RCVD_ERR__MASK 0x000000ffU +#define PCIE_CO_ERR_CTR0__RCVD_ERR__READ(src) (u_int32_t)(src) & 0x000000ffU +#define PCIE_CO_ERR_CTR0__RCVD_ERR__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define PCIE_CO_ERR_CTR0__RCVD_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define PCIE_CO_ERR_CTR0__RCVD_ERR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field BAD_TLP_ERR */ +#define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__SHIFT 8 +#define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__WIDTH 8 +#define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__MASK 0x0000ff00U +#define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field BAD_DLLP_ERR */ +#define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__SHIFT 16 +#define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__WIDTH 8 +#define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__MASK 0x00ff0000U +#define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define PCIE_CO_ERR_CTR0__TYPE u_int32_t +#define PCIE_CO_ERR_CTR0__READ 0x00ffffffU +#define PCIE_CO_ERR_CTR0__WRITE 0x00ffffffU + +#endif /* __PCIE_CO_ERR_CTR0_MACRO__ */ + + +/* macros for host_intf_reg_block.PCIE_CO_ERR_CTR0 */ +#define INST_HOST_INTF_REG_BLOCK__PCIE_CO_ERR_CTR0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCIE_CO_ERR_CTR1 */ +#ifndef __PCIE_CO_ERR_CTR1_MACRO__ +#define __PCIE_CO_ERR_CTR1_MACRO__ + +/* macros for field RPLY_TO_ERR */ +#define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__SHIFT 0 +#define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__WIDTH 8 +#define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__MASK 0x000000ffU +#define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__READ(src) (u_int32_t)(src) & 0x000000ffU +#define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field RPLY_NUM_RO_ERR */ +#define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__SHIFT 8 +#define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__WIDTH 8 +#define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__MASK 0x0000ff00U +#define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define PCIE_CO_ERR_CTR1__TYPE u_int32_t +#define PCIE_CO_ERR_CTR1__READ 0x0000ffffU +#define PCIE_CO_ERR_CTR1__WRITE 0x0000ffffU + +#endif /* __PCIE_CO_ERR_CTR1_MACRO__ */ + + +/* macros for host_intf_reg_block.PCIE_CO_ERR_CTR1 */ +#define INST_HOST_INTF_REG_BLOCK__PCIE_CO_ERR_CTR1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCIE_CO_ERR_CTR_CTRL */ +#ifndef __PCIE_CO_ERR_CTR_CTRL_MACRO__ +#define __PCIE_CO_ERR_CTR_CTRL_MACRO__ + +/* macros for field RCVD_ERR_CTR_RUN */ +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__SHIFT 0 +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__WIDTH 1 +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__MASK 0x00000001U +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RCVD_ERR_CTR_AUTO_STOP */ +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__SHIFT 1 +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__WIDTH 1 +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__MASK 0x00000002U +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field BAD_TLP_ERR_CTR_RUN */ +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__SHIFT 2 +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__WIDTH 1 +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__MASK 0x00000004U +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field BAD_TLP_ERR_CTR_AUTO_STOP */ +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__SHIFT 3 +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__WIDTH 1 +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__MASK 0x00000008U +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BAD_DLLP_ERR_CTR_RUN */ +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__SHIFT 4 +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__WIDTH 1 +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__MASK 0x00000010U +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field BAD_DLLP_ERR_CTR_AUTO_STOP */ +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__SHIFT 5 +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__WIDTH 1 +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__MASK 0x00000020U +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field RPLY_TO_ERR_CTR_RUN */ +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__SHIFT 6 +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__WIDTH 1 +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__MASK 0x00000040U +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field RPLY_TO_ERR_CTR_AUTO_STOP */ +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__SHIFT 7 +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__WIDTH 1 +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__MASK 0x00000080U +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field RPLY_NUM_RO_ERR_CTR_RUN */ +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__SHIFT 8 +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__WIDTH 1 +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__MASK 0x00000100U +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field RPLY_NUM_RO_ERR_CTR_AUTO_STOP */ +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__SHIFT 9 +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__WIDTH 1 +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__MASK 0x00000200U +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) +#define PCIE_CO_ERR_CTR_CTRL__TYPE u_int32_t +#define PCIE_CO_ERR_CTR_CTRL__READ 0x000003ffU +#define PCIE_CO_ERR_CTR_CTRL__WRITE 0x000003ffU + +#endif /* __PCIE_CO_ERR_CTR_CTRL_MACRO__ */ + + +/* macros for host_intf_reg_block.PCIE_CO_ERR_CTR_CTRL */ +#define INST_HOST_INTF_REG_BLOCK__PCIE_CO_ERR_CTR_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_PHY_LAYER_REVID */ +#ifndef __FPGA_PHY_LAYER_REVID_MACRO__ +#define __FPGA_PHY_LAYER_REVID_MACRO__ + +/* macros for field FPGA_RADIO_FEATURE_INDEX */ +#define FPGA_PHY_LAYER_REVID__FPGA_RADIO_FEATURE_INDEX__SHIFT 0 +#define FPGA_PHY_LAYER_REVID__FPGA_RADIO_FEATURE_INDEX__WIDTH 16 +#define FPGA_PHY_LAYER_REVID__FPGA_RADIO_FEATURE_INDEX__MASK 0x0000ffffU +#define FPGA_PHY_LAYER_REVID__FPGA_RADIO_FEATURE_INDEX__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field FPGA_BASEBAND_FEATURE_INDEX */ +#define FPGA_PHY_LAYER_REVID__FPGA_BASEBAND_FEATURE_INDEX__SHIFT 16 +#define FPGA_PHY_LAYER_REVID__FPGA_BASEBAND_FEATURE_INDEX__WIDTH 16 +#define FPGA_PHY_LAYER_REVID__FPGA_BASEBAND_FEATURE_INDEX__MASK 0xffff0000U +#define FPGA_PHY_LAYER_REVID__FPGA_BASEBAND_FEATURE_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define FPGA_PHY_LAYER_REVID__TYPE u_int32_t +#define FPGA_PHY_LAYER_REVID__READ 0xffffffffU + +#endif /* __FPGA_PHY_LAYER_REVID_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_PHY_LAYER_REVID */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_PHY_LAYER_REVID__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_LINK_LAYER_REVID */ +#ifndef __FPGA_LINK_LAYER_REVID_MACRO__ +#define __FPGA_LINK_LAYER_REVID_MACRO__ + +/* macros for field FPGA_MAC_FEATURE_INDEX */ +#define FPGA_LINK_LAYER_REVID__FPGA_MAC_FEATURE_INDEX__SHIFT 0 +#define FPGA_LINK_LAYER_REVID__FPGA_MAC_FEATURE_INDEX__WIDTH 16 +#define FPGA_LINK_LAYER_REVID__FPGA_MAC_FEATURE_INDEX__MASK 0x0000ffffU +#define FPGA_LINK_LAYER_REVID__FPGA_MAC_FEATURE_INDEX__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field FPGA_SOC_FEATURE_INDEX */ +#define FPGA_LINK_LAYER_REVID__FPGA_SOC_FEATURE_INDEX__SHIFT 16 +#define FPGA_LINK_LAYER_REVID__FPGA_SOC_FEATURE_INDEX__WIDTH 16 +#define FPGA_LINK_LAYER_REVID__FPGA_SOC_FEATURE_INDEX__MASK 0xffff0000U +#define FPGA_LINK_LAYER_REVID__FPGA_SOC_FEATURE_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define FPGA_LINK_LAYER_REVID__TYPE u_int32_t +#define FPGA_LINK_LAYER_REVID__READ 0xffffffffU + +#endif /* __FPGA_LINK_LAYER_REVID_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_LINK_LAYER_REVID */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_LINK_LAYER_REVID__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_REG1 */ +#ifndef __FPGA_REG1_MACRO__ +#define __FPGA_REG1_MACRO__ + +/* macros for field spare_reg1_bit0 */ +#define FPGA_REG1__SPARE_REG1_BIT0__SHIFT 0 +#define FPGA_REG1__SPARE_REG1_BIT0__WIDTH 1 +#define FPGA_REG1__SPARE_REG1_BIT0__MASK 0x00000001U +#define FPGA_REG1__SPARE_REG1_BIT0__READ(src) (u_int32_t)(src) & 0x00000001U +#define FPGA_REG1__SPARE_REG1_BIT0__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define FPGA_REG1__SPARE_REG1_BIT0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define FPGA_REG1__SPARE_REG1_BIT0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define FPGA_REG1__SPARE_REG1_BIT0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define FPGA_REG1__SPARE_REG1_BIT0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field mask_rx_rf */ +#define FPGA_REG1__MASK_RX_RF__SHIFT 1 +#define FPGA_REG1__MASK_RX_RF__WIDTH 1 +#define FPGA_REG1__MASK_RX_RF__MASK 0x00000002U +#define FPGA_REG1__MASK_RX_RF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define FPGA_REG1__MASK_RX_RF__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define FPGA_REG1__MASK_RX_RF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define FPGA_REG1__MASK_RX_RF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define FPGA_REG1__MASK_RX_RF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define FPGA_REG1__MASK_RX_RF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field dcm_release */ +#define FPGA_REG1__DCM_RELEASE__SHIFT 2 +#define FPGA_REG1__DCM_RELEASE__WIDTH 1 +#define FPGA_REG1__DCM_RELEASE__MASK 0x00000004U +#define FPGA_REG1__DCM_RELEASE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define FPGA_REG1__DCM_RELEASE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define FPGA_REG1__DCM_RELEASE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field SPARE0 */ +#define FPGA_REG1__SPARE0__SHIFT 3 +#define FPGA_REG1__SPARE0__WIDTH 1 +#define FPGA_REG1__SPARE0__MASK 0x00000008U +#define FPGA_REG1__SPARE0__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define FPGA_REG1__SPARE0__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define FPGA_REG1__SPARE0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define FPGA_REG1__SPARE0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define FPGA_REG1__SPARE0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define FPGA_REG1__SPARE0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field emulation_clock_ratio */ +#define FPGA_REG1__EMULATION_CLOCK_RATIO__SHIFT 4 +#define FPGA_REG1__EMULATION_CLOCK_RATIO__WIDTH 4 +#define FPGA_REG1__EMULATION_CLOCK_RATIO__MASK 0x000000f0U +#define FPGA_REG1__EMULATION_CLOCK_RATIO__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define FPGA_REG1__EMULATION_CLOCK_RATIO__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define FPGA_REG1__EMULATION_CLOCK_RATIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define FPGA_REG1__EMULATION_CLOCK_RATIO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field long_shift_chain_override_index */ +#define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__SHIFT 8 +#define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__WIDTH 2 +#define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__MASK 0x00000300U +#define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field enable_long_shift_chain_override_index */ +#define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__SHIFT 10 +#define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__WIDTH 1 +#define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__MASK 0x00000400U +#define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field SPARE1 */ +#define FPGA_REG1__SPARE1__SHIFT 11 +#define FPGA_REG1__SPARE1__WIDTH 21 +#define FPGA_REG1__SPARE1__MASK 0xfffff800U +#define FPGA_REG1__SPARE1__READ(src) (((u_int32_t)(src) & 0xfffff800U) >> 11) +#define FPGA_REG1__SPARE1__WRITE(src) (((u_int32_t)(src) << 11) & 0xfffff800U) +#define FPGA_REG1__SPARE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffff800U) | (((u_int32_t)(src) <<\ + 11) & 0xfffff800U) +#define FPGA_REG1__SPARE1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0xfffff800U))) +#define FPGA_REG1__TYPE u_int32_t +#define FPGA_REG1__READ 0xffffffffU +#define FPGA_REG1__WRITE 0xffffffffU + +#endif /* __FPGA_REG1_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_REG1 */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_REG1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_REG2 */ +#ifndef __FPGA_REG2_MACRO__ +#define __FPGA_REG2_MACRO__ + +/* macros for field RxPipeIFerrInjEn */ +#define FPGA_REG2__RXPIPEIFERRINJEN__SHIFT 0 +#define FPGA_REG2__RXPIPEIFERRINJEN__WIDTH 1 +#define FPGA_REG2__RXPIPEIFERRINJEN__MASK 0x00000001U +#define FPGA_REG2__RXPIPEIFERRINJEN__READ(src) (u_int32_t)(src) & 0x00000001U +#define FPGA_REG2__RXPIPEIFERRINJEN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define FPGA_REG2__RXPIPEIFERRINJEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define FPGA_REG2__RXPIPEIFERRINJEN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define FPGA_REG2__RXPIPEIFERRINJEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define FPGA_REG2__RXPIPEIFERRINJEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field TxPipeIFerrInjEn */ +#define FPGA_REG2__TXPIPEIFERRINJEN__SHIFT 1 +#define FPGA_REG2__TXPIPEIFERRINJEN__WIDTH 1 +#define FPGA_REG2__TXPIPEIFERRINJEN__MASK 0x00000002U +#define FPGA_REG2__TXPIPEIFERRINJEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define FPGA_REG2__TXPIPEIFERRINJEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define FPGA_REG2__TXPIPEIFERRINJEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define FPGA_REG2__TXPIPEIFERRINJEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define FPGA_REG2__TXPIPEIFERRINJEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define FPGA_REG2__TXPIPEIFERRINJEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field RxPipeIFInjErrInDataK */ +#define FPGA_REG2__RXPIPEIFINJERRINDATAK__SHIFT 2 +#define FPGA_REG2__RXPIPEIFINJERRINDATAK__WIDTH 1 +#define FPGA_REG2__RXPIPEIFINJERRINDATAK__MASK 0x00000004U +#define FPGA_REG2__RXPIPEIFINJERRINDATAK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define FPGA_REG2__RXPIPEIFINJERRINDATAK__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define FPGA_REG2__RXPIPEIFINJERRINDATAK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define FPGA_REG2__RXPIPEIFINJERRINDATAK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define FPGA_REG2__RXPIPEIFINJERRINDATAK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define FPGA_REG2__RXPIPEIFINJERRINDATAK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field TxPipeIFInjErrInDataK */ +#define FPGA_REG2__TXPIPEIFINJERRINDATAK__SHIFT 3 +#define FPGA_REG2__TXPIPEIFINJERRINDATAK__WIDTH 1 +#define FPGA_REG2__TXPIPEIFINJERRINDATAK__MASK 0x00000008U +#define FPGA_REG2__TXPIPEIFINJERRINDATAK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define FPGA_REG2__TXPIPEIFINJERRINDATAK__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define FPGA_REG2__TXPIPEIFINJERRINDATAK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define FPGA_REG2__TXPIPEIFINJERRINDATAK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define FPGA_REG2__TXPIPEIFINJERRINDATAK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define FPGA_REG2__TXPIPEIFINJERRINDATAK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field dummy_error_injection */ +#define FPGA_REG2__DUMMY_ERROR_INJECTION__SHIFT 4 +#define FPGA_REG2__DUMMY_ERROR_INJECTION__WIDTH 28 +#define FPGA_REG2__DUMMY_ERROR_INJECTION__MASK 0xfffffff0U +#define FPGA_REG2__DUMMY_ERROR_INJECTION__READ(src) \ + (((u_int32_t)(src)\ + & 0xfffffff0U) >> 4) +#define FPGA_REG2__DUMMY_ERROR_INJECTION__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0xfffffff0U) +#define FPGA_REG2__DUMMY_ERROR_INJECTION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffffff0U) | (((u_int32_t)(src) <<\ + 4) & 0xfffffff0U) +#define FPGA_REG2__DUMMY_ERROR_INJECTION__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0xfffffff0U))) +#define FPGA_REG2__TYPE u_int32_t +#define FPGA_REG2__READ 0xffffffffU +#define FPGA_REG2__WRITE 0xffffffffU + +#endif /* __FPGA_REG2_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_REG2 */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_REG2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_REG3 */ +#ifndef __FPGA_REG3_MACRO__ +#define __FPGA_REG3_MACRO__ + +/* macros for field fpga_changelist */ +#define FPGA_REG3__FPGA_CHANGELIST__SHIFT 0 +#define FPGA_REG3__FPGA_CHANGELIST__WIDTH 32 +#define FPGA_REG3__FPGA_CHANGELIST__MASK 0xffffffffU +#define FPGA_REG3__FPGA_CHANGELIST__READ(src) (u_int32_t)(src) & 0xffffffffU +#define FPGA_REG3__TYPE u_int32_t +#define FPGA_REG3__READ 0xffffffffU + +#endif /* __FPGA_REG3_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_REG3 */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_REG3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_REG4 */ +#ifndef __FPGA_REG4_MACRO__ +#define __FPGA_REG4_MACRO__ + +/* macros for field radio_0_tck */ +#define FPGA_REG4__RADIO_0_TCK__SHIFT 0 +#define FPGA_REG4__RADIO_0_TCK__WIDTH 1 +#define FPGA_REG4__RADIO_0_TCK__MASK 0x00000001U +#define FPGA_REG4__RADIO_0_TCK__READ(src) (u_int32_t)(src) & 0x00000001U +#define FPGA_REG4__RADIO_0_TCK__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define FPGA_REG4__RADIO_0_TCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define FPGA_REG4__RADIO_0_TCK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define FPGA_REG4__RADIO_0_TCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define FPGA_REG4__RADIO_0_TCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field radio_0_tdi */ +#define FPGA_REG4__RADIO_0_TDI__SHIFT 1 +#define FPGA_REG4__RADIO_0_TDI__WIDTH 1 +#define FPGA_REG4__RADIO_0_TDI__MASK 0x00000002U +#define FPGA_REG4__RADIO_0_TDI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define FPGA_REG4__RADIO_0_TDI__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define FPGA_REG4__RADIO_0_TDI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define FPGA_REG4__RADIO_0_TDI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define FPGA_REG4__RADIO_0_TDI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define FPGA_REG4__RADIO_0_TDI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field radio_0_tms */ +#define FPGA_REG4__RADIO_0_TMS__SHIFT 2 +#define FPGA_REG4__RADIO_0_TMS__WIDTH 1 +#define FPGA_REG4__RADIO_0_TMS__MASK 0x00000004U +#define FPGA_REG4__RADIO_0_TMS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define FPGA_REG4__RADIO_0_TMS__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define FPGA_REG4__RADIO_0_TMS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define FPGA_REG4__RADIO_0_TMS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define FPGA_REG4__RADIO_0_TMS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define FPGA_REG4__RADIO_0_TMS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field radio_0_tdo */ +#define FPGA_REG4__RADIO_0_TDO__SHIFT 3 +#define FPGA_REG4__RADIO_0_TDO__WIDTH 1 +#define FPGA_REG4__RADIO_0_TDO__MASK 0x00000008U +#define FPGA_REG4__RADIO_0_TDO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define FPGA_REG4__RADIO_0_TDO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define FPGA_REG4__RADIO_0_TDO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field radio_1_tck */ +#define FPGA_REG4__RADIO_1_TCK__SHIFT 4 +#define FPGA_REG4__RADIO_1_TCK__WIDTH 1 +#define FPGA_REG4__RADIO_1_TCK__MASK 0x00000010U +#define FPGA_REG4__RADIO_1_TCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define FPGA_REG4__RADIO_1_TCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define FPGA_REG4__RADIO_1_TCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define FPGA_REG4__RADIO_1_TCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define FPGA_REG4__RADIO_1_TCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define FPGA_REG4__RADIO_1_TCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field radio_1_tdi */ +#define FPGA_REG4__RADIO_1_TDI__SHIFT 5 +#define FPGA_REG4__RADIO_1_TDI__WIDTH 1 +#define FPGA_REG4__RADIO_1_TDI__MASK 0x00000020U +#define FPGA_REG4__RADIO_1_TDI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define FPGA_REG4__RADIO_1_TDI__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define FPGA_REG4__RADIO_1_TDI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define FPGA_REG4__RADIO_1_TDI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define FPGA_REG4__RADIO_1_TDI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define FPGA_REG4__RADIO_1_TDI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field radio_1_tms */ +#define FPGA_REG4__RADIO_1_TMS__SHIFT 6 +#define FPGA_REG4__RADIO_1_TMS__WIDTH 1 +#define FPGA_REG4__RADIO_1_TMS__MASK 0x00000040U +#define FPGA_REG4__RADIO_1_TMS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define FPGA_REG4__RADIO_1_TMS__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define FPGA_REG4__RADIO_1_TMS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define FPGA_REG4__RADIO_1_TMS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define FPGA_REG4__RADIO_1_TMS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define FPGA_REG4__RADIO_1_TMS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field radio_1_tdo */ +#define FPGA_REG4__RADIO_1_TDO__SHIFT 7 +#define FPGA_REG4__RADIO_1_TDO__WIDTH 1 +#define FPGA_REG4__RADIO_1_TDO__MASK 0x00000080U +#define FPGA_REG4__RADIO_1_TDO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define FPGA_REG4__RADIO_1_TDO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define FPGA_REG4__RADIO_1_TDO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field radio_2_tck */ +#define FPGA_REG4__RADIO_2_TCK__SHIFT 8 +#define FPGA_REG4__RADIO_2_TCK__WIDTH 1 +#define FPGA_REG4__RADIO_2_TCK__MASK 0x00000100U +#define FPGA_REG4__RADIO_2_TCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define FPGA_REG4__RADIO_2_TCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define FPGA_REG4__RADIO_2_TCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define FPGA_REG4__RADIO_2_TCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define FPGA_REG4__RADIO_2_TCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define FPGA_REG4__RADIO_2_TCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field radio_2_tdi */ +#define FPGA_REG4__RADIO_2_TDI__SHIFT 9 +#define FPGA_REG4__RADIO_2_TDI__WIDTH 1 +#define FPGA_REG4__RADIO_2_TDI__MASK 0x00000200U +#define FPGA_REG4__RADIO_2_TDI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define FPGA_REG4__RADIO_2_TDI__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define FPGA_REG4__RADIO_2_TDI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define FPGA_REG4__RADIO_2_TDI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define FPGA_REG4__RADIO_2_TDI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define FPGA_REG4__RADIO_2_TDI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field radio_2_tms */ +#define FPGA_REG4__RADIO_2_TMS__SHIFT 10 +#define FPGA_REG4__RADIO_2_TMS__WIDTH 1 +#define FPGA_REG4__RADIO_2_TMS__MASK 0x00000400U +#define FPGA_REG4__RADIO_2_TMS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define FPGA_REG4__RADIO_2_TMS__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define FPGA_REG4__RADIO_2_TMS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define FPGA_REG4__RADIO_2_TMS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define FPGA_REG4__RADIO_2_TMS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define FPGA_REG4__RADIO_2_TMS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field radio_2_tdo */ +#define FPGA_REG4__RADIO_2_TDO__SHIFT 11 +#define FPGA_REG4__RADIO_2_TDO__WIDTH 1 +#define FPGA_REG4__RADIO_2_TDO__MASK 0x00000800U +#define FPGA_REG4__RADIO_2_TDO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define FPGA_REG4__RADIO_2_TDO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define FPGA_REG4__RADIO_2_TDO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field radio_3_tck */ +#define FPGA_REG4__RADIO_3_TCK__SHIFT 12 +#define FPGA_REG4__RADIO_3_TCK__WIDTH 1 +#define FPGA_REG4__RADIO_3_TCK__MASK 0x00001000U +#define FPGA_REG4__RADIO_3_TCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define FPGA_REG4__RADIO_3_TCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define FPGA_REG4__RADIO_3_TCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define FPGA_REG4__RADIO_3_TCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define FPGA_REG4__RADIO_3_TCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define FPGA_REG4__RADIO_3_TCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field radio_3_tdi */ +#define FPGA_REG4__RADIO_3_TDI__SHIFT 13 +#define FPGA_REG4__RADIO_3_TDI__WIDTH 1 +#define FPGA_REG4__RADIO_3_TDI__MASK 0x00002000U +#define FPGA_REG4__RADIO_3_TDI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define FPGA_REG4__RADIO_3_TDI__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define FPGA_REG4__RADIO_3_TDI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define FPGA_REG4__RADIO_3_TDI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define FPGA_REG4__RADIO_3_TDI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define FPGA_REG4__RADIO_3_TDI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field radio_3_tms */ +#define FPGA_REG4__RADIO_3_TMS__SHIFT 14 +#define FPGA_REG4__RADIO_3_TMS__WIDTH 1 +#define FPGA_REG4__RADIO_3_TMS__MASK 0x00004000U +#define FPGA_REG4__RADIO_3_TMS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define FPGA_REG4__RADIO_3_TMS__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define FPGA_REG4__RADIO_3_TMS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define FPGA_REG4__RADIO_3_TMS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define FPGA_REG4__RADIO_3_TMS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define FPGA_REG4__RADIO_3_TMS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field radio_3_tdo */ +#define FPGA_REG4__RADIO_3_TDO__SHIFT 15 +#define FPGA_REG4__RADIO_3_TDO__WIDTH 1 +#define FPGA_REG4__RADIO_3_TDO__MASK 0x00008000U +#define FPGA_REG4__RADIO_3_TDO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define FPGA_REG4__RADIO_3_TDO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define FPGA_REG4__RADIO_3_TDO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) +#define FPGA_REG4__TYPE u_int32_t +#define FPGA_REG4__READ 0x0000ffffU +#define FPGA_REG4__WRITE 0x0000ffffU + +#endif /* __FPGA_REG4_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_REG4 */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_REG4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_REG5 */ +#ifndef __FPGA_REG5_MACRO__ +#define __FPGA_REG5_MACRO__ + +/* macros for field drp_den */ +#define FPGA_REG5__DRP_DEN__SHIFT 0 +#define FPGA_REG5__DRP_DEN__WIDTH 1 +#define FPGA_REG5__DRP_DEN__MASK 0x00000001U +#define FPGA_REG5__DRP_DEN__READ(src) (u_int32_t)(src) & 0x00000001U +#define FPGA_REG5__DRP_DEN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define FPGA_REG5__DRP_DEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define FPGA_REG5__DRP_DEN__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define FPGA_REG5__DRP_DEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define FPGA_REG5__DRP_DEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field drp_dwe */ +#define FPGA_REG5__DRP_DWE__SHIFT 1 +#define FPGA_REG5__DRP_DWE__WIDTH 1 +#define FPGA_REG5__DRP_DWE__MASK 0x00000002U +#define FPGA_REG5__DRP_DWE__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define FPGA_REG5__DRP_DWE__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define FPGA_REG5__DRP_DWE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define FPGA_REG5__DRP_DWE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define FPGA_REG5__DRP_DWE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define FPGA_REG5__DRP_DWE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field drp_reset */ +#define FPGA_REG5__DRP_RESET__SHIFT 2 +#define FPGA_REG5__DRP_RESET__WIDTH 1 +#define FPGA_REG5__DRP_RESET__MASK 0x00000004U +#define FPGA_REG5__DRP_RESET__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define FPGA_REG5__DRP_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define FPGA_REG5__DRP_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define FPGA_REG5__DRP_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define FPGA_REG5__DRP_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define FPGA_REG5__DRP_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field drp_address */ +#define FPGA_REG5__DRP_ADDRESS__SHIFT 3 +#define FPGA_REG5__DRP_ADDRESS__WIDTH 5 +#define FPGA_REG5__DRP_ADDRESS__MASK 0x000000f8U +#define FPGA_REG5__DRP_ADDRESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f8U) >> 3) +#define FPGA_REG5__DRP_ADDRESS__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000000f8U) +#define FPGA_REG5__DRP_ADDRESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000000f8U) +#define FPGA_REG5__DRP_ADDRESS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000000f8U))) + +/* macros for field drp_reserved */ +#define FPGA_REG5__DRP_RESERVED__SHIFT 8 +#define FPGA_REG5__DRP_RESERVED__WIDTH 8 +#define FPGA_REG5__DRP_RESERVED__MASK 0x0000ff00U +#define FPGA_REG5__DRP_RESERVED__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define FPGA_REG5__DRP_RESERVED__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define FPGA_REG5__DRP_RESERVED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define FPGA_REG5__DRP_RESERVED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field drp_din */ +#define FPGA_REG5__DRP_DIN__SHIFT 16 +#define FPGA_REG5__DRP_DIN__WIDTH 16 +#define FPGA_REG5__DRP_DIN__MASK 0xffff0000U +#define FPGA_REG5__DRP_DIN__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16) +#define FPGA_REG5__DRP_DIN__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U) +#define FPGA_REG5__DRP_DIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define FPGA_REG5__DRP_DIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define FPGA_REG5__TYPE u_int32_t +#define FPGA_REG5__READ 0xffffffffU +#define FPGA_REG5__WRITE 0xffffffffU + +#endif /* __FPGA_REG5_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_REG5 */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_REG5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_REG6 */ +#ifndef __FPGA_REG6_MACRO__ +#define __FPGA_REG6_MACRO__ + +/* macros for field drp_drdy */ +#define FPGA_REG6__DRP_DRDY__SHIFT 0 +#define FPGA_REG6__DRP_DRDY__WIDTH 1 +#define FPGA_REG6__DRP_DRDY__MASK 0x00000001U +#define FPGA_REG6__DRP_DRDY__READ(src) (u_int32_t)(src) & 0x00000001U +#define FPGA_REG6__DRP_DRDY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define FPGA_REG6__DRP_DRDY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field drp_dout */ +#define FPGA_REG6__DRP_DOUT__SHIFT 16 +#define FPGA_REG6__DRP_DOUT__WIDTH 16 +#define FPGA_REG6__DRP_DOUT__MASK 0xffff0000U +#define FPGA_REG6__DRP_DOUT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16) +#define FPGA_REG6__TYPE u_int32_t +#define FPGA_REG6__READ 0xffff0001U + +#endif /* __FPGA_REG6_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_REG6 */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_REG6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_REG7 */ +#ifndef __FPGA_REG7_MACRO__ +#define __FPGA_REG7_MACRO__ + +/* macros for field RxPipeIFerrInjMsk */ +#define FPGA_REG7__RXPIPEIFERRINJMSK__SHIFT 0 +#define FPGA_REG7__RXPIPEIFERRINJMSK__WIDTH 32 +#define FPGA_REG7__RXPIPEIFERRINJMSK__MASK 0xffffffffU +#define FPGA_REG7__RXPIPEIFERRINJMSK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define FPGA_REG7__RXPIPEIFERRINJMSK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define FPGA_REG7__RXPIPEIFERRINJMSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define FPGA_REG7__RXPIPEIFERRINJMSK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define FPGA_REG7__TYPE u_int32_t +#define FPGA_REG7__READ 0xffffffffU +#define FPGA_REG7__WRITE 0xffffffffU + +#endif /* __FPGA_REG7_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_REG7 */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_REG7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_REG8 */ +#ifndef __FPGA_REG8_MACRO__ +#define __FPGA_REG8_MACRO__ + +/* macros for field TxPipeIFerrInjMsk */ +#define FPGA_REG8__TXPIPEIFERRINJMSK__SHIFT 0 +#define FPGA_REG8__TXPIPEIFERRINJMSK__WIDTH 32 +#define FPGA_REG8__TXPIPEIFERRINJMSK__MASK 0xffffffffU +#define FPGA_REG8__TXPIPEIFERRINJMSK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define FPGA_REG8__TXPIPEIFERRINJMSK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define FPGA_REG8__TXPIPEIFERRINJMSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define FPGA_REG8__TXPIPEIFERRINJMSK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define FPGA_REG8__TYPE u_int32_t +#define FPGA_REG8__READ 0xffffffffU +#define FPGA_REG8__WRITE 0xffffffffU + +#endif /* __FPGA_REG8_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_REG8 */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_REG8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_REG9 */ +#ifndef __FPGA_REG9_MACRO__ +#define __FPGA_REG9_MACRO__ + +/* macros for field RxPipeIFDataErrMsk */ +#define FPGA_REG9__RXPIPEIFDATAERRMSK__SHIFT 0 +#define FPGA_REG9__RXPIPEIFDATAERRMSK__WIDTH 16 +#define FPGA_REG9__RXPIPEIFDATAERRMSK__MASK 0x0000ffffU +#define FPGA_REG9__RXPIPEIFDATAERRMSK__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define FPGA_REG9__RXPIPEIFDATAERRMSK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define FPGA_REG9__RXPIPEIFDATAERRMSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define FPGA_REG9__RXPIPEIFDATAERRMSK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TxPipeIFDataErrMsk */ +#define FPGA_REG9__TXPIPEIFDATAERRMSK__SHIFT 16 +#define FPGA_REG9__TXPIPEIFDATAERRMSK__WIDTH 16 +#define FPGA_REG9__TXPIPEIFDATAERRMSK__MASK 0xffff0000U +#define FPGA_REG9__TXPIPEIFDATAERRMSK__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define FPGA_REG9__TXPIPEIFDATAERRMSK__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define FPGA_REG9__TXPIPEIFDATAERRMSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define FPGA_REG9__TXPIPEIFDATAERRMSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define FPGA_REG9__TYPE u_int32_t +#define FPGA_REG9__READ 0xffffffffU +#define FPGA_REG9__WRITE 0xffffffffU + +#endif /* __FPGA_REG9_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_REG9 */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_REG9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::FPGA_REG10 */ +#ifndef __FPGA_REG10_MACRO__ +#define __FPGA_REG10_MACRO__ + +/* macros for field RxPipeIFSpdMsk */ +#define FPGA_REG10__RXPIPEIFSPDMSK__SHIFT 0 +#define FPGA_REG10__RXPIPEIFSPDMSK__WIDTH 16 +#define FPGA_REG10__RXPIPEIFSPDMSK__MASK 0x0000ffffU +#define FPGA_REG10__RXPIPEIFSPDMSK__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define FPGA_REG10__RXPIPEIFSPDMSK__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define FPGA_REG10__RXPIPEIFSPDMSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define FPGA_REG10__RXPIPEIFSPDMSK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TxPipeIFSpdMsk */ +#define FPGA_REG10__TXPIPEIFSPDMSK__SHIFT 16 +#define FPGA_REG10__TXPIPEIFSPDMSK__WIDTH 16 +#define FPGA_REG10__TXPIPEIFSPDMSK__MASK 0xffff0000U +#define FPGA_REG10__TXPIPEIFSPDMSK__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define FPGA_REG10__TXPIPEIFSPDMSK__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define FPGA_REG10__TXPIPEIFSPDMSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define FPGA_REG10__TXPIPEIFSPDMSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define FPGA_REG10__TYPE u_int32_t +#define FPGA_REG10__READ 0xffffffffU +#define FPGA_REG10__WRITE 0xffffffffU + +#endif /* __FPGA_REG10_MACRO__ */ + + +/* macros for emulation_misc_reg_block.FPGA_REG10 */ +#define INST_EMULATION_MISC_REG_BLOCK__FPGA_REG10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::ID */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID_MACRO__ + +/* macros for field VendorID */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__VENDORID__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__VENDORID__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__VENDORID__MASK 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__VENDORID__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field DeviceID */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__DEVICEID__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__DEVICEID__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__DEVICEID__MASK 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__DEVICEID__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.ID */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__ID__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::STS_CMD_RGSTR */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR_MACRO__ + +/* macros for field CMD_RGSTR */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__CMD_RGSTR__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__CMD_RGSTR__WIDTH \ + 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__CMD_RGSTR__MASK \ + 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__CMD_RGSTR__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field STS_RGSTR */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__STS_RGSTR__SHIFT \ + 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__STS_RGSTR__WIDTH \ + 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__STS_RGSTR__MASK \ + 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__STS_RGSTR__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.STS_CMD_RGSTR */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__STS_CMD_RGSTR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::CLS_REV_ID */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID_MACRO__ + +/* macros for field RevID */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__REVID__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__REVID__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__REVID__MASK \ + 0x000000ffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__REVID__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field CLS_CD */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__CLS_CD__SHIFT 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__CLS_CD__WIDTH 24 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__CLS_CD__MASK \ + 0xffffff00U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__CLS_CD__READ(src) \ + (((u_int32_t)(src)\ + & 0xffffff00U) >> 8) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.CLS_REV_ID */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__CLS_REV_ID__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::BIST_HEAD_LAT_CACH */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH_MACRO__ + +/* macros for field CACH_LN_SZE */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__CACH_LN_SZE__SHIFT \ + 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__CACH_LN_SZE__WIDTH \ + 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__CACH_LN_SZE__MASK \ + 0x000000ffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__CACH_LN_SZE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field LAT_TIM */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__LAT_TIM__SHIFT \ + 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__LAT_TIM__WIDTH \ + 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__LAT_TIM__MASK \ + 0x0000ff00U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__LAT_TIM__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field HEAD_TYP */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__HEAD_TYP__SHIFT \ + 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__HEAD_TYP__WIDTH \ + 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__HEAD_TYP__MASK \ + 0x00ff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__HEAD_TYP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) + +/* macros for field BIST */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__BIST__SHIFT \ + 24 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__BIST__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__BIST__MASK \ + 0xff000000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__BIST__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__TYPE \ + u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__READ \ + 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.BIST_HEAD_LAT_CACH */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__BIST_HEAD_LAT_CACH__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::BAS_ADR_0 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_0_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_0_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_0__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_0__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_0__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_0__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_0__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_0__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_0_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.BAS_ADR_0 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__BAS_ADR_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::BAS_ADR_1 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_1_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_1_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_1__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_1__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_1__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_1__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_1__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_1__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_1_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.BAS_ADR_1 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__BAS_ADR_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::BAS_ADR_2 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_2_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_2_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_2__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_2__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_2__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_2__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_2__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_2__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_2_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.BAS_ADR_2 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__BAS_ADR_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::BAS_ADR_3 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_3_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_3_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_3__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_3__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_3__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_3__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_3__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_3__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_3_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.BAS_ADR_3 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__BAS_ADR_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::BAS_ADR_4 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_4_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_4_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_4__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_4__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_4__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_4__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_4__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_4__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_4_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.BAS_ADR_4 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__BAS_ADR_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::BAS_ADR_5 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_5_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_5_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_5__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_5__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_5__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_5__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_5__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_5__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_5_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.BAS_ADR_5 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__BAS_ADR_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::CRD_CIS_PTR */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CRD_CIS_PTR_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CRD_CIS_PTR_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CRD_CIS_PTR__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CRD_CIS_PTR__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CRD_CIS_PTR__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CRD_CIS_PTR__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CRD_CIS_PTR__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CRD_CIS_PTR__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CRD_CIS_PTR_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.CRD_CIS_PTR */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__CRD_CIS_PTR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::Sub_VenID */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID_MACRO__ + +/* macros for field Subsys_VenID */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__SUBSYS_VENID__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__SUBSYS_VENID__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__SUBSYS_VENID__MASK \ + 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__SUBSYS_VENID__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field SubsysID */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__SUBSYSID__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__SUBSYSID__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__SUBSYSID__MASK \ + 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__SUBSYSID__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.Sub_VenID */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__SUB_VENID__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::EXP_ROM_ADDR */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__EXP_ROM_ADDR_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__EXP_ROM_ADDR_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__EXP_ROM_ADDR__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__EXP_ROM_ADDR__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__EXP_ROM_ADDR__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__EXP_ROM_ADDR__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__EXP_ROM_ADDR__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__EXP_ROM_ADDR__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__EXP_ROM_ADDR_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.EXP_ROM_ADDR */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__EXP_ROM_ADDR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::CAPPTR */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR_MACRO__ + +/* macros for field Captr */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__CAPTR__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__CAPTR__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__CAPTR__MASK 0x000000ffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__CAPTR__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field RESERVE1 */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__RESERVE1__SHIFT 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__RESERVE1__WIDTH 24 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__RESERVE1__MASK \ + 0xffffff00U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__RESERVE1__READ(src) \ + (((u_int32_t)(src)\ + & 0xffffff00U) >> 8) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.CAPPTR */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__CAPPTR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::RESERVE2 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__RESERVE2_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__RESERVE2_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__RESERVE2__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__RESERVE2__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__RESERVE2__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__RESERVE2__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__RESERVE2__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__RESERVE2__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__RESERVE2_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.RESERVE2 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__RESERVE2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_0::LAT_INT */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT_MACRO__ + +/* macros for field INT_LIN */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__INT_LIN__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__INT_LIN__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__INT_LIN__MASK \ + 0x000000ffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__INT_LIN__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field INT_PIN */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__INT_PIN__SHIFT 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__INT_PIN__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__INT_PIN__MASK \ + 0x0000ff00U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__INT_PIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field MIN_GRNT */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__MIN_GRNT__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__MIN_GRNT__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__MIN_GRNT__MASK \ + 0x00ff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__MIN_GRNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) + +/* macros for field MX_LAT */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__MX_LAT__SHIFT 24 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__MX_LAT__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__MX_LAT__MASK 0xff000000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__MX_LAT__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.LAT_INT */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__LAT_INT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_1::CFG_PWR_CAP */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP_MACRO__ + +/* macros for field CAP_ID */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__CAP_ID__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__CAP_ID__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__CAP_ID__MASK \ + 0x000000ffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__CAP_ID__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field PM_NX_PTR */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__PM_NX_PTR__SHIFT 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__PM_NX_PTR__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__PM_NX_PTR__MASK \ + 0x0000ff00U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__PM_NX_PTR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field PMC */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__PMC__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__PMC__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__PMC__MASK \ + 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__PMC__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.CFG_PWR_CAP */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__CFG_PWR_CAP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_1::PWR_CSR */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR_MACRO__ + +/* macros for field PMCSR */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__PMCSR__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__PMCSR__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__PMCSR__MASK 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__PMCSR__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field PM_BSE */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__PM_BSE__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__PM_BSE__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__PM_BSE__MASK 0x00ff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__PM_BSE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) + +/* macros for field Data1 */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__DATA1__SHIFT 24 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__DATA1__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__DATA1__MASK 0xff000000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__DATA1__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.PWR_CSR */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__PWR_CSR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_2::MSG_CTR */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR_MACRO__ + +/* macros for field CAP_ID */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__CAP_ID__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__CAP_ID__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__CAP_ID__MASK 0x000000ffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__CAP_ID__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field MSI_NX_PTR */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__MSI_NX_PTR__SHIFT 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__MSI_NX_PTR__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__MSI_NX_PTR__MASK \ + 0x0000ff00U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__MSI_NX_PTR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field MSG_CTR_RGS */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__MSG_CTR_RGS__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__MSG_CTR_RGS__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__MSG_CTR_RGS__MASK \ + 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__MSG_CTR_RGS__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.MSG_CTR */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__MSG_CTR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_2::MSI_L32 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_L32_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_L32_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_L32__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_L32__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_L32__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_L32__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_L32__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_L32__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_L32_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.MSI_L32 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__MSI_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_2::MSI_U32 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_U32_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_U32_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_U32__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_U32__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_U32__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_U32__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_U32__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_U32__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_U32_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.MSI_U32 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__MSI_U32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_2::MSI_DATA */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_DATA_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_DATA_MACRO__ + +/* macros for field MSI_DATA_F */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_DATA__MSI_DATA_F__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_DATA__MSI_DATA_F__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_DATA__MSI_DATA_F__MASK \ + 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_DATA__MSI_DATA_F__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_DATA__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_DATA__READ 0x0000ffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_DATA_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.MSI_DATA */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__MSI_DATA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_3::PCIE_CAP */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP_MACRO__ + +/* macros for field CAP_ID */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__CAP_ID__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__CAP_ID__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__CAP_ID__MASK \ + 0x000000ffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__CAP_ID__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field PCIE_NX_PTR */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__PCIE_NX_PTR__SHIFT 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__PCIE_NX_PTR__WIDTH 8 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__PCIE_NX_PTR__MASK \ + 0x0000ff00U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__PCIE_NX_PTR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field PCIE_CAP_R */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__PCIE_CAP_R__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__PCIE_CAP_R__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__PCIE_CAP_R__MASK \ + 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__PCIE_CAP_R__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.PCIE_CAP */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__PCIE_CAP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_3::DEV_CAP */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_CAP_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_CAP_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_CAP__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_CAP__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_CAP__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_CAP__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_CAP__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_CAP__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_CAP_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.DEV_CAP */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__DEV_CAP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_3::DEV_STS_CTRL */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL_MACRO__ + +/* macros for field DEV_CTRL */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__DEV_CTRL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__DEV_CTRL__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__DEV_CTRL__MASK \ + 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__DEV_CTRL__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field DEV_STS */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__DEV_STS__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__DEV_STS__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__DEV_STS__MASK \ + 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__DEV_STS__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.DEV_STS_CTRL */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__DEV_STS_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_3::LNK_CAP */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_CAP_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_CAP_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_CAP__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_CAP__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_CAP__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_CAP__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_CAP__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_CAP__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_CAP_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.LNK_CAP */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__LNK_CAP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_3::LNK_STS_CTRL */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL_MACRO__ + +/* macros for field LNK_CTRL */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__LNK_CTRL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__LNK_CTRL__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__LNK_CTRL__MASK \ + 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__LNK_CTRL__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field LNK_STS */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__LNK_STS__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__LNK_STS__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__LNK_STS__MASK \ + 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__LNK_STS__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.LNK_STS_CTRL */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__LNK_STS_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_3::SLT_CAP */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_CAP_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_CAP_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_CAP__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_CAP__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_CAP__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_CAP__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_CAP__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_CAP__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_CAP_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.SLT_CAP */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__SLT_CAP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_3::SLT_STS_CTRL */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL_MACRO__ + +/* macros for field SLT_CTRL */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__SLT_CTRL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__SLT_CTRL__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__SLT_CTRL__MASK \ + 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__SLT_CTRL__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field SLT_STS */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__SLT_STS__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__SLT_STS__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__SLT_STS__MASK \ + 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__SLT_STS__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.SLT_STS_CTRL */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__SLT_STS_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_5::VPD_CAP */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_CAP_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_CAP_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_CAP__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_CAP__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_CAP__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_CAP__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_CAP__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_CAP__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_CAP_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VPD_CAP */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VPD_CAP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_5::VPD_DATA */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_DATA_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_DATA_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_DATA__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_DATA__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_DATA__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_DATA__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_DATA__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_DATA__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_DATA_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VPD_DATA */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VPD_DATA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_6::PCIE_EN_CAP_AER */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__PCIE_EN_CAP_AER_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__PCIE_EN_CAP_AER_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__PCIE_EN_CAP_AER__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__PCIE_EN_CAP_AER__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__PCIE_EN_CAP_AER__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__PCIE_EN_CAP_AER__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__PCIE_EN_CAP_AER__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__PCIE_EN_CAP_AER__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__PCIE_EN_CAP_AER_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.PCIE_EN_CAP_AER */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__PCIE_EN_CAP_AER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_6::UN_ERR_ST_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_ST_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_ST_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_ST_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_ST_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_ST_R__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_ST_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_ST_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_ST_R__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_ST_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.UN_ERR_ST_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__UN_ERR_ST_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_6::UN_ERR_MS_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_MS_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_MS_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_MS_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_MS_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_MS_R__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_MS_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_MS_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_MS_R__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_MS_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.UN_ERR_MS_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__UN_ERR_MS_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_6::UN_ERR_SV_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_SV_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_SV_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_SV_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_SV_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_SV_R__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_SV_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_SV_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_SV_R__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_SV_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.UN_ERR_SV_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__UN_ERR_SV_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_6::CO_ERR_ST_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_ST_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_ST_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_ST_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_ST_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_ST_R__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_ST_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_ST_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_ST_R__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_ST_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.CO_ERR_ST_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__CO_ERR_ST_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_6::CO_ERR_MS_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_MS_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_MS_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_MS_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_MS_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_MS_R__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_MS_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_MS_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_MS_R__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_MS_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.CO_ERR_MS_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__CO_ERR_MS_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_6::ADERR_CAP_CR */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__ADERR_CAP_CR_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__ADERR_CAP_CR_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__ADERR_CAP_CR__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__ADERR_CAP_CR__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__ADERR_CAP_CR__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__ADERR_CAP_CR__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__ADERR_CAP_CR__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__ADERR_CAP_CR__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__ADERR_CAP_CR_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.ADERR_CAP_CR */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__ADERR_CAP_CR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_6::HD_L_R0 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R0_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R0_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R0__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R0__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R0__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R0__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R0__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R0__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R0_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.HD_L_R0 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__HD_L_R0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_6::HD_L_R4 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R4_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R4_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R4__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R4__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R4__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R4__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R4__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R4__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R4_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.HD_L_R4 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__HD_L_R4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_6::HD_L_R8 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R8_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R8_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R8__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R8__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R8__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R8__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R8__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R8__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R8_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.HD_L_R8 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__HD_L_R8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_6::HD_L_R12 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R12_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R12_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R12__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R12__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R12__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R12__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R12__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R12__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R12_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.HD_L_R12 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__HD_L_R12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_7::PCIE_EN_CAP_VC */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PCIE_EN_CAP_VC_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PCIE_EN_CAP_VC_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PCIE_EN_CAP_VC__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PCIE_EN_CAP_VC__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PCIE_EN_CAP_VC__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PCIE_EN_CAP_VC__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PCIE_EN_CAP_VC__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PCIE_EN_CAP_VC__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PCIE_EN_CAP_VC_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.PCIE_EN_CAP_VC */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__PCIE_EN_CAP_VC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_7::PVC_CAP_R1 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_CAP_R1_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_CAP_R1_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_CAP_R1__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_CAP_R1__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_CAP_R1__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_CAP_R1__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_CAP_R1__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_CAP_R1__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_CAP_R1_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.PVC_CAP_R1 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__PVC_CAP_R1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_7::P_CAP_R2 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__P_CAP_R2_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__P_CAP_R2_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__P_CAP_R2__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__P_CAP_R2__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__P_CAP_R2__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__P_CAP_R2__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__P_CAP_R2__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__P_CAP_R2__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__P_CAP_R2_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.P_CAP_R2 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__P_CAP_R2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_7::PVC_STS_CTRL */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL_MACRO__ + +/* macros for field PVC_CTRL */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__PVC_CTRL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__PVC_CTRL__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__PVC_CTRL__MASK \ + 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__PVC_CTRL__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field PVC_STS */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__PVC_STS__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__PVC_STS__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__PVC_STS__MASK \ + 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__PVC_STS__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.PVC_STS_CTRL */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__PVC_STS_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_7::VC_CAP_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CAP_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CAP_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CAP_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CAP_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CAP_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CAP_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CAP_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CAP_R__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CAP_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC_CAP_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC_CAP_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_7::VC_CTL_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CTL_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CTL_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CTL_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CTL_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CTL_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CTL_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CTL_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CTL_R__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CTL_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC_CTL_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC_CTL_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_7::VC_STS_RSV */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV_MACRO__ + +/* macros for field RSVDP */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__RSVDP__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__RSVDP__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__RSVDP__MASK \ + 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__RSVDP__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field VC_STS */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__VC_STS__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__VC_STS__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__VC_STS__MASK \ + 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__VC_STS__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC_STS_RSV */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC_STS_RSV__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_7::VCR_CAP_R1 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CAP_R1_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CAP_R1_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CAP_R1__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CAP_R1__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CAP_R1__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CAP_R1__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CAP_R1__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CAP_R1__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CAP_R1_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VCR_CAP_R1 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VCR_CAP_R1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_7::VCR_CTRL_R1 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CTRL_R1_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CTRL_R1_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CTRL_R1__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CTRL_R1__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CTRL_R1__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CTRL_R1__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CTRL_R1__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CTRL_R1__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CTRL_R1_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VCR_CTRL_R1 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VCR_CTRL_R1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_7::VCR_STS_R1 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1_MACRO__ + +/* macros for field RSVDP1 */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__RSVDP1__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__RSVDP1__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__RSVDP1__MASK \ + 0x0000ffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__RSVDP1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field VC_STS1 */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__VC_STS1__SHIFT 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__VC_STS1__WIDTH 16 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__VC_STS1__MASK \ + 0xffff0000U +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__VC_STS1__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VCR_STS_R1 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VCR_STS_R1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_8::DEV_EN_CAP */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__DEV_EN_CAP_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__DEV_EN_CAP_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__DEV_EN_CAP__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__DEV_EN_CAP__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__DEV_EN_CAP__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__DEV_EN_CAP__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__DEV_EN_CAP__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__DEV_EN_CAP__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__DEV_EN_CAP_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.DEV_EN_CAP */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__DEV_EN_CAP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_8::SN_R1 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R1_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R1_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R1__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R1__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R1__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R1__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R1__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R1__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R1_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.SN_R1 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__SN_R1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_8::SN_R2 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R2_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R2_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R2__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R2__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R2__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R2__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R2__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R2__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R2_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.SN_R2 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__SN_R2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::LAT_REL_TIM */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.LAT_REL_TIM */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__LAT_REL_TIM__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::OT_MSG_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.OT_MSG_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__OT_MSG_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::PT_LNK_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.PT_LNK_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__PT_LNK_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::ACk_FREQ_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.ACk_FREQ_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__ACK_FREQ_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::PT_LNK_CTRL_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.PT_LNK_CTRL_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__PT_LNK_CTRL_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::LN_SKW_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.LN_SKW_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__LN_SKW_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::SYMB_N_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.SYMB_N_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__SYMB_N_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::SYMB_T_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.SYMB_T_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__SYMB_T_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::FL_MSK_R2 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.FL_MSK_R2 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__FL_MSK_R2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::DB_R0 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R0_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R0_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R0__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R0__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R0__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R0__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R0__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R0__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R0_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.DB_R0 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__DB_R0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::DB_R1 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R1_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R1_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R1__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R1__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R1__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R1__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R1__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R1__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R1_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.DB_R1 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__DB_R1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::TR_P_STS_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_P_STS_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_P_STS_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_P_STS_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_P_STS_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_P_STS_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_P_STS_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_P_STS_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_P_STS_R__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_P_STS_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.TR_P_STS_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__TR_P_STS_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::TR_NP_STS_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_NP_STS_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_NP_STS_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_NP_STS_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_NP_STS_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_NP_STS_R__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_NP_STS_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_NP_STS_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_NP_STS_R__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_NP_STS_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.TR_NP_STS_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__TR_NP_STS_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::TR_C_STS_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_C_STS_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_C_STS_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_C_STS_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_C_STS_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_C_STS_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_C_STS_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_C_STS_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_C_STS_R__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_C_STS_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.TR_C_STS_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__TR_C_STS_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::Q_STS_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__Q_STS_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__Q_STS_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__Q_STS_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__Q_STS_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__Q_STS_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__Q_STS_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__Q_STS_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__Q_STS_R__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__Q_STS_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.Q_STS_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__Q_STS_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC_TR_A_R1 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC_TR_A_R1 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC_TR_A_R1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC_TR_A_R2 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC_TR_A_R2 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC_TR_A_R2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC0_PR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC0_PR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC0_PR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC0_NPR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPR_Q_C__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC0_NPR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC0_NPR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC0_CR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC0_CR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC0_CR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC1_PR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC1_PR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC1_PR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC1_NPR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPR_Q_C__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC1_NPR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC1_NPR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC1_CR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC1_CR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC1_CR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC2_PR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC2_PR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC2_PR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC2_NPR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPR_Q_C__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC2_NPR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC2_NPR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC2_CR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC2_CR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC2_CR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC3_PR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC3_PR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC3_PR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC3_NPR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPR_Q_C__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC3_NPR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC3_NPR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC3_CR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC3_CR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC3_CR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC4_PR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC4_PR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC4_PR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC4_NPR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPR_Q_C__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC4_NPR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC4_NPR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC4_CR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC4_CR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC4_CR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC5_PR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC5_PR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC5_PR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC5_NPR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPR_Q_C__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC5_NPR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC5_NPR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC5_CR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC5_CR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC5_CR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC6_PR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC6_PR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC6_PR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC6_NPR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPR_Q_C__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC6_NPR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC6_NPR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC6_CR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC6_CR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC6_CR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC7_PR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC7_PR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC7_PR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC7_NPR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPR_Q_C__RDL__MASK \ + 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC7_NPR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC7_NPR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC7_CR_Q_C */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CR_Q_C_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CR_Q_C_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CR_Q_C__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CR_Q_C__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CR_Q_C__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CR_Q_C__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CR_Q_C__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CR_Q_C__READ 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CR_Q_C_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC7_CR_Q_C */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC7_CR_Q_C__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC0_PB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC0_PB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC0_PB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC0_NPB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC0_NPB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC0_NPB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC0_CB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC0_CB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC0_CB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC1_PB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC1_PB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC1_PB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC1_NPB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC1_NPB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC1_NPB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC1_CB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC1_CB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC1_CB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC2_PB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC2_PB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC2_PB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC2_NPB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC2_NPB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC2_NPB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC2_CB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC2_CB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC2_CB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC3_PB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC3_PB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC3_PB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC3_NPB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC3_NPB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC3_NPB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC3_CB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC3_CB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC3_CB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC4_PB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC4_PB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC4_PB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC4_NPB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC4_NPB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC4_NPB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC4_CB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC4_CB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC4_CB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC5_PB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC5_PB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC5_PB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC5_NPB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC5_NPB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC5_NPB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC5_CB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC5_CB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC5_CB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC6_PB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC6_PB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC6_PB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC6_NPB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC6_NPB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC6_NPB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC6_CB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC6_CB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC6_CB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC7_PB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC7_PB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC7_PB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC7_NPB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC7_NPB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC7_NPB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::VC7_CB_D */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.VC7_CB_D */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__VC7_CB_D__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::GEN2 */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.GEN2 */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__GEN2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::PHY_STS_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.PHY_STS_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__PHY_STS_R__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DWC_pcie_dbi_axi::DWC_pcie_dbi_axi_9::PHY_CTRL_R */ +#ifndef __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R_MACRO__ +#define __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R_MACRO__ + +/* macros for field rdl */ +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__SHIFT 0 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__WIDTH 32 +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__MASK 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__TYPE u_int32_t +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__READ 0xffffffffU +#define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__WRITE 0xffffffffU + +#endif /* __DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R_MACRO__ */ + + +/* macros for DWC_pcie_dbi_axi_block.PHY_CTRL_R */ +#define INST_DWC_PCIE_DBI_AXI_BLOCK__PHY_CTRL_R__NUM 1 +#define RFILE_INST_DWC_PCIE_DBI_AXI_BLOCK__DWC_PCIE_DBI_AXI_0__NUM 1 +#define RFILE_INST_DWC_PCIE_DBI_AXI_BLOCK__DWC_PCIE_DBI_AXI_1__NUM 1 +#define RFILE_INST_DWC_PCIE_DBI_AXI_BLOCK__DWC_PCIE_DBI_AXI_2__NUM 1 +#define RFILE_INST_DWC_PCIE_DBI_AXI_BLOCK__DWC_PCIE_DBI_AXI_3__NUM 1 +#define RFILE_INST_DWC_PCIE_DBI_AXI_BLOCK__DWC_PCIE_DBI_AXI_5__NUM 1 +#define RFILE_INST_DWC_PCIE_DBI_AXI_BLOCK__DWC_PCIE_DBI_AXI_6__NUM 1 +#define RFILE_INST_DWC_PCIE_DBI_AXI_BLOCK__DWC_PCIE_DBI_AXI_7__NUM 1 +#define RFILE_INST_DWC_PCIE_DBI_AXI_BLOCK__DWC_PCIE_DBI_AXI_8__NUM 1 +#define RFILE_INST_DWC_PCIE_DBI_AXI_BLOCK__DWC_PCIE_DBI_AXI_9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RESET_CONTROL */ +#ifndef __RESET_CONTROL_MACRO__ +#define __RESET_CONTROL_MACRO__ + +/* macros for field MAC_WARM_RST */ +#define RESET_CONTROL__MAC_WARM_RST__SHIFT 0 +#define RESET_CONTROL__MAC_WARM_RST__WIDTH 1 +#define RESET_CONTROL__MAC_WARM_RST__MASK 0x00000001U +#define RESET_CONTROL__MAC_WARM_RST__READ(src) (u_int32_t)(src) & 0x00000001U +#define RESET_CONTROL__MAC_WARM_RST__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RESET_CONTROL__MAC_WARM_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RESET_CONTROL__MAC_WARM_RST__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RESET_CONTROL__MAC_WARM_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RESET_CONTROL__MAC_WARM_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field MAC_COLD_RST */ +#define RESET_CONTROL__MAC_COLD_RST__SHIFT 1 +#define RESET_CONTROL__MAC_COLD_RST__WIDTH 1 +#define RESET_CONTROL__MAC_COLD_RST__MASK 0x00000002U +#define RESET_CONTROL__MAC_COLD_RST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RESET_CONTROL__MAC_COLD_RST__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RESET_CONTROL__MAC_COLD_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RESET_CONTROL__MAC_COLD_RST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RESET_CONTROL__MAC_COLD_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RESET_CONTROL__MAC_COLD_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field WARM_RST */ +#define RESET_CONTROL__WARM_RST__SHIFT 2 +#define RESET_CONTROL__WARM_RST__WIDTH 1 +#define RESET_CONTROL__WARM_RST__MASK 0x00000004U +#define RESET_CONTROL__WARM_RST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RESET_CONTROL__WARM_RST__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RESET_CONTROL__WARM_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RESET_CONTROL__WARM_RST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RESET_CONTROL__WARM_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RESET_CONTROL__WARM_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field COLD_RST */ +#define RESET_CONTROL__COLD_RST__SHIFT 3 +#define RESET_CONTROL__COLD_RST__WIDTH 1 +#define RESET_CONTROL__COLD_RST__MASK 0x00000008U +#define RESET_CONTROL__COLD_RST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RESET_CONTROL__COLD_RST__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RESET_CONTROL__COLD_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RESET_CONTROL__COLD_RST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RESET_CONTROL__COLD_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RESET_CONTROL__COLD_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define RESET_CONTROL__TYPE u_int32_t +#define RESET_CONTROL__READ 0x0000000fU +#define RESET_CONTROL__WRITE 0x0000000fU + +#endif /* __RESET_CONTROL_MACRO__ */ + + +/* macros for rtc_reg_block.RESET_CONTROL */ +#define INST_RTC_REG_BLOCK__RESET_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::XTAL_CONTROL */ +#ifndef __XTAL_CONTROL_MACRO__ +#define __XTAL_CONTROL_MACRO__ + +/* macros for field TCXO */ +#define XTAL_CONTROL__TCXO__SHIFT 0 +#define XTAL_CONTROL__TCXO__WIDTH 1 +#define XTAL_CONTROL__TCXO__MASK 0x00000001U +#define XTAL_CONTROL__TCXO__READ(src) (u_int32_t)(src) & 0x00000001U +#define XTAL_CONTROL__TCXO__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define XTAL_CONTROL__TCXO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define XTAL_CONTROL__TCXO__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define XTAL_CONTROL__TCXO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define XTAL_CONTROL__TCXO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define XTAL_CONTROL__TYPE u_int32_t +#define XTAL_CONTROL__READ 0x00000001U +#define XTAL_CONTROL__WRITE 0x00000001U + +#endif /* __XTAL_CONTROL_MACRO__ */ + + +/* macros for rtc_reg_block.XTAL_CONTROL */ +#define INST_RTC_REG_BLOCK__XTAL_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::REG_CONTROL0 */ +#ifndef __REG_CONTROL0_MACRO__ +#define __REG_CONTROL0_MACRO__ + +/* macros for field SWREG_BITS */ +#define REG_CONTROL0__SWREG_BITS__SHIFT 0 +#define REG_CONTROL0__SWREG_BITS__WIDTH 32 +#define REG_CONTROL0__SWREG_BITS__MASK 0xffffffffU +#define REG_CONTROL0__SWREG_BITS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define REG_CONTROL0__SWREG_BITS__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define REG_CONTROL0__SWREG_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define REG_CONTROL0__SWREG_BITS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define REG_CONTROL0__TYPE u_int32_t +#define REG_CONTROL0__READ 0xffffffffU +#define REG_CONTROL0__WRITE 0xffffffffU + +#endif /* __REG_CONTROL0_MACRO__ */ + + +/* macros for rtc_reg_block.REG_CONTROL0 */ +#define INST_RTC_REG_BLOCK__REG_CONTROL0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::REG_CONTROL1 */ +#ifndef __REG_CONTROL1_MACRO__ +#define __REG_CONTROL1_MACRO__ + +/* macros for field SWREG_PROGRAM */ +#define REG_CONTROL1__SWREG_PROGRAM__SHIFT 0 +#define REG_CONTROL1__SWREG_PROGRAM__WIDTH 1 +#define REG_CONTROL1__SWREG_PROGRAM__MASK 0x00000001U +#define REG_CONTROL1__SWREG_PROGRAM__READ(src) (u_int32_t)(src) & 0x00000001U +#define REG_CONTROL1__SWREG_PROGRAM__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define REG_CONTROL1__SWREG_PROGRAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define REG_CONTROL1__SWREG_PROGRAM__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define REG_CONTROL1__SWREG_PROGRAM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define REG_CONTROL1__SWREG_PROGRAM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field OTPREG_LVL */ +#define REG_CONTROL1__OTPREG_LVL__SHIFT 1 +#define REG_CONTROL1__OTPREG_LVL__WIDTH 2 +#define REG_CONTROL1__OTPREG_LVL__MASK 0x00000006U +#define REG_CONTROL1__OTPREG_LVL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000006U) >> 1) +#define REG_CONTROL1__OTPREG_LVL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000006U) +#define REG_CONTROL1__OTPREG_LVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((u_int32_t)(src) <<\ + 1) & 0x00000006U) +#define REG_CONTROL1__OTPREG_LVL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000006U))) +#define REG_CONTROL1__TYPE u_int32_t +#define REG_CONTROL1__READ 0x00000007U +#define REG_CONTROL1__WRITE 0x00000007U + +#endif /* __REG_CONTROL1_MACRO__ */ + + +/* macros for rtc_reg_block.REG_CONTROL1 */ +#define INST_RTC_REG_BLOCK__REG_CONTROL1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::QUADRATURE */ +#ifndef __QUADRATURE_MACRO__ +#define __QUADRATURE_MACRO__ + +/* macros for field DAC */ +#define QUADRATURE__DAC__SHIFT 0 +#define QUADRATURE__DAC__WIDTH 3 +#define QUADRATURE__DAC__MASK 0x00000007U +#define QUADRATURE__DAC__READ(src) (u_int32_t)(src) & 0x00000007U +#define QUADRATURE__DAC__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define QUADRATURE__DAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define QUADRATURE__DAC__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) + +/* macros for field ADC */ +#define QUADRATURE__ADC__SHIFT 4 +#define QUADRATURE__ADC__WIDTH 4 +#define QUADRATURE__ADC__MASK 0x000000f0U +#define QUADRATURE__ADC__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) +#define QUADRATURE__ADC__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) +#define QUADRATURE__ADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define QUADRATURE__ADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) +#define QUADRATURE__TYPE u_int32_t +#define QUADRATURE__READ 0x000000f7U +#define QUADRATURE__WRITE 0x000000f7U + +#endif /* __QUADRATURE_MACRO__ */ + + +/* macros for rtc_reg_block.QUADRATURE */ +#define INST_RTC_REG_BLOCK__QUADRATURE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PLL_CONTROL */ +#ifndef __PLL_CONTROL_MACRO__ +#define __PLL_CONTROL_MACRO__ + +/* macros for field DIV */ +#define PLL_CONTROL__DIV__SHIFT 0 +#define PLL_CONTROL__DIV__WIDTH 10 +#define PLL_CONTROL__DIV__MASK 0x000003ffU +#define PLL_CONTROL__DIV__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PLL_CONTROL__DIV__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PLL_CONTROL__DIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PLL_CONTROL__DIV__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU))) + +/* macros for field REFDIV */ +#define PLL_CONTROL__REFDIV__SHIFT 10 +#define PLL_CONTROL__REFDIV__WIDTH 4 +#define PLL_CONTROL__REFDIV__MASK 0x00003c00U +#define PLL_CONTROL__REFDIV__READ(src) (((u_int32_t)(src) & 0x00003c00U) >> 10) +#define PLL_CONTROL__REFDIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00003c00U) +#define PLL_CONTROL__REFDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00003c00U) +#define PLL_CONTROL__REFDIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00003c00U))) + +/* macros for field CLK_SEL */ +#define PLL_CONTROL__CLK_SEL__SHIFT 14 +#define PLL_CONTROL__CLK_SEL__WIDTH 2 +#define PLL_CONTROL__CLK_SEL__MASK 0x0000c000U +#define PLL_CONTROL__CLK_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define PLL_CONTROL__CLK_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define PLL_CONTROL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define PLL_CONTROL__CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field BYPASS */ +#define PLL_CONTROL__BYPASS__SHIFT 16 +#define PLL_CONTROL__BYPASS__WIDTH 1 +#define PLL_CONTROL__BYPASS__MASK 0x00010000U +#define PLL_CONTROL__BYPASS__READ(src) (((u_int32_t)(src) & 0x00010000U) >> 16) +#define PLL_CONTROL__BYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define PLL_CONTROL__BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define PLL_CONTROL__BYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define PLL_CONTROL__BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define PLL_CONTROL__BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field UPDATING */ +#define PLL_CONTROL__UPDATING__SHIFT 17 +#define PLL_CONTROL__UPDATING__WIDTH 1 +#define PLL_CONTROL__UPDATING__MASK 0x00020000U +#define PLL_CONTROL__UPDATING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define PLL_CONTROL__UPDATING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define PLL_CONTROL__UPDATING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field NOPWD */ +#define PLL_CONTROL__NOPWD__SHIFT 18 +#define PLL_CONTROL__NOPWD__WIDTH 1 +#define PLL_CONTROL__NOPWD__MASK 0x00040000U +#define PLL_CONTROL__NOPWD__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define PLL_CONTROL__NOPWD__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define PLL_CONTROL__NOPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define PLL_CONTROL__NOPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define PLL_CONTROL__NOPWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define PLL_CONTROL__NOPWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field MAC_OVERRIDE */ +#define PLL_CONTROL__MAC_OVERRIDE__SHIFT 19 +#define PLL_CONTROL__MAC_OVERRIDE__WIDTH 1 +#define PLL_CONTROL__MAC_OVERRIDE__MASK 0x00080000U +#define PLL_CONTROL__MAC_OVERRIDE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define PLL_CONTROL__MAC_OVERRIDE__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define PLL_CONTROL__MAC_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define PLL_CONTROL__MAC_OVERRIDE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define PLL_CONTROL__MAC_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define PLL_CONTROL__MAC_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) +#define PLL_CONTROL__TYPE u_int32_t +#define PLL_CONTROL__READ 0x000fffffU +#define PLL_CONTROL__WRITE 0x000fffffU + +#endif /* __PLL_CONTROL_MACRO__ */ + + +/* macros for rtc_reg_block.PLL_CONTROL */ +#define INST_RTC_REG_BLOCK__PLL_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PLL_SETTLE */ +#ifndef __PLL_SETTLE_MACRO__ +#define __PLL_SETTLE_MACRO__ + +/* macros for field TIME */ +#define PLL_SETTLE__TIME__SHIFT 0 +#define PLL_SETTLE__TIME__WIDTH 11 +#define PLL_SETTLE__TIME__MASK 0x000007ffU +#define PLL_SETTLE__TIME__READ(src) (u_int32_t)(src) & 0x000007ffU +#define PLL_SETTLE__TIME__WRITE(src) ((u_int32_t)(src) & 0x000007ffU) +#define PLL_SETTLE__TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define PLL_SETTLE__TIME__VERIFY(src) (!(((u_int32_t)(src) & ~0x000007ffU))) +#define PLL_SETTLE__TYPE u_int32_t +#define PLL_SETTLE__READ 0x000007ffU +#define PLL_SETTLE__WRITE 0x000007ffU + +#endif /* __PLL_SETTLE_MACRO__ */ + + +/* macros for rtc_reg_block.PLL_SETTLE */ +#define INST_RTC_REG_BLOCK__PLL_SETTLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::XTAL_SETTLE */ +#ifndef __XTAL_SETTLE_MACRO__ +#define __XTAL_SETTLE_MACRO__ + +/* macros for field TIME */ +#define XTAL_SETTLE__TIME__SHIFT 0 +#define XTAL_SETTLE__TIME__WIDTH 7 +#define XTAL_SETTLE__TIME__MASK 0x0000007fU +#define XTAL_SETTLE__TIME__READ(src) (u_int32_t)(src) & 0x0000007fU +#define XTAL_SETTLE__TIME__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) +#define XTAL_SETTLE__TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define XTAL_SETTLE__TIME__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU))) +#define XTAL_SETTLE__TYPE u_int32_t +#define XTAL_SETTLE__READ 0x0000007fU +#define XTAL_SETTLE__WRITE 0x0000007fU + +#endif /* __XTAL_SETTLE_MACRO__ */ + + +/* macros for rtc_reg_block.XTAL_SETTLE */ +#define INST_RTC_REG_BLOCK__XTAL_SETTLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::CLOCK_OUT */ +#ifndef __CLOCK_OUT_MACRO__ +#define __CLOCK_OUT_MACRO__ + +/* macros for field SELECT */ +#define CLOCK_OUT__SELECT__SHIFT 0 +#define CLOCK_OUT__SELECT__WIDTH 4 +#define CLOCK_OUT__SELECT__MASK 0x0000000fU +#define CLOCK_OUT__SELECT__READ(src) (u_int32_t)(src) & 0x0000000fU +#define CLOCK_OUT__SELECT__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define CLOCK_OUT__SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CLOCK_OUT__SELECT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) + +/* macros for field DELAY */ +#define CLOCK_OUT__DELAY__SHIFT 4 +#define CLOCK_OUT__DELAY__WIDTH 3 +#define CLOCK_OUT__DELAY__MASK 0x00000070U +#define CLOCK_OUT__DELAY__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4) +#define CLOCK_OUT__DELAY__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000070U) +#define CLOCK_OUT__DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define CLOCK_OUT__DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) +#define CLOCK_OUT__TYPE u_int32_t +#define CLOCK_OUT__READ 0x0000007fU +#define CLOCK_OUT__WRITE 0x0000007fU + +#endif /* __CLOCK_OUT_MACRO__ */ + + +/* macros for rtc_reg_block.CLOCK_OUT */ +#define INST_RTC_REG_BLOCK__CLOCK_OUT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BIAS_OVERRIDE */ +#ifndef __BIAS_OVERRIDE_MACRO__ +#define __BIAS_OVERRIDE_MACRO__ + +/* macros for field ON */ +#define BIAS_OVERRIDE__ON__SHIFT 0 +#define BIAS_OVERRIDE__ON__WIDTH 1 +#define BIAS_OVERRIDE__ON__MASK 0x00000001U +#define BIAS_OVERRIDE__ON__READ(src) (u_int32_t)(src) & 0x00000001U +#define BIAS_OVERRIDE__ON__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define BIAS_OVERRIDE__ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BIAS_OVERRIDE__ON__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define BIAS_OVERRIDE__ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BIAS_OVERRIDE__ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define BIAS_OVERRIDE__TYPE u_int32_t +#define BIAS_OVERRIDE__READ 0x00000001U +#define BIAS_OVERRIDE__WRITE 0x00000001U + +#endif /* __BIAS_OVERRIDE_MACRO__ */ + + +/* macros for rtc_reg_block.BIAS_OVERRIDE */ +#define INST_RTC_REG_BLOCK__BIAS_OVERRIDE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RESET_CAUSE */ +#ifndef __RESET_CAUSE_MACRO__ +#define __RESET_CAUSE_MACRO__ + +/* macros for field LAST */ +#define RESET_CAUSE__LAST__SHIFT 0 +#define RESET_CAUSE__LAST__WIDTH 2 +#define RESET_CAUSE__LAST__MASK 0x00000003U +#define RESET_CAUSE__LAST__READ(src) (u_int32_t)(src) & 0x00000003U +#define RESET_CAUSE__TYPE u_int32_t +#define RESET_CAUSE__READ 0x00000003U + +#endif /* __RESET_CAUSE_MACRO__ */ + + +/* macros for rtc_reg_block.RESET_CAUSE */ +#define INST_RTC_REG_BLOCK__RESET_CAUSE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYSTEM_SLEEP */ +#ifndef __SYSTEM_SLEEP_MACRO__ +#define __SYSTEM_SLEEP_MACRO__ + +/* macros for field DISABLE */ +#define SYSTEM_SLEEP__DISABLE__SHIFT 0 +#define SYSTEM_SLEEP__DISABLE__WIDTH 1 +#define SYSTEM_SLEEP__DISABLE__MASK 0x00000001U +#define SYSTEM_SLEEP__DISABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYSTEM_SLEEP__DISABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define SYSTEM_SLEEP__DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYSTEM_SLEEP__DISABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SYSTEM_SLEEP__DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYSTEM_SLEEP__DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LIGHT */ +#define SYSTEM_SLEEP__LIGHT__SHIFT 1 +#define SYSTEM_SLEEP__LIGHT__WIDTH 1 +#define SYSTEM_SLEEP__LIGHT__MASK 0x00000002U +#define SYSTEM_SLEEP__LIGHT__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define SYSTEM_SLEEP__LIGHT__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define SYSTEM_SLEEP__LIGHT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define SYSTEM_SLEEP__LIGHT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define SYSTEM_SLEEP__LIGHT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define SYSTEM_SLEEP__LIGHT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field MAC_IF */ +#define SYSTEM_SLEEP__MAC_IF__SHIFT 2 +#define SYSTEM_SLEEP__MAC_IF__WIDTH 1 +#define SYSTEM_SLEEP__MAC_IF__MASK 0x00000004U +#define SYSTEM_SLEEP__MAC_IF__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define SYSTEM_SLEEP__MAC_IF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define SYSTEM_SLEEP__MAC_IF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define SYSTEM_SLEEP__TYPE u_int32_t +#define SYSTEM_SLEEP__READ 0x00000007U +#define SYSTEM_SLEEP__WRITE 0x00000007U + +#endif /* __SYSTEM_SLEEP_MACRO__ */ + + +/* macros for rtc_reg_block.SYSTEM_SLEEP */ +#define INST_RTC_REG_BLOCK__SYSTEM_SLEEP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_SLEEP_CONTROL */ +#ifndef __MAC_SLEEP_CONTROL_MACRO__ +#define __MAC_SLEEP_CONTROL_MACRO__ + +/* macros for field ENABLE */ +#define MAC_SLEEP_CONTROL__ENABLE__SHIFT 0 +#define MAC_SLEEP_CONTROL__ENABLE__WIDTH 2 +#define MAC_SLEEP_CONTROL__ENABLE__MASK 0x00000003U +#define MAC_SLEEP_CONTROL__ENABLE__READ(src) (u_int32_t)(src) & 0x00000003U +#define MAC_SLEEP_CONTROL__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define MAC_SLEEP_CONTROL__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define MAC_SLEEP_CONTROL__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) +#define MAC_SLEEP_CONTROL__TYPE u_int32_t +#define MAC_SLEEP_CONTROL__READ 0x00000003U +#define MAC_SLEEP_CONTROL__WRITE 0x00000003U + +#endif /* __MAC_SLEEP_CONTROL_MACRO__ */ + + +/* macros for rtc_reg_block.MAC_SLEEP_CONTROL */ +#define INST_RTC_REG_BLOCK__MAC_SLEEP_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::KEEP_AWAKE */ +#ifndef __KEEP_AWAKE_MACRO__ +#define __KEEP_AWAKE_MACRO__ + +/* macros for field COUNT */ +#define KEEP_AWAKE__COUNT__SHIFT 0 +#define KEEP_AWAKE__COUNT__WIDTH 8 +#define KEEP_AWAKE__COUNT__MASK 0x000000ffU +#define KEEP_AWAKE__COUNT__READ(src) (u_int32_t)(src) & 0x000000ffU +#define KEEP_AWAKE__COUNT__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define KEEP_AWAKE__COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define KEEP_AWAKE__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) +#define KEEP_AWAKE__TYPE u_int32_t +#define KEEP_AWAKE__READ 0x000000ffU +#define KEEP_AWAKE__WRITE 0x000000ffU + +#endif /* __KEEP_AWAKE_MACRO__ */ + + +/* macros for rtc_reg_block.KEEP_AWAKE */ +#define INST_RTC_REG_BLOCK__KEEP_AWAKE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DERIVED_RTC_CLK */ +#ifndef __DERIVED_RTC_CLK_MACRO__ +#define __DERIVED_RTC_CLK_MACRO__ + +/* macros for field PERIOD */ +#define DERIVED_RTC_CLK__PERIOD__SHIFT 1 +#define DERIVED_RTC_CLK__PERIOD__WIDTH 15 +#define DERIVED_RTC_CLK__PERIOD__MASK 0x0000fffeU +#define DERIVED_RTC_CLK__PERIOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fffeU) >> 1) +#define DERIVED_RTC_CLK__PERIOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000fffeU) +#define DERIVED_RTC_CLK__PERIOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fffeU) | (((u_int32_t)(src) <<\ + 1) & 0x0000fffeU) +#define DERIVED_RTC_CLK__PERIOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000fffeU))) + +/* macros for field EXTERNAL_DETECT */ +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__SHIFT 18 +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__WIDTH 1 +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__MASK 0x00040000U +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) +#define DERIVED_RTC_CLK__TYPE u_int32_t +#define DERIVED_RTC_CLK__READ 0x0004fffeU +#define DERIVED_RTC_CLK__WRITE 0x0004fffeU + +#endif /* __DERIVED_RTC_CLK_MACRO__ */ + + +/* macros for rtc_reg_block.DERIVED_RTC_CLK */ +#define INST_RTC_REG_BLOCK__DERIVED_RTC_CLK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_RESET */ +#ifndef __RTC_SYNC_RESET_MACRO__ +#define __RTC_SYNC_RESET_MACRO__ + +/* macros for field RESET_L */ +#define RTC_SYNC_RESET__RESET_L__SHIFT 0 +#define RTC_SYNC_RESET__RESET_L__WIDTH 1 +#define RTC_SYNC_RESET__RESET_L__MASK 0x00000001U +#define RTC_SYNC_RESET__RESET_L__READ(src) (u_int32_t)(src) & 0x00000001U +#define RTC_SYNC_RESET__RESET_L__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RTC_SYNC_RESET__RESET_L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTC_SYNC_RESET__RESET_L__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTC_SYNC_RESET__RESET_L__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_RESET__RESET_L__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define RTC_SYNC_RESET__TYPE u_int32_t +#define RTC_SYNC_RESET__READ 0x00000001U +#define RTC_SYNC_RESET__WRITE 0x00000001U + +#endif /* __RTC_SYNC_RESET_MACRO__ */ + + +/* macros for rtc_sync_reg_block.RTC_SYNC_RESET */ +#define INST_RTC_SYNC_REG_BLOCK__RTC_SYNC_RESET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_STATUS */ +#ifndef __RTC_SYNC_STATUS_MACRO__ +#define __RTC_SYNC_STATUS_MACRO__ + +/* macros for field SHUTDOWN_STATE */ +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__SHIFT 0 +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__WIDTH 1 +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__MASK 0x00000001U +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ON_STATE */ +#define RTC_SYNC_STATUS__ON_STATE__SHIFT 1 +#define RTC_SYNC_STATUS__ON_STATE__WIDTH 1 +#define RTC_SYNC_STATUS__ON_STATE__MASK 0x00000002U +#define RTC_SYNC_STATUS__ON_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_STATUS__ON_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_STATUS__ON_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SLEEP_STATE */ +#define RTC_SYNC_STATUS__SLEEP_STATE__SHIFT 2 +#define RTC_SYNC_STATUS__SLEEP_STATE__WIDTH 1 +#define RTC_SYNC_STATUS__SLEEP_STATE__MASK 0x00000004U +#define RTC_SYNC_STATUS__SLEEP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RTC_SYNC_STATUS__SLEEP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RTC_SYNC_STATUS__SLEEP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field WAKEUP_STATE */ +#define RTC_SYNC_STATUS__WAKEUP_STATE__SHIFT 3 +#define RTC_SYNC_STATUS__WAKEUP_STATE__WIDTH 1 +#define RTC_SYNC_STATUS__WAKEUP_STATE__MASK 0x00000008U +#define RTC_SYNC_STATUS__WAKEUP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RTC_SYNC_STATUS__WAKEUP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RTC_SYNC_STATUS__WAKEUP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field WRESET */ +#define RTC_SYNC_STATUS__WRESET__SHIFT 4 +#define RTC_SYNC_STATUS__WRESET__WIDTH 1 +#define RTC_SYNC_STATUS__WRESET__MASK 0x00000010U +#define RTC_SYNC_STATUS__WRESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RTC_SYNC_STATUS__WRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RTC_SYNC_STATUS__WRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PLL_CHANGING */ +#define RTC_SYNC_STATUS__PLL_CHANGING__SHIFT 5 +#define RTC_SYNC_STATUS__PLL_CHANGING__WIDTH 1 +#define RTC_SYNC_STATUS__PLL_CHANGING__MASK 0x00000020U +#define RTC_SYNC_STATUS__PLL_CHANGING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RTC_SYNC_STATUS__PLL_CHANGING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RTC_SYNC_STATUS__PLL_CHANGING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define RTC_SYNC_STATUS__TYPE u_int32_t +#define RTC_SYNC_STATUS__READ 0x0000003fU + +#endif /* __RTC_SYNC_STATUS_MACRO__ */ + + +/* macros for rtc_sync_reg_block.RTC_SYNC_STATUS */ +#define INST_RTC_SYNC_REG_BLOCK__RTC_SYNC_STATUS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_DERIVED */ +#ifndef __RTC_SYNC_DERIVED_MACRO__ +#define __RTC_SYNC_DERIVED_MACRO__ + +/* macros for field BYPASS */ +#define RTC_SYNC_DERIVED__BYPASS__SHIFT 0 +#define RTC_SYNC_DERIVED__BYPASS__WIDTH 1 +#define RTC_SYNC_DERIVED__BYPASS__MASK 0x00000001U +#define RTC_SYNC_DERIVED__BYPASS__READ(src) (u_int32_t)(src) & 0x00000001U +#define RTC_SYNC_DERIVED__BYPASS__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RTC_SYNC_DERIVED__BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTC_SYNC_DERIVED__BYPASS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTC_SYNC_DERIVED__BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_DERIVED__BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field FORCE */ +#define RTC_SYNC_DERIVED__FORCE__SHIFT 1 +#define RTC_SYNC_DERIVED__FORCE__WIDTH 1 +#define RTC_SYNC_DERIVED__FORCE__MASK 0x00000002U +#define RTC_SYNC_DERIVED__FORCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_DERIVED__FORCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTC_SYNC_DERIVED__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTC_SYNC_DERIVED__FORCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTC_SYNC_DERIVED__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_DERIVED__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field FORCE_SWREG_PWD */ +#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__SHIFT 2 +#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__WIDTH 1 +#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__MASK 0x00000004U +#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field FORCE_LPO_PWD */ +#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__SHIFT 3 +#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__WIDTH 1 +#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__MASK 0x00000008U +#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define RTC_SYNC_DERIVED__TYPE u_int32_t +#define RTC_SYNC_DERIVED__READ 0x00000003U +#define RTC_SYNC_DERIVED__WRITE 0x00000003U + +#endif /* __RTC_SYNC_DERIVED_MACRO__ */ + + +/* macros for rtc_sync_reg_block.RTC_SYNC_DERIVED */ +#define INST_RTC_SYNC_REG_BLOCK__RTC_SYNC_DERIVED__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_FORCE_WAKE */ +#ifndef __RTC_SYNC_FORCE_WAKE_MACRO__ +#define __RTC_SYNC_FORCE_WAKE_MACRO__ + +/* macros for field ENABLE */ +#define RTC_SYNC_FORCE_WAKE__ENABLE__SHIFT 0 +#define RTC_SYNC_FORCE_WAKE__ENABLE__WIDTH 1 +#define RTC_SYNC_FORCE_WAKE__ENABLE__MASK 0x00000001U +#define RTC_SYNC_FORCE_WAKE__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RTC_SYNC_FORCE_WAKE__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_FORCE_WAKE__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field INTR */ +#define RTC_SYNC_FORCE_WAKE__INTR__SHIFT 1 +#define RTC_SYNC_FORCE_WAKE__INTR__WIDTH 1 +#define RTC_SYNC_FORCE_WAKE__INTR__MASK 0x00000002U +#define RTC_SYNC_FORCE_WAKE__INTR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_FORCE_WAKE__INTR__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTC_SYNC_FORCE_WAKE__INTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTC_SYNC_FORCE_WAKE__INTR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTC_SYNC_FORCE_WAKE__INTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_FORCE_WAKE__INTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define RTC_SYNC_FORCE_WAKE__TYPE u_int32_t +#define RTC_SYNC_FORCE_WAKE__READ 0x00000003U +#define RTC_SYNC_FORCE_WAKE__WRITE 0x00000003U + +#endif /* __RTC_SYNC_FORCE_WAKE_MACRO__ */ + + +/* macros for rtc_sync_reg_block.RTC_SYNC_FORCE_WAKE */ +#define INST_RTC_SYNC_REG_BLOCK__RTC_SYNC_FORCE_WAKE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_CAUSE */ +#ifndef __RTC_SYNC_INTR_CAUSE_MACRO__ +#define __RTC_SYNC_INTR_CAUSE_MACRO__ + +/* macros for field SHUTDOWN_STATE */ +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__SHIFT 0 +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MASK 0x00000001U +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ON_STATE */ +#define RTC_SYNC_INTR_CAUSE__ON_STATE__SHIFT 1 +#define RTC_SYNC_INTR_CAUSE__ON_STATE__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__ON_STATE__MASK 0x00000002U +#define RTC_SYNC_INTR_CAUSE__ON_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_INTR_CAUSE__ON_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTC_SYNC_INTR_CAUSE__ON_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTC_SYNC_INTR_CAUSE__ON_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTC_SYNC_INTR_CAUSE__ON_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_INTR_CAUSE__ON_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SLEEP_STATE */ +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__SHIFT 2 +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MASK 0x00000004U +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field WAKEUP_STATE */ +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__SHIFT 3 +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MASK 0x00000008U +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field SLEEP_ACCESS */ +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__SHIFT 4 +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MASK 0x00000010U +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PLL_CHANGING */ +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__SHIFT 5 +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MASK 0x00000020U +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define RTC_SYNC_INTR_CAUSE__TYPE u_int32_t +#define RTC_SYNC_INTR_CAUSE__READ 0x0000003fU +#define RTC_SYNC_INTR_CAUSE__WRITE 0x0000003fU + +#endif /* __RTC_SYNC_INTR_CAUSE_MACRO__ */ + + +/* macros for rtc_sync_reg_block.RTC_SYNC_INTR_CAUSE */ +#define INST_RTC_SYNC_REG_BLOCK__RTC_SYNC_INTR_CAUSE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_ENABLE */ +#ifndef __RTC_SYNC_INTR_ENABLE_MACRO__ +#define __RTC_SYNC_INTR_ENABLE_MACRO__ + +/* macros for field SHUTDOWN_STATE */ +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__SHIFT 0 +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MASK 0x00000001U +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ON_STATE */ +#define RTC_SYNC_INTR_ENABLE__ON_STATE__SHIFT 1 +#define RTC_SYNC_INTR_ENABLE__ON_STATE__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__ON_STATE__MASK 0x00000002U +#define RTC_SYNC_INTR_ENABLE__ON_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_INTR_ENABLE__ON_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTC_SYNC_INTR_ENABLE__ON_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTC_SYNC_INTR_ENABLE__ON_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTC_SYNC_INTR_ENABLE__ON_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_INTR_ENABLE__ON_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SLEEP_STATE */ +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__SHIFT 2 +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MASK 0x00000004U +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field WAKEUP_STATE */ +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__SHIFT 3 +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MASK 0x00000008U +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field SLEEP_ACCESS */ +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__SHIFT 4 +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MASK 0x00000010U +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PLL_CHANGING */ +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__SHIFT 5 +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MASK 0x00000020U +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define RTC_SYNC_INTR_ENABLE__TYPE u_int32_t +#define RTC_SYNC_INTR_ENABLE__READ 0x0000003fU +#define RTC_SYNC_INTR_ENABLE__WRITE 0x0000003fU + +#endif /* __RTC_SYNC_INTR_ENABLE_MACRO__ */ + + +/* macros for rtc_sync_reg_block.RTC_SYNC_INTR_ENABLE */ +#define INST_RTC_SYNC_REG_BLOCK__RTC_SYNC_INTR_ENABLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_MASK */ +#ifndef __RTC_SYNC_INTR_MASK_MACRO__ +#define __RTC_SYNC_INTR_MASK_MACRO__ + +/* macros for field SHUTDOWN_STATE */ +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__SHIFT 0 +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WIDTH 1 +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MASK 0x00000001U +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ON_STATE */ +#define RTC_SYNC_INTR_MASK__ON_STATE__SHIFT 1 +#define RTC_SYNC_INTR_MASK__ON_STATE__WIDTH 1 +#define RTC_SYNC_INTR_MASK__ON_STATE__MASK 0x00000002U +#define RTC_SYNC_INTR_MASK__ON_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_INTR_MASK__ON_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTC_SYNC_INTR_MASK__ON_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTC_SYNC_INTR_MASK__ON_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTC_SYNC_INTR_MASK__ON_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_INTR_MASK__ON_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SLEEP_STATE */ +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__SHIFT 2 +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__MASK 0x00000004U +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field WAKEUP_STATE */ +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__SHIFT 3 +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MASK 0x00000008U +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field SLEEP_ACCESS */ +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__SHIFT 4 +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WIDTH 1 +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MASK 0x00000010U +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PLL_CHANGING */ +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__SHIFT 5 +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__WIDTH 1 +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__MASK 0x00000020U +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define RTC_SYNC_INTR_MASK__TYPE u_int32_t +#define RTC_SYNC_INTR_MASK__READ 0x0000003fU +#define RTC_SYNC_INTR_MASK__WRITE 0x0000003fU + +#endif /* __RTC_SYNC_INTR_MASK_MACRO__ */ + + +/* macros for rtc_sync_reg_block.RTC_SYNC_INTR_MASK */ +#define INST_RTC_SYNC_REG_BLOCK__RTC_SYNC_INTR_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RXTXBB1_CH1 */ +#ifndef __RADIO130NM_RXTXBB1_CH1_MACRO__ +#define __RADIO130NM_RXTXBB1_CH1_MACRO__ + +/* macros for field PDHIQ */ +#define RADIO130NM_RXTXBB1_CH1__PDHIQ__SHIFT 0 +#define RADIO130NM_RXTXBB1_CH1__PDHIQ__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH1__PDHIQ__MASK 0x00000001U +#define RADIO130NM_RXTXBB1_CH1__PDHIQ__READ(src) (u_int32_t)(src) & 0x00000001U +#define RADIO130NM_RXTXBB1_CH1__PDHIQ__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_RXTXBB1_CH1__PDHIQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_RXTXBB1_CH1__PDHIQ__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_RXTXBB1_CH1__PDHIQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_RXTXBB1_CH1__PDHIQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PDLOQ */ +#define RADIO130NM_RXTXBB1_CH1__PDLOQ__SHIFT 1 +#define RADIO130NM_RXTXBB1_CH1__PDLOQ__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH1__PDLOQ__MASK 0x00000002U +#define RADIO130NM_RXTXBB1_CH1__PDLOQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO130NM_RXTXBB1_CH1__PDLOQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO130NM_RXTXBB1_CH1__PDLOQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO130NM_RXTXBB1_CH1__PDLOQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO130NM_RXTXBB1_CH1__PDLOQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RADIO130NM_RXTXBB1_CH1__PDLOQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field PDOFFSETI2V */ +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__SHIFT 2 +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__MASK 0x00000004U +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field PDOFFSETHIQ */ +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__SHIFT 3 +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__MASK 0x00000008U +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field PDOFFSETLOQ */ +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__SHIFT 4 +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__MASK 0x00000010U +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PDRXTXBB */ +#define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__SHIFT 5 +#define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__MASK 0x00000020U +#define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field PDI2V */ +#define RADIO130NM_RXTXBB1_CH1__PDI2V__SHIFT 6 +#define RADIO130NM_RXTXBB1_CH1__PDI2V__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH1__PDI2V__MASK 0x00000040U +#define RADIO130NM_RXTXBB1_CH1__PDI2V__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO130NM_RXTXBB1_CH1__PDI2V__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO130NM_RXTXBB1_CH1__PDI2V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO130NM_RXTXBB1_CH1__PDI2V__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO130NM_RXTXBB1_CH1__PDI2V__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RADIO130NM_RXTXBB1_CH1__PDI2V__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field PDV2I */ +#define RADIO130NM_RXTXBB1_CH1__PDV2I__SHIFT 7 +#define RADIO130NM_RXTXBB1_CH1__PDV2I__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH1__PDV2I__MASK 0x00000080U +#define RADIO130NM_RXTXBB1_CH1__PDV2I__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO130NM_RXTXBB1_CH1__PDV2I__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO130NM_RXTXBB1_CH1__PDV2I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO130NM_RXTXBB1_CH1__PDV2I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO130NM_RXTXBB1_CH1__PDV2I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RADIO130NM_RXTXBB1_CH1__PDV2I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field PDDACINTERFACE */ +#define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__SHIFT 8 +#define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__MASK 0x00000100U +#define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field SEL_ATB */ +#define RADIO130NM_RXTXBB1_CH1__SEL_ATB__SHIFT 9 +#define RADIO130NM_RXTXBB1_CH1__SEL_ATB__WIDTH 8 +#define RADIO130NM_RXTXBB1_CH1__SEL_ATB__MASK 0x0001fe00U +#define RADIO130NM_RXTXBB1_CH1__SEL_ATB__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fe00U) >> 9) +#define RADIO130NM_RXTXBB1_CH1__SEL_ATB__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x0001fe00U) +#define RADIO130NM_RXTXBB1_CH1__SEL_ATB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((u_int32_t)(src) <<\ + 9) & 0x0001fe00U) +#define RADIO130NM_RXTXBB1_CH1__SEL_ATB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x0001fe00U))) + +/* macros for field FNOTCH */ +#define RADIO130NM_RXTXBB1_CH1__FNOTCH__SHIFT 17 +#define RADIO130NM_RXTXBB1_CH1__FNOTCH__WIDTH 2 +#define RADIO130NM_RXTXBB1_CH1__FNOTCH__MASK 0x00060000U +#define RADIO130NM_RXTXBB1_CH1__FNOTCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00060000U) >> 17) +#define RADIO130NM_RXTXBB1_CH1__FNOTCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00060000U) +#define RADIO130NM_RXTXBB1_CH1__FNOTCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((u_int32_t)(src) <<\ + 17) & 0x00060000U) +#define RADIO130NM_RXTXBB1_CH1__FNOTCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00060000U))) + +/* macros for field SPARE */ +#define RADIO130NM_RXTXBB1_CH1__SPARE__SHIFT 19 +#define RADIO130NM_RXTXBB1_CH1__SPARE__WIDTH 13 +#define RADIO130NM_RXTXBB1_CH1__SPARE__MASK 0xfff80000U +#define RADIO130NM_RXTXBB1_CH1__SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0xfff80000U) >> 19) +#define RADIO130NM_RXTXBB1_CH1__SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0xfff80000U) +#define RADIO130NM_RXTXBB1_CH1__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfff80000U) | (((u_int32_t)(src) <<\ + 19) & 0xfff80000U) +#define RADIO130NM_RXTXBB1_CH1__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0xfff80000U))) +#define RADIO130NM_RXTXBB1_CH1__TYPE u_int32_t +#define RADIO130NM_RXTXBB1_CH1__READ 0xffffffffU +#define RADIO130NM_RXTXBB1_CH1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RXTXBB1_CH1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RXTXBB1_CH1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RXTXBB1_CH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RXTXBB2_CH1 */ +#ifndef __RADIO130NM_RXTXBB2_CH1_MACRO__ +#define __RADIO130NM_RXTXBB2_CH1_MACRO__ + +/* macros for field PATH_OVERRIDE */ +#define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__SHIFT 0 +#define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__MASK 0x00000001U +#define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PATH1LOQ_EN */ +#define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__SHIFT 1 +#define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__MASK 0x00000002U +#define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field PATH2LOQ_EN */ +#define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__SHIFT 2 +#define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__MASK 0x00000004U +#define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field PATH3LOQ_EN */ +#define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__SHIFT 3 +#define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__MASK 0x00000008U +#define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field PATH1HIQ_EN */ +#define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__SHIFT 4 +#define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__MASK 0x00000010U +#define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PATH2HIQ_EN */ +#define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__SHIFT 5 +#define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__MASK 0x00000020U +#define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field FILTERDOUBLEBW */ +#define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__SHIFT 6 +#define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__MASK 0x00000040U +#define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field LOCALFILTERTUNING */ +#define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__SHIFT 7 +#define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__MASK 0x00000080U +#define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field FILTERFC */ +#define RADIO130NM_RXTXBB2_CH1__FILTERFC__SHIFT 8 +#define RADIO130NM_RXTXBB2_CH1__FILTERFC__WIDTH 5 +#define RADIO130NM_RXTXBB2_CH1__FILTERFC__MASK 0x00001f00U +#define RADIO130NM_RXTXBB2_CH1__FILTERFC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define RADIO130NM_RXTXBB2_CH1__FILTERFC__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define RADIO130NM_RXTXBB2_CH1__FILTERFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define RADIO130NM_RXTXBB2_CH1__FILTERFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) + +/* macros for field CMSEL */ +#define RADIO130NM_RXTXBB2_CH1__CMSEL__SHIFT 13 +#define RADIO130NM_RXTXBB2_CH1__CMSEL__WIDTH 2 +#define RADIO130NM_RXTXBB2_CH1__CMSEL__MASK 0x00006000U +#define RADIO130NM_RXTXBB2_CH1__CMSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00006000U) >> 13) +#define RADIO130NM_RXTXBB2_CH1__CMSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00006000U) +#define RADIO130NM_RXTXBB2_CH1__CMSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00006000U) | (((u_int32_t)(src) <<\ + 13) & 0x00006000U) +#define RADIO130NM_RXTXBB2_CH1__CMSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00006000U))) + +/* macros for field SEL_I2V_TEST */ +#define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__SHIFT 15 +#define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__MASK 0x00008000U +#define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field SEL_HIQ_TEST */ +#define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__SHIFT 16 +#define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__MASK 0x00010000U +#define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field SEL_LOQ_TEST */ +#define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__SHIFT 17 +#define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__MASK 0x00020000U +#define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field SEL_DAC_TEST */ +#define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__SHIFT 18 +#define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__MASK 0x00040000U +#define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field SELBUFFER */ +#define RADIO130NM_RXTXBB2_CH1__SELBUFFER__SHIFT 19 +#define RADIO130NM_RXTXBB2_CH1__SELBUFFER__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__SELBUFFER__MASK 0x00080000U +#define RADIO130NM_RXTXBB2_CH1__SELBUFFER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define RADIO130NM_RXTXBB2_CH1__SELBUFFER__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define RADIO130NM_RXTXBB2_CH1__SELBUFFER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define RADIO130NM_RXTXBB2_CH1__SELBUFFER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define RADIO130NM_RXTXBB2_CH1__SELBUFFER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define RADIO130NM_RXTXBB2_CH1__SELBUFFER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field SHORTBUFFER */ +#define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__SHIFT 20 +#define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__MASK 0x00100000U +#define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field SPARE */ +#define RADIO130NM_RXTXBB2_CH1__SPARE__SHIFT 21 +#define RADIO130NM_RXTXBB2_CH1__SPARE__WIDTH 2 +#define RADIO130NM_RXTXBB2_CH1__SPARE__MASK 0x00600000U +#define RADIO130NM_RXTXBB2_CH1__SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00600000U) >> 21) +#define RADIO130NM_RXTXBB2_CH1__SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00600000U) +#define RADIO130NM_RXTXBB2_CH1__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((u_int32_t)(src) <<\ + 21) & 0x00600000U) +#define RADIO130NM_RXTXBB2_CH1__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00600000U))) + +/* macros for field IBN_37P5_OSI2V_CTRL */ +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__SHIFT 23 +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__MASK 0x03800000U +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field IBN_37P5_OSLO_CTRL */ +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__SHIFT 26 +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__MASK 0x1c000000U +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field IBN_37P5_OSHI_CTRL */ +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__SHIFT 29 +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__MASK 0xe0000000U +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RADIO130NM_RXTXBB2_CH1__TYPE u_int32_t +#define RADIO130NM_RXTXBB2_CH1__READ 0xffffffffU +#define RADIO130NM_RXTXBB2_CH1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RXTXBB2_CH1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RXTXBB2_CH1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RXTXBB2_CH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RXTXBB3_CH1 */ +#ifndef __RADIO130NM_RXTXBB3_CH1_MACRO__ +#define __RADIO130NM_RXTXBB3_CH1_MACRO__ + +/* macros for field IBN_100U_TEST_CTRL */ +#define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__SHIFT 0 +#define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__MASK 0x00000007U +#define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field IBRN_12P5_CM_CTRL */ +#define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__SHIFT 3 +#define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__MASK 0x00000038U +#define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field IBN_25U_LO2_CTRL */ +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__SHIFT 6 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__MASK 0x000001c0U +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001c0U) >> 6) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000001c0U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field IBN_25U_LO1_CTRL */ +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__SHIFT 9 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__MASK 0x00000e00U +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000e00U) >> 9) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field IBN_25U_HI2_CTRL */ +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__SHIFT 12 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__MASK 0x00007000U +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007000U) >> 12) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00007000U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field IBN_25U_HI1_CTRL */ +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__SHIFT 15 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__MASK 0x00038000U +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00038000U) >> 15) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00038000U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field IBN_25U_I2V_CTRL */ +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__SHIFT 18 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__MASK 0x001c0000U +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x001c0000U) >> 18) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x001c0000U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field IBN_25U_BKV2I_CTRL */ +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__SHIFT 21 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__MASK 0x00e00000U +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00e00000U) >> 21) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00e00000U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field IBN_25U_CM_BUFAMP_CTRL */ +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__SHIFT 24 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__MASK 0x07000000U +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x07000000U) >> 24) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x07000000U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x07000000U))) + +/* macros for field SPARE */ +#define RADIO130NM_RXTXBB3_CH1__SPARE__SHIFT 27 +#define RADIO130NM_RXTXBB3_CH1__SPARE__WIDTH 5 +#define RADIO130NM_RXTXBB3_CH1__SPARE__MASK 0xf8000000U +#define RADIO130NM_RXTXBB3_CH1__SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define RADIO130NM_RXTXBB3_CH1__SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define RADIO130NM_RXTXBB3_CH1__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define RADIO130NM_RXTXBB3_CH1__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define RADIO130NM_RXTXBB3_CH1__TYPE u_int32_t +#define RADIO130NM_RXTXBB3_CH1__READ 0xffffffffU +#define RADIO130NM_RXTXBB3_CH1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RXTXBB3_CH1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RXTXBB3_CH1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RXTXBB3_CH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RXTXBB4_CH1 */ +#ifndef __RADIO130NM_RXTXBB4_CH1_MACRO__ +#define __RADIO130NM_RXTXBB4_CH1_MACRO__ + +/* macros for field OFSTCORRI2VQ */ +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__SHIFT 0 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__MASK 0x0000001fU +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field OFSTCORRI2VI */ +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__SHIFT 5 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__MASK 0x000003e0U +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field OFSTCORRLOQ */ +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__SHIFT 10 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__MASK 0x00007c00U +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field OFSTCORRLOI */ +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__SHIFT 15 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__MASK 0x000f8000U +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field OFSTCORRHIQ */ +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__SHIFT 20 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__MASK 0x01f00000U +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field OFSTCORRHII */ +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__SHIFT 25 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__MASK 0x3e000000U +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) + +/* macros for field LOCALOFFSET */ +#define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__SHIFT 30 +#define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__WIDTH 1 +#define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__MASK 0x40000000U +#define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field SPARE */ +#define RADIO130NM_RXTXBB4_CH1__SPARE__SHIFT 31 +#define RADIO130NM_RXTXBB4_CH1__SPARE__WIDTH 1 +#define RADIO130NM_RXTXBB4_CH1__SPARE__MASK 0x80000000U +#define RADIO130NM_RXTXBB4_CH1__SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_RXTXBB4_CH1__SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_RXTXBB4_CH1__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_RXTXBB4_CH1__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_RXTXBB4_CH1__SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_RXTXBB4_CH1__SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_RXTXBB4_CH1__TYPE u_int32_t +#define RADIO130NM_RXTXBB4_CH1__READ 0xffffffffU +#define RADIO130NM_RXTXBB4_CH1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RXTXBB4_CH1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RXTXBB4_CH1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RXTXBB4_CH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RF2G1_CH1 */ +#ifndef __RADIO130NM_RF2G1_CH1_MACRO__ +#define __RADIO130NM_RF2G1_CH1_MACRO__ + +/* macros for field SPARES */ +#define RADIO130NM_RF2G1_CH1__SPARES__SHIFT 0 +#define RADIO130NM_RF2G1_CH1__SPARES__WIDTH 6 +#define RADIO130NM_RF2G1_CH1__SPARES__MASK 0x0000003fU +#define RADIO130NM_RF2G1_CH1__SPARES__READ(src) (u_int32_t)(src) & 0x0000003fU +#define RADIO130NM_RF2G1_CH1__SPARES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define RADIO130NM_RF2G1_CH1__SPARES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define RADIO130NM_RF2G1_CH1__SPARES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field REGLO_BYPASS */ +#define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__SHIFT 6 +#define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__WIDTH 1 +#define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__MASK 0x00000040U +#define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field REGLNA_BYPASS */ +#define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__SHIFT 7 +#define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__WIDTH 1 +#define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__MASK 0x00000080U +#define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field PDIC25U_VGM */ +#define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__SHIFT 8 +#define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__WIDTH 3 +#define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__MASK 0x00000700U +#define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field PACA_SEL */ +#define RADIO130NM_RF2G1_CH1__PACA_SEL__SHIFT 11 +#define RADIO130NM_RF2G1_CH1__PACA_SEL__WIDTH 2 +#define RADIO130NM_RF2G1_CH1__PACA_SEL__MASK 0x00001800U +#define RADIO130NM_RF2G1_CH1__PACA_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001800U) >> 11) +#define RADIO130NM_RF2G1_CH1__PACA_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00001800U) +#define RADIO130NM_RF2G1_CH1__PACA_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define RADIO130NM_RF2G1_CH1__PACA_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field LOCONTROL */ +#define RADIO130NM_RF2G1_CH1__LOCONTROL__SHIFT 13 +#define RADIO130NM_RF2G1_CH1__LOCONTROL__WIDTH 1 +#define RADIO130NM_RF2G1_CH1__LOCONTROL__MASK 0x00002000U +#define RADIO130NM_RF2G1_CH1__LOCONTROL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define RADIO130NM_RF2G1_CH1__LOCONTROL__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define RADIO130NM_RF2G1_CH1__LOCONTROL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RADIO130NM_RF2G1_CH1__LOCONTROL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RADIO130NM_RF2G1_CH1__LOCONTROL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RADIO130NM_RF2G1_CH1__LOCONTROL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field TXATB_SEL */ +#define RADIO130NM_RF2G1_CH1__TXATB_SEL__SHIFT 14 +#define RADIO130NM_RF2G1_CH1__TXATB_SEL__WIDTH 3 +#define RADIO130NM_RF2G1_CH1__TXATB_SEL__MASK 0x0001c000U +#define RADIO130NM_RF2G1_CH1__TXATB_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define RADIO130NM_RF2G1_CH1__TXATB_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define RADIO130NM_RF2G1_CH1__TXATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define RADIO130NM_RF2G1_CH1__TXATB_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field RXATB_SEL */ +#define RADIO130NM_RF2G1_CH1__RXATB_SEL__SHIFT 17 +#define RADIO130NM_RF2G1_CH1__RXATB_SEL__WIDTH 3 +#define RADIO130NM_RF2G1_CH1__RXATB_SEL__MASK 0x000e0000U +#define RADIO130NM_RF2G1_CH1__RXATB_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define RADIO130NM_RF2G1_CH1__RXATB_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define RADIO130NM_RF2G1_CH1__RXATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define RADIO130NM_RF2G1_CH1__RXATB_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field LOATB_SEL */ +#define RADIO130NM_RF2G1_CH1__LOATB_SEL__SHIFT 20 +#define RADIO130NM_RF2G1_CH1__LOATB_SEL__WIDTH 3 +#define RADIO130NM_RF2G1_CH1__LOATB_SEL__MASK 0x00700000U +#define RADIO130NM_RF2G1_CH1__LOATB_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RADIO130NM_RF2G1_CH1__LOATB_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RADIO130NM_RF2G1_CH1__LOATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RADIO130NM_RF2G1_CH1__LOATB_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field OB */ +#define RADIO130NM_RF2G1_CH1__OB__SHIFT 23 +#define RADIO130NM_RF2G1_CH1__OB__WIDTH 3 +#define RADIO130NM_RF2G1_CH1__OB__MASK 0x03800000U +#define RADIO130NM_RF2G1_CH1__OB__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RADIO130NM_RF2G1_CH1__OB__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RADIO130NM_RF2G1_CH1__OB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RADIO130NM_RF2G1_CH1__OB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field DB */ +#define RADIO130NM_RF2G1_CH1__DB__SHIFT 26 +#define RADIO130NM_RF2G1_CH1__DB__WIDTH 3 +#define RADIO130NM_RF2G1_CH1__DB__MASK 0x1c000000U +#define RADIO130NM_RF2G1_CH1__DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define RADIO130NM_RF2G1_CH1__DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define RADIO130NM_RF2G1_CH1__DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RADIO130NM_RF2G1_CH1__DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field PDIC25U_LNA */ +#define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__SHIFT 29 +#define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__WIDTH 3 +#define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__MASK 0xe0000000U +#define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RADIO130NM_RF2G1_CH1__TYPE u_int32_t +#define RADIO130NM_RF2G1_CH1__READ 0xffffffffU +#define RADIO130NM_RF2G1_CH1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RF2G1_CH1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RF2G1_CH1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RF2G1_CH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RF2G2_CH1 */ +#ifndef __RADIO130NM_RF2G2_CH1_MACRO__ +#define __RADIO130NM_RF2G2_CH1_MACRO__ + +/* macros for field PDIR25U_VREGLO */ +#define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__SHIFT 0 +#define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__WIDTH 3 +#define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__MASK 0x00000007U +#define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field PDIC25U_VREGLO */ +#define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__SHIFT 3 +#define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__WIDTH 3 +#define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__MASK 0x00000038U +#define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field PDIC50U_DIV */ +#define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__SHIFT 6 +#define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__WIDTH 3 +#define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__MASK 0x000001c0U +#define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001c0U) >> 6) +#define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000001c0U) +#define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field PDIC25U_RXRF */ +#define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__SHIFT 9 +#define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__WIDTH 3 +#define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__MASK 0x00000e00U +#define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000e00U) >> 9) +#define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field PDIC25U_TXRF */ +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__SHIFT 12 +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__WIDTH 3 +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__MASK 0x00007000U +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007000U) >> 12) +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00007000U) +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field PDIC25U_TXPA */ +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__SHIFT 15 +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__WIDTH 3 +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__MASK 0x00038000U +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00038000U) >> 15) +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00038000U) +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field PDIR25U_TXPA */ +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__SHIFT 18 +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__WIDTH 1 +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__MASK 0x00040000U +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field PDIR25U_TXMIX */ +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__SHIFT 19 +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__WIDTH 3 +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__MASK 0x00380000U +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00380000U) >> 19) +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field PDTXMIX */ +#define RADIO130NM_RF2G2_CH1__PDTXMIX__SHIFT 22 +#define RADIO130NM_RF2G2_CH1__PDTXMIX__WIDTH 1 +#define RADIO130NM_RF2G2_CH1__PDTXMIX__MASK 0x00400000U +#define RADIO130NM_RF2G2_CH1__PDTXMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define RADIO130NM_RF2G2_CH1__PDTXMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define RADIO130NM_RF2G2_CH1__PDTXMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define RADIO130NM_RF2G2_CH1__PDTXMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define RADIO130NM_RF2G2_CH1__PDTXMIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define RADIO130NM_RF2G2_CH1__PDTXMIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field PDTXLO */ +#define RADIO130NM_RF2G2_CH1__PDTXLO__SHIFT 23 +#define RADIO130NM_RF2G2_CH1__PDTXLO__WIDTH 1 +#define RADIO130NM_RF2G2_CH1__PDTXLO__MASK 0x00800000U +#define RADIO130NM_RF2G2_CH1__PDTXLO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define RADIO130NM_RF2G2_CH1__PDTXLO__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define RADIO130NM_RF2G2_CH1__PDTXLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RADIO130NM_RF2G2_CH1__PDTXLO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RADIO130NM_RF2G2_CH1__PDTXLO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RADIO130NM_RF2G2_CH1__PDTXLO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field PDRXLO */ +#define RADIO130NM_RF2G2_CH1__PDRXLO__SHIFT 24 +#define RADIO130NM_RF2G2_CH1__PDRXLO__WIDTH 1 +#define RADIO130NM_RF2G2_CH1__PDRXLO__MASK 0x01000000U +#define RADIO130NM_RF2G2_CH1__PDRXLO__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO130NM_RF2G2_CH1__PDRXLO__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RADIO130NM_RF2G2_CH1__PDRXLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RADIO130NM_RF2G2_CH1__PDRXLO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RADIO130NM_RF2G2_CH1__PDRXLO__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RADIO130NM_RF2G2_CH1__PDRXLO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field PDVGM */ +#define RADIO130NM_RF2G2_CH1__PDVGM__SHIFT 25 +#define RADIO130NM_RF2G2_CH1__PDVGM__WIDTH 1 +#define RADIO130NM_RF2G2_CH1__PDVGM__MASK 0x02000000U +#define RADIO130NM_RF2G2_CH1__PDVGM__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define RADIO130NM_RF2G2_CH1__PDVGM__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define RADIO130NM_RF2G2_CH1__PDVGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RADIO130NM_RF2G2_CH1__PDVGM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RADIO130NM_RF2G2_CH1__PDVGM__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RADIO130NM_RF2G2_CH1__PDVGM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field PDREGLO */ +#define RADIO130NM_RF2G2_CH1__PDREGLO__SHIFT 26 +#define RADIO130NM_RF2G2_CH1__PDREGLO__WIDTH 1 +#define RADIO130NM_RF2G2_CH1__PDREGLO__MASK 0x04000000U +#define RADIO130NM_RF2G2_CH1__PDREGLO__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO130NM_RF2G2_CH1__PDREGLO__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO130NM_RF2G2_CH1__PDREGLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO130NM_RF2G2_CH1__PDREGLO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO130NM_RF2G2_CH1__PDREGLO__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RADIO130NM_RF2G2_CH1__PDREGLO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field PDREGLNA */ +#define RADIO130NM_RF2G2_CH1__PDREGLNA__SHIFT 27 +#define RADIO130NM_RF2G2_CH1__PDREGLNA__WIDTH 1 +#define RADIO130NM_RF2G2_CH1__PDREGLNA__MASK 0x08000000U +#define RADIO130NM_RF2G2_CH1__PDREGLNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO130NM_RF2G2_CH1__PDREGLNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO130NM_RF2G2_CH1__PDREGLNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO130NM_RF2G2_CH1__PDREGLNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO130NM_RF2G2_CH1__PDREGLNA__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADIO130NM_RF2G2_CH1__PDREGLNA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field PDPAOUT */ +#define RADIO130NM_RF2G2_CH1__PDPAOUT__SHIFT 28 +#define RADIO130NM_RF2G2_CH1__PDPAOUT__WIDTH 1 +#define RADIO130NM_RF2G2_CH1__PDPAOUT__MASK 0x10000000U +#define RADIO130NM_RF2G2_CH1__PDPAOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_RF2G2_CH1__PDPAOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_RF2G2_CH1__PDPAOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_RF2G2_CH1__PDPAOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_RF2G2_CH1__PDPAOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_RF2G2_CH1__PDPAOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PDPADRV */ +#define RADIO130NM_RF2G2_CH1__PDPADRV__SHIFT 29 +#define RADIO130NM_RF2G2_CH1__PDPADRV__WIDTH 1 +#define RADIO130NM_RF2G2_CH1__PDPADRV__MASK 0x20000000U +#define RADIO130NM_RF2G2_CH1__PDPADRV__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_RF2G2_CH1__PDPADRV__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_RF2G2_CH1__PDPADRV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_RF2G2_CH1__PDPADRV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_RF2G2_CH1__PDPADRV__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_RF2G2_CH1__PDPADRV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PDDIV */ +#define RADIO130NM_RF2G2_CH1__PDDIV__SHIFT 30 +#define RADIO130NM_RF2G2_CH1__PDDIV__WIDTH 1 +#define RADIO130NM_RF2G2_CH1__PDDIV__MASK 0x40000000U +#define RADIO130NM_RF2G2_CH1__PDDIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_RF2G2_CH1__PDDIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_RF2G2_CH1__PDDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_RF2G2_CH1__PDDIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_RF2G2_CH1__PDDIV__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_RF2G2_CH1__PDDIV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PDLNA */ +#define RADIO130NM_RF2G2_CH1__PDLNA__SHIFT 31 +#define RADIO130NM_RF2G2_CH1__PDLNA__WIDTH 1 +#define RADIO130NM_RF2G2_CH1__PDLNA__MASK 0x80000000U +#define RADIO130NM_RF2G2_CH1__PDLNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_RF2G2_CH1__PDLNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_RF2G2_CH1__PDLNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_RF2G2_CH1__PDLNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_RF2G2_CH1__PDLNA__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_RF2G2_CH1__PDLNA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_RF2G2_CH1__TYPE u_int32_t +#define RADIO130NM_RF2G2_CH1__READ 0xffffffffU +#define RADIO130NM_RF2G2_CH1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RF2G2_CH1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RF2G2_CH1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RF2G2_CH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RF5G1_CH1 */ +#ifndef __RADIO130NM_RF5G1_CH1_MACRO__ +#define __RADIO130NM_RF5G1_CH1_MACRO__ + +/* macros for field SPARE */ +#define RADIO130NM_RF5G1_CH1__SPARE__SHIFT 0 +#define RADIO130NM_RF5G1_CH1__SPARE__WIDTH 10 +#define RADIO130NM_RF5G1_CH1__SPARE__MASK 0x000003ffU +#define RADIO130NM_RF5G1_CH1__SPARE__READ(src) (u_int32_t)(src) & 0x000003ffU +#define RADIO130NM_RF5G1_CH1__SPARE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define RADIO130NM_RF5G1_CH1__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define RADIO130NM_RF5G1_CH1__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field PDREGLO5 */ +#define RADIO130NM_RF5G1_CH1__PDREGLO5__SHIFT 10 +#define RADIO130NM_RF5G1_CH1__PDREGLO5__WIDTH 1 +#define RADIO130NM_RF5G1_CH1__PDREGLO5__MASK 0x00000400U +#define RADIO130NM_RF5G1_CH1__PDREGLO5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define RADIO130NM_RF5G1_CH1__PDREGLO5__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define RADIO130NM_RF5G1_CH1__PDREGLO5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RADIO130NM_RF5G1_CH1__PDREGLO5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RADIO130NM_RF5G1_CH1__PDREGLO5__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RADIO130NM_RF5G1_CH1__PDREGLO5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field REGLO_BYPASS5 */ +#define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__SHIFT 11 +#define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__WIDTH 1 +#define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__MASK 0x00000800U +#define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field LO5CONTROL */ +#define RADIO130NM_RF5G1_CH1__LO5CONTROL__SHIFT 12 +#define RADIO130NM_RF5G1_CH1__LO5CONTROL__WIDTH 1 +#define RADIO130NM_RF5G1_CH1__LO5CONTROL__MASK 0x00001000U +#define RADIO130NM_RF5G1_CH1__LO5CONTROL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define RADIO130NM_RF5G1_CH1__LO5CONTROL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define RADIO130NM_RF5G1_CH1__LO5CONTROL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define RADIO130NM_RF5G1_CH1__LO5CONTROL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define RADIO130NM_RF5G1_CH1__LO5CONTROL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define RADIO130NM_RF5G1_CH1__LO5CONTROL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field TX5_ATB_SEL */ +#define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__SHIFT 13 +#define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__WIDTH 3 +#define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__MASK 0x0000e000U +#define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000e000U) >> 13) +#define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0000e000U) +#define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0000e000U))) + +/* macros for field OB5 */ +#define RADIO130NM_RF5G1_CH1__OB5__SHIFT 16 +#define RADIO130NM_RF5G1_CH1__OB5__WIDTH 3 +#define RADIO130NM_RF5G1_CH1__OB5__MASK 0x00070000U +#define RADIO130NM_RF5G1_CH1__OB5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define RADIO130NM_RF5G1_CH1__OB5__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define RADIO130NM_RF5G1_CH1__OB5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define RADIO130NM_RF5G1_CH1__OB5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field DB5 */ +#define RADIO130NM_RF5G1_CH1__DB5__SHIFT 19 +#define RADIO130NM_RF5G1_CH1__DB5__WIDTH 3 +#define RADIO130NM_RF5G1_CH1__DB5__MASK 0x00380000U +#define RADIO130NM_RF5G1_CH1__DB5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00380000U) >> 19) +#define RADIO130NM_RF5G1_CH1__DB5__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define RADIO130NM_RF5G1_CH1__DB5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define RADIO130NM_RF5G1_CH1__DB5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field PWDTXPKD */ +#define RADIO130NM_RF5G1_CH1__PWDTXPKD__SHIFT 22 +#define RADIO130NM_RF5G1_CH1__PWDTXPKD__WIDTH 3 +#define RADIO130NM_RF5G1_CH1__PWDTXPKD__MASK 0x01c00000U +#define RADIO130NM_RF5G1_CH1__PWDTXPKD__READ(src) \ + (((u_int32_t)(src)\ + & 0x01c00000U) >> 22) +#define RADIO130NM_RF5G1_CH1__PWDTXPKD__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x01c00000U) +#define RADIO130NM_RF5G1_CH1__PWDTXPKD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x01c00000U) +#define RADIO130NM_RF5G1_CH1__PWDTXPKD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x01c00000U))) + +/* macros for field PACASCBIAS */ +#define RADIO130NM_RF5G1_CH1__PACASCBIAS__SHIFT 25 +#define RADIO130NM_RF5G1_CH1__PACASCBIAS__WIDTH 2 +#define RADIO130NM_RF5G1_CH1__PACASCBIAS__MASK 0x06000000U +#define RADIO130NM_RF5G1_CH1__PACASCBIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define RADIO130NM_RF5G1_CH1__PACASCBIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define RADIO130NM_RF5G1_CH1__PACASCBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define RADIO130NM_RF5G1_CH1__PACASCBIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field PDPAOUT5 */ +#define RADIO130NM_RF5G1_CH1__PDPAOUT5__SHIFT 27 +#define RADIO130NM_RF5G1_CH1__PDPAOUT5__WIDTH 1 +#define RADIO130NM_RF5G1_CH1__PDPAOUT5__MASK 0x08000000U +#define RADIO130NM_RF5G1_CH1__PDPAOUT5__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO130NM_RF5G1_CH1__PDPAOUT5__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO130NM_RF5G1_CH1__PDPAOUT5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO130NM_RF5G1_CH1__PDPAOUT5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO130NM_RF5G1_CH1__PDPAOUT5__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADIO130NM_RF5G1_CH1__PDPAOUT5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field PDPADRV5 */ +#define RADIO130NM_RF5G1_CH1__PDPADRV5__SHIFT 28 +#define RADIO130NM_RF5G1_CH1__PDPADRV5__WIDTH 1 +#define RADIO130NM_RF5G1_CH1__PDPADRV5__MASK 0x10000000U +#define RADIO130NM_RF5G1_CH1__PDPADRV5__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_RF5G1_CH1__PDPADRV5__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_RF5G1_CH1__PDPADRV5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_RF5G1_CH1__PDPADRV5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_RF5G1_CH1__PDPADRV5__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_RF5G1_CH1__PDPADRV5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PDTXBUF5 */ +#define RADIO130NM_RF5G1_CH1__PDTXBUF5__SHIFT 29 +#define RADIO130NM_RF5G1_CH1__PDTXBUF5__WIDTH 1 +#define RADIO130NM_RF5G1_CH1__PDTXBUF5__MASK 0x20000000U +#define RADIO130NM_RF5G1_CH1__PDTXBUF5__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_RF5G1_CH1__PDTXBUF5__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_RF5G1_CH1__PDTXBUF5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_RF5G1_CH1__PDTXBUF5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_RF5G1_CH1__PDTXBUF5__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_RF5G1_CH1__PDTXBUF5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PDTXMIX5 */ +#define RADIO130NM_RF5G1_CH1__PDTXMIX5__SHIFT 30 +#define RADIO130NM_RF5G1_CH1__PDTXMIX5__WIDTH 1 +#define RADIO130NM_RF5G1_CH1__PDTXMIX5__MASK 0x40000000U +#define RADIO130NM_RF5G1_CH1__PDTXMIX5__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_RF5G1_CH1__PDTXMIX5__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_RF5G1_CH1__PDTXMIX5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_RF5G1_CH1__PDTXMIX5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_RF5G1_CH1__PDTXMIX5__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_RF5G1_CH1__PDTXMIX5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PDTXLO5 */ +#define RADIO130NM_RF5G1_CH1__PDTXLO5__SHIFT 31 +#define RADIO130NM_RF5G1_CH1__PDTXLO5__WIDTH 1 +#define RADIO130NM_RF5G1_CH1__PDTXLO5__MASK 0x80000000U +#define RADIO130NM_RF5G1_CH1__PDTXLO5__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_RF5G1_CH1__PDTXLO5__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_RF5G1_CH1__PDTXLO5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_RF5G1_CH1__PDTXLO5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_RF5G1_CH1__PDTXLO5__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_RF5G1_CH1__PDTXLO5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_RF5G1_CH1__TYPE u_int32_t +#define RADIO130NM_RF5G1_CH1__READ 0xffffffffU +#define RADIO130NM_RF5G1_CH1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RF5G1_CH1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RF5G1_CH1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RF5G1_CH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RF5G2_CH1 */ +#ifndef __RADIO130NM_RF5G2_CH1_MACRO__ +#define __RADIO130NM_RF5G2_CH1_MACRO__ + +/* macros for field SPARE */ +#define RADIO130NM_RF5G2_CH1__SPARE__SHIFT 0 +#define RADIO130NM_RF5G2_CH1__SPARE__WIDTH 11 +#define RADIO130NM_RF5G2_CH1__SPARE__MASK 0x000007ffU +#define RADIO130NM_RF5G2_CH1__SPARE__READ(src) (u_int32_t)(src) & 0x000007ffU +#define RADIO130NM_RF5G2_CH1__SPARE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000007ffU) +#define RADIO130NM_RF5G2_CH1__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define RADIO130NM_RF5G2_CH1__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000007ffU))) + +/* macros for field PDBIR2 */ +#define RADIO130NM_RF5G2_CH1__PDBIR2__SHIFT 11 +#define RADIO130NM_RF5G2_CH1__PDBIR2__WIDTH 3 +#define RADIO130NM_RF5G2_CH1__PDBIR2__MASK 0x00003800U +#define RADIO130NM_RF5G2_CH1__PDBIR2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define RADIO130NM_RF5G2_CH1__PDBIR2__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define RADIO130NM_RF5G2_CH1__PDBIR2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define RADIO130NM_RF5G2_CH1__PDBIR2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field PDBIR1 */ +#define RADIO130NM_RF5G2_CH1__PDBIR1__SHIFT 14 +#define RADIO130NM_RF5G2_CH1__PDBIR1__WIDTH 3 +#define RADIO130NM_RF5G2_CH1__PDBIR1__MASK 0x0001c000U +#define RADIO130NM_RF5G2_CH1__PDBIR1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define RADIO130NM_RF5G2_CH1__PDBIR1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define RADIO130NM_RF5G2_CH1__PDBIR1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define RADIO130NM_RF5G2_CH1__PDBIR1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field PDBIRTXPA */ +#define RADIO130NM_RF5G2_CH1__PDBIRTXPA__SHIFT 17 +#define RADIO130NM_RF5G2_CH1__PDBIRTXPA__WIDTH 3 +#define RADIO130NM_RF5G2_CH1__PDBIRTXPA__MASK 0x000e0000U +#define RADIO130NM_RF5G2_CH1__PDBIRTXPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define RADIO130NM_RF5G2_CH1__PDBIRTXPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define RADIO130NM_RF5G2_CH1__PDBIRTXPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define RADIO130NM_RF5G2_CH1__PDBIRTXPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field PDBIRTXMIX */ +#define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__SHIFT 20 +#define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__WIDTH 3 +#define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__MASK 0x00700000U +#define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field RX5_ATB_SEL */ +#define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__SHIFT 23 +#define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__WIDTH 3 +#define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__MASK 0x03800000U +#define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field PDRFVGA5 */ +#define RADIO130NM_RF5G2_CH1__PDRFVGA5__SHIFT 26 +#define RADIO130NM_RF5G2_CH1__PDRFVGA5__WIDTH 1 +#define RADIO130NM_RF5G2_CH1__PDRFVGA5__MASK 0x04000000U +#define RADIO130NM_RF5G2_CH1__PDRFVGA5__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO130NM_RF5G2_CH1__PDRFVGA5__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO130NM_RF5G2_CH1__PDRFVGA5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO130NM_RF5G2_CH1__PDRFVGA5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO130NM_RF5G2_CH1__PDRFVGA5__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RADIO130NM_RF5G2_CH1__PDRFVGA5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field PDCSLNA5 */ +#define RADIO130NM_RF5G2_CH1__PDCSLNA5__SHIFT 27 +#define RADIO130NM_RF5G2_CH1__PDCSLNA5__WIDTH 1 +#define RADIO130NM_RF5G2_CH1__PDCSLNA5__MASK 0x08000000U +#define RADIO130NM_RF5G2_CH1__PDCSLNA5__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO130NM_RF5G2_CH1__PDCSLNA5__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO130NM_RF5G2_CH1__PDCSLNA5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO130NM_RF5G2_CH1__PDCSLNA5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO130NM_RF5G2_CH1__PDCSLNA5__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADIO130NM_RF5G2_CH1__PDCSLNA5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field PDVGM5 */ +#define RADIO130NM_RF5G2_CH1__PDVGM5__SHIFT 28 +#define RADIO130NM_RF5G2_CH1__PDVGM5__WIDTH 1 +#define RADIO130NM_RF5G2_CH1__PDVGM5__MASK 0x10000000U +#define RADIO130NM_RF5G2_CH1__PDVGM5__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_RF5G2_CH1__PDVGM5__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_RF5G2_CH1__PDVGM5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_RF5G2_CH1__PDVGM5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_RF5G2_CH1__PDVGM5__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_RF5G2_CH1__PDVGM5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PDRXLO5 */ +#define RADIO130NM_RF5G2_CH1__PDRXLO5__SHIFT 29 +#define RADIO130NM_RF5G2_CH1__PDRXLO5__WIDTH 1 +#define RADIO130NM_RF5G2_CH1__PDRXLO5__MASK 0x20000000U +#define RADIO130NM_RF5G2_CH1__PDRXLO5__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_RF5G2_CH1__PDRXLO5__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_RF5G2_CH1__PDRXLO5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_RF5G2_CH1__PDRXLO5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_RF5G2_CH1__PDRXLO5__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_RF5G2_CH1__PDRXLO5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PDREGFE5 */ +#define RADIO130NM_RF5G2_CH1__PDREGFE5__SHIFT 30 +#define RADIO130NM_RF5G2_CH1__PDREGFE5__WIDTH 1 +#define RADIO130NM_RF5G2_CH1__PDREGFE5__MASK 0x40000000U +#define RADIO130NM_RF5G2_CH1__PDREGFE5__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_RF5G2_CH1__PDREGFE5__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_RF5G2_CH1__PDREGFE5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_RF5G2_CH1__PDREGFE5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_RF5G2_CH1__PDREGFE5__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_RF5G2_CH1__PDREGFE5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field REGFE_BYPASS5 */ +#define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__SHIFT 31 +#define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__WIDTH 1 +#define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__MASK 0x80000000U +#define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_RF5G2_CH1__TYPE u_int32_t +#define RADIO130NM_RF5G2_CH1__READ 0xffffffffU +#define RADIO130NM_RF5G2_CH1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RF5G2_CH1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RF5G2_CH1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RF5G2_CH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RF5G3_CH1 */ +#ifndef __RADIO130NM_RF5G3_CH1_MACRO__ +#define __RADIO130NM_RF5G3_CH1_MACRO__ + +/* macros for field SPARE */ +#define RADIO130NM_RF5G3_CH1__SPARE__SHIFT 0 +#define RADIO130NM_RF5G3_CH1__SPARE__WIDTH 5 +#define RADIO130NM_RF5G3_CH1__SPARE__MASK 0x0000001fU +#define RADIO130NM_RF5G3_CH1__SPARE__READ(src) (u_int32_t)(src) & 0x0000001fU +#define RADIO130NM_RF5G3_CH1__SPARE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define RADIO130NM_RF5G3_CH1__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define RADIO130NM_RF5G3_CH1__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field PDBIBCVGM */ +#define RADIO130NM_RF5G3_CH1__PDBIBCVGM__SHIFT 5 +#define RADIO130NM_RF5G3_CH1__PDBIBCVGM__WIDTH 3 +#define RADIO130NM_RF5G3_CH1__PDBIBCVGM__MASK 0x000000e0U +#define RADIO130NM_RF5G3_CH1__PDBIBCVGM__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define RADIO130NM_RF5G3_CH1__PDBIBCVGM__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define RADIO130NM_RF5G3_CH1__PDBIBCVGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define RADIO130NM_RF5G3_CH1__PDBIBCVGM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field PDBIBCRFVGA */ +#define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__SHIFT 8 +#define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__WIDTH 3 +#define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__MASK 0x00000700U +#define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field PDBIBCLNA */ +#define RADIO130NM_RF5G3_CH1__PDBIBCLNA__SHIFT 11 +#define RADIO130NM_RF5G3_CH1__PDBIBCLNA__WIDTH 3 +#define RADIO130NM_RF5G3_CH1__PDBIBCLNA__MASK 0x00003800U +#define RADIO130NM_RF5G3_CH1__PDBIBCLNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define RADIO130NM_RF5G3_CH1__PDBIBCLNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define RADIO130NM_RF5G3_CH1__PDBIBCLNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define RADIO130NM_RF5G3_CH1__PDBIBCLNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field PDBIC3 */ +#define RADIO130NM_RF5G3_CH1__PDBIC3__SHIFT 14 +#define RADIO130NM_RF5G3_CH1__PDBIC3__WIDTH 3 +#define RADIO130NM_RF5G3_CH1__PDBIC3__MASK 0x0001c000U +#define RADIO130NM_RF5G3_CH1__PDBIC3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define RADIO130NM_RF5G3_CH1__PDBIC3__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define RADIO130NM_RF5G3_CH1__PDBIC3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define RADIO130NM_RF5G3_CH1__PDBIC3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field PDBIC2 */ +#define RADIO130NM_RF5G3_CH1__PDBIC2__SHIFT 17 +#define RADIO130NM_RF5G3_CH1__PDBIC2__WIDTH 3 +#define RADIO130NM_RF5G3_CH1__PDBIC2__MASK 0x000e0000U +#define RADIO130NM_RF5G3_CH1__PDBIC2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define RADIO130NM_RF5G3_CH1__PDBIC2__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define RADIO130NM_RF5G3_CH1__PDBIC2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define RADIO130NM_RF5G3_CH1__PDBIC2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field PDBIC1 */ +#define RADIO130NM_RF5G3_CH1__PDBIC1__SHIFT 20 +#define RADIO130NM_RF5G3_CH1__PDBIC1__WIDTH 3 +#define RADIO130NM_RF5G3_CH1__PDBIC1__MASK 0x00700000U +#define RADIO130NM_RF5G3_CH1__PDBIC1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RADIO130NM_RF5G3_CH1__PDBIC1__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RADIO130NM_RF5G3_CH1__PDBIC1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RADIO130NM_RF5G3_CH1__PDBIC1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field PDBICTXMIX */ +#define RADIO130NM_RF5G3_CH1__PDBICTXMIX__SHIFT 23 +#define RADIO130NM_RF5G3_CH1__PDBICTXMIX__WIDTH 3 +#define RADIO130NM_RF5G3_CH1__PDBICTXMIX__MASK 0x03800000U +#define RADIO130NM_RF5G3_CH1__PDBICTXMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RADIO130NM_RF5G3_CH1__PDBICTXMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RADIO130NM_RF5G3_CH1__PDBICTXMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RADIO130NM_RF5G3_CH1__PDBICTXMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field PDBICTXPA */ +#define RADIO130NM_RF5G3_CH1__PDBICTXPA__SHIFT 26 +#define RADIO130NM_RF5G3_CH1__PDBICTXPA__WIDTH 3 +#define RADIO130NM_RF5G3_CH1__PDBICTXPA__MASK 0x1c000000U +#define RADIO130NM_RF5G3_CH1__PDBICTXPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define RADIO130NM_RF5G3_CH1__PDBICTXPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define RADIO130NM_RF5G3_CH1__PDBICTXPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RADIO130NM_RF5G3_CH1__PDBICTXPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field PDBICTXBUF */ +#define RADIO130NM_RF5G3_CH1__PDBICTXBUF__SHIFT 29 +#define RADIO130NM_RF5G3_CH1__PDBICTXBUF__WIDTH 3 +#define RADIO130NM_RF5G3_CH1__PDBICTXBUF__MASK 0xe0000000U +#define RADIO130NM_RF5G3_CH1__PDBICTXBUF__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define RADIO130NM_RF5G3_CH1__PDBICTXBUF__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define RADIO130NM_RF5G3_CH1__PDBICTXBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RADIO130NM_RF5G3_CH1__PDBICTXBUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RADIO130NM_RF5G3_CH1__TYPE u_int32_t +#define RADIO130NM_RF5G3_CH1__READ 0xffffffffU +#define RADIO130NM_RF5G3_CH1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RF5G3_CH1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RF5G3_CH1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RF5G3_CH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RXTXBB1_CH0 */ +#ifndef __RADIO130NM_RXTXBB1_CH0_MACRO__ +#define __RADIO130NM_RXTXBB1_CH0_MACRO__ + +/* macros for field PDHIQ */ +#define RADIO130NM_RXTXBB1_CH0__PDHIQ__SHIFT 0 +#define RADIO130NM_RXTXBB1_CH0__PDHIQ__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH0__PDHIQ__MASK 0x00000001U +#define RADIO130NM_RXTXBB1_CH0__PDHIQ__READ(src) (u_int32_t)(src) & 0x00000001U +#define RADIO130NM_RXTXBB1_CH0__PDHIQ__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_RXTXBB1_CH0__PDHIQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_RXTXBB1_CH0__PDHIQ__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_RXTXBB1_CH0__PDHIQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_RXTXBB1_CH0__PDHIQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PDLOQ */ +#define RADIO130NM_RXTXBB1_CH0__PDLOQ__SHIFT 1 +#define RADIO130NM_RXTXBB1_CH0__PDLOQ__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH0__PDLOQ__MASK 0x00000002U +#define RADIO130NM_RXTXBB1_CH0__PDLOQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO130NM_RXTXBB1_CH0__PDLOQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO130NM_RXTXBB1_CH0__PDLOQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO130NM_RXTXBB1_CH0__PDLOQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO130NM_RXTXBB1_CH0__PDLOQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RADIO130NM_RXTXBB1_CH0__PDLOQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field PDOFFSETI2V */ +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__SHIFT 2 +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__MASK 0x00000004U +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field PDOFFSETHIQ */ +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__SHIFT 3 +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__MASK 0x00000008U +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field PDOFFSETLOQ */ +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__SHIFT 4 +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__MASK 0x00000010U +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PDRXTXBB */ +#define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__SHIFT 5 +#define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__MASK 0x00000020U +#define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field PDI2V */ +#define RADIO130NM_RXTXBB1_CH0__PDI2V__SHIFT 6 +#define RADIO130NM_RXTXBB1_CH0__PDI2V__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH0__PDI2V__MASK 0x00000040U +#define RADIO130NM_RXTXBB1_CH0__PDI2V__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO130NM_RXTXBB1_CH0__PDI2V__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO130NM_RXTXBB1_CH0__PDI2V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO130NM_RXTXBB1_CH0__PDI2V__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO130NM_RXTXBB1_CH0__PDI2V__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RADIO130NM_RXTXBB1_CH0__PDI2V__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field PDV2I */ +#define RADIO130NM_RXTXBB1_CH0__PDV2I__SHIFT 7 +#define RADIO130NM_RXTXBB1_CH0__PDV2I__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH0__PDV2I__MASK 0x00000080U +#define RADIO130NM_RXTXBB1_CH0__PDV2I__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO130NM_RXTXBB1_CH0__PDV2I__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO130NM_RXTXBB1_CH0__PDV2I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO130NM_RXTXBB1_CH0__PDV2I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO130NM_RXTXBB1_CH0__PDV2I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RADIO130NM_RXTXBB1_CH0__PDV2I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field PDDACINTERFACE */ +#define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__SHIFT 8 +#define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__WIDTH 1 +#define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__MASK 0x00000100U +#define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field SEL_ATB */ +#define RADIO130NM_RXTXBB1_CH0__SEL_ATB__SHIFT 9 +#define RADIO130NM_RXTXBB1_CH0__SEL_ATB__WIDTH 8 +#define RADIO130NM_RXTXBB1_CH0__SEL_ATB__MASK 0x0001fe00U +#define RADIO130NM_RXTXBB1_CH0__SEL_ATB__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fe00U) >> 9) +#define RADIO130NM_RXTXBB1_CH0__SEL_ATB__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x0001fe00U) +#define RADIO130NM_RXTXBB1_CH0__SEL_ATB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((u_int32_t)(src) <<\ + 9) & 0x0001fe00U) +#define RADIO130NM_RXTXBB1_CH0__SEL_ATB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x0001fe00U))) + +/* macros for field FNOTCH */ +#define RADIO130NM_RXTXBB1_CH0__FNOTCH__SHIFT 17 +#define RADIO130NM_RXTXBB1_CH0__FNOTCH__WIDTH 2 +#define RADIO130NM_RXTXBB1_CH0__FNOTCH__MASK 0x00060000U +#define RADIO130NM_RXTXBB1_CH0__FNOTCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00060000U) >> 17) +#define RADIO130NM_RXTXBB1_CH0__FNOTCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00060000U) +#define RADIO130NM_RXTXBB1_CH0__FNOTCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((u_int32_t)(src) <<\ + 17) & 0x00060000U) +#define RADIO130NM_RXTXBB1_CH0__FNOTCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00060000U))) + +/* macros for field SPARE */ +#define RADIO130NM_RXTXBB1_CH0__SPARE__SHIFT 19 +#define RADIO130NM_RXTXBB1_CH0__SPARE__WIDTH 13 +#define RADIO130NM_RXTXBB1_CH0__SPARE__MASK 0xfff80000U +#define RADIO130NM_RXTXBB1_CH0__SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0xfff80000U) >> 19) +#define RADIO130NM_RXTXBB1_CH0__SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0xfff80000U) +#define RADIO130NM_RXTXBB1_CH0__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfff80000U) | (((u_int32_t)(src) <<\ + 19) & 0xfff80000U) +#define RADIO130NM_RXTXBB1_CH0__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0xfff80000U))) +#define RADIO130NM_RXTXBB1_CH0__TYPE u_int32_t +#define RADIO130NM_RXTXBB1_CH0__READ 0xffffffffU +#define RADIO130NM_RXTXBB1_CH0__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RXTXBB1_CH0_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RXTXBB1_CH0 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RXTXBB1_CH0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RXTXBB2_CH0 */ +#ifndef __RADIO130NM_RXTXBB2_CH0_MACRO__ +#define __RADIO130NM_RXTXBB2_CH0_MACRO__ + +/* macros for field PATH_OVERRIDE */ +#define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__SHIFT 0 +#define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__MASK 0x00000001U +#define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PATH1LOQ_EN */ +#define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__SHIFT 1 +#define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__MASK 0x00000002U +#define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field PATH2LOQ_EN */ +#define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__SHIFT 2 +#define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__MASK 0x00000004U +#define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field PATH3LOQ_EN */ +#define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__SHIFT 3 +#define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__MASK 0x00000008U +#define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field PATH1HIQ_EN */ +#define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__SHIFT 4 +#define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__MASK 0x00000010U +#define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PATH2HIQ_EN */ +#define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__SHIFT 5 +#define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__MASK 0x00000020U +#define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field FILTERDOUBLEBW */ +#define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__SHIFT 6 +#define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__MASK 0x00000040U +#define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field LOCALFILTERTUNING */ +#define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__SHIFT 7 +#define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__MASK 0x00000080U +#define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field FILTERFC */ +#define RADIO130NM_RXTXBB2_CH0__FILTERFC__SHIFT 8 +#define RADIO130NM_RXTXBB2_CH0__FILTERFC__WIDTH 5 +#define RADIO130NM_RXTXBB2_CH0__FILTERFC__MASK 0x00001f00U +#define RADIO130NM_RXTXBB2_CH0__FILTERFC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define RADIO130NM_RXTXBB2_CH0__FILTERFC__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define RADIO130NM_RXTXBB2_CH0__FILTERFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define RADIO130NM_RXTXBB2_CH0__FILTERFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) + +/* macros for field CMSEL */ +#define RADIO130NM_RXTXBB2_CH0__CMSEL__SHIFT 13 +#define RADIO130NM_RXTXBB2_CH0__CMSEL__WIDTH 2 +#define RADIO130NM_RXTXBB2_CH0__CMSEL__MASK 0x00006000U +#define RADIO130NM_RXTXBB2_CH0__CMSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00006000U) >> 13) +#define RADIO130NM_RXTXBB2_CH0__CMSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00006000U) +#define RADIO130NM_RXTXBB2_CH0__CMSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00006000U) | (((u_int32_t)(src) <<\ + 13) & 0x00006000U) +#define RADIO130NM_RXTXBB2_CH0__CMSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00006000U))) + +/* macros for field SEL_I2V_TEST */ +#define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__SHIFT 15 +#define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__MASK 0x00008000U +#define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field SEL_HIQ_TEST */ +#define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__SHIFT 16 +#define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__MASK 0x00010000U +#define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field SEL_LOQ_TEST */ +#define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__SHIFT 17 +#define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__MASK 0x00020000U +#define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field SEL_DAC_TEST */ +#define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__SHIFT 18 +#define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__MASK 0x00040000U +#define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field SELBUFFER */ +#define RADIO130NM_RXTXBB2_CH0__SELBUFFER__SHIFT 19 +#define RADIO130NM_RXTXBB2_CH0__SELBUFFER__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__SELBUFFER__MASK 0x00080000U +#define RADIO130NM_RXTXBB2_CH0__SELBUFFER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define RADIO130NM_RXTXBB2_CH0__SELBUFFER__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define RADIO130NM_RXTXBB2_CH0__SELBUFFER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define RADIO130NM_RXTXBB2_CH0__SELBUFFER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define RADIO130NM_RXTXBB2_CH0__SELBUFFER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define RADIO130NM_RXTXBB2_CH0__SELBUFFER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field SHORTBUFFER */ +#define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__SHIFT 20 +#define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__WIDTH 1 +#define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__MASK 0x00100000U +#define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field SPARE */ +#define RADIO130NM_RXTXBB2_CH0__SPARE__SHIFT 21 +#define RADIO130NM_RXTXBB2_CH0__SPARE__WIDTH 2 +#define RADIO130NM_RXTXBB2_CH0__SPARE__MASK 0x00600000U +#define RADIO130NM_RXTXBB2_CH0__SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00600000U) >> 21) +#define RADIO130NM_RXTXBB2_CH0__SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00600000U) +#define RADIO130NM_RXTXBB2_CH0__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((u_int32_t)(src) <<\ + 21) & 0x00600000U) +#define RADIO130NM_RXTXBB2_CH0__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00600000U))) + +/* macros for field IBN_37P5_OSI2V_CTRL */ +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__SHIFT 23 +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__MASK 0x03800000U +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field IBN_37P5_OSLO_CTRL */ +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__SHIFT 26 +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__MASK 0x1c000000U +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field IBN_37P5_OSHI_CTRL */ +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__SHIFT 29 +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__MASK 0xe0000000U +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RADIO130NM_RXTXBB2_CH0__TYPE u_int32_t +#define RADIO130NM_RXTXBB2_CH0__READ 0xffffffffU +#define RADIO130NM_RXTXBB2_CH0__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RXTXBB2_CH0_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RXTXBB2_CH0 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RXTXBB2_CH0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RXTXBB3_CH0 */ +#ifndef __RADIO130NM_RXTXBB3_CH0_MACRO__ +#define __RADIO130NM_RXTXBB3_CH0_MACRO__ + +/* macros for field IBN_100U_TEST_CTRL */ +#define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__SHIFT 0 +#define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__MASK 0x00000007U +#define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field IBRN_12P5_CM_CTRL */ +#define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__SHIFT 3 +#define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__MASK 0x00000038U +#define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field IBN_25U_LO2_CTRL */ +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__SHIFT 6 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__MASK 0x000001c0U +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001c0U) >> 6) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000001c0U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field IBN_25U_LO1_CTRL */ +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__SHIFT 9 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__MASK 0x00000e00U +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000e00U) >> 9) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field IBN_25U_HI2_CTRL */ +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__SHIFT 12 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__MASK 0x00007000U +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007000U) >> 12) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00007000U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field IBN_25U_HI1_CTRL */ +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__SHIFT 15 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__MASK 0x00038000U +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00038000U) >> 15) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00038000U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field IBN_25U_I2V_CTRL */ +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__SHIFT 18 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__MASK 0x001c0000U +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x001c0000U) >> 18) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x001c0000U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field IBN_25U_BKV2I_CTRL */ +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__SHIFT 21 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__MASK 0x00e00000U +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00e00000U) >> 21) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00e00000U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field IBN_25U_CM_BUFAMP_CTRL */ +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__SHIFT 24 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__WIDTH 3 +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__MASK 0x07000000U +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x07000000U) >> 24) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x07000000U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x07000000U))) + +/* macros for field SPARE */ +#define RADIO130NM_RXTXBB3_CH0__SPARE__SHIFT 27 +#define RADIO130NM_RXTXBB3_CH0__SPARE__WIDTH 5 +#define RADIO130NM_RXTXBB3_CH0__SPARE__MASK 0xf8000000U +#define RADIO130NM_RXTXBB3_CH0__SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define RADIO130NM_RXTXBB3_CH0__SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define RADIO130NM_RXTXBB3_CH0__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define RADIO130NM_RXTXBB3_CH0__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define RADIO130NM_RXTXBB3_CH0__TYPE u_int32_t +#define RADIO130NM_RXTXBB3_CH0__READ 0xffffffffU +#define RADIO130NM_RXTXBB3_CH0__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RXTXBB3_CH0_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RXTXBB3_CH0 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RXTXBB3_CH0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RXTXBB4_CH0 */ +#ifndef __RADIO130NM_RXTXBB4_CH0_MACRO__ +#define __RADIO130NM_RXTXBB4_CH0_MACRO__ + +/* macros for field OFSTCORRI2VQ */ +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__SHIFT 0 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__MASK 0x0000001fU +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field OFSTCORRI2VI */ +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__SHIFT 5 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__MASK 0x000003e0U +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field OFSTCORRLOQ */ +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__SHIFT 10 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__MASK 0x00007c00U +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field OFSTCORRLOI */ +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__SHIFT 15 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__MASK 0x000f8000U +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field OFSTCORRHIQ */ +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__SHIFT 20 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__MASK 0x01f00000U +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field OFSTCORRHII */ +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__SHIFT 25 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__WIDTH 5 +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__MASK 0x3e000000U +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) + +/* macros for field LOCALOFFSET */ +#define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__SHIFT 30 +#define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__WIDTH 1 +#define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__MASK 0x40000000U +#define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field SPARE */ +#define RADIO130NM_RXTXBB4_CH0__SPARE__SHIFT 31 +#define RADIO130NM_RXTXBB4_CH0__SPARE__WIDTH 1 +#define RADIO130NM_RXTXBB4_CH0__SPARE__MASK 0x80000000U +#define RADIO130NM_RXTXBB4_CH0__SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_RXTXBB4_CH0__SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_RXTXBB4_CH0__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_RXTXBB4_CH0__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_RXTXBB4_CH0__SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_RXTXBB4_CH0__SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_RXTXBB4_CH0__TYPE u_int32_t +#define RADIO130NM_RXTXBB4_CH0__READ 0xffffffffU +#define RADIO130NM_RXTXBB4_CH0__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RXTXBB4_CH0_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RXTXBB4_CH0 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RXTXBB4_CH0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RF5G1_CH0 */ +#ifndef __RADIO130NM_RF5G1_CH0_MACRO__ +#define __RADIO130NM_RF5G1_CH0_MACRO__ + +/* macros for field SPARE */ +#define RADIO130NM_RF5G1_CH0__SPARE__SHIFT 0 +#define RADIO130NM_RF5G1_CH0__SPARE__WIDTH 10 +#define RADIO130NM_RF5G1_CH0__SPARE__MASK 0x000003ffU +#define RADIO130NM_RF5G1_CH0__SPARE__READ(src) (u_int32_t)(src) & 0x000003ffU +#define RADIO130NM_RF5G1_CH0__SPARE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define RADIO130NM_RF5G1_CH0__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define RADIO130NM_RF5G1_CH0__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field PDREGLO5 */ +#define RADIO130NM_RF5G1_CH0__PDREGLO5__SHIFT 10 +#define RADIO130NM_RF5G1_CH0__PDREGLO5__WIDTH 1 +#define RADIO130NM_RF5G1_CH0__PDREGLO5__MASK 0x00000400U +#define RADIO130NM_RF5G1_CH0__PDREGLO5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define RADIO130NM_RF5G1_CH0__PDREGLO5__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define RADIO130NM_RF5G1_CH0__PDREGLO5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RADIO130NM_RF5G1_CH0__PDREGLO5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RADIO130NM_RF5G1_CH0__PDREGLO5__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RADIO130NM_RF5G1_CH0__PDREGLO5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field REGLO_BYPASS5 */ +#define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__SHIFT 11 +#define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__WIDTH 1 +#define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__MASK 0x00000800U +#define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field LO5CONTROL */ +#define RADIO130NM_RF5G1_CH0__LO5CONTROL__SHIFT 12 +#define RADIO130NM_RF5G1_CH0__LO5CONTROL__WIDTH 1 +#define RADIO130NM_RF5G1_CH0__LO5CONTROL__MASK 0x00001000U +#define RADIO130NM_RF5G1_CH0__LO5CONTROL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define RADIO130NM_RF5G1_CH0__LO5CONTROL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define RADIO130NM_RF5G1_CH0__LO5CONTROL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define RADIO130NM_RF5G1_CH0__LO5CONTROL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define RADIO130NM_RF5G1_CH0__LO5CONTROL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define RADIO130NM_RF5G1_CH0__LO5CONTROL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field TX5_ATB_SEL */ +#define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__SHIFT 13 +#define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__WIDTH 3 +#define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__MASK 0x0000e000U +#define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000e000U) >> 13) +#define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0000e000U) +#define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0000e000U))) + +/* macros for field OB5 */ +#define RADIO130NM_RF5G1_CH0__OB5__SHIFT 16 +#define RADIO130NM_RF5G1_CH0__OB5__WIDTH 3 +#define RADIO130NM_RF5G1_CH0__OB5__MASK 0x00070000U +#define RADIO130NM_RF5G1_CH0__OB5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define RADIO130NM_RF5G1_CH0__OB5__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define RADIO130NM_RF5G1_CH0__OB5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define RADIO130NM_RF5G1_CH0__OB5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field DB5 */ +#define RADIO130NM_RF5G1_CH0__DB5__SHIFT 19 +#define RADIO130NM_RF5G1_CH0__DB5__WIDTH 3 +#define RADIO130NM_RF5G1_CH0__DB5__MASK 0x00380000U +#define RADIO130NM_RF5G1_CH0__DB5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00380000U) >> 19) +#define RADIO130NM_RF5G1_CH0__DB5__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define RADIO130NM_RF5G1_CH0__DB5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define RADIO130NM_RF5G1_CH0__DB5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field PWDTXPKD */ +#define RADIO130NM_RF5G1_CH0__PWDTXPKD__SHIFT 22 +#define RADIO130NM_RF5G1_CH0__PWDTXPKD__WIDTH 3 +#define RADIO130NM_RF5G1_CH0__PWDTXPKD__MASK 0x01c00000U +#define RADIO130NM_RF5G1_CH0__PWDTXPKD__READ(src) \ + (((u_int32_t)(src)\ + & 0x01c00000U) >> 22) +#define RADIO130NM_RF5G1_CH0__PWDTXPKD__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x01c00000U) +#define RADIO130NM_RF5G1_CH0__PWDTXPKD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x01c00000U) +#define RADIO130NM_RF5G1_CH0__PWDTXPKD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x01c00000U))) + +/* macros for field PACASCBIAS */ +#define RADIO130NM_RF5G1_CH0__PACASCBIAS__SHIFT 25 +#define RADIO130NM_RF5G1_CH0__PACASCBIAS__WIDTH 2 +#define RADIO130NM_RF5G1_CH0__PACASCBIAS__MASK 0x06000000U +#define RADIO130NM_RF5G1_CH0__PACASCBIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define RADIO130NM_RF5G1_CH0__PACASCBIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define RADIO130NM_RF5G1_CH0__PACASCBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define RADIO130NM_RF5G1_CH0__PACASCBIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field PDPAOUT5 */ +#define RADIO130NM_RF5G1_CH0__PDPAOUT5__SHIFT 27 +#define RADIO130NM_RF5G1_CH0__PDPAOUT5__WIDTH 1 +#define RADIO130NM_RF5G1_CH0__PDPAOUT5__MASK 0x08000000U +#define RADIO130NM_RF5G1_CH0__PDPAOUT5__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO130NM_RF5G1_CH0__PDPAOUT5__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO130NM_RF5G1_CH0__PDPAOUT5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO130NM_RF5G1_CH0__PDPAOUT5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO130NM_RF5G1_CH0__PDPAOUT5__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADIO130NM_RF5G1_CH0__PDPAOUT5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field PDPADRV5 */ +#define RADIO130NM_RF5G1_CH0__PDPADRV5__SHIFT 28 +#define RADIO130NM_RF5G1_CH0__PDPADRV5__WIDTH 1 +#define RADIO130NM_RF5G1_CH0__PDPADRV5__MASK 0x10000000U +#define RADIO130NM_RF5G1_CH0__PDPADRV5__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_RF5G1_CH0__PDPADRV5__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_RF5G1_CH0__PDPADRV5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_RF5G1_CH0__PDPADRV5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_RF5G1_CH0__PDPADRV5__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_RF5G1_CH0__PDPADRV5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PDTXBUF5 */ +#define RADIO130NM_RF5G1_CH0__PDTXBUF5__SHIFT 29 +#define RADIO130NM_RF5G1_CH0__PDTXBUF5__WIDTH 1 +#define RADIO130NM_RF5G1_CH0__PDTXBUF5__MASK 0x20000000U +#define RADIO130NM_RF5G1_CH0__PDTXBUF5__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_RF5G1_CH0__PDTXBUF5__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_RF5G1_CH0__PDTXBUF5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_RF5G1_CH0__PDTXBUF5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_RF5G1_CH0__PDTXBUF5__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_RF5G1_CH0__PDTXBUF5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PDTXMIX5 */ +#define RADIO130NM_RF5G1_CH0__PDTXMIX5__SHIFT 30 +#define RADIO130NM_RF5G1_CH0__PDTXMIX5__WIDTH 1 +#define RADIO130NM_RF5G1_CH0__PDTXMIX5__MASK 0x40000000U +#define RADIO130NM_RF5G1_CH0__PDTXMIX5__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_RF5G1_CH0__PDTXMIX5__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_RF5G1_CH0__PDTXMIX5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_RF5G1_CH0__PDTXMIX5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_RF5G1_CH0__PDTXMIX5__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_RF5G1_CH0__PDTXMIX5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PDTXLO5 */ +#define RADIO130NM_RF5G1_CH0__PDTXLO5__SHIFT 31 +#define RADIO130NM_RF5G1_CH0__PDTXLO5__WIDTH 1 +#define RADIO130NM_RF5G1_CH0__PDTXLO5__MASK 0x80000000U +#define RADIO130NM_RF5G1_CH0__PDTXLO5__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_RF5G1_CH0__PDTXLO5__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_RF5G1_CH0__PDTXLO5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_RF5G1_CH0__PDTXLO5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_RF5G1_CH0__PDTXLO5__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_RF5G1_CH0__PDTXLO5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_RF5G1_CH0__TYPE u_int32_t +#define RADIO130NM_RF5G1_CH0__READ 0xffffffffU +#define RADIO130NM_RF5G1_CH0__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RF5G1_CH0_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RF5G1_CH0 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RF5G1_CH0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RF5G2_CH0 */ +#ifndef __RADIO130NM_RF5G2_CH0_MACRO__ +#define __RADIO130NM_RF5G2_CH0_MACRO__ + +/* macros for field SPARE */ +#define RADIO130NM_RF5G2_CH0__SPARE__SHIFT 0 +#define RADIO130NM_RF5G2_CH0__SPARE__WIDTH 11 +#define RADIO130NM_RF5G2_CH0__SPARE__MASK 0x000007ffU +#define RADIO130NM_RF5G2_CH0__SPARE__READ(src) (u_int32_t)(src) & 0x000007ffU +#define RADIO130NM_RF5G2_CH0__SPARE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000007ffU) +#define RADIO130NM_RF5G2_CH0__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define RADIO130NM_RF5G2_CH0__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000007ffU))) + +/* macros for field PDBIR2 */ +#define RADIO130NM_RF5G2_CH0__PDBIR2__SHIFT 11 +#define RADIO130NM_RF5G2_CH0__PDBIR2__WIDTH 3 +#define RADIO130NM_RF5G2_CH0__PDBIR2__MASK 0x00003800U +#define RADIO130NM_RF5G2_CH0__PDBIR2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define RADIO130NM_RF5G2_CH0__PDBIR2__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define RADIO130NM_RF5G2_CH0__PDBIR2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define RADIO130NM_RF5G2_CH0__PDBIR2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field PDBIR1 */ +#define RADIO130NM_RF5G2_CH0__PDBIR1__SHIFT 14 +#define RADIO130NM_RF5G2_CH0__PDBIR1__WIDTH 3 +#define RADIO130NM_RF5G2_CH0__PDBIR1__MASK 0x0001c000U +#define RADIO130NM_RF5G2_CH0__PDBIR1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define RADIO130NM_RF5G2_CH0__PDBIR1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define RADIO130NM_RF5G2_CH0__PDBIR1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define RADIO130NM_RF5G2_CH0__PDBIR1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field PDBIRTXPA */ +#define RADIO130NM_RF5G2_CH0__PDBIRTXPA__SHIFT 17 +#define RADIO130NM_RF5G2_CH0__PDBIRTXPA__WIDTH 3 +#define RADIO130NM_RF5G2_CH0__PDBIRTXPA__MASK 0x000e0000U +#define RADIO130NM_RF5G2_CH0__PDBIRTXPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define RADIO130NM_RF5G2_CH0__PDBIRTXPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define RADIO130NM_RF5G2_CH0__PDBIRTXPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define RADIO130NM_RF5G2_CH0__PDBIRTXPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field PDBIRTXMIX */ +#define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__SHIFT 20 +#define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__WIDTH 3 +#define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__MASK 0x00700000U +#define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field RX5_ATB_SEL */ +#define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__SHIFT 23 +#define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__WIDTH 3 +#define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__MASK 0x03800000U +#define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field PDRFVGA5 */ +#define RADIO130NM_RF5G2_CH0__PDRFVGA5__SHIFT 26 +#define RADIO130NM_RF5G2_CH0__PDRFVGA5__WIDTH 1 +#define RADIO130NM_RF5G2_CH0__PDRFVGA5__MASK 0x04000000U +#define RADIO130NM_RF5G2_CH0__PDRFVGA5__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO130NM_RF5G2_CH0__PDRFVGA5__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO130NM_RF5G2_CH0__PDRFVGA5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO130NM_RF5G2_CH0__PDRFVGA5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO130NM_RF5G2_CH0__PDRFVGA5__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RADIO130NM_RF5G2_CH0__PDRFVGA5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field PDCSLNA5 */ +#define RADIO130NM_RF5G2_CH0__PDCSLNA5__SHIFT 27 +#define RADIO130NM_RF5G2_CH0__PDCSLNA5__WIDTH 1 +#define RADIO130NM_RF5G2_CH0__PDCSLNA5__MASK 0x08000000U +#define RADIO130NM_RF5G2_CH0__PDCSLNA5__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO130NM_RF5G2_CH0__PDCSLNA5__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO130NM_RF5G2_CH0__PDCSLNA5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO130NM_RF5G2_CH0__PDCSLNA5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO130NM_RF5G2_CH0__PDCSLNA5__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADIO130NM_RF5G2_CH0__PDCSLNA5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field PDVGM5 */ +#define RADIO130NM_RF5G2_CH0__PDVGM5__SHIFT 28 +#define RADIO130NM_RF5G2_CH0__PDVGM5__WIDTH 1 +#define RADIO130NM_RF5G2_CH0__PDVGM5__MASK 0x10000000U +#define RADIO130NM_RF5G2_CH0__PDVGM5__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_RF5G2_CH0__PDVGM5__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_RF5G2_CH0__PDVGM5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_RF5G2_CH0__PDVGM5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_RF5G2_CH0__PDVGM5__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_RF5G2_CH0__PDVGM5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PDRXLO5 */ +#define RADIO130NM_RF5G2_CH0__PDRXLO5__SHIFT 29 +#define RADIO130NM_RF5G2_CH0__PDRXLO5__WIDTH 1 +#define RADIO130NM_RF5G2_CH0__PDRXLO5__MASK 0x20000000U +#define RADIO130NM_RF5G2_CH0__PDRXLO5__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_RF5G2_CH0__PDRXLO5__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_RF5G2_CH0__PDRXLO5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_RF5G2_CH0__PDRXLO5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_RF5G2_CH0__PDRXLO5__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_RF5G2_CH0__PDRXLO5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PDREGFE5 */ +#define RADIO130NM_RF5G2_CH0__PDREGFE5__SHIFT 30 +#define RADIO130NM_RF5G2_CH0__PDREGFE5__WIDTH 1 +#define RADIO130NM_RF5G2_CH0__PDREGFE5__MASK 0x40000000U +#define RADIO130NM_RF5G2_CH0__PDREGFE5__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_RF5G2_CH0__PDREGFE5__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_RF5G2_CH0__PDREGFE5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_RF5G2_CH0__PDREGFE5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_RF5G2_CH0__PDREGFE5__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_RF5G2_CH0__PDREGFE5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field REGFE_BYPASS5 */ +#define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__SHIFT 31 +#define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__WIDTH 1 +#define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__MASK 0x80000000U +#define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_RF5G2_CH0__TYPE u_int32_t +#define RADIO130NM_RF5G2_CH0__READ 0xffffffffU +#define RADIO130NM_RF5G2_CH0__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RF5G2_CH0_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RF5G2_CH0 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RF5G2_CH0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RF5G3_CH0 */ +#ifndef __RADIO130NM_RF5G3_CH0_MACRO__ +#define __RADIO130NM_RF5G3_CH0_MACRO__ + +/* macros for field SPARE */ +#define RADIO130NM_RF5G3_CH0__SPARE__SHIFT 0 +#define RADIO130NM_RF5G3_CH0__SPARE__WIDTH 5 +#define RADIO130NM_RF5G3_CH0__SPARE__MASK 0x0000001fU +#define RADIO130NM_RF5G3_CH0__SPARE__READ(src) (u_int32_t)(src) & 0x0000001fU +#define RADIO130NM_RF5G3_CH0__SPARE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define RADIO130NM_RF5G3_CH0__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define RADIO130NM_RF5G3_CH0__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field PDBIBCVGM */ +#define RADIO130NM_RF5G3_CH0__PDBIBCVGM__SHIFT 5 +#define RADIO130NM_RF5G3_CH0__PDBIBCVGM__WIDTH 3 +#define RADIO130NM_RF5G3_CH0__PDBIBCVGM__MASK 0x000000e0U +#define RADIO130NM_RF5G3_CH0__PDBIBCVGM__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define RADIO130NM_RF5G3_CH0__PDBIBCVGM__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define RADIO130NM_RF5G3_CH0__PDBIBCVGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define RADIO130NM_RF5G3_CH0__PDBIBCVGM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field PDBIBCRFVGA */ +#define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__SHIFT 8 +#define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__WIDTH 3 +#define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__MASK 0x00000700U +#define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field PDBIBCLNA */ +#define RADIO130NM_RF5G3_CH0__PDBIBCLNA__SHIFT 11 +#define RADIO130NM_RF5G3_CH0__PDBIBCLNA__WIDTH 3 +#define RADIO130NM_RF5G3_CH0__PDBIBCLNA__MASK 0x00003800U +#define RADIO130NM_RF5G3_CH0__PDBIBCLNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define RADIO130NM_RF5G3_CH0__PDBIBCLNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define RADIO130NM_RF5G3_CH0__PDBIBCLNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define RADIO130NM_RF5G3_CH0__PDBIBCLNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field PDBIC3 */ +#define RADIO130NM_RF5G3_CH0__PDBIC3__SHIFT 14 +#define RADIO130NM_RF5G3_CH0__PDBIC3__WIDTH 3 +#define RADIO130NM_RF5G3_CH0__PDBIC3__MASK 0x0001c000U +#define RADIO130NM_RF5G3_CH0__PDBIC3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define RADIO130NM_RF5G3_CH0__PDBIC3__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define RADIO130NM_RF5G3_CH0__PDBIC3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define RADIO130NM_RF5G3_CH0__PDBIC3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field PDBIC2 */ +#define RADIO130NM_RF5G3_CH0__PDBIC2__SHIFT 17 +#define RADIO130NM_RF5G3_CH0__PDBIC2__WIDTH 3 +#define RADIO130NM_RF5G3_CH0__PDBIC2__MASK 0x000e0000U +#define RADIO130NM_RF5G3_CH0__PDBIC2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define RADIO130NM_RF5G3_CH0__PDBIC2__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define RADIO130NM_RF5G3_CH0__PDBIC2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define RADIO130NM_RF5G3_CH0__PDBIC2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field PDBIC1 */ +#define RADIO130NM_RF5G3_CH0__PDBIC1__SHIFT 20 +#define RADIO130NM_RF5G3_CH0__PDBIC1__WIDTH 3 +#define RADIO130NM_RF5G3_CH0__PDBIC1__MASK 0x00700000U +#define RADIO130NM_RF5G3_CH0__PDBIC1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RADIO130NM_RF5G3_CH0__PDBIC1__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RADIO130NM_RF5G3_CH0__PDBIC1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RADIO130NM_RF5G3_CH0__PDBIC1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field PDBICTXMIX */ +#define RADIO130NM_RF5G3_CH0__PDBICTXMIX__SHIFT 23 +#define RADIO130NM_RF5G3_CH0__PDBICTXMIX__WIDTH 3 +#define RADIO130NM_RF5G3_CH0__PDBICTXMIX__MASK 0x03800000U +#define RADIO130NM_RF5G3_CH0__PDBICTXMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RADIO130NM_RF5G3_CH0__PDBICTXMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RADIO130NM_RF5G3_CH0__PDBICTXMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RADIO130NM_RF5G3_CH0__PDBICTXMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field PDBICTXPA */ +#define RADIO130NM_RF5G3_CH0__PDBICTXPA__SHIFT 26 +#define RADIO130NM_RF5G3_CH0__PDBICTXPA__WIDTH 3 +#define RADIO130NM_RF5G3_CH0__PDBICTXPA__MASK 0x1c000000U +#define RADIO130NM_RF5G3_CH0__PDBICTXPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define RADIO130NM_RF5G3_CH0__PDBICTXPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define RADIO130NM_RF5G3_CH0__PDBICTXPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RADIO130NM_RF5G3_CH0__PDBICTXPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field PDBICTXBUF */ +#define RADIO130NM_RF5G3_CH0__PDBICTXBUF__SHIFT 29 +#define RADIO130NM_RF5G3_CH0__PDBICTXBUF__WIDTH 3 +#define RADIO130NM_RF5G3_CH0__PDBICTXBUF__MASK 0xe0000000U +#define RADIO130NM_RF5G3_CH0__PDBICTXBUF__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define RADIO130NM_RF5G3_CH0__PDBICTXBUF__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define RADIO130NM_RF5G3_CH0__PDBICTXBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RADIO130NM_RF5G3_CH0__PDBICTXBUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RADIO130NM_RF5G3_CH0__TYPE u_int32_t +#define RADIO130NM_RF5G3_CH0__READ 0xffffffffU +#define RADIO130NM_RF5G3_CH0__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RF5G3_CH0_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RF5G3_CH0 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RF5G3_CH0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RF2G1_CH0 */ +#ifndef __RADIO130NM_RF2G1_CH0_MACRO__ +#define __RADIO130NM_RF2G1_CH0_MACRO__ + +/* macros for field SPARES */ +#define RADIO130NM_RF2G1_CH0__SPARES__SHIFT 0 +#define RADIO130NM_RF2G1_CH0__SPARES__WIDTH 6 +#define RADIO130NM_RF2G1_CH0__SPARES__MASK 0x0000003fU +#define RADIO130NM_RF2G1_CH0__SPARES__READ(src) (u_int32_t)(src) & 0x0000003fU +#define RADIO130NM_RF2G1_CH0__SPARES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define RADIO130NM_RF2G1_CH0__SPARES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define RADIO130NM_RF2G1_CH0__SPARES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field REGLO_BYPASS */ +#define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__SHIFT 6 +#define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__WIDTH 1 +#define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__MASK 0x00000040U +#define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field REGLNA_BYPASS */ +#define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__SHIFT 7 +#define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__WIDTH 1 +#define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__MASK 0x00000080U +#define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field PDIC25U_VGM */ +#define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__SHIFT 8 +#define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__WIDTH 3 +#define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__MASK 0x00000700U +#define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field PACA_SEL */ +#define RADIO130NM_RF2G1_CH0__PACA_SEL__SHIFT 11 +#define RADIO130NM_RF2G1_CH0__PACA_SEL__WIDTH 2 +#define RADIO130NM_RF2G1_CH0__PACA_SEL__MASK 0x00001800U +#define RADIO130NM_RF2G1_CH0__PACA_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001800U) >> 11) +#define RADIO130NM_RF2G1_CH0__PACA_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00001800U) +#define RADIO130NM_RF2G1_CH0__PACA_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define RADIO130NM_RF2G1_CH0__PACA_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field LOCONTROL */ +#define RADIO130NM_RF2G1_CH0__LOCONTROL__SHIFT 13 +#define RADIO130NM_RF2G1_CH0__LOCONTROL__WIDTH 1 +#define RADIO130NM_RF2G1_CH0__LOCONTROL__MASK 0x00002000U +#define RADIO130NM_RF2G1_CH0__LOCONTROL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define RADIO130NM_RF2G1_CH0__LOCONTROL__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define RADIO130NM_RF2G1_CH0__LOCONTROL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RADIO130NM_RF2G1_CH0__LOCONTROL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RADIO130NM_RF2G1_CH0__LOCONTROL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RADIO130NM_RF2G1_CH0__LOCONTROL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field TXATB_SEL */ +#define RADIO130NM_RF2G1_CH0__TXATB_SEL__SHIFT 14 +#define RADIO130NM_RF2G1_CH0__TXATB_SEL__WIDTH 3 +#define RADIO130NM_RF2G1_CH0__TXATB_SEL__MASK 0x0001c000U +#define RADIO130NM_RF2G1_CH0__TXATB_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define RADIO130NM_RF2G1_CH0__TXATB_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define RADIO130NM_RF2G1_CH0__TXATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define RADIO130NM_RF2G1_CH0__TXATB_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field RXATB_SEL */ +#define RADIO130NM_RF2G1_CH0__RXATB_SEL__SHIFT 17 +#define RADIO130NM_RF2G1_CH0__RXATB_SEL__WIDTH 3 +#define RADIO130NM_RF2G1_CH0__RXATB_SEL__MASK 0x000e0000U +#define RADIO130NM_RF2G1_CH0__RXATB_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define RADIO130NM_RF2G1_CH0__RXATB_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define RADIO130NM_RF2G1_CH0__RXATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define RADIO130NM_RF2G1_CH0__RXATB_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field LOATB_SEL */ +#define RADIO130NM_RF2G1_CH0__LOATB_SEL__SHIFT 20 +#define RADIO130NM_RF2G1_CH0__LOATB_SEL__WIDTH 3 +#define RADIO130NM_RF2G1_CH0__LOATB_SEL__MASK 0x00700000U +#define RADIO130NM_RF2G1_CH0__LOATB_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RADIO130NM_RF2G1_CH0__LOATB_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RADIO130NM_RF2G1_CH0__LOATB_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RADIO130NM_RF2G1_CH0__LOATB_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field OB */ +#define RADIO130NM_RF2G1_CH0__OB__SHIFT 23 +#define RADIO130NM_RF2G1_CH0__OB__WIDTH 3 +#define RADIO130NM_RF2G1_CH0__OB__MASK 0x03800000U +#define RADIO130NM_RF2G1_CH0__OB__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RADIO130NM_RF2G1_CH0__OB__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RADIO130NM_RF2G1_CH0__OB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RADIO130NM_RF2G1_CH0__OB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field DB */ +#define RADIO130NM_RF2G1_CH0__DB__SHIFT 26 +#define RADIO130NM_RF2G1_CH0__DB__WIDTH 3 +#define RADIO130NM_RF2G1_CH0__DB__MASK 0x1c000000U +#define RADIO130NM_RF2G1_CH0__DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define RADIO130NM_RF2G1_CH0__DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define RADIO130NM_RF2G1_CH0__DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RADIO130NM_RF2G1_CH0__DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field PDIC25U_LNA */ +#define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__SHIFT 29 +#define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__WIDTH 3 +#define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__MASK 0xe0000000U +#define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RADIO130NM_RF2G1_CH0__TYPE u_int32_t +#define RADIO130NM_RF2G1_CH0__READ 0xffffffffU +#define RADIO130NM_RF2G1_CH0__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RF2G1_CH0_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RF2G1_CH0 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RF2G1_CH0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_RF2G2_CH0 */ +#ifndef __RADIO130NM_RF2G2_CH0_MACRO__ +#define __RADIO130NM_RF2G2_CH0_MACRO__ + +/* macros for field PDIR25U_VREGLO */ +#define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__SHIFT 0 +#define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__WIDTH 3 +#define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__MASK 0x00000007U +#define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field PDIC25U_VREGLO */ +#define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__SHIFT 3 +#define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__WIDTH 3 +#define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__MASK 0x00000038U +#define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field PDIC50U_DIV */ +#define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__SHIFT 6 +#define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__WIDTH 3 +#define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__MASK 0x000001c0U +#define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001c0U) >> 6) +#define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000001c0U) +#define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field PDIC25U_RXRF */ +#define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__SHIFT 9 +#define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__WIDTH 3 +#define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__MASK 0x00000e00U +#define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000e00U) >> 9) +#define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field PDIC25U_TXRF */ +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__SHIFT 12 +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__WIDTH 3 +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__MASK 0x00007000U +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007000U) >> 12) +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00007000U) +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field PDIC25U_TXPA */ +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__SHIFT 15 +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__WIDTH 3 +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__MASK 0x00038000U +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00038000U) >> 15) +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00038000U) +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field PDIR25U_TXPA */ +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__SHIFT 18 +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__WIDTH 1 +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__MASK 0x00040000U +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field PDIR25U_TXMIX */ +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__SHIFT 19 +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__WIDTH 3 +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__MASK 0x00380000U +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00380000U) >> 19) +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field PDTXMIX */ +#define RADIO130NM_RF2G2_CH0__PDTXMIX__SHIFT 22 +#define RADIO130NM_RF2G2_CH0__PDTXMIX__WIDTH 1 +#define RADIO130NM_RF2G2_CH0__PDTXMIX__MASK 0x00400000U +#define RADIO130NM_RF2G2_CH0__PDTXMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define RADIO130NM_RF2G2_CH0__PDTXMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define RADIO130NM_RF2G2_CH0__PDTXMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define RADIO130NM_RF2G2_CH0__PDTXMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define RADIO130NM_RF2G2_CH0__PDTXMIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define RADIO130NM_RF2G2_CH0__PDTXMIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field PDTXLO */ +#define RADIO130NM_RF2G2_CH0__PDTXLO__SHIFT 23 +#define RADIO130NM_RF2G2_CH0__PDTXLO__WIDTH 1 +#define RADIO130NM_RF2G2_CH0__PDTXLO__MASK 0x00800000U +#define RADIO130NM_RF2G2_CH0__PDTXLO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define RADIO130NM_RF2G2_CH0__PDTXLO__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define RADIO130NM_RF2G2_CH0__PDTXLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RADIO130NM_RF2G2_CH0__PDTXLO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RADIO130NM_RF2G2_CH0__PDTXLO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RADIO130NM_RF2G2_CH0__PDTXLO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field PDRXLO */ +#define RADIO130NM_RF2G2_CH0__PDRXLO__SHIFT 24 +#define RADIO130NM_RF2G2_CH0__PDRXLO__WIDTH 1 +#define RADIO130NM_RF2G2_CH0__PDRXLO__MASK 0x01000000U +#define RADIO130NM_RF2G2_CH0__PDRXLO__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO130NM_RF2G2_CH0__PDRXLO__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RADIO130NM_RF2G2_CH0__PDRXLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RADIO130NM_RF2G2_CH0__PDRXLO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RADIO130NM_RF2G2_CH0__PDRXLO__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RADIO130NM_RF2G2_CH0__PDRXLO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field PDVGM */ +#define RADIO130NM_RF2G2_CH0__PDVGM__SHIFT 25 +#define RADIO130NM_RF2G2_CH0__PDVGM__WIDTH 1 +#define RADIO130NM_RF2G2_CH0__PDVGM__MASK 0x02000000U +#define RADIO130NM_RF2G2_CH0__PDVGM__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define RADIO130NM_RF2G2_CH0__PDVGM__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define RADIO130NM_RF2G2_CH0__PDVGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RADIO130NM_RF2G2_CH0__PDVGM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RADIO130NM_RF2G2_CH0__PDVGM__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RADIO130NM_RF2G2_CH0__PDVGM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field PDREGLO */ +#define RADIO130NM_RF2G2_CH0__PDREGLO__SHIFT 26 +#define RADIO130NM_RF2G2_CH0__PDREGLO__WIDTH 1 +#define RADIO130NM_RF2G2_CH0__PDREGLO__MASK 0x04000000U +#define RADIO130NM_RF2G2_CH0__PDREGLO__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO130NM_RF2G2_CH0__PDREGLO__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO130NM_RF2G2_CH0__PDREGLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO130NM_RF2G2_CH0__PDREGLO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO130NM_RF2G2_CH0__PDREGLO__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RADIO130NM_RF2G2_CH0__PDREGLO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field PDREGLNA */ +#define RADIO130NM_RF2G2_CH0__PDREGLNA__SHIFT 27 +#define RADIO130NM_RF2G2_CH0__PDREGLNA__WIDTH 1 +#define RADIO130NM_RF2G2_CH0__PDREGLNA__MASK 0x08000000U +#define RADIO130NM_RF2G2_CH0__PDREGLNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO130NM_RF2G2_CH0__PDREGLNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO130NM_RF2G2_CH0__PDREGLNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO130NM_RF2G2_CH0__PDREGLNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO130NM_RF2G2_CH0__PDREGLNA__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADIO130NM_RF2G2_CH0__PDREGLNA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field PDPAOUT */ +#define RADIO130NM_RF2G2_CH0__PDPAOUT__SHIFT 28 +#define RADIO130NM_RF2G2_CH0__PDPAOUT__WIDTH 1 +#define RADIO130NM_RF2G2_CH0__PDPAOUT__MASK 0x10000000U +#define RADIO130NM_RF2G2_CH0__PDPAOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_RF2G2_CH0__PDPAOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_RF2G2_CH0__PDPAOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_RF2G2_CH0__PDPAOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_RF2G2_CH0__PDPAOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_RF2G2_CH0__PDPAOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PDPADRV */ +#define RADIO130NM_RF2G2_CH0__PDPADRV__SHIFT 29 +#define RADIO130NM_RF2G2_CH0__PDPADRV__WIDTH 1 +#define RADIO130NM_RF2G2_CH0__PDPADRV__MASK 0x20000000U +#define RADIO130NM_RF2G2_CH0__PDPADRV__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_RF2G2_CH0__PDPADRV__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_RF2G2_CH0__PDPADRV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_RF2G2_CH0__PDPADRV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_RF2G2_CH0__PDPADRV__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_RF2G2_CH0__PDPADRV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PDDIV */ +#define RADIO130NM_RF2G2_CH0__PDDIV__SHIFT 30 +#define RADIO130NM_RF2G2_CH0__PDDIV__WIDTH 1 +#define RADIO130NM_RF2G2_CH0__PDDIV__MASK 0x40000000U +#define RADIO130NM_RF2G2_CH0__PDDIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_RF2G2_CH0__PDDIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_RF2G2_CH0__PDDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_RF2G2_CH0__PDDIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_RF2G2_CH0__PDDIV__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_RF2G2_CH0__PDDIV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PDLNA */ +#define RADIO130NM_RF2G2_CH0__PDLNA__SHIFT 31 +#define RADIO130NM_RF2G2_CH0__PDLNA__WIDTH 1 +#define RADIO130NM_RF2G2_CH0__PDLNA__MASK 0x80000000U +#define RADIO130NM_RF2G2_CH0__PDLNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_RF2G2_CH0__PDLNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_RF2G2_CH0__PDLNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_RF2G2_CH0__PDLNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_RF2G2_CH0__PDLNA__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_RF2G2_CH0__PDLNA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_RF2G2_CH0__TYPE u_int32_t +#define RADIO130NM_RF2G2_CH0__READ 0xffffffffU +#define RADIO130NM_RF2G2_CH0__WRITE 0xffffffffU + +#endif /* __RADIO130NM_RF2G2_CH0_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.RF2G2_CH0 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__RF2G2_CH0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_SYNTH1 */ +#ifndef __RADIO130NM_SYNTH1_MACRO__ +#define __RADIO130NM_SYNTH1_MACRO__ + +/* macros for field SEL_VCMONABUS */ +#define RADIO130NM_SYNTH1__SEL_VCMONABUS__SHIFT 0 +#define RADIO130NM_SYNTH1__SEL_VCMONABUS__WIDTH 3 +#define RADIO130NM_SYNTH1__SEL_VCMONABUS__MASK 0x00000007U +#define RADIO130NM_SYNTH1__SEL_VCMONABUS__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define RADIO130NM_SYNTH1__SEL_VCMONABUS__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define RADIO130NM_SYNTH1__SEL_VCMONABUS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define RADIO130NM_SYNTH1__SEL_VCMONABUS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field CON_IVCOBUF */ +#define RADIO130NM_SYNTH1__CON_IVCOBUF__SHIFT 3 +#define RADIO130NM_SYNTH1__CON_IVCOBUF__WIDTH 1 +#define RADIO130NM_SYNTH1__CON_IVCOBUF__MASK 0x00000008U +#define RADIO130NM_SYNTH1__CON_IVCOBUF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO130NM_SYNTH1__CON_IVCOBUF__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO130NM_SYNTH1__CON_IVCOBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO130NM_SYNTH1__CON_IVCOBUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO130NM_SYNTH1__CON_IVCOBUF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RADIO130NM_SYNTH1__CON_IVCOBUF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field CON_IVCOREG */ +#define RADIO130NM_SYNTH1__CON_IVCOREG__SHIFT 4 +#define RADIO130NM_SYNTH1__CON_IVCOREG__WIDTH 1 +#define RADIO130NM_SYNTH1__CON_IVCOREG__MASK 0x00000010U +#define RADIO130NM_SYNTH1__CON_IVCOREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO130NM_SYNTH1__CON_IVCOREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO130NM_SYNTH1__CON_IVCOREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO130NM_SYNTH1__CON_IVCOREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO130NM_SYNTH1__CON_IVCOREG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RADIO130NM_SYNTH1__CON_IVCOREG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field CON_VDDVCOREG */ +#define RADIO130NM_SYNTH1__CON_VDDVCOREG__SHIFT 5 +#define RADIO130NM_SYNTH1__CON_VDDVCOREG__WIDTH 1 +#define RADIO130NM_SYNTH1__CON_VDDVCOREG__MASK 0x00000020U +#define RADIO130NM_SYNTH1__CON_VDDVCOREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO130NM_SYNTH1__CON_VDDVCOREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO130NM_SYNTH1__CON_VDDVCOREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO130NM_SYNTH1__CON_VDDVCOREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO130NM_SYNTH1__CON_VDDVCOREG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RADIO130NM_SYNTH1__CON_VDDVCOREG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field MONITOR_SYNTHLOCKVCOK */ +#define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__SHIFT 6 +#define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__WIDTH 1 +#define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__MASK 0x00000040U +#define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field MONITOR_VC2LOW */ +#define RADIO130NM_SYNTH1__MONITOR_VC2LOW__SHIFT 7 +#define RADIO130NM_SYNTH1__MONITOR_VC2LOW__WIDTH 1 +#define RADIO130NM_SYNTH1__MONITOR_VC2LOW__MASK 0x00000080U +#define RADIO130NM_SYNTH1__MONITOR_VC2LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO130NM_SYNTH1__MONITOR_VC2LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO130NM_SYNTH1__MONITOR_VC2LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO130NM_SYNTH1__MONITOR_VC2LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO130NM_SYNTH1__MONITOR_VC2LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RADIO130NM_SYNTH1__MONITOR_VC2LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field MONITOR_VC2HIGH */ +#define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__SHIFT 8 +#define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__WIDTH 1 +#define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__MASK 0x00000100U +#define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field MONITOR_FB_DIV2 */ +#define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__SHIFT 9 +#define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__WIDTH 1 +#define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__MASK 0x00000200U +#define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field MONITOR_REF */ +#define RADIO130NM_SYNTH1__MONITOR_REF__SHIFT 10 +#define RADIO130NM_SYNTH1__MONITOR_REF__WIDTH 1 +#define RADIO130NM_SYNTH1__MONITOR_REF__MASK 0x00000400U +#define RADIO130NM_SYNTH1__MONITOR_REF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define RADIO130NM_SYNTH1__MONITOR_REF__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define RADIO130NM_SYNTH1__MONITOR_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RADIO130NM_SYNTH1__MONITOR_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RADIO130NM_SYNTH1__MONITOR_REF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RADIO130NM_SYNTH1__MONITOR_REF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field MONITOR_FB */ +#define RADIO130NM_SYNTH1__MONITOR_FB__SHIFT 11 +#define RADIO130NM_SYNTH1__MONITOR_FB__WIDTH 1 +#define RADIO130NM_SYNTH1__MONITOR_FB__MASK 0x00000800U +#define RADIO130NM_SYNTH1__MONITOR_FB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define RADIO130NM_SYNTH1__MONITOR_FB__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define RADIO130NM_SYNTH1__MONITOR_FB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define RADIO130NM_SYNTH1__MONITOR_FB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define RADIO130NM_SYNTH1__MONITOR_FB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define RADIO130NM_SYNTH1__MONITOR_FB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field PWUP_LOMIX_PD */ +#define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__SHIFT 12 +#define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__WIDTH 1 +#define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__MASK 0x00001000U +#define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field PWUP_LODIV_PD */ +#define RADIO130NM_SYNTH1__PWUP_LODIV_PD__SHIFT 13 +#define RADIO130NM_SYNTH1__PWUP_LODIV_PD__WIDTH 1 +#define RADIO130NM_SYNTH1__PWUP_LODIV_PD__MASK 0x00002000U +#define RADIO130NM_SYNTH1__PWUP_LODIV_PD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define RADIO130NM_SYNTH1__PWUP_LODIV_PD__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define RADIO130NM_SYNTH1__PWUP_LODIV_PD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RADIO130NM_SYNTH1__PWUP_LODIV_PD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RADIO130NM_SYNTH1__PWUP_LODIV_PD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RADIO130NM_SYNTH1__PWUP_LODIV_PD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field PWUP_LOBUF5G_PD */ +#define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__SHIFT 14 +#define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__WIDTH 1 +#define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__MASK 0x00004000U +#define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field PWUP_LOBUF2G_PD */ +#define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__SHIFT 15 +#define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__WIDTH 1 +#define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__MASK 0x00008000U +#define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field PWUP_VCOBUF_PD */ +#define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__SHIFT 16 +#define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__WIDTH 1 +#define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__MASK 0x00010000U +#define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field VCOBUFBIAS */ +#define RADIO130NM_SYNTH1__VCOBUFBIAS__SHIFT 17 +#define RADIO130NM_SYNTH1__VCOBUFBIAS__WIDTH 2 +#define RADIO130NM_SYNTH1__VCOBUFBIAS__MASK 0x00060000U +#define RADIO130NM_SYNTH1__VCOBUFBIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00060000U) >> 17) +#define RADIO130NM_SYNTH1__VCOBUFBIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00060000U) +#define RADIO130NM_SYNTH1__VCOBUFBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((u_int32_t)(src) <<\ + 17) & 0x00060000U) +#define RADIO130NM_SYNTH1__VCOBUFBIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00060000U))) + +/* macros for field VCOREGLEVEL */ +#define RADIO130NM_SYNTH1__VCOREGLEVEL__SHIFT 19 +#define RADIO130NM_SYNTH1__VCOREGLEVEL__WIDTH 2 +#define RADIO130NM_SYNTH1__VCOREGLEVEL__MASK 0x00180000U +#define RADIO130NM_SYNTH1__VCOREGLEVEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00180000U) >> 19) +#define RADIO130NM_SYNTH1__VCOREGLEVEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00180000U) +#define RADIO130NM_SYNTH1__VCOREGLEVEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((u_int32_t)(src) <<\ + 19) & 0x00180000U) +#define RADIO130NM_SYNTH1__VCOREGLEVEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00180000U))) + +/* macros for field VCOREGBYPASS */ +#define RADIO130NM_SYNTH1__VCOREGBYPASS__SHIFT 21 +#define RADIO130NM_SYNTH1__VCOREGBYPASS__WIDTH 1 +#define RADIO130NM_SYNTH1__VCOREGBYPASS__MASK 0x00200000U +#define RADIO130NM_SYNTH1__VCOREGBYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define RADIO130NM_SYNTH1__VCOREGBYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define RADIO130NM_SYNTH1__VCOREGBYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define RADIO130NM_SYNTH1__VCOREGBYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define RADIO130NM_SYNTH1__VCOREGBYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define RADIO130NM_SYNTH1__VCOREGBYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field PWUP_LOREF */ +#define RADIO130NM_SYNTH1__PWUP_LOREF__SHIFT 22 +#define RADIO130NM_SYNTH1__PWUP_LOREF__WIDTH 1 +#define RADIO130NM_SYNTH1__PWUP_LOREF__MASK 0x00400000U +#define RADIO130NM_SYNTH1__PWUP_LOREF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define RADIO130NM_SYNTH1__PWUP_LOREF__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define RADIO130NM_SYNTH1__PWUP_LOREF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define RADIO130NM_SYNTH1__PWUP_LOREF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define RADIO130NM_SYNTH1__PWUP_LOREF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define RADIO130NM_SYNTH1__PWUP_LOREF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field PWD_LOMIX */ +#define RADIO130NM_SYNTH1__PWD_LOMIX__SHIFT 23 +#define RADIO130NM_SYNTH1__PWD_LOMIX__WIDTH 1 +#define RADIO130NM_SYNTH1__PWD_LOMIX__MASK 0x00800000U +#define RADIO130NM_SYNTH1__PWD_LOMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define RADIO130NM_SYNTH1__PWD_LOMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define RADIO130NM_SYNTH1__PWD_LOMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RADIO130NM_SYNTH1__PWD_LOMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RADIO130NM_SYNTH1__PWD_LOMIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RADIO130NM_SYNTH1__PWD_LOMIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field PWD_LODIV */ +#define RADIO130NM_SYNTH1__PWD_LODIV__SHIFT 24 +#define RADIO130NM_SYNTH1__PWD_LODIV__WIDTH 1 +#define RADIO130NM_SYNTH1__PWD_LODIV__MASK 0x01000000U +#define RADIO130NM_SYNTH1__PWD_LODIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO130NM_SYNTH1__PWD_LODIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RADIO130NM_SYNTH1__PWD_LODIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RADIO130NM_SYNTH1__PWD_LODIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RADIO130NM_SYNTH1__PWD_LODIV__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RADIO130NM_SYNTH1__PWD_LODIV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field PWD_LOBUF5G */ +#define RADIO130NM_SYNTH1__PWD_LOBUF5G__SHIFT 25 +#define RADIO130NM_SYNTH1__PWD_LOBUF5G__WIDTH 1 +#define RADIO130NM_SYNTH1__PWD_LOBUF5G__MASK 0x02000000U +#define RADIO130NM_SYNTH1__PWD_LOBUF5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define RADIO130NM_SYNTH1__PWD_LOBUF5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define RADIO130NM_SYNTH1__PWD_LOBUF5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RADIO130NM_SYNTH1__PWD_LOBUF5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RADIO130NM_SYNTH1__PWD_LOBUF5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RADIO130NM_SYNTH1__PWD_LOBUF5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field PWD_LOBUF2G */ +#define RADIO130NM_SYNTH1__PWD_LOBUF2G__SHIFT 26 +#define RADIO130NM_SYNTH1__PWD_LOBUF2G__WIDTH 1 +#define RADIO130NM_SYNTH1__PWD_LOBUF2G__MASK 0x04000000U +#define RADIO130NM_SYNTH1__PWD_LOBUF2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO130NM_SYNTH1__PWD_LOBUF2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO130NM_SYNTH1__PWD_LOBUF2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO130NM_SYNTH1__PWD_LOBUF2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO130NM_SYNTH1__PWD_LOBUF2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RADIO130NM_SYNTH1__PWD_LOBUF2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field PWD_PRESC */ +#define RADIO130NM_SYNTH1__PWD_PRESC__SHIFT 27 +#define RADIO130NM_SYNTH1__PWD_PRESC__WIDTH 1 +#define RADIO130NM_SYNTH1__PWD_PRESC__MASK 0x08000000U +#define RADIO130NM_SYNTH1__PWD_PRESC__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO130NM_SYNTH1__PWD_PRESC__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO130NM_SYNTH1__PWD_PRESC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO130NM_SYNTH1__PWD_PRESC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO130NM_SYNTH1__PWD_PRESC__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADIO130NM_SYNTH1__PWD_PRESC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field PWD_VCO */ +#define RADIO130NM_SYNTH1__PWD_VCO__SHIFT 28 +#define RADIO130NM_SYNTH1__PWD_VCO__WIDTH 1 +#define RADIO130NM_SYNTH1__PWD_VCO__MASK 0x10000000U +#define RADIO130NM_SYNTH1__PWD_VCO__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_SYNTH1__PWD_VCO__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_SYNTH1__PWD_VCO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_SYNTH1__PWD_VCO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_SYNTH1__PWD_VCO__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_SYNTH1__PWD_VCO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PWD_VCMON */ +#define RADIO130NM_SYNTH1__PWD_VCMON__SHIFT 29 +#define RADIO130NM_SYNTH1__PWD_VCMON__WIDTH 1 +#define RADIO130NM_SYNTH1__PWD_VCMON__MASK 0x20000000U +#define RADIO130NM_SYNTH1__PWD_VCMON__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_SYNTH1__PWD_VCMON__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_SYNTH1__PWD_VCMON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_SYNTH1__PWD_VCMON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_SYNTH1__PWD_VCMON__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_SYNTH1__PWD_VCMON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PWD_CP */ +#define RADIO130NM_SYNTH1__PWD_CP__SHIFT 30 +#define RADIO130NM_SYNTH1__PWD_CP__WIDTH 1 +#define RADIO130NM_SYNTH1__PWD_CP__MASK 0x40000000U +#define RADIO130NM_SYNTH1__PWD_CP__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_SYNTH1__PWD_CP__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_SYNTH1__PWD_CP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_SYNTH1__PWD_CP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_SYNTH1__PWD_CP__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_SYNTH1__PWD_CP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PWD_BIAS */ +#define RADIO130NM_SYNTH1__PWD_BIAS__SHIFT 31 +#define RADIO130NM_SYNTH1__PWD_BIAS__WIDTH 1 +#define RADIO130NM_SYNTH1__PWD_BIAS__MASK 0x80000000U +#define RADIO130NM_SYNTH1__PWD_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_SYNTH1__PWD_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_SYNTH1__PWD_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_SYNTH1__PWD_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_SYNTH1__PWD_BIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_SYNTH1__PWD_BIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_SYNTH1__TYPE u_int32_t +#define RADIO130NM_SYNTH1__READ 0xffffffffU +#define RADIO130NM_SYNTH1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_SYNTH1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.SYNTH1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__SYNTH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_SYNTH2 */ +#ifndef __RADIO130NM_SYNTH2_MACRO__ +#define __RADIO130NM_SYNTH2_MACRO__ + +/* macros for field CAPRANGE3 */ +#define RADIO130NM_SYNTH2__CAPRANGE3__SHIFT 0 +#define RADIO130NM_SYNTH2__CAPRANGE3__WIDTH 4 +#define RADIO130NM_SYNTH2__CAPRANGE3__MASK 0x0000000fU +#define RADIO130NM_SYNTH2__CAPRANGE3__READ(src) (u_int32_t)(src) & 0x0000000fU +#define RADIO130NM_SYNTH2__CAPRANGE3__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define RADIO130NM_SYNTH2__CAPRANGE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define RADIO130NM_SYNTH2__CAPRANGE3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field CAPRANGE2 */ +#define RADIO130NM_SYNTH2__CAPRANGE2__SHIFT 4 +#define RADIO130NM_SYNTH2__CAPRANGE2__WIDTH 4 +#define RADIO130NM_SYNTH2__CAPRANGE2__MASK 0x000000f0U +#define RADIO130NM_SYNTH2__CAPRANGE2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define RADIO130NM_SYNTH2__CAPRANGE2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define RADIO130NM_SYNTH2__CAPRANGE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define RADIO130NM_SYNTH2__CAPRANGE2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field CAPRANGE1 */ +#define RADIO130NM_SYNTH2__CAPRANGE1__SHIFT 8 +#define RADIO130NM_SYNTH2__CAPRANGE1__WIDTH 4 +#define RADIO130NM_SYNTH2__CAPRANGE1__MASK 0x00000f00U +#define RADIO130NM_SYNTH2__CAPRANGE1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define RADIO130NM_SYNTH2__CAPRANGE1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define RADIO130NM_SYNTH2__CAPRANGE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define RADIO130NM_SYNTH2__CAPRANGE1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field LOOPLEAKCUR */ +#define RADIO130NM_SYNTH2__LOOPLEAKCUR__SHIFT 12 +#define RADIO130NM_SYNTH2__LOOPLEAKCUR__WIDTH 4 +#define RADIO130NM_SYNTH2__LOOPLEAKCUR__MASK 0x0000f000U +#define RADIO130NM_SYNTH2__LOOPLEAKCUR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define RADIO130NM_SYNTH2__LOOPLEAKCUR__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define RADIO130NM_SYNTH2__LOOPLEAKCUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define RADIO130NM_SYNTH2__LOOPLEAKCUR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field CPLOWLK */ +#define RADIO130NM_SYNTH2__CPLOWLK__SHIFT 16 +#define RADIO130NM_SYNTH2__CPLOWLK__WIDTH 1 +#define RADIO130NM_SYNTH2__CPLOWLK__MASK 0x00010000U +#define RADIO130NM_SYNTH2__CPLOWLK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO130NM_SYNTH2__CPLOWLK__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define RADIO130NM_SYNTH2__CPLOWLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define RADIO130NM_SYNTH2__CPLOWLK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define RADIO130NM_SYNTH2__CPLOWLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define RADIO130NM_SYNTH2__CPLOWLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field CPSTEERING_EN_INTN */ +#define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__SHIFT 17 +#define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__WIDTH 1 +#define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__MASK 0x00020000U +#define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field CPBIAS */ +#define RADIO130NM_SYNTH2__CPBIAS__SHIFT 18 +#define RADIO130NM_SYNTH2__CPBIAS__WIDTH 2 +#define RADIO130NM_SYNTH2__CPBIAS__MASK 0x000c0000U +#define RADIO130NM_SYNTH2__CPBIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x000c0000U) >> 18) +#define RADIO130NM_SYNTH2__CPBIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define RADIO130NM_SYNTH2__CPBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define RADIO130NM_SYNTH2__CPBIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field VC_LOW_REF */ +#define RADIO130NM_SYNTH2__VC_LOW_REF__SHIFT 20 +#define RADIO130NM_SYNTH2__VC_LOW_REF__WIDTH 3 +#define RADIO130NM_SYNTH2__VC_LOW_REF__MASK 0x00700000U +#define RADIO130NM_SYNTH2__VC_LOW_REF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RADIO130NM_SYNTH2__VC_LOW_REF__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RADIO130NM_SYNTH2__VC_LOW_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RADIO130NM_SYNTH2__VC_LOW_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field VC_MID_REF */ +#define RADIO130NM_SYNTH2__VC_MID_REF__SHIFT 23 +#define RADIO130NM_SYNTH2__VC_MID_REF__WIDTH 3 +#define RADIO130NM_SYNTH2__VC_MID_REF__MASK 0x03800000U +#define RADIO130NM_SYNTH2__VC_MID_REF__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RADIO130NM_SYNTH2__VC_MID_REF__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RADIO130NM_SYNTH2__VC_MID_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RADIO130NM_SYNTH2__VC_MID_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field VC_HI_REF */ +#define RADIO130NM_SYNTH2__VC_HI_REF__SHIFT 26 +#define RADIO130NM_SYNTH2__VC_HI_REF__WIDTH 3 +#define RADIO130NM_SYNTH2__VC_HI_REF__MASK 0x1c000000U +#define RADIO130NM_SYNTH2__VC_HI_REF__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define RADIO130NM_SYNTH2__VC_HI_REF__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define RADIO130NM_SYNTH2__VC_HI_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RADIO130NM_SYNTH2__VC_HI_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field VC_CAL_REF */ +#define RADIO130NM_SYNTH2__VC_CAL_REF__SHIFT 29 +#define RADIO130NM_SYNTH2__VC_CAL_REF__WIDTH 3 +#define RADIO130NM_SYNTH2__VC_CAL_REF__MASK 0xe0000000U +#define RADIO130NM_SYNTH2__VC_CAL_REF__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define RADIO130NM_SYNTH2__VC_CAL_REF__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define RADIO130NM_SYNTH2__VC_CAL_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RADIO130NM_SYNTH2__VC_CAL_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RADIO130NM_SYNTH2__TYPE u_int32_t +#define RADIO130NM_SYNTH2__READ 0xffffffffU +#define RADIO130NM_SYNTH2__WRITE 0xffffffffU + +#endif /* __RADIO130NM_SYNTH2_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.SYNTH2 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__SYNTH2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_SYNTH3 */ +#ifndef __RADIO130NM_SYNTH3_MACRO__ +#define __RADIO130NM_SYNTH3_MACRO__ + +/* macros for field WAIT_VC_CHECK */ +#define RADIO130NM_SYNTH3__WAIT_VC_CHECK__SHIFT 0 +#define RADIO130NM_SYNTH3__WAIT_VC_CHECK__WIDTH 6 +#define RADIO130NM_SYNTH3__WAIT_VC_CHECK__MASK 0x0000003fU +#define RADIO130NM_SYNTH3__WAIT_VC_CHECK__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define RADIO130NM_SYNTH3__WAIT_VC_CHECK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define RADIO130NM_SYNTH3__WAIT_VC_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define RADIO130NM_SYNTH3__WAIT_VC_CHECK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field WAIT_CAL_LIN */ +#define RADIO130NM_SYNTH3__WAIT_CAL_LIN__SHIFT 6 +#define RADIO130NM_SYNTH3__WAIT_CAL_LIN__WIDTH 6 +#define RADIO130NM_SYNTH3__WAIT_CAL_LIN__MASK 0x00000fc0U +#define RADIO130NM_SYNTH3__WAIT_CAL_LIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define RADIO130NM_SYNTH3__WAIT_CAL_LIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define RADIO130NM_SYNTH3__WAIT_CAL_LIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define RADIO130NM_SYNTH3__WAIT_CAL_LIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field WAIT_CAL_BIN */ +#define RADIO130NM_SYNTH3__WAIT_CAL_BIN__SHIFT 12 +#define RADIO130NM_SYNTH3__WAIT_CAL_BIN__WIDTH 6 +#define RADIO130NM_SYNTH3__WAIT_CAL_BIN__MASK 0x0003f000U +#define RADIO130NM_SYNTH3__WAIT_CAL_BIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define RADIO130NM_SYNTH3__WAIT_CAL_BIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define RADIO130NM_SYNTH3__WAIT_CAL_BIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define RADIO130NM_SYNTH3__WAIT_CAL_BIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field WAIT_PWRUP */ +#define RADIO130NM_SYNTH3__WAIT_PWRUP__SHIFT 18 +#define RADIO130NM_SYNTH3__WAIT_PWRUP__WIDTH 6 +#define RADIO130NM_SYNTH3__WAIT_PWRUP__MASK 0x00fc0000U +#define RADIO130NM_SYNTH3__WAIT_PWRUP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define RADIO130NM_SYNTH3__WAIT_PWRUP__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define RADIO130NM_SYNTH3__WAIT_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define RADIO130NM_SYNTH3__WAIT_PWRUP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field WAIT_SHORTR_PWRUP */ +#define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__SHIFT 24 +#define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__WIDTH 6 +#define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__MASK 0x3f000000U +#define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) + +/* macros for field SEL_CLK_DIV2 */ +#define RADIO130NM_SYNTH3__SEL_CLK_DIV2__SHIFT 30 +#define RADIO130NM_SYNTH3__SEL_CLK_DIV2__WIDTH 1 +#define RADIO130NM_SYNTH3__SEL_CLK_DIV2__MASK 0x40000000U +#define RADIO130NM_SYNTH3__SEL_CLK_DIV2__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_SYNTH3__SEL_CLK_DIV2__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_SYNTH3__SEL_CLK_DIV2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_SYNTH3__SEL_CLK_DIV2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_SYNTH3__SEL_CLK_DIV2__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_SYNTH3__SEL_CLK_DIV2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field DIS_CLK_XTAL */ +#define RADIO130NM_SYNTH3__DIS_CLK_XTAL__SHIFT 31 +#define RADIO130NM_SYNTH3__DIS_CLK_XTAL__WIDTH 1 +#define RADIO130NM_SYNTH3__DIS_CLK_XTAL__MASK 0x80000000U +#define RADIO130NM_SYNTH3__DIS_CLK_XTAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_SYNTH3__DIS_CLK_XTAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_SYNTH3__DIS_CLK_XTAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_SYNTH3__DIS_CLK_XTAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_SYNTH3__DIS_CLK_XTAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_SYNTH3__DIS_CLK_XTAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_SYNTH3__TYPE u_int32_t +#define RADIO130NM_SYNTH3__READ 0xffffffffU +#define RADIO130NM_SYNTH3__WRITE 0xffffffffU + +#endif /* __RADIO130NM_SYNTH3_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.SYNTH3 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__SYNTH3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_SYNTH4 */ +#ifndef __RADIO130NM_SYNTH4_MACRO__ +#define __RADIO130NM_SYNTH4_MACRO__ + +/* macros for field FORCE_SHIFTREG */ +#define RADIO130NM_SYNTH4__FORCE_SHIFTREG__SHIFT 0 +#define RADIO130NM_SYNTH4__FORCE_SHIFTREG__WIDTH 1 +#define RADIO130NM_SYNTH4__FORCE_SHIFTREG__MASK 0x00000001U +#define RADIO130NM_SYNTH4__FORCE_SHIFTREG__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RADIO130NM_SYNTH4__FORCE_SHIFTREG__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_SYNTH4__FORCE_SHIFTREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_SYNTH4__FORCE_SHIFTREG__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_SYNTH4__FORCE_SHIFTREG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_SYNTH4__FORCE_SHIFTREG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LONGSHIFTSEL */ +#define RADIO130NM_SYNTH4__LONGSHIFTSEL__SHIFT 1 +#define RADIO130NM_SYNTH4__LONGSHIFTSEL__WIDTH 1 +#define RADIO130NM_SYNTH4__LONGSHIFTSEL__MASK 0x00000002U +#define RADIO130NM_SYNTH4__LONGSHIFTSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO130NM_SYNTH4__LONGSHIFTSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO130NM_SYNTH4__LONGSHIFTSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO130NM_SYNTH4__LONGSHIFTSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO130NM_SYNTH4__LONGSHIFTSEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RADIO130NM_SYNTH4__LONGSHIFTSEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field LOBUF5GTUNE_OVR */ +#define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__SHIFT 2 +#define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__WIDTH 2 +#define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__MASK 0x0000000cU +#define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field FORCE_LOBUF5GTUNE */ +#define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__SHIFT 4 +#define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__WIDTH 1 +#define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__MASK 0x00000010U +#define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PSCOUNT_FBSEL */ +#define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__SHIFT 5 +#define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__WIDTH 1 +#define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__MASK 0x00000020U +#define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field SDM_DITHER */ +#define RADIO130NM_SYNTH4__SDM_DITHER__SHIFT 6 +#define RADIO130NM_SYNTH4__SDM_DITHER__WIDTH 2 +#define RADIO130NM_SYNTH4__SDM_DITHER__MASK 0x000000c0U +#define RADIO130NM_SYNTH4__SDM_DITHER__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define RADIO130NM_SYNTH4__SDM_DITHER__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define RADIO130NM_SYNTH4__SDM_DITHER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define RADIO130NM_SYNTH4__SDM_DITHER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field SDM_MODE */ +#define RADIO130NM_SYNTH4__SDM_MODE__SHIFT 8 +#define RADIO130NM_SYNTH4__SDM_MODE__WIDTH 1 +#define RADIO130NM_SYNTH4__SDM_MODE__MASK 0x00000100U +#define RADIO130NM_SYNTH4__SDM_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define RADIO130NM_SYNTH4__SDM_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define RADIO130NM_SYNTH4__SDM_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RADIO130NM_SYNTH4__SDM_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RADIO130NM_SYNTH4__SDM_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RADIO130NM_SYNTH4__SDM_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field SDM_DISABLE */ +#define RADIO130NM_SYNTH4__SDM_DISABLE__SHIFT 9 +#define RADIO130NM_SYNTH4__SDM_DISABLE__WIDTH 1 +#define RADIO130NM_SYNTH4__SDM_DISABLE__MASK 0x00000200U +#define RADIO130NM_SYNTH4__SDM_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define RADIO130NM_SYNTH4__SDM_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define RADIO130NM_SYNTH4__SDM_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define RADIO130NM_SYNTH4__SDM_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define RADIO130NM_SYNTH4__SDM_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define RADIO130NM_SYNTH4__SDM_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field RESET_PRESC */ +#define RADIO130NM_SYNTH4__RESET_PRESC__SHIFT 10 +#define RADIO130NM_SYNTH4__RESET_PRESC__WIDTH 1 +#define RADIO130NM_SYNTH4__RESET_PRESC__MASK 0x00000400U +#define RADIO130NM_SYNTH4__RESET_PRESC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define RADIO130NM_SYNTH4__RESET_PRESC__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define RADIO130NM_SYNTH4__RESET_PRESC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RADIO130NM_SYNTH4__RESET_PRESC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RADIO130NM_SYNTH4__RESET_PRESC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RADIO130NM_SYNTH4__RESET_PRESC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field PRESCSEL */ +#define RADIO130NM_SYNTH4__PRESCSEL__SHIFT 11 +#define RADIO130NM_SYNTH4__PRESCSEL__WIDTH 2 +#define RADIO130NM_SYNTH4__PRESCSEL__MASK 0x00001800U +#define RADIO130NM_SYNTH4__PRESCSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001800U) >> 11) +#define RADIO130NM_SYNTH4__PRESCSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00001800U) +#define RADIO130NM_SYNTH4__PRESCSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define RADIO130NM_SYNTH4__PRESCSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field PFD_DISABLE */ +#define RADIO130NM_SYNTH4__PFD_DISABLE__SHIFT 13 +#define RADIO130NM_SYNTH4__PFD_DISABLE__WIDTH 1 +#define RADIO130NM_SYNTH4__PFD_DISABLE__MASK 0x00002000U +#define RADIO130NM_SYNTH4__PFD_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define RADIO130NM_SYNTH4__PFD_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define RADIO130NM_SYNTH4__PFD_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RADIO130NM_SYNTH4__PFD_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RADIO130NM_SYNTH4__PFD_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RADIO130NM_SYNTH4__PFD_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field PFDDELAY_FRACN */ +#define RADIO130NM_SYNTH4__PFDDELAY_FRACN__SHIFT 14 +#define RADIO130NM_SYNTH4__PFDDELAY_FRACN__WIDTH 1 +#define RADIO130NM_SYNTH4__PFDDELAY_FRACN__MASK 0x00004000U +#define RADIO130NM_SYNTH4__PFDDELAY_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RADIO130NM_SYNTH4__PFDDELAY_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RADIO130NM_SYNTH4__PFDDELAY_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RADIO130NM_SYNTH4__PFDDELAY_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RADIO130NM_SYNTH4__PFDDELAY_FRACN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RADIO130NM_SYNTH4__PFDDELAY_FRACN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field FORCE_LO_ON */ +#define RADIO130NM_SYNTH4__FORCE_LO_ON__SHIFT 15 +#define RADIO130NM_SYNTH4__FORCE_LO_ON__WIDTH 1 +#define RADIO130NM_SYNTH4__FORCE_LO_ON__MASK 0x00008000U +#define RADIO130NM_SYNTH4__FORCE_LO_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define RADIO130NM_SYNTH4__FORCE_LO_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define RADIO130NM_SYNTH4__FORCE_LO_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define RADIO130NM_SYNTH4__FORCE_LO_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define RADIO130NM_SYNTH4__FORCE_LO_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define RADIO130NM_SYNTH4__FORCE_LO_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field CLKXTAL_EDGE_SEL */ +#define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__SHIFT 16 +#define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__WIDTH 1 +#define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__MASK 0x00010000U +#define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field VCOCAPPULLUP */ +#define RADIO130NM_SYNTH4__VCOCAPPULLUP__SHIFT 17 +#define RADIO130NM_SYNTH4__VCOCAPPULLUP__WIDTH 1 +#define RADIO130NM_SYNTH4__VCOCAPPULLUP__MASK 0x00020000U +#define RADIO130NM_SYNTH4__VCOCAPPULLUP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO130NM_SYNTH4__VCOCAPPULLUP__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define RADIO130NM_SYNTH4__VCOCAPPULLUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RADIO130NM_SYNTH4__VCOCAPPULLUP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RADIO130NM_SYNTH4__VCOCAPPULLUP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RADIO130NM_SYNTH4__VCOCAPPULLUP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field VCOCAP_OVR */ +#define RADIO130NM_SYNTH4__VCOCAP_OVR__SHIFT 18 +#define RADIO130NM_SYNTH4__VCOCAP_OVR__WIDTH 8 +#define RADIO130NM_SYNTH4__VCOCAP_OVR__MASK 0x03fc0000U +#define RADIO130NM_SYNTH4__VCOCAP_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x03fc0000U) >> 18) +#define RADIO130NM_SYNTH4__VCOCAP_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x03fc0000U) +#define RADIO130NM_SYNTH4__VCOCAP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x03fc0000U) +#define RADIO130NM_SYNTH4__VCOCAP_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x03fc0000U))) + +/* macros for field FORCE_VCOCAP */ +#define RADIO130NM_SYNTH4__FORCE_VCOCAP__SHIFT 26 +#define RADIO130NM_SYNTH4__FORCE_VCOCAP__WIDTH 1 +#define RADIO130NM_SYNTH4__FORCE_VCOCAP__MASK 0x04000000U +#define RADIO130NM_SYNTH4__FORCE_VCOCAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO130NM_SYNTH4__FORCE_VCOCAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO130NM_SYNTH4__FORCE_VCOCAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO130NM_SYNTH4__FORCE_VCOCAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO130NM_SYNTH4__FORCE_VCOCAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RADIO130NM_SYNTH4__FORCE_VCOCAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field FORCE_PINVC */ +#define RADIO130NM_SYNTH4__FORCE_PINVC__SHIFT 27 +#define RADIO130NM_SYNTH4__FORCE_PINVC__WIDTH 1 +#define RADIO130NM_SYNTH4__FORCE_PINVC__MASK 0x08000000U +#define RADIO130NM_SYNTH4__FORCE_PINVC__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO130NM_SYNTH4__FORCE_PINVC__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO130NM_SYNTH4__FORCE_PINVC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO130NM_SYNTH4__FORCE_PINVC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO130NM_SYNTH4__FORCE_PINVC__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADIO130NM_SYNTH4__FORCE_PINVC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field SHORTR_UNTIL_LOCKED */ +#define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__SHIFT 28 +#define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__WIDTH 1 +#define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__MASK 0x10000000U +#define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field ALWAYS_SHORTR */ +#define RADIO130NM_SYNTH4__ALWAYS_SHORTR__SHIFT 29 +#define RADIO130NM_SYNTH4__ALWAYS_SHORTR__WIDTH 1 +#define RADIO130NM_SYNTH4__ALWAYS_SHORTR__MASK 0x20000000U +#define RADIO130NM_SYNTH4__ALWAYS_SHORTR__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_SYNTH4__ALWAYS_SHORTR__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_SYNTH4__ALWAYS_SHORTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_SYNTH4__ALWAYS_SHORTR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_SYNTH4__ALWAYS_SHORTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_SYNTH4__ALWAYS_SHORTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field DIS_LOSTVC */ +#define RADIO130NM_SYNTH4__DIS_LOSTVC__SHIFT 30 +#define RADIO130NM_SYNTH4__DIS_LOSTVC__WIDTH 1 +#define RADIO130NM_SYNTH4__DIS_LOSTVC__MASK 0x40000000U +#define RADIO130NM_SYNTH4__DIS_LOSTVC__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_SYNTH4__DIS_LOSTVC__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_SYNTH4__DIS_LOSTVC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_SYNTH4__DIS_LOSTVC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_SYNTH4__DIS_LOSTVC__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_SYNTH4__DIS_LOSTVC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field DIS_LIN_CAPSEARCH */ +#define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__SHIFT 31 +#define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__WIDTH 1 +#define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__MASK 0x80000000U +#define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_SYNTH4__TYPE u_int32_t +#define RADIO130NM_SYNTH4__READ 0xffffffffU +#define RADIO130NM_SYNTH4__WRITE 0xffffffffU + +#endif /* __RADIO130NM_SYNTH4_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.SYNTH4 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__SYNTH4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_SYNTH5 */ +#ifndef __RADIO130NM_SYNTH5_MACRO__ +#define __RADIO130NM_SYNTH5_MACRO__ + +/* macros for field ICPKCOMP */ +#define RADIO130NM_SYNTH5__ICPKCOMP__SHIFT 0 +#define RADIO130NM_SYNTH5__ICPKCOMP__WIDTH 2 +#define RADIO130NM_SYNTH5__ICPKCOMP__MASK 0x00000003U +#define RADIO130NM_SYNTH5__ICPKCOMP__READ(src) (u_int32_t)(src) & 0x00000003U +#define RADIO130NM_SYNTH5__ICPKCOMP__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define RADIO130NM_SYNTH5__ICPKCOMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define RADIO130NM_SYNTH5__ICPKCOMP__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field ICLOBUF5G */ +#define RADIO130NM_SYNTH5__ICLOBUF5G__SHIFT 2 +#define RADIO130NM_SYNTH5__ICLOBUF5G__WIDTH 3 +#define RADIO130NM_SYNTH5__ICLOBUF5G__MASK 0x0000001cU +#define RADIO130NM_SYNTH5__ICLOBUF5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define RADIO130NM_SYNTH5__ICLOBUF5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define RADIO130NM_SYNTH5__ICLOBUF5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define RADIO130NM_SYNTH5__ICLOBUF5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field ICLOBUF2G */ +#define RADIO130NM_SYNTH5__ICLOBUF2G__SHIFT 5 +#define RADIO130NM_SYNTH5__ICLOBUF2G__WIDTH 3 +#define RADIO130NM_SYNTH5__ICLOBUF2G__MASK 0x000000e0U +#define RADIO130NM_SYNTH5__ICLOBUF2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define RADIO130NM_SYNTH5__ICLOBUF2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define RADIO130NM_SYNTH5__ICLOBUF2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define RADIO130NM_SYNTH5__ICLOBUF2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field ICVCO */ +#define RADIO130NM_SYNTH5__ICVCO__SHIFT 8 +#define RADIO130NM_SYNTH5__ICVCO__WIDTH 3 +#define RADIO130NM_SYNTH5__ICVCO__MASK 0x00000700U +#define RADIO130NM_SYNTH5__ICVCO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define RADIO130NM_SYNTH5__ICVCO__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define RADIO130NM_SYNTH5__ICVCO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define RADIO130NM_SYNTH5__ICVCO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field ICVCOREG */ +#define RADIO130NM_SYNTH5__ICVCOREG__SHIFT 11 +#define RADIO130NM_SYNTH5__ICVCOREG__WIDTH 3 +#define RADIO130NM_SYNTH5__ICVCOREG__MASK 0x00003800U +#define RADIO130NM_SYNTH5__ICVCOREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define RADIO130NM_SYNTH5__ICVCOREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define RADIO130NM_SYNTH5__ICVCOREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define RADIO130NM_SYNTH5__ICVCOREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field ICLOMIX */ +#define RADIO130NM_SYNTH5__ICLOMIX__SHIFT 14 +#define RADIO130NM_SYNTH5__ICLOMIX__WIDTH 3 +#define RADIO130NM_SYNTH5__ICLOMIX__MASK 0x0001c000U +#define RADIO130NM_SYNTH5__ICLOMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define RADIO130NM_SYNTH5__ICLOMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define RADIO130NM_SYNTH5__ICLOMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define RADIO130NM_SYNTH5__ICLOMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field ICLODIV */ +#define RADIO130NM_SYNTH5__ICLODIV__SHIFT 17 +#define RADIO130NM_SYNTH5__ICLODIV__WIDTH 3 +#define RADIO130NM_SYNTH5__ICLODIV__MASK 0x000e0000U +#define RADIO130NM_SYNTH5__ICLODIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define RADIO130NM_SYNTH5__ICLODIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define RADIO130NM_SYNTH5__ICLODIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define RADIO130NM_SYNTH5__ICLODIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field ICPRESC */ +#define RADIO130NM_SYNTH5__ICPRESC__SHIFT 20 +#define RADIO130NM_SYNTH5__ICPRESC__WIDTH 3 +#define RADIO130NM_SYNTH5__ICPRESC__MASK 0x00700000U +#define RADIO130NM_SYNTH5__ICPRESC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RADIO130NM_SYNTH5__ICPRESC__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RADIO130NM_SYNTH5__ICPRESC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RADIO130NM_SYNTH5__ICPRESC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field IRLOPKDET */ +#define RADIO130NM_SYNTH5__IRLOPKDET__SHIFT 23 +#define RADIO130NM_SYNTH5__IRLOPKDET__WIDTH 3 +#define RADIO130NM_SYNTH5__IRLOPKDET__MASK 0x03800000U +#define RADIO130NM_SYNTH5__IRLOPKDET__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RADIO130NM_SYNTH5__IRLOPKDET__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RADIO130NM_SYNTH5__IRLOPKDET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RADIO130NM_SYNTH5__IRLOPKDET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field IRVCMON */ +#define RADIO130NM_SYNTH5__IRVCMON__SHIFT 26 +#define RADIO130NM_SYNTH5__IRVCMON__WIDTH 3 +#define RADIO130NM_SYNTH5__IRVCMON__MASK 0x1c000000U +#define RADIO130NM_SYNTH5__IRVCMON__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define RADIO130NM_SYNTH5__IRVCMON__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define RADIO130NM_SYNTH5__IRVCMON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RADIO130NM_SYNTH5__IRVCMON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field IRCP */ +#define RADIO130NM_SYNTH5__IRCP__SHIFT 29 +#define RADIO130NM_SYNTH5__IRCP__WIDTH 3 +#define RADIO130NM_SYNTH5__IRCP__MASK 0xe0000000U +#define RADIO130NM_SYNTH5__IRCP__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define RADIO130NM_SYNTH5__IRCP__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define RADIO130NM_SYNTH5__IRCP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RADIO130NM_SYNTH5__IRCP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RADIO130NM_SYNTH5__TYPE u_int32_t +#define RADIO130NM_SYNTH5__READ 0xffffffffU +#define RADIO130NM_SYNTH5__WRITE 0xffffffffU + +#endif /* __RADIO130NM_SYNTH5_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.SYNTH5 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__SYNTH5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_SYNTH6 */ +#ifndef __RADIO130NM_SYNTH6_MACRO__ +#define __RADIO130NM_SYNTH6_MACRO__ + +/* macros for field LOBUF5GTUNE */ +#define RADIO130NM_SYNTH6__LOBUF5GTUNE__SHIFT 0 +#define RADIO130NM_SYNTH6__LOBUF5GTUNE__WIDTH 2 +#define RADIO130NM_SYNTH6__LOBUF5GTUNE__MASK 0x00000003U +#define RADIO130NM_SYNTH6__LOBUF5GTUNE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U + +/* macros for field LOOP_IP */ +#define RADIO130NM_SYNTH6__LOOP_IP__SHIFT 2 +#define RADIO130NM_SYNTH6__LOOP_IP__WIDTH 7 +#define RADIO130NM_SYNTH6__LOOP_IP__MASK 0x000001fcU +#define RADIO130NM_SYNTH6__LOOP_IP__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001fcU) >> 2) + +/* macros for field VC2LOW */ +#define RADIO130NM_SYNTH6__VC2LOW__SHIFT 9 +#define RADIO130NM_SYNTH6__VC2LOW__WIDTH 1 +#define RADIO130NM_SYNTH6__VC2LOW__MASK 0x00000200U +#define RADIO130NM_SYNTH6__VC2LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define RADIO130NM_SYNTH6__VC2LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define RADIO130NM_SYNTH6__VC2LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field VC2HIGH */ +#define RADIO130NM_SYNTH6__VC2HIGH__SHIFT 10 +#define RADIO130NM_SYNTH6__VC2HIGH__WIDTH 1 +#define RADIO130NM_SYNTH6__VC2HIGH__MASK 0x00000400U +#define RADIO130NM_SYNTH6__VC2HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define RADIO130NM_SYNTH6__VC2HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RADIO130NM_SYNTH6__VC2HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field RESET_SDM_B */ +#define RADIO130NM_SYNTH6__RESET_SDM_B__SHIFT 11 +#define RADIO130NM_SYNTH6__RESET_SDM_B__WIDTH 1 +#define RADIO130NM_SYNTH6__RESET_SDM_B__MASK 0x00000800U +#define RADIO130NM_SYNTH6__RESET_SDM_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define RADIO130NM_SYNTH6__RESET_SDM_B__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define RADIO130NM_SYNTH6__RESET_SDM_B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field RESET_PSCOUNTERS */ +#define RADIO130NM_SYNTH6__RESET_PSCOUNTERS__SHIFT 12 +#define RADIO130NM_SYNTH6__RESET_PSCOUNTERS__WIDTH 1 +#define RADIO130NM_SYNTH6__RESET_PSCOUNTERS__MASK 0x00001000U +#define RADIO130NM_SYNTH6__RESET_PSCOUNTERS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define RADIO130NM_SYNTH6__RESET_PSCOUNTERS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define RADIO130NM_SYNTH6__RESET_PSCOUNTERS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field RESET_PFD */ +#define RADIO130NM_SYNTH6__RESET_PFD__SHIFT 13 +#define RADIO130NM_SYNTH6__RESET_PFD__WIDTH 1 +#define RADIO130NM_SYNTH6__RESET_PFD__MASK 0x00002000U +#define RADIO130NM_SYNTH6__RESET_PFD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define RADIO130NM_SYNTH6__RESET_PFD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RADIO130NM_SYNTH6__RESET_PFD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field RESET_RFD */ +#define RADIO130NM_SYNTH6__RESET_RFD__SHIFT 14 +#define RADIO130NM_SYNTH6__RESET_RFD__WIDTH 1 +#define RADIO130NM_SYNTH6__RESET_RFD__MASK 0x00004000U +#define RADIO130NM_SYNTH6__RESET_RFD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RADIO130NM_SYNTH6__RESET_RFD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RADIO130NM_SYNTH6__RESET_RFD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field SHORT_R */ +#define RADIO130NM_SYNTH6__SHORT_R__SHIFT 15 +#define RADIO130NM_SYNTH6__SHORT_R__WIDTH 1 +#define RADIO130NM_SYNTH6__SHORT_R__MASK 0x00008000U +#define RADIO130NM_SYNTH6__SHORT_R__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define RADIO130NM_SYNTH6__SHORT_R__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define RADIO130NM_SYNTH6__SHORT_R__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field VCO_CAP_ST */ +#define RADIO130NM_SYNTH6__VCO_CAP_ST__SHIFT 16 +#define RADIO130NM_SYNTH6__VCO_CAP_ST__WIDTH 8 +#define RADIO130NM_SYNTH6__VCO_CAP_ST__MASK 0x00ff0000U +#define RADIO130NM_SYNTH6__VCO_CAP_ST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) + +/* macros for field PIN_VC */ +#define RADIO130NM_SYNTH6__PIN_VC__SHIFT 24 +#define RADIO130NM_SYNTH6__PIN_VC__WIDTH 1 +#define RADIO130NM_SYNTH6__PIN_VC__MASK 0x01000000U +#define RADIO130NM_SYNTH6__PIN_VC__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO130NM_SYNTH6__PIN_VC__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RADIO130NM_SYNTH6__PIN_VC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field SYNTH_LOCK_VC_OK */ +#define RADIO130NM_SYNTH6__SYNTH_LOCK_VC_OK__SHIFT 25 +#define RADIO130NM_SYNTH6__SYNTH_LOCK_VC_OK__WIDTH 1 +#define RADIO130NM_SYNTH6__SYNTH_LOCK_VC_OK__MASK 0x02000000U +#define RADIO130NM_SYNTH6__SYNTH_LOCK_VC_OK__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define RADIO130NM_SYNTH6__SYNTH_LOCK_VC_OK__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RADIO130NM_SYNTH6__SYNTH_LOCK_VC_OK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field CAP_SEARCH */ +#define RADIO130NM_SYNTH6__CAP_SEARCH__SHIFT 26 +#define RADIO130NM_SYNTH6__CAP_SEARCH__WIDTH 1 +#define RADIO130NM_SYNTH6__CAP_SEARCH__MASK 0x04000000U +#define RADIO130NM_SYNTH6__CAP_SEARCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO130NM_SYNTH6__CAP_SEARCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RADIO130NM_SYNTH6__CAP_SEARCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field SYNTH_SM_STATE */ +#define RADIO130NM_SYNTH6__SYNTH_SM_STATE__SHIFT 27 +#define RADIO130NM_SYNTH6__SYNTH_SM_STATE__WIDTH 4 +#define RADIO130NM_SYNTH6__SYNTH_SM_STATE__MASK 0x78000000U +#define RADIO130NM_SYNTH6__SYNTH_SM_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x78000000U) >> 27) + +/* macros for field SYNTH_ON */ +#define RADIO130NM_SYNTH6__SYNTH_ON__SHIFT 31 +#define RADIO130NM_SYNTH6__SYNTH_ON__WIDTH 1 +#define RADIO130NM_SYNTH6__SYNTH_ON__MASK 0x80000000U +#define RADIO130NM_SYNTH6__SYNTH_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_SYNTH6__SYNTH_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_SYNTH6__SYNTH_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_SYNTH6__TYPE u_int32_t +#define RADIO130NM_SYNTH6__READ 0xffffffffU + +#endif /* __RADIO130NM_SYNTH6_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.SYNTH6 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__SYNTH6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_SYNTH7 */ +#ifndef __RADIO130NM_SYNTH7_MACRO__ +#define __RADIO130NM_SYNTH7_MACRO__ + +/* macros for field OVRCHANDECODER */ +#define RADIO130NM_SYNTH7__OVRCHANDECODER__SHIFT 0 +#define RADIO130NM_SYNTH7__OVRCHANDECODER__WIDTH 1 +#define RADIO130NM_SYNTH7__OVRCHANDECODER__MASK 0x00000001U +#define RADIO130NM_SYNTH7__OVRCHANDECODER__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RADIO130NM_SYNTH7__OVRCHANDECODER__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_SYNTH7__OVRCHANDECODER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_SYNTH7__OVRCHANDECODER__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_SYNTH7__OVRCHANDECODER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_SYNTH7__OVRCHANDECODER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field FORCE_FRACLSB */ +#define RADIO130NM_SYNTH7__FORCE_FRACLSB__SHIFT 1 +#define RADIO130NM_SYNTH7__FORCE_FRACLSB__WIDTH 1 +#define RADIO130NM_SYNTH7__FORCE_FRACLSB__MASK 0x00000002U +#define RADIO130NM_SYNTH7__FORCE_FRACLSB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO130NM_SYNTH7__FORCE_FRACLSB__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO130NM_SYNTH7__FORCE_FRACLSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO130NM_SYNTH7__FORCE_FRACLSB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO130NM_SYNTH7__FORCE_FRACLSB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RADIO130NM_SYNTH7__FORCE_FRACLSB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field CHANFRAC */ +#define RADIO130NM_SYNTH7__CHANFRAC__SHIFT 2 +#define RADIO130NM_SYNTH7__CHANFRAC__WIDTH 17 +#define RADIO130NM_SYNTH7__CHANFRAC__MASK 0x0007fffcU +#define RADIO130NM_SYNTH7__CHANFRAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x0007fffcU) >> 2) +#define RADIO130NM_SYNTH7__CHANFRAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0007fffcU) +#define RADIO130NM_SYNTH7__CHANFRAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0007fffcU) +#define RADIO130NM_SYNTH7__CHANFRAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0007fffcU))) + +/* macros for field CHANSEL */ +#define RADIO130NM_SYNTH7__CHANSEL__SHIFT 19 +#define RADIO130NM_SYNTH7__CHANSEL__WIDTH 9 +#define RADIO130NM_SYNTH7__CHANSEL__MASK 0x0ff80000U +#define RADIO130NM_SYNTH7__CHANSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0ff80000U) >> 19) +#define RADIO130NM_SYNTH7__CHANSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x0ff80000U) +#define RADIO130NM_SYNTH7__CHANSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ff80000U) | (((u_int32_t)(src) <<\ + 19) & 0x0ff80000U) +#define RADIO130NM_SYNTH7__CHANSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x0ff80000U))) + +/* macros for field AMODEREFSEL */ +#define RADIO130NM_SYNTH7__AMODEREFSEL__SHIFT 28 +#define RADIO130NM_SYNTH7__AMODEREFSEL__WIDTH 2 +#define RADIO130NM_SYNTH7__AMODEREFSEL__MASK 0x30000000U +#define RADIO130NM_SYNTH7__AMODEREFSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x30000000U) >> 28) +#define RADIO130NM_SYNTH7__AMODEREFSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x30000000U) +#define RADIO130NM_SYNTH7__AMODEREFSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define RADIO130NM_SYNTH7__AMODEREFSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) + +/* macros for field FRACMODE */ +#define RADIO130NM_SYNTH7__FRACMODE__SHIFT 30 +#define RADIO130NM_SYNTH7__FRACMODE__WIDTH 1 +#define RADIO130NM_SYNTH7__FRACMODE__MASK 0x40000000U +#define RADIO130NM_SYNTH7__FRACMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_SYNTH7__FRACMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_SYNTH7__FRACMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_SYNTH7__FRACMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_SYNTH7__FRACMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_SYNTH7__FRACMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field LOADSYNTHCHANNEL */ +#define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__SHIFT 31 +#define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__WIDTH 1 +#define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__MASK 0x80000000U +#define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_SYNTH7__TYPE u_int32_t +#define RADIO130NM_SYNTH7__READ 0xffffffffU +#define RADIO130NM_SYNTH7__WRITE 0xffffffffU + +#endif /* __RADIO130NM_SYNTH7_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.SYNTH7 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__SYNTH7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_SYNTH8 */ +#ifndef __RADIO130NM_SYNTH8_MACRO__ +#define __RADIO130NM_SYNTH8_MACRO__ + +/* macros for field CPSTEERING_EN_FRACN */ +#define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__SHIFT 0 +#define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__WIDTH 1 +#define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__MASK 0x00000001U +#define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LOOP_ICPB */ +#define RADIO130NM_SYNTH8__LOOP_ICPB__SHIFT 1 +#define RADIO130NM_SYNTH8__LOOP_ICPB__WIDTH 7 +#define RADIO130NM_SYNTH8__LOOP_ICPB__MASK 0x000000feU +#define RADIO130NM_SYNTH8__LOOP_ICPB__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000feU) >> 1) +#define RADIO130NM_SYNTH8__LOOP_ICPB__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000000feU) +#define RADIO130NM_SYNTH8__LOOP_ICPB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((u_int32_t)(src) <<\ + 1) & 0x000000feU) +#define RADIO130NM_SYNTH8__LOOP_ICPB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000000feU))) + +/* macros for field LOOP_CSB */ +#define RADIO130NM_SYNTH8__LOOP_CSB__SHIFT 8 +#define RADIO130NM_SYNTH8__LOOP_CSB__WIDTH 4 +#define RADIO130NM_SYNTH8__LOOP_CSB__MASK 0x00000f00U +#define RADIO130NM_SYNTH8__LOOP_CSB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define RADIO130NM_SYNTH8__LOOP_CSB__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define RADIO130NM_SYNTH8__LOOP_CSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define RADIO130NM_SYNTH8__LOOP_CSB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field LOOP_RSB */ +#define RADIO130NM_SYNTH8__LOOP_RSB__SHIFT 12 +#define RADIO130NM_SYNTH8__LOOP_RSB__WIDTH 5 +#define RADIO130NM_SYNTH8__LOOP_RSB__MASK 0x0001f000U +#define RADIO130NM_SYNTH8__LOOP_RSB__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define RADIO130NM_SYNTH8__LOOP_RSB__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define RADIO130NM_SYNTH8__LOOP_RSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define RADIO130NM_SYNTH8__LOOP_RSB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field LOOP_CPB */ +#define RADIO130NM_SYNTH8__LOOP_CPB__SHIFT 17 +#define RADIO130NM_SYNTH8__LOOP_CPB__WIDTH 5 +#define RADIO130NM_SYNTH8__LOOP_CPB__MASK 0x003e0000U +#define RADIO130NM_SYNTH8__LOOP_CPB__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define RADIO130NM_SYNTH8__LOOP_CPB__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define RADIO130NM_SYNTH8__LOOP_CPB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define RADIO130NM_SYNTH8__LOOP_CPB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field LOOP_3RD_ORDER_RB */ +#define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__SHIFT 22 +#define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__WIDTH 5 +#define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__MASK 0x07c00000U +#define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field REFDIVB */ +#define RADIO130NM_SYNTH8__REFDIVB__SHIFT 27 +#define RADIO130NM_SYNTH8__REFDIVB__WIDTH 5 +#define RADIO130NM_SYNTH8__REFDIVB__MASK 0xf8000000U +#define RADIO130NM_SYNTH8__REFDIVB__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define RADIO130NM_SYNTH8__REFDIVB__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define RADIO130NM_SYNTH8__REFDIVB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define RADIO130NM_SYNTH8__REFDIVB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define RADIO130NM_SYNTH8__TYPE u_int32_t +#define RADIO130NM_SYNTH8__READ 0xffffffffU +#define RADIO130NM_SYNTH8__WRITE 0xffffffffU + +#endif /* __RADIO130NM_SYNTH8_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.SYNTH8 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__SYNTH8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_SYNTH9 */ +#ifndef __RADIO130NM_SYNTH9_MACRO__ +#define __RADIO130NM_SYNTH9_MACRO__ + +/* macros for field PFDDELAY_INTN */ +#define RADIO130NM_SYNTH9__PFDDELAY_INTN__SHIFT 0 +#define RADIO130NM_SYNTH9__PFDDELAY_INTN__WIDTH 1 +#define RADIO130NM_SYNTH9__PFDDELAY_INTN__MASK 0x00000001U +#define RADIO130NM_SYNTH9__PFDDELAY_INTN__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RADIO130NM_SYNTH9__PFDDELAY_INTN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_SYNTH9__PFDDELAY_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_SYNTH9__PFDDELAY_INTN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_SYNTH9__PFDDELAY_INTN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_SYNTH9__PFDDELAY_INTN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field SLOPE_ICPA0 */ +#define RADIO130NM_SYNTH9__SLOPE_ICPA0__SHIFT 1 +#define RADIO130NM_SYNTH9__SLOPE_ICPA0__WIDTH 3 +#define RADIO130NM_SYNTH9__SLOPE_ICPA0__MASK 0x0000000eU +#define RADIO130NM_SYNTH9__SLOPE_ICPA0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define RADIO130NM_SYNTH9__SLOPE_ICPA0__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define RADIO130NM_SYNTH9__SLOPE_ICPA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define RADIO130NM_SYNTH9__SLOPE_ICPA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field LOOP_ICPA0 */ +#define RADIO130NM_SYNTH9__LOOP_ICPA0__SHIFT 4 +#define RADIO130NM_SYNTH9__LOOP_ICPA0__WIDTH 4 +#define RADIO130NM_SYNTH9__LOOP_ICPA0__MASK 0x000000f0U +#define RADIO130NM_SYNTH9__LOOP_ICPA0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define RADIO130NM_SYNTH9__LOOP_ICPA0__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define RADIO130NM_SYNTH9__LOOP_ICPA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define RADIO130NM_SYNTH9__LOOP_ICPA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field LOOP_CSA0 */ +#define RADIO130NM_SYNTH9__LOOP_CSA0__SHIFT 8 +#define RADIO130NM_SYNTH9__LOOP_CSA0__WIDTH 4 +#define RADIO130NM_SYNTH9__LOOP_CSA0__MASK 0x00000f00U +#define RADIO130NM_SYNTH9__LOOP_CSA0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define RADIO130NM_SYNTH9__LOOP_CSA0__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define RADIO130NM_SYNTH9__LOOP_CSA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define RADIO130NM_SYNTH9__LOOP_CSA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field LOOP_RSA0 */ +#define RADIO130NM_SYNTH9__LOOP_RSA0__SHIFT 12 +#define RADIO130NM_SYNTH9__LOOP_RSA0__WIDTH 5 +#define RADIO130NM_SYNTH9__LOOP_RSA0__MASK 0x0001f000U +#define RADIO130NM_SYNTH9__LOOP_RSA0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define RADIO130NM_SYNTH9__LOOP_RSA0__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define RADIO130NM_SYNTH9__LOOP_RSA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define RADIO130NM_SYNTH9__LOOP_RSA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field LOOP_CPA0 */ +#define RADIO130NM_SYNTH9__LOOP_CPA0__SHIFT 17 +#define RADIO130NM_SYNTH9__LOOP_CPA0__WIDTH 5 +#define RADIO130NM_SYNTH9__LOOP_CPA0__MASK 0x003e0000U +#define RADIO130NM_SYNTH9__LOOP_CPA0__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define RADIO130NM_SYNTH9__LOOP_CPA0__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define RADIO130NM_SYNTH9__LOOP_CPA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define RADIO130NM_SYNTH9__LOOP_CPA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field LOOP_3RD_ORDER_RA */ +#define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__SHIFT 22 +#define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__WIDTH 5 +#define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__MASK 0x07c00000U +#define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field REFDIVA */ +#define RADIO130NM_SYNTH9__REFDIVA__SHIFT 27 +#define RADIO130NM_SYNTH9__REFDIVA__WIDTH 5 +#define RADIO130NM_SYNTH9__REFDIVA__MASK 0xf8000000U +#define RADIO130NM_SYNTH9__REFDIVA__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define RADIO130NM_SYNTH9__REFDIVA__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define RADIO130NM_SYNTH9__REFDIVA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define RADIO130NM_SYNTH9__REFDIVA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define RADIO130NM_SYNTH9__TYPE u_int32_t +#define RADIO130NM_SYNTH9__READ 0xffffffffU +#define RADIO130NM_SYNTH9__WRITE 0xffffffffU + +#endif /* __RADIO130NM_SYNTH9_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.SYNTH9 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__SYNTH9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_SYNTH10 */ +#ifndef __RADIO130NM_SYNTH10_MACRO__ +#define __RADIO130NM_SYNTH10_MACRO__ + +/* macros for field SPARE */ +#define RADIO130NM_SYNTH10__SPARE__SHIFT 0 +#define RADIO130NM_SYNTH10__SPARE__WIDTH 11 +#define RADIO130NM_SYNTH10__SPARE__MASK 0x000007ffU +#define RADIO130NM_SYNTH10__SPARE__READ(src) (u_int32_t)(src) & 0x000007ffU +#define RADIO130NM_SYNTH10__SPARE__WRITE(src) ((u_int32_t)(src) & 0x000007ffU) +#define RADIO130NM_SYNTH10__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define RADIO130NM_SYNTH10__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000007ffU))) + +/* macros for field SLOPE_ICPA1 */ +#define RADIO130NM_SYNTH10__SLOPE_ICPA1__SHIFT 11 +#define RADIO130NM_SYNTH10__SLOPE_ICPA1__WIDTH 3 +#define RADIO130NM_SYNTH10__SLOPE_ICPA1__MASK 0x00003800U +#define RADIO130NM_SYNTH10__SLOPE_ICPA1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define RADIO130NM_SYNTH10__SLOPE_ICPA1__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define RADIO130NM_SYNTH10__SLOPE_ICPA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define RADIO130NM_SYNTH10__SLOPE_ICPA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field LOOP_ICPA1 */ +#define RADIO130NM_SYNTH10__LOOP_ICPA1__SHIFT 14 +#define RADIO130NM_SYNTH10__LOOP_ICPA1__WIDTH 4 +#define RADIO130NM_SYNTH10__LOOP_ICPA1__MASK 0x0003c000U +#define RADIO130NM_SYNTH10__LOOP_ICPA1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003c000U) >> 14) +#define RADIO130NM_SYNTH10__LOOP_ICPA1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0003c000U) +#define RADIO130NM_SYNTH10__LOOP_ICPA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0003c000U) +#define RADIO130NM_SYNTH10__LOOP_ICPA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0003c000U))) + +/* macros for field LOOP_CSA1 */ +#define RADIO130NM_SYNTH10__LOOP_CSA1__SHIFT 18 +#define RADIO130NM_SYNTH10__LOOP_CSA1__WIDTH 4 +#define RADIO130NM_SYNTH10__LOOP_CSA1__MASK 0x003c0000U +#define RADIO130NM_SYNTH10__LOOP_CSA1__READ(src) \ + (((u_int32_t)(src)\ + & 0x003c0000U) >> 18) +#define RADIO130NM_SYNTH10__LOOP_CSA1__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x003c0000U) +#define RADIO130NM_SYNTH10__LOOP_CSA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x003c0000U) +#define RADIO130NM_SYNTH10__LOOP_CSA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x003c0000U))) + +/* macros for field LOOP_RSA1 */ +#define RADIO130NM_SYNTH10__LOOP_RSA1__SHIFT 22 +#define RADIO130NM_SYNTH10__LOOP_RSA1__WIDTH 5 +#define RADIO130NM_SYNTH10__LOOP_RSA1__MASK 0x07c00000U +#define RADIO130NM_SYNTH10__LOOP_RSA1__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define RADIO130NM_SYNTH10__LOOP_RSA1__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define RADIO130NM_SYNTH10__LOOP_RSA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define RADIO130NM_SYNTH10__LOOP_RSA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field LOOP_CPA1 */ +#define RADIO130NM_SYNTH10__LOOP_CPA1__SHIFT 27 +#define RADIO130NM_SYNTH10__LOOP_CPA1__WIDTH 5 +#define RADIO130NM_SYNTH10__LOOP_CPA1__MASK 0xf8000000U +#define RADIO130NM_SYNTH10__LOOP_CPA1__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define RADIO130NM_SYNTH10__LOOP_CPA1__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define RADIO130NM_SYNTH10__LOOP_CPA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define RADIO130NM_SYNTH10__LOOP_CPA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define RADIO130NM_SYNTH10__TYPE u_int32_t +#define RADIO130NM_SYNTH10__READ 0xffffffffU +#define RADIO130NM_SYNTH10__WRITE 0xffffffffU + +#endif /* __RADIO130NM_SYNTH10_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.SYNTH10 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__SYNTH10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_SYNTH11 */ +#ifndef __RADIO130NM_SYNTH11_MACRO__ +#define __RADIO130NM_SYNTH11_MACRO__ + +/* macros for field SPARE */ +#define RADIO130NM_SYNTH11__SPARE__SHIFT 0 +#define RADIO130NM_SYNTH11__SPARE__WIDTH 5 +#define RADIO130NM_SYNTH11__SPARE__MASK 0x0000001fU +#define RADIO130NM_SYNTH11__SPARE__READ(src) (u_int32_t)(src) & 0x0000001fU +#define RADIO130NM_SYNTH11__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define RADIO130NM_SYNTH11__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define RADIO130NM_SYNTH11__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field FORCE_LOBUF5G_ON */ +#define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__SHIFT 5 +#define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__WIDTH 1 +#define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__MASK 0x00000020U +#define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field LOREFSEL */ +#define RADIO130NM_SYNTH11__LOREFSEL__SHIFT 6 +#define RADIO130NM_SYNTH11__LOREFSEL__WIDTH 2 +#define RADIO130NM_SYNTH11__LOREFSEL__MASK 0x000000c0U +#define RADIO130NM_SYNTH11__LOREFSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define RADIO130NM_SYNTH11__LOREFSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define RADIO130NM_SYNTH11__LOREFSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define RADIO130NM_SYNTH11__LOREFSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field LO2GSEL */ +#define RADIO130NM_SYNTH11__LO2GSEL__SHIFT 8 +#define RADIO130NM_SYNTH11__LO2GSEL__WIDTH 2 +#define RADIO130NM_SYNTH11__LO2GSEL__MASK 0x00000300U +#define RADIO130NM_SYNTH11__LO2GSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define RADIO130NM_SYNTH11__LO2GSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define RADIO130NM_SYNTH11__LO2GSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define RADIO130NM_SYNTH11__LO2GSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field CPSTEERING_MODE */ +#define RADIO130NM_SYNTH11__CPSTEERING_MODE__SHIFT 10 +#define RADIO130NM_SYNTH11__CPSTEERING_MODE__WIDTH 1 +#define RADIO130NM_SYNTH11__CPSTEERING_MODE__MASK 0x00000400U +#define RADIO130NM_SYNTH11__CPSTEERING_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define RADIO130NM_SYNTH11__CPSTEERING_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define RADIO130NM_SYNTH11__CPSTEERING_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RADIO130NM_SYNTH11__CPSTEERING_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RADIO130NM_SYNTH11__CPSTEERING_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RADIO130NM_SYNTH11__CPSTEERING_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field SLOPE_ICPA2 */ +#define RADIO130NM_SYNTH11__SLOPE_ICPA2__SHIFT 11 +#define RADIO130NM_SYNTH11__SLOPE_ICPA2__WIDTH 3 +#define RADIO130NM_SYNTH11__SLOPE_ICPA2__MASK 0x00003800U +#define RADIO130NM_SYNTH11__SLOPE_ICPA2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define RADIO130NM_SYNTH11__SLOPE_ICPA2__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define RADIO130NM_SYNTH11__SLOPE_ICPA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define RADIO130NM_SYNTH11__SLOPE_ICPA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field LOOP_ICPA2 */ +#define RADIO130NM_SYNTH11__LOOP_ICPA2__SHIFT 14 +#define RADIO130NM_SYNTH11__LOOP_ICPA2__WIDTH 4 +#define RADIO130NM_SYNTH11__LOOP_ICPA2__MASK 0x0003c000U +#define RADIO130NM_SYNTH11__LOOP_ICPA2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003c000U) >> 14) +#define RADIO130NM_SYNTH11__LOOP_ICPA2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0003c000U) +#define RADIO130NM_SYNTH11__LOOP_ICPA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0003c000U) +#define RADIO130NM_SYNTH11__LOOP_ICPA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0003c000U))) + +/* macros for field LOOP_CSA2 */ +#define RADIO130NM_SYNTH11__LOOP_CSA2__SHIFT 18 +#define RADIO130NM_SYNTH11__LOOP_CSA2__WIDTH 4 +#define RADIO130NM_SYNTH11__LOOP_CSA2__MASK 0x003c0000U +#define RADIO130NM_SYNTH11__LOOP_CSA2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003c0000U) >> 18) +#define RADIO130NM_SYNTH11__LOOP_CSA2__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x003c0000U) +#define RADIO130NM_SYNTH11__LOOP_CSA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x003c0000U) +#define RADIO130NM_SYNTH11__LOOP_CSA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x003c0000U))) + +/* macros for field LOOP_RSA2 */ +#define RADIO130NM_SYNTH11__LOOP_RSA2__SHIFT 22 +#define RADIO130NM_SYNTH11__LOOP_RSA2__WIDTH 5 +#define RADIO130NM_SYNTH11__LOOP_RSA2__MASK 0x07c00000U +#define RADIO130NM_SYNTH11__LOOP_RSA2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define RADIO130NM_SYNTH11__LOOP_RSA2__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define RADIO130NM_SYNTH11__LOOP_RSA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define RADIO130NM_SYNTH11__LOOP_RSA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field LOOP_CPA2 */ +#define RADIO130NM_SYNTH11__LOOP_CPA2__SHIFT 27 +#define RADIO130NM_SYNTH11__LOOP_CPA2__WIDTH 5 +#define RADIO130NM_SYNTH11__LOOP_CPA2__MASK 0xf8000000U +#define RADIO130NM_SYNTH11__LOOP_CPA2__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define RADIO130NM_SYNTH11__LOOP_CPA2__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define RADIO130NM_SYNTH11__LOOP_CPA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define RADIO130NM_SYNTH11__LOOP_CPA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define RADIO130NM_SYNTH11__TYPE u_int32_t +#define RADIO130NM_SYNTH11__READ 0xffffffffU +#define RADIO130NM_SYNTH11__WRITE 0xffffffffU + +#endif /* __RADIO130NM_SYNTH11_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.SYNTH11 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__SYNTH11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_BIAS1 */ +#ifndef __RADIO130NM_BIAS1_MACRO__ +#define __RADIO130NM_BIAS1_MACRO__ + +/* macros for field PWD_IRPCIE50 */ +#define RADIO130NM_BIAS1__PWD_IRPCIE50__SHIFT 0 +#define RADIO130NM_BIAS1__PWD_IRPCIE50__WIDTH 1 +#define RADIO130NM_BIAS1__PWD_IRPCIE50__MASK 0x00000001U +#define RADIO130NM_BIAS1__PWD_IRPCIE50__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RADIO130NM_BIAS1__PWD_IRPCIE50__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_BIAS1__PWD_IRPCIE50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_BIAS1__PWD_IRPCIE50__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_BIAS1__PWD_IRPCIE50__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_BIAS1__PWD_IRPCIE50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PWD_ICPCIE50 */ +#define RADIO130NM_BIAS1__PWD_ICPCIE50__SHIFT 1 +#define RADIO130NM_BIAS1__PWD_ICPCIE50__WIDTH 1 +#define RADIO130NM_BIAS1__PWD_ICPCIE50__MASK 0x00000002U +#define RADIO130NM_BIAS1__PWD_ICPCIE50__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO130NM_BIAS1__PWD_ICPCIE50__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO130NM_BIAS1__PWD_ICPCIE50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO130NM_BIAS1__PWD_ICPCIE50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO130NM_BIAS1__PWD_ICPCIE50__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RADIO130NM_BIAS1__PWD_ICPCIE50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field PWD_IRPLL25 */ +#define RADIO130NM_BIAS1__PWD_IRPLL25__SHIFT 2 +#define RADIO130NM_BIAS1__PWD_IRPLL25__WIDTH 1 +#define RADIO130NM_BIAS1__PWD_IRPLL25__MASK 0x00000004U +#define RADIO130NM_BIAS1__PWD_IRPLL25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO130NM_BIAS1__PWD_IRPLL25__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RADIO130NM_BIAS1__PWD_IRPLL25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RADIO130NM_BIAS1__PWD_IRPLL25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RADIO130NM_BIAS1__PWD_IRPLL25__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RADIO130NM_BIAS1__PWD_IRPLL25__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field PWD_ICPLL25 */ +#define RADIO130NM_BIAS1__PWD_ICPLL25__SHIFT 3 +#define RADIO130NM_BIAS1__PWD_ICPLL25__WIDTH 1 +#define RADIO130NM_BIAS1__PWD_ICPLL25__MASK 0x00000008U +#define RADIO130NM_BIAS1__PWD_ICPLL25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO130NM_BIAS1__PWD_ICPLL25__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO130NM_BIAS1__PWD_ICPLL25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO130NM_BIAS1__PWD_ICPLL25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO130NM_BIAS1__PWD_ICPLL25__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RADIO130NM_BIAS1__PWD_ICPLL25__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field PWD_IRRXLDO25 */ +#define RADIO130NM_BIAS1__PWD_IRRXLDO25__SHIFT 4 +#define RADIO130NM_BIAS1__PWD_IRRXLDO25__WIDTH 3 +#define RADIO130NM_BIAS1__PWD_IRRXLDO25__MASK 0x00000070U +#define RADIO130NM_BIAS1__PWD_IRRXLDO25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000070U) >> 4) +#define RADIO130NM_BIAS1__PWD_IRRXLDO25__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define RADIO130NM_BIAS1__PWD_IRRXLDO25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define RADIO130NM_BIAS1__PWD_IRRXLDO25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field PWD_ICRXLDO25 */ +#define RADIO130NM_BIAS1__PWD_ICRXLDO25__SHIFT 7 +#define RADIO130NM_BIAS1__PWD_ICRXLDO25__WIDTH 3 +#define RADIO130NM_BIAS1__PWD_ICRXLDO25__MASK 0x00000380U +#define RADIO130NM_BIAS1__PWD_ICRXLDO25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000380U) >> 7) +#define RADIO130NM_BIAS1__PWD_ICRXLDO25__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000380U) +#define RADIO130NM_BIAS1__PWD_ICRXLDO25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((u_int32_t)(src) <<\ + 7) & 0x00000380U) +#define RADIO130NM_BIAS1__PWD_ICRXLDO25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000380U))) + +/* macros for field PWD_IRXPALDO25 */ +#define RADIO130NM_BIAS1__PWD_IRXPALDO25__SHIFT 10 +#define RADIO130NM_BIAS1__PWD_IRXPALDO25__WIDTH 3 +#define RADIO130NM_BIAS1__PWD_IRXPALDO25__MASK 0x00001c00U +#define RADIO130NM_BIAS1__PWD_IRXPALDO25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001c00U) >> 10) +#define RADIO130NM_BIAS1__PWD_IRXPALDO25__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00001c00U) +#define RADIO130NM_BIAS1__PWD_IRXPALDO25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00001c00U) +#define RADIO130NM_BIAS1__PWD_IRXPALDO25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00001c00U))) + +/* macros for field PWD_ICXPALDO25 */ +#define RADIO130NM_BIAS1__PWD_ICXPALDO25__SHIFT 13 +#define RADIO130NM_BIAS1__PWD_ICXPALDO25__WIDTH 3 +#define RADIO130NM_BIAS1__PWD_ICXPALDO25__MASK 0x0000e000U +#define RADIO130NM_BIAS1__PWD_ICXPALDO25__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000e000U) >> 13) +#define RADIO130NM_BIAS1__PWD_ICXPALDO25__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0000e000U) +#define RADIO130NM_BIAS1__PWD_ICXPALDO25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define RADIO130NM_BIAS1__PWD_ICXPALDO25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0000e000U))) + +/* macros for field PWD_IRXTAL25 */ +#define RADIO130NM_BIAS1__PWD_IRXTAL25__SHIFT 16 +#define RADIO130NM_BIAS1__PWD_IRXTAL25__WIDTH 3 +#define RADIO130NM_BIAS1__PWD_IRXTAL25__MASK 0x00070000U +#define RADIO130NM_BIAS1__PWD_IRXTAL25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define RADIO130NM_BIAS1__PWD_IRXTAL25__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define RADIO130NM_BIAS1__PWD_IRXTAL25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define RADIO130NM_BIAS1__PWD_IRXTAL25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field PWD_ICXTAL25 */ +#define RADIO130NM_BIAS1__PWD_ICXTAL25__SHIFT 19 +#define RADIO130NM_BIAS1__PWD_ICXTAL25__WIDTH 3 +#define RADIO130NM_BIAS1__PWD_ICXTAL25__MASK 0x00380000U +#define RADIO130NM_BIAS1__PWD_ICXTAL25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00380000U) >> 19) +#define RADIO130NM_BIAS1__PWD_ICXTAL25__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define RADIO130NM_BIAS1__PWD_ICXTAL25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define RADIO130NM_BIAS1__PWD_ICXTAL25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field BIAS1_SPARE */ +#define RADIO130NM_BIAS1__BIAS1_SPARE__SHIFT 22 +#define RADIO130NM_BIAS1__BIAS1_SPARE__WIDTH 3 +#define RADIO130NM_BIAS1__BIAS1_SPARE__MASK 0x01c00000U +#define RADIO130NM_BIAS1__BIAS1_SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0x01c00000U) >> 22) +#define RADIO130NM_BIAS1__BIAS1_SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x01c00000U) +#define RADIO130NM_BIAS1__BIAS1_SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x01c00000U) +#define RADIO130NM_BIAS1__BIAS1_SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x01c00000U))) + +/* macros for field SEL_BIAS */ +#define RADIO130NM_BIAS1__SEL_BIAS__SHIFT 25 +#define RADIO130NM_BIAS1__SEL_BIAS__WIDTH 6 +#define RADIO130NM_BIAS1__SEL_BIAS__MASK 0x7e000000U +#define RADIO130NM_BIAS1__SEL_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x7e000000U) >> 25) +#define RADIO130NM_BIAS1__SEL_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x7e000000U) +#define RADIO130NM_BIAS1__SEL_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x7e000000U) +#define RADIO130NM_BIAS1__SEL_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x7e000000U))) + +/* macros for field PADON */ +#define RADIO130NM_BIAS1__PADON__SHIFT 31 +#define RADIO130NM_BIAS1__PADON__WIDTH 1 +#define RADIO130NM_BIAS1__PADON__MASK 0x80000000U +#define RADIO130NM_BIAS1__PADON__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_BIAS1__PADON__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_BIAS1__PADON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_BIAS1__PADON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_BIAS1__PADON__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_BIAS1__PADON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_BIAS1__TYPE u_int32_t +#define RADIO130NM_BIAS1__READ 0xffffffffU +#define RADIO130NM_BIAS1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_BIAS1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.BIAS1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__BIAS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_BIAS2 */ +#ifndef __RADIO130NM_BIAS2_MACRO__ +#define __RADIO130NM_BIAS2_MACRO__ + +/* macros for field PWD_ICDAC50 */ +#define RADIO130NM_BIAS2__PWD_ICDAC50__SHIFT 0 +#define RADIO130NM_BIAS2__PWD_ICDAC50__WIDTH 3 +#define RADIO130NM_BIAS2__PWD_ICDAC50__MASK 0x00000007U +#define RADIO130NM_BIAS2__PWD_ICDAC50__READ(src) (u_int32_t)(src) & 0x00000007U +#define RADIO130NM_BIAS2__PWD_ICDAC50__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define RADIO130NM_BIAS2__PWD_ICDAC50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define RADIO130NM_BIAS2__PWD_ICDAC50__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field PWD_IRADCREFMSTRQ12P5 */ +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__SHIFT 3 +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__WIDTH 1 +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__MASK 0x00000008U +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field PWD_IRADCREFMSTRI12P5 */ +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__SHIFT 4 +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__WIDTH 1 +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__MASK 0x00000010U +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PWD_ICADCREFOPAMPQ25 */ +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__SHIFT 5 +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__WIDTH 3 +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__MASK 0x000000e0U +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field PWD_ICADCREFOPAMPI25 */ +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__SHIFT 8 +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__WIDTH 3 +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__MASK 0x00000700U +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field PWD_ICADCREFBUFQ12P5 */ +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__SHIFT 11 +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__WIDTH 3 +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__MASK 0x00003800U +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field PWD_ICADCREFBUFI12P5 */ +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__SHIFT 14 +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__WIDTH 3 +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__MASK 0x0001c000U +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field PWD_ICADCCOMPQ25 */ +#define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__SHIFT 17 +#define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__WIDTH 3 +#define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__MASK 0x000e0000U +#define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field PWD_ICADCCOMPI25 */ +#define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__SHIFT 20 +#define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__WIDTH 3 +#define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__MASK 0x00700000U +#define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field PWD_ICDACINTFACE25 */ +#define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__SHIFT 23 +#define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__WIDTH 1 +#define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__MASK 0x00800000U +#define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field PWD_IRBB50 */ +#define RADIO130NM_BIAS2__PWD_IRBB50__SHIFT 24 +#define RADIO130NM_BIAS2__PWD_IRBB50__WIDTH 1 +#define RADIO130NM_BIAS2__PWD_IRBB50__MASK 0x01000000U +#define RADIO130NM_BIAS2__PWD_IRBB50__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO130NM_BIAS2__PWD_IRBB50__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RADIO130NM_BIAS2__PWD_IRBB50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RADIO130NM_BIAS2__PWD_IRBB50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RADIO130NM_BIAS2__PWD_IRBB50__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RADIO130NM_BIAS2__PWD_IRBB50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field PWD_ICBB50 */ +#define RADIO130NM_BIAS2__PWD_ICBB50__SHIFT 25 +#define RADIO130NM_BIAS2__PWD_ICBB50__WIDTH 1 +#define RADIO130NM_BIAS2__PWD_ICBB50__MASK 0x02000000U +#define RADIO130NM_BIAS2__PWD_ICBB50__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define RADIO130NM_BIAS2__PWD_ICBB50__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define RADIO130NM_BIAS2__PWD_ICBB50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RADIO130NM_BIAS2__PWD_ICBB50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RADIO130NM_BIAS2__PWD_ICBB50__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RADIO130NM_BIAS2__PWD_ICBB50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field PWD_IRRF2G50 */ +#define RADIO130NM_BIAS2__PWD_IRRF2G50__SHIFT 26 +#define RADIO130NM_BIAS2__PWD_IRRF2G50__WIDTH 1 +#define RADIO130NM_BIAS2__PWD_IRRF2G50__MASK 0x04000000U +#define RADIO130NM_BIAS2__PWD_IRRF2G50__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO130NM_BIAS2__PWD_IRRF2G50__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO130NM_BIAS2__PWD_IRRF2G50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO130NM_BIAS2__PWD_IRRF2G50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO130NM_BIAS2__PWD_IRRF2G50__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RADIO130NM_BIAS2__PWD_IRRF2G50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field PWD_IRRF5G50 */ +#define RADIO130NM_BIAS2__PWD_IRRF5G50__SHIFT 27 +#define RADIO130NM_BIAS2__PWD_IRRF5G50__WIDTH 1 +#define RADIO130NM_BIAS2__PWD_IRRF5G50__MASK 0x08000000U +#define RADIO130NM_BIAS2__PWD_IRRF5G50__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO130NM_BIAS2__PWD_IRRF5G50__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO130NM_BIAS2__PWD_IRRF5G50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO130NM_BIAS2__PWD_IRRF5G50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO130NM_BIAS2__PWD_IRRF5G50__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADIO130NM_BIAS2__PWD_IRRF5G50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field PWD_ICRF2G50 */ +#define RADIO130NM_BIAS2__PWD_ICRF2G50__SHIFT 28 +#define RADIO130NM_BIAS2__PWD_ICRF2G50__WIDTH 1 +#define RADIO130NM_BIAS2__PWD_ICRF2G50__MASK 0x10000000U +#define RADIO130NM_BIAS2__PWD_ICRF2G50__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_BIAS2__PWD_ICRF2G50__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_BIAS2__PWD_ICRF2G50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_BIAS2__PWD_ICRF2G50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_BIAS2__PWD_ICRF2G50__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_BIAS2__PWD_ICRF2G50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PWD_ICRF5G50 */ +#define RADIO130NM_BIAS2__PWD_ICRF5G50__SHIFT 29 +#define RADIO130NM_BIAS2__PWD_ICRF5G50__WIDTH 1 +#define RADIO130NM_BIAS2__PWD_ICRF5G50__MASK 0x20000000U +#define RADIO130NM_BIAS2__PWD_ICRF5G50__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_BIAS2__PWD_ICRF5G50__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_BIAS2__PWD_ICRF5G50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_BIAS2__PWD_ICRF5G50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_BIAS2__PWD_ICRF5G50__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_BIAS2__PWD_ICRF5G50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PWD_IRSYNTH50 */ +#define RADIO130NM_BIAS2__PWD_IRSYNTH50__SHIFT 30 +#define RADIO130NM_BIAS2__PWD_IRSYNTH50__WIDTH 1 +#define RADIO130NM_BIAS2__PWD_IRSYNTH50__MASK 0x40000000U +#define RADIO130NM_BIAS2__PWD_IRSYNTH50__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_BIAS2__PWD_IRSYNTH50__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_BIAS2__PWD_IRSYNTH50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_BIAS2__PWD_IRSYNTH50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_BIAS2__PWD_IRSYNTH50__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_BIAS2__PWD_IRSYNTH50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PWD_ICSYNTH50 */ +#define RADIO130NM_BIAS2__PWD_ICSYNTH50__SHIFT 31 +#define RADIO130NM_BIAS2__PWD_ICSYNTH50__WIDTH 1 +#define RADIO130NM_BIAS2__PWD_ICSYNTH50__MASK 0x80000000U +#define RADIO130NM_BIAS2__PWD_ICSYNTH50__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_BIAS2__PWD_ICSYNTH50__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_BIAS2__PWD_ICSYNTH50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_BIAS2__PWD_ICSYNTH50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_BIAS2__PWD_ICSYNTH50__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_BIAS2__PWD_ICSYNTH50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_BIAS2__TYPE u_int32_t +#define RADIO130NM_BIAS2__READ 0xffffffffU +#define RADIO130NM_BIAS2__WRITE 0xffffffffU + +#endif /* __RADIO130NM_BIAS2_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.BIAS2 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__BIAS2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_BIAS3 */ +#ifndef __RADIO130NM_BIAS3_MACRO__ +#define __RADIO130NM_BIAS3_MACRO__ + +/* macros for field BIAS3_SPARE */ +#define RADIO130NM_BIAS3__BIAS3_SPARE__SHIFT 0 +#define RADIO130NM_BIAS3__BIAS3_SPARE__WIDTH 1 +#define RADIO130NM_BIAS3__BIAS3_SPARE__MASK 0x00000001U +#define RADIO130NM_BIAS3__BIAS3_SPARE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RADIO130NM_BIAS3__BIAS3_SPARE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_BIAS3__BIAS3_SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_BIAS3__BIAS3_SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_BIAS3__BIAS3_SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_BIAS3__BIAS3_SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PWD_ICLOLDO25 */ +#define RADIO130NM_BIAS3__PWD_ICLOLDO25__SHIFT 1 +#define RADIO130NM_BIAS3__PWD_ICLOLDO25__WIDTH 3 +#define RADIO130NM_BIAS3__PWD_ICLOLDO25__MASK 0x0000000eU +#define RADIO130NM_BIAS3__PWD_ICLOLDO25__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define RADIO130NM_BIAS3__PWD_ICLOLDO25__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define RADIO130NM_BIAS3__PWD_ICLOLDO25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define RADIO130NM_BIAS3__PWD_ICLOLDO25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field PWD_IR25SPARE4 */ +#define RADIO130NM_BIAS3__PWD_IR25SPARE4__SHIFT 4 +#define RADIO130NM_BIAS3__PWD_IR25SPARE4__WIDTH 3 +#define RADIO130NM_BIAS3__PWD_IR25SPARE4__MASK 0x00000070U +#define RADIO130NM_BIAS3__PWD_IR25SPARE4__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000070U) >> 4) +#define RADIO130NM_BIAS3__PWD_IR25SPARE4__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define RADIO130NM_BIAS3__PWD_IR25SPARE4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define RADIO130NM_BIAS3__PWD_IR25SPARE4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field PWD_IR25SPARE3 */ +#define RADIO130NM_BIAS3__PWD_IR25SPARE3__SHIFT 7 +#define RADIO130NM_BIAS3__PWD_IR25SPARE3__WIDTH 3 +#define RADIO130NM_BIAS3__PWD_IR25SPARE3__MASK 0x00000380U +#define RADIO130NM_BIAS3__PWD_IR25SPARE3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000380U) >> 7) +#define RADIO130NM_BIAS3__PWD_IR25SPARE3__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000380U) +#define RADIO130NM_BIAS3__PWD_IR25SPARE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((u_int32_t)(src) <<\ + 7) & 0x00000380U) +#define RADIO130NM_BIAS3__PWD_IR25SPARE3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000380U))) + +/* macros for field PWD_IR25SPARE2 */ +#define RADIO130NM_BIAS3__PWD_IR25SPARE2__SHIFT 10 +#define RADIO130NM_BIAS3__PWD_IR25SPARE2__WIDTH 3 +#define RADIO130NM_BIAS3__PWD_IR25SPARE2__MASK 0x00001c00U +#define RADIO130NM_BIAS3__PWD_IR25SPARE2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001c00U) >> 10) +#define RADIO130NM_BIAS3__PWD_IR25SPARE2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00001c00U) +#define RADIO130NM_BIAS3__PWD_IR25SPARE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00001c00U) +#define RADIO130NM_BIAS3__PWD_IR25SPARE2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00001c00U))) + +/* macros for field PWD_IR25SPARE1 */ +#define RADIO130NM_BIAS3__PWD_IR25SPARE1__SHIFT 13 +#define RADIO130NM_BIAS3__PWD_IR25SPARE1__WIDTH 3 +#define RADIO130NM_BIAS3__PWD_IR25SPARE1__MASK 0x0000e000U +#define RADIO130NM_BIAS3__PWD_IR25SPARE1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000e000U) >> 13) +#define RADIO130NM_BIAS3__PWD_IR25SPARE1__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0000e000U) +#define RADIO130NM_BIAS3__PWD_IR25SPARE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define RADIO130NM_BIAS3__PWD_IR25SPARE1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0000e000U))) + +/* macros for field PWD_IC25SPARE4 */ +#define RADIO130NM_BIAS3__PWD_IC25SPARE4__SHIFT 16 +#define RADIO130NM_BIAS3__PWD_IC25SPARE4__WIDTH 3 +#define RADIO130NM_BIAS3__PWD_IC25SPARE4__MASK 0x00070000U +#define RADIO130NM_BIAS3__PWD_IC25SPARE4__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define RADIO130NM_BIAS3__PWD_IC25SPARE4__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define RADIO130NM_BIAS3__PWD_IC25SPARE4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define RADIO130NM_BIAS3__PWD_IC25SPARE4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field PWD_IC25SPARE3 */ +#define RADIO130NM_BIAS3__PWD_IC25SPARE3__SHIFT 19 +#define RADIO130NM_BIAS3__PWD_IC25SPARE3__WIDTH 3 +#define RADIO130NM_BIAS3__PWD_IC25SPARE3__MASK 0x00380000U +#define RADIO130NM_BIAS3__PWD_IC25SPARE3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00380000U) >> 19) +#define RADIO130NM_BIAS3__PWD_IC25SPARE3__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define RADIO130NM_BIAS3__PWD_IC25SPARE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define RADIO130NM_BIAS3__PWD_IC25SPARE3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field PWD_IC25SPARE2 */ +#define RADIO130NM_BIAS3__PWD_IC25SPARE2__SHIFT 22 +#define RADIO130NM_BIAS3__PWD_IC25SPARE2__WIDTH 3 +#define RADIO130NM_BIAS3__PWD_IC25SPARE2__MASK 0x01c00000U +#define RADIO130NM_BIAS3__PWD_IC25SPARE2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01c00000U) >> 22) +#define RADIO130NM_BIAS3__PWD_IC25SPARE2__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x01c00000U) +#define RADIO130NM_BIAS3__PWD_IC25SPARE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x01c00000U) +#define RADIO130NM_BIAS3__PWD_IC25SPARE2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x01c00000U))) + +/* macros for field PWD_IC25SPARE1 */ +#define RADIO130NM_BIAS3__PWD_IC25SPARE1__SHIFT 25 +#define RADIO130NM_BIAS3__PWD_IC25SPARE1__WIDTH 3 +#define RADIO130NM_BIAS3__PWD_IC25SPARE1__MASK 0x0e000000U +#define RADIO130NM_BIAS3__PWD_IC25SPARE1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0e000000U) >> 25) +#define RADIO130NM_BIAS3__PWD_IC25SPARE1__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x0e000000U) +#define RADIO130NM_BIAS3__PWD_IC25SPARE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x0e000000U) +#define RADIO130NM_BIAS3__PWD_IC25SPARE1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x0e000000U))) + +/* macros for field PWD_IRTSENS25 */ +#define RADIO130NM_BIAS3__PWD_IRTSENS25__SHIFT 28 +#define RADIO130NM_BIAS3__PWD_IRTSENS25__WIDTH 1 +#define RADIO130NM_BIAS3__PWD_IRTSENS25__MASK 0x10000000U +#define RADIO130NM_BIAS3__PWD_IRTSENS25__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_BIAS3__PWD_IRTSENS25__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_BIAS3__PWD_IRTSENS25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_BIAS3__PWD_IRTSENS25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_BIAS3__PWD_IRTSENS25__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_BIAS3__PWD_IRTSENS25__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PWD_ICTSENS25 */ +#define RADIO130NM_BIAS3__PWD_ICTSENS25__SHIFT 29 +#define RADIO130NM_BIAS3__PWD_ICTSENS25__WIDTH 1 +#define RADIO130NM_BIAS3__PWD_ICTSENS25__MASK 0x20000000U +#define RADIO130NM_BIAS3__PWD_ICTSENS25__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_BIAS3__PWD_ICTSENS25__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_BIAS3__PWD_ICTSENS25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_BIAS3__PWD_ICTSENS25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_BIAS3__PWD_ICTSENS25__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_BIAS3__PWD_ICTSENS25__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PWD_IRTXPC25 */ +#define RADIO130NM_BIAS3__PWD_IRTXPC25__SHIFT 30 +#define RADIO130NM_BIAS3__PWD_IRTXPC25__WIDTH 1 +#define RADIO130NM_BIAS3__PWD_IRTXPC25__MASK 0x40000000U +#define RADIO130NM_BIAS3__PWD_IRTXPC25__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_BIAS3__PWD_IRTXPC25__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_BIAS3__PWD_IRTXPC25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_BIAS3__PWD_IRTXPC25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_BIAS3__PWD_IRTXPC25__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_BIAS3__PWD_IRTXPC25__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PWD_ICTXPC25 */ +#define RADIO130NM_BIAS3__PWD_ICTXPC25__SHIFT 31 +#define RADIO130NM_BIAS3__PWD_ICTXPC25__WIDTH 1 +#define RADIO130NM_BIAS3__PWD_ICTXPC25__MASK 0x80000000U +#define RADIO130NM_BIAS3__PWD_ICTXPC25__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_BIAS3__PWD_ICTXPC25__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_BIAS3__PWD_ICTXPC25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_BIAS3__PWD_ICTXPC25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_BIAS3__PWD_ICTXPC25__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_BIAS3__PWD_ICTXPC25__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_BIAS3__TYPE u_int32_t +#define RADIO130NM_BIAS3__READ 0xffffffffU +#define RADIO130NM_BIAS3__WRITE 0xffffffffU + +#endif /* __RADIO130NM_BIAS3_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.BIAS3 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__BIAS3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_BIAS4 */ +#ifndef __RADIO130NM_BIAS4_MACRO__ +#define __RADIO130NM_BIAS4_MACRO__ + +/* macros for field BIAS4_SPARE */ +#define RADIO130NM_BIAS4__BIAS4_SPARE__SHIFT 0 +#define RADIO130NM_BIAS4__BIAS4_SPARE__WIDTH 15 +#define RADIO130NM_BIAS4__BIAS4_SPARE__MASK 0x00007fffU +#define RADIO130NM_BIAS4__BIAS4_SPARE__READ(src) (u_int32_t)(src) & 0x00007fffU +#define RADIO130NM_BIAS4__BIAS4_SPARE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00007fffU) +#define RADIO130NM_BIAS4__BIAS4_SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007fffU) | ((u_int32_t)(src) &\ + 0x00007fffU) +#define RADIO130NM_BIAS4__BIAS4_SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00007fffU))) + +/* macros for field PWD_IRLOLDO25 */ +#define RADIO130NM_BIAS4__PWD_IRLOLDO25__SHIFT 15 +#define RADIO130NM_BIAS4__PWD_IRLOLDO25__WIDTH 3 +#define RADIO130NM_BIAS4__PWD_IRLOLDO25__MASK 0x00038000U +#define RADIO130NM_BIAS4__PWD_IRLOLDO25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00038000U) >> 15) +#define RADIO130NM_BIAS4__PWD_IRLOLDO25__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00038000U) +#define RADIO130NM_BIAS4__PWD_IRLOLDO25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define RADIO130NM_BIAS4__PWD_IRLOLDO25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field PWD_ICXLNA5G50 */ +#define RADIO130NM_BIAS4__PWD_ICXLNA5G50__SHIFT 18 +#define RADIO130NM_BIAS4__PWD_ICXLNA5G50__WIDTH 3 +#define RADIO130NM_BIAS4__PWD_ICXLNA5G50__MASK 0x001c0000U +#define RADIO130NM_BIAS4__PWD_ICXLNA5G50__READ(src) \ + (((u_int32_t)(src)\ + & 0x001c0000U) >> 18) +#define RADIO130NM_BIAS4__PWD_ICXLNA5G50__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x001c0000U) +#define RADIO130NM_BIAS4__PWD_ICXLNA5G50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define RADIO130NM_BIAS4__PWD_ICXLNA5G50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field PWD_ICXLNA2G50 */ +#define RADIO130NM_BIAS4__PWD_ICXLNA2G50__SHIFT 21 +#define RADIO130NM_BIAS4__PWD_ICXLNA2G50__WIDTH 3 +#define RADIO130NM_BIAS4__PWD_ICXLNA2G50__MASK 0x00e00000U +#define RADIO130NM_BIAS4__PWD_ICXLNA2G50__READ(src) \ + (((u_int32_t)(src)\ + & 0x00e00000U) >> 21) +#define RADIO130NM_BIAS4__PWD_ICXLNA2G50__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00e00000U) +#define RADIO130NM_BIAS4__PWD_ICXLNA2G50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define RADIO130NM_BIAS4__PWD_ICXLNA2G50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field BIAS4_SEL_SPARE */ +#define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__SHIFT 24 +#define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__WIDTH 8 +#define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__MASK 0xff000000U +#define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define RADIO130NM_BIAS4__TYPE u_int32_t +#define RADIO130NM_BIAS4__READ 0xffffffffU +#define RADIO130NM_BIAS4__WRITE 0xffffffffU + +#endif /* __RADIO130NM_BIAS4_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.BIAS4 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__BIAS4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_GAIN0 */ +#ifndef __RADIO130NM_GAIN0_MACRO__ +#define __RADIO130NM_GAIN0_MACRO__ + +/* macros for field SPARE */ +#define RADIO130NM_GAIN0__SPARE__SHIFT 0 +#define RADIO130NM_GAIN0__SPARE__WIDTH 1 +#define RADIO130NM_GAIN0__SPARE__MASK 0x00000001U +#define RADIO130NM_GAIN0__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RADIO130NM_GAIN0__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RADIO130NM_GAIN0__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_GAIN0__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_GAIN0__SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_GAIN0__SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RX6DBHIQGAIN */ +#define RADIO130NM_GAIN0__RX6DBHIQGAIN__SHIFT 1 +#define RADIO130NM_GAIN0__RX6DBHIQGAIN__WIDTH 2 +#define RADIO130NM_GAIN0__RX6DBHIQGAIN__MASK 0x00000006U +#define RADIO130NM_GAIN0__RX6DBHIQGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000006U) >> 1) +#define RADIO130NM_GAIN0__RX6DBHIQGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000006U) +#define RADIO130NM_GAIN0__RX6DBHIQGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((u_int32_t)(src) <<\ + 1) & 0x00000006U) +#define RADIO130NM_GAIN0__RX6DBHIQGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000006U))) + +/* macros for field RX1DBLOQGAIN */ +#define RADIO130NM_GAIN0__RX1DBLOQGAIN__SHIFT 3 +#define RADIO130NM_GAIN0__RX1DBLOQGAIN__WIDTH 3 +#define RADIO130NM_GAIN0__RX1DBLOQGAIN__MASK 0x00000038U +#define RADIO130NM_GAIN0__RX1DBLOQGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define RADIO130NM_GAIN0__RX1DBLOQGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define RADIO130NM_GAIN0__RX1DBLOQGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define RADIO130NM_GAIN0__RX1DBLOQGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field RX6DBLOQGAIN */ +#define RADIO130NM_GAIN0__RX6DBLOQGAIN__SHIFT 6 +#define RADIO130NM_GAIN0__RX6DBLOQGAIN__WIDTH 2 +#define RADIO130NM_GAIN0__RX6DBLOQGAIN__MASK 0x000000c0U +#define RADIO130NM_GAIN0__RX6DBLOQGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define RADIO130NM_GAIN0__RX6DBLOQGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define RADIO130NM_GAIN0__RX6DBLOQGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define RADIO130NM_GAIN0__RX6DBLOQGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field RFGMGN */ +#define RADIO130NM_GAIN0__RFGMGN__SHIFT 8 +#define RADIO130NM_GAIN0__RFGMGN__WIDTH 3 +#define RADIO130NM_GAIN0__RFGMGN__MASK 0x00000700U +#define RADIO130NM_GAIN0__RFGMGN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define RADIO130NM_GAIN0__RFGMGN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define RADIO130NM_GAIN0__RFGMGN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define RADIO130NM_GAIN0__RFGMGN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field RFVGA5GAIN */ +#define RADIO130NM_GAIN0__RFVGA5GAIN__SHIFT 11 +#define RADIO130NM_GAIN0__RFVGA5GAIN__WIDTH 2 +#define RADIO130NM_GAIN0__RFVGA5GAIN__MASK 0x00001800U +#define RADIO130NM_GAIN0__RFVGA5GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001800U) >> 11) +#define RADIO130NM_GAIN0__RFVGA5GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00001800U) +#define RADIO130NM_GAIN0__RFVGA5GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define RADIO130NM_GAIN0__RFVGA5GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field LNAGAIN */ +#define RADIO130NM_GAIN0__LNAGAIN__SHIFT 13 +#define RADIO130NM_GAIN0__LNAGAIN__WIDTH 4 +#define RADIO130NM_GAIN0__LNAGAIN__MASK 0x0001e000U +#define RADIO130NM_GAIN0__LNAGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001e000U) >> 13) +#define RADIO130NM_GAIN0__LNAGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0001e000U) +#define RADIO130NM_GAIN0__LNAGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0001e000U) +#define RADIO130NM_GAIN0__LNAGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0001e000U))) + +/* macros for field LNAON */ +#define RADIO130NM_GAIN0__LNAON__SHIFT 17 +#define RADIO130NM_GAIN0__LNAON__WIDTH 1 +#define RADIO130NM_GAIN0__LNAON__MASK 0x00020000U +#define RADIO130NM_GAIN0__LNAON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO130NM_GAIN0__LNAON__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define RADIO130NM_GAIN0__LNAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RADIO130NM_GAIN0__LNAON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RADIO130NM_GAIN0__LNAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RADIO130NM_GAIN0__LNAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field PAOUT2GN */ +#define RADIO130NM_GAIN0__PAOUT2GN__SHIFT 18 +#define RADIO130NM_GAIN0__PAOUT2GN__WIDTH 3 +#define RADIO130NM_GAIN0__PAOUT2GN__MASK 0x001c0000U +#define RADIO130NM_GAIN0__PAOUT2GN__READ(src) \ + (((u_int32_t)(src)\ + & 0x001c0000U) >> 18) +#define RADIO130NM_GAIN0__PAOUT2GN__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x001c0000U) +#define RADIO130NM_GAIN0__PAOUT2GN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define RADIO130NM_GAIN0__PAOUT2GN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field PADRVGN */ +#define RADIO130NM_GAIN0__PADRVGN__SHIFT 21 +#define RADIO130NM_GAIN0__PADRVGN__WIDTH 3 +#define RADIO130NM_GAIN0__PADRVGN__MASK 0x00e00000U +#define RADIO130NM_GAIN0__PADRVGN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00e00000U) >> 21) +#define RADIO130NM_GAIN0__PADRVGN__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00e00000U) +#define RADIO130NM_GAIN0__PADRVGN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define RADIO130NM_GAIN0__PADRVGN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field PABUF5GN */ +#define RADIO130NM_GAIN0__PABUF5GN__SHIFT 24 +#define RADIO130NM_GAIN0__PABUF5GN__WIDTH 1 +#define RADIO130NM_GAIN0__PABUF5GN__MASK 0x01000000U +#define RADIO130NM_GAIN0__PABUF5GN__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO130NM_GAIN0__PABUF5GN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RADIO130NM_GAIN0__PABUF5GN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RADIO130NM_GAIN0__PABUF5GN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RADIO130NM_GAIN0__PABUF5GN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RADIO130NM_GAIN0__PABUF5GN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field TXV2IGAIN */ +#define RADIO130NM_GAIN0__TXV2IGAIN__SHIFT 25 +#define RADIO130NM_GAIN0__TXV2IGAIN__WIDTH 2 +#define RADIO130NM_GAIN0__TXV2IGAIN__MASK 0x06000000U +#define RADIO130NM_GAIN0__TXV2IGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define RADIO130NM_GAIN0__TXV2IGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define RADIO130NM_GAIN0__TXV2IGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define RADIO130NM_GAIN0__TXV2IGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field TX1DBLOQGAIN */ +#define RADIO130NM_GAIN0__TX1DBLOQGAIN__SHIFT 27 +#define RADIO130NM_GAIN0__TX1DBLOQGAIN__WIDTH 3 +#define RADIO130NM_GAIN0__TX1DBLOQGAIN__MASK 0x38000000U +#define RADIO130NM_GAIN0__TX1DBLOQGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x38000000U) >> 27) +#define RADIO130NM_GAIN0__TX1DBLOQGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x38000000U) +#define RADIO130NM_GAIN0__TX1DBLOQGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x38000000U) | (((u_int32_t)(src) <<\ + 27) & 0x38000000U) +#define RADIO130NM_GAIN0__TX1DBLOQGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x38000000U))) + +/* macros for field TX6DBLOQGAIN */ +#define RADIO130NM_GAIN0__TX6DBLOQGAIN__SHIFT 30 +#define RADIO130NM_GAIN0__TX6DBLOQGAIN__WIDTH 2 +#define RADIO130NM_GAIN0__TX6DBLOQGAIN__MASK 0xc0000000U +#define RADIO130NM_GAIN0__TX6DBLOQGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define RADIO130NM_GAIN0__TX6DBLOQGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define RADIO130NM_GAIN0__TX6DBLOQGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define RADIO130NM_GAIN0__TX6DBLOQGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define RADIO130NM_GAIN0__TYPE u_int32_t +#define RADIO130NM_GAIN0__READ 0xffffffffU +#define RADIO130NM_GAIN0__WRITE 0xffffffffU + +#endif /* __RADIO130NM_GAIN0_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.GAIN0 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__GAIN0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_GAIN1 */ +#ifndef __RADIO130NM_GAIN1_MACRO__ +#define __RADIO130NM_GAIN1_MACRO__ + +/* macros for field SPARE */ +#define RADIO130NM_GAIN1__SPARE__SHIFT 0 +#define RADIO130NM_GAIN1__SPARE__WIDTH 1 +#define RADIO130NM_GAIN1__SPARE__MASK 0x00000001U +#define RADIO130NM_GAIN1__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RADIO130NM_GAIN1__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RADIO130NM_GAIN1__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_GAIN1__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_GAIN1__SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_GAIN1__SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RX6DBHIQGAIN */ +#define RADIO130NM_GAIN1__RX6DBHIQGAIN__SHIFT 1 +#define RADIO130NM_GAIN1__RX6DBHIQGAIN__WIDTH 2 +#define RADIO130NM_GAIN1__RX6DBHIQGAIN__MASK 0x00000006U +#define RADIO130NM_GAIN1__RX6DBHIQGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000006U) >> 1) +#define RADIO130NM_GAIN1__RX6DBHIQGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000006U) +#define RADIO130NM_GAIN1__RX6DBHIQGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((u_int32_t)(src) <<\ + 1) & 0x00000006U) +#define RADIO130NM_GAIN1__RX6DBHIQGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000006U))) + +/* macros for field RX1DBLOQGAIN */ +#define RADIO130NM_GAIN1__RX1DBLOQGAIN__SHIFT 3 +#define RADIO130NM_GAIN1__RX1DBLOQGAIN__WIDTH 3 +#define RADIO130NM_GAIN1__RX1DBLOQGAIN__MASK 0x00000038U +#define RADIO130NM_GAIN1__RX1DBLOQGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define RADIO130NM_GAIN1__RX1DBLOQGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define RADIO130NM_GAIN1__RX1DBLOQGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define RADIO130NM_GAIN1__RX1DBLOQGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field RX6DBLOQGAIN */ +#define RADIO130NM_GAIN1__RX6DBLOQGAIN__SHIFT 6 +#define RADIO130NM_GAIN1__RX6DBLOQGAIN__WIDTH 2 +#define RADIO130NM_GAIN1__RX6DBLOQGAIN__MASK 0x000000c0U +#define RADIO130NM_GAIN1__RX6DBLOQGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define RADIO130NM_GAIN1__RX6DBLOQGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define RADIO130NM_GAIN1__RX6DBLOQGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define RADIO130NM_GAIN1__RX6DBLOQGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field RFGMGN */ +#define RADIO130NM_GAIN1__RFGMGN__SHIFT 8 +#define RADIO130NM_GAIN1__RFGMGN__WIDTH 3 +#define RADIO130NM_GAIN1__RFGMGN__MASK 0x00000700U +#define RADIO130NM_GAIN1__RFGMGN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define RADIO130NM_GAIN1__RFGMGN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define RADIO130NM_GAIN1__RFGMGN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define RADIO130NM_GAIN1__RFGMGN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field RFVGA5GAIN */ +#define RADIO130NM_GAIN1__RFVGA5GAIN__SHIFT 11 +#define RADIO130NM_GAIN1__RFVGA5GAIN__WIDTH 2 +#define RADIO130NM_GAIN1__RFVGA5GAIN__MASK 0x00001800U +#define RADIO130NM_GAIN1__RFVGA5GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001800U) >> 11) +#define RADIO130NM_GAIN1__RFVGA5GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00001800U) +#define RADIO130NM_GAIN1__RFVGA5GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define RADIO130NM_GAIN1__RFVGA5GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field LNAGAIN */ +#define RADIO130NM_GAIN1__LNAGAIN__SHIFT 13 +#define RADIO130NM_GAIN1__LNAGAIN__WIDTH 4 +#define RADIO130NM_GAIN1__LNAGAIN__MASK 0x0001e000U +#define RADIO130NM_GAIN1__LNAGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001e000U) >> 13) +#define RADIO130NM_GAIN1__LNAGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0001e000U) +#define RADIO130NM_GAIN1__LNAGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0001e000U) +#define RADIO130NM_GAIN1__LNAGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0001e000U))) + +/* macros for field LNAON */ +#define RADIO130NM_GAIN1__LNAON__SHIFT 17 +#define RADIO130NM_GAIN1__LNAON__WIDTH 1 +#define RADIO130NM_GAIN1__LNAON__MASK 0x00020000U +#define RADIO130NM_GAIN1__LNAON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO130NM_GAIN1__LNAON__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define RADIO130NM_GAIN1__LNAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RADIO130NM_GAIN1__LNAON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RADIO130NM_GAIN1__LNAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RADIO130NM_GAIN1__LNAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field PAOUT2GN */ +#define RADIO130NM_GAIN1__PAOUT2GN__SHIFT 18 +#define RADIO130NM_GAIN1__PAOUT2GN__WIDTH 3 +#define RADIO130NM_GAIN1__PAOUT2GN__MASK 0x001c0000U +#define RADIO130NM_GAIN1__PAOUT2GN__READ(src) \ + (((u_int32_t)(src)\ + & 0x001c0000U) >> 18) +#define RADIO130NM_GAIN1__PAOUT2GN__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x001c0000U) +#define RADIO130NM_GAIN1__PAOUT2GN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define RADIO130NM_GAIN1__PAOUT2GN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field PADRVGN */ +#define RADIO130NM_GAIN1__PADRVGN__SHIFT 21 +#define RADIO130NM_GAIN1__PADRVGN__WIDTH 3 +#define RADIO130NM_GAIN1__PADRVGN__MASK 0x00e00000U +#define RADIO130NM_GAIN1__PADRVGN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00e00000U) >> 21) +#define RADIO130NM_GAIN1__PADRVGN__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00e00000U) +#define RADIO130NM_GAIN1__PADRVGN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define RADIO130NM_GAIN1__PADRVGN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field PABUF5GN */ +#define RADIO130NM_GAIN1__PABUF5GN__SHIFT 24 +#define RADIO130NM_GAIN1__PABUF5GN__WIDTH 1 +#define RADIO130NM_GAIN1__PABUF5GN__MASK 0x01000000U +#define RADIO130NM_GAIN1__PABUF5GN__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO130NM_GAIN1__PABUF5GN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RADIO130NM_GAIN1__PABUF5GN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RADIO130NM_GAIN1__PABUF5GN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RADIO130NM_GAIN1__PABUF5GN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RADIO130NM_GAIN1__PABUF5GN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field TXV2IGAIN */ +#define RADIO130NM_GAIN1__TXV2IGAIN__SHIFT 25 +#define RADIO130NM_GAIN1__TXV2IGAIN__WIDTH 2 +#define RADIO130NM_GAIN1__TXV2IGAIN__MASK 0x06000000U +#define RADIO130NM_GAIN1__TXV2IGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define RADIO130NM_GAIN1__TXV2IGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define RADIO130NM_GAIN1__TXV2IGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define RADIO130NM_GAIN1__TXV2IGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field TX1DBLOQGAIN */ +#define RADIO130NM_GAIN1__TX1DBLOQGAIN__SHIFT 27 +#define RADIO130NM_GAIN1__TX1DBLOQGAIN__WIDTH 3 +#define RADIO130NM_GAIN1__TX1DBLOQGAIN__MASK 0x38000000U +#define RADIO130NM_GAIN1__TX1DBLOQGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x38000000U) >> 27) +#define RADIO130NM_GAIN1__TX1DBLOQGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x38000000U) +#define RADIO130NM_GAIN1__TX1DBLOQGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x38000000U) | (((u_int32_t)(src) <<\ + 27) & 0x38000000U) +#define RADIO130NM_GAIN1__TX1DBLOQGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x38000000U))) + +/* macros for field TX6DBLOQGAIN */ +#define RADIO130NM_GAIN1__TX6DBLOQGAIN__SHIFT 30 +#define RADIO130NM_GAIN1__TX6DBLOQGAIN__WIDTH 2 +#define RADIO130NM_GAIN1__TX6DBLOQGAIN__MASK 0xc0000000U +#define RADIO130NM_GAIN1__TX6DBLOQGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define RADIO130NM_GAIN1__TX6DBLOQGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define RADIO130NM_GAIN1__TX6DBLOQGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define RADIO130NM_GAIN1__TX6DBLOQGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define RADIO130NM_GAIN1__TYPE u_int32_t +#define RADIO130NM_GAIN1__READ 0xffffffffU +#define RADIO130NM_GAIN1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_GAIN1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.GAIN1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__GAIN1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_TOP0 */ +#ifndef __RADIO130NM_TOP0_MACRO__ +#define __RADIO130NM_TOP0_MACRO__ + +/* macros for field FORCEMSBLOW */ +#define RADIO130NM_TOP0__FORCEMSBLOW__SHIFT 0 +#define RADIO130NM_TOP0__FORCEMSBLOW__WIDTH 1 +#define RADIO130NM_TOP0__FORCEMSBLOW__MASK 0x00000001U +#define RADIO130NM_TOP0__FORCEMSBLOW__READ(src) (u_int32_t)(src) & 0x00000001U +#define RADIO130NM_TOP0__FORCEMSBLOW__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_TOP0__FORCEMSBLOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_TOP0__FORCEMSBLOW__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_TOP0__FORCEMSBLOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_TOP0__FORCEMSBLOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PWDBIAS */ +#define RADIO130NM_TOP0__PWDBIAS__SHIFT 1 +#define RADIO130NM_TOP0__PWDBIAS__WIDTH 1 +#define RADIO130NM_TOP0__PWDBIAS__MASK 0x00000002U +#define RADIO130NM_TOP0__PWDBIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RADIO130NM_TOP0__PWDBIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RADIO130NM_TOP0__PWDBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RADIO130NM_TOP0__PWDBIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADIO130NM_TOP0__PWDBIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RADIO130NM_TOP0__PWDBIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SYNTHON_FORCE */ +#define RADIO130NM_TOP0__SYNTHON_FORCE__SHIFT 2 +#define RADIO130NM_TOP0__SYNTHON_FORCE__WIDTH 1 +#define RADIO130NM_TOP0__SYNTHON_FORCE__MASK 0x00000004U +#define RADIO130NM_TOP0__SYNTHON_FORCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RADIO130NM_TOP0__SYNTHON_FORCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RADIO130NM_TOP0__SYNTHON_FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RADIO130NM_TOP0__SYNTHON_FORCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RADIO130NM_TOP0__SYNTHON_FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RADIO130NM_TOP0__SYNTHON_FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field SCLKEN_FORCE */ +#define RADIO130NM_TOP0__SCLKEN_FORCE__SHIFT 3 +#define RADIO130NM_TOP0__SCLKEN_FORCE__WIDTH 1 +#define RADIO130NM_TOP0__SCLKEN_FORCE__MASK 0x00000008U +#define RADIO130NM_TOP0__SCLKEN_FORCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO130NM_TOP0__SCLKEN_FORCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO130NM_TOP0__SCLKEN_FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO130NM_TOP0__SCLKEN_FORCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO130NM_TOP0__SCLKEN_FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RADIO130NM_TOP0__SCLKEN_FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field OSCON */ +#define RADIO130NM_TOP0__OSCON__SHIFT 4 +#define RADIO130NM_TOP0__OSCON__WIDTH 1 +#define RADIO130NM_TOP0__OSCON__MASK 0x00000010U +#define RADIO130NM_TOP0__OSCON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RADIO130NM_TOP0__OSCON__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RADIO130NM_TOP0__OSCON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RADIO130NM_TOP0__OSCON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RADIO130NM_TOP0__OSCON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RADIO130NM_TOP0__OSCON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PWDCLKIN */ +#define RADIO130NM_TOP0__PWDCLKIN__SHIFT 5 +#define RADIO130NM_TOP0__PWDCLKIN__WIDTH 1 +#define RADIO130NM_TOP0__PWDCLKIN__MASK 0x00000020U +#define RADIO130NM_TOP0__PWDCLKIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RADIO130NM_TOP0__PWDCLKIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RADIO130NM_TOP0__PWDCLKIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RADIO130NM_TOP0__PWDCLKIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RADIO130NM_TOP0__PWDCLKIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RADIO130NM_TOP0__PWDCLKIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field LOCALXTAL */ +#define RADIO130NM_TOP0__LOCALXTAL__SHIFT 6 +#define RADIO130NM_TOP0__LOCALXTAL__WIDTH 1 +#define RADIO130NM_TOP0__LOCALXTAL__MASK 0x00000040U +#define RADIO130NM_TOP0__LOCALXTAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RADIO130NM_TOP0__LOCALXTAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RADIO130NM_TOP0__LOCALXTAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RADIO130NM_TOP0__LOCALXTAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RADIO130NM_TOP0__LOCALXTAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RADIO130NM_TOP0__LOCALXTAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field XPAON */ +#define RADIO130NM_TOP0__XPAON__SHIFT 7 +#define RADIO130NM_TOP0__XPAON__WIDTH 1 +#define RADIO130NM_TOP0__XPAON__MASK 0x00000080U +#define RADIO130NM_TOP0__XPAON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO130NM_TOP0__XPAON__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO130NM_TOP0__XPAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO130NM_TOP0__XPAON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO130NM_TOP0__XPAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RADIO130NM_TOP0__XPAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field XLNAON */ +#define RADIO130NM_TOP0__XLNAON__SHIFT 8 +#define RADIO130NM_TOP0__XLNAON__WIDTH 2 +#define RADIO130NM_TOP0__XLNAON__MASK 0x00000300U +#define RADIO130NM_TOP0__XLNAON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define RADIO130NM_TOP0__XLNAON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define RADIO130NM_TOP0__XLNAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define RADIO130NM_TOP0__XLNAON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field PAON */ +#define RADIO130NM_TOP0__PAON__SHIFT 10 +#define RADIO130NM_TOP0__PAON__WIDTH 2 +#define RADIO130NM_TOP0__PAON__MASK 0x00000c00U +#define RADIO130NM_TOP0__PAON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define RADIO130NM_TOP0__PAON__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define RADIO130NM_TOP0__PAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define RADIO130NM_TOP0__PAON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) + +/* macros for field TXON */ +#define RADIO130NM_TOP0__TXON__SHIFT 12 +#define RADIO130NM_TOP0__TXON__WIDTH 2 +#define RADIO130NM_TOP0__TXON__MASK 0x00003000U +#define RADIO130NM_TOP0__TXON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003000U) >> 12) +#define RADIO130NM_TOP0__TXON__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00003000U) +#define RADIO130NM_TOP0__TXON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((u_int32_t)(src) <<\ + 12) & 0x00003000U) +#define RADIO130NM_TOP0__TXON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00003000U))) + +/* macros for field RXON */ +#define RADIO130NM_TOP0__RXON__SHIFT 14 +#define RADIO130NM_TOP0__RXON__WIDTH 2 +#define RADIO130NM_TOP0__RXON__MASK 0x0000c000U +#define RADIO130NM_TOP0__RXON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define RADIO130NM_TOP0__RXON__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define RADIO130NM_TOP0__RXON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define RADIO130NM_TOP0__RXON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field SYNTHON */ +#define RADIO130NM_TOP0__SYNTHON__SHIFT 16 +#define RADIO130NM_TOP0__SYNTHON__WIDTH 1 +#define RADIO130NM_TOP0__SYNTHON__MASK 0x00010000U +#define RADIO130NM_TOP0__SYNTHON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO130NM_TOP0__SYNTHON__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define RADIO130NM_TOP0__SYNTHON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define RADIO130NM_TOP0__SYNTHON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define RADIO130NM_TOP0__SYNTHON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define RADIO130NM_TOP0__SYNTHON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field TURBOMODE */ +#define RADIO130NM_TOP0__TURBOMODE__SHIFT 17 +#define RADIO130NM_TOP0__TURBOMODE__WIDTH 1 +#define RADIO130NM_TOP0__TURBOMODE__MASK 0x00020000U +#define RADIO130NM_TOP0__TURBOMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO130NM_TOP0__TURBOMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define RADIO130NM_TOP0__TURBOMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RADIO130NM_TOP0__TURBOMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RADIO130NM_TOP0__TURBOMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RADIO130NM_TOP0__TURBOMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field BMODERXTX */ +#define RADIO130NM_TOP0__BMODERXTX__SHIFT 18 +#define RADIO130NM_TOP0__BMODERXTX__WIDTH 2 +#define RADIO130NM_TOP0__BMODERXTX__MASK 0x000c0000U +#define RADIO130NM_TOP0__BMODERXTX__READ(src) \ + (((u_int32_t)(src)\ + & 0x000c0000U) >> 18) +#define RADIO130NM_TOP0__BMODERXTX__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define RADIO130NM_TOP0__BMODERXTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define RADIO130NM_TOP0__BMODERXTX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field BMODE */ +#define RADIO130NM_TOP0__BMODE__SHIFT 20 +#define RADIO130NM_TOP0__BMODE__WIDTH 1 +#define RADIO130NM_TOP0__BMODE__MASK 0x00100000U +#define RADIO130NM_TOP0__BMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define RADIO130NM_TOP0__BMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define RADIO130NM_TOP0__BMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define RADIO130NM_TOP0__BMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define RADIO130NM_TOP0__BMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define RADIO130NM_TOP0__BMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field CALTX */ +#define RADIO130NM_TOP0__CALTX__SHIFT 21 +#define RADIO130NM_TOP0__CALTX__WIDTH 2 +#define RADIO130NM_TOP0__CALTX__MASK 0x00600000U +#define RADIO130NM_TOP0__CALTX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00600000U) >> 21) +#define RADIO130NM_TOP0__CALTX__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00600000U) +#define RADIO130NM_TOP0__CALTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((u_int32_t)(src) <<\ + 21) & 0x00600000U) +#define RADIO130NM_TOP0__CALTX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00600000U))) + +/* macros for field CAL_RESIDUE */ +#define RADIO130NM_TOP0__CAL_RESIDUE__SHIFT 23 +#define RADIO130NM_TOP0__CAL_RESIDUE__WIDTH 2 +#define RADIO130NM_TOP0__CAL_RESIDUE__MASK 0x01800000U +#define RADIO130NM_TOP0__CAL_RESIDUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x01800000U) >> 23) +#define RADIO130NM_TOP0__CAL_RESIDUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x01800000U) +#define RADIO130NM_TOP0__CAL_RESIDUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01800000U) | (((u_int32_t)(src) <<\ + 23) & 0x01800000U) +#define RADIO130NM_TOP0__CAL_RESIDUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x01800000U))) + +/* macros for field CALDC */ +#define RADIO130NM_TOP0__CALDC__SHIFT 25 +#define RADIO130NM_TOP0__CALDC__WIDTH 2 +#define RADIO130NM_TOP0__CALDC__MASK 0x06000000U +#define RADIO130NM_TOP0__CALDC__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define RADIO130NM_TOP0__CALDC__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define RADIO130NM_TOP0__CALDC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define RADIO130NM_TOP0__CALDC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field CALFC */ +#define RADIO130NM_TOP0__CALFC__SHIFT 27 +#define RADIO130NM_TOP0__CALFC__WIDTH 2 +#define RADIO130NM_TOP0__CALFC__MASK 0x18000000U +#define RADIO130NM_TOP0__CALFC__READ(src) \ + (((u_int32_t)(src)\ + & 0x18000000U) >> 27) +#define RADIO130NM_TOP0__CALFC__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x18000000U) +#define RADIO130NM_TOP0__CALFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((u_int32_t)(src) <<\ + 27) & 0x18000000U) +#define RADIO130NM_TOP0__CALFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x18000000U))) + +/* macros for field LOCALMODE */ +#define RADIO130NM_TOP0__LOCALMODE__SHIFT 29 +#define RADIO130NM_TOP0__LOCALMODE__WIDTH 1 +#define RADIO130NM_TOP0__LOCALMODE__MASK 0x20000000U +#define RADIO130NM_TOP0__LOCALMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_TOP0__LOCALMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_TOP0__LOCALMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_TOP0__LOCALMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_TOP0__LOCALMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_TOP0__LOCALMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field LOCALRXGAIN */ +#define RADIO130NM_TOP0__LOCALRXGAIN__SHIFT 30 +#define RADIO130NM_TOP0__LOCALRXGAIN__WIDTH 1 +#define RADIO130NM_TOP0__LOCALRXGAIN__MASK 0x40000000U +#define RADIO130NM_TOP0__LOCALRXGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RADIO130NM_TOP0__LOCALRXGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RADIO130NM_TOP0__LOCALRXGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RADIO130NM_TOP0__LOCALRXGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RADIO130NM_TOP0__LOCALRXGAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RADIO130NM_TOP0__LOCALRXGAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field LOCALTXGAIN */ +#define RADIO130NM_TOP0__LOCALTXGAIN__SHIFT 31 +#define RADIO130NM_TOP0__LOCALTXGAIN__WIDTH 1 +#define RADIO130NM_TOP0__LOCALTXGAIN__MASK 0x80000000U +#define RADIO130NM_TOP0__LOCALTXGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_TOP0__LOCALTXGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_TOP0__LOCALTXGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_TOP0__LOCALTXGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_TOP0__LOCALTXGAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_TOP0__LOCALTXGAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_TOP0__TYPE u_int32_t +#define RADIO130NM_TOP0__READ 0xffffffffU +#define RADIO130NM_TOP0__WRITE 0xffffffffU + +#endif /* __RADIO130NM_TOP0_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.TOP0 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__TOP0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_TOP1 */ +#ifndef __RADIO130NM_TOP1_MACRO__ +#define __RADIO130NM_TOP1_MACRO__ + +/* macros for field PLL_SVREG */ +#define RADIO130NM_TOP1__PLL_SVREG__SHIFT 0 +#define RADIO130NM_TOP1__PLL_SVREG__WIDTH 1 +#define RADIO130NM_TOP1__PLL_SVREG__MASK 0x00000001U +#define RADIO130NM_TOP1__PLL_SVREG__READ(src) (u_int32_t)(src) & 0x00000001U +#define RADIO130NM_TOP1__PLL_SVREG__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RADIO130NM_TOP1__PLL_SVREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_TOP1__PLL_SVREG__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_TOP1__PLL_SVREG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_TOP1__PLL_SVREG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PLL_SCLAMP */ +#define RADIO130NM_TOP1__PLL_SCLAMP__SHIFT 1 +#define RADIO130NM_TOP1__PLL_SCLAMP__WIDTH 3 +#define RADIO130NM_TOP1__PLL_SCLAMP__MASK 0x0000000eU +#define RADIO130NM_TOP1__PLL_SCLAMP__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define RADIO130NM_TOP1__PLL_SCLAMP__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define RADIO130NM_TOP1__PLL_SCLAMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define RADIO130NM_TOP1__PLL_SCLAMP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field PLL_ICP */ +#define RADIO130NM_TOP1__PLL_ICP__SHIFT 4 +#define RADIO130NM_TOP1__PLL_ICP__WIDTH 3 +#define RADIO130NM_TOP1__PLL_ICP__MASK 0x00000070U +#define RADIO130NM_TOP1__PLL_ICP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000070U) >> 4) +#define RADIO130NM_TOP1__PLL_ICP__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define RADIO130NM_TOP1__PLL_ICP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define RADIO130NM_TOP1__PLL_ICP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field PLL_FILTER */ +#define RADIO130NM_TOP1__PLL_FILTER__SHIFT 7 +#define RADIO130NM_TOP1__PLL_FILTER__WIDTH 8 +#define RADIO130NM_TOP1__PLL_FILTER__MASK 0x00007f80U +#define RADIO130NM_TOP1__PLL_FILTER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007f80U) >> 7) +#define RADIO130NM_TOP1__PLL_FILTER__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00007f80U) +#define RADIO130NM_TOP1__PLL_FILTER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00007f80U) +#define RADIO130NM_TOP1__PLL_FILTER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00007f80U))) + +/* macros for field PLL_ATB */ +#define RADIO130NM_TOP1__PLL_ATB__SHIFT 15 +#define RADIO130NM_TOP1__PLL_ATB__WIDTH 2 +#define RADIO130NM_TOP1__PLL_ATB__MASK 0x00018000U +#define RADIO130NM_TOP1__PLL_ATB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00018000U) >> 15) +#define RADIO130NM_TOP1__PLL_ATB__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00018000U) +#define RADIO130NM_TOP1__PLL_ATB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00018000U) | (((u_int32_t)(src) <<\ + 15) & 0x00018000U) +#define RADIO130NM_TOP1__PLL_ATB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00018000U))) + +/* macros for field INV_CLK160_ADC */ +#define RADIO130NM_TOP1__INV_CLK160_ADC__SHIFT 17 +#define RADIO130NM_TOP1__INV_CLK160_ADC__WIDTH 1 +#define RADIO130NM_TOP1__INV_CLK160_ADC__MASK 0x00020000U +#define RADIO130NM_TOP1__INV_CLK160_ADC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO130NM_TOP1__INV_CLK160_ADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define RADIO130NM_TOP1__INV_CLK160_ADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RADIO130NM_TOP1__INV_CLK160_ADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RADIO130NM_TOP1__INV_CLK160_ADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RADIO130NM_TOP1__INV_CLK160_ADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field DACLPMODE */ +#define RADIO130NM_TOP1__DACLPMODE__SHIFT 18 +#define RADIO130NM_TOP1__DACLPMODE__WIDTH 1 +#define RADIO130NM_TOP1__DACLPMODE__MASK 0x00040000U +#define RADIO130NM_TOP1__DACLPMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define RADIO130NM_TOP1__DACLPMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define RADIO130NM_TOP1__DACLPMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define RADIO130NM_TOP1__DACLPMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define RADIO130NM_TOP1__DACLPMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define RADIO130NM_TOP1__DACLPMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field PWDDAC */ +#define RADIO130NM_TOP1__PWDDAC__SHIFT 19 +#define RADIO130NM_TOP1__PWDDAC__WIDTH 2 +#define RADIO130NM_TOP1__PWDDAC__MASK 0x00180000U +#define RADIO130NM_TOP1__PWDDAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00180000U) >> 19) +#define RADIO130NM_TOP1__PWDDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00180000U) +#define RADIO130NM_TOP1__PWDDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((u_int32_t)(src) <<\ + 19) & 0x00180000U) +#define RADIO130NM_TOP1__PWDDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00180000U))) + +/* macros for field PWDADC */ +#define RADIO130NM_TOP1__PWDADC__SHIFT 21 +#define RADIO130NM_TOP1__PWDADC__WIDTH 2 +#define RADIO130NM_TOP1__PWDADC__MASK 0x00600000U +#define RADIO130NM_TOP1__PWDADC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00600000U) >> 21) +#define RADIO130NM_TOP1__PWDADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00600000U) +#define RADIO130NM_TOP1__PWDADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00600000U) | (((u_int32_t)(src) <<\ + 21) & 0x00600000U) +#define RADIO130NM_TOP1__PWDADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00600000U))) + +/* macros for field PWDPLL */ +#define RADIO130NM_TOP1__PWDPLL__SHIFT 23 +#define RADIO130NM_TOP1__PWDPLL__WIDTH 1 +#define RADIO130NM_TOP1__PWDPLL__MASK 0x00800000U +#define RADIO130NM_TOP1__PWDPLL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define RADIO130NM_TOP1__PWDPLL__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define RADIO130NM_TOP1__PWDPLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RADIO130NM_TOP1__PWDPLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RADIO130NM_TOP1__PWDPLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RADIO130NM_TOP1__PWDPLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field LOCALADDAC */ +#define RADIO130NM_TOP1__LOCALADDAC__SHIFT 24 +#define RADIO130NM_TOP1__LOCALADDAC__WIDTH 1 +#define RADIO130NM_TOP1__LOCALADDAC__MASK 0x01000000U +#define RADIO130NM_TOP1__LOCALADDAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO130NM_TOP1__LOCALADDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RADIO130NM_TOP1__LOCALADDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RADIO130NM_TOP1__LOCALADDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RADIO130NM_TOP1__LOCALADDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RADIO130NM_TOP1__LOCALADDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field INT2GND */ +#define RADIO130NM_TOP1__INT2GND__SHIFT 25 +#define RADIO130NM_TOP1__INT2GND__WIDTH 1 +#define RADIO130NM_TOP1__INT2GND__MASK 0x02000000U +#define RADIO130NM_TOP1__INT2GND__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define RADIO130NM_TOP1__INT2GND__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define RADIO130NM_TOP1__INT2GND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RADIO130NM_TOP1__INT2GND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RADIO130NM_TOP1__INT2GND__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RADIO130NM_TOP1__INT2GND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field PAD2GND */ +#define RADIO130NM_TOP1__PAD2GND__SHIFT 26 +#define RADIO130NM_TOP1__PAD2GND__WIDTH 1 +#define RADIO130NM_TOP1__PAD2GND__MASK 0x04000000U +#define RADIO130NM_TOP1__PAD2GND__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RADIO130NM_TOP1__PAD2GND__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RADIO130NM_TOP1__PAD2GND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RADIO130NM_TOP1__PAD2GND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RADIO130NM_TOP1__PAD2GND__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RADIO130NM_TOP1__PAD2GND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field INTH2PAD */ +#define RADIO130NM_TOP1__INTH2PAD__SHIFT 27 +#define RADIO130NM_TOP1__INTH2PAD__WIDTH 1 +#define RADIO130NM_TOP1__INTH2PAD__MASK 0x08000000U +#define RADIO130NM_TOP1__INTH2PAD__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADIO130NM_TOP1__INTH2PAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADIO130NM_TOP1__INTH2PAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADIO130NM_TOP1__INTH2PAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADIO130NM_TOP1__INTH2PAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADIO130NM_TOP1__INTH2PAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field INT2PAD */ +#define RADIO130NM_TOP1__INT2PAD__SHIFT 28 +#define RADIO130NM_TOP1__INT2PAD__WIDTH 1 +#define RADIO130NM_TOP1__INT2PAD__MASK 0x10000000U +#define RADIO130NM_TOP1__INT2PAD__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_TOP1__INT2PAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_TOP1__INT2PAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_TOP1__INT2PAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_TOP1__INT2PAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_TOP1__INT2PAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field REVID */ +#define RADIO130NM_TOP1__REVID__SHIFT 29 +#define RADIO130NM_TOP1__REVID__WIDTH 3 +#define RADIO130NM_TOP1__REVID__MASK 0xe0000000U +#define RADIO130NM_TOP1__REVID__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define RADIO130NM_TOP1__TYPE u_int32_t +#define RADIO130NM_TOP1__READ 0xffffffffU +#define RADIO130NM_TOP1__WRITE 0xffffffffU + +#endif /* __RADIO130NM_TOP1_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.TOP1 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__TOP1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_TOP2 */ +#ifndef __RADIO130NM_TOP2_MACRO__ +#define __RADIO130NM_TOP2_MACRO__ + +/* macros for field BYPASSVREGLO */ +#define RADIO130NM_TOP2__BYPASSVREGLO__SHIFT 0 +#define RADIO130NM_TOP2__BYPASSVREGLO__WIDTH 1 +#define RADIO130NM_TOP2__BYPASSVREGLO__MASK 0x00000001U +#define RADIO130NM_TOP2__BYPASSVREGLO__READ(src) (u_int32_t)(src) & 0x00000001U +#define RADIO130NM_TOP2__BYPASSVREGLO__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADIO130NM_TOP2__BYPASSVREGLO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADIO130NM_TOP2__BYPASSVREGLO__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADIO130NM_TOP2__BYPASSVREGLO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADIO130NM_TOP2__BYPASSVREGLO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field DATAOUTSEL */ +#define RADIO130NM_TOP2__DATAOUTSEL__SHIFT 1 +#define RADIO130NM_TOP2__DATAOUTSEL__WIDTH 2 +#define RADIO130NM_TOP2__DATAOUTSEL__MASK 0x00000006U +#define RADIO130NM_TOP2__DATAOUTSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000006U) >> 1) +#define RADIO130NM_TOP2__DATAOUTSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000006U) +#define RADIO130NM_TOP2__DATAOUTSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((u_int32_t)(src) <<\ + 1) & 0x00000006U) +#define RADIO130NM_TOP2__DATAOUTSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000006U))) + +/* macros for field TXPC_CLKDELAY */ +#define RADIO130NM_TOP2__TXPC_CLKDELAY__SHIFT 3 +#define RADIO130NM_TOP2__TXPC_CLKDELAY__WIDTH 1 +#define RADIO130NM_TOP2__TXPC_CLKDELAY__MASK 0x00000008U +#define RADIO130NM_TOP2__TXPC_CLKDELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RADIO130NM_TOP2__TXPC_CLKDELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RADIO130NM_TOP2__TXPC_CLKDELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RADIO130NM_TOP2__TXPC_CLKDELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RADIO130NM_TOP2__TXPC_CLKDELAY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RADIO130NM_TOP2__TXPC_CLKDELAY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field TXPC_XPDBS */ +#define RADIO130NM_TOP2__TXPC_XPDBS__SHIFT 4 +#define RADIO130NM_TOP2__TXPC_XPDBS__WIDTH 3 +#define RADIO130NM_TOP2__TXPC_XPDBS__MASK 0x00000070U +#define RADIO130NM_TOP2__TXPC_XPDBS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000070U) >> 4) +#define RADIO130NM_TOP2__TXPC_XPDBS__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define RADIO130NM_TOP2__TXPC_XPDBS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define RADIO130NM_TOP2__TXPC_XPDBS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field TXPC_TESTPWD */ +#define RADIO130NM_TOP2__TXPC_TESTPWD__SHIFT 7 +#define RADIO130NM_TOP2__TXPC_TESTPWD__WIDTH 1 +#define RADIO130NM_TOP2__TXPC_TESTPWD__MASK 0x00000080U +#define RADIO130NM_TOP2__TXPC_TESTPWD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RADIO130NM_TOP2__TXPC_TESTPWD__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RADIO130NM_TOP2__TXPC_TESTPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RADIO130NM_TOP2__TXPC_TESTPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RADIO130NM_TOP2__TXPC_TESTPWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RADIO130NM_TOP2__TXPC_TESTPWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field TXPC_TESTGAIN */ +#define RADIO130NM_TOP2__TXPC_TESTGAIN__SHIFT 8 +#define RADIO130NM_TOP2__TXPC_TESTGAIN__WIDTH 2 +#define RADIO130NM_TOP2__TXPC_TESTGAIN__MASK 0x00000300U +#define RADIO130NM_TOP2__TXPC_TESTGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define RADIO130NM_TOP2__TXPC_TESTGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define RADIO130NM_TOP2__TXPC_TESTGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define RADIO130NM_TOP2__TXPC_TESTGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field TXPC_TESTDAC */ +#define RADIO130NM_TOP2__TXPC_TESTDAC__SHIFT 10 +#define RADIO130NM_TOP2__TXPC_TESTDAC__WIDTH 6 +#define RADIO130NM_TOP2__TXPC_TESTDAC__MASK 0x0000fc00U +#define RADIO130NM_TOP2__TXPC_TESTDAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fc00U) >> 10) +#define RADIO130NM_TOP2__TXPC_TESTDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0000fc00U) +#define RADIO130NM_TOP2__TXPC_TESTDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0000fc00U) +#define RADIO130NM_TOP2__TXPC_TESTDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0000fc00U))) + +/* macros for field TXPC_TEST */ +#define RADIO130NM_TOP2__TXPC_TEST__SHIFT 16 +#define RADIO130NM_TOP2__TXPC_TEST__WIDTH 1 +#define RADIO130NM_TOP2__TXPC_TEST__MASK 0x00010000U +#define RADIO130NM_TOP2__TXPC_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define RADIO130NM_TOP2__TXPC_TEST__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define RADIO130NM_TOP2__TXPC_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define RADIO130NM_TOP2__TXPC_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define RADIO130NM_TOP2__TXPC_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define RADIO130NM_TOP2__TXPC_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field TXPC_NEGOUT */ +#define RADIO130NM_TOP2__TXPC_NEGOUT__SHIFT 17 +#define RADIO130NM_TOP2__TXPC_NEGOUT__WIDTH 1 +#define RADIO130NM_TOP2__TXPC_NEGOUT__MASK 0x00020000U +#define RADIO130NM_TOP2__TXPC_NEGOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define RADIO130NM_TOP2__TXPC_NEGOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define RADIO130NM_TOP2__TXPC_NEGOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RADIO130NM_TOP2__TXPC_NEGOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RADIO130NM_TOP2__TXPC_NEGOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RADIO130NM_TOP2__TXPC_NEGOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field XTALDIV */ +#define RADIO130NM_TOP2__XTALDIV__SHIFT 18 +#define RADIO130NM_TOP2__XTALDIV__WIDTH 2 +#define RADIO130NM_TOP2__XTALDIV__MASK 0x000c0000U +#define RADIO130NM_TOP2__XTALDIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x000c0000U) >> 18) +#define RADIO130NM_TOP2__XTALDIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define RADIO130NM_TOP2__XTALDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define RADIO130NM_TOP2__XTALDIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field LOCALBIAS2X */ +#define RADIO130NM_TOP2__LOCALBIAS2X__SHIFT 20 +#define RADIO130NM_TOP2__LOCALBIAS2X__WIDTH 1 +#define RADIO130NM_TOP2__LOCALBIAS2X__MASK 0x00100000U +#define RADIO130NM_TOP2__LOCALBIAS2X__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define RADIO130NM_TOP2__LOCALBIAS2X__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define RADIO130NM_TOP2__LOCALBIAS2X__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define RADIO130NM_TOP2__LOCALBIAS2X__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define RADIO130NM_TOP2__LOCALBIAS2X__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define RADIO130NM_TOP2__LOCALBIAS2X__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field LOCALBIAS */ +#define RADIO130NM_TOP2__LOCALBIAS__SHIFT 21 +#define RADIO130NM_TOP2__LOCALBIAS__WIDTH 1 +#define RADIO130NM_TOP2__LOCALBIAS__MASK 0x00200000U +#define RADIO130NM_TOP2__LOCALBIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define RADIO130NM_TOP2__LOCALBIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define RADIO130NM_TOP2__LOCALBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define RADIO130NM_TOP2__LOCALBIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define RADIO130NM_TOP2__LOCALBIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define RADIO130NM_TOP2__LOCALBIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field PWDCLKIND */ +#define RADIO130NM_TOP2__PWDCLKIND__SHIFT 22 +#define RADIO130NM_TOP2__PWDCLKIND__WIDTH 1 +#define RADIO130NM_TOP2__PWDCLKIND__MASK 0x00400000U +#define RADIO130NM_TOP2__PWDCLKIND__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define RADIO130NM_TOP2__PWDCLKIND__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define RADIO130NM_TOP2__PWDCLKIND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define RADIO130NM_TOP2__PWDCLKIND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define RADIO130NM_TOP2__PWDCLKIND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define RADIO130NM_TOP2__PWDCLKIND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field PWDXINPAD */ +#define RADIO130NM_TOP2__PWDXINPAD__SHIFT 23 +#define RADIO130NM_TOP2__PWDXINPAD__WIDTH 1 +#define RADIO130NM_TOP2__PWDXINPAD__MASK 0x00800000U +#define RADIO130NM_TOP2__PWDXINPAD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define RADIO130NM_TOP2__PWDXINPAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define RADIO130NM_TOP2__PWDXINPAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RADIO130NM_TOP2__PWDXINPAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RADIO130NM_TOP2__PWDXINPAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RADIO130NM_TOP2__PWDXINPAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field NOTCXODET */ +#define RADIO130NM_TOP2__NOTCXODET__SHIFT 24 +#define RADIO130NM_TOP2__NOTCXODET__WIDTH 1 +#define RADIO130NM_TOP2__NOTCXODET__MASK 0x01000000U +#define RADIO130NM_TOP2__NOTCXODET__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define RADIO130NM_TOP2__NOTCXODET__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RADIO130NM_TOP2__NOTCXODET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RADIO130NM_TOP2__NOTCXODET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RADIO130NM_TOP2__NOTCXODET__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RADIO130NM_TOP2__NOTCXODET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field XLNABUFIN */ +#define RADIO130NM_TOP2__XLNABUFIN__SHIFT 25 +#define RADIO130NM_TOP2__XLNABUFIN__WIDTH 1 +#define RADIO130NM_TOP2__XLNABUFIN__MASK 0x02000000U +#define RADIO130NM_TOP2__XLNABUFIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define RADIO130NM_TOP2__XLNABUFIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define RADIO130NM_TOP2__XLNABUFIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RADIO130NM_TOP2__XLNABUFIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RADIO130NM_TOP2__XLNABUFIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RADIO130NM_TOP2__XLNABUFIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field XLNAISEL */ +#define RADIO130NM_TOP2__XLNAISEL__SHIFT 26 +#define RADIO130NM_TOP2__XLNAISEL__WIDTH 2 +#define RADIO130NM_TOP2__XLNAISEL__MASK 0x0c000000U +#define RADIO130NM_TOP2__XLNAISEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0c000000U) >> 26) +#define RADIO130NM_TOP2__XLNAISEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x0c000000U) +#define RADIO130NM_TOP2__XLNAISEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define RADIO130NM_TOP2__XLNAISEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) + +/* macros for field XLNABUFMODE */ +#define RADIO130NM_TOP2__XLNABUFMODE__SHIFT 28 +#define RADIO130NM_TOP2__XLNABUFMODE__WIDTH 1 +#define RADIO130NM_TOP2__XLNABUFMODE__MASK 0x10000000U +#define RADIO130NM_TOP2__XLNABUFMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RADIO130NM_TOP2__XLNABUFMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RADIO130NM_TOP2__XLNABUFMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RADIO130NM_TOP2__XLNABUFMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RADIO130NM_TOP2__XLNABUFMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RADIO130NM_TOP2__XLNABUFMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field FORCE_XLDO_ON */ +#define RADIO130NM_TOP2__FORCE_XLDO_ON__SHIFT 29 +#define RADIO130NM_TOP2__FORCE_XLDO_ON__WIDTH 1 +#define RADIO130NM_TOP2__FORCE_XLDO_ON__MASK 0x20000000U +#define RADIO130NM_TOP2__FORCE_XLDO_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RADIO130NM_TOP2__FORCE_XLDO_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RADIO130NM_TOP2__FORCE_XLDO_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RADIO130NM_TOP2__FORCE_XLDO_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RADIO130NM_TOP2__FORCE_XLDO_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RADIO130NM_TOP2__FORCE_XLDO_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field XPABIAS_LVL */ +#define RADIO130NM_TOP2__XPABIAS_LVL__SHIFT 30 +#define RADIO130NM_TOP2__XPABIAS_LVL__WIDTH 2 +#define RADIO130NM_TOP2__XPABIAS_LVL__MASK 0xc0000000U +#define RADIO130NM_TOP2__XPABIAS_LVL__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define RADIO130NM_TOP2__XPABIAS_LVL__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define RADIO130NM_TOP2__XPABIAS_LVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define RADIO130NM_TOP2__XPABIAS_LVL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define RADIO130NM_TOP2__TYPE u_int32_t +#define RADIO130NM_TOP2__READ 0xffffffffU +#define RADIO130NM_TOP2__WRITE 0xffffffffU + +#endif /* __RADIO130NM_TOP2_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.TOP2 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__TOP2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RADIO130NM_TOP3 */ +#ifndef __RADIO130NM_TOP3_MACRO__ +#define __RADIO130NM_TOP3_MACRO__ + +/* macros for field VREGLO_ATBSEL */ +#define RADIO130NM_TOP3__VREGLO_ATBSEL__SHIFT 0 +#define RADIO130NM_TOP3__VREGLO_ATBSEL__WIDTH 3 +#define RADIO130NM_TOP3__VREGLO_ATBSEL__MASK 0x00000007U +#define RADIO130NM_TOP3__VREGLO_ATBSEL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define RADIO130NM_TOP3__VREGLO_ATBSEL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define RADIO130NM_TOP3__VREGLO_ATBSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define RADIO130NM_TOP3__VREGLO_ATBSEL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field PLLFBDIVB */ +#define RADIO130NM_TOP3__PLLFBDIVB__SHIFT 3 +#define RADIO130NM_TOP3__PLLFBDIVB__WIDTH 10 +#define RADIO130NM_TOP3__PLLFBDIVB__MASK 0x00001ff8U +#define RADIO130NM_TOP3__PLLFBDIVB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001ff8U) >> 3) +#define RADIO130NM_TOP3__PLLFBDIVB__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00001ff8U) +#define RADIO130NM_TOP3__PLLFBDIVB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001ff8U) | (((u_int32_t)(src) <<\ + 3) & 0x00001ff8U) +#define RADIO130NM_TOP3__PLLFBDIVB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00001ff8U))) + +/* macros for field PLLFBDIVA */ +#define RADIO130NM_TOP3__PLLFBDIVA__SHIFT 13 +#define RADIO130NM_TOP3__PLLFBDIVA__WIDTH 10 +#define RADIO130NM_TOP3__PLLFBDIVA__MASK 0x007fe000U +#define RADIO130NM_TOP3__PLLFBDIVA__READ(src) \ + (((u_int32_t)(src)\ + & 0x007fe000U) >> 13) +#define RADIO130NM_TOP3__PLLFBDIVA__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x007fe000U) +#define RADIO130NM_TOP3__PLLFBDIVA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007fe000U) | (((u_int32_t)(src) <<\ + 13) & 0x007fe000U) +#define RADIO130NM_TOP3__PLLFBDIVA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x007fe000U))) + +/* macros for field PLLREFDIVB */ +#define RADIO130NM_TOP3__PLLREFDIVB__SHIFT 23 +#define RADIO130NM_TOP3__PLLREFDIVB__WIDTH 4 +#define RADIO130NM_TOP3__PLLREFDIVB__MASK 0x07800000U +#define RADIO130NM_TOP3__PLLREFDIVB__READ(src) \ + (((u_int32_t)(src)\ + & 0x07800000U) >> 23) +#define RADIO130NM_TOP3__PLLREFDIVB__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x07800000U) +#define RADIO130NM_TOP3__PLLREFDIVB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07800000U) | (((u_int32_t)(src) <<\ + 23) & 0x07800000U) +#define RADIO130NM_TOP3__PLLREFDIVB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x07800000U))) + +/* macros for field PLLREFDIVA */ +#define RADIO130NM_TOP3__PLLREFDIVA__SHIFT 27 +#define RADIO130NM_TOP3__PLLREFDIVA__WIDTH 4 +#define RADIO130NM_TOP3__PLLREFDIVA__MASK 0x78000000U +#define RADIO130NM_TOP3__PLLREFDIVA__READ(src) \ + (((u_int32_t)(src)\ + & 0x78000000U) >> 27) +#define RADIO130NM_TOP3__PLLREFDIVA__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x78000000U) +#define RADIO130NM_TOP3__PLLREFDIVA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define RADIO130NM_TOP3__PLLREFDIVA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) + +/* macros for field LOCALPLLDIV */ +#define RADIO130NM_TOP3__LOCALPLLDIV__SHIFT 31 +#define RADIO130NM_TOP3__LOCALPLLDIV__WIDTH 1 +#define RADIO130NM_TOP3__LOCALPLLDIV__MASK 0x80000000U +#define RADIO130NM_TOP3__LOCALPLLDIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADIO130NM_TOP3__LOCALPLLDIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADIO130NM_TOP3__LOCALPLLDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADIO130NM_TOP3__LOCALPLLDIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADIO130NM_TOP3__LOCALPLLDIV__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADIO130NM_TOP3__LOCALPLLDIV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADIO130NM_TOP3__TYPE u_int32_t +#define RADIO130NM_TOP3__READ 0xffffffffU +#define RADIO130NM_TOP3__WRITE 0xffffffffU + +#endif /* __RADIO130NM_TOP3_MACRO__ */ + + +/* macros for merlin2_0_radio_reg_map.TOP3 */ +#define INST_MERLIN2_0_RADIO_REG_MAP__TOP3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::analog_intf_reg_csr::SW_OVERRIDE */ +#ifndef __ANALOG_INTF_REG_CSR__SW_OVERRIDE_MACRO__ +#define __ANALOG_INTF_REG_CSR__SW_OVERRIDE_MACRO__ + +/* macros for field ENABLE */ +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__SHIFT 0 +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__WIDTH 1 +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__MASK 0x00000001U +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field SUPDATE_DELAY */ +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__SHIFT 1 +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__WIDTH 1 +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__MASK 0x00000002U +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__TYPE u_int32_t +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__READ 0x00000003U +#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__WRITE 0x00000003U + +#endif /* __ANALOG_INTF_REG_CSR__SW_OVERRIDE_MACRO__ */ + + +/* macros for analog_intf_reg_csr_block.SW_OVERRIDE */ +#define INST_ANALOG_INTF_REG_CSR_BLOCK__SW_OVERRIDE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::analog_intf_reg_csr::SIN_VAL */ +#ifndef __ANALOG_INTF_REG_CSR__SIN_VAL_MACRO__ +#define __ANALOG_INTF_REG_CSR__SIN_VAL_MACRO__ + +/* macros for field SIN */ +#define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__SHIFT 0 +#define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__WIDTH 1 +#define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__MASK 0x00000001U +#define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define ANALOG_INTF_REG_CSR__SIN_VAL__TYPE u_int32_t +#define ANALOG_INTF_REG_CSR__SIN_VAL__READ 0x00000001U + +#endif /* __ANALOG_INTF_REG_CSR__SIN_VAL_MACRO__ */ + + +/* macros for analog_intf_reg_csr_block.SIN_VAL */ +#define INST_ANALOG_INTF_REG_CSR_BLOCK__SIN_VAL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::analog_intf_reg_csr::SW_SCLK */ +#ifndef __ANALOG_INTF_REG_CSR__SW_SCLK_MACRO__ +#define __ANALOG_INTF_REG_CSR__SW_SCLK_MACRO__ + +/* macros for field SW_SCLK */ +#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__SHIFT 0 +#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__WIDTH 1 +#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__MASK 0x00000001U +#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define ANALOG_INTF_REG_CSR__SW_SCLK__TYPE u_int32_t +#define ANALOG_INTF_REG_CSR__SW_SCLK__READ 0x00000001U +#define ANALOG_INTF_REG_CSR__SW_SCLK__WRITE 0x00000001U + +#endif /* __ANALOG_INTF_REG_CSR__SW_SCLK_MACRO__ */ + + +/* macros for analog_intf_reg_csr_block.SW_SCLK */ +#define INST_ANALOG_INTF_REG_CSR_BLOCK__SW_SCLK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::analog_intf_reg_csr::SW_CNTL */ +#ifndef __ANALOG_INTF_REG_CSR__SW_CNTL_MACRO__ +#define __ANALOG_INTF_REG_CSR__SW_CNTL_MACRO__ + +/* macros for field SW_SOUT */ +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__SHIFT 0 +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__WIDTH 1 +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__MASK 0x00000001U +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field SW_SUPDATE */ +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__SHIFT 1 +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__WIDTH 1 +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__MASK 0x00000002U +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SW_SCAPTURE */ +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__SHIFT 2 +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__WIDTH 1 +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__MASK 0x00000004U +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define ANALOG_INTF_REG_CSR__SW_CNTL__TYPE u_int32_t +#define ANALOG_INTF_REG_CSR__SW_CNTL__READ 0x00000007U +#define ANALOG_INTF_REG_CSR__SW_CNTL__WRITE 0x00000007U + +#endif /* __ANALOG_INTF_REG_CSR__SW_CNTL_MACRO__ */ + + +/* macros for analog_intf_reg_csr_block.SW_CNTL */ +#define INST_ANALOG_INTF_REG_CSR_BLOCK__SW_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_STA_ADDR_L32 */ +#ifndef __MAC_PCU_STA_ADDR_L32_MACRO__ +#define __MAC_PCU_STA_ADDR_L32_MACRO__ + +/* macros for field ADDR_31_0 */ +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__SHIFT 0 +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WIDTH 32 +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MASK 0xffffffffU +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_STA_ADDR_L32__TYPE u_int32_t +#define MAC_PCU_STA_ADDR_L32__READ 0xffffffffU +#define MAC_PCU_STA_ADDR_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_STA_ADDR_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_STA_ADDR_L32 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_STA_ADDR_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_STA_ADDR_U16 */ +#ifndef __MAC_PCU_STA_ADDR_U16_MACRO__ +#define __MAC_PCU_STA_ADDR_U16_MACRO__ + +/* macros for field ADDR_47_32 */ +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__SHIFT 0 +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WIDTH 16 +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MASK 0x0000ffffU +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field STA_AP */ +#define MAC_PCU_STA_ADDR_U16__STA_AP__SHIFT 16 +#define MAC_PCU_STA_ADDR_U16__STA_AP__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__STA_AP__MASK 0x00010000U +#define MAC_PCU_STA_ADDR_U16__STA_AP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_STA_ADDR_U16__STA_AP__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_STA_ADDR_U16__STA_AP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_STA_ADDR_U16__STA_AP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_STA_ADDR_U16__STA_AP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_STA_ADDR_U16__STA_AP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field ADHOC */ +#define MAC_PCU_STA_ADDR_U16__ADHOC__SHIFT 17 +#define MAC_PCU_STA_ADDR_U16__ADHOC__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__ADHOC__MASK 0x00020000U +#define MAC_PCU_STA_ADDR_U16__ADHOC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_STA_ADDR_U16__ADHOC__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_STA_ADDR_U16__ADHOC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_STA_ADDR_U16__ADHOC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_STA_ADDR_U16__ADHOC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_STA_ADDR_U16__ADHOC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field PW_SAVE */ +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__SHIFT 18 +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__MASK 0x00040000U +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field KEYSRCH_DIS */ +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__SHIFT 19 +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MASK 0x00080000U +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field PCF */ +#define MAC_PCU_STA_ADDR_U16__PCF__SHIFT 20 +#define MAC_PCU_STA_ADDR_U16__PCF__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__PCF__MASK 0x00100000U +#define MAC_PCU_STA_ADDR_U16__PCF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_STA_ADDR_U16__PCF__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_STA_ADDR_U16__PCF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_STA_ADDR_U16__PCF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_STA_ADDR_U16__PCF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_STA_ADDR_U16__PCF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field USE_DEFANT */ +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__SHIFT 21 +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MASK 0x00200000U +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field DEFANT_UPDATE */ +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__SHIFT 22 +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MASK 0x00400000U +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field RTS_USE_DEF */ +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__SHIFT 23 +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MASK 0x00800000U +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field ACKCTS_6MB */ +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__SHIFT 24 +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MASK 0x01000000U +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field BASE_RATE_11B */ +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__SHIFT 25 +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MASK 0x02000000U +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field SECTOR_SELF_GEN */ +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__SHIFT 26 +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MASK 0x04000000U +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field CRPT_MIC_ENABLE */ +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__SHIFT 27 +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MASK 0x08000000U +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field KSRCH_MODE */ +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__SHIFT 28 +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MASK 0x10000000U +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PRESERVE_SEQNUM */ +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__SHIFT 29 +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MASK 0x20000000U +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field CBCIV_ENDIAN */ +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__SHIFT 30 +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MASK 0x40000000U +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field ADHOC_MCAST_SEARCH */ +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__SHIFT 31 +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MASK 0x80000000U +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define MAC_PCU_STA_ADDR_U16__TYPE u_int32_t +#define MAC_PCU_STA_ADDR_U16__READ 0xffffffffU +#define MAC_PCU_STA_ADDR_U16__WRITE 0xffffffffU + +#endif /* __MAC_PCU_STA_ADDR_U16_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_STA_ADDR_U16 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_STA_ADDR_U16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID_L32 */ +#ifndef __MAC_PCU_BSSID_L32_MACRO__ +#define __MAC_PCU_BSSID_L32_MACRO__ + +/* macros for field ADDR */ +#define MAC_PCU_BSSID_L32__ADDR__SHIFT 0 +#define MAC_PCU_BSSID_L32__ADDR__WIDTH 32 +#define MAC_PCU_BSSID_L32__ADDR__MASK 0xffffffffU +#define MAC_PCU_BSSID_L32__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_BSSID_L32__ADDR__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_BSSID_L32__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BSSID_L32__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BSSID_L32__TYPE u_int32_t +#define MAC_PCU_BSSID_L32__READ 0xffffffffU +#define MAC_PCU_BSSID_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BSSID_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BSSID_L32 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BSSID_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID_U16 */ +#ifndef __MAC_PCU_BSSID_U16_MACRO__ +#define __MAC_PCU_BSSID_U16_MACRO__ + +/* macros for field ADDR */ +#define MAC_PCU_BSSID_U16__ADDR__SHIFT 0 +#define MAC_PCU_BSSID_U16__ADDR__WIDTH 16 +#define MAC_PCU_BSSID_U16__ADDR__MASK 0x0000ffffU +#define MAC_PCU_BSSID_U16__ADDR__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_BSSID_U16__ADDR__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_PCU_BSSID_U16__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_BSSID_U16__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field AID */ +#define MAC_PCU_BSSID_U16__AID__SHIFT 16 +#define MAC_PCU_BSSID_U16__AID__WIDTH 11 +#define MAC_PCU_BSSID_U16__AID__MASK 0x07ff0000U +#define MAC_PCU_BSSID_U16__AID__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define MAC_PCU_BSSID_U16__AID__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define MAC_PCU_BSSID_U16__AID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define MAC_PCU_BSSID_U16__AID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) +#define MAC_PCU_BSSID_U16__TYPE u_int32_t +#define MAC_PCU_BSSID_U16__READ 0x07ffffffU +#define MAC_PCU_BSSID_U16__WRITE 0x07ffffffU + +#endif /* __MAC_PCU_BSSID_U16_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BSSID_U16 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BSSID_U16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BCN_RSSI_AVE */ +#ifndef __MAC_PCU_BCN_RSSI_AVE_MACRO__ +#define __MAC_PCU_BCN_RSSI_AVE_MACRO__ + +/* macros for field AVE_VALUE */ +#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__SHIFT 0 +#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__WIDTH 12 +#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__MASK 0x00000fffU +#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define MAC_PCU_BCN_RSSI_AVE__TYPE u_int32_t +#define MAC_PCU_BCN_RSSI_AVE__READ 0x00000fffU + +#endif /* __MAC_PCU_BCN_RSSI_AVE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BCN_RSSI_AVE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BCN_RSSI_AVE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_ACK_CTS_TIMEOUT */ +#ifndef __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__ +#define __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__ + +/* macros for field ACK_TIMEOUT */ +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__SHIFT 0 +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WIDTH 14 +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MASK 0x00003fffU +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field CTS_TIMEOUT */ +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__SHIFT 16 +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WIDTH 14 +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MASK 0x3fff0000U +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0x3fff0000U) >> 16) +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x3fff0000U) +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x3fff0000U) +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x3fff0000U))) +#define MAC_PCU_ACK_CTS_TIMEOUT__TYPE u_int32_t +#define MAC_PCU_ACK_CTS_TIMEOUT__READ 0x3fff3fffU +#define MAC_PCU_ACK_CTS_TIMEOUT__WRITE 0x3fff3fffU + +#endif /* __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_ACK_CTS_TIMEOUT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_ACK_CTS_TIMEOUT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BCN_RSSI_CTL */ +#ifndef __MAC_PCU_BCN_RSSI_CTL_MACRO__ +#define __MAC_PCU_BCN_RSSI_CTL_MACRO__ + +/* macros for field RSSI_THRESH */ +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__SHIFT 0 +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WIDTH 8 +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MASK 0x000000ffU +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field MISS_THRESH */ +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__SHIFT 8 +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WIDTH 8 +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MASK 0x0000ff00U +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field WEIGHT */ +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__SHIFT 24 +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WIDTH 5 +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MASK 0x1f000000U +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f000000U) >> 24) +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x1f000000U) +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x1f000000U) +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x1f000000U))) + +/* macros for field RESET */ +#define MAC_PCU_BCN_RSSI_CTL__RESET__SHIFT 29 +#define MAC_PCU_BCN_RSSI_CTL__RESET__WIDTH 1 +#define MAC_PCU_BCN_RSSI_CTL__RESET__MASK 0x20000000U +#define MAC_PCU_BCN_RSSI_CTL__RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_BCN_RSSI_CTL__RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_BCN_RSSI_CTL__RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_BCN_RSSI_CTL__RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_BCN_RSSI_CTL__RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_BCN_RSSI_CTL__RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define MAC_PCU_BCN_RSSI_CTL__TYPE u_int32_t +#define MAC_PCU_BCN_RSSI_CTL__READ 0x3f00ffffU +#define MAC_PCU_BCN_RSSI_CTL__WRITE 0x3f00ffffU + +#endif /* __MAC_PCU_BCN_RSSI_CTL_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BCN_RSSI_CTL */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BCN_RSSI_CTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_USEC_LATENCY */ +#ifndef __MAC_PCU_USEC_LATENCY_MACRO__ +#define __MAC_PCU_USEC_LATENCY_MACRO__ + +/* macros for field USEC */ +#define MAC_PCU_USEC_LATENCY__USEC__SHIFT 0 +#define MAC_PCU_USEC_LATENCY__USEC__WIDTH 8 +#define MAC_PCU_USEC_LATENCY__USEC__MASK 0x000000ffU +#define MAC_PCU_USEC_LATENCY__USEC__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_USEC_LATENCY__USEC__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_USEC_LATENCY__USEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_USEC_LATENCY__USEC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field TX_LATENCY */ +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__SHIFT 14 +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__WIDTH 9 +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__MASK 0x007fc000U +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__READ(src) \ + (((u_int32_t)(src)\ + & 0x007fc000U) >> 14) +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x007fc000U) +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x007fc000U) +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x007fc000U))) + +/* macros for field RX_LATENCY */ +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__SHIFT 23 +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__WIDTH 6 +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__MASK 0x1f800000U +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f800000U) >> 23) +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x1f800000U) +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x1f800000U) +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x1f800000U))) +#define MAC_PCU_USEC_LATENCY__TYPE u_int32_t +#define MAC_PCU_USEC_LATENCY__READ 0x1fffc0ffU +#define MAC_PCU_USEC_LATENCY__WRITE 0x1fffc0ffU + +#endif /* __MAC_PCU_USEC_LATENCY_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_USEC_LATENCY */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_USEC_LATENCY__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RESET_TSF */ +#ifndef __MAC_PCU_RESET_TSF_MACRO__ +#define __MAC_PCU_RESET_TSF_MACRO__ + +/* macros for field ONE_SHOT */ +#define MAC_PCU_RESET_TSF__ONE_SHOT__SHIFT 24 +#define MAC_PCU_RESET_TSF__ONE_SHOT__WIDTH 1 +#define MAC_PCU_RESET_TSF__ONE_SHOT__MASK 0x01000000U +#define MAC_PCU_RESET_TSF__ONE_SHOT__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_RESET_TSF__ONE_SHOT__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_RESET_TSF__ONE_SHOT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_RESET_TSF__ONE_SHOT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_RESET_TSF__ONE_SHOT__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_RESET_TSF__ONE_SHOT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field ONE_SHOT2 */ +#define MAC_PCU_RESET_TSF__ONE_SHOT2__SHIFT 25 +#define MAC_PCU_RESET_TSF__ONE_SHOT2__WIDTH 1 +#define MAC_PCU_RESET_TSF__ONE_SHOT2__MASK 0x02000000U +#define MAC_PCU_RESET_TSF__ONE_SHOT2__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_RESET_TSF__ONE_SHOT2__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_RESET_TSF__ONE_SHOT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_RESET_TSF__ONE_SHOT2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_RESET_TSF__ONE_SHOT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_RESET_TSF__ONE_SHOT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) +#define MAC_PCU_RESET_TSF__TYPE u_int32_t +#define MAC_PCU_RESET_TSF__READ 0x03000000U +#define MAC_PCU_RESET_TSF__WRITE 0x03000000U + +#endif /* __MAC_PCU_RESET_TSF_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_RESET_TSF */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_RESET_TSF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MAX_CFP_DUR */ +#ifndef __MAC_PCU_MAX_CFP_DUR_MACRO__ +#define __MAC_PCU_MAX_CFP_DUR_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_MAX_CFP_DUR__VALUE__SHIFT 0 +#define MAC_PCU_MAX_CFP_DUR__VALUE__WIDTH 16 +#define MAC_PCU_MAX_CFP_DUR__VALUE__MASK 0x0000ffffU +#define MAC_PCU_MAX_CFP_DUR__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_MAX_CFP_DUR__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_PCU_MAX_CFP_DUR__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_MAX_CFP_DUR__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field USEC_FRAC_NUMERATOR */ +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__SHIFT 16 +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WIDTH 4 +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MASK 0x000f0000U +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field USEC_FRAC_DENOMINATOR */ +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__SHIFT 24 +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WIDTH 4 +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MASK 0x0f000000U +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) +#define MAC_PCU_MAX_CFP_DUR__TYPE u_int32_t +#define MAC_PCU_MAX_CFP_DUR__READ 0x0f0fffffU +#define MAC_PCU_MAX_CFP_DUR__WRITE 0x0f0fffffU + +#endif /* __MAC_PCU_MAX_CFP_DUR_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_MAX_CFP_DUR */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_MAX_CFP_DUR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_FILTER */ +#ifndef __MAC_PCU_RX_FILTER_MACRO__ +#define __MAC_PCU_RX_FILTER_MACRO__ + +/* macros for field UNICAST */ +#define MAC_PCU_RX_FILTER__UNICAST__SHIFT 0 +#define MAC_PCU_RX_FILTER__UNICAST__WIDTH 1 +#define MAC_PCU_RX_FILTER__UNICAST__MASK 0x00000001U +#define MAC_PCU_RX_FILTER__UNICAST__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_RX_FILTER__UNICAST__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_PCU_RX_FILTER__UNICAST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_RX_FILTER__UNICAST__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_RX_FILTER__UNICAST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_RX_FILTER__UNICAST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field MULTICAST */ +#define MAC_PCU_RX_FILTER__MULTICAST__SHIFT 1 +#define MAC_PCU_RX_FILTER__MULTICAST__WIDTH 1 +#define MAC_PCU_RX_FILTER__MULTICAST__MASK 0x00000002U +#define MAC_PCU_RX_FILTER__MULTICAST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_RX_FILTER__MULTICAST__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_RX_FILTER__MULTICAST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_RX_FILTER__MULTICAST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_RX_FILTER__MULTICAST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_RX_FILTER__MULTICAST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field BROADCAST */ +#define MAC_PCU_RX_FILTER__BROADCAST__SHIFT 2 +#define MAC_PCU_RX_FILTER__BROADCAST__WIDTH 1 +#define MAC_PCU_RX_FILTER__BROADCAST__MASK 0x00000004U +#define MAC_PCU_RX_FILTER__BROADCAST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_RX_FILTER__BROADCAST__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_RX_FILTER__BROADCAST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_RX_FILTER__BROADCAST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_RX_FILTER__BROADCAST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_RX_FILTER__BROADCAST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field CONTROL */ +#define MAC_PCU_RX_FILTER__CONTROL__SHIFT 3 +#define MAC_PCU_RX_FILTER__CONTROL__WIDTH 1 +#define MAC_PCU_RX_FILTER__CONTROL__MASK 0x00000008U +#define MAC_PCU_RX_FILTER__CONTROL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_RX_FILTER__CONTROL__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_RX_FILTER__CONTROL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_RX_FILTER__CONTROL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_RX_FILTER__CONTROL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_RX_FILTER__CONTROL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BEACON */ +#define MAC_PCU_RX_FILTER__BEACON__SHIFT 4 +#define MAC_PCU_RX_FILTER__BEACON__WIDTH 1 +#define MAC_PCU_RX_FILTER__BEACON__MASK 0x00000010U +#define MAC_PCU_RX_FILTER__BEACON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_RX_FILTER__BEACON__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_RX_FILTER__BEACON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_RX_FILTER__BEACON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_RX_FILTER__BEACON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_RX_FILTER__BEACON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PROMISCUOUS */ +#define MAC_PCU_RX_FILTER__PROMISCUOUS__SHIFT 5 +#define MAC_PCU_RX_FILTER__PROMISCUOUS__WIDTH 1 +#define MAC_PCU_RX_FILTER__PROMISCUOUS__MASK 0x00000020U +#define MAC_PCU_RX_FILTER__PROMISCUOUS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_RX_FILTER__PROMISCUOUS__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_RX_FILTER__PROMISCUOUS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_RX_FILTER__PROMISCUOUS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_RX_FILTER__PROMISCUOUS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_RX_FILTER__PROMISCUOUS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field XR_POLL */ +#define MAC_PCU_RX_FILTER__XR_POLL__SHIFT 6 +#define MAC_PCU_RX_FILTER__XR_POLL__WIDTH 1 +#define MAC_PCU_RX_FILTER__XR_POLL__MASK 0x00000040U +#define MAC_PCU_RX_FILTER__XR_POLL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_RX_FILTER__XR_POLL__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_RX_FILTER__XR_POLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_RX_FILTER__XR_POLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_RX_FILTER__XR_POLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_RX_FILTER__XR_POLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field PROBE_REQ */ +#define MAC_PCU_RX_FILTER__PROBE_REQ__SHIFT 7 +#define MAC_PCU_RX_FILTER__PROBE_REQ__WIDTH 1 +#define MAC_PCU_RX_FILTER__PROBE_REQ__MASK 0x00000080U +#define MAC_PCU_RX_FILTER__PROBE_REQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_RX_FILTER__PROBE_REQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_RX_FILTER__PROBE_REQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_RX_FILTER__PROBE_REQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_RX_FILTER__PROBE_REQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_RX_FILTER__PROBE_REQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field SYNC_FRAME */ +#define MAC_PCU_RX_FILTER__SYNC_FRAME__SHIFT 8 +#define MAC_PCU_RX_FILTER__SYNC_FRAME__WIDTH 1 +#define MAC_PCU_RX_FILTER__SYNC_FRAME__MASK 0x00000100U +#define MAC_PCU_RX_FILTER__SYNC_FRAME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_RX_FILTER__SYNC_FRAME__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_RX_FILTER__SYNC_FRAME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_RX_FILTER__SYNC_FRAME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_RX_FILTER__SYNC_FRAME__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_RX_FILTER__SYNC_FRAME__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field MY_BEACON */ +#define MAC_PCU_RX_FILTER__MY_BEACON__SHIFT 9 +#define MAC_PCU_RX_FILTER__MY_BEACON__WIDTH 1 +#define MAC_PCU_RX_FILTER__MY_BEACON__MASK 0x00000200U +#define MAC_PCU_RX_FILTER__MY_BEACON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_RX_FILTER__MY_BEACON__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_RX_FILTER__MY_BEACON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_RX_FILTER__MY_BEACON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_RX_FILTER__MY_BEACON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_RX_FILTER__MY_BEACON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field COMPRESSED_BAR */ +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__SHIFT 10 +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WIDTH 1 +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MASK 0x00000400U +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field COMPRESSED_BA */ +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__SHIFT 11 +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__WIDTH 1 +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__MASK 0x00000800U +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field UNCOMPRESSED_BA_BAR */ +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__SHIFT 12 +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WIDTH 1 +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MASK 0x00001000U +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field ASSUME_RADAR */ +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__SHIFT 13 +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__WIDTH 1 +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__MASK 0x00002000U +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field PS_POLL */ +#define MAC_PCU_RX_FILTER__PS_POLL__SHIFT 14 +#define MAC_PCU_RX_FILTER__PS_POLL__WIDTH 1 +#define MAC_PCU_RX_FILTER__PS_POLL__MASK 0x00004000U +#define MAC_PCU_RX_FILTER__PS_POLL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define MAC_PCU_RX_FILTER__PS_POLL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define MAC_PCU_RX_FILTER__PS_POLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define MAC_PCU_RX_FILTER__PS_POLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define MAC_PCU_RX_FILTER__PS_POLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define MAC_PCU_RX_FILTER__PS_POLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field MCAST_BCAST_ALL */ +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__SHIFT 15 +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WIDTH 1 +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MASK 0x00008000U +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field RST_DLMTR_CNT_DISABLE */ +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__SHIFT 16 +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WIDTH 1 +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MASK 0x00010000U +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field HW_BCN_PROC_ENABLE */ +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__SHIFT 17 +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WIDTH 1 +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MASK 0x00020000U +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field MGMT_ACTION_MCAST */ +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__SHIFT 18 +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WIDTH 1 +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MASK 0x00040000U +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) +#define MAC_PCU_RX_FILTER__TYPE u_int32_t +#define MAC_PCU_RX_FILTER__READ 0x0007ffffU +#define MAC_PCU_RX_FILTER__WRITE 0x0007ffffU + +#endif /* __MAC_PCU_RX_FILTER_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_RX_FILTER */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_RX_FILTER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MCAST_FILTER_L32 */ +#ifndef __MAC_PCU_MCAST_FILTER_L32_MACRO__ +#define __MAC_PCU_MCAST_FILTER_L32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_MCAST_FILTER_L32__VALUE__SHIFT 0 +#define MAC_PCU_MCAST_FILTER_L32__VALUE__WIDTH 32 +#define MAC_PCU_MCAST_FILTER_L32__VALUE__MASK 0xffffffffU +#define MAC_PCU_MCAST_FILTER_L32__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_MCAST_FILTER_L32__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_MCAST_FILTER_L32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_MCAST_FILTER_L32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_MCAST_FILTER_L32__TYPE u_int32_t +#define MAC_PCU_MCAST_FILTER_L32__READ 0xffffffffU +#define MAC_PCU_MCAST_FILTER_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_MCAST_FILTER_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_MCAST_FILTER_L32 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_MCAST_FILTER_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MCAST_FILTER_U32 */ +#ifndef __MAC_PCU_MCAST_FILTER_U32_MACRO__ +#define __MAC_PCU_MCAST_FILTER_U32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_MCAST_FILTER_U32__VALUE__SHIFT 0 +#define MAC_PCU_MCAST_FILTER_U32__VALUE__WIDTH 32 +#define MAC_PCU_MCAST_FILTER_U32__VALUE__MASK 0xffffffffU +#define MAC_PCU_MCAST_FILTER_U32__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_MCAST_FILTER_U32__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_MCAST_FILTER_U32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_MCAST_FILTER_U32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_MCAST_FILTER_U32__TYPE u_int32_t +#define MAC_PCU_MCAST_FILTER_U32__READ 0xffffffffU +#define MAC_PCU_MCAST_FILTER_U32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_MCAST_FILTER_U32_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_MCAST_FILTER_U32 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_MCAST_FILTER_U32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_DIAG_SW */ +#ifndef __MAC_PCU_DIAG_SW_MACRO__ +#define __MAC_PCU_DIAG_SW_MACRO__ + +/* macros for field INVALID_KEY_NO_ACK */ +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__SHIFT 0 +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WIDTH 1 +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MASK 0x00000001U +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field NO_ACK */ +#define MAC_PCU_DIAG_SW__NO_ACK__SHIFT 1 +#define MAC_PCU_DIAG_SW__NO_ACK__WIDTH 1 +#define MAC_PCU_DIAG_SW__NO_ACK__MASK 0x00000002U +#define MAC_PCU_DIAG_SW__NO_ACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_DIAG_SW__NO_ACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_DIAG_SW__NO_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_DIAG_SW__NO_ACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_DIAG_SW__NO_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_DIAG_SW__NO_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field NO_CTS */ +#define MAC_PCU_DIAG_SW__NO_CTS__SHIFT 2 +#define MAC_PCU_DIAG_SW__NO_CTS__WIDTH 1 +#define MAC_PCU_DIAG_SW__NO_CTS__MASK 0x00000004U +#define MAC_PCU_DIAG_SW__NO_CTS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_DIAG_SW__NO_CTS__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_DIAG_SW__NO_CTS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_DIAG_SW__NO_CTS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_DIAG_SW__NO_CTS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_DIAG_SW__NO_CTS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field NO_ENCRYPT */ +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__SHIFT 3 +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__WIDTH 1 +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__MASK 0x00000008U +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field NO_DECRYPT */ +#define MAC_PCU_DIAG_SW__NO_DECRYPT__SHIFT 4 +#define MAC_PCU_DIAG_SW__NO_DECRYPT__WIDTH 1 +#define MAC_PCU_DIAG_SW__NO_DECRYPT__MASK 0x00000010U +#define MAC_PCU_DIAG_SW__NO_DECRYPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_DIAG_SW__NO_DECRYPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_DIAG_SW__NO_DECRYPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_DIAG_SW__NO_DECRYPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_DIAG_SW__NO_DECRYPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_DIAG_SW__NO_DECRYPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field HALT_RX */ +#define MAC_PCU_DIAG_SW__HALT_RX__SHIFT 5 +#define MAC_PCU_DIAG_SW__HALT_RX__WIDTH 1 +#define MAC_PCU_DIAG_SW__HALT_RX__MASK 0x00000020U +#define MAC_PCU_DIAG_SW__HALT_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_DIAG_SW__HALT_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_DIAG_SW__HALT_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_DIAG_SW__HALT_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_DIAG_SW__HALT_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_DIAG_SW__HALT_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field LOOP_BACK */ +#define MAC_PCU_DIAG_SW__LOOP_BACK__SHIFT 6 +#define MAC_PCU_DIAG_SW__LOOP_BACK__WIDTH 1 +#define MAC_PCU_DIAG_SW__LOOP_BACK__MASK 0x00000040U +#define MAC_PCU_DIAG_SW__LOOP_BACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_DIAG_SW__LOOP_BACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_DIAG_SW__LOOP_BACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_DIAG_SW__LOOP_BACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_DIAG_SW__LOOP_BACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_DIAG_SW__LOOP_BACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field CORRUPT_FCS */ +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__SHIFT 7 +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__WIDTH 1 +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__MASK 0x00000080U +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field DUMP_CHAN_INFO */ +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__SHIFT 8 +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WIDTH 1 +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MASK 0x00000100U +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field ACCEPT_NON_V0 */ +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__SHIFT 17 +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WIDTH 1 +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MASK 0x00020000U +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field OBS_SEL_1_0 */ +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__SHIFT 18 +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WIDTH 2 +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MASK 0x000c0000U +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000c0000U) >> 18) +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field RX_CLEAR_HIGH */ +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__SHIFT 20 +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WIDTH 1 +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MASK 0x00100000U +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field IGNORE_NAV */ +#define MAC_PCU_DIAG_SW__IGNORE_NAV__SHIFT 21 +#define MAC_PCU_DIAG_SW__IGNORE_NAV__WIDTH 1 +#define MAC_PCU_DIAG_SW__IGNORE_NAV__MASK 0x00200000U +#define MAC_PCU_DIAG_SW__IGNORE_NAV__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_DIAG_SW__IGNORE_NAV__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_DIAG_SW__IGNORE_NAV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_DIAG_SW__IGNORE_NAV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_DIAG_SW__IGNORE_NAV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_DIAG_SW__IGNORE_NAV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field CHAN_IDLE_HIGH */ +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__SHIFT 22 +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WIDTH 1 +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MASK 0x00400000U +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field PHYERR_ENABLE_EIFS_CTL */ +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__SHIFT 23 +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WIDTH 1 +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MASK 0x00800000U +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field DUAL_CHAIN_CHAN_INFO */ +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__SHIFT 24 +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WIDTH 1 +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MASK 0x01000000U +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field FORCE_RX_ABORT */ +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__SHIFT 25 +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WIDTH 1 +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MASK 0x02000000U +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field SATURATE_CYCLE_CNT */ +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__SHIFT 26 +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WIDTH 1 +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MASK 0x04000000U +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field OBS_SEL_2 */ +#define MAC_PCU_DIAG_SW__OBS_SEL_2__SHIFT 27 +#define MAC_PCU_DIAG_SW__OBS_SEL_2__WIDTH 1 +#define MAC_PCU_DIAG_SW__OBS_SEL_2__MASK 0x08000000U +#define MAC_PCU_DIAG_SW__OBS_SEL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_PCU_DIAG_SW__OBS_SEL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_PCU_DIAG_SW__OBS_SEL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_PCU_DIAG_SW__OBS_SEL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_PCU_DIAG_SW__OBS_SEL_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_PCU_DIAG_SW__OBS_SEL_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field RX_CLEAR_CTL_LOW */ +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__SHIFT 28 +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WIDTH 1 +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MASK 0x10000000U +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field RX_CLEAR_EXT_LOW */ +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__SHIFT 29 +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WIDTH 1 +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MASK 0x20000000U +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field DEBUG_MODE */ +#define MAC_PCU_DIAG_SW__DEBUG_MODE__SHIFT 30 +#define MAC_PCU_DIAG_SW__DEBUG_MODE__WIDTH 2 +#define MAC_PCU_DIAG_SW__DEBUG_MODE__MASK 0xc0000000U +#define MAC_PCU_DIAG_SW__DEBUG_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define MAC_PCU_DIAG_SW__DEBUG_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define MAC_PCU_DIAG_SW__DEBUG_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define MAC_PCU_DIAG_SW__DEBUG_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define MAC_PCU_DIAG_SW__TYPE u_int32_t +#define MAC_PCU_DIAG_SW__READ 0xfffe01ffU +#define MAC_PCU_DIAG_SW__WRITE 0xfffe01ffU + +#endif /* __MAC_PCU_DIAG_SW_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_DIAG_SW */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_DIAG_SW__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_L32 */ +#ifndef __MAC_PCU_TSF_L32_MACRO__ +#define __MAC_PCU_TSF_L32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TSF_L32__VALUE__SHIFT 0 +#define MAC_PCU_TSF_L32__VALUE__WIDTH 32 +#define MAC_PCU_TSF_L32__VALUE__MASK 0xffffffffU +#define MAC_PCU_TSF_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TSF_L32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TSF_L32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TSF_L32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TSF_L32__TYPE u_int32_t +#define MAC_PCU_TSF_L32__READ 0xffffffffU +#define MAC_PCU_TSF_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TSF_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TSF_L32 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TSF_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_U32 */ +#ifndef __MAC_PCU_TSF_U32_MACRO__ +#define __MAC_PCU_TSF_U32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TSF_U32__VALUE__SHIFT 0 +#define MAC_PCU_TSF_U32__VALUE__WIDTH 32 +#define MAC_PCU_TSF_U32__VALUE__MASK 0xffffffffU +#define MAC_PCU_TSF_U32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TSF_U32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TSF_U32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TSF_U32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TSF_U32__TYPE u_int32_t +#define MAC_PCU_TSF_U32__READ 0xffffffffU +#define MAC_PCU_TSF_U32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TSF_U32_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TSF_U32 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TSF_U32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TST_ADDAC */ +#ifndef __MAC_PCU_TST_ADDAC_MACRO__ +#define __MAC_PCU_TST_ADDAC_MACRO__ + +/* macros for field CONT_TX */ +#define MAC_PCU_TST_ADDAC__CONT_TX__SHIFT 0 +#define MAC_PCU_TST_ADDAC__CONT_TX__WIDTH 1 +#define MAC_PCU_TST_ADDAC__CONT_TX__MASK 0x00000001U +#define MAC_PCU_TST_ADDAC__CONT_TX__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_TST_ADDAC__CONT_TX__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_PCU_TST_ADDAC__CONT_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_TST_ADDAC__CONT_TX__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_TST_ADDAC__CONT_TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_TST_ADDAC__CONT_TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field TESTMODE */ +#define MAC_PCU_TST_ADDAC__TESTMODE__SHIFT 1 +#define MAC_PCU_TST_ADDAC__TESTMODE__WIDTH 1 +#define MAC_PCU_TST_ADDAC__TESTMODE__MASK 0x00000002U +#define MAC_PCU_TST_ADDAC__TESTMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_TST_ADDAC__TESTMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_TST_ADDAC__TESTMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_TST_ADDAC__TESTMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_TST_ADDAC__TESTMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_TST_ADDAC__TESTMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field LOOP */ +#define MAC_PCU_TST_ADDAC__LOOP__SHIFT 2 +#define MAC_PCU_TST_ADDAC__LOOP__WIDTH 1 +#define MAC_PCU_TST_ADDAC__LOOP__MASK 0x00000004U +#define MAC_PCU_TST_ADDAC__LOOP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_TST_ADDAC__LOOP__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_TST_ADDAC__LOOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_TST_ADDAC__LOOP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_TST_ADDAC__LOOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_TST_ADDAC__LOOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field LOOP_LEN */ +#define MAC_PCU_TST_ADDAC__LOOP_LEN__SHIFT 3 +#define MAC_PCU_TST_ADDAC__LOOP_LEN__WIDTH 11 +#define MAC_PCU_TST_ADDAC__LOOP_LEN__MASK 0x00003ff8U +#define MAC_PCU_TST_ADDAC__LOOP_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003ff8U) >> 3) +#define MAC_PCU_TST_ADDAC__LOOP_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00003ff8U) +#define MAC_PCU_TST_ADDAC__LOOP_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003ff8U) | (((u_int32_t)(src) <<\ + 3) & 0x00003ff8U) +#define MAC_PCU_TST_ADDAC__LOOP_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00003ff8U))) + +/* macros for field UPPER_8B */ +#define MAC_PCU_TST_ADDAC__UPPER_8B__SHIFT 14 +#define MAC_PCU_TST_ADDAC__UPPER_8B__WIDTH 1 +#define MAC_PCU_TST_ADDAC__UPPER_8B__MASK 0x00004000U +#define MAC_PCU_TST_ADDAC__UPPER_8B__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define MAC_PCU_TST_ADDAC__UPPER_8B__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define MAC_PCU_TST_ADDAC__UPPER_8B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define MAC_PCU_TST_ADDAC__UPPER_8B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define MAC_PCU_TST_ADDAC__UPPER_8B__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define MAC_PCU_TST_ADDAC__UPPER_8B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field TRIG_SEL */ +#define MAC_PCU_TST_ADDAC__TRIG_SEL__SHIFT 16 +#define MAC_PCU_TST_ADDAC__TRIG_SEL__WIDTH 1 +#define MAC_PCU_TST_ADDAC__TRIG_SEL__MASK 0x00010000U +#define MAC_PCU_TST_ADDAC__TRIG_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_TST_ADDAC__TRIG_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_TST_ADDAC__TRIG_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_TST_ADDAC__TRIG_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_TST_ADDAC__TRIG_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_TST_ADDAC__TRIG_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field TRIG_POLARITY */ +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__SHIFT 17 +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WIDTH 1 +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MASK 0x00020000U +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field CONT_TEST */ +#define MAC_PCU_TST_ADDAC__CONT_TEST__SHIFT 18 +#define MAC_PCU_TST_ADDAC__CONT_TEST__WIDTH 1 +#define MAC_PCU_TST_ADDAC__CONT_TEST__MASK 0x00040000U +#define MAC_PCU_TST_ADDAC__CONT_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_TST_ADDAC__CONT_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_TST_ADDAC__CONT_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field TEST_CAPTURE */ +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__SHIFT 19 +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WIDTH 1 +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MASK 0x00080000U +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field TEST_ARM */ +#define MAC_PCU_TST_ADDAC__TEST_ARM__SHIFT 20 +#define MAC_PCU_TST_ADDAC__TEST_ARM__WIDTH 1 +#define MAC_PCU_TST_ADDAC__TEST_ARM__MASK 0x00100000U +#define MAC_PCU_TST_ADDAC__TEST_ARM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_TST_ADDAC__TEST_ARM__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_TST_ADDAC__TEST_ARM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_TST_ADDAC__TEST_ARM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_TST_ADDAC__TEST_ARM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_TST_ADDAC__TEST_ARM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) +#define MAC_PCU_TST_ADDAC__TYPE u_int32_t +#define MAC_PCU_TST_ADDAC__READ 0x001f7fffU +#define MAC_PCU_TST_ADDAC__WRITE 0x001f7fffU + +#endif /* __MAC_PCU_TST_ADDAC_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TST_ADDAC */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TST_ADDAC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_DEF_ANTENNA */ +#ifndef __MAC_PCU_DEF_ANTENNA_MACRO__ +#define __MAC_PCU_DEF_ANTENNA_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_DEF_ANTENNA__VALUE__SHIFT 0 +#define MAC_PCU_DEF_ANTENNA__VALUE__WIDTH 24 +#define MAC_PCU_DEF_ANTENNA__VALUE__MASK 0x00ffffffU +#define MAC_PCU_DEF_ANTENNA__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_PCU_DEF_ANTENNA__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) +#define MAC_PCU_DEF_ANTENNA__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_DEF_ANTENNA__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) + +/* macros for field TX_DEF_ANT_SEL */ +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__SHIFT 24 +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MASK 0x01000000U +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field SLOW_TX_ANT_EN */ +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__SHIFT 25 +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MASK 0x02000000U +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field TX_CUR_ANT */ +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__SHIFT 26 +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MASK 0x04000000U +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field FAST_DEF_ANT */ +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__SHIFT 27 +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MASK 0x08000000U +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field RX_LNA_CONFIG_SEL */ +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__SHIFT 28 +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MASK 0x10000000U +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field FAST_TX_ANT_EN */ +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__SHIFT 29 +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MASK 0x20000000U +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define MAC_PCU_DEF_ANTENNA__TYPE u_int32_t +#define MAC_PCU_DEF_ANTENNA__READ 0x3fffffffU +#define MAC_PCU_DEF_ANTENNA__WRITE 0x3fffffffU + +#endif /* __MAC_PCU_DEF_ANTENNA_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_DEF_ANTENNA */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_DEF_ANTENNA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AES_MUTE_MASK_0 */ +#ifndef __MAC_PCU_AES_MUTE_MASK_0_MACRO__ +#define __MAC_PCU_AES_MUTE_MASK_0_MACRO__ + +/* macros for field FC */ +#define MAC_PCU_AES_MUTE_MASK_0__FC__SHIFT 0 +#define MAC_PCU_AES_MUTE_MASK_0__FC__WIDTH 16 +#define MAC_PCU_AES_MUTE_MASK_0__FC__MASK 0x0000ffffU +#define MAC_PCU_AES_MUTE_MASK_0__FC__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_AES_MUTE_MASK_0__FC__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_AES_MUTE_MASK_0__FC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_AES_MUTE_MASK_0__FC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field QOS */ +#define MAC_PCU_AES_MUTE_MASK_0__QOS__SHIFT 16 +#define MAC_PCU_AES_MUTE_MASK_0__QOS__WIDTH 16 +#define MAC_PCU_AES_MUTE_MASK_0__QOS__MASK 0xffff0000U +#define MAC_PCU_AES_MUTE_MASK_0__QOS__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_AES_MUTE_MASK_0__QOS__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_AES_MUTE_MASK_0__QOS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_AES_MUTE_MASK_0__QOS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_AES_MUTE_MASK_0__TYPE u_int32_t +#define MAC_PCU_AES_MUTE_MASK_0__READ 0xffffffffU +#define MAC_PCU_AES_MUTE_MASK_0__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AES_MUTE_MASK_0_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_AES_MUTE_MASK_0 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_AES_MUTE_MASK_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AES_MUTE_MASK_1 */ +#ifndef __MAC_PCU_AES_MUTE_MASK_1_MACRO__ +#define __MAC_PCU_AES_MUTE_MASK_1_MACRO__ + +/* macros for field SEQ */ +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__SHIFT 0 +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__WIDTH 16 +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__MASK 0x0000ffffU +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field FC_MGMT */ +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__SHIFT 16 +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WIDTH 16 +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MASK 0xffff0000U +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_AES_MUTE_MASK_1__TYPE u_int32_t +#define MAC_PCU_AES_MUTE_MASK_1__READ 0xffffffffU +#define MAC_PCU_AES_MUTE_MASK_1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AES_MUTE_MASK_1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_AES_MUTE_MASK_1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_AES_MUTE_MASK_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_GATED_CLKS */ +#ifndef __MAC_PCU_GATED_CLKS_MACRO__ +#define __MAC_PCU_GATED_CLKS_MACRO__ + +/* macros for field GATED_TX */ +#define MAC_PCU_GATED_CLKS__GATED_TX__SHIFT 1 +#define MAC_PCU_GATED_CLKS__GATED_TX__WIDTH 1 +#define MAC_PCU_GATED_CLKS__GATED_TX__MASK 0x00000002U +#define MAC_PCU_GATED_CLKS__GATED_TX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_GATED_CLKS__GATED_TX__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_GATED_CLKS__GATED_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_GATED_CLKS__GATED_TX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_GATED_CLKS__GATED_TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_GATED_CLKS__GATED_TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field GATED_RX */ +#define MAC_PCU_GATED_CLKS__GATED_RX__SHIFT 2 +#define MAC_PCU_GATED_CLKS__GATED_RX__WIDTH 1 +#define MAC_PCU_GATED_CLKS__GATED_RX__MASK 0x00000004U +#define MAC_PCU_GATED_CLKS__GATED_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_GATED_CLKS__GATED_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_GATED_CLKS__GATED_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_GATED_CLKS__GATED_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_GATED_CLKS__GATED_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_GATED_CLKS__GATED_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field GATED_REG */ +#define MAC_PCU_GATED_CLKS__GATED_REG__SHIFT 3 +#define MAC_PCU_GATED_CLKS__GATED_REG__WIDTH 1 +#define MAC_PCU_GATED_CLKS__GATED_REG__MASK 0x00000008U +#define MAC_PCU_GATED_CLKS__GATED_REG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_GATED_CLKS__GATED_REG__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_GATED_CLKS__GATED_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_GATED_CLKS__GATED_REG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_GATED_CLKS__GATED_REG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_GATED_CLKS__GATED_REG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define MAC_PCU_GATED_CLKS__TYPE u_int32_t +#define MAC_PCU_GATED_CLKS__READ 0x0000000eU +#define MAC_PCU_GATED_CLKS__WRITE 0x0000000eU + +#endif /* __MAC_PCU_GATED_CLKS_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_GATED_CLKS */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_GATED_CLKS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_OBS_BUS_2 */ +#ifndef __MAC_PCU_OBS_BUS_2_MACRO__ +#define __MAC_PCU_OBS_BUS_2_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_OBS_BUS_2__VALUE__SHIFT 0 +#define MAC_PCU_OBS_BUS_2__VALUE__WIDTH 18 +#define MAC_PCU_OBS_BUS_2__VALUE__MASK 0x0003ffffU +#define MAC_PCU_OBS_BUS_2__VALUE__READ(src) (u_int32_t)(src) & 0x0003ffffU + +/* macros for field WCF_STATE */ +#define MAC_PCU_OBS_BUS_2__WCF_STATE__SHIFT 18 +#define MAC_PCU_OBS_BUS_2__WCF_STATE__WIDTH 4 +#define MAC_PCU_OBS_BUS_2__WCF_STATE__MASK 0x003c0000U +#define MAC_PCU_OBS_BUS_2__WCF_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x003c0000U) >> 18) + +/* macros for field WCF0_FULL */ +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__SHIFT 22 +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__WIDTH 1 +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__MASK 0x00400000U +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field WCF1_FULL */ +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__SHIFT 23 +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__WIDTH 1 +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__MASK 0x00800000U +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field WCF_COUNT */ +#define MAC_PCU_OBS_BUS_2__WCF_COUNT__SHIFT 24 +#define MAC_PCU_OBS_BUS_2__WCF_COUNT__WIDTH 5 +#define MAC_PCU_OBS_BUS_2__WCF_COUNT__MASK 0x1f000000U +#define MAC_PCU_OBS_BUS_2__WCF_COUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f000000U) >> 24) + +/* macros for field MACBB_ALL_AWAKE */ +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__SHIFT 29 +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__WIDTH 1 +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__MASK 0x20000000U +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define MAC_PCU_OBS_BUS_2__TYPE u_int32_t +#define MAC_PCU_OBS_BUS_2__READ 0x3fffffffU + +#endif /* __MAC_PCU_OBS_BUS_2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_OBS_BUS_2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_OBS_BUS_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_OBS_BUS_1 */ +#ifndef __MAC_PCU_OBS_BUS_1_MACRO__ +#define __MAC_PCU_OBS_BUS_1_MACRO__ + +/* macros for field PCU_DIRECTED */ +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__SHIFT 0 +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__MASK 0x00000001U +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PCU_RX_END */ +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__SHIFT 1 +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__MASK 0x00000002U +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field RX_WEP */ +#define MAC_PCU_OBS_BUS_1__RX_WEP__SHIFT 2 +#define MAC_PCU_OBS_BUS_1__RX_WEP__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__RX_WEP__MASK 0x00000004U +#define MAC_PCU_OBS_BUS_1__RX_WEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_OBS_BUS_1__RX_WEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_OBS_BUS_1__RX_WEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field RX_MY_BEACON */ +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__SHIFT 3 +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__MASK 0x00000008U +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field FILTER_PASS */ +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__SHIFT 4 +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__MASK 0x00000010U +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field TX_HCF */ +#define MAC_PCU_OBS_BUS_1__TX_HCF__SHIFT 5 +#define MAC_PCU_OBS_BUS_1__TX_HCF__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__TX_HCF__MASK 0x00000020U +#define MAC_PCU_OBS_BUS_1__TX_HCF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_OBS_BUS_1__TX_HCF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_OBS_BUS_1__TX_HCF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field TM_QUIET_TIME */ +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__SHIFT 6 +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__MASK 0x00000040U +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field PCU_CHANNEL_IDLE */ +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__SHIFT 7 +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__MASK 0x00000080U +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field TX_HOLD */ +#define MAC_PCU_OBS_BUS_1__TX_HOLD__SHIFT 8 +#define MAC_PCU_OBS_BUS_1__TX_HOLD__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__TX_HOLD__MASK 0x00000100U +#define MAC_PCU_OBS_BUS_1__TX_HOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_OBS_BUS_1__TX_HOLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_OBS_BUS_1__TX_HOLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field TX_FRAME */ +#define MAC_PCU_OBS_BUS_1__TX_FRAME__SHIFT 9 +#define MAC_PCU_OBS_BUS_1__TX_FRAME__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__TX_FRAME__MASK 0x00000200U +#define MAC_PCU_OBS_BUS_1__TX_FRAME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_OBS_BUS_1__TX_FRAME__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_OBS_BUS_1__TX_FRAME__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field RX_FRAME */ +#define MAC_PCU_OBS_BUS_1__RX_FRAME__SHIFT 10 +#define MAC_PCU_OBS_BUS_1__RX_FRAME__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__RX_FRAME__MASK 0x00000400U +#define MAC_PCU_OBS_BUS_1__RX_FRAME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_PCU_OBS_BUS_1__RX_FRAME__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_PCU_OBS_BUS_1__RX_FRAME__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field RX_CLEAR */ +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__SHIFT 11 +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__MASK 0x00000800U +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field WEP_STATE */ +#define MAC_PCU_OBS_BUS_1__WEP_STATE__SHIFT 12 +#define MAC_PCU_OBS_BUS_1__WEP_STATE__WIDTH 6 +#define MAC_PCU_OBS_BUS_1__WEP_STATE__MASK 0x0003f000U +#define MAC_PCU_OBS_BUS_1__WEP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) + +/* macros for field RX_STATE */ +#define MAC_PCU_OBS_BUS_1__RX_STATE__SHIFT 20 +#define MAC_PCU_OBS_BUS_1__RX_STATE__WIDTH 5 +#define MAC_PCU_OBS_BUS_1__RX_STATE__MASK 0x01f00000U +#define MAC_PCU_OBS_BUS_1__RX_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) + +/* macros for field TX_STATE */ +#define MAC_PCU_OBS_BUS_1__TX_STATE__SHIFT 25 +#define MAC_PCU_OBS_BUS_1__TX_STATE__WIDTH 6 +#define MAC_PCU_OBS_BUS_1__TX_STATE__MASK 0x7e000000U +#define MAC_PCU_OBS_BUS_1__TX_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x7e000000U) >> 25) +#define MAC_PCU_OBS_BUS_1__TYPE u_int32_t +#define MAC_PCU_OBS_BUS_1__READ 0x7ff3ffffU + +#endif /* __MAC_PCU_OBS_BUS_1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_OBS_BUS_1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_OBS_BUS_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_DYM_MIMO_PWR_SAVE */ +#ifndef __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__ +#define __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__ + +/* macros for field USE_MAC_CTRL */ +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__SHIFT 0 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WIDTH 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MASK 0x00000001U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field HW_CTRL_EN */ +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__SHIFT 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WIDTH 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MASK 0x00000002U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SW_CHAIN_MASK_SEL */ +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__SHIFT 2 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WIDTH 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MASK 0x00000004U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field LOW_PWR_CHAIN_MASK */ +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__SHIFT 4 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WIDTH 3 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MASK 0x00000070U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000070U) >> 4) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field HI_PWR_CHAIN_MASK */ +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__SHIFT 8 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WIDTH 3 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MASK 0x00000700U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__TYPE u_int32_t +#define MAC_PCU_DYM_MIMO_PWR_SAVE__READ 0x00000777U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__WRITE 0x00000777U + +#endif /* __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_DYM_MIMO_PWR_SAVE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_DYM_MIMO_PWR_SAVE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB */ +#ifndef __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__ +#define __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__SHIFT 0 +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WIDTH 32 +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MASK 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__TYPE u_int32_t +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__READ 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB */ +#ifndef __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__ +#define __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__SHIFT 0 +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WIDTH 32 +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MASK 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__TYPE u_int32_t +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__READ 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LAST_BEACON_TSF */ +#ifndef __MAC_PCU_LAST_BEACON_TSF_MACRO__ +#define __MAC_PCU_LAST_BEACON_TSF_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_LAST_BEACON_TSF__VALUE__SHIFT 0 +#define MAC_PCU_LAST_BEACON_TSF__VALUE__WIDTH 32 +#define MAC_PCU_LAST_BEACON_TSF__VALUE__MASK 0xffffffffU +#define MAC_PCU_LAST_BEACON_TSF__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_LAST_BEACON_TSF__TYPE u_int32_t +#define MAC_PCU_LAST_BEACON_TSF__READ 0xffffffffU + +#endif /* __MAC_PCU_LAST_BEACON_TSF_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_LAST_BEACON_TSF */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_LAST_BEACON_TSF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_NAV */ +#ifndef __MAC_PCU_NAV_MACRO__ +#define __MAC_PCU_NAV_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_NAV__VALUE__SHIFT 0 +#define MAC_PCU_NAV__VALUE__WIDTH 26 +#define MAC_PCU_NAV__VALUE__MASK 0x03ffffffU +#define MAC_PCU_NAV__VALUE__READ(src) (u_int32_t)(src) & 0x03ffffffU +#define MAC_PCU_NAV__VALUE__WRITE(src) ((u_int32_t)(src) & 0x03ffffffU) +#define MAC_PCU_NAV__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ffffffU) | ((u_int32_t)(src) &\ + 0x03ffffffU) +#define MAC_PCU_NAV__VALUE__VERIFY(src) (!(((u_int32_t)(src) & ~0x03ffffffU))) +#define MAC_PCU_NAV__TYPE u_int32_t +#define MAC_PCU_NAV__READ 0x03ffffffU +#define MAC_PCU_NAV__WRITE 0x03ffffffU + +#endif /* __MAC_PCU_NAV_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_NAV */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_NAV__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RTS_SUCCESS_CNT */ +#ifndef __MAC_PCU_RTS_SUCCESS_CNT_MACRO__ +#define __MAC_PCU_RTS_SUCCESS_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__SHIFT 0 +#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__WIDTH 16 +#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_PCU_RTS_SUCCESS_CNT__TYPE u_int32_t +#define MAC_PCU_RTS_SUCCESS_CNT__READ 0x0000ffffU + +#endif /* __MAC_PCU_RTS_SUCCESS_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_RTS_SUCCESS_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_RTS_SUCCESS_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RTS_FAIL_CNT */ +#ifndef __MAC_PCU_RTS_FAIL_CNT_MACRO__ +#define __MAC_PCU_RTS_FAIL_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_RTS_FAIL_CNT__VALUE__SHIFT 0 +#define MAC_PCU_RTS_FAIL_CNT__VALUE__WIDTH 16 +#define MAC_PCU_RTS_FAIL_CNT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_RTS_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_RTS_FAIL_CNT__TYPE u_int32_t +#define MAC_PCU_RTS_FAIL_CNT__READ 0x0000ffffU + +#endif /* __MAC_PCU_RTS_FAIL_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_RTS_FAIL_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_RTS_FAIL_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_ACK_FAIL_CNT */ +#ifndef __MAC_PCU_ACK_FAIL_CNT_MACRO__ +#define __MAC_PCU_ACK_FAIL_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_ACK_FAIL_CNT__VALUE__SHIFT 0 +#define MAC_PCU_ACK_FAIL_CNT__VALUE__WIDTH 16 +#define MAC_PCU_ACK_FAIL_CNT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_ACK_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_ACK_FAIL_CNT__TYPE u_int32_t +#define MAC_PCU_ACK_FAIL_CNT__READ 0x0000ffffU + +#endif /* __MAC_PCU_ACK_FAIL_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_ACK_FAIL_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_ACK_FAIL_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_FCS_FAIL_CNT */ +#ifndef __MAC_PCU_FCS_FAIL_CNT_MACRO__ +#define __MAC_PCU_FCS_FAIL_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_FCS_FAIL_CNT__VALUE__SHIFT 0 +#define MAC_PCU_FCS_FAIL_CNT__VALUE__WIDTH 16 +#define MAC_PCU_FCS_FAIL_CNT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_FCS_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_FCS_FAIL_CNT__TYPE u_int32_t +#define MAC_PCU_FCS_FAIL_CNT__READ 0x0000ffffU + +#endif /* __MAC_PCU_FCS_FAIL_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_FCS_FAIL_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_FCS_FAIL_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BEACON_CNT */ +#ifndef __MAC_PCU_BEACON_CNT_MACRO__ +#define __MAC_PCU_BEACON_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BEACON_CNT__VALUE__SHIFT 0 +#define MAC_PCU_BEACON_CNT__VALUE__WIDTH 16 +#define MAC_PCU_BEACON_CNT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_BEACON_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_BEACON_CNT__TYPE u_int32_t +#define MAC_PCU_BEACON_CNT__READ 0x0000ffffU + +#endif /* __MAC_PCU_BEACON_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BEACON_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BEACON_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_SLOT_ALERT_CNTL */ +#ifndef __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__ +#define __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__SHIFT 0 +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WIDTH 16 +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MASK 0x0000ffffU +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__TYPE u_int32_t +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__READ 0x0000ffffU +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TDMA_SLOT_ALERT_CNTL */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TDMA_SLOT_ALERT_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BASIC_SET */ +#ifndef __MAC_PCU_BASIC_SET_MACRO__ +#define __MAC_PCU_BASIC_SET_MACRO__ + +/* macros for field MCS */ +#define MAC_PCU_BASIC_SET__MCS__SHIFT 0 +#define MAC_PCU_BASIC_SET__MCS__WIDTH 32 +#define MAC_PCU_BASIC_SET__MCS__MASK 0xffffffffU +#define MAC_PCU_BASIC_SET__MCS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_BASIC_SET__MCS__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_BASIC_SET__MCS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BASIC_SET__MCS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BASIC_SET__TYPE u_int32_t +#define MAC_PCU_BASIC_SET__READ 0xffffffffU +#define MAC_PCU_BASIC_SET__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BASIC_SET_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BASIC_SET */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BASIC_SET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MGMT_SEQ */ +#ifndef __MAC_PCU_MGMT_SEQ_MACRO__ +#define __MAC_PCU_MGMT_SEQ_MACRO__ + +/* macros for field MIN */ +#define MAC_PCU_MGMT_SEQ__MIN__SHIFT 0 +#define MAC_PCU_MGMT_SEQ__MIN__WIDTH 12 +#define MAC_PCU_MGMT_SEQ__MIN__MASK 0x00000fffU +#define MAC_PCU_MGMT_SEQ__MIN__READ(src) (u_int32_t)(src) & 0x00000fffU +#define MAC_PCU_MGMT_SEQ__MIN__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) +#define MAC_PCU_MGMT_SEQ__MIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define MAC_PCU_MGMT_SEQ__MIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field MAX */ +#define MAC_PCU_MGMT_SEQ__MAX__SHIFT 16 +#define MAC_PCU_MGMT_SEQ__MAX__WIDTH 12 +#define MAC_PCU_MGMT_SEQ__MAX__MASK 0x0fff0000U +#define MAC_PCU_MGMT_SEQ__MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fff0000U) >> 16) +#define MAC_PCU_MGMT_SEQ__MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x0fff0000U) +#define MAC_PCU_MGMT_SEQ__MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x0fff0000U) +#define MAC_PCU_MGMT_SEQ__MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x0fff0000U))) +#define MAC_PCU_MGMT_SEQ__TYPE u_int32_t +#define MAC_PCU_MGMT_SEQ__READ 0x0fff0fffU +#define MAC_PCU_MGMT_SEQ__WRITE 0x0fff0fffU + +#endif /* __MAC_PCU_MGMT_SEQ_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_MGMT_SEQ */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_MGMT_SEQ__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BF_RPT1 */ +#ifndef __MAC_PCU_BF_RPT1_MACRO__ +#define __MAC_PCU_BF_RPT1_MACRO__ + +/* macros for field V_ACTION_VALUE */ +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__SHIFT 0 +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WIDTH 8 +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MASK 0x000000ffU +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field CV_ACTION_VALUE */ +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__SHIFT 8 +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WIDTH 8 +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MASK 0x0000ff00U +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field CATEGORY_VALUE */ +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__SHIFT 16 +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WIDTH 8 +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MASK 0x00ff0000U +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field FRAME_SUBTYPE_VALUE */ +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__SHIFT 24 +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WIDTH 4 +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MASK 0x0f000000U +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) + +/* macros for field FRAME_TYPE_VALUE */ +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__SHIFT 28 +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WIDTH 2 +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MASK 0x30000000U +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x30000000U) >> 28) +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x30000000U) +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) +#define MAC_PCU_BF_RPT1__TYPE u_int32_t +#define MAC_PCU_BF_RPT1__READ 0x3fffffffU +#define MAC_PCU_BF_RPT1__WRITE 0x3fffffffU + +#endif /* __MAC_PCU_BF_RPT1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BF_RPT1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BF_RPT1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BF_RPT2 */ +#ifndef __MAC_PCU_BF_RPT2_MACRO__ +#define __MAC_PCU_BF_RPT2_MACRO__ + +/* macros for field FRAME_SUBTYPE_VALUE */ +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__SHIFT 0 +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WIDTH 4 +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MASK 0x0000000fU +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define MAC_PCU_BF_RPT2__TYPE u_int32_t +#define MAC_PCU_BF_RPT2__READ 0x0000000fU +#define MAC_PCU_BF_RPT2__WRITE 0x0000000fU + +#endif /* __MAC_PCU_BF_RPT2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BF_RPT2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BF_RPT2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_1 */ +#ifndef __MAC_PCU_TX_ANT_1_MACRO__ +#define __MAC_PCU_TX_ANT_1_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TX_ANT_1__VALUE__SHIFT 0 +#define MAC_PCU_TX_ANT_1__VALUE__WIDTH 32 +#define MAC_PCU_TX_ANT_1__VALUE__MASK 0xffffffffU +#define MAC_PCU_TX_ANT_1__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TX_ANT_1__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TX_ANT_1__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TX_ANT_1__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TX_ANT_1__TYPE u_int32_t +#define MAC_PCU_TX_ANT_1__READ 0xffffffffU +#define MAC_PCU_TX_ANT_1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TX_ANT_1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TX_ANT_1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TX_ANT_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_2 */ +#ifndef __MAC_PCU_TX_ANT_2_MACRO__ +#define __MAC_PCU_TX_ANT_2_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TX_ANT_2__VALUE__SHIFT 0 +#define MAC_PCU_TX_ANT_2__VALUE__WIDTH 32 +#define MAC_PCU_TX_ANT_2__VALUE__MASK 0xffffffffU +#define MAC_PCU_TX_ANT_2__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TX_ANT_2__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TX_ANT_2__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TX_ANT_2__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TX_ANT_2__TYPE u_int32_t +#define MAC_PCU_TX_ANT_2__READ 0xffffffffU +#define MAC_PCU_TX_ANT_2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TX_ANT_2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TX_ANT_2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TX_ANT_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_3 */ +#ifndef __MAC_PCU_TX_ANT_3_MACRO__ +#define __MAC_PCU_TX_ANT_3_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TX_ANT_3__VALUE__SHIFT 0 +#define MAC_PCU_TX_ANT_3__VALUE__WIDTH 32 +#define MAC_PCU_TX_ANT_3__VALUE__MASK 0xffffffffU +#define MAC_PCU_TX_ANT_3__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TX_ANT_3__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TX_ANT_3__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TX_ANT_3__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TX_ANT_3__TYPE u_int32_t +#define MAC_PCU_TX_ANT_3__READ 0xffffffffU +#define MAC_PCU_TX_ANT_3__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TX_ANT_3_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TX_ANT_3 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TX_ANT_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_4 */ +#ifndef __MAC_PCU_TX_ANT_4_MACRO__ +#define __MAC_PCU_TX_ANT_4_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TX_ANT_4__VALUE__SHIFT 0 +#define MAC_PCU_TX_ANT_4__VALUE__WIDTH 32 +#define MAC_PCU_TX_ANT_4__VALUE__MASK 0xffffffffU +#define MAC_PCU_TX_ANT_4__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TX_ANT_4__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TX_ANT_4__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TX_ANT_4__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TX_ANT_4__TYPE u_int32_t +#define MAC_PCU_TX_ANT_4__READ 0xffffffffU +#define MAC_PCU_TX_ANT_4__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TX_ANT_4_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TX_ANT_4 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TX_ANT_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRMODE */ +#ifndef __MAC_PCU_XRMODE_MACRO__ +#define __MAC_PCU_XRMODE_MACRO__ + +/* macros for field POLL_TYPE */ +#define MAC_PCU_XRMODE__POLL_TYPE__SHIFT 0 +#define MAC_PCU_XRMODE__POLL_TYPE__WIDTH 6 +#define MAC_PCU_XRMODE__POLL_TYPE__MASK 0x0000003fU +#define MAC_PCU_XRMODE__POLL_TYPE__READ(src) (u_int32_t)(src) & 0x0000003fU +#define MAC_PCU_XRMODE__POLL_TYPE__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define MAC_PCU_XRMODE__POLL_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define MAC_PCU_XRMODE__POLL_TYPE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field WAIT_FOR_POLL */ +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__SHIFT 7 +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__WIDTH 1 +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__MASK 0x00000080U +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field FRAME_HOLD */ +#define MAC_PCU_XRMODE__FRAME_HOLD__SHIFT 20 +#define MAC_PCU_XRMODE__FRAME_HOLD__WIDTH 12 +#define MAC_PCU_XRMODE__FRAME_HOLD__MASK 0xfff00000U +#define MAC_PCU_XRMODE__FRAME_HOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0xfff00000U) >> 20) +#define MAC_PCU_XRMODE__FRAME_HOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0xfff00000U) +#define MAC_PCU_XRMODE__FRAME_HOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfff00000U) | (((u_int32_t)(src) <<\ + 20) & 0xfff00000U) +#define MAC_PCU_XRMODE__FRAME_HOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0xfff00000U))) +#define MAC_PCU_XRMODE__TYPE u_int32_t +#define MAC_PCU_XRMODE__READ 0xfff000bfU +#define MAC_PCU_XRMODE__WRITE 0xfff000bfU + +#endif /* __MAC_PCU_XRMODE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_XRMODE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_XRMODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRDEL */ +#ifndef __MAC_PCU_XRDEL_MACRO__ +#define __MAC_PCU_XRDEL_MACRO__ + +/* macros for field SLOT_DELAY */ +#define MAC_PCU_XRDEL__SLOT_DELAY__SHIFT 0 +#define MAC_PCU_XRDEL__SLOT_DELAY__WIDTH 16 +#define MAC_PCU_XRDEL__SLOT_DELAY__MASK 0x0000ffffU +#define MAC_PCU_XRDEL__SLOT_DELAY__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_XRDEL__SLOT_DELAY__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_PCU_XRDEL__SLOT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_XRDEL__SLOT_DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field CHIRP_DATA_DELAY */ +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__SHIFT 16 +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WIDTH 16 +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MASK 0xffff0000U +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_XRDEL__TYPE u_int32_t +#define MAC_PCU_XRDEL__READ 0xffffffffU +#define MAC_PCU_XRDEL__WRITE 0xffffffffU + +#endif /* __MAC_PCU_XRDEL_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_XRDEL */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_XRDEL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRTO */ +#ifndef __MAC_PCU_XRTO_MACRO__ +#define __MAC_PCU_XRTO_MACRO__ + +/* macros for field CHIRP_TIMEOUT */ +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__SHIFT 0 +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__WIDTH 16 +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__MASK 0x0000ffffU +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field POLL_TIMEOUT */ +#define MAC_PCU_XRTO__POLL_TIMEOUT__SHIFT 16 +#define MAC_PCU_XRTO__POLL_TIMEOUT__WIDTH 16 +#define MAC_PCU_XRTO__POLL_TIMEOUT__MASK 0xffff0000U +#define MAC_PCU_XRTO__POLL_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_XRTO__POLL_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_XRTO__POLL_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_XRTO__POLL_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_XRTO__TYPE u_int32_t +#define MAC_PCU_XRTO__READ 0xffffffffU +#define MAC_PCU_XRTO__WRITE 0xffffffffU + +#endif /* __MAC_PCU_XRTO_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_XRTO */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_XRTO__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRCRP */ +#ifndef __MAC_PCU_XRCRP_MACRO__ +#define __MAC_PCU_XRCRP_MACRO__ + +/* macros for field SEND_CHIRP */ +#define MAC_PCU_XRCRP__SEND_CHIRP__SHIFT 0 +#define MAC_PCU_XRCRP__SEND_CHIRP__WIDTH 1 +#define MAC_PCU_XRCRP__SEND_CHIRP__MASK 0x00000001U +#define MAC_PCU_XRCRP__SEND_CHIRP__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_XRCRP__SEND_CHIRP__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_PCU_XRCRP__SEND_CHIRP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_XRCRP__SEND_CHIRP__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_XRCRP__SEND_CHIRP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_XRCRP__SEND_CHIRP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field CHIRP_GAP */ +#define MAC_PCU_XRCRP__CHIRP_GAP__SHIFT 16 +#define MAC_PCU_XRCRP__CHIRP_GAP__WIDTH 16 +#define MAC_PCU_XRCRP__CHIRP_GAP__MASK 0xffff0000U +#define MAC_PCU_XRCRP__CHIRP_GAP__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_XRCRP__CHIRP_GAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_XRCRP__CHIRP_GAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_XRCRP__CHIRP_GAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_XRCRP__TYPE u_int32_t +#define MAC_PCU_XRCRP__READ 0xffff0001U +#define MAC_PCU_XRCRP__WRITE 0xffff0001U + +#endif /* __MAC_PCU_XRCRP_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_XRCRP */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_XRCRP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRSTMP */ +#ifndef __MAC_PCU_XRSTMP_MACRO__ +#define __MAC_PCU_XRSTMP_MACRO__ + +/* macros for field RX_ABORT_RSSI */ +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__SHIFT 0 +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WIDTH 1 +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MASK 0x00000001U +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RX_ABORT_BSSID */ +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__SHIFT 1 +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WIDTH 1 +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MASK 0x00000002U +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field TX_STOMP_RSSI */ +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__SHIFT 2 +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WIDTH 1 +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MASK 0x00000004U +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field TX_STOMP_BSSID */ +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__SHIFT 3 +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WIDTH 1 +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MASK 0x00000008U +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field TX_STOMP_DATA */ +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__SHIFT 4 +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__WIDTH 1 +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__MASK 0x00000010U +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field RX_ABORT_DATA */ +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__SHIFT 5 +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__WIDTH 1 +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__MASK 0x00000020U +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field TX_STOMP_RSSI_THRESH */ +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__SHIFT 8 +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WIDTH 8 +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MASK 0x0000ff00U +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field RX_ABORT_RSSI_THRESH */ +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__SHIFT 16 +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WIDTH 8 +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MASK 0x00ff0000U +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MAC_PCU_XRSTMP__TYPE u_int32_t +#define MAC_PCU_XRSTMP__READ 0x00ffff3fU +#define MAC_PCU_XRSTMP__WRITE 0x00ffff3fU + +#endif /* __MAC_PCU_XRSTMP_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_XRSTMP */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_XRSTMP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP1 */ +#ifndef __MAC_PCU_SLP1_MACRO__ +#define __MAC_PCU_SLP1_MACRO__ + +/* macros for field ASSUME_DTIM */ +#define MAC_PCU_SLP1__ASSUME_DTIM__SHIFT 19 +#define MAC_PCU_SLP1__ASSUME_DTIM__WIDTH 1 +#define MAC_PCU_SLP1__ASSUME_DTIM__MASK 0x00080000U +#define MAC_PCU_SLP1__ASSUME_DTIM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_SLP1__ASSUME_DTIM__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_SLP1__ASSUME_DTIM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_SLP1__ASSUME_DTIM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_SLP1__ASSUME_DTIM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_SLP1__ASSUME_DTIM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field CAB_TIMEOUT */ +#define MAC_PCU_SLP1__CAB_TIMEOUT__SHIFT 21 +#define MAC_PCU_SLP1__CAB_TIMEOUT__WIDTH 11 +#define MAC_PCU_SLP1__CAB_TIMEOUT__MASK 0xffe00000U +#define MAC_PCU_SLP1__CAB_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0xffe00000U) >> 21) +#define MAC_PCU_SLP1__CAB_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0xffe00000U) +#define MAC_PCU_SLP1__CAB_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffe00000U) | (((u_int32_t)(src) <<\ + 21) & 0xffe00000U) +#define MAC_PCU_SLP1__CAB_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0xffe00000U))) +#define MAC_PCU_SLP1__TYPE u_int32_t +#define MAC_PCU_SLP1__READ 0xffe80000U +#define MAC_PCU_SLP1__WRITE 0xffe80000U + +#endif /* __MAC_PCU_SLP1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_SLP1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_SLP1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP2 */ +#ifndef __MAC_PCU_SLP2_MACRO__ +#define __MAC_PCU_SLP2_MACRO__ + +/* macros for field BEACON_TIMEOUT */ +#define MAC_PCU_SLP2__BEACON_TIMEOUT__SHIFT 21 +#define MAC_PCU_SLP2__BEACON_TIMEOUT__WIDTH 11 +#define MAC_PCU_SLP2__BEACON_TIMEOUT__MASK 0xffe00000U +#define MAC_PCU_SLP2__BEACON_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0xffe00000U) >> 21) +#define MAC_PCU_SLP2__BEACON_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0xffe00000U) +#define MAC_PCU_SLP2__BEACON_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffe00000U) | (((u_int32_t)(src) <<\ + 21) & 0xffe00000U) +#define MAC_PCU_SLP2__BEACON_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0xffe00000U))) +#define MAC_PCU_SLP2__TYPE u_int32_t +#define MAC_PCU_SLP2__READ 0xffe00000U +#define MAC_PCU_SLP2__WRITE 0xffe00000U + +#endif /* __MAC_PCU_SLP2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_SLP2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_SLP2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SELF_GEN_DEFAULT */ +#ifndef __MAC_PCU_SELF_GEN_DEFAULT_MACRO__ +#define __MAC_PCU_SELF_GEN_DEFAULT_MACRO__ + +/* macros for field MMSS */ +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__SHIFT 0 +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WIDTH 3 +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MASK 0x00000007U +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field CEC */ +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__SHIFT 3 +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__WIDTH 2 +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__MASK 0x00000018U +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000018U) >> 3) +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000018U) +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000018U) | (((u_int32_t)(src) <<\ + 3) & 0x00000018U) +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000018U))) + +/* macros for field STAGGER_SOUNDING */ +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__SHIFT 5 +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WIDTH 1 +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MASK 0x00000020U +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define MAC_PCU_SELF_GEN_DEFAULT__TYPE u_int32_t +#define MAC_PCU_SELF_GEN_DEFAULT__READ 0x0000003fU +#define MAC_PCU_SELF_GEN_DEFAULT__WRITE 0x0000003fU + +#endif /* __MAC_PCU_SELF_GEN_DEFAULT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_SELF_GEN_DEFAULT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_SELF_GEN_DEFAULT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_ADDR1_MASK_L32 */ +#ifndef __MAC_PCU_ADDR1_MASK_L32_MACRO__ +#define __MAC_PCU_ADDR1_MASK_L32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_ADDR1_MASK_L32__VALUE__SHIFT 0 +#define MAC_PCU_ADDR1_MASK_L32__VALUE__WIDTH 32 +#define MAC_PCU_ADDR1_MASK_L32__VALUE__MASK 0xffffffffU +#define MAC_PCU_ADDR1_MASK_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_ADDR1_MASK_L32__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_ADDR1_MASK_L32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_ADDR1_MASK_L32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_ADDR1_MASK_L32__TYPE u_int32_t +#define MAC_PCU_ADDR1_MASK_L32__READ 0xffffffffU +#define MAC_PCU_ADDR1_MASK_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_ADDR1_MASK_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_ADDR1_MASK_L32 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_ADDR1_MASK_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_ADDR1_MASK_U16 */ +#ifndef __MAC_PCU_ADDR1_MASK_U16_MACRO__ +#define __MAC_PCU_ADDR1_MASK_U16_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_ADDR1_MASK_U16__VALUE__SHIFT 0 +#define MAC_PCU_ADDR1_MASK_U16__VALUE__WIDTH 16 +#define MAC_PCU_ADDR1_MASK_U16__VALUE__MASK 0x0000ffffU +#define MAC_PCU_ADDR1_MASK_U16__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_ADDR1_MASK_U16__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_ADDR1_MASK_U16__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_ADDR1_MASK_U16__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_ADDR1_MASK_U16__TYPE u_int32_t +#define MAC_PCU_ADDR1_MASK_U16__READ 0x0000ffffU +#define MAC_PCU_ADDR1_MASK_U16__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_ADDR1_MASK_U16_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_ADDR1_MASK_U16 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_ADDR1_MASK_U16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TPC */ +#ifndef __MAC_PCU_TPC_MACRO__ +#define __MAC_PCU_TPC_MACRO__ + +/* macros for field ACK_PWR */ +#define MAC_PCU_TPC__ACK_PWR__SHIFT 0 +#define MAC_PCU_TPC__ACK_PWR__WIDTH 6 +#define MAC_PCU_TPC__ACK_PWR__MASK 0x0000003fU +#define MAC_PCU_TPC__ACK_PWR__READ(src) (u_int32_t)(src) & 0x0000003fU +#define MAC_PCU_TPC__ACK_PWR__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define MAC_PCU_TPC__ACK_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define MAC_PCU_TPC__ACK_PWR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field CTS_PWR */ +#define MAC_PCU_TPC__CTS_PWR__SHIFT 8 +#define MAC_PCU_TPC__CTS_PWR__WIDTH 6 +#define MAC_PCU_TPC__CTS_PWR__MASK 0x00003f00U +#define MAC_PCU_TPC__CTS_PWR__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8) +#define MAC_PCU_TPC__CTS_PWR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define MAC_PCU_TPC__CTS_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define MAC_PCU_TPC__CTS_PWR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field CHIRP_PWR */ +#define MAC_PCU_TPC__CHIRP_PWR__SHIFT 16 +#define MAC_PCU_TPC__CHIRP_PWR__WIDTH 6 +#define MAC_PCU_TPC__CHIRP_PWR__MASK 0x003f0000U +#define MAC_PCU_TPC__CHIRP_PWR__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define MAC_PCU_TPC__CHIRP_PWR__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define MAC_PCU_TPC__CHIRP_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define MAC_PCU_TPC__CHIRP_PWR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field RPT_PWR */ +#define MAC_PCU_TPC__RPT_PWR__SHIFT 24 +#define MAC_PCU_TPC__RPT_PWR__WIDTH 6 +#define MAC_PCU_TPC__RPT_PWR__MASK 0x3f000000U +#define MAC_PCU_TPC__RPT_PWR__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define MAC_PCU_TPC__RPT_PWR__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define MAC_PCU_TPC__RPT_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define MAC_PCU_TPC__RPT_PWR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define MAC_PCU_TPC__TYPE u_int32_t +#define MAC_PCU_TPC__READ 0x3f3f3f3fU +#define MAC_PCU_TPC__WRITE 0x3f3f3f3fU + +#endif /* __MAC_PCU_TPC_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TPC */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TPC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_FRAME_CNT */ +#ifndef __MAC_PCU_TX_FRAME_CNT_MACRO__ +#define __MAC_PCU_TX_FRAME_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TX_FRAME_CNT__VALUE__SHIFT 0 +#define MAC_PCU_TX_FRAME_CNT__VALUE__WIDTH 32 +#define MAC_PCU_TX_FRAME_CNT__VALUE__MASK 0xffffffffU +#define MAC_PCU_TX_FRAME_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TX_FRAME_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_TX_FRAME_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TX_FRAME_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TX_FRAME_CNT__TYPE u_int32_t +#define MAC_PCU_TX_FRAME_CNT__READ 0xffffffffU +#define MAC_PCU_TX_FRAME_CNT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TX_FRAME_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TX_FRAME_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TX_FRAME_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_FRAME_CNT */ +#ifndef __MAC_PCU_RX_FRAME_CNT_MACRO__ +#define __MAC_PCU_RX_FRAME_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_RX_FRAME_CNT__VALUE__SHIFT 0 +#define MAC_PCU_RX_FRAME_CNT__VALUE__WIDTH 32 +#define MAC_PCU_RX_FRAME_CNT__VALUE__MASK 0xffffffffU +#define MAC_PCU_RX_FRAME_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_RX_FRAME_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_RX_FRAME_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_RX_FRAME_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_RX_FRAME_CNT__TYPE u_int32_t +#define MAC_PCU_RX_FRAME_CNT__READ 0xffffffffU +#define MAC_PCU_RX_FRAME_CNT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_RX_FRAME_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_RX_FRAME_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_RX_FRAME_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_CLEAR_CNT */ +#ifndef __MAC_PCU_RX_CLEAR_CNT_MACRO__ +#define __MAC_PCU_RX_CLEAR_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_RX_CLEAR_CNT__VALUE__SHIFT 0 +#define MAC_PCU_RX_CLEAR_CNT__VALUE__WIDTH 32 +#define MAC_PCU_RX_CLEAR_CNT__VALUE__MASK 0xffffffffU +#define MAC_PCU_RX_CLEAR_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_RX_CLEAR_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_RX_CLEAR_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_RX_CLEAR_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_RX_CLEAR_CNT__TYPE u_int32_t +#define MAC_PCU_RX_CLEAR_CNT__READ 0xffffffffU +#define MAC_PCU_RX_CLEAR_CNT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_RX_CLEAR_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_RX_CLEAR_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_RX_CLEAR_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_CYCLE_CNT */ +#ifndef __MAC_PCU_CYCLE_CNT_MACRO__ +#define __MAC_PCU_CYCLE_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_CYCLE_CNT__VALUE__SHIFT 0 +#define MAC_PCU_CYCLE_CNT__VALUE__WIDTH 32 +#define MAC_PCU_CYCLE_CNT__VALUE__MASK 0xffffffffU +#define MAC_PCU_CYCLE_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_CYCLE_CNT__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_CYCLE_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_CYCLE_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_CYCLE_CNT__TYPE u_int32_t +#define MAC_PCU_CYCLE_CNT__READ 0xffffffffU +#define MAC_PCU_CYCLE_CNT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_CYCLE_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_CYCLE_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_CYCLE_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_QUIET_TIME_1 */ +#ifndef __MAC_PCU_QUIET_TIME_1_MACRO__ +#define __MAC_PCU_QUIET_TIME_1_MACRO__ + +/* macros for field ACK_CTS_ENABLE */ +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__SHIFT 17 +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WIDTH 1 +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MASK 0x00020000U +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) +#define MAC_PCU_QUIET_TIME_1__TYPE u_int32_t +#define MAC_PCU_QUIET_TIME_1__READ 0x00020000U +#define MAC_PCU_QUIET_TIME_1__WRITE 0x00020000U + +#endif /* __MAC_PCU_QUIET_TIME_1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_QUIET_TIME_1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_QUIET_TIME_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_QUIET_TIME_2 */ +#ifndef __MAC_PCU_QUIET_TIME_2_MACRO__ +#define __MAC_PCU_QUIET_TIME_2_MACRO__ + +/* macros for field DURATION */ +#define MAC_PCU_QUIET_TIME_2__DURATION__SHIFT 16 +#define MAC_PCU_QUIET_TIME_2__DURATION__WIDTH 16 +#define MAC_PCU_QUIET_TIME_2__DURATION__MASK 0xffff0000U +#define MAC_PCU_QUIET_TIME_2__DURATION__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_QUIET_TIME_2__DURATION__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_QUIET_TIME_2__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_QUIET_TIME_2__DURATION__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_QUIET_TIME_2__TYPE u_int32_t +#define MAC_PCU_QUIET_TIME_2__READ 0xffff0000U +#define MAC_PCU_QUIET_TIME_2__WRITE 0xffff0000U + +#endif /* __MAC_PCU_QUIET_TIME_2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_QUIET_TIME_2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_QUIET_TIME_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_QOS_NO_ACK */ +#ifndef __MAC_PCU_QOS_NO_ACK_MACRO__ +#define __MAC_PCU_QOS_NO_ACK_MACRO__ + +/* macros for field TWO_BIT_VALUES */ +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__SHIFT 0 +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WIDTH 4 +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MASK 0x0000000fU +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field BIT_OFFSET */ +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__SHIFT 4 +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WIDTH 3 +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MASK 0x00000070U +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000070U) >> 4) +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field BYTE_OFFSET */ +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__SHIFT 7 +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WIDTH 2 +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MASK 0x00000180U +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000180U) >> 7) +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000180U) +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000180U) | (((u_int32_t)(src) <<\ + 7) & 0x00000180U) +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000180U))) +#define MAC_PCU_QOS_NO_ACK__TYPE u_int32_t +#define MAC_PCU_QOS_NO_ACK__READ 0x000001ffU +#define MAC_PCU_QOS_NO_ACK__WRITE 0x000001ffU + +#endif /* __MAC_PCU_QOS_NO_ACK_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_QOS_NO_ACK */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_QOS_NO_ACK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_MASK */ +#ifndef __MAC_PCU_PHY_ERROR_MASK_MACRO__ +#define __MAC_PCU_PHY_ERROR_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERROR_MASK__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERROR_MASK__VALUE__WIDTH 32 +#define MAC_PCU_PHY_ERROR_MASK__VALUE__MASK 0xffffffffU +#define MAC_PCU_PHY_ERROR_MASK__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_PHY_ERROR_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_PHY_ERROR_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_PHY_ERROR_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_PHY_ERROR_MASK__TYPE u_int32_t +#define MAC_PCU_PHY_ERROR_MASK__READ 0xffffffffU +#define MAC_PCU_PHY_ERROR_MASK__WRITE 0xffffffffU + +#endif /* __MAC_PCU_PHY_ERROR_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_PHY_ERROR_MASK */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_PHY_ERROR_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRLAT */ +#ifndef __MAC_PCU_XRLAT_MACRO__ +#define __MAC_PCU_XRLAT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_XRLAT__VALUE__SHIFT 0 +#define MAC_PCU_XRLAT__VALUE__WIDTH 12 +#define MAC_PCU_XRLAT__VALUE__MASK 0x00000fffU +#define MAC_PCU_XRLAT__VALUE__READ(src) (u_int32_t)(src) & 0x00000fffU +#define MAC_PCU_XRLAT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) +#define MAC_PCU_XRLAT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define MAC_PCU_XRLAT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) +#define MAC_PCU_XRLAT__TYPE u_int32_t +#define MAC_PCU_XRLAT__READ 0x00000fffU +#define MAC_PCU_XRLAT__WRITE 0x00000fffU + +#endif /* __MAC_PCU_XRLAT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_XRLAT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_XRLAT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RXBUF */ +#ifndef __MAC_PCU_RXBUF_MACRO__ +#define __MAC_PCU_RXBUF_MACRO__ + +/* macros for field HIGH_PRIORITY_THRSHD */ +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__SHIFT 0 +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WIDTH 11 +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MASK 0x000007ffU +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__READ(src) \ + (u_int32_t)(src)\ + & 0x000007ffU +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000007ffU) +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000007ffU))) + +/* macros for field REG_RD_ENABLE */ +#define MAC_PCU_RXBUF__REG_RD_ENABLE__SHIFT 11 +#define MAC_PCU_RXBUF__REG_RD_ENABLE__WIDTH 1 +#define MAC_PCU_RXBUF__REG_RD_ENABLE__MASK 0x00000800U +#define MAC_PCU_RXBUF__REG_RD_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_RXBUF__REG_RD_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_RXBUF__REG_RD_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_RXBUF__REG_RD_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_RXBUF__REG_RD_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_RXBUF__REG_RD_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) +#define MAC_PCU_RXBUF__TYPE u_int32_t +#define MAC_PCU_RXBUF__READ 0x00000fffU +#define MAC_PCU_RXBUF__WRITE 0x00000fffU + +#endif /* __MAC_PCU_RXBUF_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_RXBUF */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_RXBUF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MIC_QOS_CONTROL */ +#ifndef __MAC_PCU_MIC_QOS_CONTROL_MACRO__ +#define __MAC_PCU_MIC_QOS_CONTROL_MACRO__ + +/* macros for field VALUE_0 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__SHIFT 0 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MASK 0x00000003U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field VALUE_1 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__SHIFT 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MASK 0x0000000cU +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field VALUE_2 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__SHIFT 4 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MASK 0x00000030U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field VALUE_3 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__SHIFT 6 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MASK 0x000000c0U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field VALUE_4 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__SHIFT 8 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MASK 0x00000300U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field VALUE_5 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__SHIFT 10 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MASK 0x00000c00U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) + +/* macros for field VALUE_6 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__SHIFT 12 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MASK 0x00003000U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003000U) >> 12) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00003000U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((u_int32_t)(src) <<\ + 12) & 0x00003000U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00003000U))) + +/* macros for field VALUE_7 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__SHIFT 14 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MASK 0x0000c000U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field ENABLE */ +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__SHIFT 16 +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WIDTH 1 +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MASK 0x00010000U +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) +#define MAC_PCU_MIC_QOS_CONTROL__TYPE u_int32_t +#define MAC_PCU_MIC_QOS_CONTROL__READ 0x0001ffffU +#define MAC_PCU_MIC_QOS_CONTROL__WRITE 0x0001ffffU + +#endif /* __MAC_PCU_MIC_QOS_CONTROL_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_MIC_QOS_CONTROL */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_MIC_QOS_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MIC_QOS_SELECT */ +#ifndef __MAC_PCU_MIC_QOS_SELECT_MACRO__ +#define __MAC_PCU_MIC_QOS_SELECT_MACRO__ + +/* macros for field VALUE_0 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__SHIFT 0 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MASK 0x0000000fU +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field VALUE_1 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__SHIFT 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MASK 0x000000f0U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field VALUE_2 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__SHIFT 8 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MASK 0x00000f00U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field VALUE_3 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__SHIFT 12 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MASK 0x0000f000U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field VALUE_4 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__SHIFT 16 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MASK 0x000f0000U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field VALUE_5 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__SHIFT 20 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MASK 0x00f00000U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) + +/* macros for field VALUE_6 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__SHIFT 24 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MASK 0x0f000000U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) + +/* macros for field VALUE_7 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__SHIFT 28 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MASK 0xf0000000U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__READ(src) \ + (((u_int32_t)(src)\ + & 0xf0000000U) >> 28) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0xf0000000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((u_int32_t)(src) <<\ + 28) & 0xf0000000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0xf0000000U))) +#define MAC_PCU_MIC_QOS_SELECT__TYPE u_int32_t +#define MAC_PCU_MIC_QOS_SELECT__READ 0xffffffffU +#define MAC_PCU_MIC_QOS_SELECT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_MIC_QOS_SELECT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_MIC_QOS_SELECT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_MIC_QOS_SELECT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE */ +#ifndef __MAC_PCU_MISC_MODE_MACRO__ +#define __MAC_PCU_MISC_MODE_MACRO__ + +/* macros for field BSSID_MATCH_FORCE */ +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__SHIFT 0 +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WIDTH 1 +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MASK 0x00000001U +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field DEBUG_MODE_AD */ +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__SHIFT 1 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WIDTH 1 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MASK 0x00000002U +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field MIC_NEW_LOCATION_ENABLE */ +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__SHIFT 2 +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MASK 0x00000004U +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field TX_ADD_TSF */ +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__SHIFT 3 +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__WIDTH 1 +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__MASK 0x00000008U +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field CCK_SIFS_MODE */ +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__SHIFT 4 +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WIDTH 1 +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MASK 0x00000010U +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field RXSM2SVD_PRE_RST */ +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__SHIFT 5 +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WIDTH 1 +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MASK 0x00000020U +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field RCV_DELAY_SOUNDING_IM_TXBF */ +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__SHIFT 6 +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WIDTH 1 +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MASK 0x00000040U +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field DEBUG_MODE_BA_BITMAP */ +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__SHIFT 9 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WIDTH 1 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MASK 0x00000200U +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field DEBUG_MODE_SIFS */ +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__SHIFT 10 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WIDTH 1 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MASK 0x00000400U +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field KC_RX_ANT_UPDATE */ +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__SHIFT 11 +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WIDTH 1 +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MASK 0x00000800U +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field TXOP_TBTT_LIMIT_ENABLE */ +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__SHIFT 12 +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MASK 0x00001000U +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field MISS_BEACON_IN_SLEEP */ +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__SHIFT 14 +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WIDTH 1 +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MASK 0x00004000U +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field FORCE_QUIET_COLLISION */ +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__SHIFT 18 +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WIDTH 1 +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MASK 0x00040000U +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field BT_ANT_PREVENTS_RX */ +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__SHIFT 20 +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WIDTH 1 +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MASK 0x00100000U +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field TBTT_PROTECT */ +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__SHIFT 21 +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__WIDTH 1 +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__MASK 0x00200000U +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field HCF_POLL_CANCELS_NAV */ +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__SHIFT 22 +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WIDTH 1 +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MASK 0x00400000U +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field RX_HCF_POLL_ENABLE */ +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__SHIFT 23 +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MASK 0x00800000U +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field CLEAR_VMF */ +#define MAC_PCU_MISC_MODE__CLEAR_VMF__SHIFT 24 +#define MAC_PCU_MISC_MODE__CLEAR_VMF__WIDTH 1 +#define MAC_PCU_MISC_MODE__CLEAR_VMF__MASK 0x01000000U +#define MAC_PCU_MISC_MODE__CLEAR_VMF__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_MISC_MODE__CLEAR_VMF__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_MISC_MODE__CLEAR_VMF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_MISC_MODE__CLEAR_VMF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_MISC_MODE__CLEAR_VMF__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_MISC_MODE__CLEAR_VMF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field CLEAR_FIRST_HCF */ +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__SHIFT 25 +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WIDTH 1 +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MASK 0x02000000U +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field CLEAR_BA_VALID */ +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__SHIFT 26 +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WIDTH 1 +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MASK 0x04000000U +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field SEL_EVM */ +#define MAC_PCU_MISC_MODE__SEL_EVM__SHIFT 27 +#define MAC_PCU_MISC_MODE__SEL_EVM__WIDTH 1 +#define MAC_PCU_MISC_MODE__SEL_EVM__MASK 0x08000000U +#define MAC_PCU_MISC_MODE__SEL_EVM__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_PCU_MISC_MODE__SEL_EVM__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_PCU_MISC_MODE__SEL_EVM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_PCU_MISC_MODE__SEL_EVM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_PCU_MISC_MODE__SEL_EVM__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_PCU_MISC_MODE__SEL_EVM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field ALWAYS_PERFORM_KEY_SEARCH */ +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__SHIFT 28 +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WIDTH 1 +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MASK 0x10000000U +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field USE_EOP_PTR_FOR_DMA_WR */ +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__SHIFT 29 +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WIDTH 1 +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MASK 0x20000000U +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field DEBUG_MODE */ +#define MAC_PCU_MISC_MODE__DEBUG_MODE__SHIFT 30 +#define MAC_PCU_MISC_MODE__DEBUG_MODE__WIDTH 2 +#define MAC_PCU_MISC_MODE__DEBUG_MODE__MASK 0xc0000000U +#define MAC_PCU_MISC_MODE__DEBUG_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define MAC_PCU_MISC_MODE__DEBUG_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define MAC_PCU_MISC_MODE__TYPE u_int32_t +#define MAC_PCU_MISC_MODE__READ 0xfff45e7fU +#define MAC_PCU_MISC_MODE__WRITE 0xfff45e7fU + +#endif /* __MAC_PCU_MISC_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_MISC_MODE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_MISC_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_OFDM_CNT */ +#ifndef __MAC_PCU_FILTER_OFDM_CNT_MACRO__ +#define __MAC_PCU_FILTER_OFDM_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__SHIFT 0 +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__WIDTH 24 +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__MASK 0x00ffffffU +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x00ffffffU +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define MAC_PCU_FILTER_OFDM_CNT__TYPE u_int32_t +#define MAC_PCU_FILTER_OFDM_CNT__READ 0x00ffffffU +#define MAC_PCU_FILTER_OFDM_CNT__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_FILTER_OFDM_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_FILTER_OFDM_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_FILTER_OFDM_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_CCK_CNT */ +#ifndef __MAC_PCU_FILTER_CCK_CNT_MACRO__ +#define __MAC_PCU_FILTER_CCK_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_FILTER_CCK_CNT__VALUE__SHIFT 0 +#define MAC_PCU_FILTER_CCK_CNT__VALUE__WIDTH 24 +#define MAC_PCU_FILTER_CCK_CNT__VALUE__MASK 0x00ffffffU +#define MAC_PCU_FILTER_CCK_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_PCU_FILTER_CCK_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define MAC_PCU_FILTER_CCK_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_FILTER_CCK_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define MAC_PCU_FILTER_CCK_CNT__TYPE u_int32_t +#define MAC_PCU_FILTER_CCK_CNT__READ 0x00ffffffU +#define MAC_PCU_FILTER_CCK_CNT__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_FILTER_CCK_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_FILTER_CCK_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_FILTER_CCK_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_1 */ +#ifndef __MAC_PCU_PHY_ERR_CNT_1_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_1_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__WIDTH 24 +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__MASK 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define MAC_PCU_PHY_ERR_CNT_1__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_1__READ 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_1__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_PHY_ERR_CNT_1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_PHY_ERR_CNT_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_1_MASK */ +#ifndef __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WIDTH 32 +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MASK 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_PHY_ERR_CNT_1_MASK__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_1_MASK__READ 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_1_MASK__WRITE 0xffffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_PHY_ERR_CNT_1_MASK */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_PHY_ERR_CNT_1_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_2 */ +#ifndef __MAC_PCU_PHY_ERR_CNT_2_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_2_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__WIDTH 24 +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__MASK 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define MAC_PCU_PHY_ERR_CNT_2__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_2__READ 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_2__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_PHY_ERR_CNT_2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_PHY_ERR_CNT_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_2_MASK */ +#ifndef __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WIDTH 32 +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MASK 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_PHY_ERR_CNT_2_MASK__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_2_MASK__READ 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_2_MASK__WRITE 0xffffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_PHY_ERR_CNT_2_MASK */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_PHY_ERR_CNT_2_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_THRESHOLD */ +#ifndef __MAC_PCU_TSF_THRESHOLD_MACRO__ +#define __MAC_PCU_TSF_THRESHOLD_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TSF_THRESHOLD__VALUE__SHIFT 0 +#define MAC_PCU_TSF_THRESHOLD__VALUE__WIDTH 16 +#define MAC_PCU_TSF_THRESHOLD__VALUE__MASK 0x0000ffffU +#define MAC_PCU_TSF_THRESHOLD__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_TSF_THRESHOLD__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_TSF_THRESHOLD__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_TSF_THRESHOLD__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_TSF_THRESHOLD__TYPE u_int32_t +#define MAC_PCU_TSF_THRESHOLD__READ 0x0000ffffU +#define MAC_PCU_TSF_THRESHOLD__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_TSF_THRESHOLD_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TSF_THRESHOLD */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TSF_THRESHOLD__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_EIFS_MASK */ +#ifndef __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__ +#define __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WIDTH 32 +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MASK 0xffffffffU +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_PHY_ERROR_EIFS_MASK__TYPE u_int32_t +#define MAC_PCU_PHY_ERROR_EIFS_MASK__READ 0xffffffffU +#define MAC_PCU_PHY_ERROR_EIFS_MASK__WRITE 0xffffffffU + +#endif /* __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_PHY_ERROR_EIFS_MASK */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_PHY_ERROR_EIFS_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_3 */ +#ifndef __MAC_PCU_PHY_ERR_CNT_3_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_3_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__WIDTH 24 +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__MASK 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define MAC_PCU_PHY_ERR_CNT_3__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_3__READ 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_3__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_3_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_PHY_ERR_CNT_3 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_PHY_ERR_CNT_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_3_MASK */ +#ifndef __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WIDTH 32 +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MASK 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_PHY_ERR_CNT_3_MASK__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_3_MASK__READ 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_3_MASK__WRITE 0xffffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_PHY_ERR_CNT_3_MASK */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_PHY_ERR_CNT_3_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE */ +#ifndef __MAC_PCU_BLUETOOTH_MODE_MACRO__ +#define __MAC_PCU_BLUETOOTH_MODE_MACRO__ + +/* macros for field TIME_EXTEND */ +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__SHIFT 0 +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MASK 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field TX_STATE_EXTEND */ +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__SHIFT 8 +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MASK 0x00000100U +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field TX_FRAME_EXTEND */ +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__SHIFT 9 +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MASK 0x00000200U +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field MODE */ +#define MAC_PCU_BLUETOOTH_MODE__MODE__SHIFT 10 +#define MAC_PCU_BLUETOOTH_MODE__MODE__WIDTH 2 +#define MAC_PCU_BLUETOOTH_MODE__MODE__MASK 0x00000c00U +#define MAC_PCU_BLUETOOTH_MODE__MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define MAC_PCU_BLUETOOTH_MODE__MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define MAC_PCU_BLUETOOTH_MODE__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define MAC_PCU_BLUETOOTH_MODE__MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) + +/* macros for field QUIET */ +#define MAC_PCU_BLUETOOTH_MODE__QUIET__SHIFT 12 +#define MAC_PCU_BLUETOOTH_MODE__QUIET__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE__QUIET__MASK 0x00001000U +#define MAC_PCU_BLUETOOTH_MODE__QUIET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_BLUETOOTH_MODE__QUIET__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_BLUETOOTH_MODE__QUIET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_BLUETOOTH_MODE__QUIET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_BLUETOOTH_MODE__QUIET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_BLUETOOTH_MODE__QUIET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field QCU_THRESH */ +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__SHIFT 13 +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WIDTH 4 +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MASK 0x0001e000U +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001e000U) >> 13) +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0001e000U) +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0001e000U) +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0001e000U))) + +/* macros for field RX_CLEAR_POLARITY */ +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__SHIFT 17 +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MASK 0x00020000U +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field PRIORITY_TIME */ +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__SHIFT 18 +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WIDTH 6 +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MASK 0x00fc0000U +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field FIRST_SLOT_TIME */ +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__SHIFT 24 +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MASK 0xff000000U +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_BLUETOOTH_MODE__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_MODE__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_MODE__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BLUETOOTH_MODE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BLUETOOTH_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_WL_WEIGHTS0 */ +#ifndef __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__ +#define __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BLUETOOTH_WL_WEIGHTS0 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BLUETOOTH_WL_WEIGHTS0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_HCF_TIMEOUT */ +#ifndef __MAC_PCU_HCF_TIMEOUT_MACRO__ +#define __MAC_PCU_HCF_TIMEOUT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_HCF_TIMEOUT__VALUE__SHIFT 0 +#define MAC_PCU_HCF_TIMEOUT__VALUE__WIDTH 16 +#define MAC_PCU_HCF_TIMEOUT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_HCF_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_HCF_TIMEOUT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_PCU_HCF_TIMEOUT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_HCF_TIMEOUT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_HCF_TIMEOUT__TYPE u_int32_t +#define MAC_PCU_HCF_TIMEOUT__READ 0x0000ffffU +#define MAC_PCU_HCF_TIMEOUT__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_HCF_TIMEOUT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_HCF_TIMEOUT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_HCF_TIMEOUT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE2 */ +#ifndef __MAC_PCU_BLUETOOTH_MODE2_MACRO__ +#define __MAC_PCU_BLUETOOTH_MODE2_MACRO__ + +/* macros for field BCN_MISS_THRESH */ +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__SHIFT 0 +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MASK 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field BCN_MISS_CNT */ +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__SHIFT 8 +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__MASK 0x0000ff00U +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field HOLD_RX_CLEAR */ +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__SHIFT 16 +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MASK 0x00010000U +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field SLEEP_ALLOW_BT_ACCESS */ +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__SHIFT 17 +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MASK 0x00020000U +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field PROTECT_BT_AFTER_WAKEUP */ +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__SHIFT 19 +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MASK 0x00080000U +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field DISABLE_BT_ANT */ +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__SHIFT 20 +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MASK 0x00100000U +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field QUIET_2_WIRE */ +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__SHIFT 21 +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MASK 0x00200000U +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field WL_ACTIVE_MODE */ +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__SHIFT 22 +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WIDTH 2 +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MASK 0x00c00000U +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00c00000U) >> 22) +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00c00000U) +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x00c00000U) +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00c00000U))) + +/* macros for field WL_TXRX_SEPARATE */ +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__SHIFT 24 +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MASK 0x01000000U +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field RS_DISCARD_EXTEND */ +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__SHIFT 25 +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MASK 0x02000000U +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field TSF_BT_ACTIVE_CTRL */ +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__SHIFT 26 +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WIDTH 2 +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MASK 0x0c000000U +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0c000000U) >> 26) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x0c000000U) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) + +/* macros for field TSF_BT_PRIORITY_CTRL */ +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__SHIFT 28 +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WIDTH 2 +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MASK 0x30000000U +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x30000000U) >> 28) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x30000000U) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) + +/* macros for field INTERRUPT_ENABLE */ +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__SHIFT 30 +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MASK 0x40000000U +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PHY_ERR_BT_COLL_ENABLE */ +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__SHIFT 31 +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MASK 0x80000000U +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define MAC_PCU_BLUETOOTH_MODE2__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_MODE2__READ 0xfffbffffU +#define MAC_PCU_BLUETOOTH_MODE2__WRITE 0xfffbffffU + +#endif /* __MAC_PCU_BLUETOOTH_MODE2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BLUETOOTH_MODE2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BLUETOOTH_MODE2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS2 */ +#ifndef __MAC_PCU_GENERIC_TIMERS2_MACRO__ +#define __MAC_PCU_GENERIC_TIMERS2_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_GENERIC_TIMERS2__DATA__SHIFT 0 +#define MAC_PCU_GENERIC_TIMERS2__DATA__WIDTH 32 +#define MAC_PCU_GENERIC_TIMERS2__DATA__MASK 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS2__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_GENERIC_TIMERS2__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_GENERIC_TIMERS2__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_GENERIC_TIMERS2__TYPE u_int32_t +#define MAC_PCU_GENERIC_TIMERS2__READ 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_GENERIC_TIMERS2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_GENERIC_TIMERS2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_GENERIC_TIMERS2__NUM 16 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS2_MODE */ +#ifndef __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__ +#define __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__ + +/* macros for field ENABLE */ +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__SHIFT 0 +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WIDTH 8 +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MASK 0x000000ffU +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field OVERFLOW_INDEX */ +#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__SHIFT 8 +#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__WIDTH 3 +#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__MASK 0x00000700U +#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define MAC_PCU_GENERIC_TIMERS2_MODE__TYPE u_int32_t +#define MAC_PCU_GENERIC_TIMERS2_MODE__READ 0x000007ffU +#define MAC_PCU_GENERIC_TIMERS2_MODE__WRITE 0x000007ffU + +#endif /* __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_GENERIC_TIMERS2_MODE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_GENERIC_TIMERS2_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_WL_WEIGHTS1 */ +#ifndef __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__ +#define __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BLUETOOTH_WL_WEIGHTS1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BLUETOOTH_WL_WEIGHTS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE */ +#ifndef __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__ +#define __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__READ 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY */ +#ifndef __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__ +#define __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__READ 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXSIFS */ +#ifndef __MAC_PCU_TXSIFS_MACRO__ +#define __MAC_PCU_TXSIFS_MACRO__ + +/* macros for field SIFS_TIME */ +#define MAC_PCU_TXSIFS__SIFS_TIME__SHIFT 0 +#define MAC_PCU_TXSIFS__SIFS_TIME__WIDTH 8 +#define MAC_PCU_TXSIFS__SIFS_TIME__MASK 0x000000ffU +#define MAC_PCU_TXSIFS__SIFS_TIME__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXSIFS__SIFS_TIME__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_TXSIFS__SIFS_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXSIFS__SIFS_TIME__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field TX_LATENCY */ +#define MAC_PCU_TXSIFS__TX_LATENCY__SHIFT 8 +#define MAC_PCU_TXSIFS__TX_LATENCY__WIDTH 4 +#define MAC_PCU_TXSIFS__TX_LATENCY__MASK 0x00000f00U +#define MAC_PCU_TXSIFS__TX_LATENCY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define MAC_PCU_TXSIFS__TX_LATENCY__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define MAC_PCU_TXSIFS__TX_LATENCY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define MAC_PCU_TXSIFS__TX_LATENCY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field ACK_SHIFT */ +#define MAC_PCU_TXSIFS__ACK_SHIFT__SHIFT 12 +#define MAC_PCU_TXSIFS__ACK_SHIFT__WIDTH 3 +#define MAC_PCU_TXSIFS__ACK_SHIFT__MASK 0x00007000U +#define MAC_PCU_TXSIFS__ACK_SHIFT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007000U) >> 12) +#define MAC_PCU_TXSIFS__ACK_SHIFT__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00007000U) +#define MAC_PCU_TXSIFS__ACK_SHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define MAC_PCU_TXSIFS__ACK_SHIFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) +#define MAC_PCU_TXSIFS__TYPE u_int32_t +#define MAC_PCU_TXSIFS__READ 0x00007fffU +#define MAC_PCU_TXSIFS__WRITE 0x00007fffU + +#endif /* __MAC_PCU_TXSIFS_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TXSIFS */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TXSIFS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE3 */ +#ifndef __MAC_PCU_BLUETOOTH_MODE3_MACRO__ +#define __MAC_PCU_BLUETOOTH_MODE3_MACRO__ + +/* macros for field WL_ACTIVE_TIME */ +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__SHIFT 0 +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MASK 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field WL_QC_TIME */ +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__SHIFT 8 +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MASK 0x0000ff00U +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field ALLOW_CONCURRENT_ACCESS */ +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__SHIFT 16 +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WIDTH 4 +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MASK 0x000f0000U +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field AGC_SATURATION_CNT_ENABLE */ +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__SHIFT 20 +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MASK 0x00100000U +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) +#define MAC_PCU_BLUETOOTH_MODE3__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_MODE3__READ 0x001fffffU +#define MAC_PCU_BLUETOOTH_MODE3__WRITE 0x001fffffU + +#endif /* __MAC_PCU_BLUETOOTH_MODE3_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BLUETOOTH_MODE3 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BLUETOOTH_MODE3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_X */ +#ifndef __MAC_PCU_TXOP_X_MACRO__ +#define __MAC_PCU_TXOP_X_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TXOP_X__VALUE__SHIFT 0 +#define MAC_PCU_TXOP_X__VALUE__WIDTH 8 +#define MAC_PCU_TXOP_X__VALUE__MASK 0x000000ffU +#define MAC_PCU_TXOP_X__VALUE__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXOP_X__VALUE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_TXOP_X__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXOP_X__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) +#define MAC_PCU_TXOP_X__TYPE u_int32_t +#define MAC_PCU_TXOP_X__READ 0x000000ffU +#define MAC_PCU_TXOP_X__WRITE 0x000000ffU + +#endif /* __MAC_PCU_TXOP_X_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TXOP_X */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TXOP_X__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_0_3 */ +#ifndef __MAC_PCU_TXOP_0_3_MACRO__ +#define __MAC_PCU_TXOP_0_3_MACRO__ + +/* macros for field VALUE_0 */ +#define MAC_PCU_TXOP_0_3__VALUE_0__SHIFT 0 +#define MAC_PCU_TXOP_0_3__VALUE_0__WIDTH 8 +#define MAC_PCU_TXOP_0_3__VALUE_0__MASK 0x000000ffU +#define MAC_PCU_TXOP_0_3__VALUE_0__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXOP_0_3__VALUE_0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_TXOP_0_3__VALUE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXOP_0_3__VALUE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field VALUE_1 */ +#define MAC_PCU_TXOP_0_3__VALUE_1__SHIFT 8 +#define MAC_PCU_TXOP_0_3__VALUE_1__WIDTH 8 +#define MAC_PCU_TXOP_0_3__VALUE_1__MASK 0x0000ff00U +#define MAC_PCU_TXOP_0_3__VALUE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_TXOP_0_3__VALUE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_0_3__VALUE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_0_3__VALUE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field VALUE_2 */ +#define MAC_PCU_TXOP_0_3__VALUE_2__SHIFT 16 +#define MAC_PCU_TXOP_0_3__VALUE_2__WIDTH 8 +#define MAC_PCU_TXOP_0_3__VALUE_2__MASK 0x00ff0000U +#define MAC_PCU_TXOP_0_3__VALUE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_TXOP_0_3__VALUE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_0_3__VALUE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_0_3__VALUE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field VALUE_3 */ +#define MAC_PCU_TXOP_0_3__VALUE_3__SHIFT 24 +#define MAC_PCU_TXOP_0_3__VALUE_3__WIDTH 8 +#define MAC_PCU_TXOP_0_3__VALUE_3__MASK 0xff000000U +#define MAC_PCU_TXOP_0_3__VALUE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_TXOP_0_3__VALUE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_TXOP_0_3__VALUE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_TXOP_0_3__VALUE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_TXOP_0_3__TYPE u_int32_t +#define MAC_PCU_TXOP_0_3__READ 0xffffffffU +#define MAC_PCU_TXOP_0_3__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TXOP_0_3_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TXOP_0_3 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TXOP_0_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_4_7 */ +#ifndef __MAC_PCU_TXOP_4_7_MACRO__ +#define __MAC_PCU_TXOP_4_7_MACRO__ + +/* macros for field VALUE_4 */ +#define MAC_PCU_TXOP_4_7__VALUE_4__SHIFT 0 +#define MAC_PCU_TXOP_4_7__VALUE_4__WIDTH 8 +#define MAC_PCU_TXOP_4_7__VALUE_4__MASK 0x000000ffU +#define MAC_PCU_TXOP_4_7__VALUE_4__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXOP_4_7__VALUE_4__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_TXOP_4_7__VALUE_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXOP_4_7__VALUE_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field VALUE_5 */ +#define MAC_PCU_TXOP_4_7__VALUE_5__SHIFT 8 +#define MAC_PCU_TXOP_4_7__VALUE_5__WIDTH 8 +#define MAC_PCU_TXOP_4_7__VALUE_5__MASK 0x0000ff00U +#define MAC_PCU_TXOP_4_7__VALUE_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_TXOP_4_7__VALUE_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_4_7__VALUE_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_4_7__VALUE_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field VALUE_6 */ +#define MAC_PCU_TXOP_4_7__VALUE_6__SHIFT 16 +#define MAC_PCU_TXOP_4_7__VALUE_6__WIDTH 8 +#define MAC_PCU_TXOP_4_7__VALUE_6__MASK 0x00ff0000U +#define MAC_PCU_TXOP_4_7__VALUE_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_TXOP_4_7__VALUE_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_4_7__VALUE_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_4_7__VALUE_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field VALUE_7 */ +#define MAC_PCU_TXOP_4_7__VALUE_7__SHIFT 24 +#define MAC_PCU_TXOP_4_7__VALUE_7__WIDTH 8 +#define MAC_PCU_TXOP_4_7__VALUE_7__MASK 0xff000000U +#define MAC_PCU_TXOP_4_7__VALUE_7__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_TXOP_4_7__VALUE_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_TXOP_4_7__VALUE_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_TXOP_4_7__VALUE_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_TXOP_4_7__TYPE u_int32_t +#define MAC_PCU_TXOP_4_7__READ 0xffffffffU +#define MAC_PCU_TXOP_4_7__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TXOP_4_7_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TXOP_4_7 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TXOP_4_7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_8_11 */ +#ifndef __MAC_PCU_TXOP_8_11_MACRO__ +#define __MAC_PCU_TXOP_8_11_MACRO__ + +/* macros for field VALUE_8 */ +#define MAC_PCU_TXOP_8_11__VALUE_8__SHIFT 0 +#define MAC_PCU_TXOP_8_11__VALUE_8__WIDTH 8 +#define MAC_PCU_TXOP_8_11__VALUE_8__MASK 0x000000ffU +#define MAC_PCU_TXOP_8_11__VALUE_8__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXOP_8_11__VALUE_8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_TXOP_8_11__VALUE_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXOP_8_11__VALUE_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field VALUE_9 */ +#define MAC_PCU_TXOP_8_11__VALUE_9__SHIFT 8 +#define MAC_PCU_TXOP_8_11__VALUE_9__WIDTH 8 +#define MAC_PCU_TXOP_8_11__VALUE_9__MASK 0x0000ff00U +#define MAC_PCU_TXOP_8_11__VALUE_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_TXOP_8_11__VALUE_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_8_11__VALUE_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_8_11__VALUE_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field VALUE_10 */ +#define MAC_PCU_TXOP_8_11__VALUE_10__SHIFT 16 +#define MAC_PCU_TXOP_8_11__VALUE_10__WIDTH 8 +#define MAC_PCU_TXOP_8_11__VALUE_10__MASK 0x00ff0000U +#define MAC_PCU_TXOP_8_11__VALUE_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_TXOP_8_11__VALUE_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_8_11__VALUE_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_8_11__VALUE_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field VALUE_11 */ +#define MAC_PCU_TXOP_8_11__VALUE_11__SHIFT 24 +#define MAC_PCU_TXOP_8_11__VALUE_11__WIDTH 8 +#define MAC_PCU_TXOP_8_11__VALUE_11__MASK 0xff000000U +#define MAC_PCU_TXOP_8_11__VALUE_11__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_TXOP_8_11__VALUE_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_TXOP_8_11__VALUE_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_TXOP_8_11__VALUE_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_TXOP_8_11__TYPE u_int32_t +#define MAC_PCU_TXOP_8_11__READ 0xffffffffU +#define MAC_PCU_TXOP_8_11__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TXOP_8_11_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TXOP_8_11 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TXOP_8_11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_12_15 */ +#ifndef __MAC_PCU_TXOP_12_15_MACRO__ +#define __MAC_PCU_TXOP_12_15_MACRO__ + +/* macros for field VALUE_12 */ +#define MAC_PCU_TXOP_12_15__VALUE_12__SHIFT 0 +#define MAC_PCU_TXOP_12_15__VALUE_12__WIDTH 8 +#define MAC_PCU_TXOP_12_15__VALUE_12__MASK 0x000000ffU +#define MAC_PCU_TXOP_12_15__VALUE_12__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXOP_12_15__VALUE_12__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_TXOP_12_15__VALUE_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXOP_12_15__VALUE_12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field VALUE_13 */ +#define MAC_PCU_TXOP_12_15__VALUE_13__SHIFT 8 +#define MAC_PCU_TXOP_12_15__VALUE_13__WIDTH 8 +#define MAC_PCU_TXOP_12_15__VALUE_13__MASK 0x0000ff00U +#define MAC_PCU_TXOP_12_15__VALUE_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_TXOP_12_15__VALUE_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_12_15__VALUE_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_12_15__VALUE_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field VALUE_14 */ +#define MAC_PCU_TXOP_12_15__VALUE_14__SHIFT 16 +#define MAC_PCU_TXOP_12_15__VALUE_14__WIDTH 8 +#define MAC_PCU_TXOP_12_15__VALUE_14__MASK 0x00ff0000U +#define MAC_PCU_TXOP_12_15__VALUE_14__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_TXOP_12_15__VALUE_14__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_12_15__VALUE_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_12_15__VALUE_14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field VALUE_15 */ +#define MAC_PCU_TXOP_12_15__VALUE_15__SHIFT 24 +#define MAC_PCU_TXOP_12_15__VALUE_15__WIDTH 8 +#define MAC_PCU_TXOP_12_15__VALUE_15__MASK 0xff000000U +#define MAC_PCU_TXOP_12_15__VALUE_15__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_TXOP_12_15__VALUE_15__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_TXOP_12_15__VALUE_15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_TXOP_12_15__VALUE_15__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_TXOP_12_15__TYPE u_int32_t +#define MAC_PCU_TXOP_12_15__READ 0xffffffffU +#define MAC_PCU_TXOP_12_15__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TXOP_12_15_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TXOP_12_15 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TXOP_12_15__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS */ +#ifndef __MAC_PCU_GENERIC_TIMERS_MACRO__ +#define __MAC_PCU_GENERIC_TIMERS_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_GENERIC_TIMERS__DATA__SHIFT 0 +#define MAC_PCU_GENERIC_TIMERS__DATA__WIDTH 32 +#define MAC_PCU_GENERIC_TIMERS__DATA__MASK 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_GENERIC_TIMERS__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_GENERIC_TIMERS__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_GENERIC_TIMERS__TYPE u_int32_t +#define MAC_PCU_GENERIC_TIMERS__READ 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS__WRITE 0xffffffffU + +#endif /* __MAC_PCU_GENERIC_TIMERS_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_GENERIC_TIMERS */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_GENERIC_TIMERS__NUM 16 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS_MODE */ +#ifndef __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__ +#define __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__ + +/* macros for field ENABLE */ +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__SHIFT 0 +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WIDTH 8 +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MASK 0x000000ffU +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field OVERFLOW_INDEX */ +#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__SHIFT 8 +#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__WIDTH 3 +#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__MASK 0x00000700U +#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) + +/* macros for field THRESH */ +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__SHIFT 12 +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WIDTH 20 +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MASK 0xfffff000U +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xfffff000U) >> 12) +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0xfffff000U) +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffff000U) | (((u_int32_t)(src) <<\ + 12) & 0xfffff000U) +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0xfffff000U))) +#define MAC_PCU_GENERIC_TIMERS_MODE__TYPE u_int32_t +#define MAC_PCU_GENERIC_TIMERS_MODE__READ 0xfffff7ffU +#define MAC_PCU_GENERIC_TIMERS_MODE__WRITE 0xfffff7ffU + +#endif /* __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_GENERIC_TIMERS_MODE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_GENERIC_TIMERS_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_MODE */ +#ifndef __MAC_PCU_SLP32_MODE_MACRO__ +#define __MAC_PCU_SLP32_MODE_MACRO__ + +/* macros for field HALF_CLK_LATENCY */ +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__SHIFT 0 +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WIDTH 20 +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MASK 0x000fffffU +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__READ(src) \ + (u_int32_t)(src)\ + & 0x000fffffU +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000fffffU) +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffffU) | ((u_int32_t)(src) &\ + 0x000fffffU) +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000fffffU))) + +/* macros for field ENABLE */ +#define MAC_PCU_SLP32_MODE__ENABLE__SHIFT 20 +#define MAC_PCU_SLP32_MODE__ENABLE__WIDTH 1 +#define MAC_PCU_SLP32_MODE__ENABLE__MASK 0x00100000U +#define MAC_PCU_SLP32_MODE__ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_SLP32_MODE__ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_SLP32_MODE__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_SLP32_MODE__ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_SLP32_MODE__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_SLP32_MODE__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field TSF_WRITE_STATUS */ +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__SHIFT 21 +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__WIDTH 1 +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__MASK 0x00200000U +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field DISABLE_32KHZ */ +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__SHIFT 22 +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WIDTH 1 +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MASK 0x00400000U +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field FORCE_BIAS_BLOCK_ON */ +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__SHIFT 23 +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WIDTH 1 +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MASK 0x00800000U +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field TSF2_WRITE_STATUS */ +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__SHIFT 24 +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__WIDTH 1 +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__MASK 0x01000000U +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define MAC_PCU_SLP32_MODE__TYPE u_int32_t +#define MAC_PCU_SLP32_MODE__READ 0x01ffffffU +#define MAC_PCU_SLP32_MODE__WRITE 0x01ffffffU + +#endif /* __MAC_PCU_SLP32_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_SLP32_MODE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_SLP32_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_WAKE */ +#ifndef __MAC_PCU_SLP32_WAKE_MACRO__ +#define __MAC_PCU_SLP32_WAKE_MACRO__ + +/* macros for field XTL_TIME */ +#define MAC_PCU_SLP32_WAKE__XTL_TIME__SHIFT 0 +#define MAC_PCU_SLP32_WAKE__XTL_TIME__WIDTH 16 +#define MAC_PCU_SLP32_WAKE__XTL_TIME__MASK 0x0000ffffU +#define MAC_PCU_SLP32_WAKE__XTL_TIME__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_SLP32_WAKE__XTL_TIME__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_SLP32_WAKE__XTL_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_SLP32_WAKE__XTL_TIME__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_SLP32_WAKE__TYPE u_int32_t +#define MAC_PCU_SLP32_WAKE__READ 0x0000ffffU +#define MAC_PCU_SLP32_WAKE__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_SLP32_WAKE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_SLP32_WAKE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_SLP32_WAKE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_INC */ +#ifndef __MAC_PCU_SLP32_INC_MACRO__ +#define __MAC_PCU_SLP32_INC_MACRO__ + +/* macros for field TSF_INC */ +#define MAC_PCU_SLP32_INC__TSF_INC__SHIFT 0 +#define MAC_PCU_SLP32_INC__TSF_INC__WIDTH 20 +#define MAC_PCU_SLP32_INC__TSF_INC__MASK 0x000fffffU +#define MAC_PCU_SLP32_INC__TSF_INC__READ(src) (u_int32_t)(src) & 0x000fffffU +#define MAC_PCU_SLP32_INC__TSF_INC__WRITE(src) ((u_int32_t)(src) & 0x000fffffU) +#define MAC_PCU_SLP32_INC__TSF_INC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffffU) | ((u_int32_t)(src) &\ + 0x000fffffU) +#define MAC_PCU_SLP32_INC__TSF_INC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000fffffU))) +#define MAC_PCU_SLP32_INC__TYPE u_int32_t +#define MAC_PCU_SLP32_INC__READ 0x000fffffU +#define MAC_PCU_SLP32_INC__WRITE 0x000fffffU + +#endif /* __MAC_PCU_SLP32_INC_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_SLP32_INC */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_SLP32_INC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB1 */ +#ifndef __MAC_PCU_SLP_MIB1_MACRO__ +#define __MAC_PCU_SLP_MIB1_MACRO__ + +/* macros for field SLEEP_CNT */ +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__SHIFT 0 +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__WIDTH 32 +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__MASK 0xffffffffU +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_SLP_MIB1__TYPE u_int32_t +#define MAC_PCU_SLP_MIB1__READ 0xffffffffU +#define MAC_PCU_SLP_MIB1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_SLP_MIB1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_SLP_MIB1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_SLP_MIB1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB2 */ +#ifndef __MAC_PCU_SLP_MIB2_MACRO__ +#define __MAC_PCU_SLP_MIB2_MACRO__ + +/* macros for field CYCLE_CNT */ +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__SHIFT 0 +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__WIDTH 32 +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__MASK 0xffffffffU +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_SLP_MIB2__TYPE u_int32_t +#define MAC_PCU_SLP_MIB2__READ 0xffffffffU +#define MAC_PCU_SLP_MIB2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_SLP_MIB2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_SLP_MIB2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_SLP_MIB2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB3 */ +#ifndef __MAC_PCU_SLP_MIB3_MACRO__ +#define __MAC_PCU_SLP_MIB3_MACRO__ + +/* macros for field CLR_CNT */ +#define MAC_PCU_SLP_MIB3__CLR_CNT__SHIFT 0 +#define MAC_PCU_SLP_MIB3__CLR_CNT__WIDTH 1 +#define MAC_PCU_SLP_MIB3__CLR_CNT__MASK 0x00000001U +#define MAC_PCU_SLP_MIB3__CLR_CNT__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_SLP_MIB3__CLR_CNT__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_PCU_SLP_MIB3__CLR_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_SLP_MIB3__CLR_CNT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_SLP_MIB3__CLR_CNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_SLP_MIB3__CLR_CNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PENDING */ +#define MAC_PCU_SLP_MIB3__PENDING__SHIFT 1 +#define MAC_PCU_SLP_MIB3__PENDING__WIDTH 1 +#define MAC_PCU_SLP_MIB3__PENDING__MASK 0x00000002U +#define MAC_PCU_SLP_MIB3__PENDING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_SLP_MIB3__PENDING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_SLP_MIB3__PENDING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define MAC_PCU_SLP_MIB3__TYPE u_int32_t +#define MAC_PCU_SLP_MIB3__READ 0x00000003U +#define MAC_PCU_SLP_MIB3__WRITE 0x00000003U + +#endif /* __MAC_PCU_SLP_MIB3_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_SLP_MIB3 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_SLP_MIB3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW1 */ +#ifndef __MAC_PCU_WOW1_MACRO__ +#define __MAC_PCU_WOW1_MACRO__ + +/* macros for field PATTERN_ENABLE */ +#define MAC_PCU_WOW1__PATTERN_ENABLE__SHIFT 0 +#define MAC_PCU_WOW1__PATTERN_ENABLE__WIDTH 8 +#define MAC_PCU_WOW1__PATTERN_ENABLE__MASK 0x000000ffU +#define MAC_PCU_WOW1__PATTERN_ENABLE__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_WOW1__PATTERN_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW1__PATTERN_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW1__PATTERN_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_DETECT */ +#define MAC_PCU_WOW1__PATTERN_DETECT__SHIFT 8 +#define MAC_PCU_WOW1__PATTERN_DETECT__WIDTH 8 +#define MAC_PCU_WOW1__PATTERN_DETECT__MASK 0x0000ff00U +#define MAC_PCU_WOW1__PATTERN_DETECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field MAGIC_ENABLE */ +#define MAC_PCU_WOW1__MAGIC_ENABLE__SHIFT 16 +#define MAC_PCU_WOW1__MAGIC_ENABLE__WIDTH 1 +#define MAC_PCU_WOW1__MAGIC_ENABLE__MASK 0x00010000U +#define MAC_PCU_WOW1__MAGIC_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_WOW1__MAGIC_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_WOW1__MAGIC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_WOW1__MAGIC_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_WOW1__MAGIC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_WOW1__MAGIC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field MAGIC_DETECT */ +#define MAC_PCU_WOW1__MAGIC_DETECT__SHIFT 17 +#define MAC_PCU_WOW1__MAGIC_DETECT__WIDTH 1 +#define MAC_PCU_WOW1__MAGIC_DETECT__MASK 0x00020000U +#define MAC_PCU_WOW1__MAGIC_DETECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_WOW1__MAGIC_DETECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_WOW1__MAGIC_DETECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field INTR_ENABLE */ +#define MAC_PCU_WOW1__INTR_ENABLE__SHIFT 18 +#define MAC_PCU_WOW1__INTR_ENABLE__WIDTH 1 +#define MAC_PCU_WOW1__INTR_ENABLE__MASK 0x00040000U +#define MAC_PCU_WOW1__INTR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_WOW1__INTR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_WOW1__INTR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_WOW1__INTR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_WOW1__INTR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_WOW1__INTR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field INTR_DETECT */ +#define MAC_PCU_WOW1__INTR_DETECT__SHIFT 19 +#define MAC_PCU_WOW1__INTR_DETECT__WIDTH 1 +#define MAC_PCU_WOW1__INTR_DETECT__MASK 0x00080000U +#define MAC_PCU_WOW1__INTR_DETECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_WOW1__INTR_DETECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_WOW1__INTR_DETECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field KEEP_ALIVE_FAIL */ +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__SHIFT 20 +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__WIDTH 1 +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__MASK 0x00100000U +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field BEACON_FAIL */ +#define MAC_PCU_WOW1__BEACON_FAIL__SHIFT 21 +#define MAC_PCU_WOW1__BEACON_FAIL__WIDTH 1 +#define MAC_PCU_WOW1__BEACON_FAIL__MASK 0x00200000U +#define MAC_PCU_WOW1__BEACON_FAIL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_WOW1__BEACON_FAIL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_WOW1__BEACON_FAIL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field CW_BITS */ +#define MAC_PCU_WOW1__CW_BITS__SHIFT 28 +#define MAC_PCU_WOW1__CW_BITS__WIDTH 4 +#define MAC_PCU_WOW1__CW_BITS__MASK 0xf0000000U +#define MAC_PCU_WOW1__CW_BITS__READ(src) \ + (((u_int32_t)(src)\ + & 0xf0000000U) >> 28) +#define MAC_PCU_WOW1__CW_BITS__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0xf0000000U) +#define MAC_PCU_WOW1__CW_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((u_int32_t)(src) <<\ + 28) & 0xf0000000U) +#define MAC_PCU_WOW1__CW_BITS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0xf0000000U))) +#define MAC_PCU_WOW1__TYPE u_int32_t +#define MAC_PCU_WOW1__READ 0xf03fffffU +#define MAC_PCU_WOW1__WRITE 0xf03fffffU + +#endif /* __MAC_PCU_WOW1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW2 */ +#ifndef __MAC_PCU_WOW2_MACRO__ +#define __MAC_PCU_WOW2_MACRO__ + +/* macros for field AIFS */ +#define MAC_PCU_WOW2__AIFS__SHIFT 0 +#define MAC_PCU_WOW2__AIFS__WIDTH 8 +#define MAC_PCU_WOW2__AIFS__MASK 0x000000ffU +#define MAC_PCU_WOW2__AIFS__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_WOW2__AIFS__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_WOW2__AIFS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW2__AIFS__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field SLOT */ +#define MAC_PCU_WOW2__SLOT__SHIFT 8 +#define MAC_PCU_WOW2__SLOT__WIDTH 8 +#define MAC_PCU_WOW2__SLOT__MASK 0x0000ff00U +#define MAC_PCU_WOW2__SLOT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW2__SLOT__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define MAC_PCU_WOW2__SLOT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_WOW2__SLOT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field TRY_CNT */ +#define MAC_PCU_WOW2__TRY_CNT__SHIFT 16 +#define MAC_PCU_WOW2__TRY_CNT__WIDTH 8 +#define MAC_PCU_WOW2__TRY_CNT__MASK 0x00ff0000U +#define MAC_PCU_WOW2__TRY_CNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_WOW2__TRY_CNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_WOW2__TRY_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_WOW2__TRY_CNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MAC_PCU_WOW2__TYPE u_int32_t +#define MAC_PCU_WOW2__READ 0x00ffffffU +#define MAC_PCU_WOW2__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_WOW2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER */ +#ifndef __MAC_PCU_LOGIC_ANALYZER_MACRO__ +#define __MAC_PCU_LOGIC_ANALYZER_MACRO__ + +/* macros for field HOLD */ +#define MAC_PCU_LOGIC_ANALYZER__HOLD__SHIFT 0 +#define MAC_PCU_LOGIC_ANALYZER__HOLD__WIDTH 1 +#define MAC_PCU_LOGIC_ANALYZER__HOLD__MASK 0x00000001U +#define MAC_PCU_LOGIC_ANALYZER__HOLD__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_LOGIC_ANALYZER__HOLD__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_LOGIC_ANALYZER__HOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_LOGIC_ANALYZER__HOLD__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_LOGIC_ANALYZER__HOLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_LOGIC_ANALYZER__HOLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field CLEAR */ +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__SHIFT 1 +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__WIDTH 1 +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__MASK 0x00000002U +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field STATE */ +#define MAC_PCU_LOGIC_ANALYZER__STATE__SHIFT 2 +#define MAC_PCU_LOGIC_ANALYZER__STATE__WIDTH 1 +#define MAC_PCU_LOGIC_ANALYZER__STATE__MASK 0x00000004U +#define MAC_PCU_LOGIC_ANALYZER__STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_LOGIC_ANALYZER__STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_LOGIC_ANALYZER__STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field ENABLE */ +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__SHIFT 3 +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__WIDTH 1 +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__MASK 0x00000008U +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field QCU_SEL */ +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__SHIFT 4 +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WIDTH 4 +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MASK 0x000000f0U +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field INT_ADDR */ +#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__SHIFT 8 +#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__WIDTH 10 +#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__MASK 0x0003ff00U +#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003ff00U) >> 8) + +/* macros for field DIAG_MODE */ +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__SHIFT 18 +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WIDTH 14 +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MASK 0xfffc0000U +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0xfffc0000U) >> 18) +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0xfffc0000U) +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((u_int32_t)(src) <<\ + 18) & 0xfffc0000U) +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define MAC_PCU_LOGIC_ANALYZER__TYPE u_int32_t +#define MAC_PCU_LOGIC_ANALYZER__READ 0xffffffffU +#define MAC_PCU_LOGIC_ANALYZER__WRITE 0xffffffffU + +#endif /* __MAC_PCU_LOGIC_ANALYZER_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_LOGIC_ANALYZER */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_LOGIC_ANALYZER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER_32L */ +#ifndef __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__ +#define __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__ + +/* macros for field MASK */ +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__SHIFT 0 +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WIDTH 32 +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MASK 0xffffffffU +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_LOGIC_ANALYZER_32L__TYPE u_int32_t +#define MAC_PCU_LOGIC_ANALYZER_32L__READ 0xffffffffU +#define MAC_PCU_LOGIC_ANALYZER_32L__WRITE 0xffffffffU + +#endif /* __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_LOGIC_ANALYZER_32L */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_LOGIC_ANALYZER_32L__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER_16U */ +#ifndef __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__ +#define __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__ + +/* macros for field MASK */ +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__SHIFT 0 +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WIDTH 16 +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MASK 0x0000ffffU +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_LOGIC_ANALYZER_16U__TYPE u_int32_t +#define MAC_PCU_LOGIC_ANALYZER_16U__READ 0x0000ffffU +#define MAC_PCU_LOGIC_ANALYZER_16U__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_LOGIC_ANALYZER_16U */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_LOGIC_ANALYZER_16U__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_BEACON_FAIL */ +#ifndef __MAC_PCU_WOW3_BEACON_FAIL_MACRO__ +#define __MAC_PCU_WOW3_BEACON_FAIL_MACRO__ + +/* macros for field ENABLE */ +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__SHIFT 0 +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WIDTH 1 +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MASK 0x00000001U +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define MAC_PCU_WOW3_BEACON_FAIL__TYPE u_int32_t +#define MAC_PCU_WOW3_BEACON_FAIL__READ 0x00000001U +#define MAC_PCU_WOW3_BEACON_FAIL__WRITE 0x00000001U + +#endif /* __MAC_PCU_WOW3_BEACON_FAIL_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW3_BEACON_FAIL */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW3_BEACON_FAIL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_BEACON */ +#ifndef __MAC_PCU_WOW3_BEACON_MACRO__ +#define __MAC_PCU_WOW3_BEACON_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_PCU_WOW3_BEACON__TIMEOUT__SHIFT 0 +#define MAC_PCU_WOW3_BEACON__TIMEOUT__WIDTH 32 +#define MAC_PCU_WOW3_BEACON__TIMEOUT__MASK 0xffffffffU +#define MAC_PCU_WOW3_BEACON__TIMEOUT__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_WOW3_BEACON__TIMEOUT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_WOW3_BEACON__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_WOW3_BEACON__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_WOW3_BEACON__TYPE u_int32_t +#define MAC_PCU_WOW3_BEACON__READ 0xffffffffU +#define MAC_PCU_WOW3_BEACON__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW3_BEACON_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW3_BEACON */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW3_BEACON__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_KEEP_ALIVE */ +#ifndef __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__ +#define __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__SHIFT 0 +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WIDTH 32 +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MASK 0xffffffffU +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_WOW3_KEEP_ALIVE__TYPE u_int32_t +#define MAC_PCU_WOW3_KEEP_ALIVE__READ 0xffffffffU +#define MAC_PCU_WOW3_KEEP_ALIVE__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW3_KEEP_ALIVE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW3_KEEP_ALIVE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_KA */ +#ifndef __MAC_PCU_WOW_KA_MACRO__ +#define __MAC_PCU_WOW_KA_MACRO__ + +/* macros for field AUTO_DISABLE */ +#define MAC_PCU_WOW_KA__AUTO_DISABLE__SHIFT 0 +#define MAC_PCU_WOW_KA__AUTO_DISABLE__WIDTH 1 +#define MAC_PCU_WOW_KA__AUTO_DISABLE__MASK 0x00000001U +#define MAC_PCU_WOW_KA__AUTO_DISABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_WOW_KA__AUTO_DISABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_WOW_KA__AUTO_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_WOW_KA__AUTO_DISABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_WOW_KA__AUTO_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_WOW_KA__AUTO_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field FAIL_DISABLE */ +#define MAC_PCU_WOW_KA__FAIL_DISABLE__SHIFT 1 +#define MAC_PCU_WOW_KA__FAIL_DISABLE__WIDTH 1 +#define MAC_PCU_WOW_KA__FAIL_DISABLE__MASK 0x00000002U +#define MAC_PCU_WOW_KA__FAIL_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_WOW_KA__FAIL_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_WOW_KA__FAIL_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_WOW_KA__FAIL_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_WOW_KA__FAIL_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_WOW_KA__FAIL_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field BKOFF_CS_ENABLE */ +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__SHIFT 2 +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WIDTH 1 +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MASK 0x00000004U +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define MAC_PCU_WOW_KA__TYPE u_int32_t +#define MAC_PCU_WOW_KA__READ 0x00000007U +#define MAC_PCU_WOW_KA__WRITE 0x00000007U + +#endif /* __MAC_PCU_WOW_KA_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW_KA */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW_KA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_1US */ +#ifndef __PCU_1US_MACRO__ +#define __PCU_1US_MACRO__ + +/* macros for field SCALER */ +#define PCU_1US__SCALER__SHIFT 0 +#define PCU_1US__SCALER__WIDTH 7 +#define PCU_1US__SCALER__MASK 0x0000007fU +#define PCU_1US__SCALER__READ(src) (u_int32_t)(src) & 0x0000007fU +#define PCU_1US__SCALER__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) +#define PCU_1US__SCALER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define PCU_1US__SCALER__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU))) +#define PCU_1US__TYPE u_int32_t +#define PCU_1US__READ 0x0000007fU +#define PCU_1US__WRITE 0x0000007fU + +#endif /* __PCU_1US_MACRO__ */ + + +/* macros for mac_pcu_reg_block.PCU_1US */ +#define INST_MAC_PCU_REG_BLOCK__PCU_1US__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_KA */ +#ifndef __PCU_KA_MACRO__ +#define __PCU_KA_MACRO__ + +/* macros for field DEL */ +#define PCU_KA__DEL__SHIFT 0 +#define PCU_KA__DEL__WIDTH 12 +#define PCU_KA__DEL__MASK 0x00000fffU +#define PCU_KA__DEL__READ(src) (u_int32_t)(src) & 0x00000fffU +#define PCU_KA__DEL__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) +#define PCU_KA__DEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define PCU_KA__DEL__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000fffU))) +#define PCU_KA__TYPE u_int32_t +#define PCU_KA__READ 0x00000fffU +#define PCU_KA__WRITE 0x00000fffU + +#endif /* __PCU_KA_MACRO__ */ + + +/* macros for mac_pcu_reg_block.PCU_KA */ +#define INST_MAC_PCU_REG_BLOCK__PCU_KA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::WOW_EXACT */ +#ifndef __WOW_EXACT_MACRO__ +#define __WOW_EXACT_MACRO__ + +/* macros for field LENGTH */ +#define WOW_EXACT__LENGTH__SHIFT 0 +#define WOW_EXACT__LENGTH__WIDTH 8 +#define WOW_EXACT__LENGTH__MASK 0x000000ffU +#define WOW_EXACT__LENGTH__READ(src) (u_int32_t)(src) & 0x000000ffU +#define WOW_EXACT__LENGTH__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define WOW_EXACT__LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define WOW_EXACT__LENGTH__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET */ +#define WOW_EXACT__OFFSET__SHIFT 8 +#define WOW_EXACT__OFFSET__WIDTH 8 +#define WOW_EXACT__OFFSET__MASK 0x0000ff00U +#define WOW_EXACT__OFFSET__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define WOW_EXACT__OFFSET__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define WOW_EXACT__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WOW_EXACT__OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WOW_EXACT__TYPE u_int32_t +#define WOW_EXACT__READ 0x0000ffffU +#define WOW_EXACT__WRITE 0x0000ffffU + +#endif /* __WOW_EXACT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.WOW_EXACT */ +#define INST_MAC_PCU_REG_BLOCK__WOW_EXACT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_WOW4 */ +#ifndef __PCU_WOW4_MACRO__ +#define __PCU_WOW4_MACRO__ + +/* macros for field OFFSET0 */ +#define PCU_WOW4__OFFSET0__SHIFT 0 +#define PCU_WOW4__OFFSET0__WIDTH 8 +#define PCU_WOW4__OFFSET0__MASK 0x000000ffU +#define PCU_WOW4__OFFSET0__READ(src) (u_int32_t)(src) & 0x000000ffU +#define PCU_WOW4__OFFSET0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define PCU_WOW4__OFFSET0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define PCU_WOW4__OFFSET0__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET1 */ +#define PCU_WOW4__OFFSET1__SHIFT 8 +#define PCU_WOW4__OFFSET1__WIDTH 8 +#define PCU_WOW4__OFFSET1__MASK 0x0000ff00U +#define PCU_WOW4__OFFSET1__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define PCU_WOW4__OFFSET1__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define PCU_WOW4__OFFSET1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PCU_WOW4__OFFSET1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field OFFSET2 */ +#define PCU_WOW4__OFFSET2__SHIFT 16 +#define PCU_WOW4__OFFSET2__WIDTH 8 +#define PCU_WOW4__OFFSET2__MASK 0x00ff0000U +#define PCU_WOW4__OFFSET2__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) +#define PCU_WOW4__OFFSET2__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) +#define PCU_WOW4__OFFSET2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PCU_WOW4__OFFSET2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field OFFSET3 */ +#define PCU_WOW4__OFFSET3__SHIFT 24 +#define PCU_WOW4__OFFSET3__WIDTH 8 +#define PCU_WOW4__OFFSET3__MASK 0xff000000U +#define PCU_WOW4__OFFSET3__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) +#define PCU_WOW4__OFFSET3__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) +#define PCU_WOW4__OFFSET3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define PCU_WOW4__OFFSET3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define PCU_WOW4__TYPE u_int32_t +#define PCU_WOW4__READ 0xffffffffU +#define PCU_WOW4__WRITE 0xffffffffU + +#endif /* __PCU_WOW4_MACRO__ */ + + +/* macros for mac_pcu_reg_block.PCU_WOW4 */ +#define INST_MAC_PCU_REG_BLOCK__PCU_WOW4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_WOW5 */ +#ifndef __PCU_WOW5_MACRO__ +#define __PCU_WOW5_MACRO__ + +/* macros for field OFFSET4 */ +#define PCU_WOW5__OFFSET4__SHIFT 0 +#define PCU_WOW5__OFFSET4__WIDTH 8 +#define PCU_WOW5__OFFSET4__MASK 0x000000ffU +#define PCU_WOW5__OFFSET4__READ(src) (u_int32_t)(src) & 0x000000ffU +#define PCU_WOW5__OFFSET4__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define PCU_WOW5__OFFSET4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define PCU_WOW5__OFFSET4__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET5 */ +#define PCU_WOW5__OFFSET5__SHIFT 8 +#define PCU_WOW5__OFFSET5__WIDTH 8 +#define PCU_WOW5__OFFSET5__MASK 0x0000ff00U +#define PCU_WOW5__OFFSET5__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define PCU_WOW5__OFFSET5__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define PCU_WOW5__OFFSET5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PCU_WOW5__OFFSET5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field OFFSET6 */ +#define PCU_WOW5__OFFSET6__SHIFT 16 +#define PCU_WOW5__OFFSET6__WIDTH 8 +#define PCU_WOW5__OFFSET6__MASK 0x00ff0000U +#define PCU_WOW5__OFFSET6__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) +#define PCU_WOW5__OFFSET6__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) +#define PCU_WOW5__OFFSET6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PCU_WOW5__OFFSET6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field OFFSET7 */ +#define PCU_WOW5__OFFSET7__SHIFT 24 +#define PCU_WOW5__OFFSET7__WIDTH 8 +#define PCU_WOW5__OFFSET7__MASK 0xff000000U +#define PCU_WOW5__OFFSET7__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) +#define PCU_WOW5__OFFSET7__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) +#define PCU_WOW5__OFFSET7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define PCU_WOW5__OFFSET7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define PCU_WOW5__TYPE u_int32_t +#define PCU_WOW5__READ 0xffffffffU +#define PCU_WOW5__WRITE 0xffffffffU + +#endif /* __PCU_WOW5_MACRO__ */ + + +/* macros for mac_pcu_reg_block.PCU_WOW5 */ +#define INST_MAC_PCU_REG_BLOCK__PCU_WOW5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_MASK_CONT */ +#ifndef __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__ + +/* macros for field MASK1 */ +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WIDTH 8 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MASK 0x000000ffU +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field MASK2 */ +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__SHIFT 8 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WIDTH 8 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MASK 0x0000ff00U +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field MASK3 */ +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__SHIFT 16 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WIDTH 8 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MASK 0x00ff0000U +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__READ 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_PHY_ERR_CNT_MASK_CONT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_PHY_ERR_CNT_MASK_CONT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AZIMUTH_MODE */ +#ifndef __MAC_PCU_AZIMUTH_MODE_MACRO__ +#define __MAC_PCU_AZIMUTH_MODE_MACRO__ + +/* macros for field DISABLE_TSF_UPDATE */ +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__SHIFT 0 +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MASK 0x00000001U +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field KEY_SEARCH_AD1 */ +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__SHIFT 1 +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MASK 0x00000002U +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field TX_TSF_STATUS_SEL */ +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__SHIFT 2 +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MASK 0x00000004U +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field RX_TSF_STATUS_SEL */ +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__SHIFT 3 +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MASK 0x00000008U +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field CLK_EN */ +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__SHIFT 4 +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__MASK 0x00000010U +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field TX_DESC_EN */ +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__SHIFT 5 +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MASK 0x00000020U +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field ACK_CTS_MATCH_TX_AD2 */ +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__SHIFT 6 +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MASK 0x00000040U +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field BA_USES_AD1 */ +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__SHIFT 7 +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MASK 0x00000080U +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field WMAC_CLK_SEL */ +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__SHIFT 8 +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MASK 0x00000100U +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field FILTER_PASS_HOLD */ +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__SHIFT 9 +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MASK 0x00000200U +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) +#define MAC_PCU_AZIMUTH_MODE__TYPE u_int32_t +#define MAC_PCU_AZIMUTH_MODE__READ 0x000003ffU +#define MAC_PCU_AZIMUTH_MODE__WRITE 0x000003ffU + +#endif /* __MAC_PCU_AZIMUTH_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_AZIMUTH_MODE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_AZIMUTH_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AZIMUTH_TIME_STAMP */ +#ifndef __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__ +#define __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__SHIFT 0 +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WIDTH 32 +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MASK 0xffffffffU +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_AZIMUTH_TIME_STAMP__TYPE u_int32_t +#define MAC_PCU_AZIMUTH_TIME_STAMP__READ 0xffffffffU +#define MAC_PCU_AZIMUTH_TIME_STAMP__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_AZIMUTH_TIME_STAMP */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_AZIMUTH_TIME_STAMP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_20_40_MODE */ +#ifndef __MAC_PCU_20_40_MODE_MACRO__ +#define __MAC_PCU_20_40_MODE_MACRO__ + +/* macros for field JOINED_RX_CLEAR */ +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__SHIFT 0 +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WIDTH 1 +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MASK 0x00000001U +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field EXT_PIFS_ENABLE */ +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__SHIFT 1 +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WIDTH 1 +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MASK 0x00000002U +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field TX_HT20_ON_EXT_BUSY */ +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__SHIFT 2 +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WIDTH 1 +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MASK 0x00000004U +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field SWAMPED_FORCES_RX_CLEAR_CTL_IDLE */ +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__SHIFT 3 +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WIDTH 1 +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MASK 0x00000008U +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field PIFS_CYCLES */ +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__SHIFT 4 +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__WIDTH 12 +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__MASK 0x0000fff0U +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fff0U) >> 4) +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x0000fff0U) +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fff0U) | (((u_int32_t)(src) <<\ + 4) & 0x0000fff0U) +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x0000fff0U))) +#define MAC_PCU_20_40_MODE__TYPE u_int32_t +#define MAC_PCU_20_40_MODE__READ 0x0000ffffU +#define MAC_PCU_20_40_MODE__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_20_40_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_20_40_MODE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_20_40_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_H_XFER_TIMEOUT */ +#ifndef __MAC_PCU_H_XFER_TIMEOUT_MACRO__ +#define __MAC_PCU_H_XFER_TIMEOUT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__SHIFT 0 +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__WIDTH 5 +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__MASK 0x0000001fU +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000001fU +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field DISABLE */ +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__SHIFT 5 +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WIDTH 1 +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MASK 0x00000020U +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field EXTXBF_IMMEDIATE_RESP */ +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__SHIFT 6 +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WIDTH 1 +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MASK 0x00000040U +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field DELAY_EXTXBF_ONLY_UPLOAD_H */ +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__SHIFT 7 +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WIDTH 1 +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MASK 0x00000080U +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field EXTXBF_NOACK_NORPT */ +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__SHIFT 8 +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WIDTH 1 +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MASK 0x00000100U +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) +#define MAC_PCU_H_XFER_TIMEOUT__TYPE u_int32_t +#define MAC_PCU_H_XFER_TIMEOUT__READ 0x000001ffU +#define MAC_PCU_H_XFER_TIMEOUT__WRITE 0x000001ffU + +#endif /* __MAC_PCU_H_XFER_TIMEOUT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_H_XFER_TIMEOUT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_H_XFER_TIMEOUT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_CLEAR_DIFF_CNT */ +#ifndef __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__ +#define __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__SHIFT 0 +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WIDTH 32 +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MASK 0xffffffffU +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_RX_CLEAR_DIFF_CNT__TYPE u_int32_t +#define MAC_PCU_RX_CLEAR_DIFF_CNT__READ 0xffffffffU +#define MAC_PCU_RX_CLEAR_DIFF_CNT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_RX_CLEAR_DIFF_CNT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_RX_CLEAR_DIFF_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SELF_GEN_ANTENNA_MASK */ +#ifndef __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__ +#define __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__SHIFT 0 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WIDTH 3 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MASK 0x00000007U +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__TYPE u_int32_t +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__READ 0x00000007U +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__WRITE 0x00000007U + +#endif /* __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_SELF_GEN_ANTENNA_MASK */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_SELF_GEN_ANTENNA_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BA_BAR_CONTROL */ +#ifndef __MAC_PCU_BA_BAR_CONTROL_MACRO__ +#define __MAC_PCU_BA_BAR_CONTROL_MACRO__ + +/* macros for field COMPRESSED_OFFSET */ +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__SHIFT 0 +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WIDTH 4 +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MASK 0x0000000fU +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field ACK_POLICY_OFFSET */ +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__SHIFT 4 +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WIDTH 4 +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MASK 0x000000f0U +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field COMPRESSED_VALUE */ +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__SHIFT 8 +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WIDTH 1 +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MASK 0x00000100U +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field ACK_POLICY_VALUE */ +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__SHIFT 9 +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WIDTH 1 +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MASK 0x00000200U +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field FORCE_NO_MATCH */ +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__SHIFT 10 +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WIDTH 1 +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MASK 0x00000400U +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field TX_BA_CLEAR_BA_VALID */ +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__SHIFT 11 +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WIDTH 1 +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MASK 0x00000800U +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field UPDATE_BA_BITMAP_QOS_NULL */ +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__SHIFT 12 +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WIDTH 1 +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MASK 0x00001000U +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) +#define MAC_PCU_BA_BAR_CONTROL__TYPE u_int32_t +#define MAC_PCU_BA_BAR_CONTROL__READ 0x00001fffU +#define MAC_PCU_BA_BAR_CONTROL__WRITE 0x00001fffU + +#endif /* __MAC_PCU_BA_BAR_CONTROL_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BA_BAR_CONTROL */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BA_BAR_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LEGACY_PLCP_SPOOF */ +#ifndef __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__ +#define __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__ + +/* macros for field EIFS_MINUS_DIFS */ +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__SHIFT 0 +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WIDTH 8 +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MASK 0x000000ffU +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field MIN_LENGTH */ +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__SHIFT 8 +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WIDTH 5 +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MASK 0x00001f00U +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) +#define MAC_PCU_LEGACY_PLCP_SPOOF__TYPE u_int32_t +#define MAC_PCU_LEGACY_PLCP_SPOOF__READ 0x00001fffU +#define MAC_PCU_LEGACY_PLCP_SPOOF__WRITE 0x00001fffU + +#endif /* __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_LEGACY_PLCP_SPOOF */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_LEGACY_PLCP_SPOOF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_MASK_CONT */ +#ifndef __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__ +#define __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__ + +/* macros for field MASK_VALUE */ +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WIDTH 8 +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MASK 0x000000ffU +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field EIFS_VALUE */ +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__SHIFT 16 +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WIDTH 8 +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MASK 0x00ff0000U +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MAC_PCU_PHY_ERROR_MASK_CONT__TYPE u_int32_t +#define MAC_PCU_PHY_ERROR_MASK_CONT__READ 0x00ff00ffU +#define MAC_PCU_PHY_ERROR_MASK_CONT__WRITE 0x00ff00ffU + +#endif /* __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_PHY_ERROR_MASK_CONT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_PHY_ERROR_MASK_CONT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_TIMER */ +#ifndef __MAC_PCU_TX_TIMER_MACRO__ +#define __MAC_PCU_TX_TIMER_MACRO__ + +/* macros for field TX_TIMER */ +#define MAC_PCU_TX_TIMER__TX_TIMER__SHIFT 0 +#define MAC_PCU_TX_TIMER__TX_TIMER__WIDTH 15 +#define MAC_PCU_TX_TIMER__TX_TIMER__MASK 0x00007fffU +#define MAC_PCU_TX_TIMER__TX_TIMER__READ(src) (u_int32_t)(src) & 0x00007fffU +#define MAC_PCU_TX_TIMER__TX_TIMER__WRITE(src) ((u_int32_t)(src) & 0x00007fffU) +#define MAC_PCU_TX_TIMER__TX_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007fffU) | ((u_int32_t)(src) &\ + 0x00007fffU) +#define MAC_PCU_TX_TIMER__TX_TIMER__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00007fffU))) + +/* macros for field TX_TIMER_ENABLE */ +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__SHIFT 15 +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WIDTH 1 +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MASK 0x00008000U +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field RIFS_TIMER */ +#define MAC_PCU_TX_TIMER__RIFS_TIMER__SHIFT 16 +#define MAC_PCU_TX_TIMER__RIFS_TIMER__WIDTH 4 +#define MAC_PCU_TX_TIMER__RIFS_TIMER__MASK 0x000f0000U +#define MAC_PCU_TX_TIMER__RIFS_TIMER__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define MAC_PCU_TX_TIMER__RIFS_TIMER__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define MAC_PCU_TX_TIMER__RIFS_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define MAC_PCU_TX_TIMER__RIFS_TIMER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field QUIET_TIMER */ +#define MAC_PCU_TX_TIMER__QUIET_TIMER__SHIFT 20 +#define MAC_PCU_TX_TIMER__QUIET_TIMER__WIDTH 5 +#define MAC_PCU_TX_TIMER__QUIET_TIMER__MASK 0x01f00000U +#define MAC_PCU_TX_TIMER__QUIET_TIMER__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define MAC_PCU_TX_TIMER__QUIET_TIMER__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define MAC_PCU_TX_TIMER__QUIET_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define MAC_PCU_TX_TIMER__QUIET_TIMER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field QUIET_TIMER_ENABLE */ +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__SHIFT 25 +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WIDTH 1 +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MASK 0x02000000U +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) +#define MAC_PCU_TX_TIMER__TYPE u_int32_t +#define MAC_PCU_TX_TIMER__READ 0x03ffffffU +#define MAC_PCU_TX_TIMER__WRITE 0x03ffffffU + +#endif /* __MAC_PCU_TX_TIMER_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TX_TIMER */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TX_TIMER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXBUF_CTRL */ +#ifndef __MAC_PCU_TXBUF_CTRL_MACRO__ +#define __MAC_PCU_TXBUF_CTRL_MACRO__ + +/* macros for field USABLE_ENTRIES */ +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__SHIFT 0 +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WIDTH 12 +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MASK 0x00000fffU +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field TX_FIFO_WRAP_ENABLE */ +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__SHIFT 16 +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WIDTH 1 +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MASK 0x00010000U +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) +#define MAC_PCU_TXBUF_CTRL__TYPE u_int32_t +#define MAC_PCU_TXBUF_CTRL__READ 0x00010fffU +#define MAC_PCU_TXBUF_CTRL__WRITE 0x00010fffU + +#endif /* __MAC_PCU_TXBUF_CTRL_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TXBUF_CTRL */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TXBUF_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE2 */ +#ifndef __MAC_PCU_MISC_MODE2_MACRO__ +#define __MAC_PCU_MISC_MODE2_MACRO__ + +/* macros for field BUG_21532_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__SHIFT 0 +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MASK 0x00000001U +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field MGMT_CRYPTO_ENABLE */ +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__SHIFT 1 +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MASK 0x00000002U +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field NO_CRYPTO_FOR_NON_DATA_PKT */ +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__SHIFT 2 +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WIDTH 1 +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MASK 0x00000004U +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field BUG_58603_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__SHIFT 3 +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MASK 0x00000008U +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BUG_58057_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__SHIFT 4 +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MASK 0x00000010U +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field RESERVED_0 */ +#define MAC_PCU_MISC_MODE2__RESERVED_0__SHIFT 5 +#define MAC_PCU_MISC_MODE2__RESERVED_0__WIDTH 1 +#define MAC_PCU_MISC_MODE2__RESERVED_0__MASK 0x00000020U +#define MAC_PCU_MISC_MODE2__RESERVED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_MISC_MODE2__RESERVED_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE2__RESERVED_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE2__RESERVED_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_MISC_MODE2__RESERVED_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_MISC_MODE2__RESERVED_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field ADHOC_MCAST_KEYID_ENABLE */ +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__SHIFT 6 +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MASK 0x00000040U +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field CFP_IGNORE */ +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__SHIFT 7 +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__MASK 0x00000080U +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field MGMT_QOS */ +#define MAC_PCU_MISC_MODE2__MGMT_QOS__SHIFT 8 +#define MAC_PCU_MISC_MODE2__MGMT_QOS__WIDTH 8 +#define MAC_PCU_MISC_MODE2__MGMT_QOS__MASK 0x0000ff00U +#define MAC_PCU_MISC_MODE2__MGMT_QOS__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_MISC_MODE2__MGMT_QOS__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_MISC_MODE2__MGMT_QOS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_MISC_MODE2__MGMT_QOS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field ENABLE_LOAD_NAV_BEACON_DURATION */ +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__SHIFT 16 +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WIDTH 1 +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MASK 0x00010000U +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field AGG_WEP */ +#define MAC_PCU_MISC_MODE2__AGG_WEP__SHIFT 17 +#define MAC_PCU_MISC_MODE2__AGG_WEP__WIDTH 1 +#define MAC_PCU_MISC_MODE2__AGG_WEP__MASK 0x00020000U +#define MAC_PCU_MISC_MODE2__AGG_WEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_MISC_MODE2__AGG_WEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_MISC_MODE2__AGG_WEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_MISC_MODE2__AGG_WEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_MISC_MODE2__AGG_WEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_MISC_MODE2__AGG_WEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field BC_MC_WAPI_MODE */ +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__SHIFT 18 +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MASK 0x00040000U +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field DUR_ACCOUNT_BY_BA */ +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__SHIFT 19 +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WIDTH 1 +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MASK 0x00080000U +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field BUG_28676 */ +#define MAC_PCU_MISC_MODE2__BUG_28676__SHIFT 20 +#define MAC_PCU_MISC_MODE2__BUG_28676__WIDTH 1 +#define MAC_PCU_MISC_MODE2__BUG_28676__MASK 0x00100000U +#define MAC_PCU_MISC_MODE2__BUG_28676__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_MISC_MODE2__BUG_28676__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_MISC_MODE2__BUG_28676__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_MISC_MODE2__BUG_28676__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_MISC_MODE2__BUG_28676__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_MISC_MODE2__BUG_28676__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field CLEAR_MORE_FRAG */ +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__SHIFT 21 +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WIDTH 1 +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MASK 0x00200000U +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field IGNORE_TXOP_1ST_PKT */ +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__SHIFT 22 +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WIDTH 1 +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MASK 0x00400000U +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field MPDU_DENSITY_STS_FIX */ +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__SHIFT 23 +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WIDTH 1 +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MASK 0x00800000U +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field MPDU_DENSITY_WAIT_WEP */ +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__SHIFT 24 +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WIDTH 1 +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MASK 0x01000000U +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field RCV_TIMESTAMP_FIX */ +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__SHIFT 25 +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WIDTH 1 +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MASK 0x02000000U +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field PM_FIELD_FOR_NON_CTRL */ +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__SHIFT 26 +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WIDTH 1 +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MASK 0x04000000U +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field DECOUPLE_DECRYPTION */ +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__SHIFT 27 +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WIDTH 1 +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MASK 0x08000000U +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field H_TO_SW_DEBUG_MODE */ +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__SHIFT 28 +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MASK 0x10000000U +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field TXBF_ACT_RPT_DONE_PASS */ +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__SHIFT 29 +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WIDTH 1 +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MASK 0x20000000U +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PCU_LOOP_TXBF */ +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__SHIFT 30 +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WIDTH 1 +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MASK 0x40000000U +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field CLEAR_WEP_TXBUSY_ON_TXURN */ +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__SHIFT 31 +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WIDTH 1 +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MASK 0x80000000U +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define MAC_PCU_MISC_MODE2__TYPE u_int32_t +#define MAC_PCU_MISC_MODE2__READ 0xffffffffU +#define MAC_PCU_MISC_MODE2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_MISC_MODE2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_MISC_MODE2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_MISC_MODE2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_ALT_AES_MUTE_MASK */ +#ifndef __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__ +#define __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__ + +/* macros for field QOS */ +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__SHIFT 16 +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WIDTH 16 +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MASK 0xffff0000U +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_ALT_AES_MUTE_MASK__TYPE u_int32_t +#define MAC_PCU_ALT_AES_MUTE_MASK__READ 0xffff0000U +#define MAC_PCU_ALT_AES_MUTE_MASK__WRITE 0xffff0000U + +#endif /* __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_ALT_AES_MUTE_MASK */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_ALT_AES_MUTE_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW6 */ +#ifndef __MAC_PCU_WOW6_MACRO__ +#define __MAC_PCU_WOW6_MACRO__ + +/* macros for field RXBUF_START_ADDR */ +#define MAC_PCU_WOW6__RXBUF_START_ADDR__SHIFT 0 +#define MAC_PCU_WOW6__RXBUF_START_ADDR__WIDTH 16 +#define MAC_PCU_WOW6__RXBUF_START_ADDR__MASK 0x0000ffffU +#define MAC_PCU_WOW6__RXBUF_START_ADDR__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_PCU_WOW6__TYPE u_int32_t +#define MAC_PCU_WOW6__READ 0x0000ffffU + +#endif /* __MAC_PCU_WOW6_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW6 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG1 */ +#ifndef __ASYNC_FIFO_REG1_MACRO__ +#define __ASYNC_FIFO_REG1_MACRO__ + +/* macros for field DBG */ +#define ASYNC_FIFO_REG1__DBG__SHIFT 0 +#define ASYNC_FIFO_REG1__DBG__WIDTH 30 +#define ASYNC_FIFO_REG1__DBG__MASK 0x3fffffffU +#define ASYNC_FIFO_REG1__DBG__READ(src) (u_int32_t)(src) & 0x3fffffffU +#define ASYNC_FIFO_REG1__DBG__WRITE(src) ((u_int32_t)(src) & 0x3fffffffU) +#define ASYNC_FIFO_REG1__DBG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fffffffU) | ((u_int32_t)(src) &\ + 0x3fffffffU) +#define ASYNC_FIFO_REG1__DBG__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x3fffffffU))) +#define ASYNC_FIFO_REG1__TYPE u_int32_t +#define ASYNC_FIFO_REG1__READ 0x3fffffffU +#define ASYNC_FIFO_REG1__WRITE 0x3fffffffU + +#endif /* __ASYNC_FIFO_REG1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.ASYNC_FIFO_REG1 */ +#define INST_MAC_PCU_REG_BLOCK__ASYNC_FIFO_REG1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG2 */ +#ifndef __ASYNC_FIFO_REG2_MACRO__ +#define __ASYNC_FIFO_REG2_MACRO__ + +/* macros for field DBG */ +#define ASYNC_FIFO_REG2__DBG__SHIFT 0 +#define ASYNC_FIFO_REG2__DBG__WIDTH 28 +#define ASYNC_FIFO_REG2__DBG__MASK 0x0fffffffU +#define ASYNC_FIFO_REG2__DBG__READ(src) (u_int32_t)(src) & 0x0fffffffU +#define ASYNC_FIFO_REG2__DBG__WRITE(src) ((u_int32_t)(src) & 0x0fffffffU) +#define ASYNC_FIFO_REG2__DBG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffffffU) | ((u_int32_t)(src) &\ + 0x0fffffffU) +#define ASYNC_FIFO_REG2__DBG__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0fffffffU))) +#define ASYNC_FIFO_REG2__TYPE u_int32_t +#define ASYNC_FIFO_REG2__READ 0x0fffffffU +#define ASYNC_FIFO_REG2__WRITE 0x0fffffffU + +#endif /* __ASYNC_FIFO_REG2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.ASYNC_FIFO_REG2 */ +#define INST_MAC_PCU_REG_BLOCK__ASYNC_FIFO_REG2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG3 */ +#ifndef __ASYNC_FIFO_REG3_MACRO__ +#define __ASYNC_FIFO_REG3_MACRO__ + +/* macros for field DBG */ +#define ASYNC_FIFO_REG3__DBG__SHIFT 0 +#define ASYNC_FIFO_REG3__DBG__WIDTH 10 +#define ASYNC_FIFO_REG3__DBG__MASK 0x000003ffU +#define ASYNC_FIFO_REG3__DBG__READ(src) (u_int32_t)(src) & 0x000003ffU +#define ASYNC_FIFO_REG3__DBG__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define ASYNC_FIFO_REG3__DBG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define ASYNC_FIFO_REG3__DBG__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field DATAPATH_SEL */ +#define ASYNC_FIFO_REG3__DATAPATH_SEL__SHIFT 10 +#define ASYNC_FIFO_REG3__DATAPATH_SEL__WIDTH 1 +#define ASYNC_FIFO_REG3__DATAPATH_SEL__MASK 0x00000400U +#define ASYNC_FIFO_REG3__DATAPATH_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define ASYNC_FIFO_REG3__DATAPATH_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define ASYNC_FIFO_REG3__DATAPATH_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define ASYNC_FIFO_REG3__DATAPATH_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define ASYNC_FIFO_REG3__DATAPATH_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define ASYNC_FIFO_REG3__DATAPATH_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field SFT_RST_N */ +#define ASYNC_FIFO_REG3__SFT_RST_N__SHIFT 31 +#define ASYNC_FIFO_REG3__SFT_RST_N__WIDTH 1 +#define ASYNC_FIFO_REG3__SFT_RST_N__MASK 0x80000000U +#define ASYNC_FIFO_REG3__SFT_RST_N__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define ASYNC_FIFO_REG3__SFT_RST_N__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define ASYNC_FIFO_REG3__SFT_RST_N__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define ASYNC_FIFO_REG3__SFT_RST_N__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define ASYNC_FIFO_REG3__SFT_RST_N__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define ASYNC_FIFO_REG3__SFT_RST_N__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define ASYNC_FIFO_REG3__TYPE u_int32_t +#define ASYNC_FIFO_REG3__READ 0x800007ffU +#define ASYNC_FIFO_REG3__WRITE 0x800007ffU + +#endif /* __ASYNC_FIFO_REG3_MACRO__ */ + + +/* macros for mac_pcu_reg_block.ASYNC_FIFO_REG3 */ +#define INST_MAC_PCU_REG_BLOCK__ASYNC_FIFO_REG3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW5 */ +#ifndef __MAC_PCU_WOW5_MACRO__ +#define __MAC_PCU_WOW5_MACRO__ + +/* macros for field RX_ABORT_ENABLE */ +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__SHIFT 0 +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__WIDTH 16 +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__MASK 0x0000ffffU +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_WOW5__TYPE u_int32_t +#define MAC_PCU_WOW5__READ 0x0000ffffU +#define MAC_PCU_WOW5__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_WOW5_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW5 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH1 */ +#ifndef __MAC_PCU_WOW_LENGTH1_MACRO__ +#define __MAC_PCU_WOW_LENGTH1_MACRO__ + +/* macros for field PATTERN_3 */ +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__SHIFT 0 +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__WIDTH 8 +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__MASK 0x000000ffU +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_2 */ +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__SHIFT 8 +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__WIDTH 8 +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__MASK 0x0000ff00U +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field PATTERN_1 */ +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__SHIFT 16 +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__WIDTH 8 +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__MASK 0x00ff0000U +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field PATTERN_0 */ +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__SHIFT 24 +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__WIDTH 8 +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__MASK 0xff000000U +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_WOW_LENGTH1__TYPE u_int32_t +#define MAC_PCU_WOW_LENGTH1__READ 0xffffffffU +#define MAC_PCU_WOW_LENGTH1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW_LENGTH1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW_LENGTH1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW_LENGTH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH2 */ +#ifndef __MAC_PCU_WOW_LENGTH2_MACRO__ +#define __MAC_PCU_WOW_LENGTH2_MACRO__ + +/* macros for field PATTERN_7 */ +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__SHIFT 0 +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__WIDTH 8 +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__MASK 0x000000ffU +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_6 */ +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__SHIFT 8 +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__WIDTH 8 +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__MASK 0x0000ff00U +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field PATTERN_5 */ +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__SHIFT 16 +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__WIDTH 8 +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__MASK 0x00ff0000U +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field PATTERN_4 */ +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__SHIFT 24 +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__WIDTH 8 +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__MASK 0xff000000U +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_WOW_LENGTH2__TYPE u_int32_t +#define MAC_PCU_WOW_LENGTH2__READ 0xffffffffU +#define MAC_PCU_WOW_LENGTH2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW_LENGTH2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW_LENGTH2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW_LENGTH2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::WOW_PATTERN_MATCH_LESS_THAN_256_BYTES */ +#ifndef __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__ +#define __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__ + +/* macros for field EN */ +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__SHIFT 0 +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WIDTH 16 +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MASK 0x0000ffffU +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__TYPE u_int32_t +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__READ 0x0000ffffU +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__WRITE 0x0000ffffU + +#endif /* __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__ */ + + +/* macros for mac_pcu_reg_block.WOW_PATTERN_MATCH_LESS_THAN_256_BYTES */ +#define INST_MAC_PCU_REG_BLOCK__WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW4 */ +#ifndef __MAC_PCU_WOW4_MACRO__ +#define __MAC_PCU_WOW4_MACRO__ + +/* macros for field PATTERN_ENABLE */ +#define MAC_PCU_WOW4__PATTERN_ENABLE__SHIFT 0 +#define MAC_PCU_WOW4__PATTERN_ENABLE__WIDTH 8 +#define MAC_PCU_WOW4__PATTERN_ENABLE__MASK 0x000000ffU +#define MAC_PCU_WOW4__PATTERN_ENABLE__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_WOW4__PATTERN_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW4__PATTERN_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW4__PATTERN_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_DETECT */ +#define MAC_PCU_WOW4__PATTERN_DETECT__SHIFT 8 +#define MAC_PCU_WOW4__PATTERN_DETECT__WIDTH 8 +#define MAC_PCU_WOW4__PATTERN_DETECT__MASK 0x0000ff00U +#define MAC_PCU_WOW4__PATTERN_DETECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW4__TYPE u_int32_t +#define MAC_PCU_WOW4__READ 0x0000ffffU +#define MAC_PCU_WOW4__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_WOW4_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW4 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::WOW2_EXACT */ +#ifndef __WOW2_EXACT_MACRO__ +#define __WOW2_EXACT_MACRO__ + +/* macros for field LENGTH */ +#define WOW2_EXACT__LENGTH__SHIFT 0 +#define WOW2_EXACT__LENGTH__WIDTH 8 +#define WOW2_EXACT__LENGTH__MASK 0x000000ffU +#define WOW2_EXACT__LENGTH__READ(src) (u_int32_t)(src) & 0x000000ffU +#define WOW2_EXACT__LENGTH__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define WOW2_EXACT__LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define WOW2_EXACT__LENGTH__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET */ +#define WOW2_EXACT__OFFSET__SHIFT 8 +#define WOW2_EXACT__OFFSET__WIDTH 8 +#define WOW2_EXACT__OFFSET__MASK 0x0000ff00U +#define WOW2_EXACT__OFFSET__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define WOW2_EXACT__OFFSET__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define WOW2_EXACT__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WOW2_EXACT__OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WOW2_EXACT__TYPE u_int32_t +#define WOW2_EXACT__READ 0x0000ffffU +#define WOW2_EXACT__WRITE 0x0000ffffU + +#endif /* __WOW2_EXACT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.WOW2_EXACT */ +#define INST_MAC_PCU_REG_BLOCK__WOW2_EXACT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_WOW6 */ +#ifndef __PCU_WOW6_MACRO__ +#define __PCU_WOW6_MACRO__ + +/* macros for field OFFSET8 */ +#define PCU_WOW6__OFFSET8__SHIFT 0 +#define PCU_WOW6__OFFSET8__WIDTH 8 +#define PCU_WOW6__OFFSET8__MASK 0x000000ffU +#define PCU_WOW6__OFFSET8__READ(src) (u_int32_t)(src) & 0x000000ffU +#define PCU_WOW6__OFFSET8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define PCU_WOW6__OFFSET8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define PCU_WOW6__OFFSET8__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET9 */ +#define PCU_WOW6__OFFSET9__SHIFT 8 +#define PCU_WOW6__OFFSET9__WIDTH 8 +#define PCU_WOW6__OFFSET9__MASK 0x0000ff00U +#define PCU_WOW6__OFFSET9__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define PCU_WOW6__OFFSET9__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define PCU_WOW6__OFFSET9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PCU_WOW6__OFFSET9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field OFFSET10 */ +#define PCU_WOW6__OFFSET10__SHIFT 16 +#define PCU_WOW6__OFFSET10__WIDTH 8 +#define PCU_WOW6__OFFSET10__MASK 0x00ff0000U +#define PCU_WOW6__OFFSET10__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) +#define PCU_WOW6__OFFSET10__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) +#define PCU_WOW6__OFFSET10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PCU_WOW6__OFFSET10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field OFFSET11 */ +#define PCU_WOW6__OFFSET11__SHIFT 24 +#define PCU_WOW6__OFFSET11__WIDTH 8 +#define PCU_WOW6__OFFSET11__MASK 0xff000000U +#define PCU_WOW6__OFFSET11__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) +#define PCU_WOW6__OFFSET11__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) +#define PCU_WOW6__OFFSET11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define PCU_WOW6__OFFSET11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define PCU_WOW6__TYPE u_int32_t +#define PCU_WOW6__READ 0xffffffffU +#define PCU_WOW6__WRITE 0xffffffffU + +#endif /* __PCU_WOW6_MACRO__ */ + + +/* macros for mac_pcu_reg_block.PCU_WOW6 */ +#define INST_MAC_PCU_REG_BLOCK__PCU_WOW6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_WOW7 */ +#ifndef __PCU_WOW7_MACRO__ +#define __PCU_WOW7_MACRO__ + +/* macros for field OFFSET12 */ +#define PCU_WOW7__OFFSET12__SHIFT 0 +#define PCU_WOW7__OFFSET12__WIDTH 8 +#define PCU_WOW7__OFFSET12__MASK 0x000000ffU +#define PCU_WOW7__OFFSET12__READ(src) (u_int32_t)(src) & 0x000000ffU +#define PCU_WOW7__OFFSET12__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define PCU_WOW7__OFFSET12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define PCU_WOW7__OFFSET12__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET13 */ +#define PCU_WOW7__OFFSET13__SHIFT 8 +#define PCU_WOW7__OFFSET13__WIDTH 8 +#define PCU_WOW7__OFFSET13__MASK 0x0000ff00U +#define PCU_WOW7__OFFSET13__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define PCU_WOW7__OFFSET13__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define PCU_WOW7__OFFSET13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PCU_WOW7__OFFSET13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field OFFSET14 */ +#define PCU_WOW7__OFFSET14__SHIFT 16 +#define PCU_WOW7__OFFSET14__WIDTH 8 +#define PCU_WOW7__OFFSET14__MASK 0x00ff0000U +#define PCU_WOW7__OFFSET14__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) +#define PCU_WOW7__OFFSET14__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) +#define PCU_WOW7__OFFSET14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PCU_WOW7__OFFSET14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field OFFSET15 */ +#define PCU_WOW7__OFFSET15__SHIFT 24 +#define PCU_WOW7__OFFSET15__WIDTH 8 +#define PCU_WOW7__OFFSET15__MASK 0xff000000U +#define PCU_WOW7__OFFSET15__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) +#define PCU_WOW7__OFFSET15__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) +#define PCU_WOW7__OFFSET15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define PCU_WOW7__OFFSET15__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define PCU_WOW7__TYPE u_int32_t +#define PCU_WOW7__READ 0xffffffffU +#define PCU_WOW7__WRITE 0xffffffffU + +#endif /* __PCU_WOW7_MACRO__ */ + + +/* macros for mac_pcu_reg_block.PCU_WOW7 */ +#define INST_MAC_PCU_REG_BLOCK__PCU_WOW7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH3 */ +#ifndef __MAC_PCU_WOW_LENGTH3_MACRO__ +#define __MAC_PCU_WOW_LENGTH3_MACRO__ + +/* macros for field PATTERN_11 */ +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__SHIFT 0 +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__WIDTH 8 +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__MASK 0x000000ffU +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_10 */ +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__SHIFT 8 +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__WIDTH 8 +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__MASK 0x0000ff00U +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field PATTERN_9 */ +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__SHIFT 16 +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__WIDTH 8 +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__MASK 0x00ff0000U +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field PATTERN_8 */ +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__SHIFT 24 +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__WIDTH 8 +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__MASK 0xff000000U +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_WOW_LENGTH3__TYPE u_int32_t +#define MAC_PCU_WOW_LENGTH3__READ 0xffffffffU +#define MAC_PCU_WOW_LENGTH3__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW_LENGTH3_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW_LENGTH3 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW_LENGTH3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH4 */ +#ifndef __MAC_PCU_WOW_LENGTH4_MACRO__ +#define __MAC_PCU_WOW_LENGTH4_MACRO__ + +/* macros for field PATTERN_15 */ +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__SHIFT 0 +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__WIDTH 8 +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__MASK 0x000000ffU +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_14 */ +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__SHIFT 8 +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__WIDTH 8 +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__MASK 0x0000ff00U +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field PATTERN_13 */ +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__SHIFT 16 +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__WIDTH 8 +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__MASK 0x00ff0000U +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field PATTERN_12 */ +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__SHIFT 24 +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__WIDTH 8 +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__MASK 0xff000000U +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_WOW_LENGTH4__TYPE u_int32_t +#define MAC_PCU_WOW_LENGTH4__READ 0xffffffffU +#define MAC_PCU_WOW_LENGTH4__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW_LENGTH4_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_WOW_LENGTH4 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_WOW_LENGTH4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOCATION_MODE_CONTROL */ +#ifndef __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__ +#define __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__ + +/* macros for field ENABLE */ +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__SHIFT 0 +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WIDTH 1 +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MASK 0x00000001U +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define MAC_PCU_LOCATION_MODE_CONTROL__TYPE u_int32_t +#define MAC_PCU_LOCATION_MODE_CONTROL__READ 0x00000001U +#define MAC_PCU_LOCATION_MODE_CONTROL__WRITE 0x00000001U + +#endif /* __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_LOCATION_MODE_CONTROL */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_LOCATION_MODE_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOCATION_MODE_TIMER */ +#ifndef __MAC_PCU_LOCATION_MODE_TIMER_MACRO__ +#define __MAC_PCU_LOCATION_MODE_TIMER_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__SHIFT 0 +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WIDTH 32 +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MASK 0xffffffffU +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_LOCATION_MODE_TIMER__TYPE u_int32_t +#define MAC_PCU_LOCATION_MODE_TIMER__READ 0xffffffffU +#define MAC_PCU_LOCATION_MODE_TIMER__WRITE 0xffffffffU + +#endif /* __MAC_PCU_LOCATION_MODE_TIMER_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_LOCATION_MODE_TIMER */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_LOCATION_MODE_TIMER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF2_L32 */ +#ifndef __MAC_PCU_TSF2_L32_MACRO__ +#define __MAC_PCU_TSF2_L32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TSF2_L32__VALUE__SHIFT 0 +#define MAC_PCU_TSF2_L32__VALUE__WIDTH 32 +#define MAC_PCU_TSF2_L32__VALUE__MASK 0xffffffffU +#define MAC_PCU_TSF2_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TSF2_L32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TSF2_L32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TSF2_L32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TSF2_L32__TYPE u_int32_t +#define MAC_PCU_TSF2_L32__READ 0xffffffffU +#define MAC_PCU_TSF2_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TSF2_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TSF2_L32 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TSF2_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF2_U32 */ +#ifndef __MAC_PCU_TSF2_U32_MACRO__ +#define __MAC_PCU_TSF2_U32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TSF2_U32__VALUE__SHIFT 0 +#define MAC_PCU_TSF2_U32__VALUE__WIDTH 32 +#define MAC_PCU_TSF2_U32__VALUE__MASK 0xffffffffU +#define MAC_PCU_TSF2_U32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TSF2_U32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TSF2_U32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TSF2_U32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TSF2_U32__TYPE u_int32_t +#define MAC_PCU_TSF2_U32__READ 0xffffffffU +#define MAC_PCU_TSF2_U32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TSF2_U32_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TSF2_U32 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TSF2_U32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID2_L32 */ +#ifndef __MAC_PCU_BSSID2_L32_MACRO__ +#define __MAC_PCU_BSSID2_L32_MACRO__ + +/* macros for field ADDR */ +#define MAC_PCU_BSSID2_L32__ADDR__SHIFT 0 +#define MAC_PCU_BSSID2_L32__ADDR__WIDTH 32 +#define MAC_PCU_BSSID2_L32__ADDR__MASK 0xffffffffU +#define MAC_PCU_BSSID2_L32__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_BSSID2_L32__ADDR__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_BSSID2_L32__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BSSID2_L32__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BSSID2_L32__TYPE u_int32_t +#define MAC_PCU_BSSID2_L32__READ 0xffffffffU +#define MAC_PCU_BSSID2_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BSSID2_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BSSID2_L32 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BSSID2_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID2_U16 */ +#ifndef __MAC_PCU_BSSID2_U16_MACRO__ +#define __MAC_PCU_BSSID2_U16_MACRO__ + +/* macros for field ADDR */ +#define MAC_PCU_BSSID2_U16__ADDR__SHIFT 0 +#define MAC_PCU_BSSID2_U16__ADDR__WIDTH 16 +#define MAC_PCU_BSSID2_U16__ADDR__MASK 0x0000ffffU +#define MAC_PCU_BSSID2_U16__ADDR__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_BSSID2_U16__ADDR__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_PCU_BSSID2_U16__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_BSSID2_U16__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field ENABLE */ +#define MAC_PCU_BSSID2_U16__ENABLE__SHIFT 16 +#define MAC_PCU_BSSID2_U16__ENABLE__WIDTH 1 +#define MAC_PCU_BSSID2_U16__ENABLE__MASK 0x00010000U +#define MAC_PCU_BSSID2_U16__ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_BSSID2_U16__ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_BSSID2_U16__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_BSSID2_U16__ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_BSSID2_U16__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_BSSID2_U16__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) +#define MAC_PCU_BSSID2_U16__TYPE u_int32_t +#define MAC_PCU_BSSID2_U16__READ 0x0001ffffU +#define MAC_PCU_BSSID2_U16__WRITE 0x0001ffffU + +#endif /* __MAC_PCU_BSSID2_U16_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BSSID2_U16 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BSSID2_U16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_DIRECT_CONNECT */ +#ifndef __MAC_PCU_DIRECT_CONNECT_MACRO__ +#define __MAC_PCU_DIRECT_CONNECT_MACRO__ + +/* macros for field AP_STA_ENABLE */ +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__SHIFT 0 +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MASK 0x00000001U +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field TBTT_TIMER_0_8_SEL */ +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__SHIFT 4 +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MASK 0x00000010U +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field DMA_BALERT_TIMER_1_9_SEL */ +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__SHIFT 5 +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MASK 0x00000020U +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field SW_BALERT_TIMER_2_10_SEL */ +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__SHIFT 6 +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MASK 0x00000040U +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field HCF_TO_TIMER_3_11_SEL */ +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__SHIFT 7 +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MASK 0x00000080U +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field NEXT_TIM_TIMER_4_12_SEL */ +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__SHIFT 8 +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MASK 0x00000100U +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field NEXT_DTIM_TIMER_5_13_SEL */ +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__SHIFT 9 +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MASK 0x00000200U +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field QUIET_TM_TIMER_6_14_SEL */ +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__SHIFT 10 +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MASK 0x00000400U +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field TBTT2_TIMER_0_8_SEL */ +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__SHIFT 11 +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MASK 0x00000800U +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field AP_TSF_1_2_SEL */ +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__SHIFT 12 +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MASK 0x00001000U +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field STA_TSF_1_2_SEL */ +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__SHIFT 13 +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MASK 0x00002000U +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) +#define MAC_PCU_DIRECT_CONNECT__TYPE u_int32_t +#define MAC_PCU_DIRECT_CONNECT__READ 0x00003ff1U +#define MAC_PCU_DIRECT_CONNECT__WRITE 0x00003ff1U + +#endif /* __MAC_PCU_DIRECT_CONNECT_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_DIRECT_CONNECT */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_DIRECT_CONNECT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TID_TO_AC */ +#ifndef __MAC_PCU_TID_TO_AC_MACRO__ +#define __MAC_PCU_TID_TO_AC_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_TID_TO_AC__DATA__SHIFT 0 +#define MAC_PCU_TID_TO_AC__DATA__WIDTH 32 +#define MAC_PCU_TID_TO_AC__DATA__MASK 0xffffffffU +#define MAC_PCU_TID_TO_AC__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TID_TO_AC__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TID_TO_AC__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TID_TO_AC__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TID_TO_AC__TYPE u_int32_t +#define MAC_PCU_TID_TO_AC__READ 0xffffffffU +#define MAC_PCU_TID_TO_AC__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TID_TO_AC_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TID_TO_AC */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TID_TO_AC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_HP_QUEUE */ +#ifndef __MAC_PCU_HP_QUEUE_MACRO__ +#define __MAC_PCU_HP_QUEUE_MACRO__ + +/* macros for field ENABLE */ +#define MAC_PCU_HP_QUEUE__ENABLE__SHIFT 0 +#define MAC_PCU_HP_QUEUE__ENABLE__WIDTH 1 +#define MAC_PCU_HP_QUEUE__ENABLE__MASK 0x00000001U +#define MAC_PCU_HP_QUEUE__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_HP_QUEUE__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_PCU_HP_QUEUE__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_HP_QUEUE__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_HP_QUEUE__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_HP_QUEUE__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field AC_MASK_BE */ +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__SHIFT 1 +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__WIDTH 1 +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__MASK 0x00000002U +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field AC_MASK_BK */ +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__SHIFT 2 +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__WIDTH 1 +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__MASK 0x00000004U +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field AC_MASK_VI */ +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__SHIFT 3 +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__WIDTH 1 +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__MASK 0x00000008U +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field AC_MASK_VO */ +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__SHIFT 4 +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__WIDTH 1 +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__MASK 0x00000010U +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field HPQON_UAPSD */ +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__SHIFT 5 +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WIDTH 1 +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MASK 0x00000020U +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field FRAME_FILTER_ENABLE0 */ +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__SHIFT 6 +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WIDTH 1 +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MASK 0x00000040U +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field FRAME_BSSID_MATCH0 */ +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__SHIFT 7 +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WIDTH 1 +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MASK 0x00000080U +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field FRAME_TYPE0 */ +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__SHIFT 8 +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WIDTH 2 +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MASK 0x00000300U +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field FRAME_TYPE_MASK0 */ +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__SHIFT 10 +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WIDTH 2 +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MASK 0x00000c00U +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) + +/* macros for field FRAME_SUBTYPE0 */ +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__SHIFT 12 +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WIDTH 4 +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MASK 0x0000f000U +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field FRAME_SUBTYPE_MASK0 */ +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__SHIFT 16 +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WIDTH 4 +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MASK 0x000f0000U +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field UAPSD_EN */ +#define MAC_PCU_HP_QUEUE__UAPSD_EN__SHIFT 20 +#define MAC_PCU_HP_QUEUE__UAPSD_EN__WIDTH 1 +#define MAC_PCU_HP_QUEUE__UAPSD_EN__MASK 0x00100000U +#define MAC_PCU_HP_QUEUE__UAPSD_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_HP_QUEUE__UAPSD_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_HP_QUEUE__UAPSD_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_HP_QUEUE__UAPSD_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_HP_QUEUE__UAPSD_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_HP_QUEUE__UAPSD_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) +#define MAC_PCU_HP_QUEUE__TYPE u_int32_t +#define MAC_PCU_HP_QUEUE__READ 0x001fffffU +#define MAC_PCU_HP_QUEUE__WRITE 0x001fffffU + +#endif /* __MAC_PCU_HP_QUEUE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_HP_QUEUE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_HP_QUEUE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS0 */ +#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__ +#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BLUETOOTH_BT_WEIGHTS0 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BLUETOOTH_BT_WEIGHTS0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS1 */ +#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__ +#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BLUETOOTH_BT_WEIGHTS1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BLUETOOTH_BT_WEIGHTS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS2 */ +#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__ +#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BLUETOOTH_BT_WEIGHTS2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BLUETOOTH_BT_WEIGHTS2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS3 */ +#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__ +#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BLUETOOTH_BT_WEIGHTS3 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BLUETOOTH_BT_WEIGHTS3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT0 */ +#ifndef __MAC_PCU_AGC_SATURATION_CNT0_MACRO__ +#define __MAC_PCU_AGC_SATURATION_CNT0_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__SHIFT 0 +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WIDTH 32 +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MASK 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_AGC_SATURATION_CNT0__TYPE u_int32_t +#define MAC_PCU_AGC_SATURATION_CNT0__READ 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT0__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AGC_SATURATION_CNT0_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_AGC_SATURATION_CNT0 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_AGC_SATURATION_CNT0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT1 */ +#ifndef __MAC_PCU_AGC_SATURATION_CNT1_MACRO__ +#define __MAC_PCU_AGC_SATURATION_CNT1_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__SHIFT 0 +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WIDTH 32 +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MASK 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_AGC_SATURATION_CNT1__TYPE u_int32_t +#define MAC_PCU_AGC_SATURATION_CNT1__READ 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AGC_SATURATION_CNT1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_AGC_SATURATION_CNT1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_AGC_SATURATION_CNT1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT2 */ +#ifndef __MAC_PCU_AGC_SATURATION_CNT2_MACRO__ +#define __MAC_PCU_AGC_SATURATION_CNT2_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__SHIFT 0 +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WIDTH 32 +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MASK 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_AGC_SATURATION_CNT2__TYPE u_int32_t +#define MAC_PCU_AGC_SATURATION_CNT2__READ 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AGC_SATURATION_CNT2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_AGC_SATURATION_CNT2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_AGC_SATURATION_CNT2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_HW_BCN_PROC1 */ +#ifndef __MAC_PCU_HW_BCN_PROC1_MACRO__ +#define __MAC_PCU_HW_BCN_PROC1_MACRO__ + +/* macros for field CRC_ENABLE */ +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__SHIFT 0 +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MASK 0x00000001U +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RESET_CRC */ +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__SHIFT 1 +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MASK 0x00000002U +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field EXCLUDE_BCN_INTVL */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__SHIFT 2 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MASK 0x00000004U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field EXCLUDE_CAP_INFO */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__SHIFT 3 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MASK 0x00000008U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field EXCLUDE_TIM_ELM */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__SHIFT 4 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MASK 0x00000010U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field EXCLUDE_ELM0 */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__SHIFT 5 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MASK 0x00000020U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field EXCLUDE_ELM1 */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__SHIFT 6 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MASK 0x00000040U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field EXCLUDE_ELM2 */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__SHIFT 7 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MASK 0x00000080U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field ELM0_ID */ +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__SHIFT 8 +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WIDTH 8 +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MASK 0x0000ff00U +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field ELM1_ID */ +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__SHIFT 16 +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WIDTH 8 +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MASK 0x00ff0000U +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field ELM2_ID */ +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__SHIFT 24 +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WIDTH 8 +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MASK 0xff000000U +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_HW_BCN_PROC1__TYPE u_int32_t +#define MAC_PCU_HW_BCN_PROC1__READ 0xffffffffU +#define MAC_PCU_HW_BCN_PROC1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_HW_BCN_PROC1_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_HW_BCN_PROC1 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_HW_BCN_PROC1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_HW_BCN_PROC2 */ +#ifndef __MAC_PCU_HW_BCN_PROC2_MACRO__ +#define __MAC_PCU_HW_BCN_PROC2_MACRO__ + +/* macros for field FILTER_INTERVAL_ENABLE */ +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__SHIFT 0 +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MASK 0x00000001U +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RESET_INTERVAL */ +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__SHIFT 1 +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MASK 0x00000002U +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field EXCLUDE_ELM3 */ +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__SHIFT 2 +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MASK 0x00000004U +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field FILTER_INTERVAL */ +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__SHIFT 8 +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WIDTH 8 +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MASK 0x0000ff00U +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field ELM3_ID */ +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__SHIFT 16 +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WIDTH 8 +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MASK 0x00ff0000U +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MAC_PCU_HW_BCN_PROC2__TYPE u_int32_t +#define MAC_PCU_HW_BCN_PROC2__READ 0x00ffff07U +#define MAC_PCU_HW_BCN_PROC2__WRITE 0x00ffff07U + +#endif /* __MAC_PCU_HW_BCN_PROC2_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_HW_BCN_PROC2 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_HW_BCN_PROC2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE3 */ +#ifndef __MAC_PCU_MISC_MODE3_MACRO__ +#define __MAC_PCU_MISC_MODE3_MACRO__ + +/* macros for field BUG_55702_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__SHIFT 0 +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MASK 0x00000001U +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field AES_3STREAM */ +#define MAC_PCU_MISC_MODE3__AES_3STREAM__SHIFT 1 +#define MAC_PCU_MISC_MODE3__AES_3STREAM__WIDTH 1 +#define MAC_PCU_MISC_MODE3__AES_3STREAM__MASK 0x00000002U +#define MAC_PCU_MISC_MODE3__AES_3STREAM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_MISC_MODE3__AES_3STREAM__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE3__AES_3STREAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE3__AES_3STREAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_MISC_MODE3__AES_3STREAM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_MISC_MODE3__AES_3STREAM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field REGULAR_SOUNDING */ +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__SHIFT 2 +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WIDTH 1 +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MASK 0x00000004U +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field BUG_58011_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__SHIFT 3 +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MASK 0x00000008U +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BUG_56991_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__SHIFT 4 +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MASK 0x00000010U +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field WOW_ADDR1_MASK_ENABLE */ +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__SHIFT 5 +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MASK 0x00000020U +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field BUG_61936_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__SHIFT 6 +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MASK 0x00000040U +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field CHECK_LENGTH_FOR_BA */ +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__SHIFT 7 +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WIDTH 1 +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MASK 0x00000080U +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field BA_FRAME_LENGTH */ +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__SHIFT 8 +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WIDTH 8 +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MASK 0x0000ff00U +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field MATCH_TID_FOR_BA */ +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__SHIFT 16 +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WIDTH 1 +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MASK 0x00010000U +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field WAPI_ORDER_MASK */ +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__SHIFT 17 +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WIDTH 1 +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MASK 0x00020000U +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field BB_LDPC_EN */ +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__SHIFT 18 +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WIDTH 1 +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MASK 0x00040000U +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) +#define MAC_PCU_MISC_MODE3__TYPE u_int32_t +#define MAC_PCU_MISC_MODE3__READ 0x0007ffffU +#define MAC_PCU_MISC_MODE3__WRITE 0x0007ffffU + +#endif /* __MAC_PCU_MISC_MODE3_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_MISC_MODE3 */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_MISC_MODE3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXBUF_BA */ +#ifndef __MAC_PCU_TXBUF_BA_MACRO__ +#define __MAC_PCU_TXBUF_BA_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_TXBUF_BA__DATA__SHIFT 0 +#define MAC_PCU_TXBUF_BA__DATA__WIDTH 32 +#define MAC_PCU_TXBUF_BA__DATA__MASK 0xffffffffU +#define MAC_PCU_TXBUF_BA__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TXBUF_BA__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TXBUF_BA__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TXBUF_BA__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TXBUF_BA__TYPE u_int32_t +#define MAC_PCU_TXBUF_BA__READ 0xffffffffU +#define MAC_PCU_TXBUF_BA__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TXBUF_BA_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_TXBUF_BA */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_TXBUF_BA__NUM 64 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_KEY_CACHE */ +#ifndef __MAC_PCU_KEY_CACHE_MACRO__ +#define __MAC_PCU_KEY_CACHE_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_KEY_CACHE__DATA__SHIFT 0 +#define MAC_PCU_KEY_CACHE__DATA__WIDTH 32 +#define MAC_PCU_KEY_CACHE__DATA__MASK 0xffffffffU +#define MAC_PCU_KEY_CACHE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_KEY_CACHE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_KEY_CACHE__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_KEY_CACHE__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_KEY_CACHE__TYPE u_int32_t +#define MAC_PCU_KEY_CACHE__READ 0xffffffffU +#define MAC_PCU_KEY_CACHE__WRITE 0xffffffffU + +#endif /* __MAC_PCU_KEY_CACHE_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_KEY_CACHE */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_KEY_CACHE__NUM 1024 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BUF */ +#ifndef __MAC_PCU_BUF_MACRO__ +#define __MAC_PCU_BUF_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_BUF__DATA__SHIFT 0 +#define MAC_PCU_BUF__DATA__WIDTH 32 +#define MAC_PCU_BUF__DATA__MASK 0xffffffffU +#define MAC_PCU_BUF__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_BUF__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_BUF__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BUF__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define MAC_PCU_BUF__TYPE u_int32_t +#define MAC_PCU_BUF__READ 0xffffffffU +#define MAC_PCU_BUF__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BUF_MACRO__ */ + + +/* macros for mac_pcu_reg_block.MAC_PCU_BUF */ +#define INST_MAC_PCU_REG_BLOCK__MAC_PCU_BUF__NUM 2048 + +/* macros for BlueprintGlobalNameSpace::timing_controls_1 */ +#ifndef __TIMING_CONTROLS_1_MACRO__ +#define __TIMING_CONTROLS_1_MACRO__ + +/* macros for field ste_thr */ +#define TIMING_CONTROLS_1__STE_THR__SHIFT 0 +#define TIMING_CONTROLS_1__STE_THR__WIDTH 7 +#define TIMING_CONTROLS_1__STE_THR__MASK 0x0000007fU +#define TIMING_CONTROLS_1__STE_THR__READ(src) (u_int32_t)(src) & 0x0000007fU +#define TIMING_CONTROLS_1__STE_THR__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) +#define TIMING_CONTROLS_1__STE_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define TIMING_CONTROLS_1__STE_THR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field ste_to_long1 */ +#define TIMING_CONTROLS_1__STE_TO_LONG1__SHIFT 7 +#define TIMING_CONTROLS_1__STE_TO_LONG1__WIDTH 6 +#define TIMING_CONTROLS_1__STE_TO_LONG1__MASK 0x00001f80U +#define TIMING_CONTROLS_1__STE_TO_LONG1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f80U) >> 7) +#define TIMING_CONTROLS_1__STE_TO_LONG1__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00001f80U) +#define TIMING_CONTROLS_1__STE_TO_LONG1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00001f80U) +#define TIMING_CONTROLS_1__STE_TO_LONG1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00001f80U))) + +/* macros for field timing_backoff */ +#define TIMING_CONTROLS_1__TIMING_BACKOFF__SHIFT 13 +#define TIMING_CONTROLS_1__TIMING_BACKOFF__WIDTH 4 +#define TIMING_CONTROLS_1__TIMING_BACKOFF__MASK 0x0001e000U +#define TIMING_CONTROLS_1__TIMING_BACKOFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001e000U) >> 13) +#define TIMING_CONTROLS_1__TIMING_BACKOFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0001e000U) +#define TIMING_CONTROLS_1__TIMING_BACKOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0001e000U) +#define TIMING_CONTROLS_1__TIMING_BACKOFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0001e000U))) + +/* macros for field enable_ht_fine_ppm */ +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__SHIFT 17 +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WIDTH 1 +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MASK 0x00020000U +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field ht_fine_ppm_stream */ +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__SHIFT 18 +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WIDTH 2 +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MASK 0x000c0000U +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__READ(src) \ + (((u_int32_t)(src)\ + & 0x000c0000U) >> 18) +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field ht_fine_ppm_qam */ +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__SHIFT 20 +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WIDTH 2 +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MASK 0x00300000U +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00300000U) >> 20) +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00300000U) +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((u_int32_t)(src) <<\ + 20) & 0x00300000U) +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00300000U))) + +/* macros for field enable_long_chanfil */ +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__SHIFT 22 +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WIDTH 1 +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MASK 0x00400000U +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field enable_rx_stbc */ +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__SHIFT 23 +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__WIDTH 1 +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__MASK 0x00800000U +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field enable_channel_filter */ +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__SHIFT 24 +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WIDTH 1 +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MASK 0x01000000U +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field false_alarm */ +#define TIMING_CONTROLS_1__FALSE_ALARM__SHIFT 25 +#define TIMING_CONTROLS_1__FALSE_ALARM__WIDTH 2 +#define TIMING_CONTROLS_1__FALSE_ALARM__MASK 0x06000000U +#define TIMING_CONTROLS_1__FALSE_ALARM__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define TIMING_CONTROLS_1__FALSE_ALARM__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define TIMING_CONTROLS_1__FALSE_ALARM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define TIMING_CONTROLS_1__FALSE_ALARM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field enable_long_rescale */ +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__SHIFT 27 +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WIDTH 1 +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MASK 0x08000000U +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field timing_leak_enable */ +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__SHIFT 28 +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WIDTH 1 +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MASK 0x10000000U +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field coarse_ppm_select */ +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__SHIFT 29 +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WIDTH 2 +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MASK 0x60000000U +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x60000000U) >> 29) +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x60000000U) +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x60000000U) | (((u_int32_t)(src) <<\ + 29) & 0x60000000U) +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x60000000U))) + +/* macros for field fft_scaling */ +#define TIMING_CONTROLS_1__FFT_SCALING__SHIFT 31 +#define TIMING_CONTROLS_1__FFT_SCALING__WIDTH 1 +#define TIMING_CONTROLS_1__FFT_SCALING__MASK 0x80000000U +#define TIMING_CONTROLS_1__FFT_SCALING__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TIMING_CONTROLS_1__FFT_SCALING__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TIMING_CONTROLS_1__FFT_SCALING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TIMING_CONTROLS_1__FFT_SCALING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TIMING_CONTROLS_1__FFT_SCALING__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TIMING_CONTROLS_1__FFT_SCALING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TIMING_CONTROLS_1__TYPE u_int32_t +#define TIMING_CONTROLS_1__READ 0xffffffffU +#define TIMING_CONTROLS_1__WRITE 0xffffffffU + +#endif /* __TIMING_CONTROLS_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_timing_controls_1 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_controls_2 */ +#ifndef __TIMING_CONTROLS_2_MACRO__ +#define __TIMING_CONTROLS_2_MACRO__ + +/* macros for field forced_delta_phi_symbol */ +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__SHIFT 0 +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WIDTH 12 +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MASK 0x00000fffU +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field force_delta_phi_symbol */ +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__SHIFT 12 +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WIDTH 1 +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MASK 0x00001000U +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field enable_magnitude_track */ +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__SHIFT 13 +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MASK 0x00002000U +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field enable_slope_filter */ +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__SHIFT 14 +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MASK 0x00004000U +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field enable_offset_filter */ +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__SHIFT 15 +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MASK 0x00008000U +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field dc_off_deltaf_thres */ +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__SHIFT 16 +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WIDTH 7 +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MASK 0x007f0000U +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x007f0000U) +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x007f0000U) +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x007f0000U))) + +/* macros for field dc_off_tim_const */ +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__SHIFT 24 +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WIDTH 3 +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MASK 0x07000000U +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__READ(src) \ + (((u_int32_t)(src)\ + & 0x07000000U) >> 24) +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x07000000U) +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x07000000U))) + +/* macros for field enable_dc_offset */ +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__SHIFT 27 +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MASK 0x08000000U +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field enable_dc_offset_track */ +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__SHIFT 28 +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MASK 0x10000000U +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field enable_weighting */ +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__SHIFT 29 +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MASK 0x20000000U +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field traceback128 */ +#define TIMING_CONTROLS_2__TRACEBACK128__SHIFT 30 +#define TIMING_CONTROLS_2__TRACEBACK128__WIDTH 1 +#define TIMING_CONTROLS_2__TRACEBACK128__MASK 0x40000000U +#define TIMING_CONTROLS_2__TRACEBACK128__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define TIMING_CONTROLS_2__TRACEBACK128__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define TIMING_CONTROLS_2__TRACEBACK128__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define TIMING_CONTROLS_2__TRACEBACK128__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define TIMING_CONTROLS_2__TRACEBACK128__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define TIMING_CONTROLS_2__TRACEBACK128__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field enable_ht_fine_timing */ +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__SHIFT 31 +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MASK 0x80000000U +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TIMING_CONTROLS_2__TYPE u_int32_t +#define TIMING_CONTROLS_2__READ 0xff7fffffU +#define TIMING_CONTROLS_2__WRITE 0xff7fffffU + +#endif /* __TIMING_CONTROLS_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_timing_controls_2 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_controls_3 */ +#ifndef __TIMING_CONTROLS_3_MACRO__ +#define __TIMING_CONTROLS_3_MACRO__ + +/* macros for field ppm_rescue_interval */ +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__SHIFT 0 +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WIDTH 8 +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MASK 0x000000ffU +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field enable_ppm_rescue */ +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__SHIFT 8 +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WIDTH 1 +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MASK 0x00000100U +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field enable_fine_ppm */ +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__SHIFT 9 +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WIDTH 1 +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MASK 0x00000200U +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field enable_fine_interp */ +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__SHIFT 10 +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WIDTH 1 +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MASK 0x00000400U +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field continuous_ppm_rescue */ +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__SHIFT 11 +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WIDTH 1 +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MASK 0x00000800U +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field enable_df_chanest */ +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__SHIFT 12 +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WIDTH 1 +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MASK 0x00001000U +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field delta_slope_coef_exp */ +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__SHIFT 13 +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WIDTH 4 +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MASK 0x0001e000U +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001e000U) >> 13) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0001e000U) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0001e000U) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0001e000U))) + +/* macros for field delta_slope_coef_man */ +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__SHIFT 17 +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WIDTH 15 +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MASK 0xfffe0000U +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__READ(src) \ + (((u_int32_t)(src)\ + & 0xfffe0000U) >> 17) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0xfffe0000U) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffe0000U) | (((u_int32_t)(src) <<\ + 17) & 0xfffe0000U) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0xfffe0000U))) +#define TIMING_CONTROLS_3__TYPE u_int32_t +#define TIMING_CONTROLS_3__READ 0xffffffffU +#define TIMING_CONTROLS_3__WRITE 0xffffffffU + +#endif /* __TIMING_CONTROLS_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_timing_controls_3 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_control_4 */ +#ifndef __TIMING_CONTROL_4_MACRO__ +#define __TIMING_CONTROL_4_MACRO__ + +/* macros for field cal_lg_count_max */ +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__SHIFT 12 +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WIDTH 4 +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MASK 0x0000f000U +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field do_gain_dc_iq_cal */ +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__SHIFT 16 +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WIDTH 1 +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MASK 0x00010000U +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field use_pilot_track_df */ +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__SHIFT 17 +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WIDTH 4 +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MASK 0x001e0000U +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__READ(src) \ + (((u_int32_t)(src)\ + & 0x001e0000U) >> 17) +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x001e0000U) +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x001e0000U) +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x001e0000U))) + +/* macros for field early_trigger_thr */ +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__SHIFT 21 +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WIDTH 7 +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MASK 0x0fe00000U +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fe00000U) >> 21) +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x0fe00000U) +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x0fe00000U) +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x0fe00000U))) + +/* macros for field enable_pilot_mask */ +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__SHIFT 28 +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WIDTH 1 +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MASK 0x10000000U +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field enable_chan_mask */ +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__SHIFT 29 +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WIDTH 1 +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MASK 0x20000000U +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field enable_spur_filter */ +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__SHIFT 30 +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WIDTH 1 +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MASK 0x40000000U +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field enable_spur_rssi */ +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__SHIFT 31 +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WIDTH 1 +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MASK 0x80000000U +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TIMING_CONTROL_4__TYPE u_int32_t +#define TIMING_CONTROL_4__READ 0xfffff000U +#define TIMING_CONTROL_4__WRITE 0xfffff000U + +#endif /* __TIMING_CONTROL_4_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_timing_control_4 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_TIMING_CONTROL_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_control_5 */ +#ifndef __TIMING_CONTROL_5_MACRO__ +#define __TIMING_CONTROL_5_MACRO__ + +/* macros for field enable_cycpwr_thr1 */ +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__SHIFT 0 +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WIDTH 1 +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MASK 0x00000001U +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cycpwr_thr1 */ +#define TIMING_CONTROL_5__CYCPWR_THR1__SHIFT 1 +#define TIMING_CONTROL_5__CYCPWR_THR1__WIDTH 7 +#define TIMING_CONTROL_5__CYCPWR_THR1__MASK 0x000000feU +#define TIMING_CONTROL_5__CYCPWR_THR1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000feU) >> 1) +#define TIMING_CONTROL_5__CYCPWR_THR1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000000feU) +#define TIMING_CONTROL_5__CYCPWR_THR1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((u_int32_t)(src) <<\ + 1) & 0x000000feU) +#define TIMING_CONTROL_5__CYCPWR_THR1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000000feU))) + +/* macros for field enable_rssi_thr1a */ +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__SHIFT 15 +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WIDTH 1 +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MASK 0x00008000U +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field rssi_thr1a */ +#define TIMING_CONTROL_5__RSSI_THR1A__SHIFT 16 +#define TIMING_CONTROL_5__RSSI_THR1A__WIDTH 7 +#define TIMING_CONTROL_5__RSSI_THR1A__MASK 0x007f0000U +#define TIMING_CONTROL_5__RSSI_THR1A__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) +#define TIMING_CONTROL_5__RSSI_THR1A__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x007f0000U) +#define TIMING_CONTROL_5__RSSI_THR1A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x007f0000U) +#define TIMING_CONTROL_5__RSSI_THR1A__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x007f0000U))) + +/* macros for field long_sc_thresh_hi_rssi */ +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__SHIFT 23 +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__WIDTH 7 +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__MASK 0x3f800000U +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f800000U) >> 23) +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x3f800000U) +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x3f800000U) +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x3f800000U))) + +/* macros for field forced_agc_str_pri */ +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__SHIFT 30 +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__WIDTH 1 +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__MASK 0x40000000U +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field forced_agc_str_pri_en */ +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__SHIFT 31 +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__WIDTH 1 +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__MASK 0x80000000U +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TIMING_CONTROL_5__TYPE u_int32_t +#define TIMING_CONTROL_5__READ 0xffff80ffU +#define TIMING_CONTROL_5__WRITE 0xffff80ffU + +#endif /* __TIMING_CONTROL_5_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_timing_control_5 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_TIMING_CONTROL_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_control_6 */ +#ifndef __TIMING_CONTROL_6_MACRO__ +#define __TIMING_CONTROL_6_MACRO__ + +/* macros for field hi_rssi_thresh */ +#define TIMING_CONTROL_6__HI_RSSI_THRESH__SHIFT 0 +#define TIMING_CONTROL_6__HI_RSSI_THRESH__WIDTH 8 +#define TIMING_CONTROL_6__HI_RSSI_THRESH__MASK 0x000000ffU +#define TIMING_CONTROL_6__HI_RSSI_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define TIMING_CONTROL_6__HI_RSSI_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TIMING_CONTROL_6__HI_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TIMING_CONTROL_6__HI_RSSI_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field early_trigger_thr_hi_rssi */ +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__SHIFT 8 +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__WIDTH 7 +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__MASK 0x00007f00U +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007f00U) >> 8) +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00007f00U) +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00007f00U) +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00007f00U))) + +/* macros for field ofdm_xcorr_thresh */ +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__SHIFT 15 +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__WIDTH 6 +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__MASK 0x001f8000U +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f8000U) >> 15) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x001f8000U) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x001f8000U) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x001f8000U))) + +/* macros for field ofdm_xcorr_thresh_hi_rssi */ +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__SHIFT 21 +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__WIDTH 7 +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__MASK 0x0fe00000U +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fe00000U) >> 21) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x0fe00000U) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x0fe00000U) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x0fe00000U))) + +/* macros for field long_medium_ratio_thr */ +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__SHIFT 28 +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__WIDTH 4 +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__MASK 0xf0000000U +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0xf0000000U) >> 28) +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0xf0000000U) +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((u_int32_t)(src) <<\ + 28) & 0xf0000000U) +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0xf0000000U))) +#define TIMING_CONTROL_6__TYPE u_int32_t +#define TIMING_CONTROL_6__READ 0xffffffffU +#define TIMING_CONTROL_6__WRITE 0xffffffffU + +#endif /* __TIMING_CONTROL_6_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_timing_control_6 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_TIMING_CONTROL_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_control_11 */ +#ifndef __TIMING_CONTROL_11_MACRO__ +#define __TIMING_CONTROL_11_MACRO__ + +/* macros for field spur_delta_phase */ +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__SHIFT 0 +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__WIDTH 20 +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__MASK 0x000fffffU +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__READ(src) \ + (u_int32_t)(src)\ + & 0x000fffffU +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000fffffU) +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffffU) | ((u_int32_t)(src) &\ + 0x000fffffU) +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000fffffU))) + +/* macros for field spur_freq_sd */ +#define TIMING_CONTROL_11__SPUR_FREQ_SD__SHIFT 20 +#define TIMING_CONTROL_11__SPUR_FREQ_SD__WIDTH 10 +#define TIMING_CONTROL_11__SPUR_FREQ_SD__MASK 0x3ff00000U +#define TIMING_CONTROL_11__SPUR_FREQ_SD__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ff00000U) >> 20) +#define TIMING_CONTROL_11__SPUR_FREQ_SD__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x3ff00000U) +#define TIMING_CONTROL_11__SPUR_FREQ_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x3ff00000U) +#define TIMING_CONTROL_11__SPUR_FREQ_SD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x3ff00000U))) + +/* macros for field use_spur_filter_in_agc */ +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__SHIFT 30 +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__WIDTH 1 +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__MASK 0x40000000U +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field use_spur_filter_in_selfcor */ +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__SHIFT 31 +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__WIDTH 1 +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__MASK 0x80000000U +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TIMING_CONTROL_11__TYPE u_int32_t +#define TIMING_CONTROL_11__READ 0xffffffffU +#define TIMING_CONTROL_11__WRITE 0xffffffffU + +#endif /* __TIMING_CONTROL_11_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_timing_control_11 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_TIMING_CONTROL_11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_mask_controls */ +#ifndef __SPUR_MASK_CONTROLS_MACRO__ +#define __SPUR_MASK_CONTROLS_MACRO__ + +/* macros for field spur_rssi_thresh */ +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__SHIFT 0 +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__WIDTH 8 +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__MASK 0x000000ffU +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field en_vit_spur_rssi */ +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__SHIFT 8 +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__WIDTH 1 +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__MASK 0x00000100U +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field enable_mask_ppm */ +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__SHIFT 17 +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__WIDTH 1 +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__MASK 0x00020000U +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field mask_rate_cntl */ +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__SHIFT 18 +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__WIDTH 8 +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__MASK 0x03fc0000U +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__READ(src) \ + (((u_int32_t)(src)\ + & 0x03fc0000U) >> 18) +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x03fc0000U) +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x03fc0000U) +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x03fc0000U))) + +/* macros for field enable_nf_rssi_spur_mit */ +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__SHIFT 26 +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__WIDTH 1 +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__MASK 0x04000000U +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) +#define SPUR_MASK_CONTROLS__TYPE u_int32_t +#define SPUR_MASK_CONTROLS__READ 0x07fe01ffU +#define SPUR_MASK_CONTROLS__WRITE 0x07fe01ffU + +#endif /* __SPUR_MASK_CONTROLS_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_spur_mask_controls */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_SPUR_MASK_CONTROLS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::find_signal_low */ +#ifndef __FIND_SIGNAL_LOW_MACRO__ +#define __FIND_SIGNAL_LOW_MACRO__ + +/* macros for field relstep_low */ +#define FIND_SIGNAL_LOW__RELSTEP_LOW__SHIFT 0 +#define FIND_SIGNAL_LOW__RELSTEP_LOW__WIDTH 6 +#define FIND_SIGNAL_LOW__RELSTEP_LOW__MASK 0x0000003fU +#define FIND_SIGNAL_LOW__RELSTEP_LOW__READ(src) (u_int32_t)(src) & 0x0000003fU +#define FIND_SIGNAL_LOW__RELSTEP_LOW__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define FIND_SIGNAL_LOW__RELSTEP_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define FIND_SIGNAL_LOW__RELSTEP_LOW__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field firstep_low */ +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__SHIFT 6 +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__WIDTH 6 +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__MASK 0x00000fc0U +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field firpwr_low */ +#define FIND_SIGNAL_LOW__FIRPWR_LOW__SHIFT 12 +#define FIND_SIGNAL_LOW__FIRPWR_LOW__WIDTH 8 +#define FIND_SIGNAL_LOW__FIRPWR_LOW__MASK 0x000ff000U +#define FIND_SIGNAL_LOW__FIRPWR_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ff000U) >> 12) +#define FIND_SIGNAL_LOW__FIRPWR_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x000ff000U) +#define FIND_SIGNAL_LOW__FIRPWR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x000ff000U) +#define FIND_SIGNAL_LOW__FIRPWR_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x000ff000U))) + +/* macros for field ycok_max_low */ +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__SHIFT 20 +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__WIDTH 4 +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__MASK 0x00f00000U +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) + +/* macros for field long_sc_thresh */ +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__SHIFT 24 +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__WIDTH 7 +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__MASK 0x7f000000U +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f000000U) >> 24) +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) +#define FIND_SIGNAL_LOW__TYPE u_int32_t +#define FIND_SIGNAL_LOW__READ 0x7fffffffU +#define FIND_SIGNAL_LOW__WRITE 0x7fffffffU + +#endif /* __FIND_SIGNAL_LOW_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_find_signal_low */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_FIND_SIGNAL_LOW__NUM 1 + +/* macros for BlueprintGlobalNameSpace::sfcorr */ +#ifndef __SFCORR_MACRO__ +#define __SFCORR_MACRO__ + +/* macros for field m2count_thr */ +#define SFCORR__M2COUNT_THR__SHIFT 0 +#define SFCORR__M2COUNT_THR__WIDTH 5 +#define SFCORR__M2COUNT_THR__MASK 0x0000001fU +#define SFCORR__M2COUNT_THR__READ(src) (u_int32_t)(src) & 0x0000001fU +#define SFCORR__M2COUNT_THR__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define SFCORR__M2COUNT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define SFCORR__M2COUNT_THR__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field adcsat_thresh */ +#define SFCORR__ADCSAT_THRESH__SHIFT 5 +#define SFCORR__ADCSAT_THRESH__WIDTH 6 +#define SFCORR__ADCSAT_THRESH__MASK 0x000007e0U +#define SFCORR__ADCSAT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x000007e0U) >> 5) +#define SFCORR__ADCSAT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000007e0U) +#define SFCORR__ADCSAT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000007e0U) +#define SFCORR__ADCSAT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000007e0U))) + +/* macros for field adcsat_icount */ +#define SFCORR__ADCSAT_ICOUNT__SHIFT 11 +#define SFCORR__ADCSAT_ICOUNT__WIDTH 6 +#define SFCORR__ADCSAT_ICOUNT__MASK 0x0001f800U +#define SFCORR__ADCSAT_ICOUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f800U) >> 11) +#define SFCORR__ADCSAT_ICOUNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x0001f800U) +#define SFCORR__ADCSAT_ICOUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0001f800U) +#define SFCORR__ADCSAT_ICOUNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0001f800U))) + +/* macros for field m1_thres */ +#define SFCORR__M1_THRES__SHIFT 17 +#define SFCORR__M1_THRES__WIDTH 7 +#define SFCORR__M1_THRES__MASK 0x00fe0000U +#define SFCORR__M1_THRES__READ(src) (((u_int32_t)(src) & 0x00fe0000U) >> 17) +#define SFCORR__M1_THRES__WRITE(src) (((u_int32_t)(src) << 17) & 0x00fe0000U) +#define SFCORR__M1_THRES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x00fe0000U) +#define SFCORR__M1_THRES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00fe0000U))) + +/* macros for field m2_thres */ +#define SFCORR__M2_THRES__SHIFT 24 +#define SFCORR__M2_THRES__WIDTH 7 +#define SFCORR__M2_THRES__MASK 0x7f000000U +#define SFCORR__M2_THRES__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24) +#define SFCORR__M2_THRES__WRITE(src) (((u_int32_t)(src) << 24) & 0x7f000000U) +#define SFCORR__M2_THRES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define SFCORR__M2_THRES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) +#define SFCORR__TYPE u_int32_t +#define SFCORR__READ 0x7fffffffU +#define SFCORR__WRITE 0x7fffffffU + +#endif /* __SFCORR_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_sfcorr */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_SFCORR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::self_corr_low */ +#ifndef __SELF_CORR_LOW_MACRO__ +#define __SELF_CORR_LOW_MACRO__ + +/* macros for field use_self_corr_low */ +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__SHIFT 0 +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__WIDTH 1 +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__MASK 0x00000001U +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field m1count_max_low */ +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__SHIFT 1 +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__WIDTH 7 +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__MASK 0x000000feU +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000feU) >> 1) +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000000feU) +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((u_int32_t)(src) <<\ + 1) & 0x000000feU) +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000000feU))) + +/* macros for field m2count_thr_low */ +#define SELF_CORR_LOW__M2COUNT_THR_LOW__SHIFT 8 +#define SELF_CORR_LOW__M2COUNT_THR_LOW__WIDTH 6 +#define SELF_CORR_LOW__M2COUNT_THR_LOW__MASK 0x00003f00U +#define SELF_CORR_LOW__M2COUNT_THR_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define SELF_CORR_LOW__M2COUNT_THR_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define SELF_CORR_LOW__M2COUNT_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define SELF_CORR_LOW__M2COUNT_THR_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field m1_thresh_low */ +#define SELF_CORR_LOW__M1_THRESH_LOW__SHIFT 14 +#define SELF_CORR_LOW__M1_THRESH_LOW__WIDTH 7 +#define SELF_CORR_LOW__M1_THRESH_LOW__MASK 0x001fc000U +#define SELF_CORR_LOW__M1_THRESH_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x001fc000U) >> 14) +#define SELF_CORR_LOW__M1_THRESH_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x001fc000U) +#define SELF_CORR_LOW__M1_THRESH_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x001fc000U) +#define SELF_CORR_LOW__M1_THRESH_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x001fc000U))) + +/* macros for field m2_thresh_low */ +#define SELF_CORR_LOW__M2_THRESH_LOW__SHIFT 21 +#define SELF_CORR_LOW__M2_THRESH_LOW__WIDTH 7 +#define SELF_CORR_LOW__M2_THRESH_LOW__MASK 0x0fe00000U +#define SELF_CORR_LOW__M2_THRESH_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fe00000U) >> 21) +#define SELF_CORR_LOW__M2_THRESH_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x0fe00000U) +#define SELF_CORR_LOW__M2_THRESH_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x0fe00000U) +#define SELF_CORR_LOW__M2_THRESH_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x0fe00000U))) +#define SELF_CORR_LOW__TYPE u_int32_t +#define SELF_CORR_LOW__READ 0x0fffffffU +#define SELF_CORR_LOW__WRITE 0x0fffffffU + +#endif /* __SELF_CORR_LOW_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_self_corr_low */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_SELF_CORR_LOW__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_scorr_thr */ +#ifndef __EXT_CHAN_SCORR_THR_MACRO__ +#define __EXT_CHAN_SCORR_THR_MACRO__ + +/* macros for field m1_thres_ext */ +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__SHIFT 0 +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__WIDTH 7 +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__MASK 0x0000007fU +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field m2_thres_ext */ +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__SHIFT 7 +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__WIDTH 7 +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__MASK 0x00003f80U +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f80U) >> 7) +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00003f80U) +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00003f80U) +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00003f80U))) + +/* macros for field m1_thres_low_ext */ +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__SHIFT 14 +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__WIDTH 7 +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__MASK 0x001fc000U +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x001fc000U) >> 14) +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x001fc000U) +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x001fc000U) +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x001fc000U))) + +/* macros for field m2_thres_low_ext */ +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__SHIFT 21 +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__WIDTH 7 +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__MASK 0x0fe00000U +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fe00000U) >> 21) +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x0fe00000U) +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x0fe00000U) +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x0fe00000U))) + +/* macros for field spur_subchannel_sd */ +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__SHIFT 28 +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__WIDTH 1 +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__MASK 0x10000000U +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) +#define EXT_CHAN_SCORR_THR__TYPE u_int32_t +#define EXT_CHAN_SCORR_THR__READ 0x1fffffffU +#define EXT_CHAN_SCORR_THR__WRITE 0x1fffffffU + +#endif /* __EXT_CHAN_SCORR_THR_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_ext_chan_scorr_thr */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_EXT_CHAN_SCORR_THR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b0 */ +#ifndef __EXT_CHAN_PWR_THR_2_B0_MACRO__ +#define __EXT_CHAN_PWR_THR_2_B0_MACRO__ + +/* macros for field cf_maxCCApwr_ext_0 */ +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__SHIFT 0 +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__MASK 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field cycpwr_thr1_ext */ +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__SHIFT 9 +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__WIDTH 7 +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__MASK 0x0000fe00U +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fe00U) >> 9) +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x0000fe00U) +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fe00U) | (((u_int32_t)(src) <<\ + 9) & 0x0000fe00U) +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x0000fe00U))) + +/* macros for field minCCApwr_ext_0 */ +#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__SHIFT 16 +#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__MASK 0x01ff0000U +#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01ff0000U) >> 16) +#define EXT_CHAN_PWR_THR_2_B0__TYPE u_int32_t +#define EXT_CHAN_PWR_THR_2_B0__READ 0x01ffffffU +#define EXT_CHAN_PWR_THR_2_B0__WRITE 0x01ffffffU + +#endif /* __EXT_CHAN_PWR_THR_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_ext_chan_pwr_thr_2_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::radar_detection */ +#ifndef __RADAR_DETECTION_MACRO__ +#define __RADAR_DETECTION_MACRO__ + +/* macros for field pulse_detect_enable */ +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__SHIFT 0 +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__WIDTH 1 +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__MASK 0x00000001U +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field pulse_in_band_thresh */ +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__SHIFT 1 +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__WIDTH 5 +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__MASK 0x0000003eU +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000003eU) +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000003eU) +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000003eU))) + +/* macros for field pulse_rssi_thresh */ +#define RADAR_DETECTION__PULSE_RSSI_THRESH__SHIFT 6 +#define RADAR_DETECTION__PULSE_RSSI_THRESH__WIDTH 6 +#define RADAR_DETECTION__PULSE_RSSI_THRESH__MASK 0x00000fc0U +#define RADAR_DETECTION__PULSE_RSSI_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define RADAR_DETECTION__PULSE_RSSI_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define RADAR_DETECTION__PULSE_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define RADAR_DETECTION__PULSE_RSSI_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field pulse_height_thresh */ +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__SHIFT 12 +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__WIDTH 6 +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__MASK 0x0003f000U +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field radar_rssi_thresh */ +#define RADAR_DETECTION__RADAR_RSSI_THRESH__SHIFT 18 +#define RADAR_DETECTION__RADAR_RSSI_THRESH__WIDTH 6 +#define RADAR_DETECTION__RADAR_RSSI_THRESH__MASK 0x00fc0000U +#define RADAR_DETECTION__RADAR_RSSI_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define RADAR_DETECTION__RADAR_RSSI_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define RADAR_DETECTION__RADAR_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define RADAR_DETECTION__RADAR_RSSI_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field radar_firpwr_thresh */ +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__SHIFT 24 +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__WIDTH 7 +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__MASK 0x7f000000U +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f000000U) >> 24) +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) + +/* macros for field enable_radar_fft */ +#define RADAR_DETECTION__ENABLE_RADAR_FFT__SHIFT 31 +#define RADAR_DETECTION__ENABLE_RADAR_FFT__WIDTH 1 +#define RADAR_DETECTION__ENABLE_RADAR_FFT__MASK 0x80000000U +#define RADAR_DETECTION__ENABLE_RADAR_FFT__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADAR_DETECTION__ENABLE_RADAR_FFT__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADAR_DETECTION__ENABLE_RADAR_FFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADAR_DETECTION__ENABLE_RADAR_FFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADAR_DETECTION__ENABLE_RADAR_FFT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADAR_DETECTION__ENABLE_RADAR_FFT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADAR_DETECTION__TYPE u_int32_t +#define RADAR_DETECTION__READ 0xffffffffU +#define RADAR_DETECTION__WRITE 0xffffffffU + +#endif /* __RADAR_DETECTION_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_radar_detection */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_RADAR_DETECTION__NUM 1 + +/* macros for BlueprintGlobalNameSpace::radar_detection_2 */ +#ifndef __RADAR_DETECTION_2_MACRO__ +#define __RADAR_DETECTION_2_MACRO__ + +/* macros for field radar_length_max */ +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__SHIFT 0 +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__WIDTH 8 +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__MASK 0x000000ffU +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field pulse_relstep_thresh */ +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__SHIFT 8 +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__WIDTH 5 +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__MASK 0x00001f00U +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) + +/* macros for field enable_pulse_relstep_check */ +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__SHIFT 13 +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__WIDTH 1 +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__MASK 0x00002000U +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field enable_max_radar_rssi */ +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__SHIFT 14 +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__WIDTH 1 +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__MASK 0x00004000U +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field enable_block_radar_check */ +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__SHIFT 15 +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__WIDTH 1 +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__MASK 0x00008000U +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field radar_relpwr_thresh */ +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__SHIFT 16 +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__WIDTH 6 +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__MASK 0x003f0000U +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field radar_use_firpwr_128 */ +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__SHIFT 22 +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__WIDTH 1 +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__MASK 0x00400000U +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field enable_radar_relpwr_check */ +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__SHIFT 23 +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__WIDTH 1 +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__MASK 0x00800000U +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field cf_radar_bin_thresh_sel */ +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__SHIFT 24 +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__WIDTH 3 +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__MASK 0x07000000U +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x07000000U) >> 24) +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x07000000U) +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x07000000U))) + +/* macros for field enable_pulse_gc_count_check */ +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__SHIFT 27 +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__WIDTH 1 +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__MASK 0x08000000U +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) +#define RADAR_DETECTION_2__TYPE u_int32_t +#define RADAR_DETECTION_2__READ 0x0fffffffU +#define RADAR_DETECTION_2__WRITE 0x0fffffffU + +#endif /* __RADAR_DETECTION_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_radar_detection_2 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_RADAR_DETECTION_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::extension_radar */ +#ifndef __EXTENSION_RADAR_MACRO__ +#define __EXTENSION_RADAR_MACRO__ + +/* macros for field blocker40_max_radar */ +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__SHIFT 8 +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__WIDTH 6 +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__MASK 0x00003f00U +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field enable_ext_radar */ +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__SHIFT 14 +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__WIDTH 1 +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__MASK 0x00004000U +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field radar_dc_pwr_thresh */ +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__SHIFT 15 +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__WIDTH 8 +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__MASK 0x007f8000U +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f8000U) >> 15) +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x007f8000U) +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x007f8000U) +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x007f8000U))) + +/* macros for field radar_lb_dc_cap */ +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__SHIFT 23 +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__WIDTH 8 +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__MASK 0x7f800000U +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f800000U) >> 23) +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x7f800000U) +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x7f800000U) +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x7f800000U))) + +/* macros for field disable_adcsat_hold */ +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__SHIFT 31 +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__WIDTH 1 +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__MASK 0x80000000U +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define EXTENSION_RADAR__TYPE u_int32_t +#define EXTENSION_RADAR__READ 0xffffff00U +#define EXTENSION_RADAR__WRITE 0xffffff00U + +#endif /* __EXTENSION_RADAR_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_extension_radar */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_EXTENSION_RADAR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::multichain_control */ +#ifndef __MULTICHAIN_CONTROL_MACRO__ +#define __MULTICHAIN_CONTROL_MACRO__ + +/* macros for field force_analog_gain_diff */ +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__SHIFT 0 +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__WIDTH 1 +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__MASK 0x00000001U +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field forced_gain_diff_01 */ +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__SHIFT 1 +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__WIDTH 7 +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__MASK 0x000000feU +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000feU) >> 1) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000000feU) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((u_int32_t)(src) <<\ + 1) & 0x000000feU) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000000feU))) + +/* macros for field sync_synthon */ +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__SHIFT 8 +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__WIDTH 1 +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__MASK 0x00000100U +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field use_posedge_refclk */ +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__SHIFT 9 +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__WIDTH 1 +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__MASK 0x00000200U +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field cf_short_sat */ +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__SHIFT 10 +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__WIDTH 11 +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__MASK 0x001ffc00U +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__READ(src) \ + (((u_int32_t)(src)\ + & 0x001ffc00U) >> 10) +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x001ffc00U) +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x001ffc00U) +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x001ffc00U))) + +/* macros for field forced_gain_diff_02 */ +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__SHIFT 22 +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__WIDTH 7 +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__MASK 0x1fc00000U +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__READ(src) \ + (((u_int32_t)(src)\ + & 0x1fc00000U) >> 22) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x1fc00000U) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x1fc00000U) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x1fc00000U))) + +/* macros for field force_sigma_zero */ +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__SHIFT 29 +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__WIDTH 1 +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__MASK 0x20000000U +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define MULTICHAIN_CONTROL__TYPE u_int32_t +#define MULTICHAIN_CONTROL__READ 0x3fdfffffU +#define MULTICHAIN_CONTROL__WRITE 0x3fdfffffU + +#endif /* __MULTICHAIN_CONTROL_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_multichain_control */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_MULTICHAIN_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::per_chain_csd */ +#ifndef __PER_CHAIN_CSD_MACRO__ +#define __PER_CHAIN_CSD_MACRO__ + +/* macros for field csd_chn1_2chains */ +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__SHIFT 0 +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__WIDTH 5 +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__MASK 0x0000001fU +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field csd_chn1_3chains */ +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__SHIFT 5 +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__WIDTH 5 +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__MASK 0x000003e0U +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field csd_chn2_3chains */ +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__SHIFT 10 +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__WIDTH 5 +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__MASK 0x00007c00U +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) +#define PER_CHAIN_CSD__TYPE u_int32_t +#define PER_CHAIN_CSD__READ 0x00007fffU +#define PER_CHAIN_CSD__WRITE 0x00007fffU + +#endif /* __PER_CHAIN_CSD_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_per_chain_csd */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PER_CHAIN_CSD__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_crc */ +#ifndef __TX_CRC_MACRO__ +#define __TX_CRC_MACRO__ + +/* macros for field tx_crc */ +#define TX_CRC__TX_CRC__SHIFT 0 +#define TX_CRC__TX_CRC__WIDTH 16 +#define TX_CRC__TX_CRC__MASK 0x0000ffffU +#define TX_CRC__TX_CRC__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define TX_CRC__TYPE u_int32_t +#define TX_CRC__READ 0x0000ffffU + +#endif /* __TX_CRC_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_tx_crc */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_TX_CRC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tstdac_constant */ +#ifndef __TSTDAC_CONSTANT_MACRO__ +#define __TSTDAC_CONSTANT_MACRO__ + +/* macros for field cf_tstdac_constant_i */ +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__SHIFT 0 +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__WIDTH 11 +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__MASK 0x000007ffU +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__READ(src) \ + (u_int32_t)(src)\ + & 0x000007ffU +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000007ffU) +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000007ffU))) + +/* macros for field cf_tstdac_constant_q */ +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__SHIFT 11 +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__WIDTH 11 +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__MASK 0x003ff800U +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x003ff800U) >> 11) +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x003ff800U) +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003ff800U) | (((u_int32_t)(src) <<\ + 11) & 0x003ff800U) +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x003ff800U))) +#define TSTDAC_CONSTANT__TYPE u_int32_t +#define TSTDAC_CONSTANT__READ 0x003fffffU +#define TSTDAC_CONSTANT__WRITE 0x003fffffU + +#endif /* __TSTDAC_CONSTANT_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_tstdac_constant */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_TSTDAC_CONSTANT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_report_b0 */ +#ifndef __SPUR_REPORT_B0_MACRO__ +#define __SPUR_REPORT_B0_MACRO__ + +/* macros for field spur_est_i_0 */ +#define SPUR_REPORT_B0__SPUR_EST_I_0__SHIFT 0 +#define SPUR_REPORT_B0__SPUR_EST_I_0__WIDTH 8 +#define SPUR_REPORT_B0__SPUR_EST_I_0__MASK 0x000000ffU +#define SPUR_REPORT_B0__SPUR_EST_I_0__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field spur_est_q_0 */ +#define SPUR_REPORT_B0__SPUR_EST_Q_0__SHIFT 8 +#define SPUR_REPORT_B0__SPUR_EST_Q_0__WIDTH 8 +#define SPUR_REPORT_B0__SPUR_EST_Q_0__MASK 0x0000ff00U +#define SPUR_REPORT_B0__SPUR_EST_Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field power_with_spur_removed_0 */ +#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__SHIFT 16 +#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__WIDTH 16 +#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__MASK 0xffff0000U +#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define SPUR_REPORT_B0__TYPE u_int32_t +#define SPUR_REPORT_B0__READ 0xffffffffU + +#endif /* __SPUR_REPORT_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_spur_report_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_SPUR_REPORT_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_control_3 */ +#ifndef __TXIQCAL_CONTROL_3_MACRO__ +#define __TXIQCAL_CONTROL_3_MACRO__ + +/* macros for field pwr_high_db */ +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__SHIFT 0 +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__WIDTH 6 +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__MASK 0x0000003fU +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field pwr_low_db */ +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__SHIFT 6 +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__WIDTH 6 +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__MASK 0x00000fc0U +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field iqcal_tone_phs_step */ +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__SHIFT 12 +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__WIDTH 10 +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__MASK 0x003ff000U +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x003ff000U) >> 12) +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x003ff000U) +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x003ff000U) +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x003ff000U))) + +/* macros for field dc_est_len */ +#define TXIQCAL_CONTROL_3__DC_EST_LEN__SHIFT 22 +#define TXIQCAL_CONTROL_3__DC_EST_LEN__WIDTH 2 +#define TXIQCAL_CONTROL_3__DC_EST_LEN__MASK 0x00c00000U +#define TXIQCAL_CONTROL_3__DC_EST_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00c00000U) >> 22) +#define TXIQCAL_CONTROL_3__DC_EST_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00c00000U) +#define TXIQCAL_CONTROL_3__DC_EST_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x00c00000U) +#define TXIQCAL_CONTROL_3__DC_EST_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00c00000U))) + +/* macros for field adc_sat_len */ +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__SHIFT 24 +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__WIDTH 1 +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__MASK 0x01000000U +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field adc_sat_sel */ +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__SHIFT 25 +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__WIDTH 2 +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__MASK 0x06000000U +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field iqcal_meas_len */ +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__SHIFT 27 +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__WIDTH 2 +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__MASK 0x18000000U +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x18000000U) >> 27) +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x18000000U) +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((u_int32_t)(src) <<\ + 27) & 0x18000000U) +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x18000000U))) + +/* macros for field desired_size_db */ +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__SHIFT 29 +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__WIDTH 2 +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__MASK 0x60000000U +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x60000000U) >> 29) +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x60000000U) +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x60000000U) | (((u_int32_t)(src) <<\ + 29) & 0x60000000U) +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x60000000U))) + +/* macros for field tx_iqcorr_en */ +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__SHIFT 31 +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__WIDTH 1 +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__MASK 0x80000000U +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TXIQCAL_CONTROL_3__TYPE u_int32_t +#define TXIQCAL_CONTROL_3__READ 0xffffffffU +#define TXIQCAL_CONTROL_3__WRITE 0xffffffffU + +#endif /* __TXIQCAL_CONTROL_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_txiqcal_control_3 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_TXIQCAL_CONTROL_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b0 */ +#ifndef __IQ_ADC_MEAS_0_B0_MACRO__ +#define __IQ_ADC_MEAS_0_B0_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_0_0 */ +#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__SHIFT 0 +#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__WIDTH 32 +#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__MASK 0xffffffffU +#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_0_B0__TYPE u_int32_t +#define IQ_ADC_MEAS_0_B0__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_0_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_iq_adc_meas_0_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_0_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b0 */ +#ifndef __IQ_ADC_MEAS_1_B0_MACRO__ +#define __IQ_ADC_MEAS_1_B0_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_1_0 */ +#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__SHIFT 0 +#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__WIDTH 32 +#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__MASK 0xffffffffU +#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_1_B0__TYPE u_int32_t +#define IQ_ADC_MEAS_1_B0__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_1_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_iq_adc_meas_1_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_1_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b0 */ +#ifndef __IQ_ADC_MEAS_2_B0_MACRO__ +#define __IQ_ADC_MEAS_2_B0_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_2_0 */ +#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__SHIFT 0 +#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__WIDTH 32 +#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__MASK 0xffffffffU +#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_2_B0__TYPE u_int32_t +#define IQ_ADC_MEAS_2_B0__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_iq_adc_meas_2_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b0 */ +#ifndef __IQ_ADC_MEAS_3_B0_MACRO__ +#define __IQ_ADC_MEAS_3_B0_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_3_0 */ +#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__SHIFT 0 +#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__WIDTH 32 +#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__MASK 0xffffffffU +#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_3_B0__TYPE u_int32_t +#define IQ_ADC_MEAS_3_B0__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_3_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_iq_adc_meas_3_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_3_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b0 */ +#ifndef __TX_PHASE_RAMP_B0_MACRO__ +#define __TX_PHASE_RAMP_B0_MACRO__ + +/* macros for field cf_phase_ramp_enable_0 */ +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__SHIFT 0 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__WIDTH 1 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__MASK 0x00000001U +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_phase_ramp_bias_0 */ +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__SHIFT 1 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__WIDTH 6 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__MASK 0x0000007eU +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000007eU) >> 1) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000007eU))) + +/* macros for field cf_phase_ramp_init_0 */ +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__SHIFT 7 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__WIDTH 10 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__MASK 0x0001ff80U +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001ff80U) >> 7) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ff80U) | (((u_int32_t)(src) <<\ + 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x0001ff80U))) + +/* macros for field cf_phase_ramp_alpha_0 */ +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__SHIFT 17 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__WIDTH 8 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__MASK 0x01fe0000U +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fe0000U) >> 17) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x01fe0000U))) +#define TX_PHASE_RAMP_B0__TYPE u_int32_t +#define TX_PHASE_RAMP_B0__READ 0x01ffffffU +#define TX_PHASE_RAMP_B0__WRITE 0x01ffffffU + +#endif /* __TX_PHASE_RAMP_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_tx_phase_ramp_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_TX_PHASE_RAMP_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b0 */ +#ifndef __ADC_GAIN_DC_CORR_B0_MACRO__ +#define __ADC_GAIN_DC_CORR_B0_MACRO__ + +/* macros for field adc_gain_corr_q_coeff_0 */ +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__SHIFT 0 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__WIDTH 6 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__MASK 0x0000003fU +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field adc_gain_corr_i_coeff_0 */ +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__SHIFT 6 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__WIDTH 6 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__MASK 0x00000fc0U +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field adc_dc_corr_q_coeff_0 */ +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__SHIFT 12 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__WIDTH 9 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__MASK 0x001ff000U +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x001ff000U) >> 12) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x001ff000U))) + +/* macros for field adc_dc_corr_i_coeff_0 */ +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__SHIFT 21 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__WIDTH 9 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__MASK 0x3fe00000U +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x3fe00000U) >> 21) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x3fe00000U))) + +/* macros for field adc_gain_corr_enable */ +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__SHIFT 30 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__WIDTH 1 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__MASK 0x40000000U +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field adc_dc_corr_enable */ +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__SHIFT 31 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__WIDTH 1 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__MASK 0x80000000U +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define ADC_GAIN_DC_CORR_B0__TYPE u_int32_t +#define ADC_GAIN_DC_CORR_B0__READ 0xffffffffU +#define ADC_GAIN_DC_CORR_B0__WRITE 0xffffffffU + +#endif /* __ADC_GAIN_DC_CORR_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_adc_gain_dc_corr_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_ADC_GAIN_DC_CORR_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b0 */ +#ifndef __RX_IQ_CORR_B0_MACRO__ +#define __RX_IQ_CORR_B0_MACRO__ + +/* macros for field rx_iqcorr_q_q_coff_0 */ +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__SHIFT 0 +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__WIDTH 7 +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__MASK 0x0000007fU +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field rx_iqcorr_q_i_coff_0 */ +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__SHIFT 7 +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__WIDTH 7 +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__MASK 0x00003f80U +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f80U) >> 7) +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00003f80U) +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00003f80U) +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00003f80U))) + +/* macros for field rx_iqcorr_enable */ +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__SHIFT 14 +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__WIDTH 1 +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__MASK 0x00004000U +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field loopback_iqcorr_q_q_coff_0 */ +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__SHIFT 15 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__WIDTH 7 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__MASK 0x003f8000U +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f8000U) >> 15) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x003f8000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x003f8000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x003f8000U))) + +/* macros for field loopback_iqcorr_q_i_coff_0 */ +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__SHIFT 22 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__WIDTH 7 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__MASK 0x1fc00000U +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x1fc00000U) >> 22) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x1fc00000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x1fc00000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x1fc00000U))) + +/* macros for field loopback_iqcorr_enable */ +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__SHIFT 29 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__WIDTH 1 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__MASK 0x20000000U +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define RX_IQ_CORR_B0__TYPE u_int32_t +#define RX_IQ_CORR_B0__READ 0x3fffffffU +#define RX_IQ_CORR_B0__WRITE 0x3fffffffU + +#endif /* __RX_IQ_CORR_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_rx_iq_corr_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_RX_IQ_CORR_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_am2am_mask */ +#ifndef __PAPRD_AM2AM_MASK_MACRO__ +#define __PAPRD_AM2AM_MASK_MACRO__ + +/* macros for field paprd_am2am_mask */ +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__SHIFT 0 +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__WIDTH 25 +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__MASK 0x01ffffffU +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x01ffffffU +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x01ffffffU) +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01ffffffU) | ((u_int32_t)(src) &\ + 0x01ffffffU) +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x01ffffffU))) +#define PAPRD_AM2AM_MASK__TYPE u_int32_t +#define PAPRD_AM2AM_MASK__READ 0x01ffffffU +#define PAPRD_AM2AM_MASK__WRITE 0x01ffffffU + +#endif /* __PAPRD_AM2AM_MASK_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_am2am_mask */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_AM2AM_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_am2pm_mask */ +#ifndef __PAPRD_AM2PM_MASK_MACRO__ +#define __PAPRD_AM2PM_MASK_MACRO__ + +/* macros for field paprd_am2pm_mask */ +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__SHIFT 0 +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__WIDTH 25 +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__MASK 0x01ffffffU +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x01ffffffU +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x01ffffffU) +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01ffffffU) | ((u_int32_t)(src) &\ + 0x01ffffffU) +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x01ffffffU))) +#define PAPRD_AM2PM_MASK__TYPE u_int32_t +#define PAPRD_AM2PM_MASK__READ 0x01ffffffU +#define PAPRD_AM2PM_MASK__WRITE 0x01ffffffU + +#endif /* __PAPRD_AM2PM_MASK_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_am2pm_mask */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_AM2PM_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ht40_mask */ +#ifndef __PAPRD_HT40_MASK_MACRO__ +#define __PAPRD_HT40_MASK_MACRO__ + +/* macros for field paprd_ht40_mask */ +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__SHIFT 0 +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__WIDTH 25 +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__MASK 0x01ffffffU +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x01ffffffU +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x01ffffffU) +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01ffffffU) | ((u_int32_t)(src) &\ + 0x01ffffffU) +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x01ffffffU))) +#define PAPRD_HT40_MASK__TYPE u_int32_t +#define PAPRD_HT40_MASK__READ 0x01ffffffU +#define PAPRD_HT40_MASK__WRITE 0x01ffffffU + +#endif /* __PAPRD_HT40_MASK_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_ht40_mask */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_HT40_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b0 */ +#ifndef __PAPRD_CTRL0_B0_MACRO__ +#define __PAPRD_CTRL0_B0_MACRO__ + +/* macros for field paprd_enable_0 */ +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__SHIFT 0 +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__WIDTH 1 +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__MASK 0x00000001U +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_use_single_table_0 */ +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__SHIFT 1 +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__WIDTH 1 +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__MASK 0x00000002U +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_valid_gain_0 */ +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__SHIFT 2 +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__WIDTH 25 +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__MASK 0x07fffffcU +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fffffcU) >> 2) +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fffffcU) | (((u_int32_t)(src) <<\ + 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x07fffffcU))) + +/* macros for field paprd_mag_thrsh_0 */ +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__SHIFT 27 +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__WIDTH 5 +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__MASK 0xf8000000U +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define PAPRD_CTRL0_B0__TYPE u_int32_t +#define PAPRD_CTRL0_B0__READ 0xffffffffU +#define PAPRD_CTRL0_B0__WRITE 0xffffffffU + +#endif /* __PAPRD_CTRL0_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_ctrl0_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_CTRL0_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b0 */ +#ifndef __PAPRD_CTRL1_B0_MACRO__ +#define __PAPRD_CTRL1_B0_MACRO__ + +/* macros for field paprd_adaptive_scaling_enable_0 */ +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__SHIFT 0 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__WIDTH 1 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__MASK 0x00000001U +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_am2am_enable_0 */ +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__SHIFT 1 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__WIDTH 1 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__MASK 0x00000002U +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_adaptive_am2pm_enable_0 */ +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__SHIFT 2 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__WIDTH 1 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__MASK 0x00000004U +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field paprd_power_at_am2am_cal_0 */ +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__SHIFT 3 +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__WIDTH 6 +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__MASK 0x000001f8U +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001f8U) >> 3) +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000001f8U) +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000001f8U) +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000001f8U))) + +/* macros for field pa_gain_scale_factor_0 */ +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__SHIFT 9 +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__WIDTH 8 +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__MASK 0x0001fe00U +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fe00U) >> 9) +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((u_int32_t)(src) <<\ + 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x0001fe00U))) + +/* macros for field paprd_mag_scale_factor_0 */ +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__SHIFT 17 +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__WIDTH 10 +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__MASK 0x07fe0000U +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fe0000U) >> 17) +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x07fe0000U))) + +/* macros for field paprd_trainer_iandq_sel_0 */ +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__SHIFT 27 +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__WIDTH 1 +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__MASK 0x08000000U +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) +#define PAPRD_CTRL1_B0__TYPE u_int32_t +#define PAPRD_CTRL1_B0__READ 0x0fffffffU +#define PAPRD_CTRL1_B0__WRITE 0x0fffffffU + +#endif /* __PAPRD_CTRL1_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_ctrl1_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_CTRL1_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain123_b0 */ +#ifndef __PA_GAIN123_B0_MACRO__ +#define __PA_GAIN123_B0_MACRO__ + +/* macros for field pa_gain1_0 */ +#define PA_GAIN123_B0__PA_GAIN1_0__SHIFT 0 +#define PA_GAIN123_B0__PA_GAIN1_0__WIDTH 10 +#define PA_GAIN123_B0__PA_GAIN1_0__MASK 0x000003ffU +#define PA_GAIN123_B0__PA_GAIN1_0__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN123_B0__PA_GAIN1_0__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN123_B0__PA_GAIN1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN123_B0__PA_GAIN1_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain2_0 */ +#define PA_GAIN123_B0__PA_GAIN2_0__SHIFT 10 +#define PA_GAIN123_B0__PA_GAIN2_0__WIDTH 10 +#define PA_GAIN123_B0__PA_GAIN2_0__MASK 0x000ffc00U +#define PA_GAIN123_B0__PA_GAIN2_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN123_B0__PA_GAIN2_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN123_B0__PA_GAIN2_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN123_B0__PA_GAIN2_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field pa_gain3_0 */ +#define PA_GAIN123_B0__PA_GAIN3_0__SHIFT 20 +#define PA_GAIN123_B0__PA_GAIN3_0__WIDTH 10 +#define PA_GAIN123_B0__PA_GAIN3_0__MASK 0x3ff00000U +#define PA_GAIN123_B0__PA_GAIN3_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ff00000U) >> 20) +#define PA_GAIN123_B0__PA_GAIN3_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x3ff00000U) +#define PA_GAIN123_B0__PA_GAIN3_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x3ff00000U) +#define PA_GAIN123_B0__PA_GAIN3_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define PA_GAIN123_B0__TYPE u_int32_t +#define PA_GAIN123_B0__READ 0x3fffffffU +#define PA_GAIN123_B0__WRITE 0x3fffffffU + +#endif /* __PA_GAIN123_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_pa_gain123_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PA_GAIN123_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain45_b0 */ +#ifndef __PA_GAIN45_B0_MACRO__ +#define __PA_GAIN45_B0_MACRO__ + +/* macros for field pa_gain4_0 */ +#define PA_GAIN45_B0__PA_GAIN4_0__SHIFT 0 +#define PA_GAIN45_B0__PA_GAIN4_0__WIDTH 10 +#define PA_GAIN45_B0__PA_GAIN4_0__MASK 0x000003ffU +#define PA_GAIN45_B0__PA_GAIN4_0__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN45_B0__PA_GAIN4_0__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN45_B0__PA_GAIN4_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN45_B0__PA_GAIN4_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain5_0 */ +#define PA_GAIN45_B0__PA_GAIN5_0__SHIFT 10 +#define PA_GAIN45_B0__PA_GAIN5_0__WIDTH 10 +#define PA_GAIN45_B0__PA_GAIN5_0__MASK 0x000ffc00U +#define PA_GAIN45_B0__PA_GAIN5_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN45_B0__PA_GAIN5_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN45_B0__PA_GAIN5_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN45_B0__PA_GAIN5_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field paprd_adaptive_table_valid_0 */ +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__SHIFT 20 +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__WIDTH 5 +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__MASK 0x01f00000U +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) +#define PA_GAIN45_B0__TYPE u_int32_t +#define PA_GAIN45_B0__READ 0x01ffffffU +#define PA_GAIN45_B0__WRITE 0x01ffffffU + +#endif /* __PA_GAIN45_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_pa_gain45_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PA_GAIN45_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_0_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_0_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_0_0 */ +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_0_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_0_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_0_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_pre_post_scale_0_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_1_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_1_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_1_0 */ +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_1_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_1_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_1_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_pre_post_scale_1_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_2_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_2_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_2_0 */ +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_2_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_2_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_pre_post_scale_2_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_3_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_3_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_3_0 */ +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_3_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_3_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_3_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_pre_post_scale_3_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_4_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_4_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_4_0 */ +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_4_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_4_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_4_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_pre_post_scale_4_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_5_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_5_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_5_0 */ +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_5_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_5_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_5_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_pre_post_scale_5_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_6_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_6_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_6_0 */ +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_6_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_6_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_6_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_pre_post_scale_6_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_7_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_7_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_7_0 */ +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_7_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_7_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_7_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_pre_post_scale_7_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */ +#ifndef __PAPRD_MEM_TAB_MACRO__ +#define __PAPRD_MEM_TAB_MACRO__ + +/* macros for field paprd_mem */ +#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT 0 +#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH 22 +#define PAPRD_MEM_TAB__PAPRD_MEM__MASK 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((u_int32_t)(src) &\ + 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x003fffffU))) +#define PAPRD_MEM_TAB__TYPE u_int32_t +#define PAPRD_MEM_TAB__READ 0x003fffffU +#define PAPRD_MEM_TAB__WRITE 0x003fffffU + +#endif /* __PAPRD_MEM_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_paprd_mem_tab_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_PAPRD_MEM_TAB_B0__NUM 120 + +/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */ +#ifndef __CHAN_INFO_CHAN_TAB_MACRO__ +#define __CHAN_INFO_CHAN_TAB_MACRO__ + +/* macros for field chaninfo_word */ +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT 0 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH 32 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK 0xffffffffU +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define CHAN_INFO_CHAN_TAB__TYPE u_int32_t +#define CHAN_INFO_CHAN_TAB__READ 0xffffffffU + +#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_reg_map.BB_chan_info_chan_tab_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B0__NUM 60 + +/* macros for BlueprintGlobalNameSpace::timing_control_3a */ +#ifndef __TIMING_CONTROL_3A_MACRO__ +#define __TIMING_CONTROL_3A_MACRO__ + +/* macros for field ste_thr_hi_rssi */ +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__SHIFT 0 +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__WIDTH 7 +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__MASK 0x0000007fU +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field use_htsig1_20_40_bw_value */ +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__SHIFT 7 +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__WIDTH 1 +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__MASK 0x00000080U +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) +#define TIMING_CONTROL_3A__TYPE u_int32_t +#define TIMING_CONTROL_3A__READ 0x000000ffU +#define TIMING_CONTROL_3A__WRITE 0x000000ffU + +#endif /* __TIMING_CONTROL_3A_MACRO__ */ + + +/* macros for bb_reg_block.bb_mrc_reg_map.BB_timing_control_3a */ +#define INST_BB_REG_BLOCK__BB_MRC_REG_MAP__BB_TIMING_CONTROL_3A__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ldpc_cntl1 */ +#ifndef __LDPC_CNTL1_MACRO__ +#define __LDPC_CNTL1_MACRO__ + +/* macros for field ldpc_llr_scaling0 */ +#define LDPC_CNTL1__LDPC_LLR_SCALING0__SHIFT 0 +#define LDPC_CNTL1__LDPC_LLR_SCALING0__WIDTH 32 +#define LDPC_CNTL1__LDPC_LLR_SCALING0__MASK 0xffffffffU +#define LDPC_CNTL1__LDPC_LLR_SCALING0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define LDPC_CNTL1__LDPC_LLR_SCALING0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define LDPC_CNTL1__LDPC_LLR_SCALING0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define LDPC_CNTL1__LDPC_LLR_SCALING0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define LDPC_CNTL1__TYPE u_int32_t +#define LDPC_CNTL1__READ 0xffffffffU +#define LDPC_CNTL1__WRITE 0xffffffffU + +#endif /* __LDPC_CNTL1_MACRO__ */ + + +/* macros for bb_reg_block.bb_mrc_reg_map.BB_ldpc_cntl1 */ +#define INST_BB_REG_BLOCK__BB_MRC_REG_MAP__BB_LDPC_CNTL1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ldpc_cntl2 */ +#ifndef __LDPC_CNTL2_MACRO__ +#define __LDPC_CNTL2_MACRO__ + +/* macros for field ldpc_llr_scaling1 */ +#define LDPC_CNTL2__LDPC_LLR_SCALING1__SHIFT 0 +#define LDPC_CNTL2__LDPC_LLR_SCALING1__WIDTH 16 +#define LDPC_CNTL2__LDPC_LLR_SCALING1__MASK 0x0000ffffU +#define LDPC_CNTL2__LDPC_LLR_SCALING1__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define LDPC_CNTL2__LDPC_LLR_SCALING1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define LDPC_CNTL2__LDPC_LLR_SCALING1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define LDPC_CNTL2__LDPC_LLR_SCALING1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field ldpc_latency */ +#define LDPC_CNTL2__LDPC_LATENCY__SHIFT 16 +#define LDPC_CNTL2__LDPC_LATENCY__WIDTH 11 +#define LDPC_CNTL2__LDPC_LATENCY__MASK 0x07ff0000U +#define LDPC_CNTL2__LDPC_LATENCY__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define LDPC_CNTL2__LDPC_LATENCY__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define LDPC_CNTL2__LDPC_LATENCY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define LDPC_CNTL2__LDPC_LATENCY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) +#define LDPC_CNTL2__TYPE u_int32_t +#define LDPC_CNTL2__READ 0x07ffffffU +#define LDPC_CNTL2__WRITE 0x07ffffffU + +#endif /* __LDPC_CNTL2_MACRO__ */ + + +/* macros for bb_reg_block.bb_mrc_reg_map.BB_ldpc_cntl2 */ +#define INST_BB_REG_BLOCK__BB_MRC_REG_MAP__BB_LDPC_CNTL2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pilot_spur_mask */ +#ifndef __PILOT_SPUR_MASK_MACRO__ +#define __PILOT_SPUR_MASK_MACRO__ + +/* macros for field cf_pilot_mask_A */ +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__SHIFT 0 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__WIDTH 5 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__MASK 0x0000001fU +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field cf_pilot_mask_idx_A */ +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__SHIFT 5 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__WIDTH 7 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__MASK 0x00000fe0U +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fe0U) >> 5) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000fe0U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fe0U) | (((u_int32_t)(src) <<\ + 5) & 0x00000fe0U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000fe0U))) + +/* macros for field cf_pilot_mask_B */ +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__SHIFT 12 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__WIDTH 5 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__MASK 0x0001f000U +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field cf_pilot_mask_idx_B */ +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__SHIFT 17 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__WIDTH 7 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__MASK 0x00fe0000U +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fe0000U) >> 17) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00fe0000U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x00fe0000U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00fe0000U))) +#define PILOT_SPUR_MASK__TYPE u_int32_t +#define PILOT_SPUR_MASK__READ 0x00ffffffU +#define PILOT_SPUR_MASK__WRITE 0x00ffffffU + +#endif /* __PILOT_SPUR_MASK_MACRO__ */ + + +/* macros for bb_reg_block.bb_mrc_reg_map.BB_pilot_spur_mask */ +#define INST_BB_REG_BLOCK__BB_MRC_REG_MAP__BB_PILOT_SPUR_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chan_spur_mask */ +#ifndef __CHAN_SPUR_MASK_MACRO__ +#define __CHAN_SPUR_MASK_MACRO__ + +/* macros for field cf_chan_mask_A */ +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__SHIFT 0 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__WIDTH 5 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__MASK 0x0000001fU +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field cf_chan_mask_idx_A */ +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__SHIFT 5 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__WIDTH 7 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__MASK 0x00000fe0U +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fe0U) >> 5) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000fe0U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fe0U) | (((u_int32_t)(src) <<\ + 5) & 0x00000fe0U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000fe0U))) + +/* macros for field cf_chan_mask_B */ +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__SHIFT 12 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__WIDTH 5 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__MASK 0x0001f000U +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field cf_chan_mask_idx_B */ +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__SHIFT 17 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__WIDTH 7 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__MASK 0x00fe0000U +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fe0000U) >> 17) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00fe0000U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x00fe0000U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00fe0000U))) +#define CHAN_SPUR_MASK__TYPE u_int32_t +#define CHAN_SPUR_MASK__READ 0x00ffffffU +#define CHAN_SPUR_MASK__WRITE 0x00ffffffU + +#endif /* __CHAN_SPUR_MASK_MACRO__ */ + + +/* macros for bb_reg_block.bb_mrc_reg_map.BB_chan_spur_mask */ +#define INST_BB_REG_BLOCK__BB_MRC_REG_MAP__BB_CHAN_SPUR_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::short_gi_delta_slope */ +#ifndef __SHORT_GI_DELTA_SLOPE_MACRO__ +#define __SHORT_GI_DELTA_SLOPE_MACRO__ + +/* macros for field delta_slope_coef_exp_short_gi */ +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__SHIFT 0 +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__WIDTH 4 +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__MASK 0x0000000fU +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field delta_slope_coef_man_short_gi */ +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__SHIFT 4 +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__WIDTH 15 +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__MASK 0x0007fff0U +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__READ(src) \ + (((u_int32_t)(src)\ + & 0x0007fff0U) >> 4) +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x0007fff0U) +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007fff0U) | (((u_int32_t)(src) <<\ + 4) & 0x0007fff0U) +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x0007fff0U))) +#define SHORT_GI_DELTA_SLOPE__TYPE u_int32_t +#define SHORT_GI_DELTA_SLOPE__READ 0x0007ffffU +#define SHORT_GI_DELTA_SLOPE__WRITE 0x0007ffffU + +#endif /* __SHORT_GI_DELTA_SLOPE_MACRO__ */ + + +/* macros for bb_reg_block.bb_mrc_reg_map.BB_short_gi_delta_slope */ +#define INST_BB_REG_BLOCK__BB_MRC_REG_MAP__BB_SHORT_GI_DELTA_SLOPE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ml_cntl1 */ +#ifndef __ML_CNTL1_MACRO__ +#define __ML_CNTL1_MACRO__ + +/* macros for field cf_ml_2s_weight_table */ +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__SHIFT 0 +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__WIDTH 24 +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__MASK 0x00ffffffU +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00ffffffU +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) + +/* macros for field cf_is_flat_ch_thr_ml */ +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__SHIFT 24 +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__WIDTH 2 +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__MASK 0x03000000U +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__READ(src) \ + (((u_int32_t)(src)\ + & 0x03000000U) >> 24) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x03000000U) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field cf_is_flat_ch_thr_zf */ +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__SHIFT 26 +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__WIDTH 2 +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__MASK 0x0c000000U +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__READ(src) \ + (((u_int32_t)(src)\ + & 0x0c000000U) >> 26) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x0c000000U) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) +#define ML_CNTL1__TYPE u_int32_t +#define ML_CNTL1__READ 0x0fffffffU +#define ML_CNTL1__WRITE 0x0fffffffU + +#endif /* __ML_CNTL1_MACRO__ */ + + +/* macros for bb_reg_block.bb_mrc_reg_map.BB_ml_cntl1 */ +#define INST_BB_REG_BLOCK__BB_MRC_REG_MAP__BB_ML_CNTL1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ml_cntl2 */ +#ifndef __ML_CNTL2_MACRO__ +#define __ML_CNTL2_MACRO__ + +/* macros for field cf_ml_3s_weight_table */ +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__SHIFT 0 +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__WIDTH 24 +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__MASK 0x00ffffffU +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00ffffffU +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define ML_CNTL2__TYPE u_int32_t +#define ML_CNTL2__READ 0x00ffffffU +#define ML_CNTL2__WRITE 0x00ffffffU + +#endif /* __ML_CNTL2_MACRO__ */ + + +/* macros for bb_reg_block.bb_mrc_reg_map.BB_ml_cntl2 */ +#define INST_BB_REG_BLOCK__BB_MRC_REG_MAP__BB_ML_CNTL2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tstadc */ +#ifndef __TSTADC_MACRO__ +#define __TSTADC_MACRO__ + +/* macros for field tstadc_out_q */ +#define TSTADC__TSTADC_OUT_Q__SHIFT 0 +#define TSTADC__TSTADC_OUT_Q__WIDTH 10 +#define TSTADC__TSTADC_OUT_Q__MASK 0x000003ffU +#define TSTADC__TSTADC_OUT_Q__READ(src) (u_int32_t)(src) & 0x000003ffU + +/* macros for field tstadc_out_i */ +#define TSTADC__TSTADC_OUT_I__SHIFT 10 +#define TSTADC__TSTADC_OUT_I__WIDTH 10 +#define TSTADC__TSTADC_OUT_I__MASK 0x000ffc00U +#define TSTADC__TSTADC_OUT_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define TSTADC__TYPE u_int32_t +#define TSTADC__READ 0x000fffffU + +#endif /* __TSTADC_MACRO__ */ + + +/* macros for bb_reg_block.bb_mrc_reg_map.BB_tstadc */ +#define INST_BB_REG_BLOCK__BB_MRC_REG_MAP__BB_TSTADC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_1 */ +#ifndef __BBB_RX_CTRL_1_MACRO__ +#define __BBB_RX_CTRL_1_MACRO__ + +/* macros for field coarse_tim_threshold_2 */ +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__SHIFT 0 +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__WIDTH 3 +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__MASK 0x00000007U +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field coarse_tim_threshold */ +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__SHIFT 3 +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__WIDTH 5 +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__MASK 0x000000f8U +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f8U) >> 3) +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000000f8U) +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000000f8U) +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000000f8U))) + +/* macros for field coarse_tim_n_sync */ +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__SHIFT 8 +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__WIDTH 3 +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__MASK 0x00000700U +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field max_bal_long */ +#define BBB_RX_CTRL_1__MAX_BAL_LONG__SHIFT 11 +#define BBB_RX_CTRL_1__MAX_BAL_LONG__WIDTH 5 +#define BBB_RX_CTRL_1__MAX_BAL_LONG__MASK 0x0000f800U +#define BBB_RX_CTRL_1__MAX_BAL_LONG__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f800U) >> 11) +#define BBB_RX_CTRL_1__MAX_BAL_LONG__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x0000f800U) +#define BBB_RX_CTRL_1__MAX_BAL_LONG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0000f800U) +#define BBB_RX_CTRL_1__MAX_BAL_LONG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0000f800U))) + +/* macros for field max_bal_short */ +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__SHIFT 16 +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__WIDTH 5 +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__MASK 0x001f0000U +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) + +/* macros for field recon_lms_step */ +#define BBB_RX_CTRL_1__RECON_LMS_STEP__SHIFT 21 +#define BBB_RX_CTRL_1__RECON_LMS_STEP__WIDTH 3 +#define BBB_RX_CTRL_1__RECON_LMS_STEP__MASK 0x00e00000U +#define BBB_RX_CTRL_1__RECON_LMS_STEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00e00000U) >> 21) +#define BBB_RX_CTRL_1__RECON_LMS_STEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00e00000U) +#define BBB_RX_CTRL_1__RECON_LMS_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define BBB_RX_CTRL_1__RECON_LMS_STEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field sb_check_win */ +#define BBB_RX_CTRL_1__SB_CHECK_WIN__SHIFT 24 +#define BBB_RX_CTRL_1__SB_CHECK_WIN__WIDTH 7 +#define BBB_RX_CTRL_1__SB_CHECK_WIN__MASK 0x7f000000U +#define BBB_RX_CTRL_1__SB_CHECK_WIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f000000U) >> 24) +#define BBB_RX_CTRL_1__SB_CHECK_WIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define BBB_RX_CTRL_1__SB_CHECK_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define BBB_RX_CTRL_1__SB_CHECK_WIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) + +/* macros for field en_rx_abort_cck */ +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__SHIFT 31 +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__WIDTH 1 +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__MASK 0x80000000U +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define BBB_RX_CTRL_1__TYPE u_int32_t +#define BBB_RX_CTRL_1__READ 0xffffffffU +#define BBB_RX_CTRL_1__WRITE 0xffffffffU + +#endif /* __BBB_RX_CTRL_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_bbb_reg_map.BB_bbb_rx_ctrl_1 */ +#define INST_BB_REG_BLOCK__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_2 */ +#ifndef __BBB_RX_CTRL_2_MACRO__ +#define __BBB_RX_CTRL_2_MACRO__ + +/* macros for field freq_est_n_avg_long */ +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__SHIFT 0 +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__WIDTH 6 +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__MASK 0x0000003fU +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field chan_avg_long */ +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__SHIFT 6 +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__WIDTH 6 +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__MASK 0x00000fc0U +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field coarse_tim_threshold_3 */ +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__SHIFT 12 +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__WIDTH 5 +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__MASK 0x0001f000U +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field freq_track_update_period */ +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__SHIFT 17 +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__WIDTH 5 +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__MASK 0x003e0000U +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field freq_est_scaling_period */ +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__SHIFT 22 +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__WIDTH 4 +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__MASK 0x03c00000U +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x03c00000U) >> 22) +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x03c00000U) +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x03c00000U) +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x03c00000U))) + +/* macros for field loop_coef_dpsk_c2_data */ +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__SHIFT 26 +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__WIDTH 6 +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__MASK 0xfc000000U +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0xfc000000U) >> 26) +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0xfc000000U) +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((u_int32_t)(src) <<\ + 26) & 0xfc000000U) +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0xfc000000U))) +#define BBB_RX_CTRL_2__TYPE u_int32_t +#define BBB_RX_CTRL_2__READ 0xffffffffU +#define BBB_RX_CTRL_2__WRITE 0xffffffffU + +#endif /* __BBB_RX_CTRL_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_bbb_reg_map.BB_bbb_rx_ctrl_2 */ +#define INST_BB_REG_BLOCK__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_3 */ +#ifndef __BBB_RX_CTRL_3_MACRO__ +#define __BBB_RX_CTRL_3_MACRO__ + +/* macros for field tim_adjust_freq_dpsk */ +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__SHIFT 0 +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__WIDTH 8 +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__MASK 0x000000ffU +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tim_adjust_freq_cck */ +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__SHIFT 8 +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__WIDTH 8 +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__MASK 0x0000ff00U +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field timer_n_sfd */ +#define BBB_RX_CTRL_3__TIMER_N_SFD__SHIFT 16 +#define BBB_RX_CTRL_3__TIMER_N_SFD__WIDTH 8 +#define BBB_RX_CTRL_3__TIMER_N_SFD__MASK 0x00ff0000U +#define BBB_RX_CTRL_3__TIMER_N_SFD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define BBB_RX_CTRL_3__TIMER_N_SFD__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define BBB_RX_CTRL_3__TIMER_N_SFD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define BBB_RX_CTRL_3__TIMER_N_SFD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define BBB_RX_CTRL_3__TYPE u_int32_t +#define BBB_RX_CTRL_3__READ 0x00ffffffU +#define BBB_RX_CTRL_3__WRITE 0x00ffffffU + +#endif /* __BBB_RX_CTRL_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_bbb_reg_map.BB_bbb_rx_ctrl_3 */ +#define INST_BB_REG_BLOCK__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_4 */ +#ifndef __BBB_RX_CTRL_4_MACRO__ +#define __BBB_RX_CTRL_4_MACRO__ + +/* macros for field timer_n_sync */ +#define BBB_RX_CTRL_4__TIMER_N_SYNC__SHIFT 0 +#define BBB_RX_CTRL_4__TIMER_N_SYNC__WIDTH 4 +#define BBB_RX_CTRL_4__TIMER_N_SYNC__MASK 0x0000000fU +#define BBB_RX_CTRL_4__TIMER_N_SYNC__READ(src) (u_int32_t)(src) & 0x0000000fU +#define BBB_RX_CTRL_4__TIMER_N_SYNC__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define BBB_RX_CTRL_4__TIMER_N_SYNC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define BBB_RX_CTRL_4__TIMER_N_SYNC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field tim_adjust_timer_exp */ +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__SHIFT 4 +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__WIDTH 12 +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__MASK 0x0000fff0U +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fff0U) >> 4) +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x0000fff0U) +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fff0U) | (((u_int32_t)(src) <<\ + 4) & 0x0000fff0U) +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x0000fff0U))) + +/* macros for field force_unlocked_clocks */ +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__SHIFT 16 +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__WIDTH 1 +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__MASK 0x00010000U +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field dynamic_pream_sel */ +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__SHIFT 17 +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__WIDTH 1 +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__MASK 0x00020000U +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field short_preamble */ +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__SHIFT 18 +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__WIDTH 1 +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__MASK 0x00040000U +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field freq_est_n_avg_short */ +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__SHIFT 19 +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__WIDTH 6 +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__MASK 0x01f80000U +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f80000U) >> 19) +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x01f80000U) +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f80000U) | (((u_int32_t)(src) <<\ + 19) & 0x01f80000U) +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x01f80000U))) + +/* macros for field chan_avg_short */ +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__SHIFT 25 +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__WIDTH 6 +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__MASK 0x7e000000U +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x7e000000U) >> 25) +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x7e000000U) +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x7e000000U) +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x7e000000U))) + +/* macros for field use_mrc_weight */ +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__SHIFT 31 +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__WIDTH 1 +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__MASK 0x80000000U +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define BBB_RX_CTRL_4__TYPE u_int32_t +#define BBB_RX_CTRL_4__READ 0xffffffffU +#define BBB_RX_CTRL_4__WRITE 0xffffffffU + +#endif /* __BBB_RX_CTRL_4_MACRO__ */ + + +/* macros for bb_reg_block.bb_bbb_reg_map.BB_bbb_rx_ctrl_4 */ +#define INST_BB_REG_BLOCK__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_5 */ +#ifndef __BBB_RX_CTRL_5_MACRO__ +#define __BBB_RX_CTRL_5_MACRO__ + +/* macros for field loop_coef_dpsk_c1_data */ +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__SHIFT 0 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__WIDTH 5 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__MASK 0x0000001fU +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field loop_coef_dpsk_c1_head */ +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__SHIFT 5 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__WIDTH 5 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__MASK 0x000003e0U +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field loop_coef_dpsk_c2_head */ +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__SHIFT 10 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__WIDTH 6 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__MASK 0x0000fc00U +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fc00U) >> 10) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0000fc00U) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0000fc00U) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0000fc00U))) + +/* macros for field loop_coef_cck_c1 */ +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__SHIFT 16 +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__WIDTH 5 +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__MASK 0x001f0000U +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) + +/* macros for field loop_coef_cck_c2 */ +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__SHIFT 21 +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__WIDTH 6 +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__MASK 0x07e00000U +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07e00000U) >> 21) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x07e00000U) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x07e00000U) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x07e00000U))) +#define BBB_RX_CTRL_5__TYPE u_int32_t +#define BBB_RX_CTRL_5__READ 0x07ffffffU +#define BBB_RX_CTRL_5__WRITE 0x07ffffffU + +#endif /* __BBB_RX_CTRL_5_MACRO__ */ + + +/* macros for bb_reg_block.bb_bbb_reg_map.BB_bbb_rx_ctrl_5 */ +#define INST_BB_REG_BLOCK__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_6 */ +#ifndef __BBB_RX_CTRL_6_MACRO__ +#define __BBB_RX_CTRL_6_MACRO__ + +/* macros for field sync_start_delay */ +#define BBB_RX_CTRL_6__SYNC_START_DELAY__SHIFT 0 +#define BBB_RX_CTRL_6__SYNC_START_DELAY__WIDTH 10 +#define BBB_RX_CTRL_6__SYNC_START_DELAY__MASK 0x000003ffU +#define BBB_RX_CTRL_6__SYNC_START_DELAY__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define BBB_RX_CTRL_6__SYNC_START_DELAY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define BBB_RX_CTRL_6__SYNC_START_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define BBB_RX_CTRL_6__SYNC_START_DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field map_1s_to_2s */ +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__SHIFT 10 +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__WIDTH 1 +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__MASK 0x00000400U +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field start_iir_delay */ +#define BBB_RX_CTRL_6__START_IIR_DELAY__SHIFT 11 +#define BBB_RX_CTRL_6__START_IIR_DELAY__WIDTH 10 +#define BBB_RX_CTRL_6__START_IIR_DELAY__MASK 0x001ff800U +#define BBB_RX_CTRL_6__START_IIR_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x001ff800U) >> 11) +#define BBB_RX_CTRL_6__START_IIR_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x001ff800U) +#define BBB_RX_CTRL_6__START_IIR_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001ff800U) | (((u_int32_t)(src) <<\ + 11) & 0x001ff800U) +#define BBB_RX_CTRL_6__START_IIR_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x001ff800U))) + +/* macros for field use_mcorr_weight */ +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__SHIFT 21 +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__WIDTH 1 +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__MASK 0x00200000U +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field use_bkpwr_for_center_index */ +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__SHIFT 22 +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__WIDTH 1 +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__MASK 0x00400000U +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field cck_sel_chain_by_eo */ +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__SHIFT 23 +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__WIDTH 1 +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__MASK 0x00800000U +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field force_cck_sel_chain */ +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__SHIFT 24 +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__WIDTH 1 +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__MASK 0x01000000U +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field force_center_index */ +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__SHIFT 25 +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__WIDTH 1 +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__MASK 0x02000000U +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) +#define BBB_RX_CTRL_6__TYPE u_int32_t +#define BBB_RX_CTRL_6__READ 0x03ffffffU +#define BBB_RX_CTRL_6__WRITE 0x03ffffffU + +#endif /* __BBB_RX_CTRL_6_MACRO__ */ + + +/* macros for bb_reg_block.bb_bbb_reg_map.BB_bbb_rx_ctrl_6 */ +#define INST_BB_REG_BLOCK__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::force_clken_cck */ +#ifndef __FORCE_CLKEN_CCK_MACRO__ +#define __FORCE_CLKEN_CCK_MACRO__ + +/* macros for field force_rx_enable0 */ +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__SHIFT 0 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__MASK 0x00000001U +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field force_rx_enable1 */ +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__SHIFT 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__MASK 0x00000002U +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field force_rx_enable2 */ +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__SHIFT 2 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__MASK 0x00000004U +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field force_rx_enable3 */ +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__SHIFT 3 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__MASK 0x00000008U +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field force_rx_always */ +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__SHIFT 4 +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__MASK 0x00000010U +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field force_txsm_clken */ +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__SHIFT 5 +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__MASK 0x00000020U +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define FORCE_CLKEN_CCK__TYPE u_int32_t +#define FORCE_CLKEN_CCK__READ 0x0000003fU +#define FORCE_CLKEN_CCK__WRITE 0x0000003fU + +#endif /* __FORCE_CLKEN_CCK_MACRO__ */ + + +/* macros for bb_reg_block.bb_bbb_reg_map.BB_force_clken_cck */ +#define INST_BB_REG_BLOCK__BB_BBB_REG_MAP__BB_FORCE_CLKEN_CCK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::settling_time */ +#ifndef __SETTLING_TIME_MACRO__ +#define __SETTLING_TIME_MACRO__ + +/* macros for field agc_settling */ +#define SETTLING_TIME__AGC_SETTLING__SHIFT 0 +#define SETTLING_TIME__AGC_SETTLING__WIDTH 7 +#define SETTLING_TIME__AGC_SETTLING__MASK 0x0000007fU +#define SETTLING_TIME__AGC_SETTLING__READ(src) (u_int32_t)(src) & 0x0000007fU +#define SETTLING_TIME__AGC_SETTLING__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define SETTLING_TIME__AGC_SETTLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define SETTLING_TIME__AGC_SETTLING__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field switch_settling */ +#define SETTLING_TIME__SWITCH_SETTLING__SHIFT 7 +#define SETTLING_TIME__SWITCH_SETTLING__WIDTH 7 +#define SETTLING_TIME__SWITCH_SETTLING__MASK 0x00003f80U +#define SETTLING_TIME__SWITCH_SETTLING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f80U) >> 7) +#define SETTLING_TIME__SWITCH_SETTLING__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00003f80U) +#define SETTLING_TIME__SWITCH_SETTLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00003f80U) +#define SETTLING_TIME__SWITCH_SETTLING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00003f80U))) + +/* macros for field adcsat_thrl */ +#define SETTLING_TIME__ADCSAT_THRL__SHIFT 14 +#define SETTLING_TIME__ADCSAT_THRL__WIDTH 6 +#define SETTLING_TIME__ADCSAT_THRL__MASK 0x000fc000U +#define SETTLING_TIME__ADCSAT_THRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) +#define SETTLING_TIME__ADCSAT_THRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x000fc000U) +#define SETTLING_TIME__ADCSAT_THRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x000fc000U) +#define SETTLING_TIME__ADCSAT_THRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x000fc000U))) + +/* macros for field adcsat_thrh */ +#define SETTLING_TIME__ADCSAT_THRH__SHIFT 20 +#define SETTLING_TIME__ADCSAT_THRH__WIDTH 6 +#define SETTLING_TIME__ADCSAT_THRH__MASK 0x03f00000U +#define SETTLING_TIME__ADCSAT_THRH__READ(src) \ + (((u_int32_t)(src)\ + & 0x03f00000U) >> 20) +#define SETTLING_TIME__ADCSAT_THRH__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x03f00000U) +#define SETTLING_TIME__ADCSAT_THRH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x03f00000U) +#define SETTLING_TIME__ADCSAT_THRH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x03f00000U))) + +/* macros for field lbreset_advance */ +#define SETTLING_TIME__LBRESET_ADVANCE__SHIFT 26 +#define SETTLING_TIME__LBRESET_ADVANCE__WIDTH 4 +#define SETTLING_TIME__LBRESET_ADVANCE__MASK 0x3c000000U +#define SETTLING_TIME__LBRESET_ADVANCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x3c000000U) >> 26) +#define SETTLING_TIME__LBRESET_ADVANCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x3c000000U) +#define SETTLING_TIME__LBRESET_ADVANCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x3c000000U) +#define SETTLING_TIME__LBRESET_ADVANCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x3c000000U))) +#define SETTLING_TIME__TYPE u_int32_t +#define SETTLING_TIME__READ 0x3fffffffU +#define SETTLING_TIME__WRITE 0x3fffffffU + +#endif /* __SETTLING_TIME_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_settling_time */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_SETTLING_TIME__NUM 1 + +/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b0 */ +#ifndef __GAIN_FORCE_MAX_GAINS_B0_MACRO__ +#define __GAIN_FORCE_MAX_GAINS_B0_MACRO__ + +/* macros for field rf_gain_f_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__SHIFT 0 +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__MASK 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field mb_gain_f_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__SHIFT 8 +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__MASK 0x0000ff00U +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field xatten1_sw_f_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__SHIFT 16 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__MASK 0x00010000U +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field xatten2_sw_f_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__SHIFT 17 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__MASK 0x00020000U +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field xatten1_hyst_margin_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__SHIFT 18 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__MASK 0x01fc0000U +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fc0000U) >> 18) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x01fc0000U))) + +/* macros for field xatten2_hyst_margin_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__SHIFT 25 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__MASK 0xfe000000U +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0xfe000000U) >> 25) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfe000000U) | (((u_int32_t)(src) <<\ + 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0xfe000000U))) +#define GAIN_FORCE_MAX_GAINS_B0__TYPE u_int32_t +#define GAIN_FORCE_MAX_GAINS_B0__READ 0xffffffffU +#define GAIN_FORCE_MAX_GAINS_B0__WRITE 0xffffffffU + +#endif /* __GAIN_FORCE_MAX_GAINS_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_gain_force_max_gains_b0 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::gains_min_offsets */ +#ifndef __GAINS_MIN_OFFSETS_MACRO__ +#define __GAINS_MIN_OFFSETS_MACRO__ + +/* macros for field offsetC1 */ +#define GAINS_MIN_OFFSETS__OFFSETC1__SHIFT 0 +#define GAINS_MIN_OFFSETS__OFFSETC1__WIDTH 7 +#define GAINS_MIN_OFFSETS__OFFSETC1__MASK 0x0000007fU +#define GAINS_MIN_OFFSETS__OFFSETC1__READ(src) (u_int32_t)(src) & 0x0000007fU +#define GAINS_MIN_OFFSETS__OFFSETC1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GAINS_MIN_OFFSETS__OFFSETC1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GAINS_MIN_OFFSETS__OFFSETC1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field offsetC2 */ +#define GAINS_MIN_OFFSETS__OFFSETC2__SHIFT 7 +#define GAINS_MIN_OFFSETS__OFFSETC2__WIDTH 5 +#define GAINS_MIN_OFFSETS__OFFSETC2__MASK 0x00000f80U +#define GAINS_MIN_OFFSETS__OFFSETC2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f80U) >> 7) +#define GAINS_MIN_OFFSETS__OFFSETC2__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000f80U) +#define GAINS_MIN_OFFSETS__OFFSETC2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00000f80U) +#define GAINS_MIN_OFFSETS__OFFSETC2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000f80U))) + +/* macros for field offsetC3 */ +#define GAINS_MIN_OFFSETS__OFFSETC3__SHIFT 12 +#define GAINS_MIN_OFFSETS__OFFSETC3__WIDTH 5 +#define GAINS_MIN_OFFSETS__OFFSETC3__MASK 0x0001f000U +#define GAINS_MIN_OFFSETS__OFFSETC3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define GAINS_MIN_OFFSETS__OFFSETC3__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define GAINS_MIN_OFFSETS__OFFSETC3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define GAINS_MIN_OFFSETS__OFFSETC3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field gain_force */ +#define GAINS_MIN_OFFSETS__GAIN_FORCE__SHIFT 17 +#define GAINS_MIN_OFFSETS__GAIN_FORCE__WIDTH 1 +#define GAINS_MIN_OFFSETS__GAIN_FORCE__MASK 0x00020000U +#define GAINS_MIN_OFFSETS__GAIN_FORCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define GAINS_MIN_OFFSETS__GAIN_FORCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define GAINS_MIN_OFFSETS__GAIN_FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define GAINS_MIN_OFFSETS__GAIN_FORCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define GAINS_MIN_OFFSETS__GAIN_FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define GAINS_MIN_OFFSETS__GAIN_FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field cf_agc_hist_enable */ +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__SHIFT 18 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__WIDTH 1 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__MASK 0x00040000U +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field cf_agc_hist_gc */ +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__SHIFT 19 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__WIDTH 1 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__MASK 0x00080000U +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field cf_agc_hist_voting */ +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__SHIFT 20 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__WIDTH 1 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__MASK 0x00100000U +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field cf_agc_hist_phy_err */ +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__SHIFT 21 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__WIDTH 1 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__MASK 0x00200000U +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) +#define GAINS_MIN_OFFSETS__TYPE u_int32_t +#define GAINS_MIN_OFFSETS__READ 0x003fffffU +#define GAINS_MIN_OFFSETS__WRITE 0x003fffffU + +#endif /* __GAINS_MIN_OFFSETS_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_gains_min_offsets */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_GAINS_MIN_OFFSETS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::desired_sigsize */ +#ifndef __DESIRED_SIGSIZE_MACRO__ +#define __DESIRED_SIGSIZE_MACRO__ + +/* macros for field adc_desired_size */ +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__SHIFT 0 +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__WIDTH 8 +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__MASK 0x000000ffU +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field total_desired */ +#define DESIRED_SIGSIZE__TOTAL_DESIRED__SHIFT 20 +#define DESIRED_SIGSIZE__TOTAL_DESIRED__WIDTH 8 +#define DESIRED_SIGSIZE__TOTAL_DESIRED__MASK 0x0ff00000U +#define DESIRED_SIGSIZE__TOTAL_DESIRED__READ(src) \ + (((u_int32_t)(src)\ + & 0x0ff00000U) >> 20) +#define DESIRED_SIGSIZE__TOTAL_DESIRED__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x0ff00000U) +#define DESIRED_SIGSIZE__TOTAL_DESIRED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x0ff00000U) +#define DESIRED_SIGSIZE__TOTAL_DESIRED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x0ff00000U))) + +/* macros for field init_gc_count_max */ +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__SHIFT 28 +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__WIDTH 2 +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__MASK 0x30000000U +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x30000000U) >> 28) +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x30000000U) +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) + +/* macros for field reduce_init_gc_count */ +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__SHIFT 30 +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__WIDTH 1 +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__MASK 0x40000000U +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field ena_init_gain */ +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__SHIFT 31 +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__WIDTH 1 +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__MASK 0x80000000U +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define DESIRED_SIGSIZE__TYPE u_int32_t +#define DESIRED_SIGSIZE__READ 0xfff000ffU +#define DESIRED_SIGSIZE__WRITE 0xfff000ffU + +#endif /* __DESIRED_SIGSIZE_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_desired_sigsize */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_DESIRED_SIGSIZE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::find_signal */ +#ifndef __FIND_SIGNAL_MACRO__ +#define __FIND_SIGNAL_MACRO__ + +/* macros for field relstep */ +#define FIND_SIGNAL__RELSTEP__SHIFT 0 +#define FIND_SIGNAL__RELSTEP__WIDTH 6 +#define FIND_SIGNAL__RELSTEP__MASK 0x0000003fU +#define FIND_SIGNAL__RELSTEP__READ(src) (u_int32_t)(src) & 0x0000003fU +#define FIND_SIGNAL__RELSTEP__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define FIND_SIGNAL__RELSTEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define FIND_SIGNAL__RELSTEP__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field relpwr */ +#define FIND_SIGNAL__RELPWR__SHIFT 6 +#define FIND_SIGNAL__RELPWR__WIDTH 6 +#define FIND_SIGNAL__RELPWR__MASK 0x00000fc0U +#define FIND_SIGNAL__RELPWR__READ(src) (((u_int32_t)(src) & 0x00000fc0U) >> 6) +#define FIND_SIGNAL__RELPWR__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000fc0U) +#define FIND_SIGNAL__RELPWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define FIND_SIGNAL__RELPWR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field firstep */ +#define FIND_SIGNAL__FIRSTEP__SHIFT 12 +#define FIND_SIGNAL__FIRSTEP__WIDTH 6 +#define FIND_SIGNAL__FIRSTEP__MASK 0x0003f000U +#define FIND_SIGNAL__FIRSTEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define FIND_SIGNAL__FIRSTEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define FIND_SIGNAL__FIRSTEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define FIND_SIGNAL__FIRSTEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field firpwr */ +#define FIND_SIGNAL__FIRPWR__SHIFT 18 +#define FIND_SIGNAL__FIRPWR__WIDTH 8 +#define FIND_SIGNAL__FIRPWR__MASK 0x03fc0000U +#define FIND_SIGNAL__FIRPWR__READ(src) (((u_int32_t)(src) & 0x03fc0000U) >> 18) +#define FIND_SIGNAL__FIRPWR__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x03fc0000U) +#define FIND_SIGNAL__FIRPWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x03fc0000U) +#define FIND_SIGNAL__FIRPWR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x03fc0000U))) + +/* macros for field m1count_max */ +#define FIND_SIGNAL__M1COUNT_MAX__SHIFT 26 +#define FIND_SIGNAL__M1COUNT_MAX__WIDTH 6 +#define FIND_SIGNAL__M1COUNT_MAX__MASK 0xfc000000U +#define FIND_SIGNAL__M1COUNT_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0xfc000000U) >> 26) +#define FIND_SIGNAL__M1COUNT_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0xfc000000U) +#define FIND_SIGNAL__M1COUNT_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((u_int32_t)(src) <<\ + 26) & 0xfc000000U) +#define FIND_SIGNAL__M1COUNT_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0xfc000000U))) +#define FIND_SIGNAL__TYPE u_int32_t +#define FIND_SIGNAL__READ 0xffffffffU +#define FIND_SIGNAL__WRITE 0xffffffffU + +#endif /* __FIND_SIGNAL_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_find_signal */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_FIND_SIGNAL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc */ +#ifndef __AGC_MACRO__ +#define __AGC_MACRO__ + +/* macros for field coarsepwr_const */ +#define AGC__COARSEPWR_CONST__SHIFT 0 +#define AGC__COARSEPWR_CONST__WIDTH 7 +#define AGC__COARSEPWR_CONST__MASK 0x0000007fU +#define AGC__COARSEPWR_CONST__READ(src) (u_int32_t)(src) & 0x0000007fU +#define AGC__COARSEPWR_CONST__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) +#define AGC__COARSEPWR_CONST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define AGC__COARSEPWR_CONST__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field coarse_low */ +#define AGC__COARSE_LOW__SHIFT 7 +#define AGC__COARSE_LOW__WIDTH 8 +#define AGC__COARSE_LOW__MASK 0x00007f80U +#define AGC__COARSE_LOW__READ(src) (((u_int32_t)(src) & 0x00007f80U) >> 7) +#define AGC__COARSE_LOW__WRITE(src) (((u_int32_t)(src) << 7) & 0x00007f80U) +#define AGC__COARSE_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00007f80U) +#define AGC__COARSE_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00007f80U))) + +/* macros for field coarse_high */ +#define AGC__COARSE_HIGH__SHIFT 15 +#define AGC__COARSE_HIGH__WIDTH 7 +#define AGC__COARSE_HIGH__MASK 0x003f8000U +#define AGC__COARSE_HIGH__READ(src) (((u_int32_t)(src) & 0x003f8000U) >> 15) +#define AGC__COARSE_HIGH__WRITE(src) (((u_int32_t)(src) << 15) & 0x003f8000U) +#define AGC__COARSE_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x003f8000U) +#define AGC__COARSE_HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x003f8000U))) + +/* macros for field quick_drop */ +#define AGC__QUICK_DROP__SHIFT 22 +#define AGC__QUICK_DROP__WIDTH 8 +#define AGC__QUICK_DROP__MASK 0x3fc00000U +#define AGC__QUICK_DROP__READ(src) (((u_int32_t)(src) & 0x3fc00000U) >> 22) +#define AGC__QUICK_DROP__WRITE(src) (((u_int32_t)(src) << 22) & 0x3fc00000U) +#define AGC__QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x3fc00000U) +#define AGC__QUICK_DROP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x3fc00000U))) + +/* macros for field rssi_out_select */ +#define AGC__RSSI_OUT_SELECT__SHIFT 30 +#define AGC__RSSI_OUT_SELECT__WIDTH 2 +#define AGC__RSSI_OUT_SELECT__MASK 0xc0000000U +#define AGC__RSSI_OUT_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define AGC__RSSI_OUT_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define AGC__RSSI_OUT_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define AGC__RSSI_OUT_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AGC__TYPE u_int32_t +#define AGC__READ 0xffffffffU +#define AGC__WRITE 0xffffffffU + +#endif /* __AGC_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_agc */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_AGC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b0 */ +#ifndef __EXT_ATTEN_SWITCH_CTL_B0_MACRO__ +#define __EXT_ATTEN_SWITCH_CTL_B0_MACRO__ + +/* macros for field xatten1_db_0 */ +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__SHIFT 0 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__MASK 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field xatten2_db_0 */ +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__SHIFT 6 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__MASK 0x00000fc0U +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field xatten1_margin_0 */ +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__SHIFT 12 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__MASK 0x0001f000U +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field xatten2_margin_0 */ +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__SHIFT 17 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__MASK 0x003e0000U +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field xlna_gain_db_0 */ +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__SHIFT 22 +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__MASK 0x07c00000U +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) +#define EXT_ATTEN_SWITCH_CTL_B0__TYPE u_int32_t +#define EXT_ATTEN_SWITCH_CTL_B0__READ 0x07ffffffU +#define EXT_ATTEN_SWITCH_CTL_B0__WRITE 0x07ffffffU + +#endif /* __EXT_ATTEN_SWITCH_CTL_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_ext_atten_switch_ctl_b0 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_b0 */ +#ifndef __CCA_B0_MACRO__ +#define __CCA_B0_MACRO__ + +/* macros for field cf_maxCCApwr_0 */ +#define CCA_B0__CF_MAXCCAPWR_0__SHIFT 0 +#define CCA_B0__CF_MAXCCAPWR_0__WIDTH 9 +#define CCA_B0__CF_MAXCCAPWR_0__MASK 0x000001ffU +#define CCA_B0__CF_MAXCCAPWR_0__READ(src) (u_int32_t)(src) & 0x000001ffU +#define CCA_B0__CF_MAXCCAPWR_0__WRITE(src) ((u_int32_t)(src) & 0x000001ffU) +#define CCA_B0__CF_MAXCCAPWR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_B0__CF_MAXCCAPWR_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field cf_cca_count_maxC */ +#define CCA_B0__CF_CCA_COUNT_MAXC__SHIFT 9 +#define CCA_B0__CF_CCA_COUNT_MAXC__WIDTH 3 +#define CCA_B0__CF_CCA_COUNT_MAXC__MASK 0x00000e00U +#define CCA_B0__CF_CCA_COUNT_MAXC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000e00U) >> 9) +#define CCA_B0__CF_CCA_COUNT_MAXC__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define CCA_B0__CF_CCA_COUNT_MAXC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define CCA_B0__CF_CCA_COUNT_MAXC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field cf_thresh62 */ +#define CCA_B0__CF_THRESH62__SHIFT 12 +#define CCA_B0__CF_THRESH62__WIDTH 8 +#define CCA_B0__CF_THRESH62__MASK 0x000ff000U +#define CCA_B0__CF_THRESH62__READ(src) (((u_int32_t)(src) & 0x000ff000U) >> 12) +#define CCA_B0__CF_THRESH62__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x000ff000U) +#define CCA_B0__CF_THRESH62__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x000ff000U) +#define CCA_B0__CF_THRESH62__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x000ff000U))) + +/* macros for field minCCApwr_0 */ +#define CCA_B0__MINCCAPWR_0__SHIFT 20 +#define CCA_B0__MINCCAPWR_0__WIDTH 9 +#define CCA_B0__MINCCAPWR_0__MASK 0x1ff00000U +#define CCA_B0__MINCCAPWR_0__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20) +#define CCA_B0__TYPE u_int32_t +#define CCA_B0__READ 0x1fffffffU +#define CCA_B0__WRITE 0x1fffffffU + +#endif /* __CCA_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_cca_b0 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_CCA_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b0 */ +#ifndef __CCA_CTRL_2_B0_MACRO__ +#define __CCA_CTRL_2_B0_MACRO__ + +/* macros for field minCCApwr_thr_0 */ +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__SHIFT 0 +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__WIDTH 9 +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__MASK 0x000001ffU +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field enable_minCCApwr_thr */ +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__SHIFT 9 +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__WIDTH 1 +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__MASK 0x00000200U +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field NF_gain_comp_0 */ +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__SHIFT 10 +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__WIDTH 8 +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__MASK 0x0003fc00U +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fc00U) >> 10) +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0003fc00U) +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0003fc00U) +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0003fc00U))) + +/* macros for field thresh62_mode */ +#define CCA_CTRL_2_B0__THRESH62_MODE__SHIFT 18 +#define CCA_CTRL_2_B0__THRESH62_MODE__WIDTH 1 +#define CCA_CTRL_2_B0__THRESH62_MODE__MASK 0x00040000U +#define CCA_CTRL_2_B0__THRESH62_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define CCA_CTRL_2_B0__THRESH62_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define CCA_CTRL_2_B0__THRESH62_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define CCA_CTRL_2_B0__THRESH62_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define CCA_CTRL_2_B0__THRESH62_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define CCA_CTRL_2_B0__THRESH62_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) +#define CCA_CTRL_2_B0__TYPE u_int32_t +#define CCA_CTRL_2_B0__READ 0x0007ffffU +#define CCA_CTRL_2_B0__WRITE 0x0007ffffU + +#endif /* __CCA_CTRL_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_cca_ctrl_2_b0 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_CCA_CTRL_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::restart */ +#ifndef __RESTART_MACRO__ +#define __RESTART_MACRO__ + +/* macros for field enable_restart */ +#define RESTART__ENABLE_RESTART__SHIFT 0 +#define RESTART__ENABLE_RESTART__WIDTH 1 +#define RESTART__ENABLE_RESTART__MASK 0x00000001U +#define RESTART__ENABLE_RESTART__READ(src) (u_int32_t)(src) & 0x00000001U +#define RESTART__ENABLE_RESTART__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RESTART__ENABLE_RESTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RESTART__ENABLE_RESTART__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RESTART__ENABLE_RESTART__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RESTART__ENABLE_RESTART__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field restart_lgfirpwr_delta */ +#define RESTART__RESTART_LGFIRPWR_DELTA__SHIFT 1 +#define RESTART__RESTART_LGFIRPWR_DELTA__WIDTH 5 +#define RESTART__RESTART_LGFIRPWR_DELTA__MASK 0x0000003eU +#define RESTART__RESTART_LGFIRPWR_DELTA__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) +#define RESTART__RESTART_LGFIRPWR_DELTA__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000003eU) +#define RESTART__RESTART_LGFIRPWR_DELTA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000003eU) +#define RESTART__RESTART_LGFIRPWR_DELTA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000003eU))) + +/* macros for field enable_pwr_drop_err */ +#define RESTART__ENABLE_PWR_DROP_ERR__SHIFT 6 +#define RESTART__ENABLE_PWR_DROP_ERR__WIDTH 1 +#define RESTART__ENABLE_PWR_DROP_ERR__MASK 0x00000040U +#define RESTART__ENABLE_PWR_DROP_ERR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RESTART__ENABLE_PWR_DROP_ERR__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RESTART__ENABLE_PWR_DROP_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RESTART__ENABLE_PWR_DROP_ERR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RESTART__ENABLE_PWR_DROP_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RESTART__ENABLE_PWR_DROP_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field pwrdrop_lgfirpwr_delta */ +#define RESTART__PWRDROP_LGFIRPWR_DELTA__SHIFT 7 +#define RESTART__PWRDROP_LGFIRPWR_DELTA__WIDTH 5 +#define RESTART__PWRDROP_LGFIRPWR_DELTA__MASK 0x00000f80U +#define RESTART__PWRDROP_LGFIRPWR_DELTA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f80U) >> 7) +#define RESTART__PWRDROP_LGFIRPWR_DELTA__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000f80U) +#define RESTART__PWRDROP_LGFIRPWR_DELTA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00000f80U) +#define RESTART__PWRDROP_LGFIRPWR_DELTA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000f80U))) + +/* macros for field ofdm_cck_rssi_bias */ +#define RESTART__OFDM_CCK_RSSI_BIAS__SHIFT 12 +#define RESTART__OFDM_CCK_RSSI_BIAS__WIDTH 6 +#define RESTART__OFDM_CCK_RSSI_BIAS__MASK 0x0003f000U +#define RESTART__OFDM_CCK_RSSI_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define RESTART__OFDM_CCK_RSSI_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define RESTART__OFDM_CCK_RSSI_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define RESTART__OFDM_CCK_RSSI_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field ant_fast_div_gc_limit */ +#define RESTART__ANT_FAST_DIV_GC_LIMIT__SHIFT 18 +#define RESTART__ANT_FAST_DIV_GC_LIMIT__WIDTH 3 +#define RESTART__ANT_FAST_DIV_GC_LIMIT__MASK 0x001c0000U +#define RESTART__ANT_FAST_DIV_GC_LIMIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x001c0000U) >> 18) +#define RESTART__ANT_FAST_DIV_GC_LIMIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x001c0000U) +#define RESTART__ANT_FAST_DIV_GC_LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define RESTART__ANT_FAST_DIV_GC_LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field enable_ant_fast_div_m2flag */ +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__SHIFT 21 +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__WIDTH 1 +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MASK 0x00200000U +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field weak_rssi_vote_thr */ +#define RESTART__WEAK_RSSI_VOTE_THR__SHIFT 22 +#define RESTART__WEAK_RSSI_VOTE_THR__WIDTH 7 +#define RESTART__WEAK_RSSI_VOTE_THR__MASK 0x1fc00000U +#define RESTART__WEAK_RSSI_VOTE_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x1fc00000U) >> 22) +#define RESTART__WEAK_RSSI_VOTE_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x1fc00000U) +#define RESTART__WEAK_RSSI_VOTE_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x1fc00000U) +#define RESTART__WEAK_RSSI_VOTE_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x1fc00000U))) + +/* macros for field enable_pwr_drop_err_cck */ +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__SHIFT 29 +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__WIDTH 1 +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__MASK 0x20000000U +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field disable_dc_restart */ +#define RESTART__DISABLE_DC_RESTART__SHIFT 30 +#define RESTART__DISABLE_DC_RESTART__WIDTH 1 +#define RESTART__DISABLE_DC_RESTART__MASK 0x40000000U +#define RESTART__DISABLE_DC_RESTART__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RESTART__DISABLE_DC_RESTART__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RESTART__DISABLE_DC_RESTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RESTART__DISABLE_DC_RESTART__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RESTART__DISABLE_DC_RESTART__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RESTART__DISABLE_DC_RESTART__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field restart_mode_bw40 */ +#define RESTART__RESTART_MODE_BW40__SHIFT 31 +#define RESTART__RESTART_MODE_BW40__WIDTH 1 +#define RESTART__RESTART_MODE_BW40__MASK 0x80000000U +#define RESTART__RESTART_MODE_BW40__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RESTART__RESTART_MODE_BW40__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RESTART__RESTART_MODE_BW40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RESTART__RESTART_MODE_BW40__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RESTART__RESTART_MODE_BW40__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RESTART__RESTART_MODE_BW40__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RESTART__TYPE u_int32_t +#define RESTART__READ 0xffffffffU +#define RESTART__WRITE 0xffffffffU + +#endif /* __RESTART_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_restart */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_RESTART__NUM 1 + +/* macros for BlueprintGlobalNameSpace::multichain_gain_ctrl */ +#ifndef __MULTICHAIN_GAIN_CTRL_MACRO__ +#define __MULTICHAIN_GAIN_CTRL_MACRO__ + +/* macros for field quickdrop_low */ +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__SHIFT 0 +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__WIDTH 8 +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__MASK 0x000000ffU +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field enable_check_strong_ant */ +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__SHIFT 8 +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__MASK 0x00000100U +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field ant_fast_div_bias */ +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__SHIFT 9 +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WIDTH 6 +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK 0x00007e00U +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007e00U) >> 9) +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00007e00U) +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00007e00U) +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00007e00U))) + +/* macros for field cap_gain_ratio_SNR */ +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__SHIFT 15 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__WIDTH 6 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__MASK 0x001f8000U +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f8000U) >> 15) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x001f8000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x001f8000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x001f8000U))) + +/* macros for field cap_gain_ratio_ena */ +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__SHIFT 21 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__MASK 0x00200000U +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field cap_gain_ratio_mode */ +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__SHIFT 22 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__MASK 0x00400000U +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field enable_ant_sw_rx_prot */ +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SHIFT 23 +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__MASK 0x00800000U +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field enable_ant_div_lnadiv */ +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__SHIFT 24 +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MASK 0x01000000U +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field ant_div_alt_lnaconf */ +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__SHIFT 25 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WIDTH 2 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK 0x06000000U +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field ant_div_main_lnaconf */ +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__SHIFT 27 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WIDTH 2 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK 0x18000000U +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(src) \ + (((u_int32_t)(src)\ + & 0x18000000U) >> 27) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x18000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((u_int32_t)(src) <<\ + 27) & 0x18000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x18000000U))) + +/* macros for field ant_div_alt_gaintb */ +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__SHIFT 29 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK 0x20000000U +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field ant_div_main_gaintb */ +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__SHIFT 30 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK 0x40000000U +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define MULTICHAIN_GAIN_CTRL__TYPE u_int32_t +#define MULTICHAIN_GAIN_CTRL__READ 0x7fffffffU +#define MULTICHAIN_GAIN_CTRL__WRITE 0x7fffffffU + +#endif /* __MULTICHAIN_GAIN_CTRL_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_multichain_gain_ctrl */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_MULTICHAIN_GAIN_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_1 */ +#ifndef __EXT_CHAN_PWR_THR_1_MACRO__ +#define __EXT_CHAN_PWR_THR_1_MACRO__ + +/* macros for field thresh62_ext */ +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__SHIFT 0 +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__WIDTH 8 +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__MASK 0x000000ffU +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field ant_div_alt_ant_minGainIdx */ +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__SHIFT 8 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__WIDTH 8 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__MASK 0x0000ff00U +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field ant_div_alt_ant_deltaGainIdx */ +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__SHIFT 16 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__WIDTH 5 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__MASK 0x001f0000U +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) + +/* macros for field ant_div_alt_ant_deltaNF */ +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__SHIFT 21 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__WIDTH 6 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__MASK 0x07e00000U +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__READ(src) \ + (((u_int32_t)(src)\ + & 0x07e00000U) >> 21) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x07e00000U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x07e00000U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x07e00000U))) +#define EXT_CHAN_PWR_THR_1__TYPE u_int32_t +#define EXT_CHAN_PWR_THR_1__READ 0x07ffffffU +#define EXT_CHAN_PWR_THR_1__WRITE 0x07ffffffU + +#endif /* __EXT_CHAN_PWR_THR_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_ext_chan_pwr_thr_1 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_EXT_CHAN_PWR_THR_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_detect_win */ +#ifndef __EXT_CHAN_DETECT_WIN_MACRO__ +#define __EXT_CHAN_DETECT_WIN_MACRO__ + +/* macros for field det_diff_win_weak */ +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__SHIFT 0 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__WIDTH 4 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__MASK 0x0000000fU +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field det_diff_win_weak_low */ +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__SHIFT 4 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__WIDTH 4 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__MASK 0x000000f0U +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field det_diff_win_weak_cck */ +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__SHIFT 8 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__WIDTH 5 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__MASK 0x00001f00U +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) + +/* macros for field det_20h_count */ +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__SHIFT 13 +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__WIDTH 3 +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__MASK 0x0000e000U +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000e000U) >> 13) +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0000e000U) +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0000e000U))) + +/* macros for field det_ext_blk_count */ +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__SHIFT 16 +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__WIDTH 3 +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__MASK 0x00070000U +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field weak_sig_thr_cck_ext */ +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__SHIFT 19 +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__WIDTH 6 +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__MASK 0x01f80000U +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f80000U) >> 19) +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x01f80000U) +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f80000U) | (((u_int32_t)(src) <<\ + 19) & 0x01f80000U) +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x01f80000U))) + +/* macros for field det_diff_win_thresh */ +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__SHIFT 25 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__WIDTH 4 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__MASK 0x1e000000U +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x1e000000U) >> 25) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x1e000000U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x1e000000U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x1e000000U))) +#define EXT_CHAN_DETECT_WIN__TYPE u_int32_t +#define EXT_CHAN_DETECT_WIN__READ 0x1fffffffU +#define EXT_CHAN_DETECT_WIN__WRITE 0x1fffffffU + +#endif /* __EXT_CHAN_DETECT_WIN_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_ext_chan_detect_win */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_EXT_CHAN_DETECT_WIN__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pwr_thr_20_40_det */ +#ifndef __PWR_THR_20_40_DET_MACRO__ +#define __PWR_THR_20_40_DET_MACRO__ + +/* macros for field pwrdiff40_thrstr */ +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__SHIFT 0 +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__WIDTH 5 +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__MASK 0x0000001fU +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field blocker40_max */ +#define PWR_THR_20_40_DET__BLOCKER40_MAX__SHIFT 5 +#define PWR_THR_20_40_DET__BLOCKER40_MAX__WIDTH 6 +#define PWR_THR_20_40_DET__BLOCKER40_MAX__MASK 0x000007e0U +#define PWR_THR_20_40_DET__BLOCKER40_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x000007e0U) >> 5) +#define PWR_THR_20_40_DET__BLOCKER40_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000007e0U) +#define PWR_THR_20_40_DET__BLOCKER40_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000007e0U) +#define PWR_THR_20_40_DET__BLOCKER40_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000007e0U))) + +/* macros for field det40_pwrstep_max */ +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__SHIFT 11 +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__WIDTH 5 +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__MASK 0x0000f800U +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f800U) >> 11) +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x0000f800U) +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0000f800U) +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0000f800U))) + +/* macros for field det40_thr_snr */ +#define PWR_THR_20_40_DET__DET40_THR_SNR__SHIFT 16 +#define PWR_THR_20_40_DET__DET40_THR_SNR__WIDTH 8 +#define PWR_THR_20_40_DET__DET40_THR_SNR__MASK 0x00ff0000U +#define PWR_THR_20_40_DET__DET40_THR_SNR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define PWR_THR_20_40_DET__DET40_THR_SNR__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define PWR_THR_20_40_DET__DET40_THR_SNR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PWR_THR_20_40_DET__DET40_THR_SNR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field det40_pri_bias */ +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__SHIFT 24 +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__WIDTH 5 +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__MASK 0x1f000000U +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f000000U) >> 24) +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x1f000000U) +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x1f000000U) +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x1f000000U))) + +/* macros for field pwrstep40_ena */ +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__SHIFT 29 +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__WIDTH 1 +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__MASK 0x20000000U +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field lowsnr40_ena */ +#define PWR_THR_20_40_DET__LOWSNR40_ENA__SHIFT 30 +#define PWR_THR_20_40_DET__LOWSNR40_ENA__WIDTH 1 +#define PWR_THR_20_40_DET__LOWSNR40_ENA__MASK 0x40000000U +#define PWR_THR_20_40_DET__LOWSNR40_ENA__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define PWR_THR_20_40_DET__LOWSNR40_ENA__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define PWR_THR_20_40_DET__LOWSNR40_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define PWR_THR_20_40_DET__LOWSNR40_ENA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define PWR_THR_20_40_DET__LOWSNR40_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define PWR_THR_20_40_DET__LOWSNR40_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define PWR_THR_20_40_DET__TYPE u_int32_t +#define PWR_THR_20_40_DET__READ 0x7fffffffU +#define PWR_THR_20_40_DET__WRITE 0x7fffffffU + +#endif /* __PWR_THR_20_40_DET_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_pwr_thr_20_40_det */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_PWR_THR_20_40_DET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rifs_srch */ +#ifndef __RIFS_SRCH_MACRO__ +#define __RIFS_SRCH_MACRO__ + +/* macros for field init_gain_dB_offset */ +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__SHIFT 8 +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__WIDTH 8 +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__MASK 0x0000ff00U +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field rifs_init_delay */ +#define RIFS_SRCH__RIFS_INIT_DELAY__SHIFT 16 +#define RIFS_SRCH__RIFS_INIT_DELAY__WIDTH 10 +#define RIFS_SRCH__RIFS_INIT_DELAY__MASK 0x03ff0000U +#define RIFS_SRCH__RIFS_INIT_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x03ff0000U) >> 16) +#define RIFS_SRCH__RIFS_INIT_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x03ff0000U) +#define RIFS_SRCH__RIFS_INIT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x03ff0000U) +#define RIFS_SRCH__RIFS_INIT_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x03ff0000U))) + +/* macros for field rifs_disable_pwrlow_gc */ +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__SHIFT 26 +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__WIDTH 1 +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__MASK 0x04000000U +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field rifs_disable_cck_det */ +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__SHIFT 27 +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__WIDTH 1 +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__MASK 0x08000000U +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) +#define RIFS_SRCH__TYPE u_int32_t +#define RIFS_SRCH__READ 0x0fffff00U +#define RIFS_SRCH__WRITE 0x0fffff00U + +#endif /* __RIFS_SRCH_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_rifs_srch */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_RIFS_SRCH__NUM 1 + +/* macros for BlueprintGlobalNameSpace::peak_det_ctrl_1 */ +#ifndef __PEAK_DET_CTRL_1_MACRO__ +#define __PEAK_DET_CTRL_1_MACRO__ + +/* macros for field use_oc_gain_table */ +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__SHIFT 0 +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__WIDTH 1 +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__MASK 0x00000001U +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field use_peak_det */ +#define PEAK_DET_CTRL_1__USE_PEAK_DET__SHIFT 1 +#define PEAK_DET_CTRL_1__USE_PEAK_DET__WIDTH 1 +#define PEAK_DET_CTRL_1__USE_PEAK_DET__MASK 0x00000002U +#define PEAK_DET_CTRL_1__USE_PEAK_DET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PEAK_DET_CTRL_1__USE_PEAK_DET__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PEAK_DET_CTRL_1__USE_PEAK_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PEAK_DET_CTRL_1__USE_PEAK_DET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PEAK_DET_CTRL_1__USE_PEAK_DET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PEAK_DET_CTRL_1__USE_PEAK_DET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field peak_det_win_len */ +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__SHIFT 2 +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__WIDTH 6 +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__MASK 0x000000fcU +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000fcU) >> 2) +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x000000fcU) +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000fcU) | (((u_int32_t)(src) <<\ + 2) & 0x000000fcU) +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x000000fcU))) + +/* macros for field peak_det_tally_thr_low */ +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__SHIFT 8 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__WIDTH 5 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__MASK 0x00001f00U +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) + +/* macros for field peak_det_tally_thr_med */ +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__SHIFT 13 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__WIDTH 5 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__MASK 0x0003e000U +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003e000U) >> 13) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0003e000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0003e000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0003e000U))) + +/* macros for field peak_det_tally_thr_high */ +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__SHIFT 18 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__WIDTH 5 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__MASK 0x007c0000U +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x007c0000U) >> 18) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x007c0000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x007c0000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x007c0000U))) + +/* macros for field peak_det_settling */ +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__SHIFT 23 +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__WIDTH 7 +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__MASK 0x3f800000U +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f800000U) >> 23) +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x3f800000U) +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x3f800000U) +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x3f800000U))) + +/* macros for field pwd_pkdet_during_cal */ +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__SHIFT 30 +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__WIDTH 1 +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__MASK 0x40000000U +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field pwd_pkdet_during_rx */ +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__SHIFT 31 +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__WIDTH 1 +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__MASK 0x80000000U +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define PEAK_DET_CTRL_1__TYPE u_int32_t +#define PEAK_DET_CTRL_1__READ 0xffffffffU +#define PEAK_DET_CTRL_1__WRITE 0xffffffffU + +#endif /* __PEAK_DET_CTRL_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_peak_det_ctrl_1 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_PEAK_DET_CTRL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::peak_det_ctrl_2 */ +#ifndef __PEAK_DET_CTRL_2_MACRO__ +#define __PEAK_DET_CTRL_2_MACRO__ + +/* macros for field rfsat_2_add_rfgain_del */ +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__SHIFT 0 +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__WIDTH 10 +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__MASK 0x000003ffU +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field rf_gain_drop_db_low */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__SHIFT 10 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__MASK 0x00007c00U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field rf_gain_drop_db_med */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__SHIFT 15 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__MASK 0x000f8000U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field rf_gain_drop_db_high */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__SHIFT 20 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__MASK 0x01f00000U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field rf_gain_drop_db_non */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__SHIFT 25 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__MASK 0x3e000000U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +//#define PEAK_DET_CTRL_2__TYPE u_int32_t +//#define PEAK_DET_CTRL_2__READ 0x3fffffffU +//#define PEAK_DET_CTRL_2__WRITE 0x3fffffffU + +#endif /* __PEAK_DET_CTRL_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_peak_det_ctrl_2 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_PEAK_DET_CTRL_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_gain_bounds_1 */ +#ifndef __RX_GAIN_BOUNDS_1_MACRO__ +#define __RX_GAIN_BOUNDS_1_MACRO__ + +/* macros for field rx_max_mb_gain */ +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__SHIFT 0 +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__WIDTH 8 +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__MASK 0x000000ffU +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field rx_max_rf_gain_ref */ +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__SHIFT 8 +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__WIDTH 8 +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__MASK 0x0000ff00U +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field rx_max_rf_gain */ +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__SHIFT 16 +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__WIDTH 8 +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__MASK 0x00ff0000U +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field rx_ocgain_sel_2G */ +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__SHIFT 24 +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__WIDTH 1 +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__MASK 0x01000000U +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field rx_ocgain_sel_5G */ +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__SHIFT 25 +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__WIDTH 1 +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__MASK 0x02000000U +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) +#define RX_GAIN_BOUNDS_1__TYPE u_int32_t +#define RX_GAIN_BOUNDS_1__READ 0x03ffffffU +#define RX_GAIN_BOUNDS_1__WRITE 0x03ffffffU + +#endif /* __RX_GAIN_BOUNDS_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_rx_gain_bounds_1 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_RX_GAIN_BOUNDS_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_gain_bounds_2 */ +#ifndef __RX_GAIN_BOUNDS_2_MACRO__ +#define __RX_GAIN_BOUNDS_2_MACRO__ + +/* macros for field gc_rssi_low_db */ +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__SHIFT 0 +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__WIDTH 8 +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__MASK 0x000000ffU +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field rf_gain_ref_base_addr */ +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__SHIFT 8 +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__WIDTH 8 +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__MASK 0x0000ff00U +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field rf_gain_base_addr */ +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__SHIFT 16 +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__WIDTH 8 +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__MASK 0x00ff0000U +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field rf_gain_div_base_addr */ +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__SHIFT 24 +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__WIDTH 8 +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__MASK 0xff000000U +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define RX_GAIN_BOUNDS_2__TYPE u_int32_t +#define RX_GAIN_BOUNDS_2__READ 0xffffffffU +#define RX_GAIN_BOUNDS_2__WRITE 0xffffffffU + +#endif /* __RX_GAIN_BOUNDS_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_rx_gain_bounds_2 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_RX_GAIN_BOUNDS_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::peak_det_cal_ctrl */ +#ifndef __PEAK_DET_CAL_CTRL_MACRO__ +#define __PEAK_DET_CAL_CTRL_MACRO__ + +/* macros for field pkdet_cal_win_thr */ +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__SHIFT 0 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__WIDTH 6 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__MASK 0x0000003fU +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field pkdet_cal_bias */ +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__SHIFT 6 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__WIDTH 6 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__MASK 0x00000fc0U +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field pkdet_cal_meas_time_sel */ +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__SHIFT 12 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__WIDTH 2 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__MASK 0x00003000U +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003000U) >> 12) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00003000U) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((u_int32_t)(src) <<\ + 12) & 0x00003000U) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00003000U))) +#define PEAK_DET_CAL_CTRL__TYPE u_int32_t +#define PEAK_DET_CAL_CTRL__READ 0x00003fffU +#define PEAK_DET_CAL_CTRL__WRITE 0x00003fffU + +#endif /* __PEAK_DET_CAL_CTRL_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_peak_det_cal_ctrl */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_PEAK_DET_CAL_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_ctrl */ +#ifndef __AGC_DIG_DC_CTRL_MACRO__ +#define __AGC_DIG_DC_CTRL_MACRO__ + +/* macros for field use_dig_dc */ +#define AGC_DIG_DC_CTRL__USE_DIG_DC__SHIFT 0 +#define AGC_DIG_DC_CTRL__USE_DIG_DC__WIDTH 1 +#define AGC_DIG_DC_CTRL__USE_DIG_DC__MASK 0x00000001U +#define AGC_DIG_DC_CTRL__USE_DIG_DC__READ(src) (u_int32_t)(src) & 0x00000001U +#define AGC_DIG_DC_CTRL__USE_DIG_DC__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define AGC_DIG_DC_CTRL__USE_DIG_DC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define AGC_DIG_DC_CTRL__USE_DIG_DC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define AGC_DIG_DC_CTRL__USE_DIG_DC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define AGC_DIG_DC_CTRL__USE_DIG_DC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dig_dc_scale_bias */ +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__SHIFT 1 +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__WIDTH 3 +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__MASK 0x0000000eU +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field dig_dc_correct_cap */ +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__SHIFT 4 +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__WIDTH 6 +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__MASK 0x000003f0U +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field dig_dc_switch_cck */ +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__SHIFT 10 +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__WIDTH 1 +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__MASK 0x00000400U +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field dig_dc_mixer_sel_mask */ +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__SHIFT 16 +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__WIDTH 16 +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__MASK 0xffff0000U +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define AGC_DIG_DC_CTRL__TYPE u_int32_t +#define AGC_DIG_DC_CTRL__READ 0xffff07ffU +#define AGC_DIG_DC_CTRL__WRITE 0xffff07ffU + +#endif /* __AGC_DIG_DC_CTRL_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_agc_dig_dc_ctrl */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_AGC_DIG_DC_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bt_coex */ +#ifndef __BT_COEX_MACRO__ +#define __BT_COEX_MACRO__ + +/* macros for field enable_bt_coex */ +#define BT_COEX__ENABLE_BT_COEX__SHIFT 0 +#define BT_COEX__ENABLE_BT_COEX__WIDTH 1 +#define BT_COEX__ENABLE_BT_COEX__MASK 0x00000001U +#define BT_COEX__ENABLE_BT_COEX__READ(src) (u_int32_t)(src) & 0x00000001U +#define BT_COEX__ENABLE_BT_COEX__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define BT_COEX__ENABLE_BT_COEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BT_COEX__ENABLE_BT_COEX__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define BT_COEX__ENABLE_BT_COEX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BT_COEX__ENABLE_BT_COEX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field wlan_bt_priority */ +#define BT_COEX__WLAN_BT_PRIORITY__SHIFT 1 +#define BT_COEX__WLAN_BT_PRIORITY__WIDTH 1 +#define BT_COEX__WLAN_BT_PRIORITY__MASK 0x00000002U +#define BT_COEX__WLAN_BT_PRIORITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define BT_COEX__WLAN_BT_PRIORITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define BT_COEX__WLAN_BT_PRIORITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define BT_COEX__WLAN_BT_PRIORITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define BT_COEX__WLAN_BT_PRIORITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define BT_COEX__WLAN_BT_PRIORITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field rfsat_restart_thresh */ +#define BT_COEX__RFSAT_RESTART_THRESH__SHIFT 2 +#define BT_COEX__RFSAT_RESTART_THRESH__WIDTH 2 +#define BT_COEX__RFSAT_RESTART_THRESH__MASK 0x0000000cU +#define BT_COEX__RFSAT_RESTART_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define BT_COEX__RFSAT_RESTART_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define BT_COEX__RFSAT_RESTART_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define BT_COEX__RFSAT_RESTART_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field enable_rfsat_restart */ +#define BT_COEX__ENABLE_RFSAT_RESTART__SHIFT 4 +#define BT_COEX__ENABLE_RFSAT_RESTART__WIDTH 1 +#define BT_COEX__ENABLE_RFSAT_RESTART__MASK 0x00000010U +#define BT_COEX__ENABLE_RFSAT_RESTART__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define BT_COEX__ENABLE_RFSAT_RESTART__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define BT_COEX__ENABLE_RFSAT_RESTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define BT_COEX__ENABLE_RFSAT_RESTART__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define BT_COEX__ENABLE_RFSAT_RESTART__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define BT_COEX__ENABLE_RFSAT_RESTART__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) +#define BT_COEX__TYPE u_int32_t +#define BT_COEX__READ 0x0000001fU +#define BT_COEX__WRITE 0x0000001fU + +#endif /* __BT_COEX_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_bt_coex */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BT_COEX__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rssi_b0 */ +#ifndef __RSSI_B0_MACRO__ +#define __RSSI_B0_MACRO__ + +/* macros for field rssi_0 */ +#define RSSI_B0__RSSI_0__SHIFT 0 +#define RSSI_B0__RSSI_0__WIDTH 8 +#define RSSI_B0__RSSI_0__MASK 0x000000ffU +#define RSSI_B0__RSSI_0__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field rssi_ext_0 */ +#define RSSI_B0__RSSI_EXT_0__SHIFT 8 +#define RSSI_B0__RSSI_EXT_0__WIDTH 8 +#define RSSI_B0__RSSI_EXT_0__MASK 0x0000ff00U +#define RSSI_B0__RSSI_EXT_0__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define RSSI_B0__TYPE u_int32_t +#define RSSI_B0__READ 0x0000ffffU + +#endif /* __RSSI_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_rssi_b0 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_RSSI_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_est_cck_report_b0 */ +#ifndef __SPUR_EST_CCK_REPORT_B0_MACRO__ +#define __SPUR_EST_CCK_REPORT_B0_MACRO__ + +/* macros for field spur_est_sd_i_0_cck */ +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__SHIFT 0 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__MASK 0x000000ffU +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field spur_est_sd_q_0_cck */ +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__SHIFT 8 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__MASK 0x0000ff00U +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field spur_est_i_0_cck */ +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__SHIFT 16 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__MASK 0x00ff0000U +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) + +/* macros for field spur_est_q_0_cck */ +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__SHIFT 24 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__MASK 0xff000000U +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define SPUR_EST_CCK_REPORT_B0__TYPE u_int32_t +#define SPUR_EST_CCK_REPORT_B0__READ 0xffffffffU + +#endif /* __SPUR_EST_CCK_REPORT_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_spur_est_cck_report_b0 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_SPUR_EST_CCK_REPORT_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b0 */ +#ifndef __AGC_DIG_DC_STATUS_I_B0_MACRO__ +#define __AGC_DIG_DC_STATUS_I_B0_MACRO__ + +/* macros for field dig_dc_C1_res_i_0 */ +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__SHIFT 0 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_i_0 */ +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__SHIFT 9 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_i_0 */ +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__SHIFT 18 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_I_B0__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_I_B0__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_I_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_agc_dig_dc_status_i_b0 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b0 */ +#ifndef __AGC_DIG_DC_STATUS_Q_B0_MACRO__ +#define __AGC_DIG_DC_STATUS_Q_B0_MACRO__ + +/* macros for field dig_dc_C1_res_q_0 */ +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__SHIFT 0 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_q_0 */ +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__SHIFT 9 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_q_0 */ +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__SHIFT 18 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_Q_B0__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_Q_B0__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_Q_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_agc_dig_dc_status_q_b0 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_sig_detect */ +#ifndef __BBB_SIG_DETECT_MACRO__ +#define __BBB_SIG_DETECT_MACRO__ + +/* macros for field weak_sig_thr_cck */ +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__SHIFT 0 +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__WIDTH 6 +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__MASK 0x0000003fU +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field ant_switch_time */ +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__SHIFT 6 +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__WIDTH 7 +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__MASK 0x00001fc0U +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001fc0U) >> 6) +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00001fc0U) +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00001fc0U) +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00001fc0U))) + +/* macros for field enable_ant_fast_div */ +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SHIFT 13 +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__WIDTH 1 +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MASK 0x00002000U +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field lb_alpha_128_cck */ +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__SHIFT 14 +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__WIDTH 1 +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__MASK 0x00004000U +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field lb_rx_enable_cck */ +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__SHIFT 15 +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__WIDTH 1 +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__MASK 0x00008000U +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field cyc32_coarse_dc_est_cck */ +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__SHIFT 16 +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__WIDTH 1 +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__MASK 0x00010000U +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field cyc64_coarse_dc_est_cck */ +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__SHIFT 17 +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__WIDTH 1 +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__MASK 0x00020000U +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field enable_coarse_dc_cck */ +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__SHIFT 18 +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__WIDTH 1 +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__MASK 0x00040000U +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field cyc256_fine_dc_est_cck */ +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__SHIFT 19 +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__WIDTH 1 +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__MASK 0x00080000U +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field enable_fine_dc_cck */ +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__SHIFT 20 +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__WIDTH 1 +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__MASK 0x00100000U +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field delay_start_sync_cck */ +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__SHIFT 21 +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__WIDTH 1 +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__MASK 0x00200000U +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field use_dc_est_during_srch */ +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__SHIFT 22 +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__WIDTH 1 +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__MASK 0x00400000U +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field enable_barker_two_phase */ +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__SHIFT 31 +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__WIDTH 1 +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__MASK 0x80000000U +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +//#define BBB_SIG_DETECT__TYPE u_int32_t +//#define BBB_SIG_DETECT__READ 0x807fffffU +//#define BBB_SIG_DETECT__WRITE 0x807fffffU + +#endif /* __BBB_SIG_DETECT_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_bbb_sig_detect */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BBB_SIG_DETECT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_dagc_ctrl */ +#ifndef __BBB_DAGC_CTRL_MACRO__ +#define __BBB_DAGC_CTRL_MACRO__ + +/* macros for field enable_dagc_cck */ +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__SHIFT 0 +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__WIDTH 1 +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__MASK 0x00000001U +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dagc_target_pwr_cck */ +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__SHIFT 1 +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__WIDTH 8 +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__MASK 0x000001feU +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000001feU) +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((u_int32_t)(src) <<\ + 1) & 0x000001feU) +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000001feU))) + +/* macros for field enable_barker_rssi_thr */ +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__SHIFT 9 +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__WIDTH 1 +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__MASK 0x00000200U +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field barker_rssi_thr */ +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__SHIFT 10 +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__WIDTH 7 +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__MASK 0x0001fc00U +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fc00U) >> 10) +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0001fc00U) +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0001fc00U) +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0001fc00U))) + +/* macros for field enable_firstep_sel */ +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__SHIFT 17 +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__WIDTH 1 +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__MASK 0x00020000U +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field firstep_2 */ +#define BBB_DAGC_CTRL__FIRSTEP_2__SHIFT 18 +#define BBB_DAGC_CTRL__FIRSTEP_2__WIDTH 6 +#define BBB_DAGC_CTRL__FIRSTEP_2__MASK 0x00fc0000U +#define BBB_DAGC_CTRL__FIRSTEP_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define BBB_DAGC_CTRL__FIRSTEP_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define BBB_DAGC_CTRL__FIRSTEP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define BBB_DAGC_CTRL__FIRSTEP_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field firstep_count_lgmax */ +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__SHIFT 24 +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__WIDTH 4 +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__MASK 0x0f000000U +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) + +/* macros for field force_rx_chain_cck_0 */ +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__SHIFT 28 +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__WIDTH 2 +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__MASK 0x30000000U +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x30000000U) >> 28) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x30000000U) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) + +/* macros for field force_rx_chain_cck_1 */ +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__SHIFT 30 +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__WIDTH 2 +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__MASK 0xc0000000U +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define BBB_DAGC_CTRL__TYPE u_int32_t +#define BBB_DAGC_CTRL__READ 0xffffffffU +#define BBB_DAGC_CTRL__WRITE 0xffffffffU + +#endif /* __BBB_DAGC_CTRL_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_bbb_dagc_ctrl */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BBB_DAGC_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iqcorr_ctrl_cck */ +#ifndef __IQCORR_CTRL_CCK_MACRO__ +#define __IQCORR_CTRL_CCK_MACRO__ + +/* macros for field iqcorr_q_q_coff_cck */ +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__SHIFT 0 +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__WIDTH 5 +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__MASK 0x0000001fU +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field iqcorr_q_i_coff_cck */ +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__SHIFT 5 +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__WIDTH 6 +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__MASK 0x000007e0U +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x000007e0U) >> 5) +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000007e0U) +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000007e0U) +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000007e0U))) + +/* macros for field enable_iqcorr_cck */ +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__SHIFT 11 +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__WIDTH 1 +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__MASK 0x00000800U +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field rxcal_meas_time_sel */ +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__SHIFT 12 +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__WIDTH 2 +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__MASK 0x00003000U +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003000U) >> 12) +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00003000U) +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((u_int32_t)(src) <<\ + 12) & 0x00003000U) +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00003000U))) + +/* macros for field clcal_meas_time_sel */ +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__SHIFT 14 +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__WIDTH 2 +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__MASK 0x0000c000U +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field cf_clc_init_rfgain */ +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__SHIFT 16 +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__WIDTH 5 +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__MASK 0x001f0000U +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) +#define IQCORR_CTRL_CCK__TYPE u_int32_t +#define IQCORR_CTRL_CCK__READ 0x001fffffU +#define IQCORR_CTRL_CCK__WRITE 0x001fffffU + +#endif /* __IQCORR_CTRL_CCK_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_iqcorr_ctrl_cck */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_IQCORR_CTRL_CCK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cck_spur_mit */ +#ifndef __CCK_SPUR_MIT_MACRO__ +#define __CCK_SPUR_MIT_MACRO__ + +/* macros for field use_cck_spur_mit */ +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__SHIFT 0 +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__WIDTH 1 +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__MASK 0x00000001U +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field spur_rssi_thr */ +#define CCK_SPUR_MIT__SPUR_RSSI_THR__SHIFT 1 +#define CCK_SPUR_MIT__SPUR_RSSI_THR__WIDTH 8 +#define CCK_SPUR_MIT__SPUR_RSSI_THR__MASK 0x000001feU +#define CCK_SPUR_MIT__SPUR_RSSI_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) +#define CCK_SPUR_MIT__SPUR_RSSI_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000001feU) +#define CCK_SPUR_MIT__SPUR_RSSI_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((u_int32_t)(src) <<\ + 1) & 0x000001feU) +#define CCK_SPUR_MIT__SPUR_RSSI_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000001feU))) + +/* macros for field cck_spur_freq */ +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__SHIFT 9 +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__WIDTH 20 +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__MASK 0x1ffffe00U +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x1ffffe00U) >> 9) +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x1ffffe00U) +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1ffffe00U) | (((u_int32_t)(src) <<\ + 9) & 0x1ffffe00U) +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x1ffffe00U))) + +/* macros for field spur_filter_type */ +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__SHIFT 29 +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__WIDTH 2 +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__MASK 0x60000000U +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__READ(src) \ + (((u_int32_t)(src)\ + & 0x60000000U) >> 29) +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x60000000U) +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x60000000U) | (((u_int32_t)(src) <<\ + 29) & 0x60000000U) +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x60000000U))) +#define CCK_SPUR_MIT__TYPE u_int32_t +#define CCK_SPUR_MIT__READ 0x7fffffffU +#define CCK_SPUR_MIT__WRITE 0x7fffffffU + +#endif /* __CCK_SPUR_MIT_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_cck_spur_mit */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_CCK_SPUR_MIT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::mrc_cck_ctrl */ +#ifndef __MRC_CCK_CTRL_MACRO__ +#define __MRC_CCK_CTRL_MACRO__ + +/* macros for field bbb_mrc_en */ +#define MRC_CCK_CTRL__BBB_MRC_EN__SHIFT 0 +#define MRC_CCK_CTRL__BBB_MRC_EN__WIDTH 1 +#define MRC_CCK_CTRL__BBB_MRC_EN__MASK 0x00000001U +#define MRC_CCK_CTRL__BBB_MRC_EN__READ(src) (u_int32_t)(src) & 0x00000001U +#define MRC_CCK_CTRL__BBB_MRC_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MRC_CCK_CTRL__BBB_MRC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MRC_CCK_CTRL__BBB_MRC_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MRC_CCK_CTRL__BBB_MRC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MRC_CCK_CTRL__BBB_MRC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field agcdp_cck_mrc_mux_reg */ +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__SHIFT 1 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__WIDTH 1 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__MASK 0x00000002U +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field agcdp_cck_pd_accu_thr_hi */ +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__SHIFT 2 +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__WIDTH 3 +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__MASK 0x0000001cU +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field agcdp_cck_pd_accu_thr_low */ +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__SHIFT 5 +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__WIDTH 3 +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__MASK 0x000000e0U +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field agcdp_cck_barker_rssi_thr */ +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__SHIFT 8 +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__WIDTH 4 +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__MASK 0x00000f00U +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field agcdp_cck_mrc_bk_thr_hi */ +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__SHIFT 12 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__WIDTH 5 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__MASK 0x0001f000U +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field agcdp_cck_mrc_bk_thr_low */ +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__SHIFT 17 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__WIDTH 5 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__MASK 0x003e0000U +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field agcdp_cck_min_value */ +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__SHIFT 22 +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__WIDTH 6 +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__MASK 0x0fc00000U +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fc00000U) >> 22) +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x0fc00000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x0fc00000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x0fc00000U))) +#define MRC_CCK_CTRL__TYPE u_int32_t +#define MRC_CCK_CTRL__READ 0x0fffffffU +#define MRC_CCK_CTRL__WRITE 0x0fffffffU + +#endif /* __MRC_CCK_CTRL_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_mrc_cck_ctrl */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_MRC_CCK_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_ocgain */ +#ifndef __RX_OCGAIN_MACRO__ +#define __RX_OCGAIN_MACRO__ + +/* macros for field gain_entry */ +#define RX_OCGAIN__GAIN_ENTRY__SHIFT 0 +#define RX_OCGAIN__GAIN_ENTRY__WIDTH 32 +#define RX_OCGAIN__GAIN_ENTRY__MASK 0xffffffffU +#define RX_OCGAIN__GAIN_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define RX_OCGAIN__GAIN_ENTRY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define RX_OCGAIN__GAIN_ENTRY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define RX_OCGAIN__TYPE u_int32_t +#define RX_OCGAIN__WRITE 0x00000000U + +#endif /* __RX_OCGAIN_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_rx_ocgain */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_RX_OCGAIN__NUM 128 + +/* macros for BlueprintGlobalNameSpace::D2_chip_id */ +#ifndef __D2_CHIP_ID_MACRO__ +#define __D2_CHIP_ID_MACRO__ + +/* macros for field old_id */ +#define D2_CHIP_ID__OLD_ID__SHIFT 0 +#define D2_CHIP_ID__OLD_ID__WIDTH 8 +#define D2_CHIP_ID__OLD_ID__MASK 0x000000ffU +#define D2_CHIP_ID__OLD_ID__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field id */ +#define D2_CHIP_ID__ID__SHIFT 8 +#define D2_CHIP_ID__ID__WIDTH 24 +#define D2_CHIP_ID__ID__MASK 0xffffff00U +#define D2_CHIP_ID__ID__READ(src) (((u_int32_t)(src) & 0xffffff00U) >> 8) +#define D2_CHIP_ID__TYPE u_int32_t +#define D2_CHIP_ID__READ 0xffffffffU + +#endif /* __D2_CHIP_ID_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_D2_chip_id */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_D2_CHIP_ID__NUM 1 + +/* macros for BlueprintGlobalNameSpace::gen_controls */ +#ifndef __GEN_CONTROLS_MACRO__ +#define __GEN_CONTROLS_MACRO__ + +/* macros for field turbo */ +#define GEN_CONTROLS__TURBO__SHIFT 0 +#define GEN_CONTROLS__TURBO__WIDTH 1 +#define GEN_CONTROLS__TURBO__MASK 0x00000001U +#define GEN_CONTROLS__TURBO__READ(src) (u_int32_t)(src) & 0x00000001U +#define GEN_CONTROLS__TURBO__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define GEN_CONTROLS__TURBO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define GEN_CONTROLS__TURBO__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define GEN_CONTROLS__TURBO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define GEN_CONTROLS__TURBO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_short20 */ +#define GEN_CONTROLS__CF_SHORT20__SHIFT 1 +#define GEN_CONTROLS__CF_SHORT20__WIDTH 1 +#define GEN_CONTROLS__CF_SHORT20__MASK 0x00000002U +#define GEN_CONTROLS__CF_SHORT20__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define GEN_CONTROLS__CF_SHORT20__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define GEN_CONTROLS__CF_SHORT20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define GEN_CONTROLS__CF_SHORT20__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define GEN_CONTROLS__CF_SHORT20__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define GEN_CONTROLS__CF_SHORT20__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field dyn_20_40 */ +#define GEN_CONTROLS__DYN_20_40__SHIFT 2 +#define GEN_CONTROLS__DYN_20_40__WIDTH 1 +#define GEN_CONTROLS__DYN_20_40__MASK 0x00000004U +#define GEN_CONTROLS__DYN_20_40__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define GEN_CONTROLS__DYN_20_40__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define GEN_CONTROLS__DYN_20_40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define GEN_CONTROLS__DYN_20_40__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define GEN_CONTROLS__DYN_20_40__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define GEN_CONTROLS__DYN_20_40__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field dyn_20_40_pri_only */ +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__SHIFT 3 +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__WIDTH 1 +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__MASK 0x00000008U +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field dyn_20_40_pri_chn */ +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__SHIFT 4 +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__WIDTH 1 +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__MASK 0x00000010U +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field dyn_20_40_ext_chn */ +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__SHIFT 5 +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__WIDTH 1 +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__MASK 0x00000020U +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field ht_enable */ +#define GEN_CONTROLS__HT_ENABLE__SHIFT 6 +#define GEN_CONTROLS__HT_ENABLE__WIDTH 1 +#define GEN_CONTROLS__HT_ENABLE__MASK 0x00000040U +#define GEN_CONTROLS__HT_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define GEN_CONTROLS__HT_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define GEN_CONTROLS__HT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define GEN_CONTROLS__HT_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define GEN_CONTROLS__HT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define GEN_CONTROLS__HT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field allow_short_gi */ +#define GEN_CONTROLS__ALLOW_SHORT_GI__SHIFT 7 +#define GEN_CONTROLS__ALLOW_SHORT_GI__WIDTH 1 +#define GEN_CONTROLS__ALLOW_SHORT_GI__MASK 0x00000080U +#define GEN_CONTROLS__ALLOW_SHORT_GI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define GEN_CONTROLS__ALLOW_SHORT_GI__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define GEN_CONTROLS__ALLOW_SHORT_GI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define GEN_CONTROLS__ALLOW_SHORT_GI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define GEN_CONTROLS__ALLOW_SHORT_GI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define GEN_CONTROLS__ALLOW_SHORT_GI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field cf_2_chains_use_walsh */ +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__SHIFT 8 +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__WIDTH 1 +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__MASK 0x00000100U +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field cf_3_chains_use_walsh */ +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__SHIFT 9 +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__WIDTH 1 +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__MASK 0x00000200U +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field gf_enable */ +#define GEN_CONTROLS__GF_ENABLE__SHIFT 10 +#define GEN_CONTROLS__GF_ENABLE__WIDTH 1 +#define GEN_CONTROLS__GF_ENABLE__MASK 0x00000400U +#define GEN_CONTROLS__GF_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define GEN_CONTROLS__GF_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define GEN_CONTROLS__GF_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define GEN_CONTROLS__GF_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define GEN_CONTROLS__GF_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define GEN_CONTROLS__GF_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field bypass_dac_fifo_n */ +#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__SHIFT 11 +#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__WIDTH 1 +#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__MASK 0x00000800U +#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field ml_enable */ +#define GEN_CONTROLS__ML_ENABLE__SHIFT 12 +#define GEN_CONTROLS__ML_ENABLE__WIDTH 1 +#define GEN_CONTROLS__ML_ENABLE__MASK 0x00001000U +#define GEN_CONTROLS__ML_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define GEN_CONTROLS__ML_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define GEN_CONTROLS__ML_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define GEN_CONTROLS__ML_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define GEN_CONTROLS__ML_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define GEN_CONTROLS__ML_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field cf_corr_tim_ht_dltf */ +#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__SHIFT 13 +#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__WIDTH 1 +#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__MASK 0x00002000U +#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field bond_opt_chain_sel */ +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__SHIFT 14 +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__WIDTH 1 +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__MASK 0x00004000U +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) +//#define GEN_CONTROLS__TYPE u_int32_t +//#define GEN_CONTROLS__READ 0x00007fffU +//#define GEN_CONTROLS__WRITE 0x00007fffU + +#endif /* __GEN_CONTROLS_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_gen_controls */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_GEN_CONTROLS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::modes_select */ +#ifndef __MODES_SELECT_MACRO__ +#define __MODES_SELECT_MACRO__ + +/* macros for field cck_mode */ +#define MODES_SELECT__CCK_MODE__SHIFT 0 +#define MODES_SELECT__CCK_MODE__WIDTH 1 +#define MODES_SELECT__CCK_MODE__MASK 0x00000001U +#define MODES_SELECT__CCK_MODE__READ(src) (u_int32_t)(src) & 0x00000001U +#define MODES_SELECT__CCK_MODE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MODES_SELECT__CCK_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MODES_SELECT__CCK_MODE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MODES_SELECT__CCK_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MODES_SELECT__CCK_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dyn_ofdm_cck_mode */ +#define MODES_SELECT__DYN_OFDM_CCK_MODE__SHIFT 2 +#define MODES_SELECT__DYN_OFDM_CCK_MODE__WIDTH 1 +#define MODES_SELECT__DYN_OFDM_CCK_MODE__MASK 0x00000004U +#define MODES_SELECT__DYN_OFDM_CCK_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MODES_SELECT__DYN_OFDM_CCK_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MODES_SELECT__DYN_OFDM_CCK_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MODES_SELECT__DYN_OFDM_CCK_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MODES_SELECT__DYN_OFDM_CCK_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MODES_SELECT__DYN_OFDM_CCK_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field half_rate_mode */ +#define MODES_SELECT__HALF_RATE_MODE__SHIFT 5 +#define MODES_SELECT__HALF_RATE_MODE__WIDTH 1 +#define MODES_SELECT__HALF_RATE_MODE__MASK 0x00000020U +#define MODES_SELECT__HALF_RATE_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MODES_SELECT__HALF_RATE_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MODES_SELECT__HALF_RATE_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MODES_SELECT__HALF_RATE_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MODES_SELECT__HALF_RATE_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MODES_SELECT__HALF_RATE_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field quarter_rate_mode */ +#define MODES_SELECT__QUARTER_RATE_MODE__SHIFT 6 +#define MODES_SELECT__QUARTER_RATE_MODE__WIDTH 1 +#define MODES_SELECT__QUARTER_RATE_MODE__MASK 0x00000040U +#define MODES_SELECT__QUARTER_RATE_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MODES_SELECT__QUARTER_RATE_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MODES_SELECT__QUARTER_RATE_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MODES_SELECT__QUARTER_RATE_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MODES_SELECT__QUARTER_RATE_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MODES_SELECT__QUARTER_RATE_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field mac_clk_mode */ +#define MODES_SELECT__MAC_CLK_MODE__SHIFT 7 +#define MODES_SELECT__MAC_CLK_MODE__WIDTH 1 +#define MODES_SELECT__MAC_CLK_MODE__MASK 0x00000080U +#define MODES_SELECT__MAC_CLK_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MODES_SELECT__MAC_CLK_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MODES_SELECT__MAC_CLK_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MODES_SELECT__MAC_CLK_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MODES_SELECT__MAC_CLK_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MODES_SELECT__MAC_CLK_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field disable_dyn_cck_det */ +#define MODES_SELECT__DISABLE_DYN_CCK_DET__SHIFT 8 +#define MODES_SELECT__DISABLE_DYN_CCK_DET__WIDTH 1 +#define MODES_SELECT__DISABLE_DYN_CCK_DET__MASK 0x00000100U +#define MODES_SELECT__DISABLE_DYN_CCK_DET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MODES_SELECT__DISABLE_DYN_CCK_DET__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MODES_SELECT__DISABLE_DYN_CCK_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MODES_SELECT__DISABLE_DYN_CCK_DET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MODES_SELECT__DISABLE_DYN_CCK_DET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MODES_SELECT__DISABLE_DYN_CCK_DET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field svd_half_rate_mode */ +#define MODES_SELECT__SVD_HALF_RATE_MODE__SHIFT 9 +#define MODES_SELECT__SVD_HALF_RATE_MODE__WIDTH 1 +#define MODES_SELECT__SVD_HALF_RATE_MODE__MASK 0x00000200U +#define MODES_SELECT__SVD_HALF_RATE_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MODES_SELECT__SVD_HALF_RATE_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MODES_SELECT__SVD_HALF_RATE_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MODES_SELECT__SVD_HALF_RATE_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MODES_SELECT__SVD_HALF_RATE_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MODES_SELECT__SVD_HALF_RATE_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) +#define MODES_SELECT__TYPE u_int32_t +#define MODES_SELECT__READ 0x000003e5U +#define MODES_SELECT__WRITE 0x000003e5U + +#endif /* __MODES_SELECT_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_modes_select */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_MODES_SELECT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::active */ +#ifndef __ACTIVE_MACRO__ +#define __ACTIVE_MACRO__ + +/* macros for field cf_active */ +#define ACTIVE__CF_ACTIVE__SHIFT 0 +#define ACTIVE__CF_ACTIVE__WIDTH 1 +#define ACTIVE__CF_ACTIVE__MASK 0x00000001U +#define ACTIVE__CF_ACTIVE__READ(src) (u_int32_t)(src) & 0x00000001U +#define ACTIVE__CF_ACTIVE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define ACTIVE__CF_ACTIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define ACTIVE__CF_ACTIVE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define ACTIVE__CF_ACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define ACTIVE__CF_ACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define ACTIVE__TYPE u_int32_t +#define ACTIVE__READ 0x00000001U +#define ACTIVE__WRITE 0x00000001U + +#endif /* __ACTIVE_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_active */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_ACTIVE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::vit_spur_mask_A */ +#ifndef __VIT_SPUR_MASK_A_MACRO__ +#define __VIT_SPUR_MASK_A_MACRO__ + +/* macros for field cf_punc_mask_A */ +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__SHIFT 0 +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__WIDTH 10 +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__MASK 0x000003ffU +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field cf_punc_mask_idx_A */ +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__SHIFT 10 +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__WIDTH 7 +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__MASK 0x0001fc00U +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fc00U) >> 10) +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0001fc00U) +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0001fc00U) +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0001fc00U))) +#define VIT_SPUR_MASK_A__TYPE u_int32_t +#define VIT_SPUR_MASK_A__READ 0x0001ffffU +#define VIT_SPUR_MASK_A__WRITE 0x0001ffffU + +#endif /* __VIT_SPUR_MASK_A_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_vit_spur_mask_A */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_VIT_SPUR_MASK_A__NUM 1 + +/* macros for BlueprintGlobalNameSpace::vit_spur_mask_B */ +#ifndef __VIT_SPUR_MASK_B_MACRO__ +#define __VIT_SPUR_MASK_B_MACRO__ + +/* macros for field cf_punc_mask_B */ +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__SHIFT 0 +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__WIDTH 10 +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__MASK 0x000003ffU +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field cf_punc_mask_idx_B */ +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__SHIFT 10 +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__WIDTH 7 +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__MASK 0x0001fc00U +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fc00U) >> 10) +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0001fc00U) +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0001fc00U) +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0001fc00U))) +#define VIT_SPUR_MASK_B__TYPE u_int32_t +#define VIT_SPUR_MASK_B__READ 0x0001ffffU +#define VIT_SPUR_MASK_B__WRITE 0x0001ffffU + +#endif /* __VIT_SPUR_MASK_B_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_vit_spur_mask_B */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_VIT_SPUR_MASK_B__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spectral_scan */ +#ifndef __SPECTRAL_SCAN_MACRO__ +#define __SPECTRAL_SCAN_MACRO__ + +/* macros for field spectral_scan_ena */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__SHIFT 0 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__MASK 0x00000001U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field spectral_scan_active */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__SHIFT 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__MASK 0x00000002U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field disable_radar_tctl_rst */ +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__SHIFT 2 +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__WIDTH 1 +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__MASK 0x00000004U +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field disable_pulse_coarse_low */ +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__SHIFT 3 +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__WIDTH 1 +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__MASK 0x00000008U +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field spectral_scan_fft_period */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__SHIFT 4 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__WIDTH 4 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__MASK 0x000000f0U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field spectral_scan_period */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__SHIFT 8 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__WIDTH 8 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__MASK 0x0000ff00U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field spectral_scan_count */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__SHIFT 16 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__WIDTH 12 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__MASK 0x0fff0000U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fff0000U) >> 16) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x0fff0000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x0fff0000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x0fff0000U))) + +/* macros for field spectral_scan_short_rpt */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__SHIFT 28 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__MASK 0x10000000U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field spectral_scan_priority */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__SHIFT 29 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__MASK 0x20000000U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field spectral_scan_use_err5 */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__SHIFT 30 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__MASK 0x40000000U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +//#define SPECTRAL_SCAN__TYPE u_int32_t +//#define SPECTRAL_SCAN__READ 0x7fffffffU +//#define SPECTRAL_SCAN__WRITE 0x7fffffffU + +#endif /* __SPECTRAL_SCAN_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_spectral_scan */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_SPECTRAL_SCAN__NUM 1 + +/* macros for BlueprintGlobalNameSpace::radar_bw_filter */ +#ifndef __RADAR_BW_FILTER_MACRO__ +#define __RADAR_BW_FILTER_MACRO__ + +/* macros for field radar_avg_bw_check */ +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__SHIFT 0 +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__WIDTH 1 +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__MASK 0x00000001U +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field radar_dc_src_sel */ +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__SHIFT 1 +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__WIDTH 1 +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__MASK 0x00000002U +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field radar_firpwr_sel */ +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__SHIFT 2 +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__WIDTH 2 +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__MASK 0x0000000cU +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field radar_pulse_width_sel */ +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__SHIFT 4 +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__WIDTH 2 +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__MASK 0x00000030U +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field radar_dc_firpwr_thresh */ +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__SHIFT 8 +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__WIDTH 7 +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__MASK 0x00007f00U +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007f00U) >> 8) +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00007f00U) +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00007f00U) +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00007f00U))) + +/* macros for field radar_dc_pwr_bias */ +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__SHIFT 15 +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__WIDTH 6 +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__MASK 0x001f8000U +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f8000U) >> 15) +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x001f8000U) +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x001f8000U) +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x001f8000U))) + +/* macros for field radar_bin_max_bw */ +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__SHIFT 21 +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__WIDTH 6 +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__MASK 0x07e00000U +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__READ(src) \ + (((u_int32_t)(src)\ + & 0x07e00000U) >> 21) +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x07e00000U) +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x07e00000U) +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x07e00000U))) +#define RADAR_BW_FILTER__TYPE u_int32_t +#define RADAR_BW_FILTER__READ 0x07ffff3fU +#define RADAR_BW_FILTER__WRITE 0x07ffff3fU + +#endif /* __RADAR_BW_FILTER_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_radar_bw_filter */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_RADAR_BW_FILTER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::search_start_delay */ +#ifndef __SEARCH_START_DELAY_MACRO__ +#define __SEARCH_START_DELAY_MACRO__ + +/* macros for field search_start_delay */ +#define SEARCH_START_DELAY__SEARCH_START_DELAY__SHIFT 0 +#define SEARCH_START_DELAY__SEARCH_START_DELAY__WIDTH 12 +#define SEARCH_START_DELAY__SEARCH_START_DELAY__MASK 0x00000fffU +#define SEARCH_START_DELAY__SEARCH_START_DELAY__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define SEARCH_START_DELAY__SEARCH_START_DELAY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define SEARCH_START_DELAY__SEARCH_START_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define SEARCH_START_DELAY__SEARCH_START_DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field enable_flt_svd */ +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__SHIFT 12 +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__WIDTH 1 +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__MASK 0x00001000U +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field enable_send_chan */ +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__SHIFT 13 +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__WIDTH 1 +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__MASK 0x00002000U +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) +//#define SEARCH_START_DELAY__TYPE u_int32_t +//#define SEARCH_START_DELAY__READ 0x00003fffU +//#define SEARCH_START_DELAY__WRITE 0x00003fffU + +#endif /* __SEARCH_START_DELAY_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_search_start_delay */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_SEARCH_START_DELAY__NUM 1 + +/* macros for BlueprintGlobalNameSpace::max_rx_length */ +#ifndef __MAX_RX_LENGTH_MACRO__ +#define __MAX_RX_LENGTH_MACRO__ + +/* macros for field max_rx_length */ +#define MAX_RX_LENGTH__MAX_RX_LENGTH__SHIFT 0 +#define MAX_RX_LENGTH__MAX_RX_LENGTH__WIDTH 12 +#define MAX_RX_LENGTH__MAX_RX_LENGTH__MASK 0x00000fffU +#define MAX_RX_LENGTH__MAX_RX_LENGTH__READ(src) (u_int32_t)(src) & 0x00000fffU +#define MAX_RX_LENGTH__MAX_RX_LENGTH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define MAX_RX_LENGTH__MAX_RX_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define MAX_RX_LENGTH__MAX_RX_LENGTH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field max_ht_length */ +#define MAX_RX_LENGTH__MAX_HT_LENGTH__SHIFT 12 +#define MAX_RX_LENGTH__MAX_HT_LENGTH__WIDTH 18 +#define MAX_RX_LENGTH__MAX_HT_LENGTH__MASK 0x3ffff000U +#define MAX_RX_LENGTH__MAX_HT_LENGTH__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ffff000U) >> 12) +#define MAX_RX_LENGTH__MAX_HT_LENGTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x3ffff000U) +#define MAX_RX_LENGTH__MAX_HT_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ffff000U) | (((u_int32_t)(src) <<\ + 12) & 0x3ffff000U) +#define MAX_RX_LENGTH__MAX_HT_LENGTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x3ffff000U))) +#define MAX_RX_LENGTH__TYPE u_int32_t +#define MAX_RX_LENGTH__READ 0x3fffffffU +#define MAX_RX_LENGTH__WRITE 0x3fffffffU + +#endif /* __MAX_RX_LENGTH_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_max_rx_length */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_MAX_RX_LENGTH__NUM 1 + +/* macros for BlueprintGlobalNameSpace::frame_control */ +#ifndef __FRAME_CONTROL_MACRO__ +#define __FRAME_CONTROL_MACRO__ + +/* macros for field cf_overlap_window */ +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__SHIFT 0 +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__WIDTH 2 +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__MASK 0x00000003U +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field cf_scale_short */ +#define FRAME_CONTROL__CF_SCALE_SHORT__SHIFT 2 +#define FRAME_CONTROL__CF_SCALE_SHORT__WIDTH 1 +#define FRAME_CONTROL__CF_SCALE_SHORT__MASK 0x00000004U +#define FRAME_CONTROL__CF_SCALE_SHORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define FRAME_CONTROL__CF_SCALE_SHORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define FRAME_CONTROL__CF_SCALE_SHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define FRAME_CONTROL__CF_SCALE_SHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define FRAME_CONTROL__CF_SCALE_SHORT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define FRAME_CONTROL__CF_SCALE_SHORT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field cf_tx_clip */ +#define FRAME_CONTROL__CF_TX_CLIP__SHIFT 3 +#define FRAME_CONTROL__CF_TX_CLIP__WIDTH 3 +#define FRAME_CONTROL__CF_TX_CLIP__MASK 0x00000038U +#define FRAME_CONTROL__CF_TX_CLIP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define FRAME_CONTROL__CF_TX_CLIP__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define FRAME_CONTROL__CF_TX_CLIP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define FRAME_CONTROL__CF_TX_CLIP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field cf_tx_doublesamp_dac */ +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__SHIFT 6 +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__WIDTH 2 +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__MASK 0x000000c0U +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field tx_end_adjust */ +#define FRAME_CONTROL__TX_END_ADJUST__SHIFT 8 +#define FRAME_CONTROL__TX_END_ADJUST__WIDTH 8 +#define FRAME_CONTROL__TX_END_ADJUST__MASK 0x0000ff00U +#define FRAME_CONTROL__TX_END_ADJUST__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define FRAME_CONTROL__TX_END_ADJUST__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define FRAME_CONTROL__TX_END_ADJUST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define FRAME_CONTROL__TX_END_ADJUST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field prepend_chan_info */ +#define FRAME_CONTROL__PREPEND_CHAN_INFO__SHIFT 16 +#define FRAME_CONTROL__PREPEND_CHAN_INFO__WIDTH 1 +#define FRAME_CONTROL__PREPEND_CHAN_INFO__MASK 0x00010000U +#define FRAME_CONTROL__PREPEND_CHAN_INFO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define FRAME_CONTROL__PREPEND_CHAN_INFO__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define FRAME_CONTROL__PREPEND_CHAN_INFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define FRAME_CONTROL__PREPEND_CHAN_INFO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define FRAME_CONTROL__PREPEND_CHAN_INFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define FRAME_CONTROL__PREPEND_CHAN_INFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field short_high_par_norm */ +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__SHIFT 17 +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__WIDTH 1 +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__MASK 0x00020000U +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field en_err_green_field */ +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__SHIFT 18 +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__MASK 0x00040000U +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field en_err_xr_power_ratio */ +#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__SHIFT 19 +#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__MASK 0x00080000U +#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field en_err_ofdm_xcorr */ +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__SHIFT 20 +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__MASK 0x00100000U +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field en_err_long_sc_thr */ +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__SHIFT 21 +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__MASK 0x00200000U +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field en_err_tim_long1 */ +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__SHIFT 22 +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__MASK 0x00400000U +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field en_err_tim_early_trig */ +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__SHIFT 23 +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__MASK 0x00800000U +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field en_err_tim_timeout */ +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__SHIFT 24 +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__MASK 0x01000000U +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field en_err_signal_parity */ +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__SHIFT 25 +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__MASK 0x02000000U +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field en_err_rate_illegal */ +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__SHIFT 26 +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__MASK 0x04000000U +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field en_err_length_illegal */ +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__SHIFT 27 +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__MASK 0x08000000U +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field no_6mbps_service_err */ +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__SHIFT 28 +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__WIDTH 1 +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__MASK 0x10000000U +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field en_err_service */ +#define FRAME_CONTROL__EN_ERR_SERVICE__SHIFT 29 +#define FRAME_CONTROL__EN_ERR_SERVICE__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_SERVICE__MASK 0x20000000U +#define FRAME_CONTROL__EN_ERR_SERVICE__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define FRAME_CONTROL__EN_ERR_SERVICE__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define FRAME_CONTROL__EN_ERR_SERVICE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define FRAME_CONTROL__EN_ERR_SERVICE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define FRAME_CONTROL__EN_ERR_SERVICE__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define FRAME_CONTROL__EN_ERR_SERVICE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field en_err_tx_underrun */ +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__SHIFT 30 +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__MASK 0x40000000U +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field en_err_rx_abort */ +#define FRAME_CONTROL__EN_ERR_RX_ABORT__SHIFT 31 +#define FRAME_CONTROL__EN_ERR_RX_ABORT__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_RX_ABORT__MASK 0x80000000U +#define FRAME_CONTROL__EN_ERR_RX_ABORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define FRAME_CONTROL__EN_ERR_RX_ABORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define FRAME_CONTROL__EN_ERR_RX_ABORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define FRAME_CONTROL__EN_ERR_RX_ABORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define FRAME_CONTROL__EN_ERR_RX_ABORT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define FRAME_CONTROL__EN_ERR_RX_ABORT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define FRAME_CONTROL__TYPE u_int32_t +#define FRAME_CONTROL__READ 0xffffffffU +#define FRAME_CONTROL__WRITE 0xffffffffU + +#endif /* __FRAME_CONTROL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_frame_control */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_FRAME_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rfbus_request */ +#ifndef __RFBUS_REQUEST_MACRO__ +#define __RFBUS_REQUEST_MACRO__ + +/* macros for field rfbus_request */ +#define RFBUS_REQUEST__RFBUS_REQUEST__SHIFT 0 +#define RFBUS_REQUEST__RFBUS_REQUEST__WIDTH 1 +#define RFBUS_REQUEST__RFBUS_REQUEST__MASK 0x00000001U +#define RFBUS_REQUEST__RFBUS_REQUEST__READ(src) (u_int32_t)(src) & 0x00000001U +#define RFBUS_REQUEST__RFBUS_REQUEST__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RFBUS_REQUEST__RFBUS_REQUEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RFBUS_REQUEST__RFBUS_REQUEST__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RFBUS_REQUEST__RFBUS_REQUEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RFBUS_REQUEST__RFBUS_REQUEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define RFBUS_REQUEST__TYPE u_int32_t +#define RFBUS_REQUEST__READ 0x00000001U +#define RFBUS_REQUEST__WRITE 0x00000001U + +#endif /* __RFBUS_REQUEST_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_rfbus_request */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_RFBUS_REQUEST__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rfbus_grant */ +#ifndef __RFBUS_GRANT_MACRO__ +#define __RFBUS_GRANT_MACRO__ + +/* macros for field rfbus_grant */ +#define RFBUS_GRANT__RFBUS_GRANT__SHIFT 0 +#define RFBUS_GRANT__RFBUS_GRANT__WIDTH 1 +#define RFBUS_GRANT__RFBUS_GRANT__MASK 0x00000001U +#define RFBUS_GRANT__RFBUS_GRANT__READ(src) (u_int32_t)(src) & 0x00000001U +#define RFBUS_GRANT__RFBUS_GRANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RFBUS_GRANT__RFBUS_GRANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field bt_ant */ +#define RFBUS_GRANT__BT_ANT__SHIFT 1 +#define RFBUS_GRANT__BT_ANT__WIDTH 1 +#define RFBUS_GRANT__BT_ANT__MASK 0x00000002U +#define RFBUS_GRANT__BT_ANT__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define RFBUS_GRANT__BT_ANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RFBUS_GRANT__BT_ANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define RFBUS_GRANT__TYPE u_int32_t +#define RFBUS_GRANT__READ 0x00000003U + +#endif /* __RFBUS_GRANT_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_rfbus_grant */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_RFBUS_GRANT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rifs */ +#ifndef __RIFS_MACRO__ +#define __RIFS_MACRO__ + +/* macros for field disable_fcc_fix */ +#define RIFS__DISABLE_FCC_FIX__SHIFT 25 +#define RIFS__DISABLE_FCC_FIX__WIDTH 1 +#define RIFS__DISABLE_FCC_FIX__MASK 0x02000000U +#define RIFS__DISABLE_FCC_FIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define RIFS__DISABLE_FCC_FIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define RIFS__DISABLE_FCC_FIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RIFS__DISABLE_FCC_FIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RIFS__DISABLE_FCC_FIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RIFS__DISABLE_FCC_FIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field enable_reset_tdomain */ +#define RIFS__ENABLE_RESET_TDOMAIN__SHIFT 26 +#define RIFS__ENABLE_RESET_TDOMAIN__WIDTH 1 +#define RIFS__ENABLE_RESET_TDOMAIN__MASK 0x04000000U +#define RIFS__ENABLE_RESET_TDOMAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RIFS__ENABLE_RESET_TDOMAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RIFS__ENABLE_RESET_TDOMAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RIFS__ENABLE_RESET_TDOMAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RIFS__ENABLE_RESET_TDOMAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RIFS__ENABLE_RESET_TDOMAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field disable_fcc_fix2 */ +#define RIFS__DISABLE_FCC_FIX2__SHIFT 27 +#define RIFS__DISABLE_FCC_FIX2__WIDTH 1 +#define RIFS__DISABLE_FCC_FIX2__MASK 0x08000000U +#define RIFS__DISABLE_FCC_FIX2__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RIFS__DISABLE_FCC_FIX2__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RIFS__DISABLE_FCC_FIX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RIFS__DISABLE_FCC_FIX2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RIFS__DISABLE_FCC_FIX2__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RIFS__DISABLE_FCC_FIX2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field disable_rifs_cck_fix */ +#define RIFS__DISABLE_RIFS_CCK_FIX__SHIFT 28 +#define RIFS__DISABLE_RIFS_CCK_FIX__WIDTH 1 +#define RIFS__DISABLE_RIFS_CCK_FIX__MASK 0x10000000U +#define RIFS__DISABLE_RIFS_CCK_FIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RIFS__DISABLE_RIFS_CCK_FIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RIFS__DISABLE_RIFS_CCK_FIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RIFS__DISABLE_RIFS_CCK_FIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RIFS__DISABLE_RIFS_CCK_FIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RIFS__DISABLE_RIFS_CCK_FIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field disable_error_reset_fix */ +#define RIFS__DISABLE_ERROR_RESET_FIX__SHIFT 29 +#define RIFS__DISABLE_ERROR_RESET_FIX__WIDTH 1 +#define RIFS__DISABLE_ERROR_RESET_FIX__MASK 0x20000000U +#define RIFS__DISABLE_ERROR_RESET_FIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RIFS__DISABLE_ERROR_RESET_FIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RIFS__DISABLE_ERROR_RESET_FIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RIFS__DISABLE_ERROR_RESET_FIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RIFS__DISABLE_ERROR_RESET_FIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RIFS__DISABLE_ERROR_RESET_FIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field radar_use_fdomain_reset */ +#define RIFS__RADAR_USE_FDOMAIN_RESET__SHIFT 30 +#define RIFS__RADAR_USE_FDOMAIN_RESET__WIDTH 1 +#define RIFS__RADAR_USE_FDOMAIN_RESET__MASK 0x40000000U +#define RIFS__RADAR_USE_FDOMAIN_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RIFS__RADAR_USE_FDOMAIN_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RIFS__RADAR_USE_FDOMAIN_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RIFS__RADAR_USE_FDOMAIN_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RIFS__RADAR_USE_FDOMAIN_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RIFS__RADAR_USE_FDOMAIN_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define RIFS__TYPE u_int32_t +#define RIFS__READ 0x7e000000U +#define RIFS__WRITE 0x7e000000U + +#endif /* __RIFS_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_rifs */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_RIFS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_clear_delay */ +#ifndef __RX_CLEAR_DELAY_MACRO__ +#define __RX_CLEAR_DELAY_MACRO__ + +/* macros for field ofdm_xr_rx_clear_delay */ +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__SHIFT 0 +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__WIDTH 10 +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__MASK 0x000003ffU +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define RX_CLEAR_DELAY__TYPE u_int32_t +#define RX_CLEAR_DELAY__READ 0x000003ffU +#define RX_CLEAR_DELAY__WRITE 0x000003ffU + +#endif /* __RX_CLEAR_DELAY_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_rx_clear_delay */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_RX_CLEAR_DELAY__NUM 1 + +/* macros for BlueprintGlobalNameSpace::analog_power_on_time */ +#ifndef __ANALOG_POWER_ON_TIME_MACRO__ +#define __ANALOG_POWER_ON_TIME_MACRO__ + +/* macros for field active_to_receive */ +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__SHIFT 0 +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__WIDTH 14 +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__MASK 0x00003fffU +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) +#define ANALOG_POWER_ON_TIME__TYPE u_int32_t +#define ANALOG_POWER_ON_TIME__READ 0x00003fffU +#define ANALOG_POWER_ON_TIME__WRITE 0x00003fffU + +#endif /* __ANALOG_POWER_ON_TIME_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_analog_power_on_time */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_ANALOG_POWER_ON_TIME__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_timing_1 */ +#ifndef __TX_TIMING_1_MACRO__ +#define __TX_TIMING_1_MACRO__ + +/* macros for field tx_frame_to_adc_off */ +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__SHIFT 0 +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__WIDTH 8 +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__MASK 0x000000ffU +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_frame_to_a2_rx_off */ +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__SHIFT 8 +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__WIDTH 8 +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__MASK 0x0000ff00U +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field tx_frame_to_dac_on */ +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__SHIFT 16 +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__WIDTH 8 +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__MASK 0x00ff0000U +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field tx_frame_to_a2_tx_on */ +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__SHIFT 24 +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__WIDTH 8 +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__MASK 0xff000000U +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TX_TIMING_1__TYPE u_int32_t +#define TX_TIMING_1__READ 0xffffffffU +#define TX_TIMING_1__WRITE 0xffffffffU + +#endif /* __TX_TIMING_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_timing_1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_TIMING_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_timing_2 */ +#ifndef __TX_TIMING_2_MACRO__ +#define __TX_TIMING_2_MACRO__ + +/* macros for field tx_frame_to_tx_d_start */ +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__SHIFT 0 +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__WIDTH 8 +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__MASK 0x000000ffU +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_frame_to_pa_on */ +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__SHIFT 8 +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__WIDTH 8 +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__MASK 0x0000ff00U +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field tx_end_to_pa_off */ +#define TX_TIMING_2__TX_END_TO_PA_OFF__SHIFT 16 +#define TX_TIMING_2__TX_END_TO_PA_OFF__WIDTH 8 +#define TX_TIMING_2__TX_END_TO_PA_OFF__MASK 0x00ff0000U +#define TX_TIMING_2__TX_END_TO_PA_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TX_TIMING_2__TX_END_TO_PA_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TX_TIMING_2__TX_END_TO_PA_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TX_TIMING_2__TX_END_TO_PA_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field tx_end_to_a2_tx_off */ +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__SHIFT 24 +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__WIDTH 8 +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__MASK 0xff000000U +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TX_TIMING_2__TYPE u_int32_t +#define TX_TIMING_2__READ 0xffffffffU +#define TX_TIMING_2__WRITE 0xffffffffU + +#endif /* __TX_TIMING_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_timing_2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_TIMING_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_timing_3 */ +#ifndef __TX_TIMING_3_MACRO__ +#define __TX_TIMING_3_MACRO__ + +/* macros for field tx_end_to_dac_off */ +#define TX_TIMING_3__TX_END_TO_DAC_OFF__SHIFT 0 +#define TX_TIMING_3__TX_END_TO_DAC_OFF__WIDTH 8 +#define TX_TIMING_3__TX_END_TO_DAC_OFF__MASK 0x000000ffU +#define TX_TIMING_3__TX_END_TO_DAC_OFF__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define TX_TIMING_3__TX_END_TO_DAC_OFF__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TX_TIMING_3__TX_END_TO_DAC_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TX_TIMING_3__TX_END_TO_DAC_OFF__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_frame_to_therm_chain_on */ +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__SHIFT 8 +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__WIDTH 8 +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__MASK 0x0000ff00U +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field tx_end_to_a2_rx_on */ +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__SHIFT 16 +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__WIDTH 8 +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__MASK 0x00ff0000U +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field tx_end_to_adc_on */ +#define TX_TIMING_3__TX_END_TO_ADC_ON__SHIFT 24 +#define TX_TIMING_3__TX_END_TO_ADC_ON__WIDTH 8 +#define TX_TIMING_3__TX_END_TO_ADC_ON__MASK 0xff000000U +#define TX_TIMING_3__TX_END_TO_ADC_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TX_TIMING_3__TX_END_TO_ADC_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TX_TIMING_3__TX_END_TO_ADC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TX_TIMING_3__TX_END_TO_ADC_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TX_TIMING_3__TYPE u_int32_t +#define TX_TIMING_3__READ 0xffffffffU +#define TX_TIMING_3__WRITE 0xffffffffU + +#endif /* __TX_TIMING_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_timing_3 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_TIMING_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::xpa_timing_control */ +#ifndef __XPA_TIMING_CONTROL_MACRO__ +#define __XPA_TIMING_CONTROL_MACRO__ + +/* macros for field tx_frame_to_xpaa_on */ +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__SHIFT 0 +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__WIDTH 8 +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__MASK 0x000000ffU +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_frame_to_xpab_on */ +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__SHIFT 8 +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__WIDTH 8 +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__MASK 0x0000ff00U +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field tx_end_to_xpaa_off */ +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__SHIFT 16 +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__WIDTH 8 +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__MASK 0x00ff0000U +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field tx_end_to_xpab_off */ +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__SHIFT 24 +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__WIDTH 8 +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__MASK 0xff000000U +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define XPA_TIMING_CONTROL__TYPE u_int32_t +#define XPA_TIMING_CONTROL__READ 0xffffffffU +#define XPA_TIMING_CONTROL__WRITE 0xffffffffU + +#endif /* __XPA_TIMING_CONTROL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_xpa_timing_control */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_XPA_TIMING_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::misc_pa_control */ +#ifndef __MISC_PA_CONTROL_MACRO__ +#define __MISC_PA_CONTROL_MACRO__ + +/* macros for field xpaa_active_high */ +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__SHIFT 0 +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__WIDTH 1 +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__MASK 0x00000001U +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field xpab_active_high */ +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__SHIFT 1 +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__WIDTH 1 +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__MASK 0x00000002U +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field enable_xpaa */ +#define MISC_PA_CONTROL__ENABLE_XPAA__SHIFT 2 +#define MISC_PA_CONTROL__ENABLE_XPAA__WIDTH 1 +#define MISC_PA_CONTROL__ENABLE_XPAA__MASK 0x00000004U +#define MISC_PA_CONTROL__ENABLE_XPAA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MISC_PA_CONTROL__ENABLE_XPAA__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MISC_PA_CONTROL__ENABLE_XPAA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MISC_PA_CONTROL__ENABLE_XPAA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MISC_PA_CONTROL__ENABLE_XPAA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MISC_PA_CONTROL__ENABLE_XPAA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field enable_xpab */ +#define MISC_PA_CONTROL__ENABLE_XPAB__SHIFT 3 +#define MISC_PA_CONTROL__ENABLE_XPAB__WIDTH 1 +#define MISC_PA_CONTROL__ENABLE_XPAB__MASK 0x00000008U +#define MISC_PA_CONTROL__ENABLE_XPAB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MISC_PA_CONTROL__ENABLE_XPAB__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MISC_PA_CONTROL__ENABLE_XPAB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MISC_PA_CONTROL__ENABLE_XPAB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MISC_PA_CONTROL__ENABLE_XPAB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MISC_PA_CONTROL__ENABLE_XPAB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define MISC_PA_CONTROL__TYPE u_int32_t +#define MISC_PA_CONTROL__READ 0x0000000fU +#define MISC_PA_CONTROL__WRITE 0x0000000fU + +#endif /* __MISC_PA_CONTROL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_misc_pa_control */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_MISC_PA_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::switch_table_chn_b0 */ +#ifndef __SWITCH_TABLE_CHN_B0_MACRO__ +#define __SWITCH_TABLE_CHN_B0_MACRO__ + +/* macros for field switch_table_idle_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__SHIFT 0 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__MASK 0x00000003U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field switch_table_t_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__SHIFT 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__MASK 0x0000000cU +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field switch_table_r_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__SHIFT 4 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__MASK 0x00000030U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field switch_table_rx1_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__SHIFT 6 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__MASK 0x000000c0U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field switch_table_rx12_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__SHIFT 8 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__MASK 0x00000300U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field switch_table_b_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__SHIFT 10 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__MASK 0x00000c00U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) +#define SWITCH_TABLE_CHN_B0__TYPE u_int32_t +#define SWITCH_TABLE_CHN_B0__READ 0x00000fffU +#define SWITCH_TABLE_CHN_B0__WRITE 0x00000fffU + +#endif /* __SWITCH_TABLE_CHN_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_switch_table_chn_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_SWITCH_TABLE_CHN_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::switch_table_com1 */ +#ifndef __SWITCH_TABLE_COM1_MACRO__ +#define __SWITCH_TABLE_COM1_MACRO__ + +/* macros for field switch_table_com_idle */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__SHIFT 0 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__MASK 0x0000000fU +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field switch_table_com_t1 */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__SHIFT 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__MASK 0x000000f0U +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field switch_table_com_t2 */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__SHIFT 8 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__MASK 0x00000f00U +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field switch_table_com_b */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__SHIFT 12 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__MASK 0x0000f000U +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field switch_table_com_idle_alt */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__SHIFT 16 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__MASK 0x000f0000U +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) +//#define SWITCH_TABLE_COM1__TYPE u_int32_t +//#define SWITCH_TABLE_COM1__READ 0x000fffffU +//#define SWITCH_TABLE_COM1__WRITE 0x000fffffU + +#endif /* __SWITCH_TABLE_COM1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_switch_table_com1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_SWITCH_TABLE_COM1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::switch_table_com2 */ +#ifndef __SWITCH_TABLE_COM2_MACRO__ +#define __SWITCH_TABLE_COM2_MACRO__ + +/* macros for field switch_table_com_ra1l1 */ +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__SHIFT 0 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__WIDTH 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__MASK 0x0000000fU +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field switch_table_com_ra2l1 */ +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__SHIFT 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__WIDTH 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__MASK 0x000000f0U +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field switch_table_com_ra1l2 */ +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__SHIFT 8 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__WIDTH 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__MASK 0x00000f00U +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field switch_table_com_ra2l2 */ +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__SHIFT 12 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__WIDTH 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__MASK 0x0000f000U +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field switch_table_com_ra12 */ +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__SHIFT 16 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__WIDTH 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__MASK 0x000f0000U +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) +#define SWITCH_TABLE_COM2__TYPE u_int32_t +#define SWITCH_TABLE_COM2__READ 0x000fffffU +#define SWITCH_TABLE_COM2__WRITE 0x000fffffU + +#endif /* __SWITCH_TABLE_COM2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_switch_table_com2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_SWITCH_TABLE_COM2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::multichain_enable */ +#ifndef __MULTICHAIN_ENABLE_MACRO__ +#define __MULTICHAIN_ENABLE_MACRO__ + +/* macros for field rx_chain_mask */ +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__SHIFT 0 +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__WIDTH 3 +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__MASK 0x00000007U +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) +#define MULTICHAIN_ENABLE__TYPE u_int32_t +#define MULTICHAIN_ENABLE__READ 0x00000007U +#define MULTICHAIN_ENABLE__WRITE 0x00000007U + +#endif /* __MULTICHAIN_ENABLE_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_multichain_enable */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_MULTICHAIN_ENABLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_chain_mask */ +#ifndef __CAL_CHAIN_MASK_MACRO__ +#define __CAL_CHAIN_MASK_MACRO__ + +/* macros for field cal_chain_mask */ +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__SHIFT 0 +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__WIDTH 3 +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__MASK 0x00000007U +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) +#define CAL_CHAIN_MASK__TYPE u_int32_t +#define CAL_CHAIN_MASK__READ 0x00000007U +#define CAL_CHAIN_MASK__WRITE 0x00000007U + +#endif /* __CAL_CHAIN_MASK_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cal_chain_mask */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CAL_CHAIN_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_control */ +#ifndef __AGC_CONTROL_MACRO__ +#define __AGC_CONTROL_MACRO__ + +/* macros for field do_calibrate */ +#define AGC_CONTROL__DO_CALIBRATE__SHIFT 0 +#define AGC_CONTROL__DO_CALIBRATE__WIDTH 1 +#define AGC_CONTROL__DO_CALIBRATE__MASK 0x00000001U +#define AGC_CONTROL__DO_CALIBRATE__READ(src) (u_int32_t)(src) & 0x00000001U +#define AGC_CONTROL__DO_CALIBRATE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define AGC_CONTROL__DO_CALIBRATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define AGC_CONTROL__DO_CALIBRATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define AGC_CONTROL__DO_CALIBRATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define AGC_CONTROL__DO_CALIBRATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field do_noisefloor */ +#define AGC_CONTROL__DO_NOISEFLOOR__SHIFT 1 +#define AGC_CONTROL__DO_NOISEFLOOR__WIDTH 1 +#define AGC_CONTROL__DO_NOISEFLOOR__MASK 0x00000002U +#define AGC_CONTROL__DO_NOISEFLOOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define AGC_CONTROL__DO_NOISEFLOOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define AGC_CONTROL__DO_NOISEFLOOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define AGC_CONTROL__DO_NOISEFLOOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define AGC_CONTROL__DO_NOISEFLOOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define AGC_CONTROL__DO_NOISEFLOOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field min_num_gain_change */ +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__SHIFT 3 +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__WIDTH 3 +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__MASK 0x00000038U +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field ycok_max */ +#define AGC_CONTROL__YCOK_MAX__SHIFT 6 +#define AGC_CONTROL__YCOK_MAX__WIDTH 4 +#define AGC_CONTROL__YCOK_MAX__MASK 0x000003c0U +#define AGC_CONTROL__YCOK_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003c0U) >> 6) +#define AGC_CONTROL__YCOK_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000003c0U) +#define AGC_CONTROL__YCOK_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000003c0U) +#define AGC_CONTROL__YCOK_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000003c0U))) + +/* macros for field leaky_bucket_enable */ +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__SHIFT 10 +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__WIDTH 1 +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__MASK 0x00000400U +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field CAL_enable */ +#define AGC_CONTROL__CAL_ENABLE__SHIFT 11 +#define AGC_CONTROL__CAL_ENABLE__WIDTH 1 +#define AGC_CONTROL__CAL_ENABLE__MASK 0x00000800U +#define AGC_CONTROL__CAL_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define AGC_CONTROL__CAL_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define AGC_CONTROL__CAL_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define AGC_CONTROL__CAL_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define AGC_CONTROL__CAL_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define AGC_CONTROL__CAL_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field use_table_seed */ +#define AGC_CONTROL__USE_TABLE_SEED__SHIFT 12 +#define AGC_CONTROL__USE_TABLE_SEED__WIDTH 1 +#define AGC_CONTROL__USE_TABLE_SEED__MASK 0x00001000U +#define AGC_CONTROL__USE_TABLE_SEED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define AGC_CONTROL__USE_TABLE_SEED__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define AGC_CONTROL__USE_TABLE_SEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define AGC_CONTROL__USE_TABLE_SEED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define AGC_CONTROL__USE_TABLE_SEED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define AGC_CONTROL__USE_TABLE_SEED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field agc_update_table_seed */ +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__SHIFT 13 +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__WIDTH 1 +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__MASK 0x00002000U +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field enable_noisefloor */ +#define AGC_CONTROL__ENABLE_NOISEFLOOR__SHIFT 15 +#define AGC_CONTROL__ENABLE_NOISEFLOOR__WIDTH 1 +#define AGC_CONTROL__ENABLE_NOISEFLOOR__MASK 0x00008000U +#define AGC_CONTROL__ENABLE_NOISEFLOOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define AGC_CONTROL__ENABLE_NOISEFLOOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define AGC_CONTROL__ENABLE_NOISEFLOOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define AGC_CONTROL__ENABLE_NOISEFLOOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define AGC_CONTROL__ENABLE_NOISEFLOOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define AGC_CONTROL__ENABLE_NOISEFLOOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field enable_fltr_cal */ +#define AGC_CONTROL__ENABLE_FLTR_CAL__SHIFT 16 +#define AGC_CONTROL__ENABLE_FLTR_CAL__WIDTH 1 +#define AGC_CONTROL__ENABLE_FLTR_CAL__MASK 0x00010000U +#define AGC_CONTROL__ENABLE_FLTR_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define AGC_CONTROL__ENABLE_FLTR_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define AGC_CONTROL__ENABLE_FLTR_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define AGC_CONTROL__ENABLE_FLTR_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define AGC_CONTROL__ENABLE_FLTR_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define AGC_CONTROL__ENABLE_FLTR_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field no_update_noisefloor */ +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__SHIFT 17 +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__WIDTH 1 +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__MASK 0x00020000U +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field extend_NF_pwr_meas */ +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__SHIFT 18 +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__WIDTH 1 +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__MASK 0x00040000U +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field clc_success */ +#define AGC_CONTROL__CLC_SUCCESS__SHIFT 19 +#define AGC_CONTROL__CLC_SUCCESS__WIDTH 1 +#define AGC_CONTROL__CLC_SUCCESS__MASK 0x00080000U +#define AGC_CONTROL__CLC_SUCCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define AGC_CONTROL__CLC_SUCCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define AGC_CONTROL__CLC_SUCCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field enable_pkdet_cal */ +#define AGC_CONTROL__ENABLE_PKDET_CAL__SHIFT 20 +#define AGC_CONTROL__ENABLE_PKDET_CAL__WIDTH 1 +#define AGC_CONTROL__ENABLE_PKDET_CAL__MASK 0x00100000U +#define AGC_CONTROL__ENABLE_PKDET_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define AGC_CONTROL__ENABLE_PKDET_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define AGC_CONTROL__ENABLE_PKDET_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define AGC_CONTROL__ENABLE_PKDET_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define AGC_CONTROL__ENABLE_PKDET_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define AGC_CONTROL__ENABLE_PKDET_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) +#define AGC_CONTROL__TYPE u_int32_t +#define AGC_CONTROL__READ 0x001fbffbU +#define AGC_CONTROL__WRITE 0x001fbffbU + +#endif /* __AGC_CONTROL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_agc_control */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_AGC_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_cal_mode */ +#ifndef __IQ_ADC_CAL_MODE_MACRO__ +#define __IQ_ADC_CAL_MODE_MACRO__ + +/* macros for field gain_dc_iq_cal_mode */ +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__SHIFT 0 +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__WIDTH 2 +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__MASK 0x00000003U +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field test_caladcoff */ +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__SHIFT 2 +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__WIDTH 1 +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__MASK 0x00000004U +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define IQ_ADC_CAL_MODE__TYPE u_int32_t +#define IQ_ADC_CAL_MODE__READ 0x00000007U +#define IQ_ADC_CAL_MODE__WRITE 0x00000007U + +#endif /* __IQ_ADC_CAL_MODE_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_iq_adc_cal_mode */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_IQ_ADC_CAL_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::fcal_1 */ +#ifndef __FCAL_1_MACRO__ +#define __FCAL_1_MACRO__ + +/* macros for field flc_pb_fstep */ +#define FCAL_1__FLC_PB_FSTEP__SHIFT 0 +#define FCAL_1__FLC_PB_FSTEP__WIDTH 10 +#define FCAL_1__FLC_PB_FSTEP__MASK 0x000003ffU +#define FCAL_1__FLC_PB_FSTEP__READ(src) (u_int32_t)(src) & 0x000003ffU +#define FCAL_1__FLC_PB_FSTEP__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define FCAL_1__FLC_PB_FSTEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define FCAL_1__FLC_PB_FSTEP__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field flc_sb_fstep */ +#define FCAL_1__FLC_SB_FSTEP__SHIFT 10 +#define FCAL_1__FLC_SB_FSTEP__WIDTH 10 +#define FCAL_1__FLC_SB_FSTEP__MASK 0x000ffc00U +#define FCAL_1__FLC_SB_FSTEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define FCAL_1__FLC_SB_FSTEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define FCAL_1__FLC_SB_FSTEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define FCAL_1__FLC_SB_FSTEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field flc_pb_atten */ +#define FCAL_1__FLC_PB_ATTEN__SHIFT 20 +#define FCAL_1__FLC_PB_ATTEN__WIDTH 5 +#define FCAL_1__FLC_PB_ATTEN__MASK 0x01f00000U +#define FCAL_1__FLC_PB_ATTEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define FCAL_1__FLC_PB_ATTEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define FCAL_1__FLC_PB_ATTEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define FCAL_1__FLC_PB_ATTEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field flc_sb_atten */ +#define FCAL_1__FLC_SB_ATTEN__SHIFT 25 +#define FCAL_1__FLC_SB_ATTEN__WIDTH 5 +#define FCAL_1__FLC_SB_ATTEN__MASK 0x3e000000U +#define FCAL_1__FLC_SB_ATTEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define FCAL_1__FLC_SB_ATTEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define FCAL_1__FLC_SB_ATTEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define FCAL_1__FLC_SB_ATTEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define FCAL_1__TYPE u_int32_t +#define FCAL_1__READ 0x3fffffffU +#define FCAL_1__WRITE 0x3fffffffU + +#endif /* __FCAL_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_fcal_1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_FCAL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::fcal_2_b0 */ +#ifndef __FCAL_2_B0_MACRO__ +#define __FCAL_2_B0_MACRO__ + +/* macros for field flc_pwr_thresh */ +#define FCAL_2_B0__FLC_PWR_THRESH__SHIFT 0 +#define FCAL_2_B0__FLC_PWR_THRESH__WIDTH 3 +#define FCAL_2_B0__FLC_PWR_THRESH__MASK 0x00000007U +#define FCAL_2_B0__FLC_PWR_THRESH__READ(src) (u_int32_t)(src) & 0x00000007U +#define FCAL_2_B0__FLC_PWR_THRESH__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define FCAL_2_B0__FLC_PWR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define FCAL_2_B0__FLC_PWR_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field flc_sw_cap_val_0 */ +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__SHIFT 3 +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__WIDTH 5 +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__MASK 0x000000f8U +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f8U) >> 3) +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000000f8U) +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000000f8U) +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000000f8U))) + +/* macros for field flc_bbmiscgain */ +#define FCAL_2_B0__FLC_BBMISCGAIN__SHIFT 8 +#define FCAL_2_B0__FLC_BBMISCGAIN__WIDTH 2 +#define FCAL_2_B0__FLC_BBMISCGAIN__MASK 0x00000300U +#define FCAL_2_B0__FLC_BBMISCGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define FCAL_2_B0__FLC_BBMISCGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define FCAL_2_B0__FLC_BBMISCGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define FCAL_2_B0__FLC_BBMISCGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field flc_bb1dbgain */ +#define FCAL_2_B0__FLC_BB1DBGAIN__SHIFT 10 +#define FCAL_2_B0__FLC_BB1DBGAIN__WIDTH 3 +#define FCAL_2_B0__FLC_BB1DBGAIN__MASK 0x00001c00U +#define FCAL_2_B0__FLC_BB1DBGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001c00U) >> 10) +#define FCAL_2_B0__FLC_BB1DBGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00001c00U) +#define FCAL_2_B0__FLC_BB1DBGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00001c00U) +#define FCAL_2_B0__FLC_BB1DBGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00001c00U))) + +/* macros for field flc_bb6dbgain */ +#define FCAL_2_B0__FLC_BB6DBGAIN__SHIFT 13 +#define FCAL_2_B0__FLC_BB6DBGAIN__WIDTH 2 +#define FCAL_2_B0__FLC_BB6DBGAIN__MASK 0x00006000U +#define FCAL_2_B0__FLC_BB6DBGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00006000U) >> 13) +#define FCAL_2_B0__FLC_BB6DBGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00006000U) +#define FCAL_2_B0__FLC_BB6DBGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00006000U) | (((u_int32_t)(src) <<\ + 13) & 0x00006000U) +#define FCAL_2_B0__FLC_BB6DBGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00006000U))) + +/* macros for field flc_sw_cap_set */ +#define FCAL_2_B0__FLC_SW_CAP_SET__SHIFT 15 +#define FCAL_2_B0__FLC_SW_CAP_SET__WIDTH 1 +#define FCAL_2_B0__FLC_SW_CAP_SET__MASK 0x00008000U +#define FCAL_2_B0__FLC_SW_CAP_SET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define FCAL_2_B0__FLC_SW_CAP_SET__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define FCAL_2_B0__FLC_SW_CAP_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define FCAL_2_B0__FLC_SW_CAP_SET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define FCAL_2_B0__FLC_SW_CAP_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define FCAL_2_B0__FLC_SW_CAP_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field flc_meas_win */ +#define FCAL_2_B0__FLC_MEAS_WIN__SHIFT 16 +#define FCAL_2_B0__FLC_MEAS_WIN__WIDTH 3 +#define FCAL_2_B0__FLC_MEAS_WIN__MASK 0x00070000U +#define FCAL_2_B0__FLC_MEAS_WIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define FCAL_2_B0__FLC_MEAS_WIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define FCAL_2_B0__FLC_MEAS_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define FCAL_2_B0__FLC_MEAS_WIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field flc_cap_val_status_0 */ +#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__SHIFT 20 +#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__WIDTH 5 +#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__MASK 0x01f00000U +#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define FCAL_2_B0__TYPE u_int32_t +#define FCAL_2_B0__READ 0x01f7ffffU +#define FCAL_2_B0__WRITE 0x01f7ffffU + +#endif /* __FCAL_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_fcal_2_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_FCAL_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b0 */ +#ifndef __DFT_TONE_CTRL_B0_MACRO__ +#define __DFT_TONE_CTRL_B0_MACRO__ + +/* macros for field dft_tone_en_0 */ +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__SHIFT 0 +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__WIDTH 1 +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__MASK 0x00000001U +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dft_tone_amp_sel_0 */ +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__SHIFT 2 +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__WIDTH 2 +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__MASK 0x0000000cU +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field dft_tone_freq_ang_0 */ +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__SHIFT 4 +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__WIDTH 9 +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__MASK 0x00001ff0U +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001ff0U) >> 4) +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001ff0U) | (((u_int32_t)(src) <<\ + 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00001ff0U))) +#define DFT_TONE_CTRL_B0__TYPE u_int32_t +#define DFT_TONE_CTRL_B0__READ 0x00001ffdU +#define DFT_TONE_CTRL_B0__WRITE 0x00001ffdU + +#endif /* __DFT_TONE_CTRL_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_dft_tone_ctrl_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_DFT_TONE_CTRL_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_cal_ctrl */ +#ifndef __CL_CAL_CTRL_MACRO__ +#define __CL_CAL_CTRL_MACRO__ + +/* macros for field enable_parallel_cal */ +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__SHIFT 0 +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__WIDTH 1 +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__MASK 0x00000001U +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field enable_cl_calibrate */ +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__SHIFT 1 +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__WIDTH 1 +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__MASK 0x00000002U +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field cf_clc_test_point */ +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__SHIFT 2 +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__WIDTH 2 +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__MASK 0x0000000cU +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field cf_clc_forced_pagain */ +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__SHIFT 4 +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__WIDTH 4 +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__MASK 0x000000f0U +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field carr_leak_max_offset */ +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__SHIFT 8 +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__WIDTH 8 +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__MASK 0x0000ff00U +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field cf_clc_init_bbgain */ +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__SHIFT 16 +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__WIDTH 6 +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__MASK 0x003f0000U +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field cf_adc_bound */ +#define CL_CAL_CTRL__CF_ADC_BOUND__SHIFT 22 +#define CL_CAL_CTRL__CF_ADC_BOUND__WIDTH 8 +#define CL_CAL_CTRL__CF_ADC_BOUND__MASK 0x3fc00000U +#define CL_CAL_CTRL__CF_ADC_BOUND__READ(src) \ + (((u_int32_t)(src)\ + & 0x3fc00000U) >> 22) +#define CL_CAL_CTRL__CF_ADC_BOUND__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x3fc00000U) +#define CL_CAL_CTRL__CF_ADC_BOUND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x3fc00000U) +#define CL_CAL_CTRL__CF_ADC_BOUND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x3fc00000U))) + +/* macros for field use_dac_cl_correction */ +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__SHIFT 30 +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__WIDTH 1 +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__MASK 0x40000000U +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field cl_map_hw_gen */ +#define CL_CAL_CTRL__CL_MAP_HW_GEN__SHIFT 31 +#define CL_CAL_CTRL__CL_MAP_HW_GEN__WIDTH 1 +#define CL_CAL_CTRL__CL_MAP_HW_GEN__MASK 0x80000000U +#define CL_CAL_CTRL__CL_MAP_HW_GEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define CL_CAL_CTRL__CL_MAP_HW_GEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define CL_CAL_CTRL__CL_MAP_HW_GEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define CL_CAL_CTRL__CL_MAP_HW_GEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define CL_CAL_CTRL__CL_MAP_HW_GEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define CL_CAL_CTRL__CL_MAP_HW_GEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define CL_CAL_CTRL__TYPE u_int32_t +#define CL_CAL_CTRL__READ 0xffffffffU +#define CL_CAL_CTRL__WRITE 0xffffffffU + +#endif /* __CL_CAL_CTRL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cl_cal_ctrl */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CL_CAL_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_0 */ +#ifndef __CL_MAP_0_MACRO__ +#define __CL_MAP_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_0__TYPE u_int32_t +#define CL_MAP_0__READ 0xffffffffU +#define CL_MAP_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cl_map_0_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CL_MAP_0_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_1 */ +#ifndef __CL_MAP_1_MACRO__ +#define __CL_MAP_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_1__TYPE u_int32_t +#define CL_MAP_1__READ 0xffffffffU +#define CL_MAP_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cl_map_1_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CL_MAP_1_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_2 */ +#ifndef __CL_MAP_2_MACRO__ +#define __CL_MAP_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_2__TYPE u_int32_t +#define CL_MAP_2__READ 0xffffffffU +#define CL_MAP_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cl_map_2_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CL_MAP_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_3 */ +#ifndef __CL_MAP_3_MACRO__ +#define __CL_MAP_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_3__TYPE u_int32_t +#define CL_MAP_3__READ 0xffffffffU +#define CL_MAP_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cl_map_3_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CL_MAP_3_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */ +#ifndef __CL_MAP_PAL_0_MACRO__ +#define __CL_MAP_PAL_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_PAL_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_PAL_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_PAL_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_0__TYPE u_int32_t +#define CL_MAP_PAL_0__READ 0xffffffffU +#define CL_MAP_PAL_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cl_map_pal_0_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CL_MAP_PAL_0_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */ +#ifndef __CL_MAP_PAL_1_MACRO__ +#define __CL_MAP_PAL_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_PAL_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_PAL_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_PAL_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_1__TYPE u_int32_t +#define CL_MAP_PAL_1__READ 0xffffffffU +#define CL_MAP_PAL_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cl_map_pal_1_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CL_MAP_PAL_1_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */ +#ifndef __CL_MAP_PAL_2_MACRO__ +#define __CL_MAP_PAL_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_PAL_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_PAL_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_PAL_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_2__TYPE u_int32_t +#define CL_MAP_PAL_2__READ 0xffffffffU +#define CL_MAP_PAL_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cl_map_pal_2_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CL_MAP_PAL_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */ +#ifndef __CL_MAP_PAL_3_MACRO__ +#define __CL_MAP_PAL_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_PAL_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_PAL_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_PAL_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_3__TYPE u_int32_t +#define CL_MAP_PAL_3__READ 0xffffffffU +#define CL_MAP_PAL_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cl_map_pal_3_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CL_MAP_PAL_3_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_tab */ +#ifndef __CL_TAB_MACRO__ +#define __CL_TAB_MACRO__ + +/* macros for field cl_gain_mod */ +#define CL_TAB__CL_GAIN_MOD__SHIFT 0 +#define CL_TAB__CL_GAIN_MOD__WIDTH 5 +#define CL_TAB__CL_GAIN_MOD__MASK 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field carr_lk_dc_add_Q */ +#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT 5 +#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_Q__MASK 0x0000ffe0U +#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ffe0U) >> 5) +#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffe0U) | (((u_int32_t)(src) <<\ + 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x0000ffe0U))) + +/* macros for field carr_lk_dc_add_I */ +#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT 16 +#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_I__MASK 0x07ff0000U +#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) + +/* macros for field bb_gain */ +#define CL_TAB__BB_GAIN__SHIFT 27 +#define CL_TAB__BB_GAIN__WIDTH 4 +#define CL_TAB__BB_GAIN__MASK 0x78000000U +#define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) +#define CL_TAB__TYPE u_int32_t +#define CL_TAB__READ 0x7fffffffU +#define CL_TAB__WRITE 0x7fffffffU + +#endif /* __CL_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cl_tab_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CL_TAB_B0__NUM 16 + +/* macros for BlueprintGlobalNameSpace::synth_control */ +#ifndef __SYNTH_CONTROL_MACRO__ +#define __SYNTH_CONTROL_MACRO__ + +/* macros for field rfchanFrac */ +#define SYNTH_CONTROL__RFCHANFRAC__SHIFT 0 +#define SYNTH_CONTROL__RFCHANFRAC__WIDTH 17 +#define SYNTH_CONTROL__RFCHANFRAC__MASK 0x0001ffffU +#define SYNTH_CONTROL__RFCHANFRAC__READ(src) (u_int32_t)(src) & 0x0001ffffU +#define SYNTH_CONTROL__RFCHANFRAC__WRITE(src) ((u_int32_t)(src) & 0x0001ffffU) +#define SYNTH_CONTROL__RFCHANFRAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ffffU) | ((u_int32_t)(src) &\ + 0x0001ffffU) +#define SYNTH_CONTROL__RFCHANFRAC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0001ffffU))) + +/* macros for field rfchannel */ +#define SYNTH_CONTROL__RFCHANNEL__SHIFT 17 +#define SYNTH_CONTROL__RFCHANNEL__WIDTH 9 +#define SYNTH_CONTROL__RFCHANNEL__MASK 0x03fe0000U +#define SYNTH_CONTROL__RFCHANNEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x03fe0000U) >> 17) +#define SYNTH_CONTROL__RFCHANNEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x03fe0000U) +#define SYNTH_CONTROL__RFCHANNEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x03fe0000U) +#define SYNTH_CONTROL__RFCHANNEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x03fe0000U))) + +/* macros for field rfAmodeRefSel */ +#define SYNTH_CONTROL__RFAMODEREFSEL__SHIFT 26 +#define SYNTH_CONTROL__RFAMODEREFSEL__WIDTH 2 +#define SYNTH_CONTROL__RFAMODEREFSEL__MASK 0x0c000000U +#define SYNTH_CONTROL__RFAMODEREFSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0c000000U) >> 26) +#define SYNTH_CONTROL__RFAMODEREFSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x0c000000U) +#define SYNTH_CONTROL__RFAMODEREFSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define SYNTH_CONTROL__RFAMODEREFSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) + +/* macros for field rfFracmode */ +#define SYNTH_CONTROL__RFFRACMODE__SHIFT 28 +#define SYNTH_CONTROL__RFFRACMODE__WIDTH 1 +#define SYNTH_CONTROL__RFFRACMODE__MASK 0x10000000U +#define SYNTH_CONTROL__RFFRACMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define SYNTH_CONTROL__RFFRACMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define SYNTH_CONTROL__RFFRACMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define SYNTH_CONTROL__RFFRACMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define SYNTH_CONTROL__RFFRACMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define SYNTH_CONTROL__RFFRACMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field rfbmode */ +#define SYNTH_CONTROL__RFBMODE__SHIFT 29 +#define SYNTH_CONTROL__RFBMODE__WIDTH 1 +#define SYNTH_CONTROL__RFBMODE__MASK 0x20000000U +#define SYNTH_CONTROL__RFBMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define SYNTH_CONTROL__RFBMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define SYNTH_CONTROL__RFBMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define SYNTH_CONTROL__RFBMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define SYNTH_CONTROL__RFBMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define SYNTH_CONTROL__RFBMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field rfsynth_ctrl_sshift */ +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__SHIFT 30 +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__WIDTH 1 +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__MASK 0x40000000U +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define SYNTH_CONTROL__TYPE u_int32_t +#define SYNTH_CONTROL__READ 0x7fffffffU +#define SYNTH_CONTROL__WRITE 0x7fffffffU + +#endif /* __SYNTH_CONTROL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_synth_control */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_SYNTH_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::addac_clk_select */ +#ifndef __ADDAC_CLK_SELECT_MACRO__ +#define __ADDAC_CLK_SELECT_MACRO__ + +/* macros for field bb_dac_clk_select */ +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__SHIFT 1 +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__WIDTH 3 +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__MASK 0x0000000eU +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field bb_adc_clk_select */ +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__SHIFT 4 +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__WIDTH 4 +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__MASK 0x000000f0U +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) +#define ADDAC_CLK_SELECT__TYPE u_int32_t +#define ADDAC_CLK_SELECT__READ 0x000000feU +#define ADDAC_CLK_SELECT__WRITE 0x000000feU + +#endif /* __ADDAC_CLK_SELECT_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_addac_clk_select */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_ADDAC_CLK_SELECT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pll_cntl */ +#ifndef __PLL_CNTL_MACRO__ +#define __PLL_CNTL_MACRO__ + +/* macros for field bb_pll_div */ +#define PLL_CNTL__BB_PLL_DIV__SHIFT 0 +#define PLL_CNTL__BB_PLL_DIV__WIDTH 10 +#define PLL_CNTL__BB_PLL_DIV__MASK 0x000003ffU +#define PLL_CNTL__BB_PLL_DIV__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PLL_CNTL__BB_PLL_DIV__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PLL_CNTL__BB_PLL_DIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PLL_CNTL__BB_PLL_DIV__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field bb_pll_refdiv */ +#define PLL_CNTL__BB_PLL_REFDIV__SHIFT 10 +#define PLL_CNTL__BB_PLL_REFDIV__WIDTH 4 +#define PLL_CNTL__BB_PLL_REFDIV__MASK 0x00003c00U +#define PLL_CNTL__BB_PLL_REFDIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003c00U) >> 10) +#define PLL_CNTL__BB_PLL_REFDIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00003c00U) +#define PLL_CNTL__BB_PLL_REFDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00003c00U) +#define PLL_CNTL__BB_PLL_REFDIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00003c00U))) + +/* macros for field bb_pll_clk_sel */ +#define PLL_CNTL__BB_PLL_CLK_SEL__SHIFT 14 +#define PLL_CNTL__BB_PLL_CLK_SEL__WIDTH 2 +#define PLL_CNTL__BB_PLL_CLK_SEL__MASK 0x0000c000U +#define PLL_CNTL__BB_PLL_CLK_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define PLL_CNTL__BB_PLL_CLK_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define PLL_CNTL__BB_PLL_CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define PLL_CNTL__BB_PLL_CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field bb_pllbypass */ +#define PLL_CNTL__BB_PLLBYPASS__SHIFT 16 +#define PLL_CNTL__BB_PLLBYPASS__WIDTH 1 +#define PLL_CNTL__BB_PLLBYPASS__MASK 0x00010000U +#define PLL_CNTL__BB_PLLBYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define PLL_CNTL__BB_PLLBYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define PLL_CNTL__BB_PLLBYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define PLL_CNTL__BB_PLLBYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define PLL_CNTL__BB_PLLBYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define PLL_CNTL__BB_PLLBYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field bb_pll_settle_time */ +#define PLL_CNTL__BB_PLL_SETTLE_TIME__SHIFT 17 +#define PLL_CNTL__BB_PLL_SETTLE_TIME__WIDTH 11 +#define PLL_CNTL__BB_PLL_SETTLE_TIME__MASK 0x0ffe0000U +#define PLL_CNTL__BB_PLL_SETTLE_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x0ffe0000U) >> 17) +#define PLL_CNTL__BB_PLL_SETTLE_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x0ffe0000U) +#define PLL_CNTL__BB_PLL_SETTLE_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ffe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x0ffe0000U) +#define PLL_CNTL__BB_PLL_SETTLE_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x0ffe0000U))) +#define PLL_CNTL__TYPE u_int32_t +#define PLL_CNTL__READ 0x0fffffffU +#define PLL_CNTL__WRITE 0x0fffffffU + +#endif /* __PLL_CNTL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_pll_cntl */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PLL_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::analog_swap */ +#ifndef __ANALOG_SWAP_MACRO__ +#define __ANALOG_SWAP_MACRO__ + +/* macros for field analog_rx_swap_cntl */ +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__SHIFT 0 +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__WIDTH 3 +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__MASK 0x00000007U +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field analog_tx_swap_cntl */ +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__SHIFT 3 +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__WIDTH 3 +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__MASK 0x00000038U +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field swap_alt_chn */ +#define ANALOG_SWAP__SWAP_ALT_CHN__SHIFT 6 +#define ANALOG_SWAP__SWAP_ALT_CHN__WIDTH 1 +#define ANALOG_SWAP__SWAP_ALT_CHN__MASK 0x00000040U +#define ANALOG_SWAP__SWAP_ALT_CHN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define ANALOG_SWAP__SWAP_ALT_CHN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define ANALOG_SWAP__SWAP_ALT_CHN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define ANALOG_SWAP__SWAP_ALT_CHN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define ANALOG_SWAP__SWAP_ALT_CHN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define ANALOG_SWAP__SWAP_ALT_CHN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field analog_dc_dac_polarity */ +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__SHIFT 7 +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__WIDTH 1 +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__MASK 0x00000080U +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field analog_pkdet_dac_polarity */ +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__SHIFT 8 +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__WIDTH 1 +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__MASK 0x00000100U +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) +#define ANALOG_SWAP__TYPE u_int32_t +#define ANALOG_SWAP__READ 0x000001ffU +#define ANALOG_SWAP__WRITE 0x000001ffU + +#endif /* __ANALOG_SWAP_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_analog_swap */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_ANALOG_SWAP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::addac_parallel_control */ +#ifndef __ADDAC_PARALLEL_CONTROL_MACRO__ +#define __ADDAC_PARALLEL_CONTROL_MACRO__ + +/* macros for field off_daclpmode */ +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__SHIFT 12 +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__MASK 0x00001000U +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field off_pwdDac */ +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__SHIFT 13 +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__MASK 0x00002000U +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field off_pwdAdc */ +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__SHIFT 15 +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__MASK 0x00008000U +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field on_daclpmode */ +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__SHIFT 28 +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__MASK 0x10000000U +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field on_pwdDac */ +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__SHIFT 29 +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__MASK 0x20000000U +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field on_pwdAdc */ +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__SHIFT 31 +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__MASK 0x80000000U +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define ADDAC_PARALLEL_CONTROL__TYPE u_int32_t +#define ADDAC_PARALLEL_CONTROL__READ 0xb000b000U +#define ADDAC_PARALLEL_CONTROL__WRITE 0xb000b000U + +#endif /* __ADDAC_PARALLEL_CONTROL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_addac_parallel_control */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_ADDAC_PARALLEL_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::force_analog */ +#ifndef __FORCE_ANALOG_MACRO__ +#define __FORCE_ANALOG_MACRO__ + +/* macros for field force_xpaon */ +#define FORCE_ANALOG__FORCE_XPAON__SHIFT 0 +#define FORCE_ANALOG__FORCE_XPAON__WIDTH 1 +#define FORCE_ANALOG__FORCE_XPAON__MASK 0x00000001U +#define FORCE_ANALOG__FORCE_XPAON__READ(src) (u_int32_t)(src) & 0x00000001U +#define FORCE_ANALOG__FORCE_XPAON__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define FORCE_ANALOG__FORCE_XPAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define FORCE_ANALOG__FORCE_XPAON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define FORCE_ANALOG__FORCE_XPAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define FORCE_ANALOG__FORCE_XPAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field forced_xpaon */ +#define FORCE_ANALOG__FORCED_XPAON__SHIFT 1 +#define FORCE_ANALOG__FORCED_XPAON__WIDTH 3 +#define FORCE_ANALOG__FORCED_XPAON__MASK 0x0000000eU +#define FORCE_ANALOG__FORCED_XPAON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define FORCE_ANALOG__FORCED_XPAON__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define FORCE_ANALOG__FORCED_XPAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define FORCE_ANALOG__FORCED_XPAON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field force_pdadc_pwd */ +#define FORCE_ANALOG__FORCE_PDADC_PWD__SHIFT 4 +#define FORCE_ANALOG__FORCE_PDADC_PWD__WIDTH 1 +#define FORCE_ANALOG__FORCE_PDADC_PWD__MASK 0x00000010U +#define FORCE_ANALOG__FORCE_PDADC_PWD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define FORCE_ANALOG__FORCE_PDADC_PWD__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define FORCE_ANALOG__FORCE_PDADC_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define FORCE_ANALOG__FORCE_PDADC_PWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define FORCE_ANALOG__FORCE_PDADC_PWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define FORCE_ANALOG__FORCE_PDADC_PWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field forced_pdadc_pwd */ +#define FORCE_ANALOG__FORCED_PDADC_PWD__SHIFT 5 +#define FORCE_ANALOG__FORCED_PDADC_PWD__WIDTH 3 +#define FORCE_ANALOG__FORCED_PDADC_PWD__MASK 0x000000e0U +#define FORCE_ANALOG__FORCED_PDADC_PWD__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define FORCE_ANALOG__FORCED_PDADC_PWD__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define FORCE_ANALOG__FORCED_PDADC_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define FORCE_ANALOG__FORCED_PDADC_PWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) +#define FORCE_ANALOG__TYPE u_int32_t +#define FORCE_ANALOG__READ 0x000000ffU +#define FORCE_ANALOG__WRITE 0x000000ffU + +#endif /* __FORCE_ANALOG_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_force_analog */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_FORCE_ANALOG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::test_controls */ +#ifndef __TEST_CONTROLS_MACRO__ +#define __TEST_CONTROLS_MACRO__ + +/* macros for field cf_tsttrig_sel */ +#define TEST_CONTROLS__CF_TSTTRIG_SEL__SHIFT 0 +#define TEST_CONTROLS__CF_TSTTRIG_SEL__WIDTH 4 +#define TEST_CONTROLS__CF_TSTTRIG_SEL__MASK 0x0000000fU +#define TEST_CONTROLS__CF_TSTTRIG_SEL__READ(src) (u_int32_t)(src) & 0x0000000fU +#define TEST_CONTROLS__CF_TSTTRIG_SEL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define TEST_CONTROLS__CF_TSTTRIG_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define TEST_CONTROLS__CF_TSTTRIG_SEL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field cf_tsttrig */ +#define TEST_CONTROLS__CF_TSTTRIG__SHIFT 4 +#define TEST_CONTROLS__CF_TSTTRIG__WIDTH 1 +#define TEST_CONTROLS__CF_TSTTRIG__MASK 0x00000010U +#define TEST_CONTROLS__CF_TSTTRIG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define TEST_CONTROLS__CF_TSTTRIG__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define TEST_CONTROLS__CF_TSTTRIG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define TEST_CONTROLS__CF_TSTTRIG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define TEST_CONTROLS__CF_TSTTRIG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define TEST_CONTROLS__CF_TSTTRIG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field cf_rfshift_sel */ +#define TEST_CONTROLS__CF_RFSHIFT_SEL__SHIFT 5 +#define TEST_CONTROLS__CF_RFSHIFT_SEL__WIDTH 2 +#define TEST_CONTROLS__CF_RFSHIFT_SEL__MASK 0x00000060U +#define TEST_CONTROLS__CF_RFSHIFT_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000060U) >> 5) +#define TEST_CONTROLS__CF_RFSHIFT_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000060U) +#define TEST_CONTROLS__CF_RFSHIFT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((u_int32_t)(src) <<\ + 5) & 0x00000060U) +#define TEST_CONTROLS__CF_RFSHIFT_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000060U))) + +/* macros for field cardbus_mode */ +#define TEST_CONTROLS__CARDBUS_MODE__SHIFT 8 +#define TEST_CONTROLS__CARDBUS_MODE__WIDTH 2 +#define TEST_CONTROLS__CARDBUS_MODE__MASK 0x00000300U +#define TEST_CONTROLS__CARDBUS_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define TEST_CONTROLS__CARDBUS_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define TEST_CONTROLS__CARDBUS_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define TEST_CONTROLS__CARDBUS_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field clkout_is_clk32 */ +#define TEST_CONTROLS__CLKOUT_IS_CLK32__SHIFT 10 +#define TEST_CONTROLS__CLKOUT_IS_CLK32__WIDTH 1 +#define TEST_CONTROLS__CLKOUT_IS_CLK32__MASK 0x00000400U +#define TEST_CONTROLS__CLKOUT_IS_CLK32__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define TEST_CONTROLS__CLKOUT_IS_CLK32__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define TEST_CONTROLS__CLKOUT_IS_CLK32__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TEST_CONTROLS__CLKOUT_IS_CLK32__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TEST_CONTROLS__CLKOUT_IS_CLK32__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TEST_CONTROLS__CLKOUT_IS_CLK32__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field enable_rfsilent_bb */ +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__SHIFT 13 +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__WIDTH 1 +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__MASK 0x00002000U +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field enable_mini_obs */ +#define TEST_CONTROLS__ENABLE_MINI_OBS__SHIFT 15 +#define TEST_CONTROLS__ENABLE_MINI_OBS__WIDTH 1 +#define TEST_CONTROLS__ENABLE_MINI_OBS__MASK 0x00008000U +#define TEST_CONTROLS__ENABLE_MINI_OBS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TEST_CONTROLS__ENABLE_MINI_OBS__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TEST_CONTROLS__ENABLE_MINI_OBS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TEST_CONTROLS__ENABLE_MINI_OBS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TEST_CONTROLS__ENABLE_MINI_OBS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TEST_CONTROLS__ENABLE_MINI_OBS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field slow_clk160 */ +#define TEST_CONTROLS__SLOW_CLK160__SHIFT 17 +#define TEST_CONTROLS__SLOW_CLK160__WIDTH 1 +#define TEST_CONTROLS__SLOW_CLK160__MASK 0x00020000U +#define TEST_CONTROLS__SLOW_CLK160__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define TEST_CONTROLS__SLOW_CLK160__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define TEST_CONTROLS__SLOW_CLK160__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define TEST_CONTROLS__SLOW_CLK160__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define TEST_CONTROLS__SLOW_CLK160__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define TEST_CONTROLS__SLOW_CLK160__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field agc_obs_sel_3 */ +#define TEST_CONTROLS__AGC_OBS_SEL_3__SHIFT 18 +#define TEST_CONTROLS__AGC_OBS_SEL_3__WIDTH 1 +#define TEST_CONTROLS__AGC_OBS_SEL_3__MASK 0x00040000U +#define TEST_CONTROLS__AGC_OBS_SEL_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define TEST_CONTROLS__AGC_OBS_SEL_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define TEST_CONTROLS__AGC_OBS_SEL_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define TEST_CONTROLS__AGC_OBS_SEL_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define TEST_CONTROLS__AGC_OBS_SEL_3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define TEST_CONTROLS__AGC_OBS_SEL_3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field cf_bbb_obs_sel */ +#define TEST_CONTROLS__CF_BBB_OBS_SEL__SHIFT 19 +#define TEST_CONTROLS__CF_BBB_OBS_SEL__WIDTH 4 +#define TEST_CONTROLS__CF_BBB_OBS_SEL__MASK 0x00780000U +#define TEST_CONTROLS__CF_BBB_OBS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00780000U) >> 19) +#define TEST_CONTROLS__CF_BBB_OBS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00780000U) +#define TEST_CONTROLS__CF_BBB_OBS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00780000U) | (((u_int32_t)(src) <<\ + 19) & 0x00780000U) +#define TEST_CONTROLS__CF_BBB_OBS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00780000U))) + +/* macros for field rx_obs_sel_5th_bit */ +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__SHIFT 23 +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__WIDTH 1 +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__MASK 0x00800000U +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field agc_obs_sel_4 */ +#define TEST_CONTROLS__AGC_OBS_SEL_4__SHIFT 24 +#define TEST_CONTROLS__AGC_OBS_SEL_4__WIDTH 1 +#define TEST_CONTROLS__AGC_OBS_SEL_4__MASK 0x01000000U +#define TEST_CONTROLS__AGC_OBS_SEL_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TEST_CONTROLS__AGC_OBS_SEL_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TEST_CONTROLS__AGC_OBS_SEL_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TEST_CONTROLS__AGC_OBS_SEL_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TEST_CONTROLS__AGC_OBS_SEL_4__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TEST_CONTROLS__AGC_OBS_SEL_4__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field force_agc_clear */ +#define TEST_CONTROLS__FORCE_AGC_CLEAR__SHIFT 28 +#define TEST_CONTROLS__FORCE_AGC_CLEAR__WIDTH 1 +#define TEST_CONTROLS__FORCE_AGC_CLEAR__MASK 0x10000000U +#define TEST_CONTROLS__FORCE_AGC_CLEAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define TEST_CONTROLS__FORCE_AGC_CLEAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TEST_CONTROLS__FORCE_AGC_CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TEST_CONTROLS__FORCE_AGC_CLEAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TEST_CONTROLS__FORCE_AGC_CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TEST_CONTROLS__FORCE_AGC_CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field tstdac_out_sel */ +#define TEST_CONTROLS__TSTDAC_OUT_SEL__SHIFT 30 +#define TEST_CONTROLS__TSTDAC_OUT_SEL__WIDTH 2 +#define TEST_CONTROLS__TSTDAC_OUT_SEL__MASK 0xc0000000U +#define TEST_CONTROLS__TSTDAC_OUT_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define TEST_CONTROLS__TSTDAC_OUT_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define TEST_CONTROLS__TSTDAC_OUT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define TEST_CONTROLS__TSTDAC_OUT_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define TEST_CONTROLS__TYPE u_int32_t +#define TEST_CONTROLS__READ 0xd1fea77fU +#define TEST_CONTROLS__WRITE 0xd1fea77fU + +#endif /* __TEST_CONTROLS_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_test_controls */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TEST_CONTROLS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::test_controls_status */ +#ifndef __TEST_CONTROLS_STATUS_MACRO__ +#define __TEST_CONTROLS_STATUS_MACRO__ + +/* macros for field cf_tstdac_en */ +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__SHIFT 0 +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__MASK 0x00000001U +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_tx_src_is_tstdac */ +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__SHIFT 1 +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__MASK 0x00000002U +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field cf_tx_obs_sel */ +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__SHIFT 2 +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__WIDTH 3 +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__MASK 0x0000001cU +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field cf_tx_obs_mux_sel */ +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__SHIFT 5 +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__WIDTH 2 +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__MASK 0x00000060U +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000060U) >> 5) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000060U) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((u_int32_t)(src) <<\ + 5) & 0x00000060U) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000060U))) + +/* macros for field cf_tx_src_alternate */ +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__SHIFT 7 +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__MASK 0x00000080U +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field cf_tstadc_en */ +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__SHIFT 8 +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__MASK 0x00000100U +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field cf_rx_src_is_tstadc */ +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__SHIFT 9 +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__MASK 0x00000200U +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field rx_obs_sel */ +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__SHIFT 10 +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__WIDTH 4 +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__MASK 0x00003c00U +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003c00U) >> 10) +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00003c00U) +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00003c00U) +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00003c00U))) + +/* macros for field disable_a2_warm_reset */ +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__SHIFT 14 +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__WIDTH 1 +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__MASK 0x00004000U +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field reset_a2 */ +#define TEST_CONTROLS_STATUS__RESET_A2__SHIFT 15 +#define TEST_CONTROLS_STATUS__RESET_A2__WIDTH 1 +#define TEST_CONTROLS_STATUS__RESET_A2__MASK 0x00008000U +#define TEST_CONTROLS_STATUS__RESET_A2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TEST_CONTROLS_STATUS__RESET_A2__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TEST_CONTROLS_STATUS__RESET_A2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TEST_CONTROLS_STATUS__RESET_A2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TEST_CONTROLS_STATUS__RESET_A2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TEST_CONTROLS_STATUS__RESET_A2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field agc_obs_sel */ +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__SHIFT 16 +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__WIDTH 3 +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__MASK 0x00070000U +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field cf_enable_fft_dump */ +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__SHIFT 19 +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__MASK 0x00080000U +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field cf_debugport_in */ +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__SHIFT 23 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__MASK 0x00800000U +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field disable_agc_to_a2 */ +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__SHIFT 27 +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__WIDTH 1 +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__MASK 0x08000000U +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field cf_debugport_en */ +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__SHIFT 28 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__MASK 0x10000000U +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field cf_debugport_sel */ +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__SHIFT 29 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__WIDTH 3 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__MASK 0xe0000000U +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define TEST_CONTROLS_STATUS__TYPE u_int32_t +#define TEST_CONTROLS_STATUS__READ 0xf88fffffU +#define TEST_CONTROLS_STATUS__WRITE 0xf88fffffU + +#endif /* __TEST_CONTROLS_STATUS_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_test_controls_status */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TEST_CONTROLS_STATUS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tstdac */ +#ifndef __TSTDAC_MACRO__ +#define __TSTDAC_MACRO__ + +/* macros for field tstdac_out_q */ +#define TSTDAC__TSTDAC_OUT_Q__SHIFT 0 +#define TSTDAC__TSTDAC_OUT_Q__WIDTH 10 +#define TSTDAC__TSTDAC_OUT_Q__MASK 0x000003ffU +#define TSTDAC__TSTDAC_OUT_Q__READ(src) (u_int32_t)(src) & 0x000003ffU + +/* macros for field tstdac_out_i */ +#define TSTDAC__TSTDAC_OUT_I__SHIFT 10 +#define TSTDAC__TSTDAC_OUT_I__WIDTH 10 +#define TSTDAC__TSTDAC_OUT_I__MASK 0x000ffc00U +#define TSTDAC__TSTDAC_OUT_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define TSTDAC__TYPE u_int32_t +#define TSTDAC__READ 0x000fffffU + +#endif /* __TSTDAC_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tstdac */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TSTDAC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::channel_status */ +#ifndef __CHANNEL_STATUS_MACRO__ +#define __CHANNEL_STATUS_MACRO__ + +/* macros for field bt_active */ +#define CHANNEL_STATUS__BT_ACTIVE__SHIFT 0 +#define CHANNEL_STATUS__BT_ACTIVE__WIDTH 1 +#define CHANNEL_STATUS__BT_ACTIVE__MASK 0x00000001U +#define CHANNEL_STATUS__BT_ACTIVE__READ(src) (u_int32_t)(src) & 0x00000001U +#define CHANNEL_STATUS__BT_ACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define CHANNEL_STATUS__BT_ACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field rx_clear_raw */ +#define CHANNEL_STATUS__RX_CLEAR_RAW__SHIFT 1 +#define CHANNEL_STATUS__RX_CLEAR_RAW__WIDTH 1 +#define CHANNEL_STATUS__RX_CLEAR_RAW__MASK 0x00000002U +#define CHANNEL_STATUS__RX_CLEAR_RAW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define CHANNEL_STATUS__RX_CLEAR_RAW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define CHANNEL_STATUS__RX_CLEAR_RAW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field rx_clear_mac */ +#define CHANNEL_STATUS__RX_CLEAR_MAC__SHIFT 2 +#define CHANNEL_STATUS__RX_CLEAR_MAC__WIDTH 1 +#define CHANNEL_STATUS__RX_CLEAR_MAC__MASK 0x00000004U +#define CHANNEL_STATUS__RX_CLEAR_MAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define CHANNEL_STATUS__RX_CLEAR_MAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define CHANNEL_STATUS__RX_CLEAR_MAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field rx_clear_pad */ +#define CHANNEL_STATUS__RX_CLEAR_PAD__SHIFT 3 +#define CHANNEL_STATUS__RX_CLEAR_PAD__WIDTH 1 +#define CHANNEL_STATUS__RX_CLEAR_PAD__MASK 0x00000008U +#define CHANNEL_STATUS__RX_CLEAR_PAD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define CHANNEL_STATUS__RX_CLEAR_PAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define CHANNEL_STATUS__RX_CLEAR_PAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field bb_sw_out_0 */ +#define CHANNEL_STATUS__BB_SW_OUT_0__SHIFT 4 +#define CHANNEL_STATUS__BB_SW_OUT_0__WIDTH 2 +#define CHANNEL_STATUS__BB_SW_OUT_0__MASK 0x00000030U +#define CHANNEL_STATUS__BB_SW_OUT_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) + +/* macros for field bb_sw_out_1 */ +#define CHANNEL_STATUS__BB_SW_OUT_1__SHIFT 6 +#define CHANNEL_STATUS__BB_SW_OUT_1__WIDTH 2 +#define CHANNEL_STATUS__BB_SW_OUT_1__MASK 0x000000c0U +#define CHANNEL_STATUS__BB_SW_OUT_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) + +/* macros for field bb_sw_out_2 */ +#define CHANNEL_STATUS__BB_SW_OUT_2__SHIFT 8 +#define CHANNEL_STATUS__BB_SW_OUT_2__WIDTH 2 +#define CHANNEL_STATUS__BB_SW_OUT_2__MASK 0x00000300U +#define CHANNEL_STATUS__BB_SW_OUT_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) + +/* macros for field bb_sw_com_out */ +#define CHANNEL_STATUS__BB_SW_COM_OUT__SHIFT 10 +#define CHANNEL_STATUS__BB_SW_COM_OUT__WIDTH 4 +#define CHANNEL_STATUS__BB_SW_COM_OUT__MASK 0x00003c00U +#define CHANNEL_STATUS__BB_SW_COM_OUT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003c00U) >> 10) + +/* macros for field ant_div_cfg_used */ +#define CHANNEL_STATUS__ANT_DIV_CFG_USED__SHIFT 14 +#define CHANNEL_STATUS__ANT_DIV_CFG_USED__WIDTH 3 +#define CHANNEL_STATUS__ANT_DIV_CFG_USED__MASK 0x0001c000U +#define CHANNEL_STATUS__ANT_DIV_CFG_USED__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define CHANNEL_STATUS__TYPE u_int32_t +#define CHANNEL_STATUS__READ 0x0001ffffU + +#endif /* __CHANNEL_STATUS_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_channel_status */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CHANNEL_STATUS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chaninfo_ctrl */ +#ifndef __CHANINFO_CTRL_MACRO__ +#define __CHANINFO_CTRL_MACRO__ + +/* macros for field capture_chan_info */ +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__SHIFT 0 +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__WIDTH 1 +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__MASK 0x00000001U +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field disable_chaninfomem */ +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__SHIFT 1 +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__WIDTH 1 +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__MASK 0x00000002U +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field capture_sounding_packet */ +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__SHIFT 2 +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__WIDTH 1 +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__MASK 0x00000004U +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field chaninfomem_s2_read */ +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__SHIFT 3 +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__WIDTH 1 +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__MASK 0x00000008U +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define CHANINFO_CTRL__TYPE u_int32_t +#define CHANINFO_CTRL__READ 0x0000000fU +#define CHANINFO_CTRL__WRITE 0x0000000fU + +#endif /* __CHANINFO_CTRL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_chaninfo_ctrl */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CHANINFO_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chan_info_noise_pwr */ +#ifndef __CHAN_INFO_NOISE_PWR_MACRO__ +#define __CHAN_INFO_NOISE_PWR_MACRO__ + +/* macros for field noise_power */ +#define CHAN_INFO_NOISE_PWR__NOISE_POWER__SHIFT 0 +#define CHAN_INFO_NOISE_PWR__NOISE_POWER__WIDTH 12 +#define CHAN_INFO_NOISE_PWR__NOISE_POWER__MASK 0x00000fffU +#define CHAN_INFO_NOISE_PWR__NOISE_POWER__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define CHAN_INFO_NOISE_PWR__TYPE u_int32_t +#define CHAN_INFO_NOISE_PWR__READ 0x00000fffU + +#endif /* __CHAN_INFO_NOISE_PWR_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_chan_info_noise_pwr */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CHAN_INFO_NOISE_PWR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chan_info_gain_diff */ +#ifndef __CHAN_INFO_GAIN_DIFF_MACRO__ +#define __CHAN_INFO_GAIN_DIFF_MACRO__ + +/* macros for field fine_ppm */ +#define CHAN_INFO_GAIN_DIFF__FINE_PPM__SHIFT 0 +#define CHAN_INFO_GAIN_DIFF__FINE_PPM__WIDTH 12 +#define CHAN_INFO_GAIN_DIFF__FINE_PPM__MASK 0x00000fffU +#define CHAN_INFO_GAIN_DIFF__FINE_PPM__READ(src) (u_int32_t)(src) & 0x00000fffU + +/* macros for field analog_gain_diff_01 */ +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__SHIFT 12 +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__WIDTH 7 +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__MASK 0x0007f000U +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__READ(src) \ + (((u_int32_t)(src)\ + & 0x0007f000U) >> 12) + +/* macros for field analog_gain_diff_02 */ +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__SHIFT 19 +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__WIDTH 7 +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__MASK 0x03f80000U +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__READ(src) \ + (((u_int32_t)(src)\ + & 0x03f80000U) >> 19) +#define CHAN_INFO_GAIN_DIFF__TYPE u_int32_t +#define CHAN_INFO_GAIN_DIFF__READ 0x03ffffffU + +#endif /* __CHAN_INFO_GAIN_DIFF_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_chan_info_gain_diff */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CHAN_INFO_GAIN_DIFF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chan_info_fine_timing */ +#ifndef __CHAN_INFO_FINE_TIMING_MACRO__ +#define __CHAN_INFO_FINE_TIMING_MACRO__ + +/* macros for field coarse_ppm */ +#define CHAN_INFO_FINE_TIMING__COARSE_PPM__SHIFT 0 +#define CHAN_INFO_FINE_TIMING__COARSE_PPM__WIDTH 12 +#define CHAN_INFO_FINE_TIMING__COARSE_PPM__MASK 0x00000fffU +#define CHAN_INFO_FINE_TIMING__COARSE_PPM__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU + +/* macros for field fine_timing */ +#define CHAN_INFO_FINE_TIMING__FINE_TIMING__SHIFT 12 +#define CHAN_INFO_FINE_TIMING__FINE_TIMING__WIDTH 10 +#define CHAN_INFO_FINE_TIMING__FINE_TIMING__MASK 0x003ff000U +#define CHAN_INFO_FINE_TIMING__FINE_TIMING__READ(src) \ + (((u_int32_t)(src)\ + & 0x003ff000U) >> 12) +#define CHAN_INFO_FINE_TIMING__TYPE u_int32_t +#define CHAN_INFO_FINE_TIMING__READ 0x003fffffU + +#endif /* __CHAN_INFO_FINE_TIMING_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_chan_info_fine_timing */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CHAN_INFO_FINE_TIMING__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chan_info_gain_b0 */ +#ifndef __CHAN_INFO_GAIN_B0_MACRO__ +#define __CHAN_INFO_GAIN_B0_MACRO__ + +/* macros for field chan_info_rssi_0 */ +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__SHIFT 0 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__WIDTH 8 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__MASK 0x000000ffU +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field chan_info_rf_gain_0 */ +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__SHIFT 8 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__WIDTH 8 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__MASK 0x0000ff00U +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field chan_info_mb_gain_0 */ +#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__SHIFT 16 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__WIDTH 7 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__MASK 0x007f0000U +#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) + +/* macros for field chan_info_xatten1_sw_0 */ +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__SHIFT 23 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__WIDTH 1 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__MASK 0x00800000U +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field chan_info_xatten2_sw_0 */ +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__SHIFT 24 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__WIDTH 1 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__MASK 0x01000000U +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define CHAN_INFO_GAIN_B0__TYPE u_int32_t +#define CHAN_INFO_GAIN_B0__READ 0x01ffffffU + +#endif /* __CHAN_INFO_GAIN_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_chan_info_gain_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CHAN_INFO_GAIN_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::scrambler_seed */ +#ifndef __SCRAMBLER_SEED_MACRO__ +#define __SCRAMBLER_SEED_MACRO__ + +/* macros for field fixed_scrambler_seed */ +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__SHIFT 0 +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__WIDTH 7 +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__MASK 0x0000007fU +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define SCRAMBLER_SEED__TYPE u_int32_t +#define SCRAMBLER_SEED__READ 0x0000007fU +#define SCRAMBLER_SEED__WRITE 0x0000007fU + +#endif /* __SCRAMBLER_SEED_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_scrambler_seed */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_SCRAMBLER_SEED__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_tx_ctrl */ +#ifndef __BBB_TX_CTRL_MACRO__ +#define __BBB_TX_CTRL_MACRO__ + +/* macros for field disable_scrambler */ +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__SHIFT 0 +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__WIDTH 1 +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__MASK 0x00000001U +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field use_scrambler_seed */ +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__SHIFT 1 +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__WIDTH 1 +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__MASK 0x00000002U +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field tx_dac_scale_cck */ +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__SHIFT 2 +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__WIDTH 2 +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__MASK 0x0000000cU +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field txfir_japan_cck */ +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__SHIFT 4 +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__WIDTH 1 +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__MASK 0x00000010U +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field allow_1mbps_short */ +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__SHIFT 5 +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__WIDTH 1 +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__MASK 0x00000020U +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field tx_cck_delay_1 */ +#define BBB_TX_CTRL__TX_CCK_DELAY_1__SHIFT 6 +#define BBB_TX_CTRL__TX_CCK_DELAY_1__WIDTH 3 +#define BBB_TX_CTRL__TX_CCK_DELAY_1__MASK 0x000001c0U +#define BBB_TX_CTRL__TX_CCK_DELAY_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001c0U) >> 6) +#define BBB_TX_CTRL__TX_CCK_DELAY_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000001c0U) +#define BBB_TX_CTRL__TX_CCK_DELAY_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define BBB_TX_CTRL__TX_CCK_DELAY_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field tx_cck_delay_2 */ +#define BBB_TX_CTRL__TX_CCK_DELAY_2__SHIFT 9 +#define BBB_TX_CTRL__TX_CCK_DELAY_2__WIDTH 3 +#define BBB_TX_CTRL__TX_CCK_DELAY_2__MASK 0x00000e00U +#define BBB_TX_CTRL__TX_CCK_DELAY_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000e00U) >> 9) +#define BBB_TX_CTRL__TX_CCK_DELAY_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define BBB_TX_CTRL__TX_CCK_DELAY_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define BBB_TX_CTRL__TX_CCK_DELAY_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) +#define BBB_TX_CTRL__TYPE u_int32_t +#define BBB_TX_CTRL__READ 0x00000fffU +#define BBB_TX_CTRL__WRITE 0x00000fffU + +#endif /* __BBB_TX_CTRL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_bbb_tx_ctrl */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_BBB_TX_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_txfir_0 */ +#ifndef __BBB_TXFIR_0_MACRO__ +#define __BBB_TXFIR_0_MACRO__ + +/* macros for field txfir_coeff_h0 */ +#define BBB_TXFIR_0__TXFIR_COEFF_H0__SHIFT 0 +#define BBB_TXFIR_0__TXFIR_COEFF_H0__WIDTH 4 +#define BBB_TXFIR_0__TXFIR_COEFF_H0__MASK 0x0000000fU +#define BBB_TXFIR_0__TXFIR_COEFF_H0__READ(src) (u_int32_t)(src) & 0x0000000fU +#define BBB_TXFIR_0__TXFIR_COEFF_H0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define BBB_TXFIR_0__TXFIR_COEFF_H0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define BBB_TXFIR_0__TXFIR_COEFF_H0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field txfir_coeff_h1 */ +#define BBB_TXFIR_0__TXFIR_COEFF_H1__SHIFT 8 +#define BBB_TXFIR_0__TXFIR_COEFF_H1__WIDTH 4 +#define BBB_TXFIR_0__TXFIR_COEFF_H1__MASK 0x00000f00U +#define BBB_TXFIR_0__TXFIR_COEFF_H1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define BBB_TXFIR_0__TXFIR_COEFF_H1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define BBB_TXFIR_0__TXFIR_COEFF_H1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define BBB_TXFIR_0__TXFIR_COEFF_H1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field txfir_coeff_h2 */ +#define BBB_TXFIR_0__TXFIR_COEFF_H2__SHIFT 16 +#define BBB_TXFIR_0__TXFIR_COEFF_H2__WIDTH 5 +#define BBB_TXFIR_0__TXFIR_COEFF_H2__MASK 0x001f0000U +#define BBB_TXFIR_0__TXFIR_COEFF_H2__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define BBB_TXFIR_0__TXFIR_COEFF_H2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define BBB_TXFIR_0__TXFIR_COEFF_H2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define BBB_TXFIR_0__TXFIR_COEFF_H2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) + +/* macros for field txfir_coeff_h3 */ +#define BBB_TXFIR_0__TXFIR_COEFF_H3__SHIFT 24 +#define BBB_TXFIR_0__TXFIR_COEFF_H3__WIDTH 5 +#define BBB_TXFIR_0__TXFIR_COEFF_H3__MASK 0x1f000000U +#define BBB_TXFIR_0__TXFIR_COEFF_H3__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f000000U) >> 24) +#define BBB_TXFIR_0__TXFIR_COEFF_H3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x1f000000U) +#define BBB_TXFIR_0__TXFIR_COEFF_H3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x1f000000U) +#define BBB_TXFIR_0__TXFIR_COEFF_H3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x1f000000U))) +#define BBB_TXFIR_0__TYPE u_int32_t +#define BBB_TXFIR_0__READ 0x1f1f0f0fU +#define BBB_TXFIR_0__WRITE 0x1f1f0f0fU + +#endif /* __BBB_TXFIR_0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_bbb_txfir_0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_BBB_TXFIR_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_txfir_1 */ +#ifndef __BBB_TXFIR_1_MACRO__ +#define __BBB_TXFIR_1_MACRO__ + +/* macros for field txfir_coeff_h4 */ +#define BBB_TXFIR_1__TXFIR_COEFF_H4__SHIFT 0 +#define BBB_TXFIR_1__TXFIR_COEFF_H4__WIDTH 6 +#define BBB_TXFIR_1__TXFIR_COEFF_H4__MASK 0x0000003fU +#define BBB_TXFIR_1__TXFIR_COEFF_H4__READ(src) (u_int32_t)(src) & 0x0000003fU +#define BBB_TXFIR_1__TXFIR_COEFF_H4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define BBB_TXFIR_1__TXFIR_COEFF_H4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define BBB_TXFIR_1__TXFIR_COEFF_H4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field txfir_coeff_h5 */ +#define BBB_TXFIR_1__TXFIR_COEFF_H5__SHIFT 8 +#define BBB_TXFIR_1__TXFIR_COEFF_H5__WIDTH 6 +#define BBB_TXFIR_1__TXFIR_COEFF_H5__MASK 0x00003f00U +#define BBB_TXFIR_1__TXFIR_COEFF_H5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define BBB_TXFIR_1__TXFIR_COEFF_H5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define BBB_TXFIR_1__TXFIR_COEFF_H5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define BBB_TXFIR_1__TXFIR_COEFF_H5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field txfir_coeff_h6 */ +#define BBB_TXFIR_1__TXFIR_COEFF_H6__SHIFT 16 +#define BBB_TXFIR_1__TXFIR_COEFF_H6__WIDTH 7 +#define BBB_TXFIR_1__TXFIR_COEFF_H6__MASK 0x007f0000U +#define BBB_TXFIR_1__TXFIR_COEFF_H6__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) +#define BBB_TXFIR_1__TXFIR_COEFF_H6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x007f0000U) +#define BBB_TXFIR_1__TXFIR_COEFF_H6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x007f0000U) +#define BBB_TXFIR_1__TXFIR_COEFF_H6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x007f0000U))) + +/* macros for field txfir_coeff_h7 */ +#define BBB_TXFIR_1__TXFIR_COEFF_H7__SHIFT 24 +#define BBB_TXFIR_1__TXFIR_COEFF_H7__WIDTH 7 +#define BBB_TXFIR_1__TXFIR_COEFF_H7__MASK 0x7f000000U +#define BBB_TXFIR_1__TXFIR_COEFF_H7__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f000000U) >> 24) +#define BBB_TXFIR_1__TXFIR_COEFF_H7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define BBB_TXFIR_1__TXFIR_COEFF_H7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define BBB_TXFIR_1__TXFIR_COEFF_H7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) +#define BBB_TXFIR_1__TYPE u_int32_t +#define BBB_TXFIR_1__READ 0x7f7f3f3fU +#define BBB_TXFIR_1__WRITE 0x7f7f3f3fU + +#endif /* __BBB_TXFIR_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_bbb_txfir_1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_BBB_TXFIR_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_txfir_2 */ +#ifndef __BBB_TXFIR_2_MACRO__ +#define __BBB_TXFIR_2_MACRO__ + +/* macros for field txfir_coeff_h8 */ +#define BBB_TXFIR_2__TXFIR_COEFF_H8__SHIFT 0 +#define BBB_TXFIR_2__TXFIR_COEFF_H8__WIDTH 8 +#define BBB_TXFIR_2__TXFIR_COEFF_H8__MASK 0x000000ffU +#define BBB_TXFIR_2__TXFIR_COEFF_H8__READ(src) (u_int32_t)(src) & 0x000000ffU +#define BBB_TXFIR_2__TXFIR_COEFF_H8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define BBB_TXFIR_2__TXFIR_COEFF_H8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define BBB_TXFIR_2__TXFIR_COEFF_H8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txfir_coeff_h9 */ +#define BBB_TXFIR_2__TXFIR_COEFF_H9__SHIFT 8 +#define BBB_TXFIR_2__TXFIR_COEFF_H9__WIDTH 8 +#define BBB_TXFIR_2__TXFIR_COEFF_H9__MASK 0x0000ff00U +#define BBB_TXFIR_2__TXFIR_COEFF_H9__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define BBB_TXFIR_2__TXFIR_COEFF_H9__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define BBB_TXFIR_2__TXFIR_COEFF_H9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define BBB_TXFIR_2__TXFIR_COEFF_H9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txfir_coeff_h10 */ +#define BBB_TXFIR_2__TXFIR_COEFF_H10__SHIFT 16 +#define BBB_TXFIR_2__TXFIR_COEFF_H10__WIDTH 8 +#define BBB_TXFIR_2__TXFIR_COEFF_H10__MASK 0x00ff0000U +#define BBB_TXFIR_2__TXFIR_COEFF_H10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define BBB_TXFIR_2__TXFIR_COEFF_H10__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define BBB_TXFIR_2__TXFIR_COEFF_H10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define BBB_TXFIR_2__TXFIR_COEFF_H10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txfir_coeff_h11 */ +#define BBB_TXFIR_2__TXFIR_COEFF_H11__SHIFT 24 +#define BBB_TXFIR_2__TXFIR_COEFF_H11__WIDTH 8 +#define BBB_TXFIR_2__TXFIR_COEFF_H11__MASK 0xff000000U +#define BBB_TXFIR_2__TXFIR_COEFF_H11__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define BBB_TXFIR_2__TXFIR_COEFF_H11__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define BBB_TXFIR_2__TXFIR_COEFF_H11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define BBB_TXFIR_2__TXFIR_COEFF_H11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define BBB_TXFIR_2__TYPE u_int32_t +#define BBB_TXFIR_2__READ 0xffffffffU +#define BBB_TXFIR_2__WRITE 0xffffffffU + +#endif /* __BBB_TXFIR_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_bbb_txfir_2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_BBB_TXFIR_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::heavy_clip_ctrl */ +#ifndef __HEAVY_CLIP_CTRL_MACRO__ +#define __HEAVY_CLIP_CTRL_MACRO__ + +/* macros for field cf_heavy_clip_enable */ +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__SHIFT 0 +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__WIDTH 9 +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__MASK 0x000001ffU +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field pre_emp_ht40_enable */ +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__SHIFT 9 +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__WIDTH 1 +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__MASK 0x00000200U +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field heavy_clip_factor_xr */ +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__SHIFT 10 +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__WIDTH 8 +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__MASK 0x0003fc00U +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fc00U) >> 10) +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0003fc00U) +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0003fc00U) +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0003fc00U))) +#define HEAVY_CLIP_CTRL__TYPE u_int32_t +#define HEAVY_CLIP_CTRL__READ 0x0003ffffU +#define HEAVY_CLIP_CTRL__WRITE 0x0003ffffU + +#endif /* __HEAVY_CLIP_CTRL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_heavy_clip_ctrl */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_HEAVY_CLIP_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::heavy_clip_20 */ +#ifndef __HEAVY_CLIP_20_MACRO__ +#define __HEAVY_CLIP_20_MACRO__ + +/* macros for field heavy_clip_factor_0 */ +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__SHIFT 0 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__WIDTH 8 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__MASK 0x000000ffU +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field heavy_clip_factor_1 */ +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__SHIFT 8 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__WIDTH 8 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__MASK 0x0000ff00U +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field heavy_clip_factor_2 */ +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__SHIFT 16 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__WIDTH 8 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__MASK 0x00ff0000U +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field heavy_clip_factor_3 */ +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__SHIFT 24 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__WIDTH 8 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__MASK 0xff000000U +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define HEAVY_CLIP_20__TYPE u_int32_t +#define HEAVY_CLIP_20__READ 0xffffffffU +#define HEAVY_CLIP_20__WRITE 0xffffffffU + +#endif /* __HEAVY_CLIP_20_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_heavy_clip_20 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_HEAVY_CLIP_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::heavy_clip_40 */ +#ifndef __HEAVY_CLIP_40_MACRO__ +#define __HEAVY_CLIP_40_MACRO__ + +/* macros for field heavy_clip_factor_4 */ +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__SHIFT 0 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__WIDTH 8 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__MASK 0x000000ffU +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field heavy_clip_factor_5 */ +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__SHIFT 8 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__WIDTH 8 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__MASK 0x0000ff00U +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field heavy_clip_factor_6 */ +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__SHIFT 16 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__WIDTH 8 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__MASK 0x00ff0000U +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field heavy_clip_factor_7 */ +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__SHIFT 24 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__WIDTH 8 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__MASK 0xff000000U +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define HEAVY_CLIP_40__TYPE u_int32_t +#define HEAVY_CLIP_40__READ 0xffffffffU +#define HEAVY_CLIP_40__WRITE 0xffffffffU + +#endif /* __HEAVY_CLIP_40_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_heavy_clip_40 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_HEAVY_CLIP_40__NUM 1 + +/* macros for BlueprintGlobalNameSpace::illegal_tx_rate */ +#ifndef __ILLEGAL_TX_RATE_MACRO__ +#define __ILLEGAL_TX_RATE_MACRO__ + +/* macros for field illegal_tx_rate */ +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__SHIFT 0 +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__WIDTH 1 +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__MASK 0x00000001U +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define ILLEGAL_TX_RATE__TYPE u_int32_t +#define ILLEGAL_TX_RATE__READ 0x00000001U + +#endif /* __ILLEGAL_TX_RATE_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_illegal_tx_rate */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_ILLEGAL_TX_RATE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate1 */ +#ifndef __POWERTX_RATE1_MACRO__ +#define __POWERTX_RATE1_MACRO__ + +/* macros for field powertx_0 */ +#define POWERTX_RATE1__POWERTX_0__SHIFT 0 +#define POWERTX_RATE1__POWERTX_0__WIDTH 6 +#define POWERTX_RATE1__POWERTX_0__MASK 0x0000003fU +#define POWERTX_RATE1__POWERTX_0__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE1__POWERTX_0__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define POWERTX_RATE1__POWERTX_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE1__POWERTX_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_1 */ +#define POWERTX_RATE1__POWERTX_1__SHIFT 8 +#define POWERTX_RATE1__POWERTX_1__WIDTH 6 +#define POWERTX_RATE1__POWERTX_1__MASK 0x00003f00U +#define POWERTX_RATE1__POWERTX_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE1__POWERTX_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE1__POWERTX_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE1__POWERTX_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertx_2 */ +#define POWERTX_RATE1__POWERTX_2__SHIFT 16 +#define POWERTX_RATE1__POWERTX_2__WIDTH 6 +#define POWERTX_RATE1__POWERTX_2__MASK 0x003f0000U +#define POWERTX_RATE1__POWERTX_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE1__POWERTX_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE1__POWERTX_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE1__POWERTX_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertx_3 */ +#define POWERTX_RATE1__POWERTX_3__SHIFT 24 +#define POWERTX_RATE1__POWERTX_3__WIDTH 6 +#define POWERTX_RATE1__POWERTX_3__MASK 0x3f000000U +#define POWERTX_RATE1__POWERTX_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE1__POWERTX_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE1__POWERTX_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE1__POWERTX_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE1__TYPE u_int32_t +#define POWERTX_RATE1__READ 0x3f3f3f3fU +#define POWERTX_RATE1__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate2 */ +#ifndef __POWERTX_RATE2_MACRO__ +#define __POWERTX_RATE2_MACRO__ + +/* macros for field powertx_4 */ +#define POWERTX_RATE2__POWERTX_4__SHIFT 0 +#define POWERTX_RATE2__POWERTX_4__WIDTH 6 +#define POWERTX_RATE2__POWERTX_4__MASK 0x0000003fU +#define POWERTX_RATE2__POWERTX_4__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE2__POWERTX_4__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define POWERTX_RATE2__POWERTX_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE2__POWERTX_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_5 */ +#define POWERTX_RATE2__POWERTX_5__SHIFT 8 +#define POWERTX_RATE2__POWERTX_5__WIDTH 6 +#define POWERTX_RATE2__POWERTX_5__MASK 0x00003f00U +#define POWERTX_RATE2__POWERTX_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE2__POWERTX_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE2__POWERTX_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE2__POWERTX_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertx_6 */ +#define POWERTX_RATE2__POWERTX_6__SHIFT 16 +#define POWERTX_RATE2__POWERTX_6__WIDTH 6 +#define POWERTX_RATE2__POWERTX_6__MASK 0x003f0000U +#define POWERTX_RATE2__POWERTX_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE2__POWERTX_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE2__POWERTX_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE2__POWERTX_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertx_7 */ +#define POWERTX_RATE2__POWERTX_7__SHIFT 24 +#define POWERTX_RATE2__POWERTX_7__WIDTH 6 +#define POWERTX_RATE2__POWERTX_7__MASK 0x3f000000U +#define POWERTX_RATE2__POWERTX_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE2__POWERTX_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE2__POWERTX_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE2__POWERTX_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE2__TYPE u_int32_t +#define POWERTX_RATE2__READ 0x3f3f3f3fU +#define POWERTX_RATE2__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate3 */ +#ifndef __POWERTX_RATE3_MACRO__ +#define __POWERTX_RATE3_MACRO__ + +/* macros for field powertx_1l */ +#define POWERTX_RATE3__POWERTX_1L__SHIFT 0 +#define POWERTX_RATE3__POWERTX_1L__WIDTH 6 +#define POWERTX_RATE3__POWERTX_1L__MASK 0x0000003fU +#define POWERTX_RATE3__POWERTX_1L__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE3__POWERTX_1L__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define POWERTX_RATE3__POWERTX_1L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE3__POWERTX_1L__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_2l */ +#define POWERTX_RATE3__POWERTX_2L__SHIFT 16 +#define POWERTX_RATE3__POWERTX_2L__WIDTH 6 +#define POWERTX_RATE3__POWERTX_2L__MASK 0x003f0000U +#define POWERTX_RATE3__POWERTX_2L__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE3__POWERTX_2L__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE3__POWERTX_2L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE3__POWERTX_2L__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertx_2s */ +#define POWERTX_RATE3__POWERTX_2S__SHIFT 24 +#define POWERTX_RATE3__POWERTX_2S__WIDTH 6 +#define POWERTX_RATE3__POWERTX_2S__MASK 0x3f000000U +#define POWERTX_RATE3__POWERTX_2S__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE3__POWERTX_2S__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE3__POWERTX_2S__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE3__POWERTX_2S__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE3__TYPE u_int32_t +#define POWERTX_RATE3__READ 0x3f3f003fU +#define POWERTX_RATE3__WRITE 0x3f3f003fU + +#endif /* __POWERTX_RATE3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate3 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate4 */ +#ifndef __POWERTX_RATE4_MACRO__ +#define __POWERTX_RATE4_MACRO__ + +/* macros for field powertx_55l */ +#define POWERTX_RATE4__POWERTX_55L__SHIFT 0 +#define POWERTX_RATE4__POWERTX_55L__WIDTH 6 +#define POWERTX_RATE4__POWERTX_55L__MASK 0x0000003fU +#define POWERTX_RATE4__POWERTX_55L__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE4__POWERTX_55L__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define POWERTX_RATE4__POWERTX_55L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE4__POWERTX_55L__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_55s */ +#define POWERTX_RATE4__POWERTX_55S__SHIFT 8 +#define POWERTX_RATE4__POWERTX_55S__WIDTH 6 +#define POWERTX_RATE4__POWERTX_55S__MASK 0x00003f00U +#define POWERTX_RATE4__POWERTX_55S__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE4__POWERTX_55S__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE4__POWERTX_55S__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE4__POWERTX_55S__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertx_11l */ +#define POWERTX_RATE4__POWERTX_11L__SHIFT 16 +#define POWERTX_RATE4__POWERTX_11L__WIDTH 6 +#define POWERTX_RATE4__POWERTX_11L__MASK 0x003f0000U +#define POWERTX_RATE4__POWERTX_11L__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE4__POWERTX_11L__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE4__POWERTX_11L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE4__POWERTX_11L__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertx_11s */ +#define POWERTX_RATE4__POWERTX_11S__SHIFT 24 +#define POWERTX_RATE4__POWERTX_11S__WIDTH 6 +#define POWERTX_RATE4__POWERTX_11S__MASK 0x3f000000U +#define POWERTX_RATE4__POWERTX_11S__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE4__POWERTX_11S__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE4__POWERTX_11S__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE4__POWERTX_11S__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE4__TYPE u_int32_t +#define POWERTX_RATE4__READ 0x3f3f3f3fU +#define POWERTX_RATE4__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE4_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate4 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate5 */ +#ifndef __POWERTX_RATE5_MACRO__ +#define __POWERTX_RATE5_MACRO__ + +/* macros for field powertxht20_0 */ +#define POWERTX_RATE5__POWERTXHT20_0__SHIFT 0 +#define POWERTX_RATE5__POWERTXHT20_0__WIDTH 6 +#define POWERTX_RATE5__POWERTXHT20_0__MASK 0x0000003fU +#define POWERTX_RATE5__POWERTXHT20_0__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE5__POWERTXHT20_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE5__POWERTXHT20_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE5__POWERTXHT20_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht20_1 */ +#define POWERTX_RATE5__POWERTXHT20_1__SHIFT 8 +#define POWERTX_RATE5__POWERTXHT20_1__WIDTH 6 +#define POWERTX_RATE5__POWERTXHT20_1__MASK 0x00003f00U +#define POWERTX_RATE5__POWERTXHT20_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE5__POWERTXHT20_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE5__POWERTXHT20_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE5__POWERTXHT20_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht20_2 */ +#define POWERTX_RATE5__POWERTXHT20_2__SHIFT 16 +#define POWERTX_RATE5__POWERTXHT20_2__WIDTH 6 +#define POWERTX_RATE5__POWERTXHT20_2__MASK 0x003f0000U +#define POWERTX_RATE5__POWERTXHT20_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE5__POWERTXHT20_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE5__POWERTXHT20_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE5__POWERTXHT20_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht20_3 */ +#define POWERTX_RATE5__POWERTXHT20_3__SHIFT 24 +#define POWERTX_RATE5__POWERTXHT20_3__WIDTH 6 +#define POWERTX_RATE5__POWERTXHT20_3__MASK 0x3f000000U +#define POWERTX_RATE5__POWERTXHT20_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE5__POWERTXHT20_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE5__POWERTXHT20_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE5__POWERTXHT20_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE5__TYPE u_int32_t +#define POWERTX_RATE5__READ 0x3f3f3f3fU +#define POWERTX_RATE5__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE5_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate5 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate6 */ +#ifndef __POWERTX_RATE6_MACRO__ +#define __POWERTX_RATE6_MACRO__ + +/* macros for field powertxht20_4 */ +#define POWERTX_RATE6__POWERTXHT20_4__SHIFT 0 +#define POWERTX_RATE6__POWERTXHT20_4__WIDTH 6 +#define POWERTX_RATE6__POWERTXHT20_4__MASK 0x0000003fU +#define POWERTX_RATE6__POWERTXHT20_4__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE6__POWERTXHT20_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE6__POWERTXHT20_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE6__POWERTXHT20_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht20_5 */ +#define POWERTX_RATE6__POWERTXHT20_5__SHIFT 8 +#define POWERTX_RATE6__POWERTXHT20_5__WIDTH 6 +#define POWERTX_RATE6__POWERTXHT20_5__MASK 0x00003f00U +#define POWERTX_RATE6__POWERTXHT20_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE6__POWERTXHT20_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE6__POWERTXHT20_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE6__POWERTXHT20_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht20_6 */ +#define POWERTX_RATE6__POWERTXHT20_6__SHIFT 16 +#define POWERTX_RATE6__POWERTXHT20_6__WIDTH 6 +#define POWERTX_RATE6__POWERTXHT20_6__MASK 0x003f0000U +#define POWERTX_RATE6__POWERTXHT20_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE6__POWERTXHT20_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE6__POWERTXHT20_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE6__POWERTXHT20_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht20_7 */ +#define POWERTX_RATE6__POWERTXHT20_7__SHIFT 24 +#define POWERTX_RATE6__POWERTXHT20_7__WIDTH 6 +#define POWERTX_RATE6__POWERTXHT20_7__MASK 0x3f000000U +#define POWERTX_RATE6__POWERTXHT20_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE6__POWERTXHT20_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE6__POWERTXHT20_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE6__POWERTXHT20_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE6__TYPE u_int32_t +#define POWERTX_RATE6__READ 0x3f3f3f3fU +#define POWERTX_RATE6__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE6_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate6 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate7 */ +#ifndef __POWERTX_RATE7_MACRO__ +#define __POWERTX_RATE7_MACRO__ + +/* macros for field powertxht40_0 */ +#define POWERTX_RATE7__POWERTXHT40_0__SHIFT 0 +#define POWERTX_RATE7__POWERTXHT40_0__WIDTH 6 +#define POWERTX_RATE7__POWERTXHT40_0__MASK 0x0000003fU +#define POWERTX_RATE7__POWERTXHT40_0__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE7__POWERTXHT40_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE7__POWERTXHT40_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE7__POWERTXHT40_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht40_1 */ +#define POWERTX_RATE7__POWERTXHT40_1__SHIFT 8 +#define POWERTX_RATE7__POWERTXHT40_1__WIDTH 6 +#define POWERTX_RATE7__POWERTXHT40_1__MASK 0x00003f00U +#define POWERTX_RATE7__POWERTXHT40_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE7__POWERTXHT40_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE7__POWERTXHT40_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE7__POWERTXHT40_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht40_2 */ +#define POWERTX_RATE7__POWERTXHT40_2__SHIFT 16 +#define POWERTX_RATE7__POWERTXHT40_2__WIDTH 6 +#define POWERTX_RATE7__POWERTXHT40_2__MASK 0x003f0000U +#define POWERTX_RATE7__POWERTXHT40_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE7__POWERTXHT40_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE7__POWERTXHT40_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE7__POWERTXHT40_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht40_3 */ +#define POWERTX_RATE7__POWERTXHT40_3__SHIFT 24 +#define POWERTX_RATE7__POWERTXHT40_3__WIDTH 6 +#define POWERTX_RATE7__POWERTXHT40_3__MASK 0x3f000000U +#define POWERTX_RATE7__POWERTXHT40_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE7__POWERTXHT40_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE7__POWERTXHT40_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE7__POWERTXHT40_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE7__TYPE u_int32_t +#define POWERTX_RATE7__READ 0x3f3f3f3fU +#define POWERTX_RATE7__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE7_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate7 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate8 */ +#ifndef __POWERTX_RATE8_MACRO__ +#define __POWERTX_RATE8_MACRO__ + +/* macros for field powertxht40_4 */ +#define POWERTX_RATE8__POWERTXHT40_4__SHIFT 0 +#define POWERTX_RATE8__POWERTXHT40_4__WIDTH 6 +#define POWERTX_RATE8__POWERTXHT40_4__MASK 0x0000003fU +#define POWERTX_RATE8__POWERTXHT40_4__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE8__POWERTXHT40_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE8__POWERTXHT40_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE8__POWERTXHT40_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht40_5 */ +#define POWERTX_RATE8__POWERTXHT40_5__SHIFT 8 +#define POWERTX_RATE8__POWERTXHT40_5__WIDTH 6 +#define POWERTX_RATE8__POWERTXHT40_5__MASK 0x00003f00U +#define POWERTX_RATE8__POWERTXHT40_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE8__POWERTXHT40_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE8__POWERTXHT40_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE8__POWERTXHT40_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht40_6 */ +#define POWERTX_RATE8__POWERTXHT40_6__SHIFT 16 +#define POWERTX_RATE8__POWERTXHT40_6__WIDTH 6 +#define POWERTX_RATE8__POWERTXHT40_6__MASK 0x003f0000U +#define POWERTX_RATE8__POWERTXHT40_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE8__POWERTXHT40_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE8__POWERTXHT40_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE8__POWERTXHT40_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht40_7 */ +#define POWERTX_RATE8__POWERTXHT40_7__SHIFT 24 +#define POWERTX_RATE8__POWERTXHT40_7__WIDTH 6 +#define POWERTX_RATE8__POWERTXHT40_7__MASK 0x3f000000U +#define POWERTX_RATE8__POWERTXHT40_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE8__POWERTXHT40_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE8__POWERTXHT40_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE8__POWERTXHT40_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE8__TYPE u_int32_t +#define POWERTX_RATE8__READ 0x3f3f3f3fU +#define POWERTX_RATE8__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE8_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate8 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate9 */ +#ifndef __POWERTX_RATE9_MACRO__ +#define __POWERTX_RATE9_MACRO__ + +/* macros for field powertx_dup40_cck */ +#define POWERTX_RATE9__POWERTX_DUP40_CCK__SHIFT 0 +#define POWERTX_RATE9__POWERTX_DUP40_CCK__WIDTH 6 +#define POWERTX_RATE9__POWERTX_DUP40_CCK__MASK 0x0000003fU +#define POWERTX_RATE9__POWERTX_DUP40_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define POWERTX_RATE9__POWERTX_DUP40_CCK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE9__POWERTX_DUP40_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE9__POWERTX_DUP40_CCK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_dup40_ofdm */ +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__SHIFT 8 +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__WIDTH 6 +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__MASK 0x00003f00U +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertx_ext20_cck */ +#define POWERTX_RATE9__POWERTX_EXT20_CCK__SHIFT 16 +#define POWERTX_RATE9__POWERTX_EXT20_CCK__WIDTH 6 +#define POWERTX_RATE9__POWERTX_EXT20_CCK__MASK 0x003f0000U +#define POWERTX_RATE9__POWERTX_EXT20_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE9__POWERTX_EXT20_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE9__POWERTX_EXT20_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE9__POWERTX_EXT20_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertx_ext20_ofdm */ +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__SHIFT 24 +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__WIDTH 6 +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__MASK 0x3f000000U +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE9__TYPE u_int32_t +#define POWERTX_RATE9__READ 0x3f3f3f3fU +#define POWERTX_RATE9__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE9_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate9 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate10 */ +#ifndef __POWERTX_RATE10_MACRO__ +#define __POWERTX_RATE10_MACRO__ + +/* macros for field powertxht20_8 */ +#define POWERTX_RATE10__POWERTXHT20_8__SHIFT 0 +#define POWERTX_RATE10__POWERTXHT20_8__WIDTH 6 +#define POWERTX_RATE10__POWERTXHT20_8__MASK 0x0000003fU +#define POWERTX_RATE10__POWERTXHT20_8__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE10__POWERTXHT20_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE10__POWERTXHT20_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE10__POWERTXHT20_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht20_9 */ +#define POWERTX_RATE10__POWERTXHT20_9__SHIFT 8 +#define POWERTX_RATE10__POWERTXHT20_9__WIDTH 6 +#define POWERTX_RATE10__POWERTXHT20_9__MASK 0x00003f00U +#define POWERTX_RATE10__POWERTXHT20_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE10__POWERTXHT20_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE10__POWERTXHT20_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE10__POWERTXHT20_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht20_10 */ +#define POWERTX_RATE10__POWERTXHT20_10__SHIFT 16 +#define POWERTX_RATE10__POWERTXHT20_10__WIDTH 6 +#define POWERTX_RATE10__POWERTXHT20_10__MASK 0x003f0000U +#define POWERTX_RATE10__POWERTXHT20_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE10__POWERTXHT20_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE10__POWERTXHT20_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE10__POWERTXHT20_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht20_11 */ +#define POWERTX_RATE10__POWERTXHT20_11__SHIFT 24 +#define POWERTX_RATE10__POWERTXHT20_11__WIDTH 6 +#define POWERTX_RATE10__POWERTXHT20_11__MASK 0x3f000000U +#define POWERTX_RATE10__POWERTXHT20_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE10__POWERTXHT20_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE10__POWERTXHT20_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE10__POWERTXHT20_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE10__TYPE u_int32_t +#define POWERTX_RATE10__READ 0x3f3f3f3fU +#define POWERTX_RATE10__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE10_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate10 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate11 */ +#ifndef __POWERTX_RATE11_MACRO__ +#define __POWERTX_RATE11_MACRO__ + +/* macros for field powertxht20_12 */ +#define POWERTX_RATE11__POWERTXHT20_12__SHIFT 0 +#define POWERTX_RATE11__POWERTXHT20_12__WIDTH 6 +#define POWERTX_RATE11__POWERTXHT20_12__MASK 0x0000003fU +#define POWERTX_RATE11__POWERTXHT20_12__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define POWERTX_RATE11__POWERTXHT20_12__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE11__POWERTXHT20_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE11__POWERTXHT20_12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht20_13 */ +#define POWERTX_RATE11__POWERTXHT20_13__SHIFT 8 +#define POWERTX_RATE11__POWERTXHT20_13__WIDTH 6 +#define POWERTX_RATE11__POWERTXHT20_13__MASK 0x00003f00U +#define POWERTX_RATE11__POWERTXHT20_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE11__POWERTXHT20_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE11__POWERTXHT20_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE11__POWERTXHT20_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht40_12 */ +#define POWERTX_RATE11__POWERTXHT40_12__SHIFT 16 +#define POWERTX_RATE11__POWERTXHT40_12__WIDTH 6 +#define POWERTX_RATE11__POWERTXHT40_12__MASK 0x003f0000U +#define POWERTX_RATE11__POWERTXHT40_12__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE11__POWERTXHT40_12__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE11__POWERTXHT40_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE11__POWERTXHT40_12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht40_13 */ +#define POWERTX_RATE11__POWERTXHT40_13__SHIFT 24 +#define POWERTX_RATE11__POWERTXHT40_13__WIDTH 6 +#define POWERTX_RATE11__POWERTXHT40_13__MASK 0x3f000000U +#define POWERTX_RATE11__POWERTXHT40_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE11__POWERTXHT40_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE11__POWERTXHT40_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE11__POWERTXHT40_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE11__TYPE u_int32_t +#define POWERTX_RATE11__READ 0x3f3f3f3fU +#define POWERTX_RATE11__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE11_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate11 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate12 */ +#ifndef __POWERTX_RATE12_MACRO__ +#define __POWERTX_RATE12_MACRO__ + +/* macros for field powertxht40_8 */ +#define POWERTX_RATE12__POWERTXHT40_8__SHIFT 0 +#define POWERTX_RATE12__POWERTXHT40_8__WIDTH 6 +#define POWERTX_RATE12__POWERTXHT40_8__MASK 0x0000003fU +#define POWERTX_RATE12__POWERTXHT40_8__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE12__POWERTXHT40_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE12__POWERTXHT40_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE12__POWERTXHT40_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht40_9 */ +#define POWERTX_RATE12__POWERTXHT40_9__SHIFT 8 +#define POWERTX_RATE12__POWERTXHT40_9__WIDTH 6 +#define POWERTX_RATE12__POWERTXHT40_9__MASK 0x00003f00U +#define POWERTX_RATE12__POWERTXHT40_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE12__POWERTXHT40_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE12__POWERTXHT40_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE12__POWERTXHT40_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht40_10 */ +#define POWERTX_RATE12__POWERTXHT40_10__SHIFT 16 +#define POWERTX_RATE12__POWERTXHT40_10__WIDTH 6 +#define POWERTX_RATE12__POWERTXHT40_10__MASK 0x003f0000U +#define POWERTX_RATE12__POWERTXHT40_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE12__POWERTXHT40_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE12__POWERTXHT40_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE12__POWERTXHT40_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht40_11 */ +#define POWERTX_RATE12__POWERTXHT40_11__SHIFT 24 +#define POWERTX_RATE12__POWERTXHT40_11__WIDTH 6 +#define POWERTX_RATE12__POWERTXHT40_11__MASK 0x3f000000U +#define POWERTX_RATE12__POWERTXHT40_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE12__POWERTXHT40_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE12__POWERTXHT40_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE12__POWERTXHT40_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE12__TYPE u_int32_t +#define POWERTX_RATE12__READ 0x3f3f3f3fU +#define POWERTX_RATE12__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE12_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate12 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_RATE12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_max */ +#ifndef __POWERTX_MAX_MACRO__ +#define __POWERTX_MAX_MACRO__ + +/* macros for field use_per_packet_powertx_max */ +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__SHIFT 6 +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__WIDTH 1 +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__MASK 0x00000040U +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) +//#define POWERTX_MAX__TYPE u_int32_t +//#define POWERTX_MAX__READ 0x00000040U +//#define POWERTX_MAX__WRITE 0x00000040U + +#endif /* __POWERTX_MAX_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_max */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_MAX__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_sub */ +#ifndef __POWERTX_SUB_MACRO__ +#define __POWERTX_SUB_MACRO__ + +/* macros for field powertx_sub_for_2chain */ +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__SHIFT 0 +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__WIDTH 6 +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__MASK 0x0000003fU +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_sub_for_3chain */ +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__SHIFT 6 +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__WIDTH 6 +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__MASK 0x00000fc0U +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define POWERTX_SUB__TYPE u_int32_t +#define POWERTX_SUB__READ 0x00000fffU +#define POWERTX_SUB__WRITE 0x00000fffU + +#endif /* __POWERTX_SUB_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_sub */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_POWERTX_SUB__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_1 */ +#ifndef __TPC_1_MACRO__ +#define __TPC_1_MACRO__ + +/* macros for field force_dac_gain */ +#define TPC_1__FORCE_DAC_GAIN__SHIFT 0 +#define TPC_1__FORCE_DAC_GAIN__WIDTH 1 +#define TPC_1__FORCE_DAC_GAIN__MASK 0x00000001U +#define TPC_1__FORCE_DAC_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_1__FORCE_DAC_GAIN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TPC_1__FORCE_DAC_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TPC_1__FORCE_DAC_GAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TPC_1__FORCE_DAC_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_1__FORCE_DAC_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field forced_dac_gain */ +#define TPC_1__FORCED_DAC_GAIN__SHIFT 1 +#define TPC_1__FORCED_DAC_GAIN__WIDTH 5 +#define TPC_1__FORCED_DAC_GAIN__MASK 0x0000003eU +#define TPC_1__FORCED_DAC_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) +#define TPC_1__FORCED_DAC_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000003eU) +#define TPC_1__FORCED_DAC_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000003eU) +#define TPC_1__FORCED_DAC_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000003eU))) + +/* macros for field pd_dc_offset_target */ +#define TPC_1__PD_DC_OFFSET_TARGET__SHIFT 6 +#define TPC_1__PD_DC_OFFSET_TARGET__WIDTH 8 +#define TPC_1__PD_DC_OFFSET_TARGET__MASK 0x00003fc0U +#define TPC_1__PD_DC_OFFSET_TARGET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003fc0U) >> 6) +#define TPC_1__PD_DC_OFFSET_TARGET__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00003fc0U) +#define TPC_1__PD_DC_OFFSET_TARGET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00003fc0U) +#define TPC_1__PD_DC_OFFSET_TARGET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00003fc0U))) + +/* macros for field num_pd_gain */ +#define TPC_1__NUM_PD_GAIN__SHIFT 14 +#define TPC_1__NUM_PD_GAIN__WIDTH 2 +#define TPC_1__NUM_PD_GAIN__MASK 0x0000c000U +#define TPC_1__NUM_PD_GAIN__READ(src) (((u_int32_t)(src) & 0x0000c000U) >> 14) +#define TPC_1__NUM_PD_GAIN__WRITE(src) (((u_int32_t)(src) << 14) & 0x0000c000U) +#define TPC_1__NUM_PD_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define TPC_1__NUM_PD_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field pd_gain_setting1 */ +#define TPC_1__PD_GAIN_SETTING1__SHIFT 16 +#define TPC_1__PD_GAIN_SETTING1__WIDTH 2 +#define TPC_1__PD_GAIN_SETTING1__MASK 0x00030000U +#define TPC_1__PD_GAIN_SETTING1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00030000U) >> 16) +#define TPC_1__PD_GAIN_SETTING1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00030000U) +#define TPC_1__PD_GAIN_SETTING1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((u_int32_t)(src) <<\ + 16) & 0x00030000U) +#define TPC_1__PD_GAIN_SETTING1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00030000U))) + +/* macros for field pd_gain_setting2 */ +#define TPC_1__PD_GAIN_SETTING2__SHIFT 18 +#define TPC_1__PD_GAIN_SETTING2__WIDTH 2 +#define TPC_1__PD_GAIN_SETTING2__MASK 0x000c0000U +#define TPC_1__PD_GAIN_SETTING2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000c0000U) >> 18) +#define TPC_1__PD_GAIN_SETTING2__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define TPC_1__PD_GAIN_SETTING2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define TPC_1__PD_GAIN_SETTING2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field pd_gain_setting3 */ +#define TPC_1__PD_GAIN_SETTING3__SHIFT 20 +#define TPC_1__PD_GAIN_SETTING3__WIDTH 2 +#define TPC_1__PD_GAIN_SETTING3__MASK 0x00300000U +#define TPC_1__PD_GAIN_SETTING3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00300000U) >> 20) +#define TPC_1__PD_GAIN_SETTING3__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00300000U) +#define TPC_1__PD_GAIN_SETTING3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((u_int32_t)(src) <<\ + 20) & 0x00300000U) +#define TPC_1__PD_GAIN_SETTING3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00300000U))) + +/* macros for field enable_pd_calibrate */ +#define TPC_1__ENABLE_PD_CALIBRATE__SHIFT 22 +#define TPC_1__ENABLE_PD_CALIBRATE__WIDTH 1 +#define TPC_1__ENABLE_PD_CALIBRATE__MASK 0x00400000U +#define TPC_1__ENABLE_PD_CALIBRATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define TPC_1__ENABLE_PD_CALIBRATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define TPC_1__ENABLE_PD_CALIBRATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TPC_1__ENABLE_PD_CALIBRATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TPC_1__ENABLE_PD_CALIBRATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TPC_1__ENABLE_PD_CALIBRATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field pd_calibrate_wait */ +#define TPC_1__PD_CALIBRATE_WAIT__SHIFT 23 +#define TPC_1__PD_CALIBRATE_WAIT__WIDTH 6 +#define TPC_1__PD_CALIBRATE_WAIT__MASK 0x1f800000U +#define TPC_1__PD_CALIBRATE_WAIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f800000U) >> 23) +#define TPC_1__PD_CALIBRATE_WAIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x1f800000U) +#define TPC_1__PD_CALIBRATE_WAIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x1f800000U) +#define TPC_1__PD_CALIBRATE_WAIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x1f800000U))) + +/* macros for field force_pdadc_gain */ +#define TPC_1__FORCE_PDADC_GAIN__SHIFT 29 +#define TPC_1__FORCE_PDADC_GAIN__WIDTH 1 +#define TPC_1__FORCE_PDADC_GAIN__MASK 0x20000000U +#define TPC_1__FORCE_PDADC_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define TPC_1__FORCE_PDADC_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define TPC_1__FORCE_PDADC_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define TPC_1__FORCE_PDADC_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define TPC_1__FORCE_PDADC_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define TPC_1__FORCE_PDADC_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field forced_pdadc_gain */ +#define TPC_1__FORCED_PDADC_GAIN__SHIFT 30 +#define TPC_1__FORCED_PDADC_GAIN__WIDTH 2 +#define TPC_1__FORCED_PDADC_GAIN__MASK 0xc0000000U +#define TPC_1__FORCED_PDADC_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define TPC_1__FORCED_PDADC_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define TPC_1__FORCED_PDADC_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define TPC_1__FORCED_PDADC_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define TPC_1__TYPE u_int32_t +#define TPC_1__READ 0xffffffffU +#define TPC_1__WRITE 0xffffffffU + +#endif /* __TPC_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_2 */ +#ifndef __TPC_2_MACRO__ +#define __TPC_2_MACRO__ + +/* macros for field tx_frame_to_pdadc_on */ +#define TPC_2__TX_FRAME_TO_PDADC_ON__SHIFT 0 +#define TPC_2__TX_FRAME_TO_PDADC_ON__WIDTH 8 +#define TPC_2__TX_FRAME_TO_PDADC_ON__MASK 0x000000ffU +#define TPC_2__TX_FRAME_TO_PDADC_ON__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TPC_2__TX_FRAME_TO_PDADC_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TPC_2__TX_FRAME_TO_PDADC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TPC_2__TX_FRAME_TO_PDADC_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_frame_to_pd_acc_ofdm */ +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__SHIFT 8 +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__WIDTH 8 +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__MASK 0x0000ff00U +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field tx_frame_to_pd_acc_cck */ +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__SHIFT 16 +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__WIDTH 8 +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__MASK 0x00ff0000U +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define TPC_2__TYPE u_int32_t +#define TPC_2__READ 0x00ffffffU +#define TPC_2__WRITE 0x00ffffffU + +#endif /* __TPC_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_3 */ +#ifndef __TPC_3_MACRO__ +#define __TPC_3_MACRO__ + +/* macros for field tx_end_to_pdadc_on */ +#define TPC_3__TX_END_TO_PDADC_ON__SHIFT 0 +#define TPC_3__TX_END_TO_PDADC_ON__WIDTH 8 +#define TPC_3__TX_END_TO_PDADC_ON__MASK 0x000000ffU +#define TPC_3__TX_END_TO_PDADC_ON__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TPC_3__TX_END_TO_PDADC_ON__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define TPC_3__TX_END_TO_PDADC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TPC_3__TX_END_TO_PDADC_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_end_to_pd_acc_on */ +#define TPC_3__TX_END_TO_PD_ACC_ON__SHIFT 8 +#define TPC_3__TX_END_TO_PD_ACC_ON__WIDTH 8 +#define TPC_3__TX_END_TO_PD_ACC_ON__MASK 0x0000ff00U +#define TPC_3__TX_END_TO_PD_ACC_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TPC_3__TX_END_TO_PD_ACC_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TPC_3__TX_END_TO_PD_ACC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TPC_3__TX_END_TO_PD_ACC_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field pd_acc_window_dc_off */ +#define TPC_3__PD_ACC_WINDOW_DC_OFF__SHIFT 16 +#define TPC_3__PD_ACC_WINDOW_DC_OFF__WIDTH 3 +#define TPC_3__PD_ACC_WINDOW_DC_OFF__MASK 0x00070000U +#define TPC_3__PD_ACC_WINDOW_DC_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define TPC_3__PD_ACC_WINDOW_DC_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define TPC_3__PD_ACC_WINDOW_DC_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define TPC_3__PD_ACC_WINDOW_DC_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field pd_acc_window_cal */ +#define TPC_3__PD_ACC_WINDOW_CAL__SHIFT 19 +#define TPC_3__PD_ACC_WINDOW_CAL__WIDTH 3 +#define TPC_3__PD_ACC_WINDOW_CAL__MASK 0x00380000U +#define TPC_3__PD_ACC_WINDOW_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00380000U) >> 19) +#define TPC_3__PD_ACC_WINDOW_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define TPC_3__PD_ACC_WINDOW_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define TPC_3__PD_ACC_WINDOW_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field pd_acc_window_ofdm */ +#define TPC_3__PD_ACC_WINDOW_OFDM__SHIFT 22 +#define TPC_3__PD_ACC_WINDOW_OFDM__WIDTH 3 +#define TPC_3__PD_ACC_WINDOW_OFDM__MASK 0x01c00000U +#define TPC_3__PD_ACC_WINDOW_OFDM__READ(src) \ + (((u_int32_t)(src)\ + & 0x01c00000U) >> 22) +#define TPC_3__PD_ACC_WINDOW_OFDM__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x01c00000U) +#define TPC_3__PD_ACC_WINDOW_OFDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x01c00000U) +#define TPC_3__PD_ACC_WINDOW_OFDM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x01c00000U))) + +/* macros for field pd_acc_window_cck */ +#define TPC_3__PD_ACC_WINDOW_CCK__SHIFT 25 +#define TPC_3__PD_ACC_WINDOW_CCK__WIDTH 3 +#define TPC_3__PD_ACC_WINDOW_CCK__MASK 0x0e000000U +#define TPC_3__PD_ACC_WINDOW_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0e000000U) >> 25) +#define TPC_3__PD_ACC_WINDOW_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x0e000000U) +#define TPC_3__PD_ACC_WINDOW_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x0e000000U) +#define TPC_3__PD_ACC_WINDOW_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x0e000000U))) + +/* macros for field tpc_clk_gate_enable */ +#define TPC_3__TPC_CLK_GATE_ENABLE__SHIFT 31 +#define TPC_3__TPC_CLK_GATE_ENABLE__WIDTH 1 +#define TPC_3__TPC_CLK_GATE_ENABLE__MASK 0x80000000U +#define TPC_3__TPC_CLK_GATE_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TPC_3__TPC_CLK_GATE_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TPC_3__TPC_CLK_GATE_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TPC_3__TPC_CLK_GATE_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TPC_3__TPC_CLK_GATE_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TPC_3__TPC_CLK_GATE_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TPC_3__TYPE u_int32_t +#define TPC_3__READ 0x8fffffffU +#define TPC_3__WRITE 0x8fffffffU + +#endif /* __TPC_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_3 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_4_b0 */ +#ifndef __TPC_4_B0_MACRO__ +#define __TPC_4_B0_MACRO__ + +/* macros for field pd_avg_valid_0 */ +#define TPC_4_B0__PD_AVG_VALID_0__SHIFT 0 +#define TPC_4_B0__PD_AVG_VALID_0__WIDTH 1 +#define TPC_4_B0__PD_AVG_VALID_0__MASK 0x00000001U +#define TPC_4_B0__PD_AVG_VALID_0__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_4_B0__PD_AVG_VALID_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_4_B0__PD_AVG_VALID_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field pd_avg_out_0 */ +#define TPC_4_B0__PD_AVG_OUT_0__SHIFT 1 +#define TPC_4_B0__PD_AVG_OUT_0__WIDTH 8 +#define TPC_4_B0__PD_AVG_OUT_0__MASK 0x000001feU +#define TPC_4_B0__PD_AVG_OUT_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) + +/* macros for field dac_gain_0 */ +#define TPC_4_B0__DAC_GAIN_0__SHIFT 9 +#define TPC_4_B0__DAC_GAIN_0__WIDTH 5 +#define TPC_4_B0__DAC_GAIN_0__MASK 0x00003e00U +#define TPC_4_B0__DAC_GAIN_0__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9) + +/* macros for field tx_gain_setting_0 */ +#define TPC_4_B0__TX_GAIN_SETTING_0__SHIFT 14 +#define TPC_4_B0__TX_GAIN_SETTING_0__WIDTH 6 +#define TPC_4_B0__TX_GAIN_SETTING_0__MASK 0x000fc000U +#define TPC_4_B0__TX_GAIN_SETTING_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) + +/* macros for field rate_sent_0 */ +#define TPC_4_B0__RATE_SENT_0__SHIFT 20 +#define TPC_4_B0__RATE_SENT_0__WIDTH 5 +#define TPC_4_B0__RATE_SENT_0__MASK 0x01f00000U +#define TPC_4_B0__RATE_SENT_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) + +/* macros for field error_est_update_power_thresh */ +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__SHIFT 25 +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__WIDTH 6 +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__MASK 0x7e000000U +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x7e000000U) >> 25) +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x7e000000U) +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x7e000000U) +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x7e000000U))) +#define TPC_4_B0__TYPE u_int32_t +#define TPC_4_B0__READ 0x7fffffffU +#define TPC_4_B0__WRITE 0x7fffffffU + +#endif /* __TPC_4_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_4_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_4_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_5_b0 */ +#ifndef __TPC_5_B0_MACRO__ +#define __TPC_5_B0_MACRO__ + +/* macros for field pd_gain_overlap */ +#define TPC_5_B0__PD_GAIN_OVERLAP__SHIFT 0 +#define TPC_5_B0__PD_GAIN_OVERLAP__WIDTH 4 +#define TPC_5_B0__PD_GAIN_OVERLAP__MASK 0x0000000fU +#define TPC_5_B0__PD_GAIN_OVERLAP__READ(src) (u_int32_t)(src) & 0x0000000fU +#define TPC_5_B0__PD_GAIN_OVERLAP__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define TPC_5_B0__PD_GAIN_OVERLAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define TPC_5_B0__PD_GAIN_OVERLAP__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field pd_gain_boundary_1_0 */ +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__SHIFT 4 +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__WIDTH 6 +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__MASK 0x000003f0U +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field pd_gain_boundary_2_0 */ +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__SHIFT 10 +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__WIDTH 6 +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__MASK 0x0000fc00U +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fc00U) >> 10) +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0000fc00U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0000fc00U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0000fc00U))) + +/* macros for field pd_gain_boundary_3_0 */ +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__SHIFT 16 +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__WIDTH 6 +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__MASK 0x003f0000U +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field pd_gain_boundary_4_0 */ +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__SHIFT 22 +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__WIDTH 6 +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__MASK 0x0fc00000U +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fc00000U) >> 22) +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x0fc00000U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x0fc00000U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x0fc00000U))) +#define TPC_5_B0__TYPE u_int32_t +#define TPC_5_B0__READ 0x0fffffffU +#define TPC_5_B0__WRITE 0x0fffffffU + +#endif /* __TPC_5_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_5_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_5_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_6_b0 */ +#ifndef __TPC_6_B0_MACRO__ +#define __TPC_6_B0_MACRO__ + +/* macros for field pd_dac_setting_1_0 */ +#define TPC_6_B0__PD_DAC_SETTING_1_0__SHIFT 0 +#define TPC_6_B0__PD_DAC_SETTING_1_0__WIDTH 6 +#define TPC_6_B0__PD_DAC_SETTING_1_0__MASK 0x0000003fU +#define TPC_6_B0__PD_DAC_SETTING_1_0__READ(src) (u_int32_t)(src) & 0x0000003fU +#define TPC_6_B0__PD_DAC_SETTING_1_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define TPC_6_B0__PD_DAC_SETTING_1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TPC_6_B0__PD_DAC_SETTING_1_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field pd_dac_setting_2_0 */ +#define TPC_6_B0__PD_DAC_SETTING_2_0__SHIFT 6 +#define TPC_6_B0__PD_DAC_SETTING_2_0__WIDTH 6 +#define TPC_6_B0__PD_DAC_SETTING_2_0__MASK 0x00000fc0U +#define TPC_6_B0__PD_DAC_SETTING_2_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TPC_6_B0__PD_DAC_SETTING_2_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TPC_6_B0__PD_DAC_SETTING_2_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TPC_6_B0__PD_DAC_SETTING_2_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field pd_dac_setting_3_0 */ +#define TPC_6_B0__PD_DAC_SETTING_3_0__SHIFT 12 +#define TPC_6_B0__PD_DAC_SETTING_3_0__WIDTH 6 +#define TPC_6_B0__PD_DAC_SETTING_3_0__MASK 0x0003f000U +#define TPC_6_B0__PD_DAC_SETTING_3_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define TPC_6_B0__PD_DAC_SETTING_3_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define TPC_6_B0__PD_DAC_SETTING_3_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define TPC_6_B0__PD_DAC_SETTING_3_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field pd_dac_setting_4_0 */ +#define TPC_6_B0__PD_DAC_SETTING_4_0__SHIFT 18 +#define TPC_6_B0__PD_DAC_SETTING_4_0__WIDTH 6 +#define TPC_6_B0__PD_DAC_SETTING_4_0__MASK 0x00fc0000U +#define TPC_6_B0__PD_DAC_SETTING_4_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TPC_6_B0__PD_DAC_SETTING_4_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define TPC_6_B0__PD_DAC_SETTING_4_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define TPC_6_B0__PD_DAC_SETTING_4_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field error_est_mode */ +#define TPC_6_B0__ERROR_EST_MODE__SHIFT 24 +#define TPC_6_B0__ERROR_EST_MODE__WIDTH 2 +#define TPC_6_B0__ERROR_EST_MODE__MASK 0x03000000U +#define TPC_6_B0__ERROR_EST_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x03000000U) >> 24) +#define TPC_6_B0__ERROR_EST_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x03000000U) +#define TPC_6_B0__ERROR_EST_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define TPC_6_B0__ERROR_EST_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field error_est_filter_coeff */ +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__SHIFT 26 +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__WIDTH 3 +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__MASK 0x1c000000U +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) +#define TPC_6_B0__TYPE u_int32_t +#define TPC_6_B0__READ 0x1fffffffU +#define TPC_6_B0__WRITE 0x1fffffffU + +#endif /* __TPC_6_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_6_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_6_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_7 */ +#ifndef __TPC_7_MACRO__ +#define __TPC_7_MACRO__ + +/* macros for field tx_gain_table_max */ +#define TPC_7__TX_GAIN_TABLE_MAX__SHIFT 0 +#define TPC_7__TX_GAIN_TABLE_MAX__WIDTH 6 +#define TPC_7__TX_GAIN_TABLE_MAX__MASK 0x0000003fU +#define TPC_7__TX_GAIN_TABLE_MAX__READ(src) (u_int32_t)(src) & 0x0000003fU +#define TPC_7__TX_GAIN_TABLE_MAX__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define TPC_7__TX_GAIN_TABLE_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TPC_7__TX_GAIN_TABLE_MAX__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field init_tx_gain_setting */ +#define TPC_7__INIT_TX_GAIN_SETTING__SHIFT 6 +#define TPC_7__INIT_TX_GAIN_SETTING__WIDTH 6 +#define TPC_7__INIT_TX_GAIN_SETTING__MASK 0x00000fc0U +#define TPC_7__INIT_TX_GAIN_SETTING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TPC_7__INIT_TX_GAIN_SETTING__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TPC_7__INIT_TX_GAIN_SETTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TPC_7__INIT_TX_GAIN_SETTING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field en_cl_gain_mod */ +#define TPC_7__EN_CL_GAIN_MOD__SHIFT 12 +#define TPC_7__EN_CL_GAIN_MOD__WIDTH 1 +#define TPC_7__EN_CL_GAIN_MOD__MASK 0x00001000U +#define TPC_7__EN_CL_GAIN_MOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define TPC_7__EN_CL_GAIN_MOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define TPC_7__EN_CL_GAIN_MOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define TPC_7__EN_CL_GAIN_MOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define TPC_7__EN_CL_GAIN_MOD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define TPC_7__EN_CL_GAIN_MOD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field use_tx_pd_in_xpa */ +#define TPC_7__USE_TX_PD_IN_XPA__SHIFT 13 +#define TPC_7__USE_TX_PD_IN_XPA__WIDTH 1 +#define TPC_7__USE_TX_PD_IN_XPA__MASK 0x00002000U +#define TPC_7__USE_TX_PD_IN_XPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define TPC_7__USE_TX_PD_IN_XPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define TPC_7__USE_TX_PD_IN_XPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TPC_7__USE_TX_PD_IN_XPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TPC_7__USE_TX_PD_IN_XPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TPC_7__USE_TX_PD_IN_XPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field extend_tx_frame_for_tpc */ +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__SHIFT 14 +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__WIDTH 1 +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__MASK 0x00004000U +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field use_init_tx_gain_setting_after_warm_reset */ +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__SHIFT 15 +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__WIDTH 1 +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__MASK 0x00008000U +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) +#define TPC_7__TYPE u_int32_t +#define TPC_7__READ 0x0000ffffU +#define TPC_7__WRITE 0x0000ffffU + +#endif /* __TPC_7_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_7 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_8 */ +#ifndef __TPC_8_MACRO__ +#define __TPC_8_MACRO__ + +/* macros for field desired_scale_0 */ +#define TPC_8__DESIRED_SCALE_0__SHIFT 0 +#define TPC_8__DESIRED_SCALE_0__WIDTH 5 +#define TPC_8__DESIRED_SCALE_0__MASK 0x0000001fU +#define TPC_8__DESIRED_SCALE_0__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_8__DESIRED_SCALE_0__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define TPC_8__DESIRED_SCALE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_8__DESIRED_SCALE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_1 */ +#define TPC_8__DESIRED_SCALE_1__SHIFT 5 +#define TPC_8__DESIRED_SCALE_1__WIDTH 5 +#define TPC_8__DESIRED_SCALE_1__MASK 0x000003e0U +#define TPC_8__DESIRED_SCALE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_8__DESIRED_SCALE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_8__DESIRED_SCALE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_8__DESIRED_SCALE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_2 */ +#define TPC_8__DESIRED_SCALE_2__SHIFT 10 +#define TPC_8__DESIRED_SCALE_2__WIDTH 5 +#define TPC_8__DESIRED_SCALE_2__MASK 0x00007c00U +#define TPC_8__DESIRED_SCALE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_8__DESIRED_SCALE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_8__DESIRED_SCALE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_8__DESIRED_SCALE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field desired_scale_3 */ +#define TPC_8__DESIRED_SCALE_3__SHIFT 15 +#define TPC_8__DESIRED_SCALE_3__WIDTH 5 +#define TPC_8__DESIRED_SCALE_3__MASK 0x000f8000U +#define TPC_8__DESIRED_SCALE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define TPC_8__DESIRED_SCALE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define TPC_8__DESIRED_SCALE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define TPC_8__DESIRED_SCALE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field desired_scale_4 */ +#define TPC_8__DESIRED_SCALE_4__SHIFT 20 +#define TPC_8__DESIRED_SCALE_4__WIDTH 5 +#define TPC_8__DESIRED_SCALE_4__MASK 0x01f00000U +#define TPC_8__DESIRED_SCALE_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_8__DESIRED_SCALE_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define TPC_8__DESIRED_SCALE_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define TPC_8__DESIRED_SCALE_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field desired_scale_5 */ +#define TPC_8__DESIRED_SCALE_5__SHIFT 25 +#define TPC_8__DESIRED_SCALE_5__WIDTH 5 +#define TPC_8__DESIRED_SCALE_5__MASK 0x3e000000U +#define TPC_8__DESIRED_SCALE_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define TPC_8__DESIRED_SCALE_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define TPC_8__DESIRED_SCALE_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define TPC_8__DESIRED_SCALE_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define TPC_8__TYPE u_int32_t +#define TPC_8__READ 0x3fffffffU +#define TPC_8__WRITE 0x3fffffffU + +#endif /* __TPC_8_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_8 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_9 */ +#ifndef __TPC_9_MACRO__ +#define __TPC_9_MACRO__ + +/* macros for field desired_scale_6 */ +#define TPC_9__DESIRED_SCALE_6__SHIFT 0 +#define TPC_9__DESIRED_SCALE_6__WIDTH 5 +#define TPC_9__DESIRED_SCALE_6__MASK 0x0000001fU +#define TPC_9__DESIRED_SCALE_6__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_9__DESIRED_SCALE_6__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define TPC_9__DESIRED_SCALE_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_9__DESIRED_SCALE_6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_7 */ +#define TPC_9__DESIRED_SCALE_7__SHIFT 5 +#define TPC_9__DESIRED_SCALE_7__WIDTH 5 +#define TPC_9__DESIRED_SCALE_7__MASK 0x000003e0U +#define TPC_9__DESIRED_SCALE_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_9__DESIRED_SCALE_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_9__DESIRED_SCALE_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_9__DESIRED_SCALE_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_cck */ +#define TPC_9__DESIRED_SCALE_CCK__SHIFT 10 +#define TPC_9__DESIRED_SCALE_CCK__WIDTH 5 +#define TPC_9__DESIRED_SCALE_CCK__MASK 0x00007c00U +#define TPC_9__DESIRED_SCALE_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_9__DESIRED_SCALE_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_9__DESIRED_SCALE_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_9__DESIRED_SCALE_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field en_pd_dc_offset_thr */ +#define TPC_9__EN_PD_DC_OFFSET_THR__SHIFT 20 +#define TPC_9__EN_PD_DC_OFFSET_THR__WIDTH 1 +#define TPC_9__EN_PD_DC_OFFSET_THR__MASK 0x00100000U +#define TPC_9__EN_PD_DC_OFFSET_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define TPC_9__EN_PD_DC_OFFSET_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define TPC_9__EN_PD_DC_OFFSET_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TPC_9__EN_PD_DC_OFFSET_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TPC_9__EN_PD_DC_OFFSET_THR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TPC_9__EN_PD_DC_OFFSET_THR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field pd_dc_offset_thr */ +#define TPC_9__PD_DC_OFFSET_THR__SHIFT 21 +#define TPC_9__PD_DC_OFFSET_THR__WIDTH 6 +#define TPC_9__PD_DC_OFFSET_THR__MASK 0x07e00000U +#define TPC_9__PD_DC_OFFSET_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x07e00000U) >> 21) +#define TPC_9__PD_DC_OFFSET_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x07e00000U) +#define TPC_9__PD_DC_OFFSET_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x07e00000U) +#define TPC_9__PD_DC_OFFSET_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x07e00000U))) + +/* macros for field wait_caltx_settle */ +#define TPC_9__WAIT_CALTX_SETTLE__SHIFT 27 +#define TPC_9__WAIT_CALTX_SETTLE__WIDTH 4 +#define TPC_9__WAIT_CALTX_SETTLE__MASK 0x78000000U +#define TPC_9__WAIT_CALTX_SETTLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x78000000U) >> 27) +#define TPC_9__WAIT_CALTX_SETTLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x78000000U) +#define TPC_9__WAIT_CALTX_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define TPC_9__WAIT_CALTX_SETTLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) + +/* macros for field disable_pdadc_residual_dc_removal */ +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__SHIFT 31 +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__WIDTH 1 +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__MASK 0x80000000U +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TPC_9__TYPE u_int32_t +#define TPC_9__READ 0xfff07fffU +#define TPC_9__WRITE 0xfff07fffU + +#endif /* __TPC_9_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_9 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_10 */ +#ifndef __TPC_10_MACRO__ +#define __TPC_10_MACRO__ + +/* macros for field desired_scale_ht20_0 */ +#define TPC_10__DESIRED_SCALE_HT20_0__SHIFT 0 +#define TPC_10__DESIRED_SCALE_HT20_0__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_0__MASK 0x0000001fU +#define TPC_10__DESIRED_SCALE_HT20_0__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_10__DESIRED_SCALE_HT20_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_10__DESIRED_SCALE_HT20_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_10__DESIRED_SCALE_HT20_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht20_1 */ +#define TPC_10__DESIRED_SCALE_HT20_1__SHIFT 5 +#define TPC_10__DESIRED_SCALE_HT20_1__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_1__MASK 0x000003e0U +#define TPC_10__DESIRED_SCALE_HT20_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_10__DESIRED_SCALE_HT20_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_10__DESIRED_SCALE_HT20_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_10__DESIRED_SCALE_HT20_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_ht20_2 */ +#define TPC_10__DESIRED_SCALE_HT20_2__SHIFT 10 +#define TPC_10__DESIRED_SCALE_HT20_2__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_2__MASK 0x00007c00U +#define TPC_10__DESIRED_SCALE_HT20_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_10__DESIRED_SCALE_HT20_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_10__DESIRED_SCALE_HT20_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_10__DESIRED_SCALE_HT20_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field desired_scale_ht20_3 */ +#define TPC_10__DESIRED_SCALE_HT20_3__SHIFT 15 +#define TPC_10__DESIRED_SCALE_HT20_3__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_3__MASK 0x000f8000U +#define TPC_10__DESIRED_SCALE_HT20_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define TPC_10__DESIRED_SCALE_HT20_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define TPC_10__DESIRED_SCALE_HT20_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define TPC_10__DESIRED_SCALE_HT20_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field desired_scale_ht20_4 */ +#define TPC_10__DESIRED_SCALE_HT20_4__SHIFT 20 +#define TPC_10__DESIRED_SCALE_HT20_4__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_4__MASK 0x01f00000U +#define TPC_10__DESIRED_SCALE_HT20_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_10__DESIRED_SCALE_HT20_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define TPC_10__DESIRED_SCALE_HT20_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define TPC_10__DESIRED_SCALE_HT20_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field desired_scale_ht20_5 */ +#define TPC_10__DESIRED_SCALE_HT20_5__SHIFT 25 +#define TPC_10__DESIRED_SCALE_HT20_5__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_5__MASK 0x3e000000U +#define TPC_10__DESIRED_SCALE_HT20_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define TPC_10__DESIRED_SCALE_HT20_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define TPC_10__DESIRED_SCALE_HT20_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define TPC_10__DESIRED_SCALE_HT20_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define TPC_10__TYPE u_int32_t +#define TPC_10__READ 0x3fffffffU +#define TPC_10__WRITE 0x3fffffffU + +#endif /* __TPC_10_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_10 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_11_b0 */ +#ifndef __TPC_11_B0_MACRO__ +#define __TPC_11_B0_MACRO__ + +/* macros for field desired_scale_ht20_6 */ +#define TPC_11_B0__DESIRED_SCALE_HT20_6__SHIFT 0 +#define TPC_11_B0__DESIRED_SCALE_HT20_6__WIDTH 5 +#define TPC_11_B0__DESIRED_SCALE_HT20_6__MASK 0x0000001fU +#define TPC_11_B0__DESIRED_SCALE_HT20_6__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define TPC_11_B0__DESIRED_SCALE_HT20_6__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_11_B0__DESIRED_SCALE_HT20_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_11_B0__DESIRED_SCALE_HT20_6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht20_7 */ +#define TPC_11_B0__DESIRED_SCALE_HT20_7__SHIFT 5 +#define TPC_11_B0__DESIRED_SCALE_HT20_7__WIDTH 5 +#define TPC_11_B0__DESIRED_SCALE_HT20_7__MASK 0x000003e0U +#define TPC_11_B0__DESIRED_SCALE_HT20_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_11_B0__DESIRED_SCALE_HT20_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_11_B0__DESIRED_SCALE_HT20_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_11_B0__DESIRED_SCALE_HT20_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field olpc_gain_delta_0 */ +#define TPC_11_B0__OLPC_GAIN_DELTA_0__SHIFT 16 +#define TPC_11_B0__OLPC_GAIN_DELTA_0__WIDTH 8 +#define TPC_11_B0__OLPC_GAIN_DELTA_0__MASK 0x00ff0000U +#define TPC_11_B0__OLPC_GAIN_DELTA_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TPC_11_B0__OLPC_GAIN_DELTA_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TPC_11_B0__OLPC_GAIN_DELTA_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TPC_11_B0__OLPC_GAIN_DELTA_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field olpc_gain_delta_0_pal_on */ +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__SHIFT 24 +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__WIDTH 8 +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__MASK 0xff000000U +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TPC_11_B0__TYPE u_int32_t +#define TPC_11_B0__READ 0xffff03ffU +#define TPC_11_B0__WRITE 0xffff03ffU + +#endif /* __TPC_11_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_11_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_11_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_12 */ +#ifndef __TPC_12_MACRO__ +#define __TPC_12_MACRO__ + +/* macros for field desired_scale_ht40_0 */ +#define TPC_12__DESIRED_SCALE_HT40_0__SHIFT 0 +#define TPC_12__DESIRED_SCALE_HT40_0__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_0__MASK 0x0000001fU +#define TPC_12__DESIRED_SCALE_HT40_0__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_12__DESIRED_SCALE_HT40_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_12__DESIRED_SCALE_HT40_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_12__DESIRED_SCALE_HT40_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht40_1 */ +#define TPC_12__DESIRED_SCALE_HT40_1__SHIFT 5 +#define TPC_12__DESIRED_SCALE_HT40_1__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_1__MASK 0x000003e0U +#define TPC_12__DESIRED_SCALE_HT40_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_12__DESIRED_SCALE_HT40_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_12__DESIRED_SCALE_HT40_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_12__DESIRED_SCALE_HT40_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_ht40_2 */ +#define TPC_12__DESIRED_SCALE_HT40_2__SHIFT 10 +#define TPC_12__DESIRED_SCALE_HT40_2__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_2__MASK 0x00007c00U +#define TPC_12__DESIRED_SCALE_HT40_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_12__DESIRED_SCALE_HT40_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_12__DESIRED_SCALE_HT40_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_12__DESIRED_SCALE_HT40_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field desired_scale_ht40_3 */ +#define TPC_12__DESIRED_SCALE_HT40_3__SHIFT 15 +#define TPC_12__DESIRED_SCALE_HT40_3__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_3__MASK 0x000f8000U +#define TPC_12__DESIRED_SCALE_HT40_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define TPC_12__DESIRED_SCALE_HT40_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define TPC_12__DESIRED_SCALE_HT40_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define TPC_12__DESIRED_SCALE_HT40_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field desired_scale_ht40_4 */ +#define TPC_12__DESIRED_SCALE_HT40_4__SHIFT 20 +#define TPC_12__DESIRED_SCALE_HT40_4__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_4__MASK 0x01f00000U +#define TPC_12__DESIRED_SCALE_HT40_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_12__DESIRED_SCALE_HT40_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define TPC_12__DESIRED_SCALE_HT40_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define TPC_12__DESIRED_SCALE_HT40_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field desired_scale_ht40_5 */ +#define TPC_12__DESIRED_SCALE_HT40_5__SHIFT 25 +#define TPC_12__DESIRED_SCALE_HT40_5__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_5__MASK 0x3e000000U +#define TPC_12__DESIRED_SCALE_HT40_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define TPC_12__DESIRED_SCALE_HT40_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define TPC_12__DESIRED_SCALE_HT40_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define TPC_12__DESIRED_SCALE_HT40_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define TPC_12__TYPE u_int32_t +#define TPC_12__READ 0x3fffffffU +#define TPC_12__WRITE 0x3fffffffU + +#endif /* __TPC_12_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_12 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_13 */ +#ifndef __TPC_13_MACRO__ +#define __TPC_13_MACRO__ + +/* macros for field desired_scale_ht40_6 */ +#define TPC_13__DESIRED_SCALE_HT40_6__SHIFT 0 +#define TPC_13__DESIRED_SCALE_HT40_6__WIDTH 5 +#define TPC_13__DESIRED_SCALE_HT40_6__MASK 0x0000001fU +#define TPC_13__DESIRED_SCALE_HT40_6__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_13__DESIRED_SCALE_HT40_6__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_13__DESIRED_SCALE_HT40_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_13__DESIRED_SCALE_HT40_6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht40_7 */ +#define TPC_13__DESIRED_SCALE_HT40_7__SHIFT 5 +#define TPC_13__DESIRED_SCALE_HT40_7__WIDTH 5 +#define TPC_13__DESIRED_SCALE_HT40_7__MASK 0x000003e0U +#define TPC_13__DESIRED_SCALE_HT40_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_13__DESIRED_SCALE_HT40_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_13__DESIRED_SCALE_HT40_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_13__DESIRED_SCALE_HT40_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) +#define TPC_13__TYPE u_int32_t +#define TPC_13__READ 0x000003ffU +#define TPC_13__WRITE 0x000003ffU + +#endif /* __TPC_13_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_13 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_13__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_14 */ +#ifndef __TPC_14_MACRO__ +#define __TPC_14_MACRO__ + +/* macros for field desired_scale_ht20_8 */ +#define TPC_14__DESIRED_SCALE_HT20_8__SHIFT 0 +#define TPC_14__DESIRED_SCALE_HT20_8__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_8__MASK 0x0000001fU +#define TPC_14__DESIRED_SCALE_HT20_8__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_14__DESIRED_SCALE_HT20_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_14__DESIRED_SCALE_HT20_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_14__DESIRED_SCALE_HT20_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht20_9 */ +#define TPC_14__DESIRED_SCALE_HT20_9__SHIFT 5 +#define TPC_14__DESIRED_SCALE_HT20_9__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_9__MASK 0x000003e0U +#define TPC_14__DESIRED_SCALE_HT20_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_14__DESIRED_SCALE_HT20_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_14__DESIRED_SCALE_HT20_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_14__DESIRED_SCALE_HT20_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_ht20_10 */ +#define TPC_14__DESIRED_SCALE_HT20_10__SHIFT 10 +#define TPC_14__DESIRED_SCALE_HT20_10__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_10__MASK 0x00007c00U +#define TPC_14__DESIRED_SCALE_HT20_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_14__DESIRED_SCALE_HT20_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_14__DESIRED_SCALE_HT20_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_14__DESIRED_SCALE_HT20_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field desired_scale_ht20_11 */ +#define TPC_14__DESIRED_SCALE_HT20_11__SHIFT 15 +#define TPC_14__DESIRED_SCALE_HT20_11__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_11__MASK 0x000f8000U +#define TPC_14__DESIRED_SCALE_HT20_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define TPC_14__DESIRED_SCALE_HT20_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define TPC_14__DESIRED_SCALE_HT20_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define TPC_14__DESIRED_SCALE_HT20_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field desired_scale_ht20_12 */ +#define TPC_14__DESIRED_SCALE_HT20_12__SHIFT 20 +#define TPC_14__DESIRED_SCALE_HT20_12__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_12__MASK 0x01f00000U +#define TPC_14__DESIRED_SCALE_HT20_12__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_14__DESIRED_SCALE_HT20_12__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define TPC_14__DESIRED_SCALE_HT20_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define TPC_14__DESIRED_SCALE_HT20_12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field desired_scale_ht20_13 */ +#define TPC_14__DESIRED_SCALE_HT20_13__SHIFT 25 +#define TPC_14__DESIRED_SCALE_HT20_13__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_13__MASK 0x3e000000U +#define TPC_14__DESIRED_SCALE_HT20_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define TPC_14__DESIRED_SCALE_HT20_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define TPC_14__DESIRED_SCALE_HT20_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define TPC_14__DESIRED_SCALE_HT20_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define TPC_14__TYPE u_int32_t +#define TPC_14__READ 0x3fffffffU +#define TPC_14__WRITE 0x3fffffffU + +#endif /* __TPC_14_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_14 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_14__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_15 */ +#ifndef __TPC_15_MACRO__ +#define __TPC_15_MACRO__ + +/* macros for field desired_scale_ht40_8 */ +#define TPC_15__DESIRED_SCALE_HT40_8__SHIFT 0 +#define TPC_15__DESIRED_SCALE_HT40_8__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_8__MASK 0x0000001fU +#define TPC_15__DESIRED_SCALE_HT40_8__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_15__DESIRED_SCALE_HT40_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_15__DESIRED_SCALE_HT40_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_15__DESIRED_SCALE_HT40_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht40_9 */ +#define TPC_15__DESIRED_SCALE_HT40_9__SHIFT 5 +#define TPC_15__DESIRED_SCALE_HT40_9__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_9__MASK 0x000003e0U +#define TPC_15__DESIRED_SCALE_HT40_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_15__DESIRED_SCALE_HT40_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_15__DESIRED_SCALE_HT40_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_15__DESIRED_SCALE_HT40_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_ht40_10 */ +#define TPC_15__DESIRED_SCALE_HT40_10__SHIFT 10 +#define TPC_15__DESIRED_SCALE_HT40_10__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_10__MASK 0x00007c00U +#define TPC_15__DESIRED_SCALE_HT40_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_15__DESIRED_SCALE_HT40_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_15__DESIRED_SCALE_HT40_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_15__DESIRED_SCALE_HT40_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field desired_scale_ht40_11 */ +#define TPC_15__DESIRED_SCALE_HT40_11__SHIFT 15 +#define TPC_15__DESIRED_SCALE_HT40_11__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_11__MASK 0x000f8000U +#define TPC_15__DESIRED_SCALE_HT40_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define TPC_15__DESIRED_SCALE_HT40_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define TPC_15__DESIRED_SCALE_HT40_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define TPC_15__DESIRED_SCALE_HT40_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field desired_scale_ht40_12 */ +#define TPC_15__DESIRED_SCALE_HT40_12__SHIFT 20 +#define TPC_15__DESIRED_SCALE_HT40_12__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_12__MASK 0x01f00000U +#define TPC_15__DESIRED_SCALE_HT40_12__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_15__DESIRED_SCALE_HT40_12__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define TPC_15__DESIRED_SCALE_HT40_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define TPC_15__DESIRED_SCALE_HT40_12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field desired_scale_ht40_13 */ +#define TPC_15__DESIRED_SCALE_HT40_13__SHIFT 25 +#define TPC_15__DESIRED_SCALE_HT40_13__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_13__MASK 0x3e000000U +#define TPC_15__DESIRED_SCALE_HT40_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define TPC_15__DESIRED_SCALE_HT40_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define TPC_15__DESIRED_SCALE_HT40_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define TPC_15__DESIRED_SCALE_HT40_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define TPC_15__TYPE u_int32_t +#define TPC_15__READ 0x3fffffffU +#define TPC_15__WRITE 0x3fffffffU + +#endif /* __TPC_15_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_15 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_15__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_16 */ +#ifndef __TPC_16_MACRO__ +#define __TPC_16_MACRO__ + +/* macros for field pdadc_par_corr_cck */ +#define TPC_16__PDADC_PAR_CORR_CCK__SHIFT 8 +#define TPC_16__PDADC_PAR_CORR_CCK__WIDTH 6 +#define TPC_16__PDADC_PAR_CORR_CCK__MASK 0x00003f00U +#define TPC_16__PDADC_PAR_CORR_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define TPC_16__PDADC_PAR_CORR_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define TPC_16__PDADC_PAR_CORR_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define TPC_16__PDADC_PAR_CORR_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field pdadc_par_corr_ofdm */ +#define TPC_16__PDADC_PAR_CORR_OFDM__SHIFT 16 +#define TPC_16__PDADC_PAR_CORR_OFDM__WIDTH 6 +#define TPC_16__PDADC_PAR_CORR_OFDM__MASK 0x003f0000U +#define TPC_16__PDADC_PAR_CORR_OFDM__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define TPC_16__PDADC_PAR_CORR_OFDM__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define TPC_16__PDADC_PAR_CORR_OFDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define TPC_16__PDADC_PAR_CORR_OFDM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field pdadc_par_corr_ht40 */ +#define TPC_16__PDADC_PAR_CORR_HT40__SHIFT 24 +#define TPC_16__PDADC_PAR_CORR_HT40__WIDTH 6 +#define TPC_16__PDADC_PAR_CORR_HT40__MASK 0x3f000000U +#define TPC_16__PDADC_PAR_CORR_HT40__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define TPC_16__PDADC_PAR_CORR_HT40__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define TPC_16__PDADC_PAR_CORR_HT40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define TPC_16__PDADC_PAR_CORR_HT40__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define TPC_16__TYPE u_int32_t +#define TPC_16__READ 0x3f3f3f00U +#define TPC_16__WRITE 0x3f3f3f00U + +#endif /* __TPC_16_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_16 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_17 */ +#ifndef __TPC_17_MACRO__ +#define __TPC_17_MACRO__ + +/* macros for field enable_pal */ +#define TPC_17__ENABLE_PAL__SHIFT 0 +#define TPC_17__ENABLE_PAL__WIDTH 1 +#define TPC_17__ENABLE_PAL__MASK 0x00000001U +#define TPC_17__ENABLE_PAL__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_17__ENABLE_PAL__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TPC_17__ENABLE_PAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TPC_17__ENABLE_PAL__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TPC_17__ENABLE_PAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_17__ENABLE_PAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field enable_pal_cck */ +#define TPC_17__ENABLE_PAL_CCK__SHIFT 1 +#define TPC_17__ENABLE_PAL_CCK__WIDTH 1 +#define TPC_17__ENABLE_PAL_CCK__MASK 0x00000002U +#define TPC_17__ENABLE_PAL_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define TPC_17__ENABLE_PAL_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define TPC_17__ENABLE_PAL_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define TPC_17__ENABLE_PAL_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define TPC_17__ENABLE_PAL_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TPC_17__ENABLE_PAL_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field enable_pal_ofdm_20 */ +#define TPC_17__ENABLE_PAL_OFDM_20__SHIFT 2 +#define TPC_17__ENABLE_PAL_OFDM_20__WIDTH 1 +#define TPC_17__ENABLE_PAL_OFDM_20__MASK 0x00000004U +#define TPC_17__ENABLE_PAL_OFDM_20__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define TPC_17__ENABLE_PAL_OFDM_20__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define TPC_17__ENABLE_PAL_OFDM_20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define TPC_17__ENABLE_PAL_OFDM_20__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define TPC_17__ENABLE_PAL_OFDM_20__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TPC_17__ENABLE_PAL_OFDM_20__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field enable_pal_ofdm_40 */ +#define TPC_17__ENABLE_PAL_OFDM_40__SHIFT 3 +#define TPC_17__ENABLE_PAL_OFDM_40__WIDTH 1 +#define TPC_17__ENABLE_PAL_OFDM_40__MASK 0x00000008U +#define TPC_17__ENABLE_PAL_OFDM_40__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define TPC_17__ENABLE_PAL_OFDM_40__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define TPC_17__ENABLE_PAL_OFDM_40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TPC_17__ENABLE_PAL_OFDM_40__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define TPC_17__ENABLE_PAL_OFDM_40__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TPC_17__ENABLE_PAL_OFDM_40__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field pal_power_threshold */ +#define TPC_17__PAL_POWER_THRESHOLD__SHIFT 4 +#define TPC_17__PAL_POWER_THRESHOLD__WIDTH 6 +#define TPC_17__PAL_POWER_THRESHOLD__MASK 0x000003f0U +#define TPC_17__PAL_POWER_THRESHOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define TPC_17__PAL_POWER_THRESHOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define TPC_17__PAL_POWER_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define TPC_17__PAL_POWER_THRESHOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field force_pal_locked */ +#define TPC_17__FORCE_PAL_LOCKED__SHIFT 10 +#define TPC_17__FORCE_PAL_LOCKED__WIDTH 1 +#define TPC_17__FORCE_PAL_LOCKED__MASK 0x00000400U +#define TPC_17__FORCE_PAL_LOCKED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define TPC_17__FORCE_PAL_LOCKED__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define TPC_17__FORCE_PAL_LOCKED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TPC_17__FORCE_PAL_LOCKED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TPC_17__FORCE_PAL_LOCKED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TPC_17__FORCE_PAL_LOCKED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field init_tx_gain_setting_pal_on */ +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__SHIFT 11 +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__WIDTH 6 +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__MASK 0x0001f800U +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f800U) >> 11) +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x0001f800U) +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0001f800U) +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0001f800U))) +#define TPC_17__TYPE u_int32_t +#define TPC_17__READ 0x0001ffffU +#define TPC_17__WRITE 0x0001ffffU + +#endif /* __TPC_17_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_17 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_17__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_18 */ +#ifndef __TPC_18_MACRO__ +#define __TPC_18_MACRO__ + +/* macros for field therm_cal_value */ +#define TPC_18__THERM_CAL_VALUE__SHIFT 0 +#define TPC_18__THERM_CAL_VALUE__WIDTH 8 +#define TPC_18__THERM_CAL_VALUE__MASK 0x000000ffU +#define TPC_18__THERM_CAL_VALUE__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TPC_18__THERM_CAL_VALUE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define TPC_18__THERM_CAL_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TPC_18__THERM_CAL_VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field volt_cal_value */ +#define TPC_18__VOLT_CAL_VALUE__SHIFT 8 +#define TPC_18__VOLT_CAL_VALUE__WIDTH 8 +#define TPC_18__VOLT_CAL_VALUE__MASK 0x0000ff00U +#define TPC_18__VOLT_CAL_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TPC_18__VOLT_CAL_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TPC_18__VOLT_CAL_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TPC_18__VOLT_CAL_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field use_legacy_tpc */ +#define TPC_18__USE_LEGACY_TPC__SHIFT 16 +#define TPC_18__USE_LEGACY_TPC__WIDTH 1 +#define TPC_18__USE_LEGACY_TPC__MASK 0x00010000U +#define TPC_18__USE_LEGACY_TPC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define TPC_18__USE_LEGACY_TPC__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define TPC_18__USE_LEGACY_TPC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define TPC_18__USE_LEGACY_TPC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define TPC_18__USE_LEGACY_TPC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define TPC_18__USE_LEGACY_TPC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field min_power_therm_volt_gain_corr */ +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__SHIFT 17 +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__WIDTH 6 +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__MASK 0x007e0000U +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__READ(src) \ + (((u_int32_t)(src)\ + & 0x007e0000U) >> 17) +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x007e0000U) +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x007e0000U) +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x007e0000U))) +#define TPC_18__TYPE u_int32_t +#define TPC_18__READ 0x007fffffU +#define TPC_18__WRITE 0x007fffffU + +#endif /* __TPC_18_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_18 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_18__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_19 */ +#ifndef __TPC_19_MACRO__ +#define __TPC_19_MACRO__ + +/* macros for field alpha_therm */ +#define TPC_19__ALPHA_THERM__SHIFT 0 +#define TPC_19__ALPHA_THERM__WIDTH 8 +#define TPC_19__ALPHA_THERM__MASK 0x000000ffU +#define TPC_19__ALPHA_THERM__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TPC_19__ALPHA_THERM__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define TPC_19__ALPHA_THERM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TPC_19__ALPHA_THERM__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field alpha_therm_pal_on */ +#define TPC_19__ALPHA_THERM_PAL_ON__SHIFT 8 +#define TPC_19__ALPHA_THERM_PAL_ON__WIDTH 8 +#define TPC_19__ALPHA_THERM_PAL_ON__MASK 0x0000ff00U +#define TPC_19__ALPHA_THERM_PAL_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TPC_19__ALPHA_THERM_PAL_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TPC_19__ALPHA_THERM_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TPC_19__ALPHA_THERM_PAL_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field alpha_volt */ +#define TPC_19__ALPHA_VOLT__SHIFT 16 +#define TPC_19__ALPHA_VOLT__WIDTH 5 +#define TPC_19__ALPHA_VOLT__MASK 0x001f0000U +#define TPC_19__ALPHA_VOLT__READ(src) (((u_int32_t)(src) & 0x001f0000U) >> 16) +#define TPC_19__ALPHA_VOLT__WRITE(src) (((u_int32_t)(src) << 16) & 0x001f0000U) +#define TPC_19__ALPHA_VOLT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define TPC_19__ALPHA_VOLT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) + +/* macros for field alpha_volt_pal_on */ +#define TPC_19__ALPHA_VOLT_PAL_ON__SHIFT 21 +#define TPC_19__ALPHA_VOLT_PAL_ON__WIDTH 5 +#define TPC_19__ALPHA_VOLT_PAL_ON__MASK 0x03e00000U +#define TPC_19__ALPHA_VOLT_PAL_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x03e00000U) >> 21) +#define TPC_19__ALPHA_VOLT_PAL_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x03e00000U) +#define TPC_19__ALPHA_VOLT_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x03e00000U) +#define TPC_19__ALPHA_VOLT_PAL_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x03e00000U))) +#define TPC_19__TYPE u_int32_t +#define TPC_19__READ 0x03ffffffU +#define TPC_19__WRITE 0x03ffffffU + +#endif /* __TPC_19_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_19 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_19__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_20 */ +#ifndef __TPC_20_MACRO__ +#define __TPC_20_MACRO__ + +/* macros for field enable_pal_mcs_0 */ +#define TPC_20__ENABLE_PAL_MCS_0__SHIFT 0 +#define TPC_20__ENABLE_PAL_MCS_0__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_0__MASK 0x00000001U +#define TPC_20__ENABLE_PAL_MCS_0__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_20__ENABLE_PAL_MCS_0__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TPC_20__ENABLE_PAL_MCS_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TPC_20__ENABLE_PAL_MCS_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TPC_20__ENABLE_PAL_MCS_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_20__ENABLE_PAL_MCS_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field enable_pal_mcs_1 */ +#define TPC_20__ENABLE_PAL_MCS_1__SHIFT 1 +#define TPC_20__ENABLE_PAL_MCS_1__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_1__MASK 0x00000002U +#define TPC_20__ENABLE_PAL_MCS_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define TPC_20__ENABLE_PAL_MCS_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define TPC_20__ENABLE_PAL_MCS_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define TPC_20__ENABLE_PAL_MCS_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define TPC_20__ENABLE_PAL_MCS_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TPC_20__ENABLE_PAL_MCS_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field enable_pal_mcs_2 */ +#define TPC_20__ENABLE_PAL_MCS_2__SHIFT 2 +#define TPC_20__ENABLE_PAL_MCS_2__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_2__MASK 0x00000004U +#define TPC_20__ENABLE_PAL_MCS_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define TPC_20__ENABLE_PAL_MCS_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define TPC_20__ENABLE_PAL_MCS_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define TPC_20__ENABLE_PAL_MCS_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define TPC_20__ENABLE_PAL_MCS_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TPC_20__ENABLE_PAL_MCS_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field enable_pal_mcs_3 */ +#define TPC_20__ENABLE_PAL_MCS_3__SHIFT 3 +#define TPC_20__ENABLE_PAL_MCS_3__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_3__MASK 0x00000008U +#define TPC_20__ENABLE_PAL_MCS_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define TPC_20__ENABLE_PAL_MCS_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define TPC_20__ENABLE_PAL_MCS_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TPC_20__ENABLE_PAL_MCS_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define TPC_20__ENABLE_PAL_MCS_3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TPC_20__ENABLE_PAL_MCS_3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field enable_pal_mcs_4 */ +#define TPC_20__ENABLE_PAL_MCS_4__SHIFT 4 +#define TPC_20__ENABLE_PAL_MCS_4__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_4__MASK 0x00000010U +#define TPC_20__ENABLE_PAL_MCS_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define TPC_20__ENABLE_PAL_MCS_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define TPC_20__ENABLE_PAL_MCS_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define TPC_20__ENABLE_PAL_MCS_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define TPC_20__ENABLE_PAL_MCS_4__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define TPC_20__ENABLE_PAL_MCS_4__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field enable_pal_mcs_5 */ +#define TPC_20__ENABLE_PAL_MCS_5__SHIFT 5 +#define TPC_20__ENABLE_PAL_MCS_5__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_5__MASK 0x00000020U +#define TPC_20__ENABLE_PAL_MCS_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define TPC_20__ENABLE_PAL_MCS_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define TPC_20__ENABLE_PAL_MCS_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define TPC_20__ENABLE_PAL_MCS_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define TPC_20__ENABLE_PAL_MCS_5__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define TPC_20__ENABLE_PAL_MCS_5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field enable_pal_mcs_6 */ +#define TPC_20__ENABLE_PAL_MCS_6__SHIFT 6 +#define TPC_20__ENABLE_PAL_MCS_6__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_6__MASK 0x00000040U +#define TPC_20__ENABLE_PAL_MCS_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define TPC_20__ENABLE_PAL_MCS_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define TPC_20__ENABLE_PAL_MCS_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define TPC_20__ENABLE_PAL_MCS_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define TPC_20__ENABLE_PAL_MCS_6__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define TPC_20__ENABLE_PAL_MCS_6__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field enable_pal_mcs_7 */ +#define TPC_20__ENABLE_PAL_MCS_7__SHIFT 7 +#define TPC_20__ENABLE_PAL_MCS_7__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_7__MASK 0x00000080U +#define TPC_20__ENABLE_PAL_MCS_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define TPC_20__ENABLE_PAL_MCS_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define TPC_20__ENABLE_PAL_MCS_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define TPC_20__ENABLE_PAL_MCS_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define TPC_20__ENABLE_PAL_MCS_7__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define TPC_20__ENABLE_PAL_MCS_7__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field enable_pal_mcs_8 */ +#define TPC_20__ENABLE_PAL_MCS_8__SHIFT 8 +#define TPC_20__ENABLE_PAL_MCS_8__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_8__MASK 0x00000100U +#define TPC_20__ENABLE_PAL_MCS_8__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define TPC_20__ENABLE_PAL_MCS_8__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define TPC_20__ENABLE_PAL_MCS_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define TPC_20__ENABLE_PAL_MCS_8__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define TPC_20__ENABLE_PAL_MCS_8__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define TPC_20__ENABLE_PAL_MCS_8__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field enable_pal_mcs_9 */ +#define TPC_20__ENABLE_PAL_MCS_9__SHIFT 9 +#define TPC_20__ENABLE_PAL_MCS_9__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_9__MASK 0x00000200U +#define TPC_20__ENABLE_PAL_MCS_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define TPC_20__ENABLE_PAL_MCS_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define TPC_20__ENABLE_PAL_MCS_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define TPC_20__ENABLE_PAL_MCS_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define TPC_20__ENABLE_PAL_MCS_9__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define TPC_20__ENABLE_PAL_MCS_9__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field enable_pal_mcs_10 */ +#define TPC_20__ENABLE_PAL_MCS_10__SHIFT 10 +#define TPC_20__ENABLE_PAL_MCS_10__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_10__MASK 0x00000400U +#define TPC_20__ENABLE_PAL_MCS_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define TPC_20__ENABLE_PAL_MCS_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define TPC_20__ENABLE_PAL_MCS_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TPC_20__ENABLE_PAL_MCS_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TPC_20__ENABLE_PAL_MCS_10__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TPC_20__ENABLE_PAL_MCS_10__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field enable_pal_mcs_11 */ +#define TPC_20__ENABLE_PAL_MCS_11__SHIFT 11 +#define TPC_20__ENABLE_PAL_MCS_11__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_11__MASK 0x00000800U +#define TPC_20__ENABLE_PAL_MCS_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define TPC_20__ENABLE_PAL_MCS_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define TPC_20__ENABLE_PAL_MCS_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define TPC_20__ENABLE_PAL_MCS_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define TPC_20__ENABLE_PAL_MCS_11__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define TPC_20__ENABLE_PAL_MCS_11__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field enable_pal_mcs_12 */ +#define TPC_20__ENABLE_PAL_MCS_12__SHIFT 12 +#define TPC_20__ENABLE_PAL_MCS_12__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_12__MASK 0x00001000U +#define TPC_20__ENABLE_PAL_MCS_12__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define TPC_20__ENABLE_PAL_MCS_12__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define TPC_20__ENABLE_PAL_MCS_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define TPC_20__ENABLE_PAL_MCS_12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define TPC_20__ENABLE_PAL_MCS_12__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define TPC_20__ENABLE_PAL_MCS_12__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field enable_pal_mcs_13 */ +#define TPC_20__ENABLE_PAL_MCS_13__SHIFT 13 +#define TPC_20__ENABLE_PAL_MCS_13__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_13__MASK 0x00002000U +#define TPC_20__ENABLE_PAL_MCS_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define TPC_20__ENABLE_PAL_MCS_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define TPC_20__ENABLE_PAL_MCS_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TPC_20__ENABLE_PAL_MCS_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TPC_20__ENABLE_PAL_MCS_13__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TPC_20__ENABLE_PAL_MCS_13__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field enable_pal_mcs_14 */ +#define TPC_20__ENABLE_PAL_MCS_14__SHIFT 14 +#define TPC_20__ENABLE_PAL_MCS_14__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_14__MASK 0x00004000U +#define TPC_20__ENABLE_PAL_MCS_14__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define TPC_20__ENABLE_PAL_MCS_14__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define TPC_20__ENABLE_PAL_MCS_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define TPC_20__ENABLE_PAL_MCS_14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define TPC_20__ENABLE_PAL_MCS_14__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define TPC_20__ENABLE_PAL_MCS_14__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field enable_pal_mcs_15 */ +#define TPC_20__ENABLE_PAL_MCS_15__SHIFT 15 +#define TPC_20__ENABLE_PAL_MCS_15__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_15__MASK 0x00008000U +#define TPC_20__ENABLE_PAL_MCS_15__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TPC_20__ENABLE_PAL_MCS_15__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TPC_20__ENABLE_PAL_MCS_15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TPC_20__ENABLE_PAL_MCS_15__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TPC_20__ENABLE_PAL_MCS_15__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TPC_20__ENABLE_PAL_MCS_15__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field enable_pal_mcs_16 */ +#define TPC_20__ENABLE_PAL_MCS_16__SHIFT 16 +#define TPC_20__ENABLE_PAL_MCS_16__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_16__MASK 0x00010000U +#define TPC_20__ENABLE_PAL_MCS_16__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define TPC_20__ENABLE_PAL_MCS_16__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define TPC_20__ENABLE_PAL_MCS_16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define TPC_20__ENABLE_PAL_MCS_16__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define TPC_20__ENABLE_PAL_MCS_16__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define TPC_20__ENABLE_PAL_MCS_16__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field enable_pal_mcs_17 */ +#define TPC_20__ENABLE_PAL_MCS_17__SHIFT 17 +#define TPC_20__ENABLE_PAL_MCS_17__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_17__MASK 0x00020000U +#define TPC_20__ENABLE_PAL_MCS_17__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define TPC_20__ENABLE_PAL_MCS_17__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define TPC_20__ENABLE_PAL_MCS_17__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define TPC_20__ENABLE_PAL_MCS_17__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define TPC_20__ENABLE_PAL_MCS_17__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define TPC_20__ENABLE_PAL_MCS_17__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field enable_pal_mcs_18 */ +#define TPC_20__ENABLE_PAL_MCS_18__SHIFT 18 +#define TPC_20__ENABLE_PAL_MCS_18__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_18__MASK 0x00040000U +#define TPC_20__ENABLE_PAL_MCS_18__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define TPC_20__ENABLE_PAL_MCS_18__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define TPC_20__ENABLE_PAL_MCS_18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define TPC_20__ENABLE_PAL_MCS_18__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define TPC_20__ENABLE_PAL_MCS_18__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define TPC_20__ENABLE_PAL_MCS_18__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field enable_pal_mcs_19 */ +#define TPC_20__ENABLE_PAL_MCS_19__SHIFT 19 +#define TPC_20__ENABLE_PAL_MCS_19__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_19__MASK 0x00080000U +#define TPC_20__ENABLE_PAL_MCS_19__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define TPC_20__ENABLE_PAL_MCS_19__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define TPC_20__ENABLE_PAL_MCS_19__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TPC_20__ENABLE_PAL_MCS_19__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TPC_20__ENABLE_PAL_MCS_19__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TPC_20__ENABLE_PAL_MCS_19__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field enable_pal_mcs_20 */ +#define TPC_20__ENABLE_PAL_MCS_20__SHIFT 20 +#define TPC_20__ENABLE_PAL_MCS_20__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_20__MASK 0x00100000U +#define TPC_20__ENABLE_PAL_MCS_20__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define TPC_20__ENABLE_PAL_MCS_20__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define TPC_20__ENABLE_PAL_MCS_20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TPC_20__ENABLE_PAL_MCS_20__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TPC_20__ENABLE_PAL_MCS_20__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TPC_20__ENABLE_PAL_MCS_20__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field enable_pal_mcs_21 */ +#define TPC_20__ENABLE_PAL_MCS_21__SHIFT 21 +#define TPC_20__ENABLE_PAL_MCS_21__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_21__MASK 0x00200000U +#define TPC_20__ENABLE_PAL_MCS_21__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define TPC_20__ENABLE_PAL_MCS_21__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define TPC_20__ENABLE_PAL_MCS_21__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define TPC_20__ENABLE_PAL_MCS_21__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define TPC_20__ENABLE_PAL_MCS_21__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define TPC_20__ENABLE_PAL_MCS_21__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field enable_pal_mcs_22 */ +#define TPC_20__ENABLE_PAL_MCS_22__SHIFT 22 +#define TPC_20__ENABLE_PAL_MCS_22__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_22__MASK 0x00400000U +#define TPC_20__ENABLE_PAL_MCS_22__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define TPC_20__ENABLE_PAL_MCS_22__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define TPC_20__ENABLE_PAL_MCS_22__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TPC_20__ENABLE_PAL_MCS_22__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TPC_20__ENABLE_PAL_MCS_22__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TPC_20__ENABLE_PAL_MCS_22__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field enable_pal_mcs_23 */ +#define TPC_20__ENABLE_PAL_MCS_23__SHIFT 23 +#define TPC_20__ENABLE_PAL_MCS_23__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_23__MASK 0x00800000U +#define TPC_20__ENABLE_PAL_MCS_23__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TPC_20__ENABLE_PAL_MCS_23__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TPC_20__ENABLE_PAL_MCS_23__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TPC_20__ENABLE_PAL_MCS_23__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TPC_20__ENABLE_PAL_MCS_23__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TPC_20__ENABLE_PAL_MCS_23__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) +#define TPC_20__TYPE u_int32_t +#define TPC_20__READ 0x00ffffffU +#define TPC_20__WRITE 0x00ffffffU + +#endif /* __TPC_20_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tpc_20 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TPC_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::therm_adc_1 */ +#ifndef __THERM_ADC_1_MACRO__ +#define __THERM_ADC_1_MACRO__ + +/* macros for field init_therm_setting */ +#define THERM_ADC_1__INIT_THERM_SETTING__SHIFT 0 +#define THERM_ADC_1__INIT_THERM_SETTING__WIDTH 8 +#define THERM_ADC_1__INIT_THERM_SETTING__MASK 0x000000ffU +#define THERM_ADC_1__INIT_THERM_SETTING__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define THERM_ADC_1__INIT_THERM_SETTING__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define THERM_ADC_1__INIT_THERM_SETTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define THERM_ADC_1__INIT_THERM_SETTING__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field init_volt_setting */ +#define THERM_ADC_1__INIT_VOLT_SETTING__SHIFT 8 +#define THERM_ADC_1__INIT_VOLT_SETTING__WIDTH 8 +#define THERM_ADC_1__INIT_VOLT_SETTING__MASK 0x0000ff00U +#define THERM_ADC_1__INIT_VOLT_SETTING__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define THERM_ADC_1__INIT_VOLT_SETTING__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define THERM_ADC_1__INIT_VOLT_SETTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define THERM_ADC_1__INIT_VOLT_SETTING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field init_atb_setting */ +#define THERM_ADC_1__INIT_ATB_SETTING__SHIFT 16 +#define THERM_ADC_1__INIT_ATB_SETTING__WIDTH 8 +#define THERM_ADC_1__INIT_ATB_SETTING__MASK 0x00ff0000U +#define THERM_ADC_1__INIT_ATB_SETTING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define THERM_ADC_1__INIT_ATB_SETTING__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define THERM_ADC_1__INIT_ATB_SETTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define THERM_ADC_1__INIT_ATB_SETTING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field samples_cnt_coding */ +#define THERM_ADC_1__SAMPLES_CNT_CODING__SHIFT 24 +#define THERM_ADC_1__SAMPLES_CNT_CODING__WIDTH 2 +#define THERM_ADC_1__SAMPLES_CNT_CODING__MASK 0x03000000U +#define THERM_ADC_1__SAMPLES_CNT_CODING__READ(src) \ + (((u_int32_t)(src)\ + & 0x03000000U) >> 24) +#define THERM_ADC_1__SAMPLES_CNT_CODING__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x03000000U) +#define THERM_ADC_1__SAMPLES_CNT_CODING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define THERM_ADC_1__SAMPLES_CNT_CODING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field use_init_therm_volt_atb_after_warm_reset */ +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__SHIFT 26 +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__WIDTH 1 +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__MASK 0x04000000U +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field force_therm_volt_atb_to_init_settings */ +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__SHIFT 27 +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__WIDTH 1 +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__MASK 0x08000000U +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) +#define THERM_ADC_1__TYPE u_int32_t +#define THERM_ADC_1__READ 0x0fffffffU +#define THERM_ADC_1__WRITE 0x0fffffffU + +#endif /* __THERM_ADC_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_therm_adc_1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_THERM_ADC_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::therm_adc_2 */ +#ifndef __THERM_ADC_2_MACRO__ +#define __THERM_ADC_2_MACRO__ + +/* macros for field measure_therm_freq */ +#define THERM_ADC_2__MEASURE_THERM_FREQ__SHIFT 0 +#define THERM_ADC_2__MEASURE_THERM_FREQ__WIDTH 12 +#define THERM_ADC_2__MEASURE_THERM_FREQ__MASK 0x00000fffU +#define THERM_ADC_2__MEASURE_THERM_FREQ__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define THERM_ADC_2__MEASURE_THERM_FREQ__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define THERM_ADC_2__MEASURE_THERM_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define THERM_ADC_2__MEASURE_THERM_FREQ__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field measure_volt_freq */ +#define THERM_ADC_2__MEASURE_VOLT_FREQ__SHIFT 12 +#define THERM_ADC_2__MEASURE_VOLT_FREQ__WIDTH 10 +#define THERM_ADC_2__MEASURE_VOLT_FREQ__MASK 0x003ff000U +#define THERM_ADC_2__MEASURE_VOLT_FREQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x003ff000U) >> 12) +#define THERM_ADC_2__MEASURE_VOLT_FREQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x003ff000U) +#define THERM_ADC_2__MEASURE_VOLT_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x003ff000U) +#define THERM_ADC_2__MEASURE_VOLT_FREQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x003ff000U))) + +/* macros for field measure_atb_freq */ +#define THERM_ADC_2__MEASURE_ATB_FREQ__SHIFT 22 +#define THERM_ADC_2__MEASURE_ATB_FREQ__WIDTH 10 +#define THERM_ADC_2__MEASURE_ATB_FREQ__MASK 0xffc00000U +#define THERM_ADC_2__MEASURE_ATB_FREQ__READ(src) \ + (((u_int32_t)(src)\ + & 0xffc00000U) >> 22) +#define THERM_ADC_2__MEASURE_ATB_FREQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0xffc00000U) +#define THERM_ADC_2__MEASURE_ATB_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffc00000U) | (((u_int32_t)(src) <<\ + 22) & 0xffc00000U) +#define THERM_ADC_2__MEASURE_ATB_FREQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0xffc00000U))) +#define THERM_ADC_2__TYPE u_int32_t +#define THERM_ADC_2__READ 0xffffffffU +#define THERM_ADC_2__WRITE 0xffffffffU + +#endif /* __THERM_ADC_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_therm_adc_2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_THERM_ADC_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::therm_adc_3 */ +#ifndef __THERM_ADC_3_MACRO__ +#define __THERM_ADC_3_MACRO__ + +/* macros for field therm_adc_offset */ +#define THERM_ADC_3__THERM_ADC_OFFSET__SHIFT 0 +#define THERM_ADC_3__THERM_ADC_OFFSET__WIDTH 8 +#define THERM_ADC_3__THERM_ADC_OFFSET__MASK 0x000000ffU +#define THERM_ADC_3__THERM_ADC_OFFSET__READ(src) (u_int32_t)(src) & 0x000000ffU +#define THERM_ADC_3__THERM_ADC_OFFSET__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define THERM_ADC_3__THERM_ADC_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define THERM_ADC_3__THERM_ADC_OFFSET__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field therm_adc_scaled_gain */ +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__SHIFT 8 +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__WIDTH 9 +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__MASK 0x0001ff00U +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001ff00U) >> 8) +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0001ff00U) +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0001ff00U) +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0001ff00U))) + +/* macros for field adc_interval */ +#define THERM_ADC_3__ADC_INTERVAL__SHIFT 17 +#define THERM_ADC_3__ADC_INTERVAL__WIDTH 13 +#define THERM_ADC_3__ADC_INTERVAL__MASK 0x3ffe0000U +#define THERM_ADC_3__ADC_INTERVAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ffe0000U) >> 17) +#define THERM_ADC_3__ADC_INTERVAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x3ffe0000U) +#define THERM_ADC_3__ADC_INTERVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ffe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x3ffe0000U) +#define THERM_ADC_3__ADC_INTERVAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x3ffe0000U))) +#define THERM_ADC_3__TYPE u_int32_t +#define THERM_ADC_3__READ 0x3fffffffU +#define THERM_ADC_3__WRITE 0x3fffffffU + +#endif /* __THERM_ADC_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_therm_adc_3 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_THERM_ADC_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::therm_adc_4 */ +#ifndef __THERM_ADC_4_MACRO__ +#define __THERM_ADC_4_MACRO__ + +/* macros for field latest_therm_value */ +#define THERM_ADC_4__LATEST_THERM_VALUE__SHIFT 0 +#define THERM_ADC_4__LATEST_THERM_VALUE__WIDTH 8 +#define THERM_ADC_4__LATEST_THERM_VALUE__MASK 0x000000ffU +#define THERM_ADC_4__LATEST_THERM_VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field latest_volt_value */ +#define THERM_ADC_4__LATEST_VOLT_VALUE__SHIFT 8 +#define THERM_ADC_4__LATEST_VOLT_VALUE__WIDTH 8 +#define THERM_ADC_4__LATEST_VOLT_VALUE__MASK 0x0000ff00U +#define THERM_ADC_4__LATEST_VOLT_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field latest_atb_value */ +#define THERM_ADC_4__LATEST_ATB_VALUE__SHIFT 16 +#define THERM_ADC_4__LATEST_ATB_VALUE__WIDTH 8 +#define THERM_ADC_4__LATEST_ATB_VALUE__MASK 0x00ff0000U +#define THERM_ADC_4__LATEST_ATB_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define THERM_ADC_4__TYPE u_int32_t +#define THERM_ADC_4__READ 0x00ffffffU + +#endif /* __THERM_ADC_4_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_therm_adc_4 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_THERM_ADC_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_forced_gain */ +#ifndef __TX_FORCED_GAIN_MACRO__ +#define __TX_FORCED_GAIN_MACRO__ + +/* macros for field force_tx_gain */ +#define TX_FORCED_GAIN__FORCE_TX_GAIN__SHIFT 0 +#define TX_FORCED_GAIN__FORCE_TX_GAIN__WIDTH 1 +#define TX_FORCED_GAIN__FORCE_TX_GAIN__MASK 0x00000001U +#define TX_FORCED_GAIN__FORCE_TX_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U +#define TX_FORCED_GAIN__FORCE_TX_GAIN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TX_FORCED_GAIN__FORCE_TX_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TX_FORCED_GAIN__FORCE_TX_GAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TX_FORCED_GAIN__FORCE_TX_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TX_FORCED_GAIN__FORCE_TX_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field forced_txbb1dbgain */ +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__SHIFT 1 +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__WIDTH 3 +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__MASK 0x0000000eU +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field forced_txbb6dbgain */ +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__SHIFT 4 +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__WIDTH 2 +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__MASK 0x00000030U +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field forced_txmxrgain */ +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__SHIFT 6 +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__WIDTH 4 +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__MASK 0x000003c0U +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003c0U) >> 6) +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000003c0U) +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000003c0U) +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000003c0U))) + +/* macros for field forced_padrvgnA */ +#define TX_FORCED_GAIN__FORCED_PADRVGNA__SHIFT 10 +#define TX_FORCED_GAIN__FORCED_PADRVGNA__WIDTH 4 +#define TX_FORCED_GAIN__FORCED_PADRVGNA__MASK 0x00003c00U +#define TX_FORCED_GAIN__FORCED_PADRVGNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003c00U) >> 10) +#define TX_FORCED_GAIN__FORCED_PADRVGNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00003c00U) +#define TX_FORCED_GAIN__FORCED_PADRVGNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00003c00U) +#define TX_FORCED_GAIN__FORCED_PADRVGNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00003c00U))) + +/* macros for field forced_padrvgnB */ +#define TX_FORCED_GAIN__FORCED_PADRVGNB__SHIFT 14 +#define TX_FORCED_GAIN__FORCED_PADRVGNB__WIDTH 4 +#define TX_FORCED_GAIN__FORCED_PADRVGNB__MASK 0x0003c000U +#define TX_FORCED_GAIN__FORCED_PADRVGNB__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003c000U) >> 14) +#define TX_FORCED_GAIN__FORCED_PADRVGNB__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0003c000U) +#define TX_FORCED_GAIN__FORCED_PADRVGNB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0003c000U) +#define TX_FORCED_GAIN__FORCED_PADRVGNB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0003c000U))) + +/* macros for field forced_padrvgnC */ +#define TX_FORCED_GAIN__FORCED_PADRVGNC__SHIFT 18 +#define TX_FORCED_GAIN__FORCED_PADRVGNC__WIDTH 4 +#define TX_FORCED_GAIN__FORCED_PADRVGNC__MASK 0x003c0000U +#define TX_FORCED_GAIN__FORCED_PADRVGNC__READ(src) \ + (((u_int32_t)(src)\ + & 0x003c0000U) >> 18) +#define TX_FORCED_GAIN__FORCED_PADRVGNC__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x003c0000U) +#define TX_FORCED_GAIN__FORCED_PADRVGNC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x003c0000U) +#define TX_FORCED_GAIN__FORCED_PADRVGNC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x003c0000U))) + +/* macros for field forced_padrvgnD */ +#define TX_FORCED_GAIN__FORCED_PADRVGND__SHIFT 22 +#define TX_FORCED_GAIN__FORCED_PADRVGND__WIDTH 2 +#define TX_FORCED_GAIN__FORCED_PADRVGND__MASK 0x00c00000U +#define TX_FORCED_GAIN__FORCED_PADRVGND__READ(src) \ + (((u_int32_t)(src)\ + & 0x00c00000U) >> 22) +#define TX_FORCED_GAIN__FORCED_PADRVGND__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00c00000U) +#define TX_FORCED_GAIN__FORCED_PADRVGND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x00c00000U) +#define TX_FORCED_GAIN__FORCED_PADRVGND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00c00000U))) + +/* macros for field forced_enable_PAL */ +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__SHIFT 24 +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__WIDTH 1 +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__MASK 0x01000000U +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +//#define TX_FORCED_GAIN__TYPE u_int32_t +//#define TX_FORCED_GAIN__READ 0x01ffffffU +//#define TX_FORCED_GAIN__WRITE 0x01ffffffU + +#endif /* __TX_FORCED_GAIN_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_forced_gain */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_FORCED_GAIN__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pdadc_tab */ +#ifndef __PDADC_TAB_MACRO__ +#define __PDADC_TAB_MACRO__ + +/* macros for field tab_entry */ +#define PDADC_TAB__TAB_ENTRY__SHIFT 0 +#define PDADC_TAB__TAB_ENTRY__WIDTH 32 +#define PDADC_TAB__TAB_ENTRY__MASK 0xffffffffU +#define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define PDADC_TAB__TYPE u_int32_t +#define PDADC_TAB__WRITE 0x00000000U + +#endif /* __PDADC_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_pdadc_tab_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PDADC_TAB_B0__NUM 32 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_1 */ +#ifndef __TX_GAIN_TAB_1_MACRO__ +#define __TX_GAIN_TAB_1_MACRO__ + +/* macros for field tg_table1 */ +#define TX_GAIN_TAB_1__TG_TABLE1__SHIFT 0 +#define TX_GAIN_TAB_1__TG_TABLE1__WIDTH 32 +#define TX_GAIN_TAB_1__TG_TABLE1__MASK 0xffffffffU +#define TX_GAIN_TAB_1__TG_TABLE1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_1__TG_TABLE1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_1__TG_TABLE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_1__TG_TABLE1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_1__TYPE u_int32_t +#define TX_GAIN_TAB_1__READ 0xffffffffU +#define TX_GAIN_TAB_1__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_2 */ +#ifndef __TX_GAIN_TAB_2_MACRO__ +#define __TX_GAIN_TAB_2_MACRO__ + +/* macros for field tg_table2 */ +#define TX_GAIN_TAB_2__TG_TABLE2__SHIFT 0 +#define TX_GAIN_TAB_2__TG_TABLE2__WIDTH 32 +#define TX_GAIN_TAB_2__TG_TABLE2__MASK 0xffffffffU +#define TX_GAIN_TAB_2__TG_TABLE2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_2__TG_TABLE2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_2__TG_TABLE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_2__TG_TABLE2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_2__TYPE u_int32_t +#define TX_GAIN_TAB_2__READ 0xffffffffU +#define TX_GAIN_TAB_2__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_3 */ +#ifndef __TX_GAIN_TAB_3_MACRO__ +#define __TX_GAIN_TAB_3_MACRO__ + +/* macros for field tg_table3 */ +#define TX_GAIN_TAB_3__TG_TABLE3__SHIFT 0 +#define TX_GAIN_TAB_3__TG_TABLE3__WIDTH 32 +#define TX_GAIN_TAB_3__TG_TABLE3__MASK 0xffffffffU +#define TX_GAIN_TAB_3__TG_TABLE3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_3__TG_TABLE3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_3__TG_TABLE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_3__TG_TABLE3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_3__TYPE u_int32_t +#define TX_GAIN_TAB_3__READ 0xffffffffU +#define TX_GAIN_TAB_3__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_3 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_4 */ +#ifndef __TX_GAIN_TAB_4_MACRO__ +#define __TX_GAIN_TAB_4_MACRO__ + +/* macros for field tg_table4 */ +#define TX_GAIN_TAB_4__TG_TABLE4__SHIFT 0 +#define TX_GAIN_TAB_4__TG_TABLE4__WIDTH 32 +#define TX_GAIN_TAB_4__TG_TABLE4__MASK 0xffffffffU +#define TX_GAIN_TAB_4__TG_TABLE4__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_4__TG_TABLE4__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_4__TG_TABLE4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_4__TG_TABLE4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_4__TYPE u_int32_t +#define TX_GAIN_TAB_4__READ 0xffffffffU +#define TX_GAIN_TAB_4__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_4_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_4 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_5 */ +#ifndef __TX_GAIN_TAB_5_MACRO__ +#define __TX_GAIN_TAB_5_MACRO__ + +/* macros for field tg_table5 */ +#define TX_GAIN_TAB_5__TG_TABLE5__SHIFT 0 +#define TX_GAIN_TAB_5__TG_TABLE5__WIDTH 32 +#define TX_GAIN_TAB_5__TG_TABLE5__MASK 0xffffffffU +#define TX_GAIN_TAB_5__TG_TABLE5__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_5__TG_TABLE5__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_5__TG_TABLE5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_5__TG_TABLE5__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_5__TYPE u_int32_t +#define TX_GAIN_TAB_5__READ 0xffffffffU +#define TX_GAIN_TAB_5__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_5_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_5 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_6 */ +#ifndef __TX_GAIN_TAB_6_MACRO__ +#define __TX_GAIN_TAB_6_MACRO__ + +/* macros for field tg_table6 */ +#define TX_GAIN_TAB_6__TG_TABLE6__SHIFT 0 +#define TX_GAIN_TAB_6__TG_TABLE6__WIDTH 32 +#define TX_GAIN_TAB_6__TG_TABLE6__MASK 0xffffffffU +#define TX_GAIN_TAB_6__TG_TABLE6__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_6__TG_TABLE6__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_6__TG_TABLE6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_6__TG_TABLE6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_6__TYPE u_int32_t +#define TX_GAIN_TAB_6__READ 0xffffffffU +#define TX_GAIN_TAB_6__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_6_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_6 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_7 */ +#ifndef __TX_GAIN_TAB_7_MACRO__ +#define __TX_GAIN_TAB_7_MACRO__ + +/* macros for field tg_table7 */ +#define TX_GAIN_TAB_7__TG_TABLE7__SHIFT 0 +#define TX_GAIN_TAB_7__TG_TABLE7__WIDTH 32 +#define TX_GAIN_TAB_7__TG_TABLE7__MASK 0xffffffffU +#define TX_GAIN_TAB_7__TG_TABLE7__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_7__TG_TABLE7__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_7__TG_TABLE7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_7__TG_TABLE7__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_7__TYPE u_int32_t +#define TX_GAIN_TAB_7__READ 0xffffffffU +#define TX_GAIN_TAB_7__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_7_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_7 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_8 */ +#ifndef __TX_GAIN_TAB_8_MACRO__ +#define __TX_GAIN_TAB_8_MACRO__ + +/* macros for field tg_table8 */ +#define TX_GAIN_TAB_8__TG_TABLE8__SHIFT 0 +#define TX_GAIN_TAB_8__TG_TABLE8__WIDTH 32 +#define TX_GAIN_TAB_8__TG_TABLE8__MASK 0xffffffffU +#define TX_GAIN_TAB_8__TG_TABLE8__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_8__TG_TABLE8__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_8__TG_TABLE8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_8__TG_TABLE8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_8__TYPE u_int32_t +#define TX_GAIN_TAB_8__READ 0xffffffffU +#define TX_GAIN_TAB_8__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_8_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_8 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_9 */ +#ifndef __TX_GAIN_TAB_9_MACRO__ +#define __TX_GAIN_TAB_9_MACRO__ + +/* macros for field tg_table9 */ +#define TX_GAIN_TAB_9__TG_TABLE9__SHIFT 0 +#define TX_GAIN_TAB_9__TG_TABLE9__WIDTH 32 +#define TX_GAIN_TAB_9__TG_TABLE9__MASK 0xffffffffU +#define TX_GAIN_TAB_9__TG_TABLE9__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_9__TG_TABLE9__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_9__TG_TABLE9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_9__TG_TABLE9__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_9__TYPE u_int32_t +#define TX_GAIN_TAB_9__READ 0xffffffffU +#define TX_GAIN_TAB_9__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_9_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_9 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_10 */ +#ifndef __TX_GAIN_TAB_10_MACRO__ +#define __TX_GAIN_TAB_10_MACRO__ + +/* macros for field tg_table10 */ +#define TX_GAIN_TAB_10__TG_TABLE10__SHIFT 0 +#define TX_GAIN_TAB_10__TG_TABLE10__WIDTH 32 +#define TX_GAIN_TAB_10__TG_TABLE10__MASK 0xffffffffU +#define TX_GAIN_TAB_10__TG_TABLE10__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_10__TG_TABLE10__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_10__TG_TABLE10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_10__TG_TABLE10__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_10__TYPE u_int32_t +#define TX_GAIN_TAB_10__READ 0xffffffffU +#define TX_GAIN_TAB_10__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_10_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_10 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_11 */ +#ifndef __TX_GAIN_TAB_11_MACRO__ +#define __TX_GAIN_TAB_11_MACRO__ + +/* macros for field tg_table11 */ +#define TX_GAIN_TAB_11__TG_TABLE11__SHIFT 0 +#define TX_GAIN_TAB_11__TG_TABLE11__WIDTH 32 +#define TX_GAIN_TAB_11__TG_TABLE11__MASK 0xffffffffU +#define TX_GAIN_TAB_11__TG_TABLE11__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_11__TG_TABLE11__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_11__TG_TABLE11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_11__TG_TABLE11__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_11__TYPE u_int32_t +#define TX_GAIN_TAB_11__READ 0xffffffffU +#define TX_GAIN_TAB_11__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_11_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_11 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_12 */ +#ifndef __TX_GAIN_TAB_12_MACRO__ +#define __TX_GAIN_TAB_12_MACRO__ + +/* macros for field tg_table12 */ +#define TX_GAIN_TAB_12__TG_TABLE12__SHIFT 0 +#define TX_GAIN_TAB_12__TG_TABLE12__WIDTH 32 +#define TX_GAIN_TAB_12__TG_TABLE12__MASK 0xffffffffU +#define TX_GAIN_TAB_12__TG_TABLE12__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_12__TG_TABLE12__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_12__TG_TABLE12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_12__TG_TABLE12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_12__TYPE u_int32_t +#define TX_GAIN_TAB_12__READ 0xffffffffU +#define TX_GAIN_TAB_12__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_12_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_12 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_13 */ +#ifndef __TX_GAIN_TAB_13_MACRO__ +#define __TX_GAIN_TAB_13_MACRO__ + +/* macros for field tg_table13 */ +#define TX_GAIN_TAB_13__TG_TABLE13__SHIFT 0 +#define TX_GAIN_TAB_13__TG_TABLE13__WIDTH 32 +#define TX_GAIN_TAB_13__TG_TABLE13__MASK 0xffffffffU +#define TX_GAIN_TAB_13__TG_TABLE13__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_13__TG_TABLE13__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_13__TG_TABLE13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_13__TG_TABLE13__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_13__TYPE u_int32_t +#define TX_GAIN_TAB_13__READ 0xffffffffU +#define TX_GAIN_TAB_13__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_13_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_13 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_13__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_14 */ +#ifndef __TX_GAIN_TAB_14_MACRO__ +#define __TX_GAIN_TAB_14_MACRO__ + +/* macros for field tg_table14 */ +#define TX_GAIN_TAB_14__TG_TABLE14__SHIFT 0 +#define TX_GAIN_TAB_14__TG_TABLE14__WIDTH 32 +#define TX_GAIN_TAB_14__TG_TABLE14__MASK 0xffffffffU +#define TX_GAIN_TAB_14__TG_TABLE14__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_14__TG_TABLE14__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_14__TG_TABLE14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_14__TG_TABLE14__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_14__TYPE u_int32_t +#define TX_GAIN_TAB_14__READ 0xffffffffU +#define TX_GAIN_TAB_14__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_14_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_14 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_14__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_15 */ +#ifndef __TX_GAIN_TAB_15_MACRO__ +#define __TX_GAIN_TAB_15_MACRO__ + +/* macros for field tg_table15 */ +#define TX_GAIN_TAB_15__TG_TABLE15__SHIFT 0 +#define TX_GAIN_TAB_15__TG_TABLE15__WIDTH 32 +#define TX_GAIN_TAB_15__TG_TABLE15__MASK 0xffffffffU +#define TX_GAIN_TAB_15__TG_TABLE15__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_15__TG_TABLE15__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_15__TG_TABLE15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_15__TG_TABLE15__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_15__TYPE u_int32_t +#define TX_GAIN_TAB_15__READ 0xffffffffU +#define TX_GAIN_TAB_15__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_15_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_15 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_15__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_16 */ +#ifndef __TX_GAIN_TAB_16_MACRO__ +#define __TX_GAIN_TAB_16_MACRO__ + +/* macros for field tg_table16 */ +#define TX_GAIN_TAB_16__TG_TABLE16__SHIFT 0 +#define TX_GAIN_TAB_16__TG_TABLE16__WIDTH 32 +#define TX_GAIN_TAB_16__TG_TABLE16__MASK 0xffffffffU +#define TX_GAIN_TAB_16__TG_TABLE16__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_16__TG_TABLE16__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_16__TG_TABLE16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_16__TG_TABLE16__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_16__TYPE u_int32_t +#define TX_GAIN_TAB_16__READ 0xffffffffU +#define TX_GAIN_TAB_16__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_16_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_16 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_17 */ +#ifndef __TX_GAIN_TAB_17_MACRO__ +#define __TX_GAIN_TAB_17_MACRO__ + +/* macros for field tg_table17 */ +#define TX_GAIN_TAB_17__TG_TABLE17__SHIFT 0 +#define TX_GAIN_TAB_17__TG_TABLE17__WIDTH 32 +#define TX_GAIN_TAB_17__TG_TABLE17__MASK 0xffffffffU +#define TX_GAIN_TAB_17__TG_TABLE17__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_17__TG_TABLE17__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_17__TG_TABLE17__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_17__TG_TABLE17__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_17__TYPE u_int32_t +#define TX_GAIN_TAB_17__READ 0xffffffffU +#define TX_GAIN_TAB_17__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_17_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_17 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_17__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_18 */ +#ifndef __TX_GAIN_TAB_18_MACRO__ +#define __TX_GAIN_TAB_18_MACRO__ + +/* macros for field tg_table18 */ +#define TX_GAIN_TAB_18__TG_TABLE18__SHIFT 0 +#define TX_GAIN_TAB_18__TG_TABLE18__WIDTH 32 +#define TX_GAIN_TAB_18__TG_TABLE18__MASK 0xffffffffU +#define TX_GAIN_TAB_18__TG_TABLE18__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_18__TG_TABLE18__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_18__TG_TABLE18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_18__TG_TABLE18__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_18__TYPE u_int32_t +#define TX_GAIN_TAB_18__READ 0xffffffffU +#define TX_GAIN_TAB_18__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_18_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_18 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_18__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_19 */ +#ifndef __TX_GAIN_TAB_19_MACRO__ +#define __TX_GAIN_TAB_19_MACRO__ + +/* macros for field tg_table19 */ +#define TX_GAIN_TAB_19__TG_TABLE19__SHIFT 0 +#define TX_GAIN_TAB_19__TG_TABLE19__WIDTH 32 +#define TX_GAIN_TAB_19__TG_TABLE19__MASK 0xffffffffU +#define TX_GAIN_TAB_19__TG_TABLE19__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_19__TG_TABLE19__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_19__TG_TABLE19__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_19__TG_TABLE19__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_19__TYPE u_int32_t +#define TX_GAIN_TAB_19__READ 0xffffffffU +#define TX_GAIN_TAB_19__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_19_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_19 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_19__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_20 */ +#ifndef __TX_GAIN_TAB_20_MACRO__ +#define __TX_GAIN_TAB_20_MACRO__ + +/* macros for field tg_table20 */ +#define TX_GAIN_TAB_20__TG_TABLE20__SHIFT 0 +#define TX_GAIN_TAB_20__TG_TABLE20__WIDTH 32 +#define TX_GAIN_TAB_20__TG_TABLE20__MASK 0xffffffffU +#define TX_GAIN_TAB_20__TG_TABLE20__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_20__TG_TABLE20__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_20__TG_TABLE20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_20__TG_TABLE20__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_20__TYPE u_int32_t +#define TX_GAIN_TAB_20__READ 0xffffffffU +#define TX_GAIN_TAB_20__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_20_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_20 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_21 */ +#ifndef __TX_GAIN_TAB_21_MACRO__ +#define __TX_GAIN_TAB_21_MACRO__ + +/* macros for field tg_table21 */ +#define TX_GAIN_TAB_21__TG_TABLE21__SHIFT 0 +#define TX_GAIN_TAB_21__TG_TABLE21__WIDTH 32 +#define TX_GAIN_TAB_21__TG_TABLE21__MASK 0xffffffffU +#define TX_GAIN_TAB_21__TG_TABLE21__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_21__TG_TABLE21__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_21__TG_TABLE21__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_21__TG_TABLE21__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_21__TYPE u_int32_t +#define TX_GAIN_TAB_21__READ 0xffffffffU +#define TX_GAIN_TAB_21__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_21_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_21 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_21__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_22 */ +#ifndef __TX_GAIN_TAB_22_MACRO__ +#define __TX_GAIN_TAB_22_MACRO__ + +/* macros for field tg_table22 */ +#define TX_GAIN_TAB_22__TG_TABLE22__SHIFT 0 +#define TX_GAIN_TAB_22__TG_TABLE22__WIDTH 32 +#define TX_GAIN_TAB_22__TG_TABLE22__MASK 0xffffffffU +#define TX_GAIN_TAB_22__TG_TABLE22__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_22__TG_TABLE22__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_22__TG_TABLE22__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_22__TG_TABLE22__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_22__TYPE u_int32_t +#define TX_GAIN_TAB_22__READ 0xffffffffU +#define TX_GAIN_TAB_22__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_22_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_22 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_22__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_23 */ +#ifndef __TX_GAIN_TAB_23_MACRO__ +#define __TX_GAIN_TAB_23_MACRO__ + +/* macros for field tg_table23 */ +#define TX_GAIN_TAB_23__TG_TABLE23__SHIFT 0 +#define TX_GAIN_TAB_23__TG_TABLE23__WIDTH 32 +#define TX_GAIN_TAB_23__TG_TABLE23__MASK 0xffffffffU +#define TX_GAIN_TAB_23__TG_TABLE23__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_23__TG_TABLE23__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_23__TG_TABLE23__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_23__TG_TABLE23__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_23__TYPE u_int32_t +#define TX_GAIN_TAB_23__READ 0xffffffffU +#define TX_GAIN_TAB_23__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_23_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_23 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_23__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_24 */ +#ifndef __TX_GAIN_TAB_24_MACRO__ +#define __TX_GAIN_TAB_24_MACRO__ + +/* macros for field tg_table24 */ +#define TX_GAIN_TAB_24__TG_TABLE24__SHIFT 0 +#define TX_GAIN_TAB_24__TG_TABLE24__WIDTH 32 +#define TX_GAIN_TAB_24__TG_TABLE24__MASK 0xffffffffU +#define TX_GAIN_TAB_24__TG_TABLE24__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_24__TG_TABLE24__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_24__TG_TABLE24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_24__TG_TABLE24__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_24__TYPE u_int32_t +#define TX_GAIN_TAB_24__READ 0xffffffffU +#define TX_GAIN_TAB_24__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_24_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_24 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_24__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_25 */ +#ifndef __TX_GAIN_TAB_25_MACRO__ +#define __TX_GAIN_TAB_25_MACRO__ + +/* macros for field tg_table25 */ +#define TX_GAIN_TAB_25__TG_TABLE25__SHIFT 0 +#define TX_GAIN_TAB_25__TG_TABLE25__WIDTH 32 +#define TX_GAIN_TAB_25__TG_TABLE25__MASK 0xffffffffU +#define TX_GAIN_TAB_25__TG_TABLE25__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_25__TG_TABLE25__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_25__TG_TABLE25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_25__TG_TABLE25__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_25__TYPE u_int32_t +#define TX_GAIN_TAB_25__READ 0xffffffffU +#define TX_GAIN_TAB_25__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_25_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_25 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_25__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_26 */ +#ifndef __TX_GAIN_TAB_26_MACRO__ +#define __TX_GAIN_TAB_26_MACRO__ + +/* macros for field tg_table26 */ +#define TX_GAIN_TAB_26__TG_TABLE26__SHIFT 0 +#define TX_GAIN_TAB_26__TG_TABLE26__WIDTH 32 +#define TX_GAIN_TAB_26__TG_TABLE26__MASK 0xffffffffU +#define TX_GAIN_TAB_26__TG_TABLE26__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_26__TG_TABLE26__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_26__TG_TABLE26__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_26__TG_TABLE26__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_26__TYPE u_int32_t +#define TX_GAIN_TAB_26__READ 0xffffffffU +#define TX_GAIN_TAB_26__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_26_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_26 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_26__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_27 */ +#ifndef __TX_GAIN_TAB_27_MACRO__ +#define __TX_GAIN_TAB_27_MACRO__ + +/* macros for field tg_table27 */ +#define TX_GAIN_TAB_27__TG_TABLE27__SHIFT 0 +#define TX_GAIN_TAB_27__TG_TABLE27__WIDTH 32 +#define TX_GAIN_TAB_27__TG_TABLE27__MASK 0xffffffffU +#define TX_GAIN_TAB_27__TG_TABLE27__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_27__TG_TABLE27__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_27__TG_TABLE27__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_27__TG_TABLE27__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_27__TYPE u_int32_t +#define TX_GAIN_TAB_27__READ 0xffffffffU +#define TX_GAIN_TAB_27__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_27_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_27 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_27__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_28 */ +#ifndef __TX_GAIN_TAB_28_MACRO__ +#define __TX_GAIN_TAB_28_MACRO__ + +/* macros for field tg_table28 */ +#define TX_GAIN_TAB_28__TG_TABLE28__SHIFT 0 +#define TX_GAIN_TAB_28__TG_TABLE28__WIDTH 32 +#define TX_GAIN_TAB_28__TG_TABLE28__MASK 0xffffffffU +#define TX_GAIN_TAB_28__TG_TABLE28__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_28__TG_TABLE28__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_28__TG_TABLE28__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_28__TG_TABLE28__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_28__TYPE u_int32_t +#define TX_GAIN_TAB_28__READ 0xffffffffU +#define TX_GAIN_TAB_28__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_28_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_28 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_28__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_29 */ +#ifndef __TX_GAIN_TAB_29_MACRO__ +#define __TX_GAIN_TAB_29_MACRO__ + +/* macros for field tg_table29 */ +#define TX_GAIN_TAB_29__TG_TABLE29__SHIFT 0 +#define TX_GAIN_TAB_29__TG_TABLE29__WIDTH 32 +#define TX_GAIN_TAB_29__TG_TABLE29__MASK 0xffffffffU +#define TX_GAIN_TAB_29__TG_TABLE29__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_29__TG_TABLE29__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_29__TG_TABLE29__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_29__TG_TABLE29__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_29__TYPE u_int32_t +#define TX_GAIN_TAB_29__READ 0xffffffffU +#define TX_GAIN_TAB_29__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_29_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_29 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_29__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_30 */ +#ifndef __TX_GAIN_TAB_30_MACRO__ +#define __TX_GAIN_TAB_30_MACRO__ + +/* macros for field tg_table30 */ +#define TX_GAIN_TAB_30__TG_TABLE30__SHIFT 0 +#define TX_GAIN_TAB_30__TG_TABLE30__WIDTH 32 +#define TX_GAIN_TAB_30__TG_TABLE30__MASK 0xffffffffU +#define TX_GAIN_TAB_30__TG_TABLE30__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_30__TG_TABLE30__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_30__TG_TABLE30__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_30__TG_TABLE30__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_30__TYPE u_int32_t +#define TX_GAIN_TAB_30__READ 0xffffffffU +#define TX_GAIN_TAB_30__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_30_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_30 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_30__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_31 */ +#ifndef __TX_GAIN_TAB_31_MACRO__ +#define __TX_GAIN_TAB_31_MACRO__ + +/* macros for field tg_table31 */ +#define TX_GAIN_TAB_31__TG_TABLE31__SHIFT 0 +#define TX_GAIN_TAB_31__TG_TABLE31__WIDTH 32 +#define TX_GAIN_TAB_31__TG_TABLE31__MASK 0xffffffffU +#define TX_GAIN_TAB_31__TG_TABLE31__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_31__TG_TABLE31__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_31__TG_TABLE31__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_31__TG_TABLE31__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_31__TYPE u_int32_t +#define TX_GAIN_TAB_31__READ 0xffffffffU +#define TX_GAIN_TAB_31__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_31_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_31 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_31__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_32 */ +#ifndef __TX_GAIN_TAB_32_MACRO__ +#define __TX_GAIN_TAB_32_MACRO__ + +/* macros for field tg_table32 */ +#define TX_GAIN_TAB_32__TG_TABLE32__SHIFT 0 +#define TX_GAIN_TAB_32__TG_TABLE32__WIDTH 32 +#define TX_GAIN_TAB_32__TG_TABLE32__MASK 0xffffffffU +#define TX_GAIN_TAB_32__TG_TABLE32__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_32__TG_TABLE32__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_32__TG_TABLE32__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_32__TG_TABLE32__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_32__TYPE u_int32_t +#define TX_GAIN_TAB_32__READ 0xffffffffU +#define TX_GAIN_TAB_32__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_32_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_32 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_1 */ +#ifndef __TX_GAIN_TAB_PAL_1_MACRO__ +#define __TX_GAIN_TAB_PAL_1_MACRO__ + +/* macros for field tg_table1_pal_on */ +#define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_1__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_1__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_1__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_2 */ +#ifndef __TX_GAIN_TAB_PAL_2_MACRO__ +#define __TX_GAIN_TAB_PAL_2_MACRO__ + +/* macros for field tg_table2_pal_on */ +#define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_2__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_2__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_2__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_3 */ +#ifndef __TX_GAIN_TAB_PAL_3_MACRO__ +#define __TX_GAIN_TAB_PAL_3_MACRO__ + +/* macros for field tg_table3_pal_on */ +#define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_3__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_3__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_3__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_3 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_4 */ +#ifndef __TX_GAIN_TAB_PAL_4_MACRO__ +#define __TX_GAIN_TAB_PAL_4_MACRO__ + +/* macros for field tg_table4_pal_on */ +#define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_4__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_4__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_4__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_4_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_4 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_5 */ +#ifndef __TX_GAIN_TAB_PAL_5_MACRO__ +#define __TX_GAIN_TAB_PAL_5_MACRO__ + +/* macros for field tg_table5_pal_on */ +#define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_5__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_5__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_5__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_5_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_5 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_6 */ +#ifndef __TX_GAIN_TAB_PAL_6_MACRO__ +#define __TX_GAIN_TAB_PAL_6_MACRO__ + +/* macros for field tg_table6_pal_on */ +#define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_6__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_6__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_6__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_6_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_6 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_7 */ +#ifndef __TX_GAIN_TAB_PAL_7_MACRO__ +#define __TX_GAIN_TAB_PAL_7_MACRO__ + +/* macros for field tg_table7_pal_on */ +#define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_7__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_7__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_7__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_7_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_7 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_8 */ +#ifndef __TX_GAIN_TAB_PAL_8_MACRO__ +#define __TX_GAIN_TAB_PAL_8_MACRO__ + +/* macros for field tg_table8_pal_on */ +#define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_8__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_8__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_8__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_8_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_8 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_9 */ +#ifndef __TX_GAIN_TAB_PAL_9_MACRO__ +#define __TX_GAIN_TAB_PAL_9_MACRO__ + +/* macros for field tg_table9_pal_on */ +#define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_9__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_9__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_9__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_9_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_9 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_10 */ +#ifndef __TX_GAIN_TAB_PAL_10_MACRO__ +#define __TX_GAIN_TAB_PAL_10_MACRO__ + +/* macros for field tg_table10_pal_on */ +#define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_10__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_10__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_10__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_10_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_10 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_11 */ +#ifndef __TX_GAIN_TAB_PAL_11_MACRO__ +#define __TX_GAIN_TAB_PAL_11_MACRO__ + +/* macros for field tg_table11_pal_on */ +#define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_11__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_11__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_11__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_11_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_11 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_12 */ +#ifndef __TX_GAIN_TAB_PAL_12_MACRO__ +#define __TX_GAIN_TAB_PAL_12_MACRO__ + +/* macros for field tg_table12_pal_on */ +#define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_12__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_12__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_12__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_12_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_12 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_13 */ +#ifndef __TX_GAIN_TAB_PAL_13_MACRO__ +#define __TX_GAIN_TAB_PAL_13_MACRO__ + +/* macros for field tg_table13_pal_on */ +#define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_13__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_13__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_13__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_13_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_13 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_13__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_14 */ +#ifndef __TX_GAIN_TAB_PAL_14_MACRO__ +#define __TX_GAIN_TAB_PAL_14_MACRO__ + +/* macros for field tg_table14_pal_on */ +#define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_14__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_14__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_14__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_14_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_14 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_14__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_15 */ +#ifndef __TX_GAIN_TAB_PAL_15_MACRO__ +#define __TX_GAIN_TAB_PAL_15_MACRO__ + +/* macros for field tg_table15_pal_on */ +#define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_15__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_15__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_15__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_15_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_15 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_15__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_16 */ +#ifndef __TX_GAIN_TAB_PAL_16_MACRO__ +#define __TX_GAIN_TAB_PAL_16_MACRO__ + +/* macros for field tg_table16_pal_on */ +#define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_16__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_16__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_16__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_16_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_16 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_17 */ +#ifndef __TX_GAIN_TAB_PAL_17_MACRO__ +#define __TX_GAIN_TAB_PAL_17_MACRO__ + +/* macros for field tg_table17_pal_on */ +#define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_17__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_17__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_17__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_17_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_17 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_17__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_18 */ +#ifndef __TX_GAIN_TAB_PAL_18_MACRO__ +#define __TX_GAIN_TAB_PAL_18_MACRO__ + +/* macros for field tg_table18_pal_on */ +#define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_18__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_18__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_18__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_18_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_18 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_18__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_19 */ +#ifndef __TX_GAIN_TAB_PAL_19_MACRO__ +#define __TX_GAIN_TAB_PAL_19_MACRO__ + +/* macros for field tg_table19_pal_on */ +#define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_19__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_19__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_19__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_19_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_19 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_19__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_20 */ +#ifndef __TX_GAIN_TAB_PAL_20_MACRO__ +#define __TX_GAIN_TAB_PAL_20_MACRO__ + +/* macros for field tg_table20_pal_on */ +#define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_20__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_20__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_20__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_20_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_20 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_21 */ +#ifndef __TX_GAIN_TAB_PAL_21_MACRO__ +#define __TX_GAIN_TAB_PAL_21_MACRO__ + +/* macros for field tg_table21_pal_on */ +#define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_21__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_21__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_21__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_21_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_21 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_21__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_22 */ +#ifndef __TX_GAIN_TAB_PAL_22_MACRO__ +#define __TX_GAIN_TAB_PAL_22_MACRO__ + +/* macros for field tg_table22_pal_on */ +#define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_22__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_22__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_22__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_22_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_22 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_22__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_23 */ +#ifndef __TX_GAIN_TAB_PAL_23_MACRO__ +#define __TX_GAIN_TAB_PAL_23_MACRO__ + +/* macros for field tg_table23_pal_on */ +#define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_23__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_23__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_23__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_23_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_23 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_23__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_24 */ +#ifndef __TX_GAIN_TAB_PAL_24_MACRO__ +#define __TX_GAIN_TAB_PAL_24_MACRO__ + +/* macros for field tg_table24_pal_on */ +#define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_24__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_24__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_24__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_24_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_24 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_24__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_25 */ +#ifndef __TX_GAIN_TAB_PAL_25_MACRO__ +#define __TX_GAIN_TAB_PAL_25_MACRO__ + +/* macros for field tg_table25_pal_on */ +#define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_25__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_25__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_25__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_25_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_25 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_25__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_26 */ +#ifndef __TX_GAIN_TAB_PAL_26_MACRO__ +#define __TX_GAIN_TAB_PAL_26_MACRO__ + +/* macros for field tg_table26_pal_on */ +#define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_26__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_26__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_26__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_26_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_26 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_26__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_27 */ +#ifndef __TX_GAIN_TAB_PAL_27_MACRO__ +#define __TX_GAIN_TAB_PAL_27_MACRO__ + +/* macros for field tg_table27_pal_on */ +#define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_27__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_27__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_27__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_27_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_27 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_27__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_28 */ +#ifndef __TX_GAIN_TAB_PAL_28_MACRO__ +#define __TX_GAIN_TAB_PAL_28_MACRO__ + +/* macros for field tg_table28_pal_on */ +#define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_28__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_28__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_28__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_28_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_28 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_28__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_29 */ +#ifndef __TX_GAIN_TAB_PAL_29_MACRO__ +#define __TX_GAIN_TAB_PAL_29_MACRO__ + +/* macros for field tg_table29_pal_on */ +#define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_29__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_29__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_29__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_29_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_29 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_29__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_30 */ +#ifndef __TX_GAIN_TAB_PAL_30_MACRO__ +#define __TX_GAIN_TAB_PAL_30_MACRO__ + +/* macros for field tg_table30_pal_on */ +#define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_30__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_30__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_30__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_30_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_30 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_30__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_31 */ +#ifndef __TX_GAIN_TAB_PAL_31_MACRO__ +#define __TX_GAIN_TAB_PAL_31_MACRO__ + +/* macros for field tg_table31_pal_on */ +#define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_31__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_31__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_31__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_31_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_31 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_31__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_pal_32 */ +#ifndef __TX_GAIN_TAB_PAL_32_MACRO__ +#define __TX_GAIN_TAB_PAL_32_MACRO__ + +/* macros for field tg_table32_pal_on */ +#define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__SHIFT 0 +#define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__WIDTH 32 +#define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__MASK 0xffffffffU +#define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_PAL_32__TYPE u_int32_t +#define TX_GAIN_TAB_PAL_32__READ 0xffffffffU +#define TX_GAIN_TAB_PAL_32__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_PAL_32_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_gain_tab_pal_32 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TX_GAIN_TAB_PAL_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_0 */ +#ifndef __CALTX_GAIN_SET_0_MACRO__ +#define __CALTX_GAIN_SET_0_MACRO__ + +/* macros for field caltx_gain_set_0 */ +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__SHIFT 0 +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__WIDTH 14 +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__MASK 0x00003fffU +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_1 */ +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__SHIFT 14 +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__WIDTH 14 +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__MASK 0x0fffc000U +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_0__TYPE u_int32_t +#define CALTX_GAIN_SET_0__READ 0x0fffffffU +#define CALTX_GAIN_SET_0__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_2 */ +#ifndef __CALTX_GAIN_SET_2_MACRO__ +#define __CALTX_GAIN_SET_2_MACRO__ + +/* macros for field caltx_gain_set_2 */ +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__SHIFT 0 +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__WIDTH 14 +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__MASK 0x00003fffU +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_3 */ +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__SHIFT 14 +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__WIDTH 14 +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__MASK 0x0fffc000U +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_2__TYPE u_int32_t +#define CALTX_GAIN_SET_2__READ 0x0fffffffU +#define CALTX_GAIN_SET_2__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_4 */ +#ifndef __CALTX_GAIN_SET_4_MACRO__ +#define __CALTX_GAIN_SET_4_MACRO__ + +/* macros for field caltx_gain_set_4 */ +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__SHIFT 0 +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__WIDTH 14 +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__MASK 0x00003fffU +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_5 */ +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__SHIFT 14 +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__WIDTH 14 +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__MASK 0x0fffc000U +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_4__TYPE u_int32_t +#define CALTX_GAIN_SET_4__READ 0x0fffffffU +#define CALTX_GAIN_SET_4__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_4_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_4 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_6 */ +#ifndef __CALTX_GAIN_SET_6_MACRO__ +#define __CALTX_GAIN_SET_6_MACRO__ + +/* macros for field caltx_gain_set_6 */ +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__SHIFT 0 +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__WIDTH 14 +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__MASK 0x00003fffU +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_7 */ +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__SHIFT 14 +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__WIDTH 14 +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__MASK 0x0fffc000U +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_6__TYPE u_int32_t +#define CALTX_GAIN_SET_6__READ 0x0fffffffU +#define CALTX_GAIN_SET_6__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_6_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_6 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_8 */ +#ifndef __CALTX_GAIN_SET_8_MACRO__ +#define __CALTX_GAIN_SET_8_MACRO__ + +/* macros for field caltx_gain_set_8 */ +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__SHIFT 0 +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__WIDTH 14 +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__MASK 0x00003fffU +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_9 */ +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__SHIFT 14 +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__WIDTH 14 +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__MASK 0x0fffc000U +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_8__TYPE u_int32_t +#define CALTX_GAIN_SET_8__READ 0x0fffffffU +#define CALTX_GAIN_SET_8__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_8_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_8 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_10 */ +#ifndef __CALTX_GAIN_SET_10_MACRO__ +#define __CALTX_GAIN_SET_10_MACRO__ + +/* macros for field caltx_gain_set_10 */ +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__SHIFT 0 +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__WIDTH 14 +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__MASK 0x00003fffU +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_11 */ +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__SHIFT 14 +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__WIDTH 14 +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__MASK 0x0fffc000U +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_10__TYPE u_int32_t +#define CALTX_GAIN_SET_10__READ 0x0fffffffU +#define CALTX_GAIN_SET_10__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_10_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_10 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_12 */ +#ifndef __CALTX_GAIN_SET_12_MACRO__ +#define __CALTX_GAIN_SET_12_MACRO__ + +/* macros for field caltx_gain_set_12 */ +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__SHIFT 0 +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__WIDTH 14 +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__MASK 0x00003fffU +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_13 */ +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__SHIFT 14 +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__WIDTH 14 +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__MASK 0x0fffc000U +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_12__TYPE u_int32_t +#define CALTX_GAIN_SET_12__READ 0x0fffffffU +#define CALTX_GAIN_SET_12__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_12_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_12 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_14 */ +#ifndef __CALTX_GAIN_SET_14_MACRO__ +#define __CALTX_GAIN_SET_14_MACRO__ + +/* macros for field caltx_gain_set_14 */ +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__SHIFT 0 +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__WIDTH 14 +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__MASK 0x00003fffU +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_15 */ +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__SHIFT 14 +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__WIDTH 14 +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__MASK 0x0fffc000U +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_14__TYPE u_int32_t +#define CALTX_GAIN_SET_14__READ 0x0fffffffU +#define CALTX_GAIN_SET_14__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_14_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_14 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_14__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_16 */ +#ifndef __CALTX_GAIN_SET_16_MACRO__ +#define __CALTX_GAIN_SET_16_MACRO__ + +/* macros for field caltx_gain_set_16 */ +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__SHIFT 0 +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__WIDTH 14 +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__MASK 0x00003fffU +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_17 */ +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__SHIFT 14 +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__WIDTH 14 +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__MASK 0x0fffc000U +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_16__TYPE u_int32_t +#define CALTX_GAIN_SET_16__READ 0x0fffffffU +#define CALTX_GAIN_SET_16__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_16_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_16 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_18 */ +#ifndef __CALTX_GAIN_SET_18_MACRO__ +#define __CALTX_GAIN_SET_18_MACRO__ + +/* macros for field caltx_gain_set_18 */ +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__SHIFT 0 +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__WIDTH 14 +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__MASK 0x00003fffU +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_19 */ +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__SHIFT 14 +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__WIDTH 14 +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__MASK 0x0fffc000U +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_18__TYPE u_int32_t +#define CALTX_GAIN_SET_18__READ 0x0fffffffU +#define CALTX_GAIN_SET_18__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_18_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_18 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_18__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_20 */ +#ifndef __CALTX_GAIN_SET_20_MACRO__ +#define __CALTX_GAIN_SET_20_MACRO__ + +/* macros for field caltx_gain_set_20 */ +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__SHIFT 0 +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__WIDTH 14 +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__MASK 0x00003fffU +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_21 */ +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__SHIFT 14 +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__WIDTH 14 +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__MASK 0x0fffc000U +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_20__TYPE u_int32_t +#define CALTX_GAIN_SET_20__READ 0x0fffffffU +#define CALTX_GAIN_SET_20__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_20_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_20 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_22 */ +#ifndef __CALTX_GAIN_SET_22_MACRO__ +#define __CALTX_GAIN_SET_22_MACRO__ + +/* macros for field caltx_gain_set_22 */ +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__SHIFT 0 +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__WIDTH 14 +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__MASK 0x00003fffU +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_23 */ +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__SHIFT 14 +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__WIDTH 14 +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__MASK 0x0fffc000U +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_22__TYPE u_int32_t +#define CALTX_GAIN_SET_22__READ 0x0fffffffU +#define CALTX_GAIN_SET_22__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_22_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_22 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_22__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_24 */ +#ifndef __CALTX_GAIN_SET_24_MACRO__ +#define __CALTX_GAIN_SET_24_MACRO__ + +/* macros for field caltx_gain_set_24 */ +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__SHIFT 0 +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__WIDTH 14 +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__MASK 0x00003fffU +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_25 */ +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__SHIFT 14 +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__WIDTH 14 +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__MASK 0x0fffc000U +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_24__TYPE u_int32_t +#define CALTX_GAIN_SET_24__READ 0x0fffffffU +#define CALTX_GAIN_SET_24__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_24_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_24 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_24__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_26 */ +#ifndef __CALTX_GAIN_SET_26_MACRO__ +#define __CALTX_GAIN_SET_26_MACRO__ + +/* macros for field caltx_gain_set_26 */ +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__SHIFT 0 +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__WIDTH 14 +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__MASK 0x00003fffU +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_27 */ +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__SHIFT 14 +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__WIDTH 14 +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__MASK 0x0fffc000U +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_26__TYPE u_int32_t +#define CALTX_GAIN_SET_26__READ 0x0fffffffU +#define CALTX_GAIN_SET_26__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_26_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_26 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_26__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_28 */ +#ifndef __CALTX_GAIN_SET_28_MACRO__ +#define __CALTX_GAIN_SET_28_MACRO__ + +/* macros for field caltx_gain_set_28 */ +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__SHIFT 0 +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__WIDTH 14 +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__MASK 0x00003fffU +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_29 */ +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__SHIFT 14 +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__WIDTH 14 +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__MASK 0x0fffc000U +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_28__TYPE u_int32_t +#define CALTX_GAIN_SET_28__READ 0x0fffffffU +#define CALTX_GAIN_SET_28__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_28_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_28 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_28__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_30 */ +#ifndef __CALTX_GAIN_SET_30_MACRO__ +#define __CALTX_GAIN_SET_30_MACRO__ + +/* macros for field caltx_gain_set_30 */ +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__SHIFT 0 +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__WIDTH 14 +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__MASK 0x00003fffU +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_31 */ +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__SHIFT 14 +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__WIDTH 14 +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__MASK 0x0fffc000U +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_30__TYPE u_int32_t +#define CALTX_GAIN_SET_30__READ 0x0fffffffU +#define CALTX_GAIN_SET_30__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_30_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_caltx_gain_set_30 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_30__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_start */ +#ifndef __TXIQCAL_START_MACRO__ +#define __TXIQCAL_START_MACRO__ + +/* macros for field do_tx_iqcal */ +/* Moved to 0xa5c4[31] in Poseidon */ +#define TXIQCAL_START__DO_TX_IQCAL__SHIFT 0 +#define TXIQCAL_START__DO_TX_IQCAL__WIDTH 1 +#define TXIQCAL_START__DO_TX_IQCAL__MASK 0x00000001U +#define TXIQCAL_START__DO_TX_IQCAL__READ(src) (u_int32_t)(src) & 0x00000001U +#define TXIQCAL_START__DO_TX_IQCAL__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TXIQCAL_START__DO_TX_IQCAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TXIQCAL_START__DO_TX_IQCAL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TXIQCAL_START__DO_TX_IQCAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXIQCAL_START__DO_TX_IQCAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define TXIQCAL_START__TYPE u_int32_t +#define TXIQCAL_START__READ 0x00000001U +#define TXIQCAL_START__WRITE 0x00000001U + +#endif /* __TXIQCAL_START_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiqcal_start */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQCAL_START__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_control_0 */ +#ifndef __TXIQCAL_CONTROL_0_MACRO__ +#define __TXIQCAL_CONTROL_0_MACRO__ + +/* macros for field iqc_tx_table_sel */ +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__SHIFT 0 +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__WIDTH 1 +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__MASK 0x00000001U +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field base_tx_tone_db */ +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__SHIFT 1 +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__WIDTH 6 +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__MASK 0x0000007eU +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000007eU) >> 1) +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000007eU) +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000007eU) +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000007eU))) + +/* macros for field max_tx_tone_gain */ +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__SHIFT 7 +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__WIDTH 6 +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__MASK 0x00001f80U +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f80U) >> 7) +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00001f80U) +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00001f80U) +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00001f80U))) + +/* macros for field min_tx_tone_gain */ +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__SHIFT 13 +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__WIDTH 6 +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__MASK 0x0007e000U +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0007e000U) >> 13) +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0007e000U) +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0007e000U) +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0007e000U))) + +/* macros for field caltxshift_delay */ +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__SHIFT 19 +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__WIDTH 4 +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__MASK 0x00780000U +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00780000U) >> 19) +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00780000U) +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00780000U) | (((u_int32_t)(src) <<\ + 19) & 0x00780000U) +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00780000U))) + +/* macros for field loopback_delay */ +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__SHIFT 23 +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__WIDTH 7 +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__MASK 0x3f800000U +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f800000U) >> 23) +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x3f800000U) +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x3f800000U) +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x3f800000U))) + +/* macros for field enable_combined_carr_iq_cal */ +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__SHIFT 30 +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__WIDTH 1 +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__MASK 0x40000000U +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +//#define TXIQCAL_CONTROL_0__TYPE u_int32_t +//#define TXIQCAL_CONTROL_0__READ 0x7fffffffU +//#define TXIQCAL_CONTROL_0__WRITE 0x7fffffffU + +#endif /* __TXIQCAL_CONTROL_0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiqcal_control_0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_control_1 */ +#ifndef __TXIQCAL_CONTROL_1_MACRO__ +#define __TXIQCAL_CONTROL_1_MACRO__ + +/* macros for field rx_init_gain_db */ +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__SHIFT 0 +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__WIDTH 6 +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__MASK 0x0000003fU +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field max_rx_gain_db */ +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__SHIFT 6 +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__WIDTH 6 +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__MASK 0x00000fc0U +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field min_rx_gain_db */ +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__SHIFT 12 +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__WIDTH 6 +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__MASK 0x0003f000U +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field iqcorr_i_q_coff_delpt */ +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__SHIFT 18 +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__WIDTH 7 +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__MASK 0x01fc0000U +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fc0000U) >> 18) +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x01fc0000U) +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x01fc0000U) +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x01fc0000U))) +#define TXIQCAL_CONTROL_1__TYPE u_int32_t +#define TXIQCAL_CONTROL_1__READ 0x01ffffffU +#define TXIQCAL_CONTROL_1__WRITE 0x01ffffffU + +#endif /* __TXIQCAL_CONTROL_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiqcal_control_1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_control_2 */ +#ifndef __TXIQCAL_CONTROL_2_MACRO__ +#define __TXIQCAL_CONTROL_2_MACRO__ + +/* macros for field iqc_forced_pagain */ +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__SHIFT 0 +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__WIDTH 4 +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__MASK 0x0000000fU +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field iqcal_min_tx_gain */ +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__SHIFT 4 +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__WIDTH 5 +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__MASK 0x000001f0U +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001f0U) >> 4) +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000001f0U) +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000001f0U) +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000001f0U))) + +/* macros for field iqcal_max_tx_gain */ +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__SHIFT 9 +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__WIDTH 5 +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__MASK 0x00003e00U +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003e00U) >> 9) +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00003e00U) +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00003e00U) +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00003e00U))) +#define TXIQCAL_CONTROL_2__TYPE u_int32_t +#define TXIQCAL_CONTROL_2__READ 0x00003fffU +#define TXIQCAL_CONTROL_2__WRITE 0x00003fffU + +#endif /* __TXIQCAL_CONTROL_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiqcal_control_2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b0 */ +#ifndef __TXIQ_CORR_COEFF_01_B0_MACRO__ +#define __TXIQ_CORR_COEFF_01_B0_MACRO__ + +/* macros for field iqc_coeff_table_0_0 */ +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__SHIFT 0 +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_1_0 */ +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__SHIFT 14 +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_01_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_01_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_01_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_01_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiq_corr_coeff_01_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_01_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b0 */ +#ifndef __TXIQ_CORR_COEFF_23_B0_MACRO__ +#define __TXIQ_CORR_COEFF_23_B0_MACRO__ + +/* macros for field iqc_coeff_table_2_0 */ +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__SHIFT 0 +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_3_0 */ +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__SHIFT 14 +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_23_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_23_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_23_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_23_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiq_corr_coeff_23_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_23_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b0 */ +#ifndef __TXIQ_CORR_COEFF_45_B0_MACRO__ +#define __TXIQ_CORR_COEFF_45_B0_MACRO__ + +/* macros for field iqc_coeff_table_4_0 */ +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__SHIFT 0 +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_5_0 */ +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__SHIFT 14 +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_45_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_45_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_45_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_45_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiq_corr_coeff_45_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_45_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b0 */ +#ifndef __TXIQ_CORR_COEFF_67_B0_MACRO__ +#define __TXIQ_CORR_COEFF_67_B0_MACRO__ + +/* macros for field iqc_coeff_table_6_0 */ +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__SHIFT 0 +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_7_0 */ +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__SHIFT 14 +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_67_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_67_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_67_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_67_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiq_corr_coeff_67_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_67_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b0 */ +#ifndef __TXIQ_CORR_COEFF_89_B0_MACRO__ +#define __TXIQ_CORR_COEFF_89_B0_MACRO__ + +/* macros for field iqc_coeff_table_8_0 */ +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__SHIFT 0 +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_9_0 */ +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__SHIFT 14 +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_89_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_89_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_89_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_89_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiq_corr_coeff_89_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_89_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b0 */ +#ifndef __TXIQ_CORR_COEFF_AB_B0_MACRO__ +#define __TXIQ_CORR_COEFF_AB_B0_MACRO__ + +/* macros for field iqc_coeff_table_a_0 */ +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__SHIFT 0 +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_b_0 */ +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__SHIFT 14 +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_AB_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_AB_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_AB_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_AB_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiq_corr_coeff_ab_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b0 */ +#ifndef __TXIQ_CORR_COEFF_CD_B0_MACRO__ +#define __TXIQ_CORR_COEFF_CD_B0_MACRO__ + +/* macros for field iqc_coeff_table_c_0 */ +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__SHIFT 0 +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_d_0 */ +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__SHIFT 14 +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_CD_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_CD_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_CD_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_CD_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiq_corr_coeff_cd_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b0 */ +#ifndef __TXIQ_CORR_COEFF_EF_B0_MACRO__ +#define __TXIQ_CORR_COEFF_EF_B0_MACRO__ + +/* macros for field iqc_coeff_table_e_0 */ +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__SHIFT 0 +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_f_0 */ +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__SHIFT 14 +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_EF_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_EF_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_EF_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_EF_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiq_corr_coeff_ef_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_0 */ +#ifndef __CAL_RXBB_GAIN_TBL_0_MACRO__ +#define __CAL_RXBB_GAIN_TBL_0_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_0 */ +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_1 */ +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_2 */ +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_3 */ +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_0__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_0__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_0__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_4 */ +#ifndef __CAL_RXBB_GAIN_TBL_4_MACRO__ +#define __CAL_RXBB_GAIN_TBL_4_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_4 */ +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_5 */ +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_6 */ +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_7 */ +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_4__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_4__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_4__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_4_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_4 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_8 */ +#ifndef __CAL_RXBB_GAIN_TBL_8_MACRO__ +#define __CAL_RXBB_GAIN_TBL_8_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_8 */ +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_9 */ +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_10 */ +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_11 */ +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_8__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_8__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_8__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_8_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_8 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_12 */ +#ifndef __CAL_RXBB_GAIN_TBL_12_MACRO__ +#define __CAL_RXBB_GAIN_TBL_12_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_12 */ +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_13 */ +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_14 */ +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_15 */ +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_12__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_12__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_12__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_12_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_12 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_16 */ +#ifndef __CAL_RXBB_GAIN_TBL_16_MACRO__ +#define __CAL_RXBB_GAIN_TBL_16_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_16 */ +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_17 */ +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_18 */ +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_19 */ +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_16__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_16__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_16__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_16_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_16 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_20 */ +#ifndef __CAL_RXBB_GAIN_TBL_20_MACRO__ +#define __CAL_RXBB_GAIN_TBL_20_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_20 */ +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_21 */ +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_22 */ +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_23 */ +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_20__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_20__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_20__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_20_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_20 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_24 */ +#ifndef __CAL_RXBB_GAIN_TBL_24_MACRO__ +#define __CAL_RXBB_GAIN_TBL_24_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_24 */ +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) +#define CAL_RXBB_GAIN_TBL_24__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_24__READ 0x000000ffU +#define CAL_RXBB_GAIN_TBL_24__WRITE 0x000000ffU + +#endif /* __CAL_RXBB_GAIN_TBL_24_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_24 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_24__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_status_b0 */ +#ifndef __TXIQCAL_STATUS_B0_MACRO__ +#define __TXIQCAL_STATUS_B0_MACRO__ + +/* macros for field txiqcal_failed_0 */ +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__SHIFT 0 +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__WIDTH 1 +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__MASK 0x00000001U +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field calibrated_gains_0 */ +#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__SHIFT 1 +#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__WIDTH 5 +#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__MASK 0x0000003eU +#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) + +/* macros for field tone_gain_used_0 */ +#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__SHIFT 6 +#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__WIDTH 6 +#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__MASK 0x00000fc0U +#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) + +/* macros for field rx_gain_used_0 */ +#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__SHIFT 12 +#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__WIDTH 6 +#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__MASK 0x0003f000U +#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) + +/* macros for field last_meas_addr_0 */ +#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__SHIFT 18 +#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__WIDTH 6 +#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__MASK 0x00fc0000U +#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TXIQCAL_STATUS_B0__TYPE u_int32_t +#define TXIQCAL_STATUS_B0__READ 0x00ffffffU + +#endif /* __TXIQCAL_STATUS_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiqcal_status_b0 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_TXIQCAL_STATUS_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl1 */ +#ifndef __PAPRD_TRAINER_CNTL1_MACRO__ +#define __PAPRD_TRAINER_CNTL1_MACRO__ + +/* macros for field cf_paprd_train_enable */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__SHIFT 0 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__WIDTH 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__MASK 0x00000001U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_paprd_agc2_settling */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__SHIFT 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__WIDTH 7 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__MASK 0x000000feU +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000feU) >> 1) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000000feU) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((u_int32_t)(src) <<\ + 1) & 0x000000feU) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000000feU))) + +/* macros for field cf_paprd_iqcorr_enable */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__SHIFT 8 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__WIDTH 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__MASK 0x00000100U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field cf_paprd_rx_bb_gain_force */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__SHIFT 9 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__WIDTH 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__MASK 0x00000200U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field cf_paprd_tx_gain_force */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__SHIFT 10 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__WIDTH 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__MASK 0x00000400U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field cf_paprd_lb_enable */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__SHIFT 11 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__WIDTH 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__MASK 0x00000800U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field cf_paprd_lb_skip */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__SHIFT 12 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__WIDTH 7 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__MASK 0x0007f000U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__READ(src) \ + (((u_int32_t)(src)\ + & 0x0007f000U) >> 12) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0007f000U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0007f000U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0007f000U))) +#define PAPRD_TRAINER_CNTL1__TYPE u_int32_t +#define PAPRD_TRAINER_CNTL1__READ 0x0007ffffU +#define PAPRD_TRAINER_CNTL1__WRITE 0x0007ffffU + +#endif /* __PAPRD_TRAINER_CNTL1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_paprd_trainer_cntl1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl2 */ +#ifndef __PAPRD_TRAINER_CNTL2_MACRO__ +#define __PAPRD_TRAINER_CNTL2_MACRO__ + +/* macros for field cf_paprd_init_rx_bb_gain */ +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__SHIFT 0 +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__WIDTH 32 +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__MASK 0xffffffffU +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define PAPRD_TRAINER_CNTL2__TYPE u_int32_t +#define PAPRD_TRAINER_CNTL2__READ 0xffffffffU +#define PAPRD_TRAINER_CNTL2__WRITE 0xffffffffU + +#endif /* __PAPRD_TRAINER_CNTL2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_paprd_trainer_cntl2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl3 */ +#ifndef __PAPRD_TRAINER_CNTL3_MACRO__ +#define __PAPRD_TRAINER_CNTL3_MACRO__ + +/* macros for field cf_paprd_adc_desired_size */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__SHIFT 0 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__WIDTH 6 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__MASK 0x0000003fU +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field cf_paprd_quick_drop */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__SHIFT 6 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__WIDTH 6 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__MASK 0x00000fc0U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field cf_paprd_min_loopback_del */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__SHIFT 12 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__WIDTH 5 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__MASK 0x0001f000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field cf_paprd_num_corr_stages */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__SHIFT 17 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__WIDTH 3 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__MASK 0x000e0000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field cf_paprd_coarse_corr_len */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__SHIFT 20 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__WIDTH 4 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__MASK 0x00f00000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) + +/* macros for field cf_paprd_fine_corr_len */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__SHIFT 24 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__WIDTH 4 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__MASK 0x0f000000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) + +/* macros for field cf_paprd_reuse_corr */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__SHIFT 28 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__WIDTH 1 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__MASK 0x10000000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field cf_paprd_bbtxmix_disable */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__SHIFT 29 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__WIDTH 1 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__MASK 0x20000000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define PAPRD_TRAINER_CNTL3__TYPE u_int32_t +#define PAPRD_TRAINER_CNTL3__READ 0x3fffffffU +#define PAPRD_TRAINER_CNTL3__WRITE 0x3fffffffU + +#endif /* __PAPRD_TRAINER_CNTL3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_paprd_trainer_cntl3 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl4 */ +#ifndef __PAPRD_TRAINER_CNTL4_MACRO__ +#define __PAPRD_TRAINER_CNTL4_MACRO__ + +/* macros for field cf_paprd_min_corr */ +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__SHIFT 0 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__WIDTH 12 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__MASK 0x00000fffU +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field cf_paprd_safety_delta */ +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__SHIFT 12 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__WIDTH 4 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__MASK 0x0000f000U +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field cf_paprd_num_train_samples */ +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__SHIFT 16 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__WIDTH 10 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__MASK 0x03ff0000U +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__READ(src) \ + (((u_int32_t)(src)\ + & 0x03ff0000U) >> 16) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x03ff0000U) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x03ff0000U) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define PAPRD_TRAINER_CNTL4__TYPE u_int32_t +#define PAPRD_TRAINER_CNTL4__READ 0x03ffffffU +#define PAPRD_TRAINER_CNTL4__WRITE 0x03ffffffU + +#endif /* __PAPRD_TRAINER_CNTL4_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_paprd_trainer_cntl4 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat1 */ +#ifndef __PAPRD_TRAINER_STAT1_MACRO__ +#define __PAPRD_TRAINER_STAT1_MACRO__ + +/* macros for field paprd_train_done */ +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__SHIFT 0 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__WIDTH 1 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__MASK 0x00000001U +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_train_incomplete */ +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__SHIFT 1 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__WIDTH 1 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__MASK 0x00000002U +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_corr_err */ +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__SHIFT 2 +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__WIDTH 1 +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__MASK 0x00000004U +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field paprd_train_active */ +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__SHIFT 3 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__WIDTH 1 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__MASK 0x00000008U +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field paprd_rx_gain_idx */ +#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__SHIFT 4 +#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__WIDTH 5 +#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__MASK 0x000001f0U +#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001f0U) >> 4) + +/* macros for field paprd_agc2_pwr */ +#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__SHIFT 9 +#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__WIDTH 8 +#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__MASK 0x0001fe00U +#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fe00U) >> 9) +#define PAPRD_TRAINER_STAT1__TYPE u_int32_t +#define PAPRD_TRAINER_STAT1__READ 0x0001ffffU +#define PAPRD_TRAINER_STAT1__WRITE 0x0001ffffU + +#endif /* __PAPRD_TRAINER_STAT1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_paprd_trainer_stat1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat2 */ +#ifndef __PAPRD_TRAINER_STAT2_MACRO__ +#define __PAPRD_TRAINER_STAT2_MACRO__ + +/* macros for field paprd_fine_val */ +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__SHIFT 0 +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__WIDTH 16 +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__MASK 0x0000ffffU +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field paprd_coarse_idx */ +#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__SHIFT 16 +#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__WIDTH 5 +#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__MASK 0x001f0000U +#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) + +/* macros for field paprd_fine_idx */ +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__SHIFT 21 +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__WIDTH 2 +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__MASK 0x00600000U +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00600000U) >> 21) +#define PAPRD_TRAINER_STAT2__TYPE u_int32_t +#define PAPRD_TRAINER_STAT2__READ 0x007fffffU + +#endif /* __PAPRD_TRAINER_STAT2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_paprd_trainer_stat2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat3 */ +#ifndef __PAPRD_TRAINER_STAT3_MACRO__ +#define __PAPRD_TRAINER_STAT3_MACRO__ + +/* macros for field paprd_train_samples_cnt */ +#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__SHIFT 0 +#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__WIDTH 20 +#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__MASK 0x000fffffU +#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__READ(src) \ + (u_int32_t)(src)\ + & 0x000fffffU +#define PAPRD_TRAINER_STAT3__TYPE u_int32_t +#define PAPRD_TRAINER_STAT3__READ 0x000fffffU + +#endif /* __PAPRD_TRAINER_STAT3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_paprd_trainer_stat3 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::panic_watchdog_status */ +#ifndef __PANIC_WATCHDOG_STATUS_MACRO__ +#define __PANIC_WATCHDOG_STATUS_MACRO__ + +/* macros for field panic_watchdog_status_1 */ +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__SHIFT 0 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__WIDTH 3 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__MASK 0x00000007U +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field panic_watchdog_det_hang */ +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__SHIFT 3 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__WIDTH 1 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__MASK 0x00000008U +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field panic_watchdog_status_2 */ +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__SHIFT 4 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__WIDTH 4 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__MASK 0x000000f0U +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field panic_watchdog_status_3 */ +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__SHIFT 8 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__WIDTH 4 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__MASK 0x00000f00U +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field panic_watchdog_status_4 */ +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__SHIFT 12 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__WIDTH 4 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__MASK 0x0000f000U +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field panic_watchdog_status_5 */ +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__SHIFT 16 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__WIDTH 4 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__MASK 0x000f0000U +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field panic_watchdog_status_6 */ +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__SHIFT 20 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__WIDTH 4 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__MASK 0x00f00000U +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) + +/* macros for field panic_watchdog_status_7 */ +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__SHIFT 24 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__WIDTH 4 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__MASK 0x0f000000U +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) + +/* macros for field panic_watchdog_status_8 */ +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__SHIFT 28 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__WIDTH 4 +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__MASK 0xf0000000U +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__READ(src) \ + (((u_int32_t)(src)\ + & 0xf0000000U) >> 28) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0xf0000000U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((u_int32_t)(src) <<\ + 28) & 0xf0000000U) +#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0xf0000000U))) +#define PANIC_WATCHDOG_STATUS__TYPE u_int32_t +#define PANIC_WATCHDOG_STATUS__READ 0xffffffffU +#define PANIC_WATCHDOG_STATUS__WRITE 0xffffffffU + +#endif /* __PANIC_WATCHDOG_STATUS_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_panic_watchdog_status */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PANIC_WATCHDOG_STATUS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::panic_watchdog_ctrl_1 */ +#ifndef __PANIC_WATCHDOG_CTRL_1_MACRO__ +#define __PANIC_WATCHDOG_CTRL_1_MACRO__ + +/* macros for field enable_panic_watchdog_non_idle */ +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__SHIFT 0 +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__WIDTH 1 +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__MASK 0x00000001U +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field enable_panic_watchdog_idle */ +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__SHIFT 1 +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__WIDTH 1 +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__MASK 0x00000002U +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field panic_watchdog_non_idle_limit */ +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__SHIFT 2 +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__WIDTH 14 +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__MASK 0x0000fffcU +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fffcU) >> 2) +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000fffcU) +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0000fffcU) +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000fffcU))) + +/* macros for field panic_watchdog_idle_limit */ +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__SHIFT 16 +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__WIDTH 16 +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__MASK 0xffff0000U +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define PANIC_WATCHDOG_CTRL_1__TYPE u_int32_t +#define PANIC_WATCHDOG_CTRL_1__READ 0xffffffffU +#define PANIC_WATCHDOG_CTRL_1__WRITE 0xffffffffU + +#endif /* __PANIC_WATCHDOG_CTRL_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_panic_watchdog_ctrl_1 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PANIC_WATCHDOG_CTRL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::panic_watchdog_ctrl_2 */ +#ifndef __PANIC_WATCHDOG_CTRL_2_MACRO__ +#define __PANIC_WATCHDOG_CTRL_2_MACRO__ + +/* macros for field force_fast_adc_clk */ +#define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__SHIFT 0 +#define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__WIDTH 1 +#define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__MASK 0x00000001U +#define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field panic_watchdog_reset_ena */ +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__SHIFT 1 +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__WIDTH 1 +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__MASK 0x00000002U +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field panic_watchdog_irq_ena */ +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__SHIFT 2 +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__WIDTH 1 +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__MASK 0x00000004U +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define PANIC_WATCHDOG_CTRL_2__TYPE u_int32_t +#define PANIC_WATCHDOG_CTRL_2__READ 0x00000007U +#define PANIC_WATCHDOG_CTRL_2__WRITE 0x00000007U + +#endif /* __PANIC_WATCHDOG_CTRL_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_panic_watchdog_ctrl_2 */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PANIC_WATCHDOG_CTRL_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bluetooth_cntl */ +#ifndef __BLUETOOTH_CNTL_MACRO__ +#define __BLUETOOTH_CNTL_MACRO__ + +/* macros for field bt_break_cck_en */ +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__SHIFT 0 +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__WIDTH 1 +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__MASK 0x00000001U +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field bt_ant_halt_wlan */ +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__SHIFT 1 +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__WIDTH 1 +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__MASK 0x00000002U +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define BLUETOOTH_CNTL__TYPE u_int32_t +#define BLUETOOTH_CNTL__READ 0x00000003U +#define BLUETOOTH_CNTL__WRITE 0x00000003U + +#endif /* __BLUETOOTH_CNTL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_bluetooth_cntl */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_BLUETOOTH_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::phyonly_warm_reset */ +#ifndef __PHYONLY_WARM_RESET_MACRO__ +#define __PHYONLY_WARM_RESET_MACRO__ + +/* macros for field phyonly_rst_warm_l */ +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__SHIFT 0 +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__WIDTH 1 +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__MASK 0x00000001U +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define PHYONLY_WARM_RESET__TYPE u_int32_t +#define PHYONLY_WARM_RESET__READ 0x00000001U +#define PHYONLY_WARM_RESET__WRITE 0x00000001U + +#endif /* __PHYONLY_WARM_RESET_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_phyonly_warm_reset */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PHYONLY_WARM_RESET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::phyonly_control */ +#ifndef __PHYONLY_CONTROL_MACRO__ +#define __PHYONLY_CONTROL_MACRO__ + +/* macros for field rx_drain_rate */ +#define PHYONLY_CONTROL__RX_DRAIN_RATE__SHIFT 0 +#define PHYONLY_CONTROL__RX_DRAIN_RATE__WIDTH 1 +#define PHYONLY_CONTROL__RX_DRAIN_RATE__MASK 0x00000001U +#define PHYONLY_CONTROL__RX_DRAIN_RATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PHYONLY_CONTROL__RX_DRAIN_RATE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PHYONLY_CONTROL__RX_DRAIN_RATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PHYONLY_CONTROL__RX_DRAIN_RATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PHYONLY_CONTROL__RX_DRAIN_RATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PHYONLY_CONTROL__RX_DRAIN_RATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field late_tx_signal_symbol */ +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__SHIFT 1 +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__WIDTH 1 +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__MASK 0x00000002U +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field generate_scrambler */ +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__SHIFT 2 +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__WIDTH 1 +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__MASK 0x00000004U +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field tx_antenna_select */ +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__SHIFT 3 +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__WIDTH 1 +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__MASK 0x00000008U +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field static_tx_antenna */ +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__SHIFT 4 +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__WIDTH 1 +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__MASK 0x00000010U +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field rx_antenna_select */ +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__SHIFT 5 +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__WIDTH 1 +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__MASK 0x00000020U +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field static_rx_antenna */ +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__SHIFT 6 +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__WIDTH 1 +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__MASK 0x00000040U +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field en_low_freq_sleep */ +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__SHIFT 7 +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__WIDTH 1 +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__MASK 0x00000080U +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) +#define PHYONLY_CONTROL__TYPE u_int32_t +#define PHYONLY_CONTROL__READ 0x000000ffU +#define PHYONLY_CONTROL__WRITE 0x000000ffU + +#endif /* __PHYONLY_CONTROL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_phyonly_control */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_PHYONLY_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::eco_ctrl */ +#ifndef __ECO_CTRL_MACRO__ +#define __ECO_CTRL_MACRO__ + +/* macros for field eco_ctrl */ +#define ECO_CTRL__ECO_CTRL__SHIFT 0 +#define ECO_CTRL__ECO_CTRL__WIDTH 8 +#define ECO_CTRL__ECO_CTRL__MASK 0x000000ffU +#define ECO_CTRL__ECO_CTRL__READ(src) (u_int32_t)(src) & 0x000000ffU +#define ECO_CTRL__ECO_CTRL__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define ECO_CTRL__ECO_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define ECO_CTRL__ECO_CTRL__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) +#define ECO_CTRL__TYPE u_int32_t +#define ECO_CTRL__READ 0x000000ffU +#define ECO_CTRL__WRITE 0x000000ffU + +#endif /* __ECO_CTRL_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_reg_map.BB_eco_ctrl */ +#define INST_BB_REG_BLOCK__BB_SM_REG_MAP__BB_ECO_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_dummy_DONOTACCESS1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_DUMMY_DONOTACCESS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b1 */ +#ifndef __EXT_CHAN_PWR_THR_2_B1_MACRO__ +#define __EXT_CHAN_PWR_THR_2_B1_MACRO__ + +/* macros for field cf_maxCCApwr_ext_1 */ +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__SHIFT 0 +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__MASK 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field minCCApwr_ext_1 */ +#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__SHIFT 16 +#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__MASK 0x01ff0000U +#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01ff0000U) >> 16) +#define EXT_CHAN_PWR_THR_2_B1__TYPE u_int32_t +#define EXT_CHAN_PWR_THR_2_B1__READ 0x01ff01ffU +#define EXT_CHAN_PWR_THR_2_B1__WRITE 0x01ff01ffU + +#endif /* __EXT_CHAN_PWR_THR_2_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_ext_chan_pwr_thr_2_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_report_b1 */ +#ifndef __SPUR_REPORT_B1_MACRO__ +#define __SPUR_REPORT_B1_MACRO__ + +/* macros for field spur_est_i_1 */ +#define SPUR_REPORT_B1__SPUR_EST_I_1__SHIFT 0 +#define SPUR_REPORT_B1__SPUR_EST_I_1__WIDTH 8 +#define SPUR_REPORT_B1__SPUR_EST_I_1__MASK 0x000000ffU +#define SPUR_REPORT_B1__SPUR_EST_I_1__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field spur_est_q_1 */ +#define SPUR_REPORT_B1__SPUR_EST_Q_1__SHIFT 8 +#define SPUR_REPORT_B1__SPUR_EST_Q_1__WIDTH 8 +#define SPUR_REPORT_B1__SPUR_EST_Q_1__MASK 0x0000ff00U +#define SPUR_REPORT_B1__SPUR_EST_Q_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field power_with_spur_removed_1 */ +#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__SHIFT 16 +#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__WIDTH 16 +#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__MASK 0xffff0000U +#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define SPUR_REPORT_B1__TYPE u_int32_t +#define SPUR_REPORT_B1__READ 0xffffffffU + +#endif /* __SPUR_REPORT_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_spur_report_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_SPUR_REPORT_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b1 */ +#ifndef __IQ_ADC_MEAS_0_B1_MACRO__ +#define __IQ_ADC_MEAS_0_B1_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_0_1 */ +#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__SHIFT 0 +#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__WIDTH 32 +#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__MASK 0xffffffffU +#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_0_B1__TYPE u_int32_t +#define IQ_ADC_MEAS_0_B1__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_0_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_iq_adc_meas_0_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_0_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b1 */ +#ifndef __IQ_ADC_MEAS_1_B1_MACRO__ +#define __IQ_ADC_MEAS_1_B1_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_1_1 */ +#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__SHIFT 0 +#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__WIDTH 32 +#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__MASK 0xffffffffU +#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_1_B1__TYPE u_int32_t +#define IQ_ADC_MEAS_1_B1__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_1_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_iq_adc_meas_1_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_1_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b1 */ +#ifndef __IQ_ADC_MEAS_2_B1_MACRO__ +#define __IQ_ADC_MEAS_2_B1_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_2_1 */ +#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__SHIFT 0 +#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__WIDTH 32 +#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__MASK 0xffffffffU +#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_2_B1__TYPE u_int32_t +#define IQ_ADC_MEAS_2_B1__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_2_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_iq_adc_meas_2_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b1 */ +#ifndef __IQ_ADC_MEAS_3_B1_MACRO__ +#define __IQ_ADC_MEAS_3_B1_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_3_1 */ +#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__SHIFT 0 +#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__WIDTH 32 +#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__MASK 0xffffffffU +#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_3_B1__TYPE u_int32_t +#define IQ_ADC_MEAS_3_B1__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_3_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_iq_adc_meas_3_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_3_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b1 */ +#ifndef __TX_PHASE_RAMP_B1_MACRO__ +#define __TX_PHASE_RAMP_B1_MACRO__ + +/* macros for field cf_phase_ramp_enable_1 */ +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__SHIFT 0 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__WIDTH 1 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__MASK 0x00000001U +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_phase_ramp_bias_1 */ +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__SHIFT 1 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__WIDTH 6 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__MASK 0x0000007eU +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000007eU) >> 1) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000007eU))) + +/* macros for field cf_phase_ramp_init_1 */ +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__SHIFT 7 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__WIDTH 10 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__MASK 0x0001ff80U +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001ff80U) >> 7) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ff80U) | (((u_int32_t)(src) <<\ + 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x0001ff80U))) + +/* macros for field cf_phase_ramp_alpha_1 */ +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__SHIFT 17 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__WIDTH 8 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__MASK 0x01fe0000U +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fe0000U) >> 17) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x01fe0000U))) +#define TX_PHASE_RAMP_B1__TYPE u_int32_t +#define TX_PHASE_RAMP_B1__READ 0x01ffffffU +#define TX_PHASE_RAMP_B1__WRITE 0x01ffffffU + +#endif /* __TX_PHASE_RAMP_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_tx_phase_ramp_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_TX_PHASE_RAMP_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b1 */ +#ifndef __ADC_GAIN_DC_CORR_B1_MACRO__ +#define __ADC_GAIN_DC_CORR_B1_MACRO__ + +/* macros for field adc_gain_corr_q_coeff_1 */ +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__SHIFT 0 +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__WIDTH 6 +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__MASK 0x0000003fU +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field adc_gain_corr_i_coeff_1 */ +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__SHIFT 6 +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__WIDTH 6 +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__MASK 0x00000fc0U +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field adc_dc_corr_q_coeff_1 */ +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__SHIFT 12 +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__WIDTH 9 +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__MASK 0x001ff000U +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x001ff000U) >> 12) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x001ff000U))) + +/* macros for field adc_dc_corr_i_coeff_1 */ +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__SHIFT 21 +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__WIDTH 9 +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__MASK 0x3fe00000U +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x3fe00000U) >> 21) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x3fe00000U))) +#define ADC_GAIN_DC_CORR_B1__TYPE u_int32_t +#define ADC_GAIN_DC_CORR_B1__READ 0x3fffffffU +#define ADC_GAIN_DC_CORR_B1__WRITE 0x3fffffffU + +#endif /* __ADC_GAIN_DC_CORR_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_adc_gain_dc_corr_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_ADC_GAIN_DC_CORR_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b1 */ +#ifndef __RX_IQ_CORR_B1_MACRO__ +#define __RX_IQ_CORR_B1_MACRO__ + +/* macros for field rx_iqcorr_q_q_coff_1 */ +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__SHIFT 0 +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__WIDTH 7 +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__MASK 0x0000007fU +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field rx_iqcorr_q_i_coff_1 */ +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__SHIFT 7 +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__WIDTH 7 +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__MASK 0x00003f80U +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f80U) >> 7) +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00003f80U) +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00003f80U) +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00003f80U))) + +/* macros for field loopback_iqcorr_q_q_coff_1 */ +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__SHIFT 15 +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__WIDTH 7 +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__MASK 0x003f8000U +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f8000U) >> 15) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x003f8000U) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x003f8000U) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x003f8000U))) + +/* macros for field loopback_iqcorr_q_i_coff_1 */ +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__SHIFT 22 +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__WIDTH 7 +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__MASK 0x1fc00000U +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x1fc00000U) >> 22) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x1fc00000U) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x1fc00000U) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x1fc00000U))) +#define RX_IQ_CORR_B1__TYPE u_int32_t +#define RX_IQ_CORR_B1__READ 0x1fffbfffU +#define RX_IQ_CORR_B1__WRITE 0x1fffbfffU + +#endif /* __RX_IQ_CORR_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_rx_iq_corr_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_RX_IQ_CORR_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b1 */ +#ifndef __PAPRD_CTRL0_B1_MACRO__ +#define __PAPRD_CTRL0_B1_MACRO__ + +/* macros for field paprd_enable_1 */ +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__SHIFT 0 +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__WIDTH 1 +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__MASK 0x00000001U +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_use_single_table_1 */ +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__SHIFT 1 +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__WIDTH 1 +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__MASK 0x00000002U +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_valid_gain_1 */ +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__SHIFT 2 +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__WIDTH 25 +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__MASK 0x07fffffcU +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fffffcU) >> 2) +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fffffcU) | (((u_int32_t)(src) <<\ + 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x07fffffcU))) + +/* macros for field paprd_mag_thrsh_1 */ +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__SHIFT 27 +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__WIDTH 5 +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__MASK 0xf8000000U +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define PAPRD_CTRL0_B1__TYPE u_int32_t +#define PAPRD_CTRL0_B1__READ 0xffffffffU +#define PAPRD_CTRL0_B1__WRITE 0xffffffffU + +#endif /* __PAPRD_CTRL0_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_paprd_ctrl0_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PAPRD_CTRL0_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b1 */ +#ifndef __PAPRD_CTRL1_B1_MACRO__ +#define __PAPRD_CTRL1_B1_MACRO__ + +/* macros for field paprd_adaptive_scaling_enable_1 */ +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__SHIFT 0 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__WIDTH 1 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__MASK 0x00000001U +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_am2am_enable_1 */ +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__SHIFT 1 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__WIDTH 1 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__MASK 0x00000002U +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_adaptive_am2pm_enable_1 */ +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__SHIFT 2 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__WIDTH 1 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__MASK 0x00000004U +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field paprd_power_at_am2am_cal_1 */ +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__SHIFT 3 +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__WIDTH 6 +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__MASK 0x000001f8U +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001f8U) >> 3) +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000001f8U) +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000001f8U) +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000001f8U))) + +/* macros for field pa_gain_scale_factor_1 */ +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__SHIFT 9 +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__WIDTH 8 +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__MASK 0x0001fe00U +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fe00U) >> 9) +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((u_int32_t)(src) <<\ + 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x0001fe00U))) + +/* macros for field paprd_mag_scale_factor_1 */ +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__SHIFT 17 +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__WIDTH 10 +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__MASK 0x07fe0000U +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fe0000U) >> 17) +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x07fe0000U))) + +/* macros for field paprd_trainer_iandq_sel_1 */ +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__SHIFT 27 +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__WIDTH 1 +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__MASK 0x08000000U +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) +#define PAPRD_CTRL1_B1__TYPE u_int32_t +#define PAPRD_CTRL1_B1__READ 0x0fffffffU +#define PAPRD_CTRL1_B1__WRITE 0x0fffffffU + +#endif /* __PAPRD_CTRL1_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_paprd_ctrl1_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PAPRD_CTRL1_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain123_b1 */ +#ifndef __PA_GAIN123_B1_MACRO__ +#define __PA_GAIN123_B1_MACRO__ + +/* macros for field pa_gain1_1 */ +#define PA_GAIN123_B1__PA_GAIN1_1__SHIFT 0 +#define PA_GAIN123_B1__PA_GAIN1_1__WIDTH 10 +#define PA_GAIN123_B1__PA_GAIN1_1__MASK 0x000003ffU +#define PA_GAIN123_B1__PA_GAIN1_1__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN123_B1__PA_GAIN1_1__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN123_B1__PA_GAIN1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN123_B1__PA_GAIN1_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain2_1 */ +#define PA_GAIN123_B1__PA_GAIN2_1__SHIFT 10 +#define PA_GAIN123_B1__PA_GAIN2_1__WIDTH 10 +#define PA_GAIN123_B1__PA_GAIN2_1__MASK 0x000ffc00U +#define PA_GAIN123_B1__PA_GAIN2_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN123_B1__PA_GAIN2_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN123_B1__PA_GAIN2_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN123_B1__PA_GAIN2_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field pa_gain3_1 */ +#define PA_GAIN123_B1__PA_GAIN3_1__SHIFT 20 +#define PA_GAIN123_B1__PA_GAIN3_1__WIDTH 10 +#define PA_GAIN123_B1__PA_GAIN3_1__MASK 0x3ff00000U +#define PA_GAIN123_B1__PA_GAIN3_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ff00000U) >> 20) +#define PA_GAIN123_B1__PA_GAIN3_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x3ff00000U) +#define PA_GAIN123_B1__PA_GAIN3_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x3ff00000U) +#define PA_GAIN123_B1__PA_GAIN3_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define PA_GAIN123_B1__TYPE u_int32_t +#define PA_GAIN123_B1__READ 0x3fffffffU +#define PA_GAIN123_B1__WRITE 0x3fffffffU + +#endif /* __PA_GAIN123_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_pa_gain123_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PA_GAIN123_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain45_b1 */ +#ifndef __PA_GAIN45_B1_MACRO__ +#define __PA_GAIN45_B1_MACRO__ + +/* macros for field pa_gain4_1 */ +#define PA_GAIN45_B1__PA_GAIN4_1__SHIFT 0 +#define PA_GAIN45_B1__PA_GAIN4_1__WIDTH 10 +#define PA_GAIN45_B1__PA_GAIN4_1__MASK 0x000003ffU +#define PA_GAIN45_B1__PA_GAIN4_1__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN45_B1__PA_GAIN4_1__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN45_B1__PA_GAIN4_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN45_B1__PA_GAIN4_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain5_1 */ +#define PA_GAIN45_B1__PA_GAIN5_1__SHIFT 10 +#define PA_GAIN45_B1__PA_GAIN5_1__WIDTH 10 +#define PA_GAIN45_B1__PA_GAIN5_1__MASK 0x000ffc00U +#define PA_GAIN45_B1__PA_GAIN5_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN45_B1__PA_GAIN5_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN45_B1__PA_GAIN5_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN45_B1__PA_GAIN5_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field paprd_adaptive_table_valid_1 */ +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__SHIFT 20 +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__WIDTH 5 +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__MASK 0x01f00000U +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) +#define PA_GAIN45_B1__TYPE u_int32_t +#define PA_GAIN45_B1__READ 0x01ffffffU +#define PA_GAIN45_B1__WRITE 0x01ffffffU + +#endif /* __PA_GAIN45_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_pa_gain45_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PA_GAIN45_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_0_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_0_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_0_1 */ +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_0_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_0_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_0_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_paprd_pre_post_scale_0_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_1_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_1_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_1_1 */ +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_1_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_1_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_1_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_paprd_pre_post_scale_1_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_2_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_2_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_2_1 */ +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_2_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_2_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_2_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_paprd_pre_post_scale_2_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_3_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_3_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_3_1 */ +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_3_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_3_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_3_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_paprd_pre_post_scale_3_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_4_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_4_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_4_1 */ +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_4_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_4_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_4_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_paprd_pre_post_scale_4_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_5_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_5_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_5_1 */ +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_5_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_5_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_5_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_paprd_pre_post_scale_5_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_6_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_6_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_6_1 */ +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_6_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_6_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_6_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_paprd_pre_post_scale_6_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_7_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_7_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_7_1 */ +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_7_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_7_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_7_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_paprd_pre_post_scale_7_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */ +#ifndef __PAPRD_MEM_TAB_MACRO__ +#define __PAPRD_MEM_TAB_MACRO__ + +/* macros for field paprd_mem */ +#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT 0 +#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH 22 +#define PAPRD_MEM_TAB__PAPRD_MEM__MASK 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((u_int32_t)(src) &\ + 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x003fffffU))) +#define PAPRD_MEM_TAB__TYPE u_int32_t +#define PAPRD_MEM_TAB__READ 0x003fffffU +#define PAPRD_MEM_TAB__WRITE 0x003fffffU + +#endif /* __PAPRD_MEM_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_paprd_mem_tab_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_PAPRD_MEM_TAB_B1__NUM 120 + +/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */ +#ifndef __CHAN_INFO_CHAN_TAB_MACRO__ +#define __CHAN_INFO_CHAN_TAB_MACRO__ + +/* macros for field chaninfo_word */ +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT 0 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH 32 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK 0xffffffffU +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define CHAN_INFO_CHAN_TAB__TYPE u_int32_t +#define CHAN_INFO_CHAN_TAB__READ 0xffffffffU + +#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn1_reg_map.BB_chan_info_chan_tab_b1 */ +#define INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B1__NUM 60 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc1_reg_map.BB_dummy_DONOTACCESS3 */ +#define INST_BB_REG_BLOCK__BB_AGC1_REG_MAP__BB_DUMMY_DONOTACCESS3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b1 */ +#ifndef __GAIN_FORCE_MAX_GAINS_B1_MACRO__ +#define __GAIN_FORCE_MAX_GAINS_B1_MACRO__ + +/* macros for field rf_gain_f_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__SHIFT 0 +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__MASK 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field mb_gain_f_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__SHIFT 8 +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__MASK 0x0000ff00U +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field xatten1_sw_f_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__SHIFT 16 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__MASK 0x00010000U +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field xatten2_sw_f_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__SHIFT 17 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__MASK 0x00020000U +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field xatten1_hyst_margin_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__SHIFT 18 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__MASK 0x01fc0000U +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fc0000U) >> 18) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x01fc0000U))) + +/* macros for field xatten2_hyst_margin_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__SHIFT 25 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__MASK 0xfe000000U +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0xfe000000U) >> 25) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfe000000U) | (((u_int32_t)(src) <<\ + 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0xfe000000U))) +#define GAIN_FORCE_MAX_GAINS_B1__TYPE u_int32_t +#define GAIN_FORCE_MAX_GAINS_B1__READ 0xffffffffU +#define GAIN_FORCE_MAX_GAINS_B1__WRITE 0xffffffffU + +#endif /* __GAIN_FORCE_MAX_GAINS_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc1_reg_map.BB_gain_force_max_gains_b1 */ +#define INST_BB_REG_BLOCK__BB_AGC1_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b1 */ +#ifndef __EXT_ATTEN_SWITCH_CTL_B1_MACRO__ +#define __EXT_ATTEN_SWITCH_CTL_B1_MACRO__ + +/* macros for field xatten1_db_1 */ +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__SHIFT 0 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__MASK 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field xatten2_db_1 */ +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__SHIFT 6 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__MASK 0x00000fc0U +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field xatten1_margin_1 */ +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__SHIFT 12 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__MASK 0x0001f000U +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field xatten2_margin_1 */ +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__SHIFT 17 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__MASK 0x003e0000U +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field xlna_gain_db_1 */ +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__SHIFT 22 +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__MASK 0x07c00000U +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) +#define EXT_ATTEN_SWITCH_CTL_B1__TYPE u_int32_t +#define EXT_ATTEN_SWITCH_CTL_B1__READ 0x07ffffffU +#define EXT_ATTEN_SWITCH_CTL_B1__WRITE 0x07ffffffU + +#endif /* __EXT_ATTEN_SWITCH_CTL_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc1_reg_map.BB_ext_atten_switch_ctl_b1 */ +#define INST_BB_REG_BLOCK__BB_AGC1_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_b1 */ +#ifndef __CCA_B1_MACRO__ +#define __CCA_B1_MACRO__ + +/* macros for field cf_maxCCApwr_1 */ +#define CCA_B1__CF_MAXCCAPWR_1__SHIFT 0 +#define CCA_B1__CF_MAXCCAPWR_1__WIDTH 9 +#define CCA_B1__CF_MAXCCAPWR_1__MASK 0x000001ffU +#define CCA_B1__CF_MAXCCAPWR_1__READ(src) (u_int32_t)(src) & 0x000001ffU +#define CCA_B1__CF_MAXCCAPWR_1__WRITE(src) ((u_int32_t)(src) & 0x000001ffU) +#define CCA_B1__CF_MAXCCAPWR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_B1__CF_MAXCCAPWR_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field minCCApwr_1 */ +#define CCA_B1__MINCCAPWR_1__SHIFT 20 +#define CCA_B1__MINCCAPWR_1__WIDTH 9 +#define CCA_B1__MINCCAPWR_1__MASK 0x1ff00000U +#define CCA_B1__MINCCAPWR_1__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20) +#define CCA_B1__TYPE u_int32_t +#define CCA_B1__READ 0x1ff001ffU +#define CCA_B1__WRITE 0x1ff001ffU + +#endif /* __CCA_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc1_reg_map.BB_cca_b1 */ +#define INST_BB_REG_BLOCK__BB_AGC1_REG_MAP__BB_CCA_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b1 */ +#ifndef __CCA_CTRL_2_B1_MACRO__ +#define __CCA_CTRL_2_B1_MACRO__ + +/* macros for field minCCApwr_thr_1 */ +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__SHIFT 0 +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__WIDTH 9 +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__MASK 0x000001ffU +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field NF_gain_comp_1 */ +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__SHIFT 10 +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__WIDTH 8 +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__MASK 0x0003fc00U +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fc00U) >> 10) +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0003fc00U) +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0003fc00U) +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0003fc00U))) +#define CCA_CTRL_2_B1__TYPE u_int32_t +#define CCA_CTRL_2_B1__READ 0x0003fdffU +#define CCA_CTRL_2_B1__WRITE 0x0003fdffU + +#endif /* __CCA_CTRL_2_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc1_reg_map.BB_cca_ctrl_2_b1 */ +#define INST_BB_REG_BLOCK__BB_AGC1_REG_MAP__BB_CCA_CTRL_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rssi_b1 */ +#ifndef __RSSI_B1_MACRO__ +#define __RSSI_B1_MACRO__ + +/* macros for field rssi_1 */ +#define RSSI_B1__RSSI_1__SHIFT 0 +#define RSSI_B1__RSSI_1__WIDTH 8 +#define RSSI_B1__RSSI_1__MASK 0x000000ffU +#define RSSI_B1__RSSI_1__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field rssi_ext_1 */ +#define RSSI_B1__RSSI_EXT_1__SHIFT 8 +#define RSSI_B1__RSSI_EXT_1__WIDTH 8 +#define RSSI_B1__RSSI_EXT_1__MASK 0x0000ff00U +#define RSSI_B1__RSSI_EXT_1__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define RSSI_B1__TYPE u_int32_t +#define RSSI_B1__READ 0x0000ffffU + +#endif /* __RSSI_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc1_reg_map.BB_rssi_b1 */ +#define INST_BB_REG_BLOCK__BB_AGC1_REG_MAP__BB_RSSI_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_est_cck_report_b1 */ +#ifndef __SPUR_EST_CCK_REPORT_B1_MACRO__ +#define __SPUR_EST_CCK_REPORT_B1_MACRO__ + +/* macros for field spur_est_sd_i_1_cck */ +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__SHIFT 0 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__MASK 0x000000ffU +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field spur_est_sd_q_1_cck */ +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__SHIFT 8 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__MASK 0x0000ff00U +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field spur_est_i_1_cck */ +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__SHIFT 16 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__MASK 0x00ff0000U +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) + +/* macros for field spur_est_q_1_cck */ +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__SHIFT 24 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__MASK 0xff000000U +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define SPUR_EST_CCK_REPORT_B1__TYPE u_int32_t +#define SPUR_EST_CCK_REPORT_B1__READ 0xffffffffU + +#endif /* __SPUR_EST_CCK_REPORT_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc1_reg_map.BB_spur_est_cck_report_b1 */ +#define INST_BB_REG_BLOCK__BB_AGC1_REG_MAP__BB_SPUR_EST_CCK_REPORT_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b1 */ +#ifndef __AGC_DIG_DC_STATUS_I_B1_MACRO__ +#define __AGC_DIG_DC_STATUS_I_B1_MACRO__ + +/* macros for field dig_dc_C1_res_i_1 */ +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__SHIFT 0 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_i_1 */ +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__SHIFT 9 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_i_1 */ +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__SHIFT 18 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_I_B1__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_I_B1__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_I_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc1_reg_map.BB_agc_dig_dc_status_i_b1 */ +#define INST_BB_REG_BLOCK__BB_AGC1_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b1 */ +#ifndef __AGC_DIG_DC_STATUS_Q_B1_MACRO__ +#define __AGC_DIG_DC_STATUS_Q_B1_MACRO__ + +/* macros for field dig_dc_C1_res_q_1 */ +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__SHIFT 0 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_q_1 */ +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__SHIFT 9 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_q_1 */ +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__SHIFT 18 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_Q_B1__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_Q_B1__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_Q_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc1_reg_map.BB_agc_dig_dc_status_q_b1 */ +#define INST_BB_REG_BLOCK__BB_AGC1_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_ocgain2 */ +#ifndef __RX_OCGAIN2_MACRO__ +#define __RX_OCGAIN2_MACRO__ + +/* macros for field gain_entry2 */ +#define RX_OCGAIN2__GAIN_ENTRY2__SHIFT 0 +#define RX_OCGAIN2__GAIN_ENTRY2__WIDTH 32 +#define RX_OCGAIN2__GAIN_ENTRY2__MASK 0xffffffffU +#define RX_OCGAIN2__GAIN_ENTRY2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define RX_OCGAIN2__GAIN_ENTRY2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define RX_OCGAIN2__GAIN_ENTRY2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define RX_OCGAIN2__TYPE u_int32_t +#define RX_OCGAIN2__WRITE 0x00000000U + +#endif /* __RX_OCGAIN2_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc1_reg_map.BB_rx_ocgain2 */ +#define INST_BB_REG_BLOCK__BB_AGC1_REG_MAP__BB_RX_OCGAIN2__NUM 128 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_dummy_DONOTACCESS5 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_DUMMY_DONOTACCESS5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::switch_table_chn_b1 */ +#ifndef __SWITCH_TABLE_CHN_B1_MACRO__ +#define __SWITCH_TABLE_CHN_B1_MACRO__ + +/* macros for field switch_table_idle_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__SHIFT 0 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__MASK 0x00000003U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field switch_table_t_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__SHIFT 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__MASK 0x0000000cU +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field switch_table_r_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__SHIFT 4 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__MASK 0x00000030U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field switch_table_rx1_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__SHIFT 6 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__MASK 0x000000c0U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field switch_table_rx12_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__SHIFT 8 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__MASK 0x00000300U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field switch_table_b_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__SHIFT 10 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__MASK 0x00000c00U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) +#define SWITCH_TABLE_CHN_B1__TYPE u_int32_t +#define SWITCH_TABLE_CHN_B1__READ 0x00000fffU +#define SWITCH_TABLE_CHN_B1__WRITE 0x00000fffU + +#endif /* __SWITCH_TABLE_CHN_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_switch_table_chn_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_SWITCH_TABLE_CHN_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::fcal_2_b1 */ +#ifndef __FCAL_2_B1_MACRO__ +#define __FCAL_2_B1_MACRO__ + +/* macros for field flc_sw_cap_val_1 */ +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__SHIFT 3 +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__WIDTH 5 +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__MASK 0x000000f8U +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f8U) >> 3) +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000000f8U) +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000000f8U) +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000000f8U))) + +/* macros for field flc_cap_val_status_1 */ +#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__SHIFT 20 +#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__WIDTH 5 +#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__MASK 0x01f00000U +#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define FCAL_2_B1__TYPE u_int32_t +#define FCAL_2_B1__READ 0x01f000f8U +#define FCAL_2_B1__WRITE 0x01f000f8U + +#endif /* __FCAL_2_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_fcal_2_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_FCAL_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b1 */ +#ifndef __DFT_TONE_CTRL_B1_MACRO__ +#define __DFT_TONE_CTRL_B1_MACRO__ + +/* macros for field dft_tone_en_1 */ +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__SHIFT 0 +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__WIDTH 1 +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__MASK 0x00000001U +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dft_tone_amp_sel_1 */ +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__SHIFT 2 +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__WIDTH 2 +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__MASK 0x0000000cU +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field dft_tone_freq_ang_1 */ +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__SHIFT 4 +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__WIDTH 9 +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__MASK 0x00001ff0U +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001ff0U) >> 4) +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001ff0U) | (((u_int32_t)(src) <<\ + 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00001ff0U))) +#define DFT_TONE_CTRL_B1__TYPE u_int32_t +#define DFT_TONE_CTRL_B1__READ 0x00001ffdU +#define DFT_TONE_CTRL_B1__WRITE 0x00001ffdU + +#endif /* __DFT_TONE_CTRL_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_dft_tone_ctrl_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_DFT_TONE_CTRL_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_0 */ +#ifndef __CL_MAP_0_MACRO__ +#define __CL_MAP_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_0__TYPE u_int32_t +#define CL_MAP_0__READ 0xffffffffU +#define CL_MAP_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_cl_map_0_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_CL_MAP_0_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_1 */ +#ifndef __CL_MAP_1_MACRO__ +#define __CL_MAP_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_1__TYPE u_int32_t +#define CL_MAP_1__READ 0xffffffffU +#define CL_MAP_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_cl_map_1_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_CL_MAP_1_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_2 */ +#ifndef __CL_MAP_2_MACRO__ +#define __CL_MAP_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_2__TYPE u_int32_t +#define CL_MAP_2__READ 0xffffffffU +#define CL_MAP_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_cl_map_2_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_CL_MAP_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_3 */ +#ifndef __CL_MAP_3_MACRO__ +#define __CL_MAP_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_3__TYPE u_int32_t +#define CL_MAP_3__READ 0xffffffffU +#define CL_MAP_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_cl_map_3_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_CL_MAP_3_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */ +#ifndef __CL_MAP_PAL_0_MACRO__ +#define __CL_MAP_PAL_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_PAL_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_PAL_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_PAL_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_0__TYPE u_int32_t +#define CL_MAP_PAL_0__READ 0xffffffffU +#define CL_MAP_PAL_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_cl_map_pal_0_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_CL_MAP_PAL_0_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */ +#ifndef __CL_MAP_PAL_1_MACRO__ +#define __CL_MAP_PAL_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_PAL_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_PAL_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_PAL_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_1__TYPE u_int32_t +#define CL_MAP_PAL_1__READ 0xffffffffU +#define CL_MAP_PAL_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_cl_map_pal_1_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_CL_MAP_PAL_1_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */ +#ifndef __CL_MAP_PAL_2_MACRO__ +#define __CL_MAP_PAL_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_PAL_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_PAL_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_PAL_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_2__TYPE u_int32_t +#define CL_MAP_PAL_2__READ 0xffffffffU +#define CL_MAP_PAL_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_cl_map_pal_2_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_CL_MAP_PAL_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */ +#ifndef __CL_MAP_PAL_3_MACRO__ +#define __CL_MAP_PAL_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_PAL_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_PAL_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_PAL_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_3__TYPE u_int32_t +#define CL_MAP_PAL_3__READ 0xffffffffU +#define CL_MAP_PAL_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_cl_map_pal_3_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_CL_MAP_PAL_3_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_tab */ +#ifndef __CL_TAB_MACRO__ +#define __CL_TAB_MACRO__ + +/* macros for field cl_gain_mod */ +#define CL_TAB__CL_GAIN_MOD__SHIFT 0 +#define CL_TAB__CL_GAIN_MOD__WIDTH 5 +#define CL_TAB__CL_GAIN_MOD__MASK 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field carr_lk_dc_add_Q */ +#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT 5 +#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_Q__MASK 0x0000ffe0U +#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ffe0U) >> 5) +#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffe0U) | (((u_int32_t)(src) <<\ + 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x0000ffe0U))) + +/* macros for field carr_lk_dc_add_I */ +#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT 16 +#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_I__MASK 0x07ff0000U +#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) + +/* macros for field bb_gain */ +#define CL_TAB__BB_GAIN__SHIFT 27 +#define CL_TAB__BB_GAIN__WIDTH 4 +#define CL_TAB__BB_GAIN__MASK 0x78000000U +#define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) +#define CL_TAB__TYPE u_int32_t +#define CL_TAB__READ 0x7fffffffU +#define CL_TAB__WRITE 0x7fffffffU + +#endif /* __CL_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_cl_tab_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_CL_TAB_B1__NUM 16 + +/* macros for BlueprintGlobalNameSpace::chan_info_gain_b1 */ +#ifndef __CHAN_INFO_GAIN_B1_MACRO__ +#define __CHAN_INFO_GAIN_B1_MACRO__ + +/* macros for field chan_info_rssi_1 */ +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__SHIFT 0 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__WIDTH 8 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__MASK 0x000000ffU +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field chan_info_rf_gain_1 */ +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__SHIFT 8 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__WIDTH 8 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__MASK 0x0000ff00U +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field chan_info_mb_gain_1 */ +#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__SHIFT 16 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__WIDTH 7 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__MASK 0x007f0000U +#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) + +/* macros for field chan_info_xatten1_sw_1 */ +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__SHIFT 23 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__WIDTH 1 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__MASK 0x00800000U +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field chan_info_xatten2_sw_1 */ +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__SHIFT 24 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__WIDTH 1 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__MASK 0x01000000U +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define CHAN_INFO_GAIN_B1__TYPE u_int32_t +#define CHAN_INFO_GAIN_B1__READ 0x01ffffffU + +#endif /* __CHAN_INFO_GAIN_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_chan_info_gain_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_CHAN_INFO_GAIN_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_4_b1 */ +#ifndef __TPC_4_B1_MACRO__ +#define __TPC_4_B1_MACRO__ + +/* macros for field pd_avg_valid_1 */ +#define TPC_4_B1__PD_AVG_VALID_1__SHIFT 0 +#define TPC_4_B1__PD_AVG_VALID_1__WIDTH 1 +#define TPC_4_B1__PD_AVG_VALID_1__MASK 0x00000001U +#define TPC_4_B1__PD_AVG_VALID_1__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_4_B1__PD_AVG_VALID_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_4_B1__PD_AVG_VALID_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field pd_avg_out_1 */ +#define TPC_4_B1__PD_AVG_OUT_1__SHIFT 1 +#define TPC_4_B1__PD_AVG_OUT_1__WIDTH 8 +#define TPC_4_B1__PD_AVG_OUT_1__MASK 0x000001feU +#define TPC_4_B1__PD_AVG_OUT_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) + +/* macros for field dac_gain_1 */ +#define TPC_4_B1__DAC_GAIN_1__SHIFT 9 +#define TPC_4_B1__DAC_GAIN_1__WIDTH 5 +#define TPC_4_B1__DAC_GAIN_1__MASK 0x00003e00U +#define TPC_4_B1__DAC_GAIN_1__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9) + +/* macros for field tx_gain_setting_1 */ +#define TPC_4_B1__TX_GAIN_SETTING_1__SHIFT 14 +#define TPC_4_B1__TX_GAIN_SETTING_1__WIDTH 6 +#define TPC_4_B1__TX_GAIN_SETTING_1__MASK 0x000fc000U +#define TPC_4_B1__TX_GAIN_SETTING_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) + +/* macros for field rate_sent_1 */ +#define TPC_4_B1__RATE_SENT_1__SHIFT 20 +#define TPC_4_B1__RATE_SENT_1__WIDTH 5 +#define TPC_4_B1__RATE_SENT_1__MASK 0x01f00000U +#define TPC_4_B1__RATE_SENT_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_4_B1__TYPE u_int32_t +#define TPC_4_B1__READ 0x01ffffffU + +#endif /* __TPC_4_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_tpc_4_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TPC_4_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_5_b1 */ +#ifndef __TPC_5_B1_MACRO__ +#define __TPC_5_B1_MACRO__ + +/* macros for field pd_gain_boundary_1_1 */ +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__SHIFT 4 +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__WIDTH 6 +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__MASK 0x000003f0U +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field pd_gain_boundary_2_1 */ +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__SHIFT 10 +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__WIDTH 6 +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__MASK 0x0000fc00U +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fc00U) >> 10) +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0000fc00U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0000fc00U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0000fc00U))) + +/* macros for field pd_gain_boundary_3_1 */ +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__SHIFT 16 +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__WIDTH 6 +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__MASK 0x003f0000U +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field pd_gain_boundary_4_1 */ +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__SHIFT 22 +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__WIDTH 6 +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__MASK 0x0fc00000U +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fc00000U) >> 22) +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x0fc00000U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x0fc00000U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x0fc00000U))) +#define TPC_5_B1__TYPE u_int32_t +#define TPC_5_B1__READ 0x0ffffff0U +#define TPC_5_B1__WRITE 0x0ffffff0U + +#endif /* __TPC_5_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_tpc_5_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TPC_5_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_6_b1 */ +#ifndef __TPC_6_B1_MACRO__ +#define __TPC_6_B1_MACRO__ + +/* macros for field pd_dac_setting_1_1 */ +#define TPC_6_B1__PD_DAC_SETTING_1_1__SHIFT 0 +#define TPC_6_B1__PD_DAC_SETTING_1_1__WIDTH 6 +#define TPC_6_B1__PD_DAC_SETTING_1_1__MASK 0x0000003fU +#define TPC_6_B1__PD_DAC_SETTING_1_1__READ(src) (u_int32_t)(src) & 0x0000003fU +#define TPC_6_B1__PD_DAC_SETTING_1_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define TPC_6_B1__PD_DAC_SETTING_1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TPC_6_B1__PD_DAC_SETTING_1_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field pd_dac_setting_2_1 */ +#define TPC_6_B1__PD_DAC_SETTING_2_1__SHIFT 6 +#define TPC_6_B1__PD_DAC_SETTING_2_1__WIDTH 6 +#define TPC_6_B1__PD_DAC_SETTING_2_1__MASK 0x00000fc0U +#define TPC_6_B1__PD_DAC_SETTING_2_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TPC_6_B1__PD_DAC_SETTING_2_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TPC_6_B1__PD_DAC_SETTING_2_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TPC_6_B1__PD_DAC_SETTING_2_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field pd_dac_setting_3_1 */ +#define TPC_6_B1__PD_DAC_SETTING_3_1__SHIFT 12 +#define TPC_6_B1__PD_DAC_SETTING_3_1__WIDTH 6 +#define TPC_6_B1__PD_DAC_SETTING_3_1__MASK 0x0003f000U +#define TPC_6_B1__PD_DAC_SETTING_3_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define TPC_6_B1__PD_DAC_SETTING_3_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define TPC_6_B1__PD_DAC_SETTING_3_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define TPC_6_B1__PD_DAC_SETTING_3_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field pd_dac_setting_4_1 */ +#define TPC_6_B1__PD_DAC_SETTING_4_1__SHIFT 18 +#define TPC_6_B1__PD_DAC_SETTING_4_1__WIDTH 6 +#define TPC_6_B1__PD_DAC_SETTING_4_1__MASK 0x00fc0000U +#define TPC_6_B1__PD_DAC_SETTING_4_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TPC_6_B1__PD_DAC_SETTING_4_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define TPC_6_B1__PD_DAC_SETTING_4_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define TPC_6_B1__PD_DAC_SETTING_4_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field error_est_mode */ +#define TPC_6_B1__ERROR_EST_MODE__SHIFT 24 +#define TPC_6_B1__ERROR_EST_MODE__WIDTH 2 +#define TPC_6_B1__ERROR_EST_MODE__MASK 0x03000000U +#define TPC_6_B1__ERROR_EST_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x03000000U) >> 24) +#define TPC_6_B1__ERROR_EST_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x03000000U) +#define TPC_6_B1__ERROR_EST_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define TPC_6_B1__ERROR_EST_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field error_est_filter_coeff */ +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__SHIFT 26 +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__WIDTH 3 +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__MASK 0x1c000000U +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) +#define TPC_6_B1__TYPE u_int32_t +#define TPC_6_B1__READ 0x1fffffffU +#define TPC_6_B1__WRITE 0x1fffffffU + +#endif /* __TPC_6_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_tpc_6_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TPC_6_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_11_b1 */ +#ifndef __TPC_11_B1_MACRO__ +#define __TPC_11_B1_MACRO__ + +/* macros for field olpc_gain_delta_1 */ +#define TPC_11_B1__OLPC_GAIN_DELTA_1__SHIFT 16 +#define TPC_11_B1__OLPC_GAIN_DELTA_1__WIDTH 8 +#define TPC_11_B1__OLPC_GAIN_DELTA_1__MASK 0x00ff0000U +#define TPC_11_B1__OLPC_GAIN_DELTA_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TPC_11_B1__OLPC_GAIN_DELTA_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TPC_11_B1__OLPC_GAIN_DELTA_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TPC_11_B1__OLPC_GAIN_DELTA_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field olpc_gain_delta_1_pal_on */ +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__SHIFT 24 +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__WIDTH 8 +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__MASK 0xff000000U +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TPC_11_B1__TYPE u_int32_t +#define TPC_11_B1__READ 0xffff0000U +#define TPC_11_B1__WRITE 0xffff0000U + +#endif /* __TPC_11_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_tpc_11_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TPC_11_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pdadc_tab */ +#ifndef __PDADC_TAB_MACRO__ +#define __PDADC_TAB_MACRO__ + +/* macros for field tab_entry */ +#define PDADC_TAB__TAB_ENTRY__SHIFT 0 +#define PDADC_TAB__TAB_ENTRY__WIDTH 32 +#define PDADC_TAB__TAB_ENTRY__MASK 0xffffffffU +#define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define PDADC_TAB__TYPE u_int32_t +#define PDADC_TAB__WRITE 0x00000000U + +#endif /* __PDADC_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_pdadc_tab_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_PDADC_TAB_B1__NUM 32 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b1 */ +#ifndef __TXIQ_CORR_COEFF_01_B1_MACRO__ +#define __TXIQ_CORR_COEFF_01_B1_MACRO__ + +/* macros for field iqc_coeff_table_0_1 */ +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__SHIFT 0 +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_1_1 */ +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__SHIFT 14 +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_01_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_01_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_01_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_01_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_txiq_corr_coeff_01_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_01_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b1 */ +#ifndef __TXIQ_CORR_COEFF_23_B1_MACRO__ +#define __TXIQ_CORR_COEFF_23_B1_MACRO__ + +/* macros for field iqc_coeff_table_2_1 */ +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__SHIFT 0 +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_3_1 */ +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__SHIFT 14 +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_23_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_23_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_23_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_23_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_txiq_corr_coeff_23_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_23_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b1 */ +#ifndef __TXIQ_CORR_COEFF_45_B1_MACRO__ +#define __TXIQ_CORR_COEFF_45_B1_MACRO__ + +/* macros for field iqc_coeff_table_4_1 */ +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__SHIFT 0 +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_5_1 */ +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__SHIFT 14 +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_45_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_45_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_45_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_45_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_txiq_corr_coeff_45_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_45_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b1 */ +#ifndef __TXIQ_CORR_COEFF_67_B1_MACRO__ +#define __TXIQ_CORR_COEFF_67_B1_MACRO__ + +/* macros for field iqc_coeff_table_6_1 */ +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__SHIFT 0 +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_7_1 */ +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__SHIFT 14 +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_67_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_67_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_67_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_67_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_txiq_corr_coeff_67_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_67_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b1 */ +#ifndef __TXIQ_CORR_COEFF_89_B1_MACRO__ +#define __TXIQ_CORR_COEFF_89_B1_MACRO__ + +/* macros for field iqc_coeff_table_8_1 */ +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__SHIFT 0 +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_9_1 */ +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__SHIFT 14 +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_89_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_89_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_89_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_89_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_txiq_corr_coeff_89_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_89_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b1 */ +#ifndef __TXIQ_CORR_COEFF_AB_B1_MACRO__ +#define __TXIQ_CORR_COEFF_AB_B1_MACRO__ + +/* macros for field iqc_coeff_table_a_1 */ +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__SHIFT 0 +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_b_1 */ +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__SHIFT 14 +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_AB_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_AB_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_AB_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_AB_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_txiq_corr_coeff_ab_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b1 */ +#ifndef __TXIQ_CORR_COEFF_CD_B1_MACRO__ +#define __TXIQ_CORR_COEFF_CD_B1_MACRO__ + +/* macros for field iqc_coeff_table_c_1 */ +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__SHIFT 0 +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_d_1 */ +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__SHIFT 14 +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_CD_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_CD_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_CD_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_CD_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_txiq_corr_coeff_cd_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b1 */ +#ifndef __TXIQ_CORR_COEFF_EF_B1_MACRO__ +#define __TXIQ_CORR_COEFF_EF_B1_MACRO__ + +/* macros for field iqc_coeff_table_e_1 */ +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__SHIFT 0 +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_f_1 */ +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__SHIFT 14 +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_EF_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_EF_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_EF_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_EF_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_txiq_corr_coeff_ef_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_status_b1 */ +#ifndef __TXIQCAL_STATUS_B1_MACRO__ +#define __TXIQCAL_STATUS_B1_MACRO__ + +/* macros for field txiqcal_failed_1 */ +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__SHIFT 0 +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__WIDTH 1 +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__MASK 0x00000001U +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field calibrated_gains_1 */ +#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__SHIFT 1 +#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__WIDTH 5 +#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__MASK 0x0000003eU +#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) + +/* macros for field tone_gain_used_1 */ +#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__SHIFT 6 +#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__WIDTH 6 +#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__MASK 0x00000fc0U +#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) + +/* macros for field rx_gain_used_1 */ +#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__SHIFT 12 +#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__WIDTH 6 +#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__MASK 0x0003f000U +#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) + +/* macros for field last_meas_addr_1 */ +#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__SHIFT 18 +#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__WIDTH 6 +#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__MASK 0x00fc0000U +#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TXIQCAL_STATUS_B1__TYPE u_int32_t +#define TXIQCAL_STATUS_B1__READ 0x00ffffffU + +#endif /* __TXIQCAL_STATUS_B1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_txiqcal_status_b1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_TXIQCAL_STATUS_B1__NUM 1 + +/* macros for bb_reg_block.bb_sm1_reg_map.BB_dummy_sm1 */ +#define INST_BB_REG_BLOCK__BB_SM1_REG_MAP__BB_DUMMY_SM1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_dummy_DONOTACCESS2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_DUMMY_DONOTACCESS2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b2 */ +#ifndef __EXT_CHAN_PWR_THR_2_B2_MACRO__ +#define __EXT_CHAN_PWR_THR_2_B2_MACRO__ + +/* macros for field cf_maxCCApwr_ext_2 */ +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__SHIFT 0 +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__MASK 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field minCCApwr_ext_2 */ +#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__SHIFT 16 +#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__MASK 0x01ff0000U +#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01ff0000U) >> 16) +#define EXT_CHAN_PWR_THR_2_B2__TYPE u_int32_t +#define EXT_CHAN_PWR_THR_2_B2__READ 0x01ff01ffU +#define EXT_CHAN_PWR_THR_2_B2__WRITE 0x01ff01ffU + +#endif /* __EXT_CHAN_PWR_THR_2_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_ext_chan_pwr_thr_2_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_report_b2 */ +#ifndef __SPUR_REPORT_B2_MACRO__ +#define __SPUR_REPORT_B2_MACRO__ + +/* macros for field spur_est_i_2 */ +#define SPUR_REPORT_B2__SPUR_EST_I_2__SHIFT 0 +#define SPUR_REPORT_B2__SPUR_EST_I_2__WIDTH 8 +#define SPUR_REPORT_B2__SPUR_EST_I_2__MASK 0x000000ffU +#define SPUR_REPORT_B2__SPUR_EST_I_2__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field spur_est_q_2 */ +#define SPUR_REPORT_B2__SPUR_EST_Q_2__SHIFT 8 +#define SPUR_REPORT_B2__SPUR_EST_Q_2__WIDTH 8 +#define SPUR_REPORT_B2__SPUR_EST_Q_2__MASK 0x0000ff00U +#define SPUR_REPORT_B2__SPUR_EST_Q_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field power_with_spur_removed_2 */ +#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__SHIFT 16 +#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__WIDTH 16 +#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__MASK 0xffff0000U +#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define SPUR_REPORT_B2__TYPE u_int32_t +#define SPUR_REPORT_B2__READ 0xffffffffU + +#endif /* __SPUR_REPORT_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_spur_report_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_SPUR_REPORT_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b2 */ +#ifndef __IQ_ADC_MEAS_0_B2_MACRO__ +#define __IQ_ADC_MEAS_0_B2_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_0_2 */ +#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__SHIFT 0 +#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__WIDTH 32 +#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__MASK 0xffffffffU +#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_0_B2__TYPE u_int32_t +#define IQ_ADC_MEAS_0_B2__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_0_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_iq_adc_meas_0_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_0_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b2 */ +#ifndef __IQ_ADC_MEAS_1_B2_MACRO__ +#define __IQ_ADC_MEAS_1_B2_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_1_2 */ +#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__SHIFT 0 +#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__WIDTH 32 +#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__MASK 0xffffffffU +#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_1_B2__TYPE u_int32_t +#define IQ_ADC_MEAS_1_B2__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_1_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_iq_adc_meas_1_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_1_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b2 */ +#ifndef __IQ_ADC_MEAS_2_B2_MACRO__ +#define __IQ_ADC_MEAS_2_B2_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_2_2 */ +#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__SHIFT 0 +#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__WIDTH 32 +#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__MASK 0xffffffffU +#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_2_B2__TYPE u_int32_t +#define IQ_ADC_MEAS_2_B2__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_2_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_iq_adc_meas_2_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b2 */ +#ifndef __IQ_ADC_MEAS_3_B2_MACRO__ +#define __IQ_ADC_MEAS_3_B2_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_3_2 */ +#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__SHIFT 0 +#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__WIDTH 32 +#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__MASK 0xffffffffU +#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_3_B2__TYPE u_int32_t +#define IQ_ADC_MEAS_3_B2__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_3_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_iq_adc_meas_3_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_3_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b2 */ +#ifndef __TX_PHASE_RAMP_B2_MACRO__ +#define __TX_PHASE_RAMP_B2_MACRO__ + +/* macros for field cf_phase_ramp_enable_2 */ +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__SHIFT 0 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__WIDTH 1 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__MASK 0x00000001U +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_phase_ramp_bias_2 */ +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__SHIFT 1 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__WIDTH 6 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__MASK 0x0000007eU +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000007eU) >> 1) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000007eU))) + +/* macros for field cf_phase_ramp_init_2 */ +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__SHIFT 7 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__WIDTH 10 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__MASK 0x0001ff80U +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001ff80U) >> 7) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ff80U) | (((u_int32_t)(src) <<\ + 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x0001ff80U))) + +/* macros for field cf_phase_ramp_alpha_2 */ +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__SHIFT 17 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__WIDTH 8 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__MASK 0x01fe0000U +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fe0000U) >> 17) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x01fe0000U))) +#define TX_PHASE_RAMP_B2__TYPE u_int32_t +#define TX_PHASE_RAMP_B2__READ 0x01ffffffU +#define TX_PHASE_RAMP_B2__WRITE 0x01ffffffU + +#endif /* __TX_PHASE_RAMP_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_tx_phase_ramp_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_TX_PHASE_RAMP_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b2 */ +#ifndef __ADC_GAIN_DC_CORR_B2_MACRO__ +#define __ADC_GAIN_DC_CORR_B2_MACRO__ + +/* macros for field adc_gain_corr_q_coeff_2 */ +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__SHIFT 0 +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__WIDTH 6 +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__MASK 0x0000003fU +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field adc_gain_corr_i_coeff_2 */ +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__SHIFT 6 +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__WIDTH 6 +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__MASK 0x00000fc0U +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field adc_dc_corr_q_coeff_2 */ +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__SHIFT 12 +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__WIDTH 9 +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__MASK 0x001ff000U +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x001ff000U) >> 12) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x001ff000U))) + +/* macros for field adc_dc_corr_i_coeff_2 */ +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__SHIFT 21 +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__WIDTH 9 +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__MASK 0x3fe00000U +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x3fe00000U) >> 21) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x3fe00000U))) +#define ADC_GAIN_DC_CORR_B2__TYPE u_int32_t +#define ADC_GAIN_DC_CORR_B2__READ 0x3fffffffU +#define ADC_GAIN_DC_CORR_B2__WRITE 0x3fffffffU + +#endif /* __ADC_GAIN_DC_CORR_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_adc_gain_dc_corr_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_ADC_GAIN_DC_CORR_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b2 */ +#ifndef __RX_IQ_CORR_B2_MACRO__ +#define __RX_IQ_CORR_B2_MACRO__ + +/* macros for field rx_iqcorr_q_q_coff_2 */ +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__SHIFT 0 +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__WIDTH 7 +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__MASK 0x0000007fU +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field rx_iqcorr_q_i_coff_2 */ +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__SHIFT 7 +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__WIDTH 7 +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__MASK 0x00003f80U +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f80U) >> 7) +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00003f80U) +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00003f80U) +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00003f80U))) + +/* macros for field loopback_iqcorr_q_q_coff_2 */ +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__SHIFT 15 +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__WIDTH 7 +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__MASK 0x003f8000U +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f8000U) >> 15) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x003f8000U) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x003f8000U) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x003f8000U))) + +/* macros for field loopback_iqcorr_q_i_coff_2 */ +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__SHIFT 22 +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__WIDTH 7 +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__MASK 0x1fc00000U +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x1fc00000U) >> 22) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x1fc00000U) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x1fc00000U) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x1fc00000U))) +#define RX_IQ_CORR_B2__TYPE u_int32_t +#define RX_IQ_CORR_B2__READ 0x1fffbfffU +#define RX_IQ_CORR_B2__WRITE 0x1fffbfffU + +#endif /* __RX_IQ_CORR_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_rx_iq_corr_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_RX_IQ_CORR_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b2 */ +#ifndef __PAPRD_CTRL0_B2_MACRO__ +#define __PAPRD_CTRL0_B2_MACRO__ + +/* macros for field paprd_enable_2 */ +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__SHIFT 0 +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__WIDTH 1 +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__MASK 0x00000001U +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_use_single_table_2 */ +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__SHIFT 1 +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__WIDTH 1 +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__MASK 0x00000002U +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_valid_gain_2 */ +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__SHIFT 2 +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__WIDTH 25 +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__MASK 0x07fffffcU +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fffffcU) >> 2) +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fffffcU) | (((u_int32_t)(src) <<\ + 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x07fffffcU))) + +/* macros for field paprd_mag_thrsh_2 */ +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__SHIFT 27 +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__WIDTH 5 +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__MASK 0xf8000000U +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define PAPRD_CTRL0_B2__TYPE u_int32_t +#define PAPRD_CTRL0_B2__READ 0xffffffffU +#define PAPRD_CTRL0_B2__WRITE 0xffffffffU + +#endif /* __PAPRD_CTRL0_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_paprd_ctrl0_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PAPRD_CTRL0_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b2 */ +#ifndef __PAPRD_CTRL1_B2_MACRO__ +#define __PAPRD_CTRL1_B2_MACRO__ + +/* macros for field paprd_adaptive_scaling_enable_2 */ +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__SHIFT 0 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__WIDTH 1 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__MASK 0x00000001U +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_am2am_enable_2 */ +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__SHIFT 1 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__WIDTH 1 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__MASK 0x00000002U +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_adaptive_am2pm_enable_2 */ +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__SHIFT 2 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__WIDTH 1 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__MASK 0x00000004U +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field paprd_power_at_am2am_cal_2 */ +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__SHIFT 3 +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__WIDTH 6 +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__MASK 0x000001f8U +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001f8U) >> 3) +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000001f8U) +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000001f8U) +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000001f8U))) + +/* macros for field pa_gain_scale_factor_2 */ +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__SHIFT 9 +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__WIDTH 8 +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__MASK 0x0001fe00U +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fe00U) >> 9) +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((u_int32_t)(src) <<\ + 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x0001fe00U))) + +/* macros for field paprd_mag_scale_factor_2 */ +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__SHIFT 17 +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__WIDTH 10 +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__MASK 0x07fe0000U +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fe0000U) >> 17) +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x07fe0000U))) + +/* macros for field paprd_trainer_iandq_sel_2 */ +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__SHIFT 27 +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__WIDTH 1 +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__MASK 0x08000000U +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) +#define PAPRD_CTRL1_B2__TYPE u_int32_t +#define PAPRD_CTRL1_B2__READ 0x0fffffffU +#define PAPRD_CTRL1_B2__WRITE 0x0fffffffU + +#endif /* __PAPRD_CTRL1_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_paprd_ctrl1_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PAPRD_CTRL1_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain123_b2 */ +#ifndef __PA_GAIN123_B2_MACRO__ +#define __PA_GAIN123_B2_MACRO__ + +/* macros for field pa_gain1_2 */ +#define PA_GAIN123_B2__PA_GAIN1_2__SHIFT 0 +#define PA_GAIN123_B2__PA_GAIN1_2__WIDTH 10 +#define PA_GAIN123_B2__PA_GAIN1_2__MASK 0x000003ffU +#define PA_GAIN123_B2__PA_GAIN1_2__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN123_B2__PA_GAIN1_2__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN123_B2__PA_GAIN1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN123_B2__PA_GAIN1_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain2_2 */ +#define PA_GAIN123_B2__PA_GAIN2_2__SHIFT 10 +#define PA_GAIN123_B2__PA_GAIN2_2__WIDTH 10 +#define PA_GAIN123_B2__PA_GAIN2_2__MASK 0x000ffc00U +#define PA_GAIN123_B2__PA_GAIN2_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN123_B2__PA_GAIN2_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN123_B2__PA_GAIN2_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN123_B2__PA_GAIN2_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field pa_gain3_2 */ +#define PA_GAIN123_B2__PA_GAIN3_2__SHIFT 20 +#define PA_GAIN123_B2__PA_GAIN3_2__WIDTH 10 +#define PA_GAIN123_B2__PA_GAIN3_2__MASK 0x3ff00000U +#define PA_GAIN123_B2__PA_GAIN3_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ff00000U) >> 20) +#define PA_GAIN123_B2__PA_GAIN3_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x3ff00000U) +#define PA_GAIN123_B2__PA_GAIN3_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x3ff00000U) +#define PA_GAIN123_B2__PA_GAIN3_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define PA_GAIN123_B2__TYPE u_int32_t +#define PA_GAIN123_B2__READ 0x3fffffffU +#define PA_GAIN123_B2__WRITE 0x3fffffffU + +#endif /* __PA_GAIN123_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_pa_gain123_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PA_GAIN123_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain45_b2 */ +#ifndef __PA_GAIN45_B2_MACRO__ +#define __PA_GAIN45_B2_MACRO__ + +/* macros for field pa_gain4_2 */ +#define PA_GAIN45_B2__PA_GAIN4_2__SHIFT 0 +#define PA_GAIN45_B2__PA_GAIN4_2__WIDTH 10 +#define PA_GAIN45_B2__PA_GAIN4_2__MASK 0x000003ffU +#define PA_GAIN45_B2__PA_GAIN4_2__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN45_B2__PA_GAIN4_2__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN45_B2__PA_GAIN4_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN45_B2__PA_GAIN4_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain5_2 */ +#define PA_GAIN45_B2__PA_GAIN5_2__SHIFT 10 +#define PA_GAIN45_B2__PA_GAIN5_2__WIDTH 10 +#define PA_GAIN45_B2__PA_GAIN5_2__MASK 0x000ffc00U +#define PA_GAIN45_B2__PA_GAIN5_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN45_B2__PA_GAIN5_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN45_B2__PA_GAIN5_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN45_B2__PA_GAIN5_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field paprd_adaptive_table_valid_2 */ +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__SHIFT 20 +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__WIDTH 5 +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__MASK 0x01f00000U +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) +#define PA_GAIN45_B2__TYPE u_int32_t +#define PA_GAIN45_B2__READ 0x01ffffffU +#define PA_GAIN45_B2__WRITE 0x01ffffffU + +#endif /* __PA_GAIN45_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_pa_gain45_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PA_GAIN45_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_0_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_0_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_0_2 */ +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_0_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_0_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_0_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_paprd_pre_post_scale_0_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_1_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_1_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_1_2 */ +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_1_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_1_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_1_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_paprd_pre_post_scale_1_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_2_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_2_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_2_2 */ +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_2_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_2_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_2_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_paprd_pre_post_scale_2_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_3_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_3_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_3_2 */ +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_3_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_3_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_3_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_paprd_pre_post_scale_3_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_4_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_4_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_4_2 */ +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_4_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_4_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_4_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_paprd_pre_post_scale_4_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_5_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_5_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_5_2 */ +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_5_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_5_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_5_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_paprd_pre_post_scale_5_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_6_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_6_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_6_2 */ +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_6_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_6_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_6_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_paprd_pre_post_scale_6_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_7_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_7_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_7_2 */ +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_7_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_7_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_7_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_paprd_pre_post_scale_7_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */ +#ifndef __PAPRD_MEM_TAB_MACRO__ +#define __PAPRD_MEM_TAB_MACRO__ + +/* macros for field paprd_mem */ +#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT 0 +#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH 22 +#define PAPRD_MEM_TAB__PAPRD_MEM__MASK 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((u_int32_t)(src) &\ + 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x003fffffU))) +#define PAPRD_MEM_TAB__TYPE u_int32_t +#define PAPRD_MEM_TAB__READ 0x003fffffU +#define PAPRD_MEM_TAB__WRITE 0x003fffffU + +#endif /* __PAPRD_MEM_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_paprd_mem_tab_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_PAPRD_MEM_TAB_B2__NUM 120 + +/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */ +#ifndef __CHAN_INFO_CHAN_TAB_MACRO__ +#define __CHAN_INFO_CHAN_TAB_MACRO__ + +/* macros for field chaninfo_word */ +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT 0 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH 32 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK 0xffffffffU +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define CHAN_INFO_CHAN_TAB__TYPE u_int32_t +#define CHAN_INFO_CHAN_TAB__READ 0xffffffffU + +#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn2_reg_map.BB_chan_info_chan_tab_b2 */ +#define INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B2__NUM 60 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc2_reg_map.BB_dummy_DONOTACCESS4 */ +#define INST_BB_REG_BLOCK__BB_AGC2_REG_MAP__BB_DUMMY_DONOTACCESS4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b2 */ +#ifndef __GAIN_FORCE_MAX_GAINS_B2_MACRO__ +#define __GAIN_FORCE_MAX_GAINS_B2_MACRO__ + +/* macros for field rf_gain_f_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__SHIFT 0 +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__MASK 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field mb_gain_f_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__SHIFT 8 +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__MASK 0x0000ff00U +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field xatten1_sw_f_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__SHIFT 16 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__MASK 0x00010000U +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field xatten2_sw_f_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__SHIFT 17 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__MASK 0x00020000U +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field xatten1_hyst_margin_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__SHIFT 18 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__MASK 0x01fc0000U +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fc0000U) >> 18) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x01fc0000U))) + +/* macros for field xatten2_hyst_margin_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__SHIFT 25 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__MASK 0xfe000000U +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0xfe000000U) >> 25) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfe000000U) | (((u_int32_t)(src) <<\ + 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0xfe000000U))) +#define GAIN_FORCE_MAX_GAINS_B2__TYPE u_int32_t +#define GAIN_FORCE_MAX_GAINS_B2__READ 0xffffffffU +#define GAIN_FORCE_MAX_GAINS_B2__WRITE 0xffffffffU + +#endif /* __GAIN_FORCE_MAX_GAINS_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc2_reg_map.BB_gain_force_max_gains_b2 */ +#define INST_BB_REG_BLOCK__BB_AGC2_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b2 */ +#ifndef __EXT_ATTEN_SWITCH_CTL_B2_MACRO__ +#define __EXT_ATTEN_SWITCH_CTL_B2_MACRO__ + +/* macros for field xatten1_db_2 */ +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__SHIFT 0 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__MASK 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field xatten2_db_2 */ +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__SHIFT 6 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__MASK 0x00000fc0U +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field xatten1_margin_2 */ +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__SHIFT 12 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__MASK 0x0001f000U +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field xatten2_margin_2 */ +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__SHIFT 17 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__MASK 0x003e0000U +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field xlna_gain_db_2 */ +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__SHIFT 22 +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__MASK 0x07c00000U +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) +#define EXT_ATTEN_SWITCH_CTL_B2__TYPE u_int32_t +#define EXT_ATTEN_SWITCH_CTL_B2__READ 0x07ffffffU +#define EXT_ATTEN_SWITCH_CTL_B2__WRITE 0x07ffffffU + +#endif /* __EXT_ATTEN_SWITCH_CTL_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc2_reg_map.BB_ext_atten_switch_ctl_b2 */ +#define INST_BB_REG_BLOCK__BB_AGC2_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_b2 */ +#ifndef __CCA_B2_MACRO__ +#define __CCA_B2_MACRO__ + +/* macros for field cf_maxCCApwr_2 */ +#define CCA_B2__CF_MAXCCAPWR_2__SHIFT 0 +#define CCA_B2__CF_MAXCCAPWR_2__WIDTH 9 +#define CCA_B2__CF_MAXCCAPWR_2__MASK 0x000001ffU +#define CCA_B2__CF_MAXCCAPWR_2__READ(src) (u_int32_t)(src) & 0x000001ffU +#define CCA_B2__CF_MAXCCAPWR_2__WRITE(src) ((u_int32_t)(src) & 0x000001ffU) +#define CCA_B2__CF_MAXCCAPWR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_B2__CF_MAXCCAPWR_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field minCCApwr_2 */ +#define CCA_B2__MINCCAPWR_2__SHIFT 20 +#define CCA_B2__MINCCAPWR_2__WIDTH 9 +#define CCA_B2__MINCCAPWR_2__MASK 0x1ff00000U +#define CCA_B2__MINCCAPWR_2__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20) +#define CCA_B2__TYPE u_int32_t +#define CCA_B2__READ 0x1ff001ffU +#define CCA_B2__WRITE 0x1ff001ffU + +#endif /* __CCA_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc2_reg_map.BB_cca_b2 */ +#define INST_BB_REG_BLOCK__BB_AGC2_REG_MAP__BB_CCA_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b2 */ +#ifndef __CCA_CTRL_2_B2_MACRO__ +#define __CCA_CTRL_2_B2_MACRO__ + +/* macros for field minCCApwr_thr_2 */ +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__SHIFT 0 +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__WIDTH 9 +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__MASK 0x000001ffU +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field NF_gain_comp_2 */ +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__SHIFT 10 +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__WIDTH 8 +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__MASK 0x0003fc00U +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fc00U) >> 10) +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0003fc00U) +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0003fc00U) +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0003fc00U))) +#define CCA_CTRL_2_B2__TYPE u_int32_t +#define CCA_CTRL_2_B2__READ 0x0003fdffU +#define CCA_CTRL_2_B2__WRITE 0x0003fdffU + +#endif /* __CCA_CTRL_2_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc2_reg_map.BB_cca_ctrl_2_b2 */ +#define INST_BB_REG_BLOCK__BB_AGC2_REG_MAP__BB_CCA_CTRL_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rssi_b2 */ +#ifndef __RSSI_B2_MACRO__ +#define __RSSI_B2_MACRO__ + +/* macros for field rssi_2 */ +#define RSSI_B2__RSSI_2__SHIFT 0 +#define RSSI_B2__RSSI_2__WIDTH 8 +#define RSSI_B2__RSSI_2__MASK 0x000000ffU +#define RSSI_B2__RSSI_2__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field rssi_ext_2 */ +#define RSSI_B2__RSSI_EXT_2__SHIFT 8 +#define RSSI_B2__RSSI_EXT_2__WIDTH 8 +#define RSSI_B2__RSSI_EXT_2__MASK 0x0000ff00U +#define RSSI_B2__RSSI_EXT_2__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define RSSI_B2__TYPE u_int32_t +#define RSSI_B2__READ 0x0000ffffU + +#endif /* __RSSI_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc2_reg_map.BB_rssi_b2 */ +#define INST_BB_REG_BLOCK__BB_AGC2_REG_MAP__BB_RSSI_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b2 */ +#ifndef __AGC_DIG_DC_STATUS_I_B2_MACRO__ +#define __AGC_DIG_DC_STATUS_I_B2_MACRO__ + +/* macros for field dig_dc_C1_res_i_2 */ +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__SHIFT 0 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_i_2 */ +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__SHIFT 9 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_i_2 */ +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__SHIFT 18 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_I_B2__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_I_B2__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_I_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc2_reg_map.BB_agc_dig_dc_status_i_b2 */ +#define INST_BB_REG_BLOCK__BB_AGC2_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b2 */ +#ifndef __AGC_DIG_DC_STATUS_Q_B2_MACRO__ +#define __AGC_DIG_DC_STATUS_Q_B2_MACRO__ + +/* macros for field dig_dc_C1_res_q_2 */ +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__SHIFT 0 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_q_2 */ +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__SHIFT 9 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_q_2 */ +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__SHIFT 18 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_Q_B2__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_Q_B2__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_Q_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc2_reg_map.BB_agc_dig_dc_status_q_b2 */ +#define INST_BB_REG_BLOCK__BB_AGC2_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_dummy_DONOTACCESS6 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_DUMMY_DONOTACCESS6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::switch_table_chn_b2 */ +#ifndef __SWITCH_TABLE_CHN_B2_MACRO__ +#define __SWITCH_TABLE_CHN_B2_MACRO__ + +/* macros for field switch_table_idle_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__SHIFT 0 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__MASK 0x00000003U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field switch_table_t_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__SHIFT 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__MASK 0x0000000cU +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field switch_table_r_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__SHIFT 4 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__MASK 0x00000030U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field switch_table_rx1_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__SHIFT 6 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__MASK 0x000000c0U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field switch_table_rx12_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__SHIFT 8 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__MASK 0x00000300U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field switch_table_b_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__SHIFT 10 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__MASK 0x00000c00U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) +#define SWITCH_TABLE_CHN_B2__TYPE u_int32_t +#define SWITCH_TABLE_CHN_B2__READ 0x00000fffU +#define SWITCH_TABLE_CHN_B2__WRITE 0x00000fffU + +#endif /* __SWITCH_TABLE_CHN_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_switch_table_chn_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_SWITCH_TABLE_CHN_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::fcal_2_b2 */ +#ifndef __FCAL_2_B2_MACRO__ +#define __FCAL_2_B2_MACRO__ + +/* macros for field flc_sw_cap_val_2 */ +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__SHIFT 3 +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__WIDTH 5 +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__MASK 0x000000f8U +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f8U) >> 3) +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000000f8U) +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000000f8U) +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000000f8U))) + +/* macros for field flc_cap_val_status_2 */ +#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__SHIFT 20 +#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__WIDTH 5 +#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__MASK 0x01f00000U +#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define FCAL_2_B2__TYPE u_int32_t +#define FCAL_2_B2__READ 0x01f000f8U +#define FCAL_2_B2__WRITE 0x01f000f8U + +#endif /* __FCAL_2_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_fcal_2_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_FCAL_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b2 */ +#ifndef __DFT_TONE_CTRL_B2_MACRO__ +#define __DFT_TONE_CTRL_B2_MACRO__ + +/* macros for field dft_tone_en_2 */ +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__SHIFT 0 +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__WIDTH 1 +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__MASK 0x00000001U +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dft_tone_amp_sel_2 */ +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__SHIFT 2 +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__WIDTH 2 +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__MASK 0x0000000cU +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field dft_tone_freq_ang_2 */ +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__SHIFT 4 +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__WIDTH 9 +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__MASK 0x00001ff0U +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001ff0U) >> 4) +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001ff0U) | (((u_int32_t)(src) <<\ + 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00001ff0U))) +#define DFT_TONE_CTRL_B2__TYPE u_int32_t +#define DFT_TONE_CTRL_B2__READ 0x00001ffdU +#define DFT_TONE_CTRL_B2__WRITE 0x00001ffdU + +#endif /* __DFT_TONE_CTRL_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_dft_tone_ctrl_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_DFT_TONE_CTRL_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_0 */ +#ifndef __CL_MAP_0_MACRO__ +#define __CL_MAP_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_0__TYPE u_int32_t +#define CL_MAP_0__READ 0xffffffffU +#define CL_MAP_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_cl_map_0_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_CL_MAP_0_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_1 */ +#ifndef __CL_MAP_1_MACRO__ +#define __CL_MAP_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_1__TYPE u_int32_t +#define CL_MAP_1__READ 0xffffffffU +#define CL_MAP_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_cl_map_1_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_CL_MAP_1_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_2 */ +#ifndef __CL_MAP_2_MACRO__ +#define __CL_MAP_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_2__TYPE u_int32_t +#define CL_MAP_2__READ 0xffffffffU +#define CL_MAP_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_cl_map_2_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_CL_MAP_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_3 */ +#ifndef __CL_MAP_3_MACRO__ +#define __CL_MAP_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_3__TYPE u_int32_t +#define CL_MAP_3__READ 0xffffffffU +#define CL_MAP_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_cl_map_3_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_CL_MAP_3_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */ +#ifndef __CL_MAP_PAL_0_MACRO__ +#define __CL_MAP_PAL_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_PAL_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_PAL_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_PAL_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_0__TYPE u_int32_t +#define CL_MAP_PAL_0__READ 0xffffffffU +#define CL_MAP_PAL_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_0_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_cl_map_pal_0_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_CL_MAP_PAL_0_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */ +#ifndef __CL_MAP_PAL_1_MACRO__ +#define __CL_MAP_PAL_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_PAL_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_PAL_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_PAL_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_1__TYPE u_int32_t +#define CL_MAP_PAL_1__READ 0xffffffffU +#define CL_MAP_PAL_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_cl_map_pal_1_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_CL_MAP_PAL_1_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */ +#ifndef __CL_MAP_PAL_2_MACRO__ +#define __CL_MAP_PAL_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_PAL_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_PAL_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_PAL_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_2__TYPE u_int32_t +#define CL_MAP_PAL_2__READ 0xffffffffU +#define CL_MAP_PAL_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_cl_map_pal_2_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_CL_MAP_PAL_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */ +#ifndef __CL_MAP_PAL_3_MACRO__ +#define __CL_MAP_PAL_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_PAL_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_PAL_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_PAL_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_3__TYPE u_int32_t +#define CL_MAP_PAL_3__READ 0xffffffffU +#define CL_MAP_PAL_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_cl_map_pal_3_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_CL_MAP_PAL_3_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_tab */ +#ifndef __CL_TAB_MACRO__ +#define __CL_TAB_MACRO__ + +/* macros for field cl_gain_mod */ +#define CL_TAB__CL_GAIN_MOD__SHIFT 0 +#define CL_TAB__CL_GAIN_MOD__WIDTH 5 +#define CL_TAB__CL_GAIN_MOD__MASK 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field carr_lk_dc_add_Q */ +#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT 5 +#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_Q__MASK 0x0000ffe0U +#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ffe0U) >> 5) +#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffe0U) | (((u_int32_t)(src) <<\ + 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x0000ffe0U))) + +/* macros for field carr_lk_dc_add_I */ +#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT 16 +#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_I__MASK 0x07ff0000U +#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) + +/* macros for field bb_gain */ +#define CL_TAB__BB_GAIN__SHIFT 27 +#define CL_TAB__BB_GAIN__WIDTH 4 +#define CL_TAB__BB_GAIN__MASK 0x78000000U +#define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) +#define CL_TAB__TYPE u_int32_t +#define CL_TAB__READ 0x7fffffffU +#define CL_TAB__WRITE 0x7fffffffU + +#endif /* __CL_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_cl_tab_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_CL_TAB_B2__NUM 16 + +/* macros for BlueprintGlobalNameSpace::chan_info_gain_b2 */ +#ifndef __CHAN_INFO_GAIN_B2_MACRO__ +#define __CHAN_INFO_GAIN_B2_MACRO__ + +/* macros for field chan_info_rssi_2 */ +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__SHIFT 0 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__WIDTH 8 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__MASK 0x000000ffU +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field chan_info_rf_gain_2 */ +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__SHIFT 8 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__WIDTH 8 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__MASK 0x0000ff00U +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field chan_info_mb_gain_2 */ +#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__SHIFT 16 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__WIDTH 7 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__MASK 0x007f0000U +#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) + +/* macros for field chan_info_xatten1_sw_2 */ +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__SHIFT 23 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__WIDTH 1 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__MASK 0x00800000U +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field chan_info_xatten2_sw_2 */ +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__SHIFT 24 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__WIDTH 1 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__MASK 0x01000000U +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define CHAN_INFO_GAIN_B2__TYPE u_int32_t +#define CHAN_INFO_GAIN_B2__READ 0x01ffffffU + +#endif /* __CHAN_INFO_GAIN_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_chan_info_gain_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_CHAN_INFO_GAIN_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_4_b2 */ +#ifndef __TPC_4_B2_MACRO__ +#define __TPC_4_B2_MACRO__ + +/* macros for field pd_avg_valid_2 */ +#define TPC_4_B2__PD_AVG_VALID_2__SHIFT 0 +#define TPC_4_B2__PD_AVG_VALID_2__WIDTH 1 +#define TPC_4_B2__PD_AVG_VALID_2__MASK 0x00000001U +#define TPC_4_B2__PD_AVG_VALID_2__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_4_B2__PD_AVG_VALID_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_4_B2__PD_AVG_VALID_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field pd_avg_out_2 */ +#define TPC_4_B2__PD_AVG_OUT_2__SHIFT 1 +#define TPC_4_B2__PD_AVG_OUT_2__WIDTH 8 +#define TPC_4_B2__PD_AVG_OUT_2__MASK 0x000001feU +#define TPC_4_B2__PD_AVG_OUT_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) + +/* macros for field dac_gain_2 */ +#define TPC_4_B2__DAC_GAIN_2__SHIFT 9 +#define TPC_4_B2__DAC_GAIN_2__WIDTH 5 +#define TPC_4_B2__DAC_GAIN_2__MASK 0x00003e00U +#define TPC_4_B2__DAC_GAIN_2__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9) + +/* macros for field tx_gain_setting_2 */ +#define TPC_4_B2__TX_GAIN_SETTING_2__SHIFT 14 +#define TPC_4_B2__TX_GAIN_SETTING_2__WIDTH 6 +#define TPC_4_B2__TX_GAIN_SETTING_2__MASK 0x000fc000U +#define TPC_4_B2__TX_GAIN_SETTING_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) + +/* macros for field rate_sent_2 */ +#define TPC_4_B2__RATE_SENT_2__SHIFT 20 +#define TPC_4_B2__RATE_SENT_2__WIDTH 5 +#define TPC_4_B2__RATE_SENT_2__MASK 0x01f00000U +#define TPC_4_B2__RATE_SENT_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_4_B2__TYPE u_int32_t +#define TPC_4_B2__READ 0x01ffffffU + +#endif /* __TPC_4_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_tpc_4_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TPC_4_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_5_b2 */ +#ifndef __TPC_5_B2_MACRO__ +#define __TPC_5_B2_MACRO__ + +/* macros for field pd_gain_boundary_1_2 */ +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__SHIFT 4 +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__WIDTH 6 +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__MASK 0x000003f0U +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field pd_gain_boundary_2_2 */ +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__SHIFT 10 +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__WIDTH 6 +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__MASK 0x0000fc00U +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fc00U) >> 10) +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0000fc00U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0000fc00U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0000fc00U))) + +/* macros for field pd_gain_boundary_3_2 */ +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__SHIFT 16 +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__WIDTH 6 +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__MASK 0x003f0000U +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field pd_gain_boundary_4_2 */ +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__SHIFT 22 +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__WIDTH 6 +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__MASK 0x0fc00000U +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fc00000U) >> 22) +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x0fc00000U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x0fc00000U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x0fc00000U))) +#define TPC_5_B2__TYPE u_int32_t +#define TPC_5_B2__READ 0x0ffffff0U +#define TPC_5_B2__WRITE 0x0ffffff0U + +#endif /* __TPC_5_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_tpc_5_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TPC_5_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_6_b2 */ +#ifndef __TPC_6_B2_MACRO__ +#define __TPC_6_B2_MACRO__ + +/* macros for field pd_dac_setting_1_2 */ +#define TPC_6_B2__PD_DAC_SETTING_1_2__SHIFT 0 +#define TPC_6_B2__PD_DAC_SETTING_1_2__WIDTH 6 +#define TPC_6_B2__PD_DAC_SETTING_1_2__MASK 0x0000003fU +#define TPC_6_B2__PD_DAC_SETTING_1_2__READ(src) (u_int32_t)(src) & 0x0000003fU +#define TPC_6_B2__PD_DAC_SETTING_1_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define TPC_6_B2__PD_DAC_SETTING_1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TPC_6_B2__PD_DAC_SETTING_1_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field pd_dac_setting_2_2 */ +#define TPC_6_B2__PD_DAC_SETTING_2_2__SHIFT 6 +#define TPC_6_B2__PD_DAC_SETTING_2_2__WIDTH 6 +#define TPC_6_B2__PD_DAC_SETTING_2_2__MASK 0x00000fc0U +#define TPC_6_B2__PD_DAC_SETTING_2_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TPC_6_B2__PD_DAC_SETTING_2_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TPC_6_B2__PD_DAC_SETTING_2_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TPC_6_B2__PD_DAC_SETTING_2_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field pd_dac_setting_3_2 */ +#define TPC_6_B2__PD_DAC_SETTING_3_2__SHIFT 12 +#define TPC_6_B2__PD_DAC_SETTING_3_2__WIDTH 6 +#define TPC_6_B2__PD_DAC_SETTING_3_2__MASK 0x0003f000U +#define TPC_6_B2__PD_DAC_SETTING_3_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define TPC_6_B2__PD_DAC_SETTING_3_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define TPC_6_B2__PD_DAC_SETTING_3_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define TPC_6_B2__PD_DAC_SETTING_3_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field pd_dac_setting_4_2 */ +#define TPC_6_B2__PD_DAC_SETTING_4_2__SHIFT 18 +#define TPC_6_B2__PD_DAC_SETTING_4_2__WIDTH 6 +#define TPC_6_B2__PD_DAC_SETTING_4_2__MASK 0x00fc0000U +#define TPC_6_B2__PD_DAC_SETTING_4_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TPC_6_B2__PD_DAC_SETTING_4_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define TPC_6_B2__PD_DAC_SETTING_4_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define TPC_6_B2__PD_DAC_SETTING_4_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field error_est_mode */ +#define TPC_6_B2__ERROR_EST_MODE__SHIFT 24 +#define TPC_6_B2__ERROR_EST_MODE__WIDTH 2 +#define TPC_6_B2__ERROR_EST_MODE__MASK 0x03000000U +#define TPC_6_B2__ERROR_EST_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x03000000U) >> 24) +#define TPC_6_B2__ERROR_EST_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x03000000U) +#define TPC_6_B2__ERROR_EST_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define TPC_6_B2__ERROR_EST_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field error_est_filter_coeff */ +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__SHIFT 26 +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__WIDTH 3 +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__MASK 0x1c000000U +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) +#define TPC_6_B2__TYPE u_int32_t +#define TPC_6_B2__READ 0x1fffffffU +#define TPC_6_B2__WRITE 0x1fffffffU + +#endif /* __TPC_6_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_tpc_6_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TPC_6_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_11_b2 */ +#ifndef __TPC_11_B2_MACRO__ +#define __TPC_11_B2_MACRO__ + +/* macros for field olpc_gain_delta_2 */ +#define TPC_11_B2__OLPC_GAIN_DELTA_2__SHIFT 16 +#define TPC_11_B2__OLPC_GAIN_DELTA_2__WIDTH 8 +#define TPC_11_B2__OLPC_GAIN_DELTA_2__MASK 0x00ff0000U +#define TPC_11_B2__OLPC_GAIN_DELTA_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TPC_11_B2__OLPC_GAIN_DELTA_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TPC_11_B2__OLPC_GAIN_DELTA_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TPC_11_B2__OLPC_GAIN_DELTA_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field olpc_gain_delta_2_pal_on */ +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__SHIFT 24 +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__WIDTH 8 +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__MASK 0xff000000U +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TPC_11_B2__TYPE u_int32_t +#define TPC_11_B2__READ 0xffff0000U +#define TPC_11_B2__WRITE 0xffff0000U + +#endif /* __TPC_11_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_tpc_11_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TPC_11_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pdadc_tab */ +#ifndef __PDADC_TAB_MACRO__ +#define __PDADC_TAB_MACRO__ + +/* macros for field tab_entry */ +#define PDADC_TAB__TAB_ENTRY__SHIFT 0 +#define PDADC_TAB__TAB_ENTRY__WIDTH 32 +#define PDADC_TAB__TAB_ENTRY__MASK 0xffffffffU +#define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define PDADC_TAB__TYPE u_int32_t +#define PDADC_TAB__WRITE 0x00000000U + +#endif /* __PDADC_TAB_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_pdadc_tab_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_PDADC_TAB_B2__NUM 32 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b2 */ +#ifndef __TXIQ_CORR_COEFF_01_B2_MACRO__ +#define __TXIQ_CORR_COEFF_01_B2_MACRO__ + +/* macros for field iqc_coeff_table_0_2 */ +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__SHIFT 0 +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_1_2 */ +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__SHIFT 14 +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_01_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_01_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_01_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_01_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_txiq_corr_coeff_01_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_01_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b2 */ +#ifndef __TXIQ_CORR_COEFF_23_B2_MACRO__ +#define __TXIQ_CORR_COEFF_23_B2_MACRO__ + +/* macros for field iqc_coeff_table_2_2 */ +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__SHIFT 0 +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_3_2 */ +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__SHIFT 14 +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_23_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_23_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_23_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_23_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_txiq_corr_coeff_23_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_23_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b2 */ +#ifndef __TXIQ_CORR_COEFF_45_B2_MACRO__ +#define __TXIQ_CORR_COEFF_45_B2_MACRO__ + +/* macros for field iqc_coeff_table_4_2 */ +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__SHIFT 0 +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_5_2 */ +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__SHIFT 14 +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_45_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_45_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_45_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_45_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_txiq_corr_coeff_45_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_45_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b2 */ +#ifndef __TXIQ_CORR_COEFF_67_B2_MACRO__ +#define __TXIQ_CORR_COEFF_67_B2_MACRO__ + +/* macros for field iqc_coeff_table_6_2 */ +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__SHIFT 0 +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_7_2 */ +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__SHIFT 14 +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_67_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_67_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_67_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_67_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_txiq_corr_coeff_67_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_67_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b2 */ +#ifndef __TXIQ_CORR_COEFF_89_B2_MACRO__ +#define __TXIQ_CORR_COEFF_89_B2_MACRO__ + +/* macros for field iqc_coeff_table_8_2 */ +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__SHIFT 0 +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_9_2 */ +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__SHIFT 14 +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_89_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_89_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_89_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_89_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_txiq_corr_coeff_89_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_89_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b2 */ +#ifndef __TXIQ_CORR_COEFF_AB_B2_MACRO__ +#define __TXIQ_CORR_COEFF_AB_B2_MACRO__ + +/* macros for field iqc_coeff_table_a_2 */ +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__SHIFT 0 +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_b_2 */ +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__SHIFT 14 +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_AB_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_AB_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_AB_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_AB_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_txiq_corr_coeff_ab_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b2 */ +#ifndef __TXIQ_CORR_COEFF_CD_B2_MACRO__ +#define __TXIQ_CORR_COEFF_CD_B2_MACRO__ + +/* macros for field iqc_coeff_table_c_2 */ +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__SHIFT 0 +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_d_2 */ +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__SHIFT 14 +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_CD_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_CD_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_CD_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_CD_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_txiq_corr_coeff_cd_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b2 */ +#ifndef __TXIQ_CORR_COEFF_EF_B2_MACRO__ +#define __TXIQ_CORR_COEFF_EF_B2_MACRO__ + +/* macros for field iqc_coeff_table_e_2 */ +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__SHIFT 0 +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_f_2 */ +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__SHIFT 14 +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_EF_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_EF_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_EF_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_EF_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_txiq_corr_coeff_ef_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_status_b2 */ +#ifndef __TXIQCAL_STATUS_B2_MACRO__ +#define __TXIQCAL_STATUS_B2_MACRO__ + +/* macros for field txiqcal_failed_2 */ +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__SHIFT 0 +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__WIDTH 1 +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__MASK 0x00000001U +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field calibrated_gains_2 */ +#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__SHIFT 1 +#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__WIDTH 5 +#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__MASK 0x0000003eU +#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) + +/* macros for field tone_gain_used_2 */ +#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__SHIFT 6 +#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__WIDTH 6 +#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__MASK 0x00000fc0U +#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) + +/* macros for field rx_gain_used_2 */ +#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__SHIFT 12 +#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__WIDTH 6 +#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__MASK 0x0003f000U +#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) + +/* macros for field last_meas_addr_2 */ +#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__SHIFT 18 +#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__WIDTH 6 +#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__MASK 0x00fc0000U +#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TXIQCAL_STATUS_B2__TYPE u_int32_t +#define TXIQCAL_STATUS_B2__READ 0x00ffffffU + +#endif /* __TXIQCAL_STATUS_B2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_txiqcal_status_b2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_TXIQCAL_STATUS_B2__NUM 1 + +/* macros for bb_reg_block.bb_sm2_reg_map.BB_dummy_sm2 */ +#define INST_BB_REG_BLOCK__BB_SM2_REG_MAP__BB_DUMMY_SM2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn3_reg_map.BB_dummy1 */ +#define INST_BB_REG_BLOCK__BB_CHN3_REG_MAP__BB_DUMMY1__NUM 256 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc3_reg_map.BB_dummy */ +#define INST_BB_REG_BLOCK__BB_AGC3_REG_MAP__BB_DUMMY__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rssi_b3 */ +#ifndef __RSSI_B3_MACRO__ +#define __RSSI_B3_MACRO__ + +/* macros for field rssi_3 */ +#define RSSI_B3__RSSI_3__SHIFT 0 +#define RSSI_B3__RSSI_3__WIDTH 8 +#define RSSI_B3__RSSI_3__MASK 0x000000ffU +#define RSSI_B3__RSSI_3__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field rssi_ext_3 */ +#define RSSI_B3__RSSI_EXT_3__SHIFT 8 +#define RSSI_B3__RSSI_EXT_3__WIDTH 8 +#define RSSI_B3__RSSI_EXT_3__MASK 0x0000ff00U +#define RSSI_B3__RSSI_EXT_3__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define RSSI_B3__TYPE u_int32_t +#define RSSI_B3__READ 0x0000ffffU + +#endif /* __RSSI_B3_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc3_reg_map.BB_rssi_b3 */ +#define INST_BB_REG_BLOCK__BB_AGC3_REG_MAP__BB_RSSI_B3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm3_reg_map.BB_dummy2 */ +#define INST_BB_REG_BLOCK__BB_SM3_REG_MAP__BB_DUMMY2__NUM 384 +#define RFILE_INST_BB_REG_BLOCK__BB_CHN_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_MRC_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_BBB_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_AGC_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_SM_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_CHN1_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_AGC1_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_SM1_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_CHN2_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_AGC2_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_SM2_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_CHN3_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_AGC3_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__BB_SM3_REG_MAP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF_DBG */ +#ifndef __TXBF_DBG_MACRO__ +#define __TXBF_DBG_MACRO__ + +/* macros for field MODE */ +#define TXBF_DBG__MODE__SHIFT 0 +#define TXBF_DBG__MODE__WIDTH 2 +#define TXBF_DBG__MODE__MASK 0x00000003U +#define TXBF_DBG__MODE__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXBF_DBG__MODE__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXBF_DBG__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXBF_DBG__MODE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field CLIENT_TABLE */ +#define TXBF_DBG__CLIENT_TABLE__SHIFT 2 +#define TXBF_DBG__CLIENT_TABLE__WIDTH 16 +#define TXBF_DBG__CLIENT_TABLE__MASK 0x0003fffcU +#define TXBF_DBG__CLIENT_TABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fffcU) >> 2) +#define TXBF_DBG__CLIENT_TABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0003fffcU) +#define TXBF_DBG__CLIENT_TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0003fffcU) +#define TXBF_DBG__CLIENT_TABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0003fffcU))) + +/* macros for field SW_WR_V_DONE */ +#define TXBF_DBG__SW_WR_V_DONE__SHIFT 18 +#define TXBF_DBG__SW_WR_V_DONE__WIDTH 1 +#define TXBF_DBG__SW_WR_V_DONE__MASK 0x00040000U +#define TXBF_DBG__SW_WR_V_DONE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define TXBF_DBG__SW_WR_V_DONE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define TXBF_DBG__SW_WR_V_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define TXBF_DBG__SW_WR_V_DONE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define TXBF_DBG__SW_WR_V_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define TXBF_DBG__SW_WR_V_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field DBG_IM */ +#define TXBF_DBG__DBG_IM__SHIFT 19 +#define TXBF_DBG__DBG_IM__WIDTH 1 +#define TXBF_DBG__DBG_IM__MASK 0x00080000U +#define TXBF_DBG__DBG_IM__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) +#define TXBF_DBG__DBG_IM__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) +#define TXBF_DBG__DBG_IM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TXBF_DBG__DBG_IM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TXBF_DBG__DBG_IM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TXBF_DBG__DBG_IM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field DBG_BW */ +#define TXBF_DBG__DBG_BW__SHIFT 20 +#define TXBF_DBG__DBG_BW__WIDTH 1 +#define TXBF_DBG__DBG_BW__MASK 0x00100000U +#define TXBF_DBG__DBG_BW__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define TXBF_DBG__DBG_BW__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) +#define TXBF_DBG__DBG_BW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TXBF_DBG__DBG_BW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TXBF_DBG__DBG_BW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TXBF_DBG__DBG_BW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field CLK_CNTL */ +#define TXBF_DBG__CLK_CNTL__SHIFT 21 +#define TXBF_DBG__CLK_CNTL__WIDTH 1 +#define TXBF_DBG__CLK_CNTL__MASK 0x00200000U +#define TXBF_DBG__CLK_CNTL__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U) +#define TXBF_DBG__CLK_CNTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define TXBF_DBG__CLK_CNTL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define TXBF_DBG__CLK_CNTL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define TXBF_DBG__CLK_CNTL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field REGULAR_SOUNDING */ +#define TXBF_DBG__REGULAR_SOUNDING__SHIFT 22 +#define TXBF_DBG__REGULAR_SOUNDING__WIDTH 1 +#define TXBF_DBG__REGULAR_SOUNDING__MASK 0x00400000U +#define TXBF_DBG__REGULAR_SOUNDING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define TXBF_DBG__REGULAR_SOUNDING__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define TXBF_DBG__REGULAR_SOUNDING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TXBF_DBG__REGULAR_SOUNDING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TXBF_DBG__REGULAR_SOUNDING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TXBF_DBG__REGULAR_SOUNDING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field DBG_NO_WALSH */ +#define TXBF_DBG__DBG_NO_WALSH__SHIFT 23 +#define TXBF_DBG__DBG_NO_WALSH__WIDTH 1 +#define TXBF_DBG__DBG_NO_WALSH__MASK 0x00800000U +#define TXBF_DBG__DBG_NO_WALSH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TXBF_DBG__DBG_NO_WALSH__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TXBF_DBG__DBG_NO_WALSH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TXBF_DBG__DBG_NO_WALSH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TXBF_DBG__DBG_NO_WALSH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TXBF_DBG__DBG_NO_WALSH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field DBG_NO_CSD */ +#define TXBF_DBG__DBG_NO_CSD__SHIFT 24 +#define TXBF_DBG__DBG_NO_CSD__WIDTH 1 +#define TXBF_DBG__DBG_NO_CSD__MASK 0x01000000U +#define TXBF_DBG__DBG_NO_CSD__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TXBF_DBG__DBG_NO_CSD__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TXBF_DBG__DBG_NO_CSD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TXBF_DBG__DBG_NO_CSD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TXBF_DBG__DBG_NO_CSD__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TXBF_DBG__DBG_NO_CSD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define TXBF_DBG__TYPE u_int32_t +#define TXBF_DBG__READ 0x01dfffffU +#define TXBF_DBG__WRITE 0x01dfffffU + +#endif /* __TXBF_DBG_MACRO__ */ + + +/* macros for svd_reg_block.TXBF_DBG */ +#define INST_SVD_REG_BLOCK__TXBF_DBG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF */ +#ifndef __TXBF_MACRO__ +#define __TXBF_MACRO__ + +/* macros for field CB_TX */ +#define TXBF__CB_TX__SHIFT 0 +#define TXBF__CB_TX__WIDTH 2 +#define TXBF__CB_TX__MASK 0x00000003U +#define TXBF__CB_TX__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXBF__CB_TX__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXBF__CB_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXBF__CB_TX__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field NB_TX */ +#define TXBF__NB_TX__SHIFT 2 +#define TXBF__NB_TX__WIDTH 2 +#define TXBF__NB_TX__MASK 0x0000000cU +#define TXBF__NB_TX__READ(src) (((u_int32_t)(src) & 0x0000000cU) >> 2) +#define TXBF__NB_TX__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000000cU) +#define TXBF__NB_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define TXBF__NB_TX__VERIFY(src) (!((((u_int32_t)(src) << 2) & ~0x0000000cU))) + +/* macros for field NG_RPT_TX */ +#define TXBF__NG_RPT_TX__SHIFT 4 +#define TXBF__NG_RPT_TX__WIDTH 2 +#define TXBF__NG_RPT_TX__MASK 0x00000030U +#define TXBF__NG_RPT_TX__READ(src) (((u_int32_t)(src) & 0x00000030U) >> 4) +#define TXBF__NG_RPT_TX__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000030U) +#define TXBF__NG_RPT_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define TXBF__NG_RPT_TX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field NG_CVCACHE */ +#define TXBF__NG_CVCACHE__SHIFT 6 +#define TXBF__NG_CVCACHE__WIDTH 2 +#define TXBF__NG_CVCACHE__MASK 0x000000c0U +#define TXBF__NG_CVCACHE__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6) +#define TXBF__NG_CVCACHE__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U) +#define TXBF__NG_CVCACHE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define TXBF__NG_CVCACHE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field TXCV_BFWEIGHT_METHOD */ +#define TXBF__TXCV_BFWEIGHT_METHOD__SHIFT 9 +#define TXBF__TXCV_BFWEIGHT_METHOD__WIDTH 2 +#define TXBF__TXCV_BFWEIGHT_METHOD__MASK 0x00000600U +#define TXBF__TXCV_BFWEIGHT_METHOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000600U) >> 9) +#define TXBF__TXCV_BFWEIGHT_METHOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000600U) +#define TXBF__TXCV_BFWEIGHT_METHOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000600U) | (((u_int32_t)(src) <<\ + 9) & 0x00000600U) +#define TXBF__TXCV_BFWEIGHT_METHOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000600U))) + +/* macros for field RLR_EN */ +#define TXBF__RLR_EN__SHIFT 11 +#define TXBF__RLR_EN__WIDTH 1 +#define TXBF__RLR_EN__MASK 0x00000800U +#define TXBF__RLR_EN__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define TXBF__RLR_EN__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define TXBF__RLR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define TXBF__RLR_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define TXBF__RLR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define TXBF__RLR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field RC_20_U_DONE */ +#define TXBF__RC_20_U_DONE__SHIFT 12 +#define TXBF__RC_20_U_DONE__WIDTH 1 +#define TXBF__RC_20_U_DONE__MASK 0x00001000U +#define TXBF__RC_20_U_DONE__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) +#define TXBF__RC_20_U_DONE__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) +#define TXBF__RC_20_U_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define TXBF__RC_20_U_DONE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define TXBF__RC_20_U_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define TXBF__RC_20_U_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field RC_20_L_DONE */ +#define TXBF__RC_20_L_DONE__SHIFT 13 +#define TXBF__RC_20_L_DONE__WIDTH 1 +#define TXBF__RC_20_L_DONE__MASK 0x00002000U +#define TXBF__RC_20_L_DONE__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) +#define TXBF__RC_20_L_DONE__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U) +#define TXBF__RC_20_L_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TXBF__RC_20_L_DONE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TXBF__RC_20_L_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TXBF__RC_20_L_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field RC_40_DONE */ +#define TXBF__RC_40_DONE__SHIFT 14 +#define TXBF__RC_40_DONE__WIDTH 1 +#define TXBF__RC_40_DONE__MASK 0x00004000U +#define TXBF__RC_40_DONE__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) +#define TXBF__RC_40_DONE__WRITE(src) (((u_int32_t)(src) << 14) & 0x00004000U) +#define TXBF__RC_40_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define TXBF__RC_40_DONE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define TXBF__RC_40_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define TXBF__RC_40_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) +#define TXBF__TYPE u_int32_t +#define TXBF__READ 0x00007effU +#define TXBF__WRITE 0x00007effU + +#endif /* __TXBF_MACRO__ */ + + +/* macros for svd_reg_block.TXBF */ +#define INST_SVD_REG_BLOCK__TXBF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF_TIMER */ +#ifndef __TXBF_TIMER_MACRO__ +#define __TXBF_TIMER_MACRO__ + +/* macros for field TIMEOUT */ +#define TXBF_TIMER__TIMEOUT__SHIFT 0 +#define TXBF_TIMER__TIMEOUT__WIDTH 8 +#define TXBF_TIMER__TIMEOUT__MASK 0x000000ffU +#define TXBF_TIMER__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TXBF_TIMER__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define TXBF_TIMER__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TXBF_TIMER__TIMEOUT__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field ATIMEOUT */ +#define TXBF_TIMER__ATIMEOUT__SHIFT 8 +#define TXBF_TIMER__ATIMEOUT__WIDTH 8 +#define TXBF_TIMER__ATIMEOUT__MASK 0x0000ff00U +#define TXBF_TIMER__ATIMEOUT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define TXBF_TIMER__ATIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TXBF_TIMER__ATIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TXBF_TIMER__ATIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define TXBF_TIMER__TYPE u_int32_t +#define TXBF_TIMER__READ 0x0000ffffU +#define TXBF_TIMER__WRITE 0x0000ffffU + +#endif /* __TXBF_TIMER_MACRO__ */ + + +/* macros for svd_reg_block.TXBF_TIMER */ +#define INST_SVD_REG_BLOCK__TXBF_TIMER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF_SW */ +#ifndef __TXBF_SW_MACRO__ +#define __TXBF_SW_MACRO__ + +/* macros for field LRU_ACK */ +#define TXBF_SW__LRU_ACK__SHIFT 0 +#define TXBF_SW__LRU_ACK__WIDTH 1 +#define TXBF_SW__LRU_ACK__MASK 0x00000001U +#define TXBF_SW__LRU_ACK__READ(src) (u_int32_t)(src) & 0x00000001U +#define TXBF_SW__LRU_ACK__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TXBF_SW__LRU_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TXBF_SW__LRU_ACK__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TXBF_SW__LRU_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXBF_SW__LRU_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LRU_ADDR */ +#define TXBF_SW__LRU_ADDR__SHIFT 1 +#define TXBF_SW__LRU_ADDR__WIDTH 9 +#define TXBF_SW__LRU_ADDR__MASK 0x000003feU +#define TXBF_SW__LRU_ADDR__READ(src) (((u_int32_t)(src) & 0x000003feU) >> 1) + +/* macros for field LRU_EN */ +#define TXBF_SW__LRU_EN__SHIFT 11 +#define TXBF_SW__LRU_EN__WIDTH 1 +#define TXBF_SW__LRU_EN__MASK 0x00000800U +#define TXBF_SW__LRU_EN__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define TXBF_SW__LRU_EN__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define TXBF_SW__LRU_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define TXBF_SW__LRU_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define TXBF_SW__LRU_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define TXBF_SW__LRU_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field DEST_IDX */ +#define TXBF_SW__DEST_IDX__SHIFT 12 +#define TXBF_SW__DEST_IDX__WIDTH 7 +#define TXBF_SW__DEST_IDX__MASK 0x0007f000U +#define TXBF_SW__DEST_IDX__READ(src) (((u_int32_t)(src) & 0x0007f000U) >> 12) +#define TXBF_SW__DEST_IDX__WRITE(src) (((u_int32_t)(src) << 12) & 0x0007f000U) +#define TXBF_SW__DEST_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0007f000U) +#define TXBF_SW__DEST_IDX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0007f000U))) + +/* macros for field LRU_WR_ACK */ +#define TXBF_SW__LRU_WR_ACK__SHIFT 19 +#define TXBF_SW__LRU_WR_ACK__WIDTH 1 +#define TXBF_SW__LRU_WR_ACK__MASK 0x00080000U +#define TXBF_SW__LRU_WR_ACK__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) +#define TXBF_SW__LRU_WR_ACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define TXBF_SW__LRU_WR_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TXBF_SW__LRU_WR_ACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TXBF_SW__LRU_WR_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TXBF_SW__LRU_WR_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field LRU_RD_ACK */ +#define TXBF_SW__LRU_RD_ACK__SHIFT 20 +#define TXBF_SW__LRU_RD_ACK__WIDTH 1 +#define TXBF_SW__LRU_RD_ACK__MASK 0x00100000U +#define TXBF_SW__LRU_RD_ACK__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define TXBF_SW__LRU_RD_ACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define TXBF_SW__LRU_RD_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TXBF_SW__LRU_RD_ACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TXBF_SW__LRU_RD_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TXBF_SW__LRU_RD_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field WALSH_CSD_MODE */ +#define TXBF_SW__WALSH_CSD_MODE__SHIFT 21 +#define TXBF_SW__WALSH_CSD_MODE__WIDTH 1 +#define TXBF_SW__WALSH_CSD_MODE__MASK 0x00200000U +#define TXBF_SW__WALSH_CSD_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define TXBF_SW__WALSH_CSD_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define TXBF_SW__WALSH_CSD_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define TXBF_SW__WALSH_CSD_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define TXBF_SW__WALSH_CSD_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define TXBF_SW__WALSH_CSD_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field CONDITION_NUMBER */ +#define TXBF_SW__CONDITION_NUMBER__SHIFT 22 +#define TXBF_SW__CONDITION_NUMBER__WIDTH 5 +#define TXBF_SW__CONDITION_NUMBER__MASK 0x07c00000U +#define TXBF_SW__CONDITION_NUMBER__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define TXBF_SW__CONDITION_NUMBER__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define TXBF_SW__CONDITION_NUMBER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define TXBF_SW__CONDITION_NUMBER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) +#define TXBF_SW__TYPE u_int32_t +#define TXBF_SW__READ 0x07fffbffU +#define TXBF_SW__WRITE 0x07fffbffU + +#endif /* __TXBF_SW_MACRO__ */ + + +/* macros for svd_reg_block.TXBF_SW */ +#define INST_SVD_REG_BLOCK__TXBF_SW__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF_SM */ +#ifndef __TXBF_SM_MACRO__ +#define __TXBF_SM_MACRO__ + +/* macros for field OBS */ +#define TXBF_SM__OBS__SHIFT 0 +#define TXBF_SM__OBS__WIDTH 32 +#define TXBF_SM__OBS__MASK 0xffffffffU +#define TXBF_SM__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF_SM__TYPE u_int32_t +#define TXBF_SM__READ 0xffffffffU + +#endif /* __TXBF_SM_MACRO__ */ + + +/* macros for svd_reg_block.TXBF_SM */ +#define INST_SVD_REG_BLOCK__TXBF_SM__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF1_CNTL */ +#ifndef __TXBF1_CNTL_MACRO__ +#define __TXBF1_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF1_CNTL__OBS__SHIFT 0 +#define TXBF1_CNTL__OBS__WIDTH 32 +#define TXBF1_CNTL__OBS__MASK 0xffffffffU +#define TXBF1_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF1_CNTL__TYPE u_int32_t +#define TXBF1_CNTL__READ 0xffffffffU + +#endif /* __TXBF1_CNTL_MACRO__ */ + + +/* macros for svd_reg_block.TXBF1_CNTL */ +#define INST_SVD_REG_BLOCK__TXBF1_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF2_CNTL */ +#ifndef __TXBF2_CNTL_MACRO__ +#define __TXBF2_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF2_CNTL__OBS__SHIFT 0 +#define TXBF2_CNTL__OBS__WIDTH 32 +#define TXBF2_CNTL__OBS__MASK 0xffffffffU +#define TXBF2_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF2_CNTL__TYPE u_int32_t +#define TXBF2_CNTL__READ 0xffffffffU + +#endif /* __TXBF2_CNTL_MACRO__ */ + + +/* macros for svd_reg_block.TXBF2_CNTL */ +#define INST_SVD_REG_BLOCK__TXBF2_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF3_CNTL */ +#ifndef __TXBF3_CNTL_MACRO__ +#define __TXBF3_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF3_CNTL__OBS__SHIFT 0 +#define TXBF3_CNTL__OBS__WIDTH 32 +#define TXBF3_CNTL__OBS__MASK 0xffffffffU +#define TXBF3_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF3_CNTL__TYPE u_int32_t +#define TXBF3_CNTL__READ 0xffffffffU + +#endif /* __TXBF3_CNTL_MACRO__ */ + + +/* macros for svd_reg_block.TXBF3_CNTL */ +#define INST_SVD_REG_BLOCK__TXBF3_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF4_CNTL */ +#ifndef __TXBF4_CNTL_MACRO__ +#define __TXBF4_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF4_CNTL__OBS__SHIFT 0 +#define TXBF4_CNTL__OBS__WIDTH 32 +#define TXBF4_CNTL__OBS__MASK 0xffffffffU +#define TXBF4_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF4_CNTL__TYPE u_int32_t +#define TXBF4_CNTL__READ 0xffffffffU + +#endif /* __TXBF4_CNTL_MACRO__ */ + + +/* macros for svd_reg_block.TXBF4_CNTL */ +#define INST_SVD_REG_BLOCK__TXBF4_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF5_CNTL */ +#ifndef __TXBF5_CNTL_MACRO__ +#define __TXBF5_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF5_CNTL__OBS__SHIFT 0 +#define TXBF5_CNTL__OBS__WIDTH 32 +#define TXBF5_CNTL__OBS__MASK 0xffffffffU +#define TXBF5_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF5_CNTL__TYPE u_int32_t +#define TXBF5_CNTL__READ 0xffffffffU + +#endif /* __TXBF5_CNTL_MACRO__ */ + + +/* macros for svd_reg_block.TXBF5_CNTL */ +#define INST_SVD_REG_BLOCK__TXBF5_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF6_CNTL */ +#ifndef __TXBF6_CNTL_MACRO__ +#define __TXBF6_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF6_CNTL__OBS__SHIFT 0 +#define TXBF6_CNTL__OBS__WIDTH 32 +#define TXBF6_CNTL__OBS__MASK 0xffffffffU +#define TXBF6_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF6_CNTL__TYPE u_int32_t +#define TXBF6_CNTL__READ 0xffffffffU + +#endif /* __TXBF6_CNTL_MACRO__ */ + + +/* macros for svd_reg_block.TXBF6_CNTL */ +#define INST_SVD_REG_BLOCK__TXBF6_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF7_CNTL */ +#ifndef __TXBF7_CNTL_MACRO__ +#define __TXBF7_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF7_CNTL__OBS__SHIFT 0 +#define TXBF7_CNTL__OBS__WIDTH 32 +#define TXBF7_CNTL__OBS__MASK 0xffffffffU +#define TXBF7_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF7_CNTL__TYPE u_int32_t +#define TXBF7_CNTL__READ 0xffffffffU + +#endif /* __TXBF7_CNTL_MACRO__ */ + + +/* macros for svd_reg_block.TXBF7_CNTL */ +#define INST_SVD_REG_BLOCK__TXBF7_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF8_CNTL */ +#ifndef __TXBF8_CNTL_MACRO__ +#define __TXBF8_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF8_CNTL__OBS__SHIFT 0 +#define TXBF8_CNTL__OBS__WIDTH 32 +#define TXBF8_CNTL__OBS__MASK 0xffffffffU +#define TXBF8_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF8_CNTL__TYPE u_int32_t +#define TXBF8_CNTL__READ 0xffffffffU + +#endif /* __TXBF8_CNTL_MACRO__ */ + + +/* macros for svd_reg_block.TXBF8_CNTL */ +#define INST_SVD_REG_BLOCK__TXBF8_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RC0 */ +#ifndef __RC0_MACRO__ +#define __RC0_MACRO__ + +/* macros for field DATA */ +#define RC0__DATA__SHIFT 0 +#define RC0__DATA__WIDTH 32 +#define RC0__DATA__MASK 0xffffffffU +#define RC0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define RC0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define RC0__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define RC0__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define RC0__TYPE u_int32_t +#define RC0__READ 0xffffffffU +#define RC0__WRITE 0xffffffffU + +#endif /* __RC0_MACRO__ */ + + +/* macros for svd_reg_block.RC0 */ +#define INST_SVD_REG_BLOCK__RC0__NUM 118 + +/* macros for BlueprintGlobalNameSpace::RC1 */ +#ifndef __RC1_MACRO__ +#define __RC1_MACRO__ + +/* macros for field DATA */ +#define RC1__DATA__SHIFT 0 +#define RC1__DATA__WIDTH 32 +#define RC1__DATA__MASK 0xffffffffU +#define RC1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define RC1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define RC1__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define RC1__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define RC1__TYPE u_int32_t +#define RC1__READ 0xffffffffU +#define RC1__WRITE 0xffffffffU + +#endif /* __RC1_MACRO__ */ + + +/* macros for svd_reg_block.RC1 */ +#define INST_SVD_REG_BLOCK__RC1__NUM 118 + +/* macros for BlueprintGlobalNameSpace::SVD_MEM0 */ +#ifndef __SVD_MEM0_MACRO__ +#define __SVD_MEM0_MACRO__ + +/* macros for field DATA */ +#define SVD_MEM0__DATA__SHIFT 0 +#define SVD_MEM0__DATA__WIDTH 32 +#define SVD_MEM0__DATA__MASK 0xffffffffU +#define SVD_MEM0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define SVD_MEM0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define SVD_MEM0__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define SVD_MEM0__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define SVD_MEM0__TYPE u_int32_t +#define SVD_MEM0__READ 0xffffffffU +#define SVD_MEM0__WRITE 0xffffffffU + +#endif /* __SVD_MEM0_MACRO__ */ + + +/* macros for svd_reg_block.SVD_MEM0 */ +#define INST_SVD_REG_BLOCK__SVD_MEM0__NUM 114 + +/* macros for BlueprintGlobalNameSpace::SVD_MEM1 */ +#ifndef __SVD_MEM1_MACRO__ +#define __SVD_MEM1_MACRO__ + +/* macros for field DATA */ +#define SVD_MEM1__DATA__SHIFT 0 +#define SVD_MEM1__DATA__WIDTH 32 +#define SVD_MEM1__DATA__MASK 0xffffffffU +#define SVD_MEM1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define SVD_MEM1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define SVD_MEM1__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define SVD_MEM1__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define SVD_MEM1__TYPE u_int32_t +#define SVD_MEM1__READ 0xffffffffU +#define SVD_MEM1__WRITE 0xffffffffU + +#endif /* __SVD_MEM1_MACRO__ */ + + +/* macros for svd_reg_block.SVD_MEM1 */ +#define INST_SVD_REG_BLOCK__SVD_MEM1__NUM 114 + +/* macros for BlueprintGlobalNameSpace::SVD_MEM2 */ +#ifndef __SVD_MEM2_MACRO__ +#define __SVD_MEM2_MACRO__ + +/* macros for field DATA */ +#define SVD_MEM2__DATA__SHIFT 0 +#define SVD_MEM2__DATA__WIDTH 32 +#define SVD_MEM2__DATA__MASK 0xffffffffU +#define SVD_MEM2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define SVD_MEM2__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define SVD_MEM2__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define SVD_MEM2__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define SVD_MEM2__TYPE u_int32_t +#define SVD_MEM2__READ 0xffffffffU +#define SVD_MEM2__WRITE 0xffffffffU + +#endif /* __SVD_MEM2_MACRO__ */ + + +/* macros for svd_reg_block.SVD_MEM2 */ +#define INST_SVD_REG_BLOCK__SVD_MEM2__NUM 114 + +/* macros for BlueprintGlobalNameSpace::SVD_MEM3 */ +#ifndef __SVD_MEM3_MACRO__ +#define __SVD_MEM3_MACRO__ + +/* macros for field DATA */ +#define SVD_MEM3__DATA__SHIFT 0 +#define SVD_MEM3__DATA__WIDTH 32 +#define SVD_MEM3__DATA__MASK 0xffffffffU +#define SVD_MEM3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define SVD_MEM3__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define SVD_MEM3__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define SVD_MEM3__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define SVD_MEM3__TYPE u_int32_t +#define SVD_MEM3__READ 0xffffffffU +#define SVD_MEM3__WRITE 0xffffffffU + +#endif /* __SVD_MEM3_MACRO__ */ + + +/* macros for svd_reg_block.SVD_MEM3 */ +#define INST_SVD_REG_BLOCK__SVD_MEM3__NUM 114 + +/* macros for BlueprintGlobalNameSpace::SVD_MEM4 */ +#ifndef __SVD_MEM4_MACRO__ +#define __SVD_MEM4_MACRO__ + +/* macros for field DATA */ +#define SVD_MEM4__DATA__SHIFT 0 +#define SVD_MEM4__DATA__WIDTH 32 +#define SVD_MEM4__DATA__MASK 0xffffffffU +#define SVD_MEM4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define SVD_MEM4__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define SVD_MEM4__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define SVD_MEM4__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define SVD_MEM4__TYPE u_int32_t +#define SVD_MEM4__READ 0xffffffffU +#define SVD_MEM4__WRITE 0xffffffffU + +#endif /* __SVD_MEM4_MACRO__ */ + + +/* macros for svd_reg_block.SVD_MEM4 */ +#define INST_SVD_REG_BLOCK__SVD_MEM4__NUM 114 + +/* macros for BlueprintGlobalNameSpace::CVCACHE */ +#ifndef __CVCACHE_MACRO__ +#define __CVCACHE_MACRO__ + +/* macros for field DATA */ +#define CVCACHE__DATA__SHIFT 0 +#define CVCACHE__DATA__WIDTH 32 +#define CVCACHE__DATA__MASK 0xffffffffU +#define CVCACHE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CVCACHE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CVCACHE__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CVCACHE__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CVCACHE__TYPE u_int32_t +#define CVCACHE__READ 0xffffffffU +#define CVCACHE__WRITE 0xffffffffU + +#endif /* __CVCACHE_MACRO__ */ + + +/* macros for svd_reg_block.CVCACHE */ +#define INST_SVD_REG_BLOCK__CVCACHE__NUM 512 + +/* macros for BlueprintGlobalNameSpace::OTP_MEM */ +#ifndef __OTP_MEM_MACRO__ +#define __OTP_MEM_MACRO__ + +/* macros for field OTP_MEM */ +#define OTP_MEM__OTP_MEM__SHIFT 0 +#define OTP_MEM__OTP_MEM__WIDTH 32 +#define OTP_MEM__OTP_MEM__MASK 0xffffffffU +#define OTP_MEM__OTP_MEM__READ(src) (u_int32_t)(src) & 0xffffffffU +#define OTP_MEM__OTP_MEM__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define OTP_MEM__OTP_MEM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define OTP_MEM__OTP_MEM__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define OTP_MEM__TYPE u_int32_t +#define OTP_MEM__READ 0xffffffffU +#define OTP_MEM__WRITE 0xffffffffU + +#endif /* __OTP_MEM_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_MEM */ +#define INST_EFUSE_REG_BLOCK__OTP_MEM__NUM 256 + +/* macros for BlueprintGlobalNameSpace::OTP_INTF0 */ +#ifndef __OTP_INTF0_MACRO__ +#define __OTP_INTF0_MACRO__ + +/* macros for field EFUSE_WR_ENABLE_REG_V */ +#define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__SHIFT 0 +#define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__WIDTH 32 +#define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__MASK 0xffffffffU +#define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define OTP_INTF0__TYPE u_int32_t +#define OTP_INTF0__READ 0xffffffffU +#define OTP_INTF0__WRITE 0xffffffffU + +#endif /* __OTP_INTF0_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_INTF0 */ +#define INST_EFUSE_REG_BLOCK__OTP_INTF0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_INTF1 */ +#ifndef __OTP_INTF1_MACRO__ +#define __OTP_INTF1_MACRO__ + +/* macros for field BITMASK_WR_REG_V */ +#define OTP_INTF1__BITMASK_WR_REG_V__SHIFT 0 +#define OTP_INTF1__BITMASK_WR_REG_V__WIDTH 32 +#define OTP_INTF1__BITMASK_WR_REG_V__MASK 0xffffffffU +#define OTP_INTF1__BITMASK_WR_REG_V__READ(src) (u_int32_t)(src) & 0xffffffffU +#define OTP_INTF1__BITMASK_WR_REG_V__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define OTP_INTF1__BITMASK_WR_REG_V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define OTP_INTF1__BITMASK_WR_REG_V__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define OTP_INTF1__TYPE u_int32_t +#define OTP_INTF1__READ 0xffffffffU +#define OTP_INTF1__WRITE 0xffffffffU + +#endif /* __OTP_INTF1_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_INTF1 */ +#define INST_EFUSE_REG_BLOCK__OTP_INTF1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_INTF2 */ +#ifndef __OTP_INTF2_MACRO__ +#define __OTP_INTF2_MACRO__ + +/* macros for field PG_STROBE_PW_REG_V */ +#define OTP_INTF2__PG_STROBE_PW_REG_V__SHIFT 0 +#define OTP_INTF2__PG_STROBE_PW_REG_V__WIDTH 32 +#define OTP_INTF2__PG_STROBE_PW_REG_V__MASK 0xffffffffU +#define OTP_INTF2__PG_STROBE_PW_REG_V__READ(src) (u_int32_t)(src) & 0xffffffffU +#define OTP_INTF2__PG_STROBE_PW_REG_V__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define OTP_INTF2__PG_STROBE_PW_REG_V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define OTP_INTF2__PG_STROBE_PW_REG_V__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define OTP_INTF2__TYPE u_int32_t +#define OTP_INTF2__READ 0xffffffffU +#define OTP_INTF2__WRITE 0xffffffffU + +#endif /* __OTP_INTF2_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_INTF2 */ +#define INST_EFUSE_REG_BLOCK__OTP_INTF2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_INTF3 */ +#ifndef __OTP_INTF3_MACRO__ +#define __OTP_INTF3_MACRO__ + +/* macros for field RD_STROBE_PW_REG_V */ +#define OTP_INTF3__RD_STROBE_PW_REG_V__SHIFT 0 +#define OTP_INTF3__RD_STROBE_PW_REG_V__WIDTH 32 +#define OTP_INTF3__RD_STROBE_PW_REG_V__MASK 0xffffffffU +#define OTP_INTF3__RD_STROBE_PW_REG_V__READ(src) (u_int32_t)(src) & 0xffffffffU +#define OTP_INTF3__RD_STROBE_PW_REG_V__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define OTP_INTF3__RD_STROBE_PW_REG_V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define OTP_INTF3__RD_STROBE_PW_REG_V__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define OTP_INTF3__TYPE u_int32_t +#define OTP_INTF3__READ 0xffffffffU +#define OTP_INTF3__WRITE 0xffffffffU + +#endif /* __OTP_INTF3_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_INTF3 */ +#define INST_EFUSE_REG_BLOCK__OTP_INTF3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_INTF4 */ +#ifndef __OTP_INTF4_MACRO__ +#define __OTP_INTF4_MACRO__ + +/* macros for field VDDQ_SETTLE_TIME_REG_V */ +#define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__SHIFT 0 +#define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__WIDTH 32 +#define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__MASK 0xffffffffU +#define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define OTP_INTF4__TYPE u_int32_t +#define OTP_INTF4__READ 0xffffffffU +#define OTP_INTF4__WRITE 0xffffffffU + +#endif /* __OTP_INTF4_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_INTF4 */ +#define INST_EFUSE_REG_BLOCK__OTP_INTF4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_INTF5 */ +#ifndef __OTP_INTF5_MACRO__ +#define __OTP_INTF5_MACRO__ + +/* macros for field EFUSE_INT_ENABLE_REG_V */ +#define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__SHIFT 0 +#define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__WIDTH 1 +#define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__MASK 0x00000001U +#define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define OTP_INTF5__TYPE u_int32_t +#define OTP_INTF5__READ 0x00000001U +#define OTP_INTF5__WRITE 0x00000001U + +#endif /* __OTP_INTF5_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_INTF5 */ +#define INST_EFUSE_REG_BLOCK__OTP_INTF5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_STATUS0 */ +#ifndef __OTP_STATUS0_MACRO__ +#define __OTP_STATUS0_MACRO__ + +/* macros for field OTP_SM_BUSY */ +#define OTP_STATUS0__OTP_SM_BUSY__SHIFT 0 +#define OTP_STATUS0__OTP_SM_BUSY__WIDTH 1 +#define OTP_STATUS0__OTP_SM_BUSY__MASK 0x00000001U +#define OTP_STATUS0__OTP_SM_BUSY__READ(src) (u_int32_t)(src) & 0x00000001U +#define OTP_STATUS0__OTP_SM_BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define OTP_STATUS0__OTP_SM_BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field EFUSE_ACCESS_BUSY */ +#define OTP_STATUS0__EFUSE_ACCESS_BUSY__SHIFT 1 +#define OTP_STATUS0__EFUSE_ACCESS_BUSY__WIDTH 1 +#define OTP_STATUS0__EFUSE_ACCESS_BUSY__MASK 0x00000002U +#define OTP_STATUS0__EFUSE_ACCESS_BUSY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define OTP_STATUS0__EFUSE_ACCESS_BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define OTP_STATUS0__EFUSE_ACCESS_BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field EFUSE_READ_DATA_VALID */ +#define OTP_STATUS0__EFUSE_READ_DATA_VALID__SHIFT 2 +#define OTP_STATUS0__EFUSE_READ_DATA_VALID__WIDTH 1 +#define OTP_STATUS0__EFUSE_READ_DATA_VALID__MASK 0x00000004U +#define OTP_STATUS0__EFUSE_READ_DATA_VALID__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define OTP_STATUS0__EFUSE_READ_DATA_VALID__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define OTP_STATUS0__EFUSE_READ_DATA_VALID__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define OTP_STATUS0__TYPE u_int32_t +#define OTP_STATUS0__READ 0x00000007U + +#endif /* __OTP_STATUS0_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_STATUS0 */ +#define INST_EFUSE_REG_BLOCK__OTP_STATUS0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_STATUS1 */ +#ifndef __OTP_STATUS1_MACRO__ +#define __OTP_STATUS1_MACRO__ + +/* macros for field EFUSE_READ_DATA */ +#define OTP_STATUS1__EFUSE_READ_DATA__SHIFT 0 +#define OTP_STATUS1__EFUSE_READ_DATA__WIDTH 32 +#define OTP_STATUS1__EFUSE_READ_DATA__MASK 0xffffffffU +#define OTP_STATUS1__EFUSE_READ_DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define OTP_STATUS1__TYPE u_int32_t +#define OTP_STATUS1__READ 0xffffffffU + +#endif /* __OTP_STATUS1_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_STATUS1 */ +#define INST_EFUSE_REG_BLOCK__OTP_STATUS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_INTF6 */ +#ifndef __OTP_INTF6_MACRO__ +#define __OTP_INTF6_MACRO__ + +/* macros for field BACK_TO_BACK_ACCESS_DELAY */ +#define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__SHIFT 0 +#define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__WIDTH 32 +#define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__MASK 0xffffffffU +#define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define OTP_INTF6__TYPE u_int32_t +#define OTP_INTF6__READ 0xffffffffU +#define OTP_INTF6__WRITE 0xffffffffU + +#endif /* __OTP_INTF6_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_INTF6 */ +#define INST_EFUSE_REG_BLOCK__OTP_INTF6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_LDO_CONTROL */ +#ifndef __OTP_LDO_CONTROL_MACRO__ +#define __OTP_LDO_CONTROL_MACRO__ + +/* macros for field ENABLE */ +#define OTP_LDO_CONTROL__ENABLE__SHIFT 0 +#define OTP_LDO_CONTROL__ENABLE__WIDTH 1 +#define OTP_LDO_CONTROL__ENABLE__MASK 0x00000001U +#define OTP_LDO_CONTROL__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define OTP_LDO_CONTROL__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define OTP_LDO_CONTROL__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define OTP_LDO_CONTROL__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define OTP_LDO_CONTROL__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define OTP_LDO_CONTROL__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define OTP_LDO_CONTROL__TYPE u_int32_t +#define OTP_LDO_CONTROL__READ 0x00000001U +#define OTP_LDO_CONTROL__WRITE 0x00000001U + +#endif /* __OTP_LDO_CONTROL_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_LDO_CONTROL */ +#define INST_EFUSE_REG_BLOCK__OTP_LDO_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_LDO_POWER_GOOD */ +#ifndef __OTP_LDO_POWER_GOOD_MACRO__ +#define __OTP_LDO_POWER_GOOD_MACRO__ + +/* macros for field DELAY */ +#define OTP_LDO_POWER_GOOD__DELAY__SHIFT 0 +#define OTP_LDO_POWER_GOOD__DELAY__WIDTH 12 +#define OTP_LDO_POWER_GOOD__DELAY__MASK 0x00000fffU +#define OTP_LDO_POWER_GOOD__DELAY__READ(src) (u_int32_t)(src) & 0x00000fffU +#define OTP_LDO_POWER_GOOD__DELAY__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) +#define OTP_LDO_POWER_GOOD__DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define OTP_LDO_POWER_GOOD__DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) +#define OTP_LDO_POWER_GOOD__TYPE u_int32_t +#define OTP_LDO_POWER_GOOD__READ 0x00000fffU +#define OTP_LDO_POWER_GOOD__WRITE 0x00000fffU + +#endif /* __OTP_LDO_POWER_GOOD_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_LDO_POWER_GOOD */ +#define INST_EFUSE_REG_BLOCK__OTP_LDO_POWER_GOOD__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_LDO_STATUS */ +#ifndef __OTP_LDO_STATUS_MACRO__ +#define __OTP_LDO_STATUS_MACRO__ + +/* macros for field POWER_ON */ +#define OTP_LDO_STATUS__POWER_ON__SHIFT 0 +#define OTP_LDO_STATUS__POWER_ON__WIDTH 1 +#define OTP_LDO_STATUS__POWER_ON__MASK 0x00000001U +#define OTP_LDO_STATUS__POWER_ON__READ(src) (u_int32_t)(src) & 0x00000001U +#define OTP_LDO_STATUS__POWER_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define OTP_LDO_STATUS__POWER_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define OTP_LDO_STATUS__TYPE u_int32_t +#define OTP_LDO_STATUS__READ 0x00000001U + +#endif /* __OTP_LDO_STATUS_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_LDO_STATUS */ +#define INST_EFUSE_REG_BLOCK__OTP_LDO_STATUS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_VDDQ_HOLD_TIME */ +#ifndef __OTP_VDDQ_HOLD_TIME_MACRO__ +#define __OTP_VDDQ_HOLD_TIME_MACRO__ + +/* macros for field DELAY */ +#define OTP_VDDQ_HOLD_TIME__DELAY__SHIFT 0 +#define OTP_VDDQ_HOLD_TIME__DELAY__WIDTH 32 +#define OTP_VDDQ_HOLD_TIME__DELAY__MASK 0xffffffffU +#define OTP_VDDQ_HOLD_TIME__DELAY__READ(src) (u_int32_t)(src) & 0xffffffffU +#define OTP_VDDQ_HOLD_TIME__DELAY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define OTP_VDDQ_HOLD_TIME__DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define OTP_VDDQ_HOLD_TIME__DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define OTP_VDDQ_HOLD_TIME__TYPE u_int32_t +#define OTP_VDDQ_HOLD_TIME__READ 0xffffffffU +#define OTP_VDDQ_HOLD_TIME__WRITE 0xffffffffU + +#endif /* __OTP_VDDQ_HOLD_TIME_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_VDDQ_HOLD_TIME */ +#define INST_EFUSE_REG_BLOCK__OTP_VDDQ_HOLD_TIME__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_PGENB_SETUP_HOLD_TIME */ +#ifndef __OTP_PGENB_SETUP_HOLD_TIME_MACRO__ +#define __OTP_PGENB_SETUP_HOLD_TIME_MACRO__ + +/* macros for field DELAY */ +#define OTP_PGENB_SETUP_HOLD_TIME__DELAY__SHIFT 0 +#define OTP_PGENB_SETUP_HOLD_TIME__DELAY__WIDTH 32 +#define OTP_PGENB_SETUP_HOLD_TIME__DELAY__MASK 0xffffffffU +#define OTP_PGENB_SETUP_HOLD_TIME__DELAY__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define OTP_PGENB_SETUP_HOLD_TIME__DELAY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define OTP_PGENB_SETUP_HOLD_TIME__DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define OTP_PGENB_SETUP_HOLD_TIME__DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define OTP_PGENB_SETUP_HOLD_TIME__TYPE u_int32_t +#define OTP_PGENB_SETUP_HOLD_TIME__READ 0xffffffffU +#define OTP_PGENB_SETUP_HOLD_TIME__WRITE 0xffffffffU + +#endif /* __OTP_PGENB_SETUP_HOLD_TIME_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_PGENB_SETUP_HOLD_TIME */ +#define INST_EFUSE_REG_BLOCK__OTP_PGENB_SETUP_HOLD_TIME__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_STROBE_PULSE_INTERVAL */ +#ifndef __OTP_STROBE_PULSE_INTERVAL_MACRO__ +#define __OTP_STROBE_PULSE_INTERVAL_MACRO__ + +/* macros for field DELAY */ +#define OTP_STROBE_PULSE_INTERVAL__DELAY__SHIFT 0 +#define OTP_STROBE_PULSE_INTERVAL__DELAY__WIDTH 32 +#define OTP_STROBE_PULSE_INTERVAL__DELAY__MASK 0xffffffffU +#define OTP_STROBE_PULSE_INTERVAL__DELAY__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define OTP_STROBE_PULSE_INTERVAL__DELAY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define OTP_STROBE_PULSE_INTERVAL__DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define OTP_STROBE_PULSE_INTERVAL__DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define OTP_STROBE_PULSE_INTERVAL__TYPE u_int32_t +#define OTP_STROBE_PULSE_INTERVAL__READ 0xffffffffU +#define OTP_STROBE_PULSE_INTERVAL__WRITE 0xffffffffU + +#endif /* __OTP_STROBE_PULSE_INTERVAL_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_STROBE_PULSE_INTERVAL */ +#define INST_EFUSE_REG_BLOCK__OTP_STROBE_PULSE_INTERVAL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::OTP_CSB_ADDR_LOAD_SETUP_HOLD */ +#ifndef __OTP_CSB_ADDR_LOAD_SETUP_HOLD_MACRO__ +#define __OTP_CSB_ADDR_LOAD_SETUP_HOLD_MACRO__ + +/* macros for field DELAY */ +#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__SHIFT 0 +#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__WIDTH 32 +#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__MASK 0xffffffffU +#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__TYPE u_int32_t +#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__READ 0xffffffffU +#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__WRITE 0xffffffffU + +#endif /* __OTP_CSB_ADDR_LOAD_SETUP_HOLD_MACRO__ */ + + +/* macros for efuse_reg_block.OTP_CSB_ADDR_LOAD_SETUP_HOLD */ +#define INST_EFUSE_REG_BLOCK__OTP_CSB_ADDR_LOAD_SETUP_HOLD__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXRF_BIAS1 */ +#ifndef __RXRF_BIAS1_MACRO__ +#define __RXRF_BIAS1_MACRO__ + +/* macros for field SPARE */ +#define RXRF_BIAS1__SPARE__SHIFT 0 +#define RXRF_BIAS1__SPARE__WIDTH 1 +#define RXRF_BIAS1__SPARE__MASK 0x00000001U +#define RXRF_BIAS1__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXRF_BIAS1__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXRF_BIAS1__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXRF_BIAS1__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define RXRF_BIAS1__SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXRF_BIAS1__SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PWD_IR25SPARE */ +#define RXRF_BIAS1__PWD_IR25SPARE__SHIFT 1 +#define RXRF_BIAS1__PWD_IR25SPARE__WIDTH 3 +#define RXRF_BIAS1__PWD_IR25SPARE__MASK 0x0000000eU +#define RXRF_BIAS1__PWD_IR25SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define RXRF_BIAS1__PWD_IR25SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define RXRF_BIAS1__PWD_IR25SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define RXRF_BIAS1__PWD_IR25SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field PWD_IR25LO18 */ +#define RXRF_BIAS1__PWD_IR25LO18__SHIFT 4 +#define RXRF_BIAS1__PWD_IR25LO18__WIDTH 3 +#define RXRF_BIAS1__PWD_IR25LO18__MASK 0x00000070U +#define RXRF_BIAS1__PWD_IR25LO18__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000070U) >> 4) +#define RXRF_BIAS1__PWD_IR25LO18__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define RXRF_BIAS1__PWD_IR25LO18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define RXRF_BIAS1__PWD_IR25LO18__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field PWD_IC25LO36 */ +#define RXRF_BIAS1__PWD_IC25LO36__SHIFT 7 +#define RXRF_BIAS1__PWD_IC25LO36__WIDTH 3 +#define RXRF_BIAS1__PWD_IC25LO36__MASK 0x00000380U +#define RXRF_BIAS1__PWD_IC25LO36__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000380U) >> 7) +#define RXRF_BIAS1__PWD_IC25LO36__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000380U) +#define RXRF_BIAS1__PWD_IC25LO36__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((u_int32_t)(src) <<\ + 7) & 0x00000380U) +#define RXRF_BIAS1__PWD_IC25LO36__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000380U))) + +/* macros for field PWD_IC25MXR2_5GH */ +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__SHIFT 10 +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__WIDTH 3 +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__MASK 0x00001c00U +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001c00U) >> 10) +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00001c00U) +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00001c00U) +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00001c00U))) + +/* macros for field PWD_IC25MXR5GH */ +#define RXRF_BIAS1__PWD_IC25MXR5GH__SHIFT 13 +#define RXRF_BIAS1__PWD_IC25MXR5GH__WIDTH 3 +#define RXRF_BIAS1__PWD_IC25MXR5GH__MASK 0x0000e000U +#define RXRF_BIAS1__PWD_IC25MXR5GH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000e000U) >> 13) +#define RXRF_BIAS1__PWD_IC25MXR5GH__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0000e000U) +#define RXRF_BIAS1__PWD_IC25MXR5GH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define RXRF_BIAS1__PWD_IC25MXR5GH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0000e000U))) + +/* macros for field PWD_IC25VGA5G */ +#define RXRF_BIAS1__PWD_IC25VGA5G__SHIFT 16 +#define RXRF_BIAS1__PWD_IC25VGA5G__WIDTH 3 +#define RXRF_BIAS1__PWD_IC25VGA5G__MASK 0x00070000U +#define RXRF_BIAS1__PWD_IC25VGA5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define RXRF_BIAS1__PWD_IC25VGA5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define RXRF_BIAS1__PWD_IC25VGA5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define RXRF_BIAS1__PWD_IC25VGA5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field PWD_IC75LNA5G */ +#define RXRF_BIAS1__PWD_IC75LNA5G__SHIFT 19 +#define RXRF_BIAS1__PWD_IC75LNA5G__WIDTH 3 +#define RXRF_BIAS1__PWD_IC75LNA5G__MASK 0x00380000U +#define RXRF_BIAS1__PWD_IC75LNA5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00380000U) >> 19) +#define RXRF_BIAS1__PWD_IC75LNA5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define RXRF_BIAS1__PWD_IC75LNA5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define RXRF_BIAS1__PWD_IC75LNA5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field PWD_IR25LO24 */ +#define RXRF_BIAS1__PWD_IR25LO24__SHIFT 22 +#define RXRF_BIAS1__PWD_IR25LO24__WIDTH 3 +#define RXRF_BIAS1__PWD_IR25LO24__MASK 0x01c00000U +#define RXRF_BIAS1__PWD_IR25LO24__READ(src) \ + (((u_int32_t)(src)\ + & 0x01c00000U) >> 22) +#define RXRF_BIAS1__PWD_IR25LO24__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x01c00000U) +#define RXRF_BIAS1__PWD_IR25LO24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x01c00000U) +#define RXRF_BIAS1__PWD_IR25LO24__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x01c00000U))) + +/* macros for field PWD_IC25MXR2GH */ +#define RXRF_BIAS1__PWD_IC25MXR2GH__SHIFT 25 +#define RXRF_BIAS1__PWD_IC25MXR2GH__WIDTH 3 +#define RXRF_BIAS1__PWD_IC25MXR2GH__MASK 0x0e000000U +#define RXRF_BIAS1__PWD_IC25MXR2GH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0e000000U) >> 25) +#define RXRF_BIAS1__PWD_IC25MXR2GH__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x0e000000U) +#define RXRF_BIAS1__PWD_IC25MXR2GH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x0e000000U) +#define RXRF_BIAS1__PWD_IC25MXR2GH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x0e000000U))) + +/* macros for field PWD_IC75LNA2G */ +#define RXRF_BIAS1__PWD_IC75LNA2G__SHIFT 28 +#define RXRF_BIAS1__PWD_IC75LNA2G__WIDTH 3 +#define RXRF_BIAS1__PWD_IC75LNA2G__MASK 0x70000000U +#define RXRF_BIAS1__PWD_IC75LNA2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x70000000U) >> 28) +#define RXRF_BIAS1__PWD_IC75LNA2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x70000000U) +#define RXRF_BIAS1__PWD_IC75LNA2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x70000000U) | (((u_int32_t)(src) <<\ + 28) & 0x70000000U) +#define RXRF_BIAS1__PWD_IC75LNA2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x70000000U))) + +/* macros for field PWD_BIAS */ +#define RXRF_BIAS1__PWD_BIAS__SHIFT 31 +#define RXRF_BIAS1__PWD_BIAS__WIDTH 1 +#define RXRF_BIAS1__PWD_BIAS__MASK 0x80000000U +#define RXRF_BIAS1__PWD_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RXRF_BIAS1__PWD_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RXRF_BIAS1__PWD_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RXRF_BIAS1__PWD_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RXRF_BIAS1__PWD_BIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RXRF_BIAS1__PWD_BIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RXRF_BIAS1__TYPE u_int32_t +#define RXRF_BIAS1__READ 0xffffffffU +#define RXRF_BIAS1__WRITE 0xffffffffU + +#endif /* __RXRF_BIAS1_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_RXRF_BIAS1 */ +#define INST_RADIO65_REG_BLOCK__CH0_RXRF_BIAS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXRF_BIAS2 */ +#ifndef __RXRF_BIAS2_MACRO__ +#define __RXRF_BIAS2_MACRO__ + +/* macros for field SPARE */ +#define RXRF_BIAS2__SPARE__SHIFT 0 +#define RXRF_BIAS2__SPARE__WIDTH 1 +#define RXRF_BIAS2__SPARE__MASK 0x00000001U +#define RXRF_BIAS2__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXRF_BIAS2__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXRF_BIAS2__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXRF_BIAS2__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define RXRF_BIAS2__SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXRF_BIAS2__SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PKEN */ +#define RXRF_BIAS2__PKEN__SHIFT 1 +#define RXRF_BIAS2__PKEN__WIDTH 3 +#define RXRF_BIAS2__PKEN__MASK 0x0000000eU +#define RXRF_BIAS2__PKEN__READ(src) (((u_int32_t)(src) & 0x0000000eU) >> 1) +#define RXRF_BIAS2__PKEN__WRITE(src) (((u_int32_t)(src) << 1) & 0x0000000eU) +#define RXRF_BIAS2__PKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define RXRF_BIAS2__PKEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field VCMVALUE */ +#define RXRF_BIAS2__VCMVALUE__SHIFT 4 +#define RXRF_BIAS2__VCMVALUE__WIDTH 3 +#define RXRF_BIAS2__VCMVALUE__MASK 0x00000070U +#define RXRF_BIAS2__VCMVALUE__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4) +#define RXRF_BIAS2__VCMVALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define RXRF_BIAS2__VCMVALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define RXRF_BIAS2__VCMVALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field PWD_VCMBUF */ +#define RXRF_BIAS2__PWD_VCMBUF__SHIFT 7 +#define RXRF_BIAS2__PWD_VCMBUF__WIDTH 1 +#define RXRF_BIAS2__PWD_VCMBUF__MASK 0x00000080U +#define RXRF_BIAS2__PWD_VCMBUF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RXRF_BIAS2__PWD_VCMBUF__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RXRF_BIAS2__PWD_VCMBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RXRF_BIAS2__PWD_VCMBUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RXRF_BIAS2__PWD_VCMBUF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RXRF_BIAS2__PWD_VCMBUF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field PWD_IR25SPAREH */ +#define RXRF_BIAS2__PWD_IR25SPAREH__SHIFT 8 +#define RXRF_BIAS2__PWD_IR25SPAREH__WIDTH 3 +#define RXRF_BIAS2__PWD_IR25SPAREH__MASK 0x00000700U +#define RXRF_BIAS2__PWD_IR25SPAREH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define RXRF_BIAS2__PWD_IR25SPAREH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define RXRF_BIAS2__PWD_IR25SPAREH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define RXRF_BIAS2__PWD_IR25SPAREH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field PWD_IR25SPARE */ +#define RXRF_BIAS2__PWD_IR25SPARE__SHIFT 11 +#define RXRF_BIAS2__PWD_IR25SPARE__WIDTH 3 +#define RXRF_BIAS2__PWD_IR25SPARE__MASK 0x00003800U +#define RXRF_BIAS2__PWD_IR25SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define RXRF_BIAS2__PWD_IR25SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define RXRF_BIAS2__PWD_IR25SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define RXRF_BIAS2__PWD_IR25SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field PWD_IC25LNABUF */ +#define RXRF_BIAS2__PWD_IC25LNABUF__SHIFT 14 +#define RXRF_BIAS2__PWD_IC25LNABUF__WIDTH 3 +#define RXRF_BIAS2__PWD_IC25LNABUF__MASK 0x0001c000U +#define RXRF_BIAS2__PWD_IC25LNABUF__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define RXRF_BIAS2__PWD_IC25LNABUF__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define RXRF_BIAS2__PWD_IC25LNABUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define RXRF_BIAS2__PWD_IC25LNABUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field PWD_IR25AGCH */ +#define RXRF_BIAS2__PWD_IR25AGCH__SHIFT 17 +#define RXRF_BIAS2__PWD_IR25AGCH__WIDTH 3 +#define RXRF_BIAS2__PWD_IR25AGCH__MASK 0x000e0000U +#define RXRF_BIAS2__PWD_IR25AGCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define RXRF_BIAS2__PWD_IR25AGCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define RXRF_BIAS2__PWD_IR25AGCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define RXRF_BIAS2__PWD_IR25AGCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field PWD_IR25AGC */ +#define RXRF_BIAS2__PWD_IR25AGC__SHIFT 20 +#define RXRF_BIAS2__PWD_IR25AGC__WIDTH 3 +#define RXRF_BIAS2__PWD_IR25AGC__MASK 0x00700000U +#define RXRF_BIAS2__PWD_IR25AGC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RXRF_BIAS2__PWD_IR25AGC__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RXRF_BIAS2__PWD_IR25AGC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RXRF_BIAS2__PWD_IR25AGC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field PWD_IC25AGC */ +#define RXRF_BIAS2__PWD_IC25AGC__SHIFT 23 +#define RXRF_BIAS2__PWD_IC25AGC__WIDTH 3 +#define RXRF_BIAS2__PWD_IC25AGC__MASK 0x03800000U +#define RXRF_BIAS2__PWD_IC25AGC__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RXRF_BIAS2__PWD_IC25AGC__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RXRF_BIAS2__PWD_IC25AGC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RXRF_BIAS2__PWD_IC25AGC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field PWD_IC25VCMBUF */ +#define RXRF_BIAS2__PWD_IC25VCMBUF__SHIFT 26 +#define RXRF_BIAS2__PWD_IC25VCMBUF__WIDTH 3 +#define RXRF_BIAS2__PWD_IC25VCMBUF__MASK 0x1c000000U +#define RXRF_BIAS2__PWD_IC25VCMBUF__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define RXRF_BIAS2__PWD_IC25VCMBUF__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define RXRF_BIAS2__PWD_IC25VCMBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RXRF_BIAS2__PWD_IC25VCMBUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field PWD_IR25VCM */ +#define RXRF_BIAS2__PWD_IR25VCM__SHIFT 29 +#define RXRF_BIAS2__PWD_IR25VCM__WIDTH 3 +#define RXRF_BIAS2__PWD_IR25VCM__MASK 0xe0000000U +#define RXRF_BIAS2__PWD_IR25VCM__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define RXRF_BIAS2__PWD_IR25VCM__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define RXRF_BIAS2__PWD_IR25VCM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RXRF_BIAS2__PWD_IR25VCM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RXRF_BIAS2__TYPE u_int32_t +#define RXRF_BIAS2__READ 0xffffffffU +#define RXRF_BIAS2__WRITE 0xffffffffU + +#endif /* __RXRF_BIAS2_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_RXRF_BIAS2 */ +#define INST_RADIO65_REG_BLOCK__CH0_RXRF_BIAS2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXRF_GAINSTAGES */ +#ifndef __RXRF_GAINSTAGES_MACRO__ +#define __RXRF_GAINSTAGES_MACRO__ + +/* macros for field SPARE */ +#define RXRF_GAINSTAGES__SPARE__SHIFT 0 +#define RXRF_GAINSTAGES__SPARE__WIDTH 1 +#define RXRF_GAINSTAGES__SPARE__MASK 0x00000001U +#define RXRF_GAINSTAGES__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXRF_GAINSTAGES__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXRF_GAINSTAGES__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXRF_GAINSTAGES__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RXRF_GAINSTAGES__SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXRF_GAINSTAGES__SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LNAON_CALDC */ +#define RXRF_GAINSTAGES__LNAON_CALDC__SHIFT 1 +#define RXRF_GAINSTAGES__LNAON_CALDC__WIDTH 1 +#define RXRF_GAINSTAGES__LNAON_CALDC__MASK 0x00000002U +#define RXRF_GAINSTAGES__LNAON_CALDC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RXRF_GAINSTAGES__LNAON_CALDC__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RXRF_GAINSTAGES__LNAON_CALDC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RXRF_GAINSTAGES__LNAON_CALDC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RXRF_GAINSTAGES__LNAON_CALDC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RXRF_GAINSTAGES__LNAON_CALDC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field VGA5G_CAP */ +#define RXRF_GAINSTAGES__VGA5G_CAP__SHIFT 2 +#define RXRF_GAINSTAGES__VGA5G_CAP__WIDTH 2 +#define RXRF_GAINSTAGES__VGA5G_CAP__MASK 0x0000000cU +#define RXRF_GAINSTAGES__VGA5G_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define RXRF_GAINSTAGES__VGA5G_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define RXRF_GAINSTAGES__VGA5G_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define RXRF_GAINSTAGES__VGA5G_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field LNA5G_CAP */ +#define RXRF_GAINSTAGES__LNA5G_CAP__SHIFT 4 +#define RXRF_GAINSTAGES__LNA5G_CAP__WIDTH 2 +#define RXRF_GAINSTAGES__LNA5G_CAP__MASK 0x00000030U +#define RXRF_GAINSTAGES__LNA5G_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define RXRF_GAINSTAGES__LNA5G_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define RXRF_GAINSTAGES__LNA5G_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define RXRF_GAINSTAGES__LNA5G_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field LNA5G_SHORTINP */ +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__SHIFT 6 +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__WIDTH 1 +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__MASK 0x00000040U +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field PWD_LO5G */ +#define RXRF_GAINSTAGES__PWD_LO5G__SHIFT 7 +#define RXRF_GAINSTAGES__PWD_LO5G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_LO5G__MASK 0x00000080U +#define RXRF_GAINSTAGES__PWD_LO5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RXRF_GAINSTAGES__PWD_LO5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RXRF_GAINSTAGES__PWD_LO5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RXRF_GAINSTAGES__PWD_LO5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RXRF_GAINSTAGES__PWD_LO5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RXRF_GAINSTAGES__PWD_LO5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field PWD_VGA5G */ +#define RXRF_GAINSTAGES__PWD_VGA5G__SHIFT 8 +#define RXRF_GAINSTAGES__PWD_VGA5G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_VGA5G__MASK 0x00000100U +#define RXRF_GAINSTAGES__PWD_VGA5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define RXRF_GAINSTAGES__PWD_VGA5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define RXRF_GAINSTAGES__PWD_VGA5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RXRF_GAINSTAGES__PWD_VGA5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RXRF_GAINSTAGES__PWD_VGA5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RXRF_GAINSTAGES__PWD_VGA5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field PWD_MXR5G */ +#define RXRF_GAINSTAGES__PWD_MXR5G__SHIFT 9 +#define RXRF_GAINSTAGES__PWD_MXR5G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_MXR5G__MASK 0x00000200U +#define RXRF_GAINSTAGES__PWD_MXR5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define RXRF_GAINSTAGES__PWD_MXR5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define RXRF_GAINSTAGES__PWD_MXR5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define RXRF_GAINSTAGES__PWD_MXR5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define RXRF_GAINSTAGES__PWD_MXR5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define RXRF_GAINSTAGES__PWD_MXR5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field PWD_LNA5G */ +#define RXRF_GAINSTAGES__PWD_LNA5G__SHIFT 10 +#define RXRF_GAINSTAGES__PWD_LNA5G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_LNA5G__MASK 0x00000400U +#define RXRF_GAINSTAGES__PWD_LNA5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define RXRF_GAINSTAGES__PWD_LNA5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define RXRF_GAINSTAGES__PWD_LNA5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RXRF_GAINSTAGES__PWD_LNA5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RXRF_GAINSTAGES__PWD_LNA5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RXRF_GAINSTAGES__PWD_LNA5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field LNA2G_CAP */ +#define RXRF_GAINSTAGES__LNA2G_CAP__SHIFT 11 +#define RXRF_GAINSTAGES__LNA2G_CAP__WIDTH 2 +#define RXRF_GAINSTAGES__LNA2G_CAP__MASK 0x00001800U +#define RXRF_GAINSTAGES__LNA2G_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001800U) >> 11) +#define RXRF_GAINSTAGES__LNA2G_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00001800U) +#define RXRF_GAINSTAGES__LNA2G_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define RXRF_GAINSTAGES__LNA2G_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field LNA2G_SHORTINP */ +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__SHIFT 13 +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__WIDTH 1 +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__MASK 0x00002000U +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field LNA2G_LP */ +#define RXRF_GAINSTAGES__LNA2G_LP__SHIFT 14 +#define RXRF_GAINSTAGES__LNA2G_LP__WIDTH 1 +#define RXRF_GAINSTAGES__LNA2G_LP__MASK 0x00004000U +#define RXRF_GAINSTAGES__LNA2G_LP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RXRF_GAINSTAGES__LNA2G_LP__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RXRF_GAINSTAGES__LNA2G_LP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RXRF_GAINSTAGES__LNA2G_LP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RXRF_GAINSTAGES__LNA2G_LP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RXRF_GAINSTAGES__LNA2G_LP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field PWD_LO2G */ +#define RXRF_GAINSTAGES__PWD_LO2G__SHIFT 15 +#define RXRF_GAINSTAGES__PWD_LO2G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_LO2G__MASK 0x00008000U +#define RXRF_GAINSTAGES__PWD_LO2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define RXRF_GAINSTAGES__PWD_LO2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define RXRF_GAINSTAGES__PWD_LO2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define RXRF_GAINSTAGES__PWD_LO2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define RXRF_GAINSTAGES__PWD_LO2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define RXRF_GAINSTAGES__PWD_LO2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field PWD_MXR2G */ +#define RXRF_GAINSTAGES__PWD_MXR2G__SHIFT 16 +#define RXRF_GAINSTAGES__PWD_MXR2G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_MXR2G__MASK 0x00010000U +#define RXRF_GAINSTAGES__PWD_MXR2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define RXRF_GAINSTAGES__PWD_MXR2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define RXRF_GAINSTAGES__PWD_MXR2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define RXRF_GAINSTAGES__PWD_MXR2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define RXRF_GAINSTAGES__PWD_MXR2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define RXRF_GAINSTAGES__PWD_MXR2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field PWD_LNA2G */ +#define RXRF_GAINSTAGES__PWD_LNA2G__SHIFT 17 +#define RXRF_GAINSTAGES__PWD_LNA2G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_LNA2G__MASK 0x00020000U +#define RXRF_GAINSTAGES__PWD_LNA2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define RXRF_GAINSTAGES__PWD_LNA2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define RXRF_GAINSTAGES__PWD_LNA2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RXRF_GAINSTAGES__PWD_LNA2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RXRF_GAINSTAGES__PWD_LNA2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RXRF_GAINSTAGES__PWD_LNA2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field MXR5G_GAIN_OVR */ +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__SHIFT 18 +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__WIDTH 2 +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__MASK 0x000c0000U +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x000c0000U) >> 18) +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field VGA5G_GAIN_OVR */ +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__SHIFT 20 +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__WIDTH 3 +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__MASK 0x00700000U +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field LNA5G_GAIN_OVR */ +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__SHIFT 23 +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__WIDTH 3 +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__MASK 0x03800000U +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field MXR2G_GAIN_OVR */ +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__SHIFT 26 +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__WIDTH 2 +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__MASK 0x0c000000U +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0c000000U) >> 26) +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x0c000000U) +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) + +/* macros for field LNA2G_GAIN_OVR */ +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__SHIFT 28 +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__WIDTH 3 +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__MASK 0x70000000U +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x70000000U) >> 28) +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x70000000U) +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x70000000U) | (((u_int32_t)(src) <<\ + 28) & 0x70000000U) +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x70000000U))) + +/* macros for field RX_OVERRIDE */ +#define RXRF_GAINSTAGES__RX_OVERRIDE__SHIFT 31 +#define RXRF_GAINSTAGES__RX_OVERRIDE__WIDTH 1 +#define RXRF_GAINSTAGES__RX_OVERRIDE__MASK 0x80000000U +#define RXRF_GAINSTAGES__RX_OVERRIDE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RXRF_GAINSTAGES__RX_OVERRIDE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RXRF_GAINSTAGES__RX_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RXRF_GAINSTAGES__RX_OVERRIDE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RXRF_GAINSTAGES__RX_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RXRF_GAINSTAGES__RX_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RXRF_GAINSTAGES__TYPE u_int32_t +#define RXRF_GAINSTAGES__READ 0xffffffffU +#define RXRF_GAINSTAGES__WRITE 0xffffffffU + +#endif /* __RXRF_GAINSTAGES_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_RXRF_GAINSTAGES */ +#define INST_RADIO65_REG_BLOCK__CH0_RXRF_GAINSTAGES__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXRF_AGC */ +#ifndef __RXRF_AGC_MACRO__ +#define __RXRF_AGC_MACRO__ + +/* macros for field RF5G_ON_DURING_CALPA */ +#define RXRF_AGC__RF5G_ON_DURING_CALPA__SHIFT 0 +#define RXRF_AGC__RF5G_ON_DURING_CALPA__WIDTH 1 +#define RXRF_AGC__RF5G_ON_DURING_CALPA__MASK 0x00000001U +#define RXRF_AGC__RF5G_ON_DURING_CALPA__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RXRF_AGC__RF5G_ON_DURING_CALPA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RXRF_AGC__RF5G_ON_DURING_CALPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXRF_AGC__RF5G_ON_DURING_CALPA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RXRF_AGC__RF5G_ON_DURING_CALPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXRF_AGC__RF5G_ON_DURING_CALPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RF2G_ON_DURING_CALPA */ +#define RXRF_AGC__RF2G_ON_DURING_CALPA__SHIFT 1 +#define RXRF_AGC__RF2G_ON_DURING_CALPA__WIDTH 1 +#define RXRF_AGC__RF2G_ON_DURING_CALPA__MASK 0x00000002U +#define RXRF_AGC__RF2G_ON_DURING_CALPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RXRF_AGC__RF2G_ON_DURING_CALPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RXRF_AGC__RF2G_ON_DURING_CALPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RXRF_AGC__RF2G_ON_DURING_CALPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RXRF_AGC__RF2G_ON_DURING_CALPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RXRF_AGC__RF2G_ON_DURING_CALPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field AGC_OUT */ +#define RXRF_AGC__AGC_OUT__SHIFT 2 +#define RXRF_AGC__AGC_OUT__WIDTH 1 +#define RXRF_AGC__AGC_OUT__MASK 0x00000004U +#define RXRF_AGC__AGC_OUT__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define RXRF_AGC__AGC_OUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RXRF_AGC__AGC_OUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field LNABUFGAIN2X */ +#define RXRF_AGC__LNABUFGAIN2X__SHIFT 3 +#define RXRF_AGC__LNABUFGAIN2X__WIDTH 1 +#define RXRF_AGC__LNABUFGAIN2X__MASK 0x00000008U +#define RXRF_AGC__LNABUFGAIN2X__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RXRF_AGC__LNABUFGAIN2X__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RXRF_AGC__LNABUFGAIN2X__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RXRF_AGC__LNABUFGAIN2X__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RXRF_AGC__LNABUFGAIN2X__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RXRF_AGC__LNABUFGAIN2X__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field LNABUF_PWD_OVR */ +#define RXRF_AGC__LNABUF_PWD_OVR__SHIFT 4 +#define RXRF_AGC__LNABUF_PWD_OVR__WIDTH 1 +#define RXRF_AGC__LNABUF_PWD_OVR__MASK 0x00000010U +#define RXRF_AGC__LNABUF_PWD_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RXRF_AGC__LNABUF_PWD_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RXRF_AGC__LNABUF_PWD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RXRF_AGC__LNABUF_PWD_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RXRF_AGC__LNABUF_PWD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RXRF_AGC__LNABUF_PWD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PWD_LNABUF */ +#define RXRF_AGC__PWD_LNABUF__SHIFT 5 +#define RXRF_AGC__PWD_LNABUF__WIDTH 1 +#define RXRF_AGC__PWD_LNABUF__MASK 0x00000020U +#define RXRF_AGC__PWD_LNABUF__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define RXRF_AGC__PWD_LNABUF__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RXRF_AGC__PWD_LNABUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RXRF_AGC__PWD_LNABUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RXRF_AGC__PWD_LNABUF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RXRF_AGC__PWD_LNABUF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field AGC_FALL_CTRL */ +#define RXRF_AGC__AGC_FALL_CTRL__SHIFT 6 +#define RXRF_AGC__AGC_FALL_CTRL__WIDTH 3 +#define RXRF_AGC__AGC_FALL_CTRL__MASK 0x000001c0U +#define RXRF_AGC__AGC_FALL_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001c0U) >> 6) +#define RXRF_AGC__AGC_FALL_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000001c0U) +#define RXRF_AGC__AGC_FALL_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define RXRF_AGC__AGC_FALL_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field AGC5G_CALDAC_OVR */ +#define RXRF_AGC__AGC5G_CALDAC_OVR__SHIFT 9 +#define RXRF_AGC__AGC5G_CALDAC_OVR__WIDTH 6 +#define RXRF_AGC__AGC5G_CALDAC_OVR__MASK 0x00007e00U +#define RXRF_AGC__AGC5G_CALDAC_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007e00U) >> 9) +#define RXRF_AGC__AGC5G_CALDAC_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00007e00U) +#define RXRF_AGC__AGC5G_CALDAC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00007e00U) +#define RXRF_AGC__AGC5G_CALDAC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00007e00U))) + +/* macros for field AGC5G_DBDAC_OVR */ +#define RXRF_AGC__AGC5G_DBDAC_OVR__SHIFT 15 +#define RXRF_AGC__AGC5G_DBDAC_OVR__WIDTH 4 +#define RXRF_AGC__AGC5G_DBDAC_OVR__MASK 0x00078000U +#define RXRF_AGC__AGC5G_DBDAC_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00078000U) >> 15) +#define RXRF_AGC__AGC5G_DBDAC_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00078000U) +#define RXRF_AGC__AGC5G_DBDAC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00078000U) | (((u_int32_t)(src) <<\ + 15) & 0x00078000U) +#define RXRF_AGC__AGC5G_DBDAC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00078000U))) + +/* macros for field AGC2G_CALDAC_OVR */ +#define RXRF_AGC__AGC2G_CALDAC_OVR__SHIFT 19 +#define RXRF_AGC__AGC2G_CALDAC_OVR__WIDTH 6 +#define RXRF_AGC__AGC2G_CALDAC_OVR__MASK 0x01f80000U +#define RXRF_AGC__AGC2G_CALDAC_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f80000U) >> 19) +#define RXRF_AGC__AGC2G_CALDAC_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x01f80000U) +#define RXRF_AGC__AGC2G_CALDAC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f80000U) | (((u_int32_t)(src) <<\ + 19) & 0x01f80000U) +#define RXRF_AGC__AGC2G_CALDAC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x01f80000U))) + +/* macros for field AGC2G_DBDAC_OVR */ +#define RXRF_AGC__AGC2G_DBDAC_OVR__SHIFT 25 +#define RXRF_AGC__AGC2G_DBDAC_OVR__WIDTH 4 +#define RXRF_AGC__AGC2G_DBDAC_OVR__MASK 0x1e000000U +#define RXRF_AGC__AGC2G_DBDAC_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x1e000000U) >> 25) +#define RXRF_AGC__AGC2G_DBDAC_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x1e000000U) +#define RXRF_AGC__AGC2G_DBDAC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x1e000000U) +#define RXRF_AGC__AGC2G_DBDAC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x1e000000U))) + +/* macros for field AGC_CAL_OVR */ +#define RXRF_AGC__AGC_CAL_OVR__SHIFT 29 +#define RXRF_AGC__AGC_CAL_OVR__WIDTH 1 +#define RXRF_AGC__AGC_CAL_OVR__MASK 0x20000000U +#define RXRF_AGC__AGC_CAL_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RXRF_AGC__AGC_CAL_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RXRF_AGC__AGC_CAL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RXRF_AGC__AGC_CAL_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RXRF_AGC__AGC_CAL_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RXRF_AGC__AGC_CAL_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field AGC_ON_OVR */ +#define RXRF_AGC__AGC_ON_OVR__SHIFT 30 +#define RXRF_AGC__AGC_ON_OVR__WIDTH 1 +#define RXRF_AGC__AGC_ON_OVR__MASK 0x40000000U +#define RXRF_AGC__AGC_ON_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RXRF_AGC__AGC_ON_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RXRF_AGC__AGC_ON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RXRF_AGC__AGC_ON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RXRF_AGC__AGC_ON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RXRF_AGC__AGC_ON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field AGC_OVERRIDE */ +#define RXRF_AGC__AGC_OVERRIDE__SHIFT 31 +#define RXRF_AGC__AGC_OVERRIDE__WIDTH 1 +#define RXRF_AGC__AGC_OVERRIDE__MASK 0x80000000U +#define RXRF_AGC__AGC_OVERRIDE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RXRF_AGC__AGC_OVERRIDE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RXRF_AGC__AGC_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RXRF_AGC__AGC_OVERRIDE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RXRF_AGC__AGC_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RXRF_AGC__AGC_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RXRF_AGC__TYPE u_int32_t +#define RXRF_AGC__READ 0xffffffffU +#define RXRF_AGC__WRITE 0xffffffffU + +#endif /* __RXRF_AGC_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_RXRF_AGC */ +#define INST_RADIO65_REG_BLOCK__CH0_RXRF_AGC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF1 */ +#ifndef __TXRF1_MACRO__ +#define __TXRF1_MACRO__ + +/* macros for field pdlobuf5G */ +#define TXRF1__PDLOBUF5G__SHIFT 0 +#define TXRF1__PDLOBUF5G__WIDTH 1 +#define TXRF1__PDLOBUF5G__MASK 0x00000001U +#define TXRF1__PDLOBUF5G__READ(src) (u_int32_t)(src) & 0x00000001U +#define TXRF1__PDLOBUF5G__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TXRF1__PDLOBUF5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TXRF1__PDLOBUF5G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TXRF1__PDLOBUF5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXRF1__PDLOBUF5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field pdlodiv5G */ +#define TXRF1__PDLODIV5G__SHIFT 1 +#define TXRF1__PDLODIV5G__WIDTH 1 +#define TXRF1__PDLODIV5G__MASK 0x00000002U +#define TXRF1__PDLODIV5G__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define TXRF1__PDLODIV5G__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define TXRF1__PDLODIV5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define TXRF1__PDLODIV5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define TXRF1__PDLODIV5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TXRF1__PDLODIV5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field LObuf5Gforced */ +#define TXRF1__LOBUF5GFORCED__SHIFT 2 +#define TXRF1__LOBUF5GFORCED__WIDTH 1 +#define TXRF1__LOBUF5GFORCED__MASK 0x00000004U +#define TXRF1__LOBUF5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define TXRF1__LOBUF5GFORCED__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define TXRF1__LOBUF5GFORCED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define TXRF1__LOBUF5GFORCED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define TXRF1__LOBUF5GFORCED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TXRF1__LOBUF5GFORCED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field LOdiv5Gforced */ +#define TXRF1__LODIV5GFORCED__SHIFT 3 +#define TXRF1__LODIV5GFORCED__WIDTH 1 +#define TXRF1__LODIV5GFORCED__MASK 0x00000008U +#define TXRF1__LODIV5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define TXRF1__LODIV5GFORCED__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define TXRF1__LODIV5GFORCED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TXRF1__LODIV5GFORCED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define TXRF1__LODIV5GFORCED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TXRF1__LODIV5GFORCED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field padrv2gn5G */ +#define TXRF1__PADRV2GN5G__SHIFT 4 +#define TXRF1__PADRV2GN5G__WIDTH 4 +#define TXRF1__PADRV2GN5G__MASK 0x000000f0U +#define TXRF1__PADRV2GN5G__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) +#define TXRF1__PADRV2GN5G__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) +#define TXRF1__PADRV2GN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define TXRF1__PADRV2GN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field padrv3gn5G */ +#define TXRF1__PADRV3GN5G__SHIFT 8 +#define TXRF1__PADRV3GN5G__WIDTH 4 +#define TXRF1__PADRV3GN5G__MASK 0x00000f00U +#define TXRF1__PADRV3GN5G__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) +#define TXRF1__PADRV3GN5G__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) +#define TXRF1__PADRV3GN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define TXRF1__PADRV3GN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field padrv4gn5G */ +#define TXRF1__PADRV4GN5G__SHIFT 12 +#define TXRF1__PADRV4GN5G__WIDTH 4 +#define TXRF1__PADRV4GN5G__MASK 0x0000f000U +#define TXRF1__PADRV4GN5G__READ(src) (((u_int32_t)(src) & 0x0000f000U) >> 12) +#define TXRF1__PADRV4GN5G__WRITE(src) (((u_int32_t)(src) << 12) & 0x0000f000U) +#define TXRF1__PADRV4GN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define TXRF1__PADRV4GN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field localtxgain5G */ +#define TXRF1__LOCALTXGAIN5G__SHIFT 16 +#define TXRF1__LOCALTXGAIN5G__WIDTH 1 +#define TXRF1__LOCALTXGAIN5G__MASK 0x00010000U +#define TXRF1__LOCALTXGAIN5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define TXRF1__LOCALTXGAIN5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define TXRF1__LOCALTXGAIN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define TXRF1__LOCALTXGAIN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define TXRF1__LOCALTXGAIN5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define TXRF1__LOCALTXGAIN5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field pdout2G */ +#define TXRF1__PDOUT2G__SHIFT 17 +#define TXRF1__PDOUT2G__WIDTH 1 +#define TXRF1__PDOUT2G__MASK 0x00020000U +#define TXRF1__PDOUT2G__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17) +#define TXRF1__PDOUT2G__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U) +#define TXRF1__PDOUT2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define TXRF1__PDOUT2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define TXRF1__PDOUT2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define TXRF1__PDOUT2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field pdDR2G */ +#define TXRF1__PDDR2G__SHIFT 18 +#define TXRF1__PDDR2G__WIDTH 1 +#define TXRF1__PDDR2G__MASK 0x00040000U +#define TXRF1__PDDR2G__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define TXRF1__PDDR2G__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define TXRF1__PDDR2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define TXRF1__PDDR2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define TXRF1__PDDR2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define TXRF1__PDDR2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field pdmxr2G */ +#define TXRF1__PDMXR2G__SHIFT 19 +#define TXRF1__PDMXR2G__WIDTH 1 +#define TXRF1__PDMXR2G__MASK 0x00080000U +#define TXRF1__PDMXR2G__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) +#define TXRF1__PDMXR2G__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) +#define TXRF1__PDMXR2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TXRF1__PDMXR2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TXRF1__PDMXR2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TXRF1__PDMXR2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field pdlobuf2G */ +#define TXRF1__PDLOBUF2G__SHIFT 20 +#define TXRF1__PDLOBUF2G__WIDTH 1 +#define TXRF1__PDLOBUF2G__MASK 0x00100000U +#define TXRF1__PDLOBUF2G__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define TXRF1__PDLOBUF2G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) +#define TXRF1__PDLOBUF2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TXRF1__PDLOBUF2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TXRF1__PDLOBUF2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TXRF1__PDLOBUF2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field pdlodiv2G */ +#define TXRF1__PDLODIV2G__SHIFT 21 +#define TXRF1__PDLODIV2G__WIDTH 1 +#define TXRF1__PDLODIV2G__MASK 0x00200000U +#define TXRF1__PDLODIV2G__READ(src) (((u_int32_t)(src) & 0x00200000U) >> 21) +#define TXRF1__PDLODIV2G__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U) +#define TXRF1__PDLODIV2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define TXRF1__PDLODIV2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define TXRF1__PDLODIV2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define TXRF1__PDLODIV2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field LObuf2Gforced */ +#define TXRF1__LOBUF2GFORCED__SHIFT 22 +#define TXRF1__LOBUF2GFORCED__WIDTH 1 +#define TXRF1__LOBUF2GFORCED__MASK 0x00400000U +#define TXRF1__LOBUF2GFORCED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define TXRF1__LOBUF2GFORCED__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define TXRF1__LOBUF2GFORCED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TXRF1__LOBUF2GFORCED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TXRF1__LOBUF2GFORCED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TXRF1__LOBUF2GFORCED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field LOdiv2Gforced */ +#define TXRF1__LODIV2GFORCED__SHIFT 23 +#define TXRF1__LODIV2GFORCED__WIDTH 1 +#define TXRF1__LODIV2GFORCED__MASK 0x00800000U +#define TXRF1__LODIV2GFORCED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TXRF1__LODIV2GFORCED__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TXRF1__LODIV2GFORCED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TXRF1__LODIV2GFORCED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TXRF1__LODIV2GFORCED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TXRF1__LODIV2GFORCED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field padrvgn2G */ +#define TXRF1__PADRVGN2G__SHIFT 24 +#define TXRF1__PADRVGN2G__WIDTH 7 +#define TXRF1__PADRVGN2G__MASK 0x7f000000U +#define TXRF1__PADRVGN2G__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24) +#define TXRF1__PADRVGN2G__WRITE(src) (((u_int32_t)(src) << 24) & 0x7f000000U) +#define TXRF1__PADRVGN2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define TXRF1__PADRVGN2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) + +/* macros for field localtxgain2G */ +#define TXRF1__LOCALTXGAIN2G__SHIFT 31 +#define TXRF1__LOCALTXGAIN2G__WIDTH 1 +#define TXRF1__LOCALTXGAIN2G__MASK 0x80000000U +#define TXRF1__LOCALTXGAIN2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TXRF1__LOCALTXGAIN2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TXRF1__LOCALTXGAIN2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TXRF1__LOCALTXGAIN2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TXRF1__LOCALTXGAIN2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TXRF1__LOCALTXGAIN2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TXRF1__TYPE u_int32_t +#define TXRF1__READ 0xffffffffU +#define TXRF1__WRITE 0xffffffffU + +#endif /* __TXRF1_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF1 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF2 */ +#ifndef __TXRF2_MACRO__ +#define __TXRF2_MACRO__ + +/* macros for field d3b5G */ +#define TXRF2__D3B5G__SHIFT 0 +#define TXRF2__D3B5G__WIDTH 3 +#define TXRF2__D3B5G__MASK 0x00000007U +#define TXRF2__D3B5G__READ(src) (u_int32_t)(src) & 0x00000007U +#define TXRF2__D3B5G__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define TXRF2__D3B5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define TXRF2__D3B5G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) + +/* macros for field d4b5G */ +#define TXRF2__D4B5G__SHIFT 3 +#define TXRF2__D4B5G__WIDTH 3 +#define TXRF2__D4B5G__MASK 0x00000038U +#define TXRF2__D4B5G__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3) +#define TXRF2__D4B5G__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000038U) +#define TXRF2__D4B5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define TXRF2__D4B5G__VERIFY(src) (!((((u_int32_t)(src) << 3) & ~0x00000038U))) + +/* macros for field ocas2G */ +#define TXRF2__OCAS2G__SHIFT 6 +#define TXRF2__OCAS2G__WIDTH 3 +#define TXRF2__OCAS2G__MASK 0x000001c0U +#define TXRF2__OCAS2G__READ(src) (((u_int32_t)(src) & 0x000001c0U) >> 6) +#define TXRF2__OCAS2G__WRITE(src) (((u_int32_t)(src) << 6) & 0x000001c0U) +#define TXRF2__OCAS2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define TXRF2__OCAS2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field dcas2G */ +#define TXRF2__DCAS2G__SHIFT 9 +#define TXRF2__DCAS2G__WIDTH 3 +#define TXRF2__DCAS2G__MASK 0x00000e00U +#define TXRF2__DCAS2G__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) +#define TXRF2__DCAS2G__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U) +#define TXRF2__DCAS2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define TXRF2__DCAS2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field ob2G_paloff */ +#define TXRF2__OB2G_PALOFF__SHIFT 12 +#define TXRF2__OB2G_PALOFF__WIDTH 3 +#define TXRF2__OB2G_PALOFF__MASK 0x00007000U +#define TXRF2__OB2G_PALOFF__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12) +#define TXRF2__OB2G_PALOFF__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U) +#define TXRF2__OB2G_PALOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define TXRF2__OB2G_PALOFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field ob2G_qam */ +#define TXRF2__OB2G_QAM__SHIFT 15 +#define TXRF2__OB2G_QAM__WIDTH 3 +#define TXRF2__OB2G_QAM__MASK 0x00038000U +#define TXRF2__OB2G_QAM__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) +#define TXRF2__OB2G_QAM__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) +#define TXRF2__OB2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define TXRF2__OB2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field ob2G_psk */ +#define TXRF2__OB2G_PSK__SHIFT 18 +#define TXRF2__OB2G_PSK__WIDTH 3 +#define TXRF2__OB2G_PSK__MASK 0x001c0000U +#define TXRF2__OB2G_PSK__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18) +#define TXRF2__OB2G_PSK__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U) +#define TXRF2__OB2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define TXRF2__OB2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field ob2G_cck */ +#define TXRF2__OB2G_CCK__SHIFT 21 +#define TXRF2__OB2G_CCK__WIDTH 3 +#define TXRF2__OB2G_CCK__MASK 0x00e00000U +#define TXRF2__OB2G_CCK__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21) +#define TXRF2__OB2G_CCK__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U) +#define TXRF2__OB2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define TXRF2__OB2G_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field db2G */ +#define TXRF2__DB2G__SHIFT 24 +#define TXRF2__DB2G__WIDTH 3 +#define TXRF2__DB2G__MASK 0x07000000U +#define TXRF2__DB2G__READ(src) (((u_int32_t)(src) & 0x07000000U) >> 24) +#define TXRF2__DB2G__WRITE(src) (((u_int32_t)(src) << 24) & 0x07000000U) +#define TXRF2__DB2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define TXRF2__DB2G__VERIFY(src) (!((((u_int32_t)(src) << 24) & ~0x07000000U))) + +/* macros for field pdout5G */ +#define TXRF2__PDOUT5G__SHIFT 27 +#define TXRF2__PDOUT5G__WIDTH 4 +#define TXRF2__PDOUT5G__MASK 0x78000000U +#define TXRF2__PDOUT5G__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define TXRF2__PDOUT5G__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define TXRF2__PDOUT5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define TXRF2__PDOUT5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) + +/* macros for field pdmxr5G */ +#define TXRF2__PDMXR5G__SHIFT 31 +#define TXRF2__PDMXR5G__WIDTH 1 +#define TXRF2__PDMXR5G__MASK 0x80000000U +#define TXRF2__PDMXR5G__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define TXRF2__PDMXR5G__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) +#define TXRF2__PDMXR5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TXRF2__PDMXR5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TXRF2__PDMXR5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TXRF2__PDMXR5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TXRF2__TYPE u_int32_t +#define TXRF2__READ 0xffffffffU +#define TXRF2__WRITE 0xffffffffU + +#endif /* __TXRF2_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF2 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF3 */ +#ifndef __TXRF3_MACRO__ +#define __TXRF3_MACRO__ + +/* macros for field filtR2G */ +#define TXRF3__FILTR2G__SHIFT 0 +#define TXRF3__FILTR2G__WIDTH 2 +#define TXRF3__FILTR2G__MASK 0x00000003U +#define TXRF3__FILTR2G__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXRF3__FILTR2G__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXRF3__FILTR2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXRF3__FILTR2G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field pwdFB2_2G */ +#define TXRF3__PWDFB2_2G__SHIFT 2 +#define TXRF3__PWDFB2_2G__WIDTH 1 +#define TXRF3__PWDFB2_2G__MASK 0x00000004U +#define TXRF3__PWDFB2_2G__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define TXRF3__PWDFB2_2G__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define TXRF3__PWDFB2_2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define TXRF3__PWDFB2_2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define TXRF3__PWDFB2_2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TXRF3__PWDFB2_2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field pwdFB1_2G */ +#define TXRF3__PWDFB1_2G__SHIFT 3 +#define TXRF3__PWDFB1_2G__WIDTH 1 +#define TXRF3__PWDFB1_2G__MASK 0x00000008U +#define TXRF3__PWDFB1_2G__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define TXRF3__PWDFB1_2G__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define TXRF3__PWDFB1_2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TXRF3__PWDFB1_2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define TXRF3__PWDFB1_2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TXRF3__PWDFB1_2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field pdFB2G */ +#define TXRF3__PDFB2G__SHIFT 4 +#define TXRF3__PDFB2G__WIDTH 1 +#define TXRF3__PDFB2G__MASK 0x00000010U +#define TXRF3__PDFB2G__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) +#define TXRF3__PDFB2G__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) +#define TXRF3__PDFB2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define TXRF3__PDFB2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define TXRF3__PDFB2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define TXRF3__PDFB2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field rdiv5G */ +#define TXRF3__RDIV5G__SHIFT 5 +#define TXRF3__RDIV5G__WIDTH 2 +#define TXRF3__RDIV5G__MASK 0x00000060U +#define TXRF3__RDIV5G__READ(src) (((u_int32_t)(src) & 0x00000060U) >> 5) +#define TXRF3__RDIV5G__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000060U) +#define TXRF3__RDIV5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((u_int32_t)(src) <<\ + 5) & 0x00000060U) +#define TXRF3__RDIV5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000060U))) + +/* macros for field capdiv5G */ +#define TXRF3__CAPDIV5G__SHIFT 7 +#define TXRF3__CAPDIV5G__WIDTH 3 +#define TXRF3__CAPDIV5G__MASK 0x00000380U +#define TXRF3__CAPDIV5G__READ(src) (((u_int32_t)(src) & 0x00000380U) >> 7) +#define TXRF3__CAPDIV5G__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000380U) +#define TXRF3__CAPDIV5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((u_int32_t)(src) <<\ + 7) & 0x00000380U) +#define TXRF3__CAPDIV5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000380U))) + +/* macros for field pdpredist5G */ +#define TXRF3__PDPREDIST5G__SHIFT 10 +#define TXRF3__PDPREDIST5G__WIDTH 1 +#define TXRF3__PDPREDIST5G__MASK 0x00000400U +#define TXRF3__PDPREDIST5G__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define TXRF3__PDPREDIST5G__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) +#define TXRF3__PDPREDIST5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TXRF3__PDPREDIST5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TXRF3__PDPREDIST5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TXRF3__PDPREDIST5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field rdiv2G */ +#define TXRF3__RDIV2G__SHIFT 11 +#define TXRF3__RDIV2G__WIDTH 2 +#define TXRF3__RDIV2G__MASK 0x00001800U +#define TXRF3__RDIV2G__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11) +#define TXRF3__RDIV2G__WRITE(src) (((u_int32_t)(src) << 11) & 0x00001800U) +#define TXRF3__RDIV2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define TXRF3__RDIV2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field pdpredist2G */ +#define TXRF3__PDPREDIST2G__SHIFT 13 +#define TXRF3__PDPREDIST2G__WIDTH 1 +#define TXRF3__PDPREDIST2G__MASK 0x00002000U +#define TXRF3__PDPREDIST2G__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) +#define TXRF3__PDPREDIST2G__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U) +#define TXRF3__PDPREDIST2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TXRF3__PDPREDIST2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TXRF3__PDPREDIST2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TXRF3__PDPREDIST2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field ocas5G */ +#define TXRF3__OCAS5G__SHIFT 14 +#define TXRF3__OCAS5G__WIDTH 3 +#define TXRF3__OCAS5G__MASK 0x0001c000U +#define TXRF3__OCAS5G__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) +#define TXRF3__OCAS5G__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U) +#define TXRF3__OCAS5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define TXRF3__OCAS5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field d2cas5G */ +#define TXRF3__D2CAS5G__SHIFT 17 +#define TXRF3__D2CAS5G__WIDTH 3 +#define TXRF3__D2CAS5G__MASK 0x000e0000U +#define TXRF3__D2CAS5G__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) +#define TXRF3__D2CAS5G__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) +#define TXRF3__D2CAS5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define TXRF3__D2CAS5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field d3cas5G */ +#define TXRF3__D3CAS5G__SHIFT 20 +#define TXRF3__D3CAS5G__WIDTH 3 +#define TXRF3__D3CAS5G__MASK 0x00700000U +#define TXRF3__D3CAS5G__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) +#define TXRF3__D3CAS5G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) +#define TXRF3__D3CAS5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define TXRF3__D3CAS5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field d4cas5G */ +#define TXRF3__D4CAS5G__SHIFT 23 +#define TXRF3__D4CAS5G__WIDTH 3 +#define TXRF3__D4CAS5G__MASK 0x03800000U +#define TXRF3__D4CAS5G__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) +#define TXRF3__D4CAS5G__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) +#define TXRF3__D4CAS5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define TXRF3__D4CAS5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field ob5G */ +#define TXRF3__OB5G__SHIFT 26 +#define TXRF3__OB5G__WIDTH 3 +#define TXRF3__OB5G__MASK 0x1c000000U +#define TXRF3__OB5G__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define TXRF3__OB5G__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define TXRF3__OB5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TXRF3__OB5G__VERIFY(src) (!((((u_int32_t)(src) << 26) & ~0x1c000000U))) + +/* macros for field d2b5G */ +#define TXRF3__D2B5G__SHIFT 29 +#define TXRF3__D2B5G__WIDTH 3 +#define TXRF3__D2B5G__MASK 0xe0000000U +#define TXRF3__D2B5G__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define TXRF3__D2B5G__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define TXRF3__D2B5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define TXRF3__D2B5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define TXRF3__TYPE u_int32_t +#define TXRF3__READ 0xffffffffU +#define TXRF3__WRITE 0xffffffffU + +#endif /* __TXRF3_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF3 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF4 */ +#ifndef __TXRF4_MACRO__ +#define __TXRF4_MACRO__ + +/* macros for field pk1b2G_cck */ +#define TXRF4__PK1B2G_CCK__SHIFT 0 +#define TXRF4__PK1B2G_CCK__WIDTH 2 +#define TXRF4__PK1B2G_CCK__MASK 0x00000003U +#define TXRF4__PK1B2G_CCK__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXRF4__PK1B2G_CCK__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXRF4__PK1B2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXRF4__PK1B2G_CCK__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field miob2G_qam */ +#define TXRF4__MIOB2G_QAM__SHIFT 2 +#define TXRF4__MIOB2G_QAM__WIDTH 3 +#define TXRF4__MIOB2G_QAM__MASK 0x0000001cU +#define TXRF4__MIOB2G_QAM__READ(src) (((u_int32_t)(src) & 0x0000001cU) >> 2) +#define TXRF4__MIOB2G_QAM__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000001cU) +#define TXRF4__MIOB2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define TXRF4__MIOB2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field miob2G_psk */ +#define TXRF4__MIOB2G_PSK__SHIFT 5 +#define TXRF4__MIOB2G_PSK__WIDTH 3 +#define TXRF4__MIOB2G_PSK__MASK 0x000000e0U +#define TXRF4__MIOB2G_PSK__READ(src) (((u_int32_t)(src) & 0x000000e0U) >> 5) +#define TXRF4__MIOB2G_PSK__WRITE(src) (((u_int32_t)(src) << 5) & 0x000000e0U) +#define TXRF4__MIOB2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define TXRF4__MIOB2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field miob2G_cck */ +#define TXRF4__MIOB2G_CCK__SHIFT 8 +#define TXRF4__MIOB2G_CCK__WIDTH 3 +#define TXRF4__MIOB2G_CCK__MASK 0x00000700U +#define TXRF4__MIOB2G_CCK__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) +#define TXRF4__MIOB2G_CCK__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U) +#define TXRF4__MIOB2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define TXRF4__MIOB2G_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field comp2G_qam */ +#define TXRF4__COMP2G_QAM__SHIFT 11 +#define TXRF4__COMP2G_QAM__WIDTH 3 +#define TXRF4__COMP2G_QAM__MASK 0x00003800U +#define TXRF4__COMP2G_QAM__READ(src) (((u_int32_t)(src) & 0x00003800U) >> 11) +#define TXRF4__COMP2G_QAM__WRITE(src) (((u_int32_t)(src) << 11) & 0x00003800U) +#define TXRF4__COMP2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define TXRF4__COMP2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field comp2G_psk */ +#define TXRF4__COMP2G_PSK__SHIFT 14 +#define TXRF4__COMP2G_PSK__WIDTH 3 +#define TXRF4__COMP2G_PSK__MASK 0x0001c000U +#define TXRF4__COMP2G_PSK__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) +#define TXRF4__COMP2G_PSK__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U) +#define TXRF4__COMP2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define TXRF4__COMP2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field comp2G_cck */ +#define TXRF4__COMP2G_CCK__SHIFT 17 +#define TXRF4__COMP2G_CCK__WIDTH 3 +#define TXRF4__COMP2G_CCK__MASK 0x000e0000U +#define TXRF4__COMP2G_CCK__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) +#define TXRF4__COMP2G_CCK__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) +#define TXRF4__COMP2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define TXRF4__COMP2G_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field amp2b2G_qam */ +#define TXRF4__AMP2B2G_QAM__SHIFT 20 +#define TXRF4__AMP2B2G_QAM__WIDTH 3 +#define TXRF4__AMP2B2G_QAM__MASK 0x00700000U +#define TXRF4__AMP2B2G_QAM__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) +#define TXRF4__AMP2B2G_QAM__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) +#define TXRF4__AMP2B2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define TXRF4__AMP2B2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field amp2b2G_psk */ +#define TXRF4__AMP2B2G_PSK__SHIFT 23 +#define TXRF4__AMP2B2G_PSK__WIDTH 3 +#define TXRF4__AMP2B2G_PSK__MASK 0x03800000U +#define TXRF4__AMP2B2G_PSK__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) +#define TXRF4__AMP2B2G_PSK__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) +#define TXRF4__AMP2B2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define TXRF4__AMP2B2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field amp2b2G_cck */ +#define TXRF4__AMP2B2G_CCK__SHIFT 26 +#define TXRF4__AMP2B2G_CCK__WIDTH 3 +#define TXRF4__AMP2B2G_CCK__MASK 0x1c000000U +#define TXRF4__AMP2B2G_CCK__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define TXRF4__AMP2B2G_CCK__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define TXRF4__AMP2B2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TXRF4__AMP2B2G_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field amp2cas2G */ +#define TXRF4__AMP2CAS2G__SHIFT 29 +#define TXRF4__AMP2CAS2G__WIDTH 3 +#define TXRF4__AMP2CAS2G__MASK 0xe0000000U +#define TXRF4__AMP2CAS2G__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define TXRF4__AMP2CAS2G__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define TXRF4__AMP2CAS2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define TXRF4__AMP2CAS2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define TXRF4__TYPE u_int32_t +#define TXRF4__READ 0xffffffffU +#define TXRF4__WRITE 0xffffffffU + +#endif /* __TXRF4_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF4 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF5 */ +#ifndef __TXRF5_MACRO__ +#define __TXRF5_MACRO__ + +/* macros for field txmodPALonly */ +#define TXRF5__TXMODPALONLY__SHIFT 0 +#define TXRF5__TXMODPALONLY__WIDTH 1 +#define TXRF5__TXMODPALONLY__MASK 0x00000001U +#define TXRF5__TXMODPALONLY__READ(src) (u_int32_t)(src) & 0x00000001U +#define TXRF5__TXMODPALONLY__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TXRF5__TXMODPALONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TXRF5__TXMODPALONLY__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TXRF5__TXMODPALONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXRF5__TXMODPALONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PAL_locked */ +#define TXRF5__PAL_LOCKED__SHIFT 1 +#define TXRF5__PAL_LOCKED__WIDTH 1 +#define TXRF5__PAL_LOCKED__MASK 0x00000002U +#define TXRF5__PAL_LOCKED__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define TXRF5__PAL_LOCKED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TXRF5__PAL_LOCKED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field fbHi2G */ +#define TXRF5__FBHI2G__SHIFT 2 +#define TXRF5__FBHI2G__WIDTH 1 +#define TXRF5__FBHI2G__MASK 0x00000004U +#define TXRF5__FBHI2G__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define TXRF5__FBHI2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TXRF5__FBHI2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field fbLo2G */ +#define TXRF5__FBLO2G__SHIFT 3 +#define TXRF5__FBLO2G__WIDTH 1 +#define TXRF5__FBLO2G__MASK 0x00000008U +#define TXRF5__FBLO2G__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define TXRF5__FBLO2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TXRF5__FBLO2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field nopalgain2G */ +#define TXRF5__NOPALGAIN2G__SHIFT 4 +#define TXRF5__NOPALGAIN2G__WIDTH 1 +#define TXRF5__NOPALGAIN2G__MASK 0x00000010U +#define TXRF5__NOPALGAIN2G__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) +#define TXRF5__NOPALGAIN2G__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) +#define TXRF5__NOPALGAIN2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define TXRF5__NOPALGAIN2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define TXRF5__NOPALGAIN2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define TXRF5__NOPALGAIN2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field enPAcal2G */ +#define TXRF5__ENPACAL2G__SHIFT 5 +#define TXRF5__ENPACAL2G__WIDTH 1 +#define TXRF5__ENPACAL2G__MASK 0x00000020U +#define TXRF5__ENPACAL2G__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define TXRF5__ENPACAL2G__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) +#define TXRF5__ENPACAL2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define TXRF5__ENPACAL2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define TXRF5__ENPACAL2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define TXRF5__ENPACAL2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field offset2G */ +#define TXRF5__OFFSET2G__SHIFT 6 +#define TXRF5__OFFSET2G__WIDTH 7 +#define TXRF5__OFFSET2G__MASK 0x00001fc0U +#define TXRF5__OFFSET2G__READ(src) (((u_int32_t)(src) & 0x00001fc0U) >> 6) +#define TXRF5__OFFSET2G__WRITE(src) (((u_int32_t)(src) << 6) & 0x00001fc0U) +#define TXRF5__OFFSET2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00001fc0U) +#define TXRF5__OFFSET2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00001fc0U))) + +/* macros for field enoffsetcal2G */ +#define TXRF5__ENOFFSETCAL2G__SHIFT 13 +#define TXRF5__ENOFFSETCAL2G__WIDTH 1 +#define TXRF5__ENOFFSETCAL2G__MASK 0x00002000U +#define TXRF5__ENOFFSETCAL2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define TXRF5__ENOFFSETCAL2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define TXRF5__ENOFFSETCAL2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TXRF5__ENOFFSETCAL2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TXRF5__ENOFFSETCAL2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TXRF5__ENOFFSETCAL2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field refHi2G */ +#define TXRF5__REFHI2G__SHIFT 14 +#define TXRF5__REFHI2G__WIDTH 3 +#define TXRF5__REFHI2G__MASK 0x0001c000U +#define TXRF5__REFHI2G__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) +#define TXRF5__REFHI2G__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U) +#define TXRF5__REFHI2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define TXRF5__REFHI2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field refLo2G */ +#define TXRF5__REFLO2G__SHIFT 17 +#define TXRF5__REFLO2G__WIDTH 3 +#define TXRF5__REFLO2G__MASK 0x000e0000U +#define TXRF5__REFLO2G__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) +#define TXRF5__REFLO2G__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) +#define TXRF5__REFLO2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define TXRF5__REFLO2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field palclamp2G */ +#define TXRF5__PALCLAMP2G__SHIFT 20 +#define TXRF5__PALCLAMP2G__WIDTH 2 +#define TXRF5__PALCLAMP2G__MASK 0x00300000U +#define TXRF5__PALCLAMP2G__READ(src) (((u_int32_t)(src) & 0x00300000U) >> 20) +#define TXRF5__PALCLAMP2G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00300000U) +#define TXRF5__PALCLAMP2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((u_int32_t)(src) <<\ + 20) & 0x00300000U) +#define TXRF5__PALCLAMP2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00300000U))) + +/* macros for field pk2b2G_qam */ +#define TXRF5__PK2B2G_QAM__SHIFT 22 +#define TXRF5__PK2B2G_QAM__WIDTH 2 +#define TXRF5__PK2B2G_QAM__MASK 0x00c00000U +#define TXRF5__PK2B2G_QAM__READ(src) (((u_int32_t)(src) & 0x00c00000U) >> 22) +#define TXRF5__PK2B2G_QAM__WRITE(src) (((u_int32_t)(src) << 22) & 0x00c00000U) +#define TXRF5__PK2B2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x00c00000U) +#define TXRF5__PK2B2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00c00000U))) + +/* macros for field pk2b2G_psk */ +#define TXRF5__PK2B2G_PSK__SHIFT 24 +#define TXRF5__PK2B2G_PSK__WIDTH 2 +#define TXRF5__PK2B2G_PSK__MASK 0x03000000U +#define TXRF5__PK2B2G_PSK__READ(src) (((u_int32_t)(src) & 0x03000000U) >> 24) +#define TXRF5__PK2B2G_PSK__WRITE(src) (((u_int32_t)(src) << 24) & 0x03000000U) +#define TXRF5__PK2B2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define TXRF5__PK2B2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field pk2b2G_cck */ +#define TXRF5__PK2B2G_CCK__SHIFT 26 +#define TXRF5__PK2B2G_CCK__WIDTH 2 +#define TXRF5__PK2B2G_CCK__MASK 0x0c000000U +#define TXRF5__PK2B2G_CCK__READ(src) (((u_int32_t)(src) & 0x0c000000U) >> 26) +#define TXRF5__PK2B2G_CCK__WRITE(src) (((u_int32_t)(src) << 26) & 0x0c000000U) +#define TXRF5__PK2B2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define TXRF5__PK2B2G_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) + +/* macros for field pk1b2G_qam */ +#define TXRF5__PK1B2G_QAM__SHIFT 28 +#define TXRF5__PK1B2G_QAM__WIDTH 2 +#define TXRF5__PK1B2G_QAM__MASK 0x30000000U +#define TXRF5__PK1B2G_QAM__READ(src) (((u_int32_t)(src) & 0x30000000U) >> 28) +#define TXRF5__PK1B2G_QAM__WRITE(src) (((u_int32_t)(src) << 28) & 0x30000000U) +#define TXRF5__PK1B2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define TXRF5__PK1B2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) + +/* macros for field pk1b2G_psk */ +#define TXRF5__PK1B2G_PSK__SHIFT 30 +#define TXRF5__PK1B2G_PSK__WIDTH 2 +#define TXRF5__PK1B2G_PSK__MASK 0xc0000000U +#define TXRF5__PK1B2G_PSK__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) +#define TXRF5__PK1B2G_PSK__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U) +#define TXRF5__PK1B2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define TXRF5__PK1B2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define TXRF5__TYPE u_int32_t +#define TXRF5__READ 0xffffffffU +#define TXRF5__WRITE 0xffffffffU + +#endif /* __TXRF5_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF5 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF6 */ +#ifndef __TXRF6_MACRO__ +#define __TXRF6_MACRO__ + +/* macros for field palclkgate2G */ +#define TXRF6__PALCLKGATE2G__SHIFT 0 +#define TXRF6__PALCLKGATE2G__WIDTH 1 +#define TXRF6__PALCLKGATE2G__MASK 0x00000001U +#define TXRF6__PALCLKGATE2G__READ(src) (u_int32_t)(src) & 0x00000001U +#define TXRF6__PALCLKGATE2G__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TXRF6__PALCLKGATE2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TXRF6__PALCLKGATE2G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TXRF6__PALCLKGATE2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXRF6__PALCLKGATE2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field palfluctcount2G */ +#define TXRF6__PALFLUCTCOUNT2G__SHIFT 1 +#define TXRF6__PALFLUCTCOUNT2G__WIDTH 8 +#define TXRF6__PALFLUCTCOUNT2G__MASK 0x000001feU +#define TXRF6__PALFLUCTCOUNT2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) +#define TXRF6__PALFLUCTCOUNT2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000001feU) +#define TXRF6__PALFLUCTCOUNT2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((u_int32_t)(src) <<\ + 1) & 0x000001feU) +#define TXRF6__PALFLUCTCOUNT2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000001feU))) + +/* macros for field palfluctgain2G */ +#define TXRF6__PALFLUCTGAIN2G__SHIFT 9 +#define TXRF6__PALFLUCTGAIN2G__WIDTH 2 +#define TXRF6__PALFLUCTGAIN2G__MASK 0x00000600U +#define TXRF6__PALFLUCTGAIN2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000600U) >> 9) +#define TXRF6__PALFLUCTGAIN2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000600U) +#define TXRF6__PALFLUCTGAIN2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000600U) | (((u_int32_t)(src) <<\ + 9) & 0x00000600U) +#define TXRF6__PALFLUCTGAIN2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000600U))) + +/* macros for field palnofluct2G */ +#define TXRF6__PALNOFLUCT2G__SHIFT 11 +#define TXRF6__PALNOFLUCT2G__WIDTH 1 +#define TXRF6__PALNOFLUCT2G__MASK 0x00000800U +#define TXRF6__PALNOFLUCT2G__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define TXRF6__PALNOFLUCT2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define TXRF6__PALNOFLUCT2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define TXRF6__PALNOFLUCT2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define TXRF6__PALNOFLUCT2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define TXRF6__PALNOFLUCT2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field gainstep2G */ +#define TXRF6__GAINSTEP2G__SHIFT 12 +#define TXRF6__GAINSTEP2G__WIDTH 3 +#define TXRF6__GAINSTEP2G__MASK 0x00007000U +#define TXRF6__GAINSTEP2G__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12) +#define TXRF6__GAINSTEP2G__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U) +#define TXRF6__GAINSTEP2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define TXRF6__GAINSTEP2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field use_gain_delta2G */ +#define TXRF6__USE_GAIN_DELTA2G__SHIFT 15 +#define TXRF6__USE_GAIN_DELTA2G__WIDTH 1 +#define TXRF6__USE_GAIN_DELTA2G__MASK 0x00008000U +#define TXRF6__USE_GAIN_DELTA2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TXRF6__USE_GAIN_DELTA2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TXRF6__USE_GAIN_DELTA2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TXRF6__USE_GAIN_DELTA2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TXRF6__USE_GAIN_DELTA2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TXRF6__USE_GAIN_DELTA2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field capdiv_I2G */ +#define TXRF6__CAPDIV_I2G__SHIFT 16 +#define TXRF6__CAPDIV_I2G__WIDTH 4 +#define TXRF6__CAPDIV_I2G__MASK 0x000f0000U +#define TXRF6__CAPDIV_I2G__READ(src) (((u_int32_t)(src) & 0x000f0000U) >> 16) +#define TXRF6__CAPDIV_I2G__WRITE(src) (((u_int32_t)(src) << 16) & 0x000f0000U) +#define TXRF6__CAPDIV_I2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define TXRF6__CAPDIV_I2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field padrvgn_index_I2G */ +#define TXRF6__PADRVGN_INDEX_I2G__SHIFT 20 +#define TXRF6__PADRVGN_INDEX_I2G__WIDTH 4 +#define TXRF6__PADRVGN_INDEX_I2G__MASK 0x00f00000U +#define TXRF6__PADRVGN_INDEX_I2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define TXRF6__PADRVGN_INDEX_I2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define TXRF6__PADRVGN_INDEX_I2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define TXRF6__PADRVGN_INDEX_I2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) + +/* macros for field vcmondelay2G */ +#define TXRF6__VCMONDELAY2G__SHIFT 24 +#define TXRF6__VCMONDELAY2G__WIDTH 3 +#define TXRF6__VCMONDELAY2G__MASK 0x07000000U +#define TXRF6__VCMONDELAY2G__READ(src) (((u_int32_t)(src) & 0x07000000U) >> 24) +#define TXRF6__VCMONDELAY2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x07000000U) +#define TXRF6__VCMONDELAY2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define TXRF6__VCMONDELAY2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x07000000U))) + +/* macros for field capdiv2G */ +#define TXRF6__CAPDIV2G__SHIFT 27 +#define TXRF6__CAPDIV2G__WIDTH 4 +#define TXRF6__CAPDIV2G__MASK 0x78000000U +#define TXRF6__CAPDIV2G__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define TXRF6__CAPDIV2G__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define TXRF6__CAPDIV2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define TXRF6__CAPDIV2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) + +/* macros for field capdiv2Govr */ +#define TXRF6__CAPDIV2GOVR__SHIFT 31 +#define TXRF6__CAPDIV2GOVR__WIDTH 1 +#define TXRF6__CAPDIV2GOVR__MASK 0x80000000U +#define TXRF6__CAPDIV2GOVR__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define TXRF6__CAPDIV2GOVR__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) +#define TXRF6__CAPDIV2GOVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TXRF6__CAPDIV2GOVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TXRF6__CAPDIV2GOVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TXRF6__CAPDIV2GOVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TXRF6__TYPE u_int32_t +#define TXRF6__READ 0xffffffffU +#define TXRF6__WRITE 0xffffffffU + +#endif /* __TXRF6_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF6 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF7 */ +#ifndef __TXRF7_MACRO__ +#define __TXRF7_MACRO__ + +/* macros for field spare7 */ +#define TXRF7__SPARE7__SHIFT 0 +#define TXRF7__SPARE7__WIDTH 2 +#define TXRF7__SPARE7__MASK 0x00000003U +#define TXRF7__SPARE7__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXRF7__SPARE7__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXRF7__SPARE7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXRF7__SPARE7__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field padrvgntab_4 */ +#define TXRF7__PADRVGNTAB_4__SHIFT 2 +#define TXRF7__PADRVGNTAB_4__WIDTH 6 +#define TXRF7__PADRVGNTAB_4__MASK 0x000000fcU +#define TXRF7__PADRVGNTAB_4__READ(src) (((u_int32_t)(src) & 0x000000fcU) >> 2) +#define TXRF7__PADRVGNTAB_4__WRITE(src) (((u_int32_t)(src) << 2) & 0x000000fcU) +#define TXRF7__PADRVGNTAB_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000fcU) | (((u_int32_t)(src) <<\ + 2) & 0x000000fcU) +#define TXRF7__PADRVGNTAB_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x000000fcU))) + +/* macros for field padrvgntab_3 */ +#define TXRF7__PADRVGNTAB_3__SHIFT 8 +#define TXRF7__PADRVGNTAB_3__WIDTH 6 +#define TXRF7__PADRVGNTAB_3__MASK 0x00003f00U +#define TXRF7__PADRVGNTAB_3__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8) +#define TXRF7__PADRVGNTAB_3__WRITE(src) (((u_int32_t)(src) << 8) & 0x00003f00U) +#define TXRF7__PADRVGNTAB_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define TXRF7__PADRVGNTAB_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field padrvgntab_2 */ +#define TXRF7__PADRVGNTAB_2__SHIFT 14 +#define TXRF7__PADRVGNTAB_2__WIDTH 6 +#define TXRF7__PADRVGNTAB_2__MASK 0x000fc000U +#define TXRF7__PADRVGNTAB_2__READ(src) (((u_int32_t)(src) & 0x000fc000U) >> 14) +#define TXRF7__PADRVGNTAB_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x000fc000U) +#define TXRF7__PADRVGNTAB_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x000fc000U) +#define TXRF7__PADRVGNTAB_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x000fc000U))) + +/* macros for field padrvgntab_1 */ +#define TXRF7__PADRVGNTAB_1__SHIFT 20 +#define TXRF7__PADRVGNTAB_1__WIDTH 6 +#define TXRF7__PADRVGNTAB_1__MASK 0x03f00000U +#define TXRF7__PADRVGNTAB_1__READ(src) (((u_int32_t)(src) & 0x03f00000U) >> 20) +#define TXRF7__PADRVGNTAB_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x03f00000U) +#define TXRF7__PADRVGNTAB_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x03f00000U) +#define TXRF7__PADRVGNTAB_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x03f00000U))) + +/* macros for field padrvgntab_0 */ +#define TXRF7__PADRVGNTAB_0__SHIFT 26 +#define TXRF7__PADRVGNTAB_0__WIDTH 6 +#define TXRF7__PADRVGNTAB_0__MASK 0xfc000000U +#define TXRF7__PADRVGNTAB_0__READ(src) (((u_int32_t)(src) & 0xfc000000U) >> 26) +#define TXRF7__PADRVGNTAB_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0xfc000000U) +#define TXRF7__PADRVGNTAB_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((u_int32_t)(src) <<\ + 26) & 0xfc000000U) +#define TXRF7__PADRVGNTAB_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0xfc000000U))) +#define TXRF7__TYPE u_int32_t +#define TXRF7__READ 0xffffffffU +#define TXRF7__WRITE 0xffffffffU + +#endif /* __TXRF7_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF7 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF8 */ +#ifndef __TXRF8_MACRO__ +#define __TXRF8_MACRO__ + +/* macros for field spare8 */ +#define TXRF8__SPARE8__SHIFT 0 +#define TXRF8__SPARE8__WIDTH 2 +#define TXRF8__SPARE8__MASK 0x00000003U +#define TXRF8__SPARE8__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXRF8__SPARE8__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXRF8__SPARE8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXRF8__SPARE8__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field padrvgntab_9 */ +#define TXRF8__PADRVGNTAB_9__SHIFT 2 +#define TXRF8__PADRVGNTAB_9__WIDTH 6 +#define TXRF8__PADRVGNTAB_9__MASK 0x000000fcU +#define TXRF8__PADRVGNTAB_9__READ(src) (((u_int32_t)(src) & 0x000000fcU) >> 2) +#define TXRF8__PADRVGNTAB_9__WRITE(src) (((u_int32_t)(src) << 2) & 0x000000fcU) +#define TXRF8__PADRVGNTAB_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000fcU) | (((u_int32_t)(src) <<\ + 2) & 0x000000fcU) +#define TXRF8__PADRVGNTAB_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x000000fcU))) + +/* macros for field padrvgntab_8 */ +#define TXRF8__PADRVGNTAB_8__SHIFT 8 +#define TXRF8__PADRVGNTAB_8__WIDTH 6 +#define TXRF8__PADRVGNTAB_8__MASK 0x00003f00U +#define TXRF8__PADRVGNTAB_8__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8) +#define TXRF8__PADRVGNTAB_8__WRITE(src) (((u_int32_t)(src) << 8) & 0x00003f00U) +#define TXRF8__PADRVGNTAB_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define TXRF8__PADRVGNTAB_8__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field padrvgntab_7 */ +#define TXRF8__PADRVGNTAB_7__SHIFT 14 +#define TXRF8__PADRVGNTAB_7__WIDTH 6 +#define TXRF8__PADRVGNTAB_7__MASK 0x000fc000U +#define TXRF8__PADRVGNTAB_7__READ(src) (((u_int32_t)(src) & 0x000fc000U) >> 14) +#define TXRF8__PADRVGNTAB_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x000fc000U) +#define TXRF8__PADRVGNTAB_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x000fc000U) +#define TXRF8__PADRVGNTAB_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x000fc000U))) + +/* macros for field padrvgntab_6 */ +#define TXRF8__PADRVGNTAB_6__SHIFT 20 +#define TXRF8__PADRVGNTAB_6__WIDTH 6 +#define TXRF8__PADRVGNTAB_6__MASK 0x03f00000U +#define TXRF8__PADRVGNTAB_6__READ(src) (((u_int32_t)(src) & 0x03f00000U) >> 20) +#define TXRF8__PADRVGNTAB_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x03f00000U) +#define TXRF8__PADRVGNTAB_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x03f00000U) +#define TXRF8__PADRVGNTAB_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x03f00000U))) + +/* macros for field padrvgntab_5 */ +#define TXRF8__PADRVGNTAB_5__SHIFT 26 +#define TXRF8__PADRVGNTAB_5__WIDTH 6 +#define TXRF8__PADRVGNTAB_5__MASK 0xfc000000U +#define TXRF8__PADRVGNTAB_5__READ(src) (((u_int32_t)(src) & 0xfc000000U) >> 26) +#define TXRF8__PADRVGNTAB_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0xfc000000U) +#define TXRF8__PADRVGNTAB_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((u_int32_t)(src) <<\ + 26) & 0xfc000000U) +#define TXRF8__PADRVGNTAB_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0xfc000000U))) +#define TXRF8__TYPE u_int32_t +#define TXRF8__READ 0xffffffffU +#define TXRF8__WRITE 0xffffffffU + +#endif /* __TXRF8_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF8 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF9 */ +#ifndef __TXRF9_MACRO__ +#define __TXRF9_MACRO__ + +/* macros for field spare9 */ +#define TXRF9__SPARE9__SHIFT 0 +#define TXRF9__SPARE9__WIDTH 2 +#define TXRF9__SPARE9__MASK 0x00000003U +#define TXRF9__SPARE9__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXRF9__SPARE9__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXRF9__SPARE9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXRF9__SPARE9__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field padrvgntab_14 */ +#define TXRF9__PADRVGNTAB_14__SHIFT 2 +#define TXRF9__PADRVGNTAB_14__WIDTH 6 +#define TXRF9__PADRVGNTAB_14__MASK 0x000000fcU +#define TXRF9__PADRVGNTAB_14__READ(src) (((u_int32_t)(src) & 0x000000fcU) >> 2) +#define TXRF9__PADRVGNTAB_14__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x000000fcU) +#define TXRF9__PADRVGNTAB_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000fcU) | (((u_int32_t)(src) <<\ + 2) & 0x000000fcU) +#define TXRF9__PADRVGNTAB_14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x000000fcU))) + +/* macros for field padrvgntab_13 */ +#define TXRF9__PADRVGNTAB_13__SHIFT 8 +#define TXRF9__PADRVGNTAB_13__WIDTH 6 +#define TXRF9__PADRVGNTAB_13__MASK 0x00003f00U +#define TXRF9__PADRVGNTAB_13__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8) +#define TXRF9__PADRVGNTAB_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define TXRF9__PADRVGNTAB_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define TXRF9__PADRVGNTAB_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field padrvgntab_12 */ +#define TXRF9__PADRVGNTAB_12__SHIFT 14 +#define TXRF9__PADRVGNTAB_12__WIDTH 6 +#define TXRF9__PADRVGNTAB_12__MASK 0x000fc000U +#define TXRF9__PADRVGNTAB_12__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) +#define TXRF9__PADRVGNTAB_12__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x000fc000U) +#define TXRF9__PADRVGNTAB_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x000fc000U) +#define TXRF9__PADRVGNTAB_12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x000fc000U))) + +/* macros for field padrvgntab_11 */ +#define TXRF9__PADRVGNTAB_11__SHIFT 20 +#define TXRF9__PADRVGNTAB_11__WIDTH 6 +#define TXRF9__PADRVGNTAB_11__MASK 0x03f00000U +#define TXRF9__PADRVGNTAB_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x03f00000U) >> 20) +#define TXRF9__PADRVGNTAB_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x03f00000U) +#define TXRF9__PADRVGNTAB_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x03f00000U) +#define TXRF9__PADRVGNTAB_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x03f00000U))) + +/* macros for field padrvgntab_10 */ +#define TXRF9__PADRVGNTAB_10__SHIFT 26 +#define TXRF9__PADRVGNTAB_10__WIDTH 6 +#define TXRF9__PADRVGNTAB_10__MASK 0xfc000000U +#define TXRF9__PADRVGNTAB_10__READ(src) \ + (((u_int32_t)(src)\ + & 0xfc000000U) >> 26) +#define TXRF9__PADRVGNTAB_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0xfc000000U) +#define TXRF9__PADRVGNTAB_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((u_int32_t)(src) <<\ + 26) & 0xfc000000U) +#define TXRF9__PADRVGNTAB_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0xfc000000U))) +#define TXRF9__TYPE u_int32_t +#define TXRF9__READ 0xffffffffU +#define TXRF9__WRITE 0xffffffffU + +#endif /* __TXRF9_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF9 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF10 */ +#ifndef __TXRF10_MACRO__ +#define __TXRF10_MACRO__ + +/* macros for field spare10 */ +#define TXRF10__SPARE10__SHIFT 0 +#define TXRF10__SPARE10__WIDTH 3 +#define TXRF10__SPARE10__MASK 0x00000007U +#define TXRF10__SPARE10__READ(src) (u_int32_t)(src) & 0x00000007U +#define TXRF10__SPARE10__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define TXRF10__SPARE10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define TXRF10__SPARE10__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) + +/* macros for field pdout5G_3caltx */ +#define TXRF10__PDOUT5G_3CALTX__SHIFT 3 +#define TXRF10__PDOUT5G_3CALTX__WIDTH 1 +#define TXRF10__PDOUT5G_3CALTX__MASK 0x00000008U +#define TXRF10__PDOUT5G_3CALTX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define TXRF10__PDOUT5G_3CALTX__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define TXRF10__PDOUT5G_3CALTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TXRF10__PDOUT5G_3CALTX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define TXRF10__PDOUT5G_3CALTX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TXRF10__PDOUT5G_3CALTX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field d3b5Gcaltx */ +#define TXRF10__D3B5GCALTX__SHIFT 4 +#define TXRF10__D3B5GCALTX__WIDTH 3 +#define TXRF10__D3B5GCALTX__MASK 0x00000070U +#define TXRF10__D3B5GCALTX__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4) +#define TXRF10__D3B5GCALTX__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000070U) +#define TXRF10__D3B5GCALTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define TXRF10__D3B5GCALTX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field d4b5Gcaltx */ +#define TXRF10__D4B5GCALTX__SHIFT 7 +#define TXRF10__D4B5GCALTX__WIDTH 3 +#define TXRF10__D4B5GCALTX__MASK 0x00000380U +#define TXRF10__D4B5GCALTX__READ(src) (((u_int32_t)(src) & 0x00000380U) >> 7) +#define TXRF10__D4B5GCALTX__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000380U) +#define TXRF10__D4B5GCALTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((u_int32_t)(src) <<\ + 7) & 0x00000380U) +#define TXRF10__D4B5GCALTX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000380U))) + +/* macros for field padrvgn2Gcaltx */ +#define TXRF10__PADRVGN2GCALTX__SHIFT 10 +#define TXRF10__PADRVGN2GCALTX__WIDTH 7 +#define TXRF10__PADRVGN2GCALTX__MASK 0x0001fc00U +#define TXRF10__PADRVGN2GCALTX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fc00U) >> 10) +#define TXRF10__PADRVGN2GCALTX__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0001fc00U) +#define TXRF10__PADRVGN2GCALTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0001fc00U) +#define TXRF10__PADRVGN2GCALTX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0001fc00U))) + +/* macros for field db2Gcaltx */ +#define TXRF10__DB2GCALTX__SHIFT 17 +#define TXRF10__DB2GCALTX__WIDTH 3 +#define TXRF10__DB2GCALTX__MASK 0x000e0000U +#define TXRF10__DB2GCALTX__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) +#define TXRF10__DB2GCALTX__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) +#define TXRF10__DB2GCALTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define TXRF10__DB2GCALTX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field caltxshift */ +#define TXRF10__CALTXSHIFT__SHIFT 20 +#define TXRF10__CALTXSHIFT__WIDTH 1 +#define TXRF10__CALTXSHIFT__MASK 0x00100000U +#define TXRF10__CALTXSHIFT__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define TXRF10__CALTXSHIFT__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) +#define TXRF10__CALTXSHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TXRF10__CALTXSHIFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TXRF10__CALTXSHIFT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TXRF10__CALTXSHIFT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field caltxshiftovr */ +#define TXRF10__CALTXSHIFTOVR__SHIFT 21 +#define TXRF10__CALTXSHIFTOVR__WIDTH 1 +#define TXRF10__CALTXSHIFTOVR__MASK 0x00200000U +#define TXRF10__CALTXSHIFTOVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define TXRF10__CALTXSHIFTOVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define TXRF10__CALTXSHIFTOVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define TXRF10__CALTXSHIFTOVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define TXRF10__CALTXSHIFTOVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define TXRF10__CALTXSHIFTOVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field padrvgn2G_smout */ +#define TXRF10__PADRVGN2G_SMOUT__SHIFT 22 +#define TXRF10__PADRVGN2G_SMOUT__WIDTH 6 +#define TXRF10__PADRVGN2G_SMOUT__MASK 0x0fc00000U +#define TXRF10__PADRVGN2G_SMOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fc00000U) >> 22) + +/* macros for field padrvgn_index2G_smout */ +#define TXRF10__PADRVGN_INDEX2G_SMOUT__SHIFT 28 +#define TXRF10__PADRVGN_INDEX2G_SMOUT__WIDTH 4 +#define TXRF10__PADRVGN_INDEX2G_SMOUT__MASK 0xf0000000U +#define TXRF10__PADRVGN_INDEX2G_SMOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0xf0000000U) >> 28) +#define TXRF10__TYPE u_int32_t +#define TXRF10__READ 0xffffffffU +#define TXRF10__WRITE 0xffffffffU + +#endif /* __TXRF10_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF10 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF11 */ +#ifndef __TXRF11_MACRO__ +#define __TXRF11_MACRO__ + +/* macros for field spare11 */ +#define TXRF11__SPARE11__SHIFT 0 +#define TXRF11__SPARE11__WIDTH 2 +#define TXRF11__SPARE11__MASK 0x00000003U +#define TXRF11__SPARE11__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXRF11__SPARE11__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXRF11__SPARE11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXRF11__SPARE11__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field pwd_ir25mixdiv5G */ +#define TXRF11__PWD_IR25MIXDIV5G__SHIFT 2 +#define TXRF11__PWD_IR25MIXDIV5G__WIDTH 3 +#define TXRF11__PWD_IR25MIXDIV5G__MASK 0x0000001cU +#define TXRF11__PWD_IR25MIXDIV5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define TXRF11__PWD_IR25MIXDIV5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define TXRF11__PWD_IR25MIXDIV5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define TXRF11__PWD_IR25MIXDIV5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field pwd_ir25pa2G */ +#define TXRF11__PWD_IR25PA2G__SHIFT 5 +#define TXRF11__PWD_IR25PA2G__WIDTH 3 +#define TXRF11__PWD_IR25PA2G__MASK 0x000000e0U +#define TXRF11__PWD_IR25PA2G__READ(src) (((u_int32_t)(src) & 0x000000e0U) >> 5) +#define TXRF11__PWD_IR25PA2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define TXRF11__PWD_IR25PA2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define TXRF11__PWD_IR25PA2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field pwd_ir25mixbias2G */ +#define TXRF11__PWD_IR25MIXBIAS2G__SHIFT 8 +#define TXRF11__PWD_IR25MIXBIAS2G__WIDTH 3 +#define TXRF11__PWD_IR25MIXBIAS2G__MASK 0x00000700U +#define TXRF11__PWD_IR25MIXBIAS2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define TXRF11__PWD_IR25MIXBIAS2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define TXRF11__PWD_IR25MIXBIAS2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define TXRF11__PWD_IR25MIXBIAS2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field pwd_ir25mixdiv2G */ +#define TXRF11__PWD_IR25MIXDIV2G__SHIFT 11 +#define TXRF11__PWD_IR25MIXDIV2G__WIDTH 3 +#define TXRF11__PWD_IR25MIXDIV2G__MASK 0x00003800U +#define TXRF11__PWD_IR25MIXDIV2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define TXRF11__PWD_IR25MIXDIV2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define TXRF11__PWD_IR25MIXDIV2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define TXRF11__PWD_IR25MIXDIV2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field pwd_icspare */ +#define TXRF11__PWD_ICSPARE__SHIFT 14 +#define TXRF11__PWD_ICSPARE__WIDTH 3 +#define TXRF11__PWD_ICSPARE__MASK 0x0001c000U +#define TXRF11__PWD_ICSPARE__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) +#define TXRF11__PWD_ICSPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define TXRF11__PWD_ICSPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define TXRF11__PWD_ICSPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field pwd_ic25tempsen */ +#define TXRF11__PWD_IC25TEMPSEN__SHIFT 17 +#define TXRF11__PWD_IC25TEMPSEN__WIDTH 3 +#define TXRF11__PWD_IC25TEMPSEN__MASK 0x000e0000U +#define TXRF11__PWD_IC25TEMPSEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define TXRF11__PWD_IC25TEMPSEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define TXRF11__PWD_IC25TEMPSEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define TXRF11__PWD_IC25TEMPSEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field pwd_ic25pa5G2 */ +#define TXRF11__PWD_IC25PA5G2__SHIFT 20 +#define TXRF11__PWD_IC25PA5G2__WIDTH 3 +#define TXRF11__PWD_IC25PA5G2__MASK 0x00700000U +#define TXRF11__PWD_IC25PA5G2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define TXRF11__PWD_IC25PA5G2__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define TXRF11__PWD_IC25PA5G2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define TXRF11__PWD_IC25PA5G2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field pwd_ic25pa5G1 */ +#define TXRF11__PWD_IC25PA5G1__SHIFT 23 +#define TXRF11__PWD_IC25PA5G1__WIDTH 3 +#define TXRF11__PWD_IC25PA5G1__MASK 0x03800000U +#define TXRF11__PWD_IC25PA5G1__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define TXRF11__PWD_IC25PA5G1__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define TXRF11__PWD_IC25PA5G1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define TXRF11__PWD_IC25PA5G1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field pwd_ic25mixbuf5G */ +#define TXRF11__PWD_IC25MIXBUF5G__SHIFT 26 +#define TXRF11__PWD_IC25MIXBUF5G__WIDTH 3 +#define TXRF11__PWD_IC25MIXBUF5G__MASK 0x1c000000U +#define TXRF11__PWD_IC25MIXBUF5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define TXRF11__PWD_IC25MIXBUF5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define TXRF11__PWD_IC25MIXBUF5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TXRF11__PWD_IC25MIXBUF5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field pwd_ic25pa2G */ +#define TXRF11__PWD_IC25PA2G__SHIFT 29 +#define TXRF11__PWD_IC25PA2G__WIDTH 3 +#define TXRF11__PWD_IC25PA2G__MASK 0xe0000000U +#define TXRF11__PWD_IC25PA2G__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define TXRF11__PWD_IC25PA2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define TXRF11__PWD_IC25PA2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define TXRF11__PWD_IC25PA2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define TXRF11__TYPE u_int32_t +#define TXRF11__READ 0xffffffffU +#define TXRF11__WRITE 0xffffffffU + +#endif /* __TXRF11_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF11 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF12 */ +#ifndef __TXRF12_MACRO__ +#define __TXRF12_MACRO__ + +/* macros for field spare12_2 */ +#define TXRF12__SPARE12_2__SHIFT 0 +#define TXRF12__SPARE12_2__WIDTH 8 +#define TXRF12__SPARE12_2__MASK 0x000000ffU +#define TXRF12__SPARE12_2__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field spare12_1 */ +#define TXRF12__SPARE12_1__SHIFT 8 +#define TXRF12__SPARE12_1__WIDTH 2 +#define TXRF12__SPARE12_1__MASK 0x00000300U +#define TXRF12__SPARE12_1__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8) +#define TXRF12__SPARE12_1__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000300U) +#define TXRF12__SPARE12_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define TXRF12__SPARE12_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field ATBsel5G */ +#define TXRF12__ATBSEL5G__SHIFT 10 +#define TXRF12__ATBSEL5G__WIDTH 4 +#define TXRF12__ATBSEL5G__MASK 0x00003c00U +#define TXRF12__ATBSEL5G__READ(src) (((u_int32_t)(src) & 0x00003c00U) >> 10) +#define TXRF12__ATBSEL5G__WRITE(src) (((u_int32_t)(src) << 10) & 0x00003c00U) +#define TXRF12__ATBSEL5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00003c00U) +#define TXRF12__ATBSEL5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00003c00U))) + +/* macros for field ATBsel2G */ +#define TXRF12__ATBSEL2G__SHIFT 14 +#define TXRF12__ATBSEL2G__WIDTH 3 +#define TXRF12__ATBSEL2G__MASK 0x0001c000U +#define TXRF12__ATBSEL2G__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) +#define TXRF12__ATBSEL2G__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U) +#define TXRF12__ATBSEL2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define TXRF12__ATBSEL2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field pwd_irspare */ +#define TXRF12__PWD_IRSPARE__SHIFT 17 +#define TXRF12__PWD_IRSPARE__WIDTH 3 +#define TXRF12__PWD_IRSPARE__MASK 0x000e0000U +#define TXRF12__PWD_IRSPARE__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) +#define TXRF12__PWD_IRSPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define TXRF12__PWD_IRSPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define TXRF12__PWD_IRSPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field pwd_ir25tempsen */ +#define TXRF12__PWD_IR25TEMPSEN__SHIFT 20 +#define TXRF12__PWD_IR25TEMPSEN__WIDTH 3 +#define TXRF12__PWD_IR25TEMPSEN__MASK 0x00700000U +#define TXRF12__PWD_IR25TEMPSEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define TXRF12__PWD_IR25TEMPSEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define TXRF12__PWD_IR25TEMPSEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define TXRF12__PWD_IR25TEMPSEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field pwd_ir25pa5G2 */ +#define TXRF12__PWD_IR25PA5G2__SHIFT 23 +#define TXRF12__PWD_IR25PA5G2__WIDTH 3 +#define TXRF12__PWD_IR25PA5G2__MASK 0x03800000U +#define TXRF12__PWD_IR25PA5G2__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define TXRF12__PWD_IR25PA5G2__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define TXRF12__PWD_IR25PA5G2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define TXRF12__PWD_IR25PA5G2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field pwd_ir25pa5G1 */ +#define TXRF12__PWD_IR25PA5G1__SHIFT 26 +#define TXRF12__PWD_IR25PA5G1__WIDTH 3 +#define TXRF12__PWD_IR25PA5G1__MASK 0x1c000000U +#define TXRF12__PWD_IR25PA5G1__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define TXRF12__PWD_IR25PA5G1__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define TXRF12__PWD_IR25PA5G1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TXRF12__PWD_IR25PA5G1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field pwd_ir25mixbias5G */ +#define TXRF12__PWD_IR25MIXBIAS5G__SHIFT 29 +#define TXRF12__PWD_IR25MIXBIAS5G__WIDTH 3 +#define TXRF12__PWD_IR25MIXBIAS5G__MASK 0xe0000000U +#define TXRF12__PWD_IR25MIXBIAS5G__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define TXRF12__PWD_IR25MIXBIAS5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define TXRF12__PWD_IR25MIXBIAS5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define TXRF12__PWD_IR25MIXBIAS5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define TXRF12__TYPE u_int32_t +#define TXRF12__READ 0xffffffffU +#define TXRF12__WRITE 0xffffffffU + +#endif /* __TXRF12_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TXRF12 */ +#define INST_RADIO65_REG_BLOCK__CH0_TXRF12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH1 */ +#ifndef __SYNTH1_MACRO__ +#define __SYNTH1_MACRO__ + +/* macros for field SEL_VCMONABUS */ +#define SYNTH1__SEL_VCMONABUS__SHIFT 0 +#define SYNTH1__SEL_VCMONABUS__WIDTH 3 +#define SYNTH1__SEL_VCMONABUS__MASK 0x00000007U +#define SYNTH1__SEL_VCMONABUS__READ(src) (u_int32_t)(src) & 0x00000007U +#define SYNTH1__SEL_VCMONABUS__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define SYNTH1__SEL_VCMONABUS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define SYNTH1__SEL_VCMONABUS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field SEL_VCOABUS */ +#define SYNTH1__SEL_VCOABUS__SHIFT 3 +#define SYNTH1__SEL_VCOABUS__WIDTH 3 +#define SYNTH1__SEL_VCOABUS__MASK 0x00000038U +#define SYNTH1__SEL_VCOABUS__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3) +#define SYNTH1__SEL_VCOABUS__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000038U) +#define SYNTH1__SEL_VCOABUS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define SYNTH1__SEL_VCOABUS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field MONITOR_SYNTHLOCKVCOK */ +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__SHIFT 6 +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__WIDTH 1 +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__MASK 0x00000040U +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field MONITOR_VC2LOW */ +#define SYNTH1__MONITOR_VC2LOW__SHIFT 7 +#define SYNTH1__MONITOR_VC2LOW__WIDTH 1 +#define SYNTH1__MONITOR_VC2LOW__MASK 0x00000080U +#define SYNTH1__MONITOR_VC2LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define SYNTH1__MONITOR_VC2LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define SYNTH1__MONITOR_VC2LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define SYNTH1__MONITOR_VC2LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define SYNTH1__MONITOR_VC2LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define SYNTH1__MONITOR_VC2LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field MONITOR_VC2HIGH */ +#define SYNTH1__MONITOR_VC2HIGH__SHIFT 8 +#define SYNTH1__MONITOR_VC2HIGH__WIDTH 1 +#define SYNTH1__MONITOR_VC2HIGH__MASK 0x00000100U +#define SYNTH1__MONITOR_VC2HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define SYNTH1__MONITOR_VC2HIGH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define SYNTH1__MONITOR_VC2HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define SYNTH1__MONITOR_VC2HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define SYNTH1__MONITOR_VC2HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define SYNTH1__MONITOR_VC2HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field MONITOR_FB_DIV2 */ +#define SYNTH1__MONITOR_FB_DIV2__SHIFT 9 +#define SYNTH1__MONITOR_FB_DIV2__WIDTH 1 +#define SYNTH1__MONITOR_FB_DIV2__MASK 0x00000200U +#define SYNTH1__MONITOR_FB_DIV2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define SYNTH1__MONITOR_FB_DIV2__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define SYNTH1__MONITOR_FB_DIV2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define SYNTH1__MONITOR_FB_DIV2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define SYNTH1__MONITOR_FB_DIV2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define SYNTH1__MONITOR_FB_DIV2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field MONITOR_REF */ +#define SYNTH1__MONITOR_REF__SHIFT 10 +#define SYNTH1__MONITOR_REF__WIDTH 1 +#define SYNTH1__MONITOR_REF__MASK 0x00000400U +#define SYNTH1__MONITOR_REF__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define SYNTH1__MONITOR_REF__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define SYNTH1__MONITOR_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define SYNTH1__MONITOR_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define SYNTH1__MONITOR_REF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define SYNTH1__MONITOR_REF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field MONITOR_FB */ +#define SYNTH1__MONITOR_FB__SHIFT 11 +#define SYNTH1__MONITOR_FB__WIDTH 1 +#define SYNTH1__MONITOR_FB__MASK 0x00000800U +#define SYNTH1__MONITOR_FB__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define SYNTH1__MONITOR_FB__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define SYNTH1__MONITOR_FB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define SYNTH1__MONITOR_FB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define SYNTH1__MONITOR_FB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define SYNTH1__MONITOR_FB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field SEVENBITVCOCAP */ +#define SYNTH1__SEVENBITVCOCAP__SHIFT 12 +#define SYNTH1__SEVENBITVCOCAP__WIDTH 1 +#define SYNTH1__SEVENBITVCOCAP__MASK 0x00001000U +#define SYNTH1__SEVENBITVCOCAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define SYNTH1__SEVENBITVCOCAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define SYNTH1__SEVENBITVCOCAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define SYNTH1__SEVENBITVCOCAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define SYNTH1__SEVENBITVCOCAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define SYNTH1__SEVENBITVCOCAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field PWUP_PD */ +#define SYNTH1__PWUP_PD__SHIFT 13 +#define SYNTH1__PWUP_PD__WIDTH 3 +#define SYNTH1__PWUP_PD__MASK 0x0000e000U +#define SYNTH1__PWUP_PD__READ(src) (((u_int32_t)(src) & 0x0000e000U) >> 13) +#define SYNTH1__PWUP_PD__WRITE(src) (((u_int32_t)(src) << 13) & 0x0000e000U) +#define SYNTH1__PWUP_PD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define SYNTH1__PWUP_PD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0000e000U))) + +/* macros for field PWD_VCOBUF */ +#define SYNTH1__PWD_VCOBUF__SHIFT 16 +#define SYNTH1__PWD_VCOBUF__WIDTH 1 +#define SYNTH1__PWD_VCOBUF__MASK 0x00010000U +#define SYNTH1__PWD_VCOBUF__READ(src) (((u_int32_t)(src) & 0x00010000U) >> 16) +#define SYNTH1__PWD_VCOBUF__WRITE(src) (((u_int32_t)(src) << 16) & 0x00010000U) +#define SYNTH1__PWD_VCOBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define SYNTH1__PWD_VCOBUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define SYNTH1__PWD_VCOBUF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define SYNTH1__PWD_VCOBUF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field VCOBUFGAIN */ +#define SYNTH1__VCOBUFGAIN__SHIFT 17 +#define SYNTH1__VCOBUFGAIN__WIDTH 2 +#define SYNTH1__VCOBUFGAIN__MASK 0x00060000U +#define SYNTH1__VCOBUFGAIN__READ(src) (((u_int32_t)(src) & 0x00060000U) >> 17) +#define SYNTH1__VCOBUFGAIN__WRITE(src) (((u_int32_t)(src) << 17) & 0x00060000U) +#define SYNTH1__VCOBUFGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((u_int32_t)(src) <<\ + 17) & 0x00060000U) +#define SYNTH1__VCOBUFGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00060000U))) + +/* macros for field VCOREGLEVEL */ +#define SYNTH1__VCOREGLEVEL__SHIFT 19 +#define SYNTH1__VCOREGLEVEL__WIDTH 2 +#define SYNTH1__VCOREGLEVEL__MASK 0x00180000U +#define SYNTH1__VCOREGLEVEL__READ(src) (((u_int32_t)(src) & 0x00180000U) >> 19) +#define SYNTH1__VCOREGLEVEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00180000U) +#define SYNTH1__VCOREGLEVEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((u_int32_t)(src) <<\ + 19) & 0x00180000U) +#define SYNTH1__VCOREGLEVEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00180000U))) + +/* macros for field VCOREGBYPASS */ +#define SYNTH1__VCOREGBYPASS__SHIFT 21 +#define SYNTH1__VCOREGBYPASS__WIDTH 1 +#define SYNTH1__VCOREGBYPASS__MASK 0x00200000U +#define SYNTH1__VCOREGBYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define SYNTH1__VCOREGBYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define SYNTH1__VCOREGBYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define SYNTH1__VCOREGBYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define SYNTH1__VCOREGBYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define SYNTH1__VCOREGBYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field PWUP_LOREF */ +#define SYNTH1__PWUP_LOREF__SHIFT 22 +#define SYNTH1__PWUP_LOREF__WIDTH 1 +#define SYNTH1__PWUP_LOREF__MASK 0x00400000U +#define SYNTH1__PWUP_LOREF__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22) +#define SYNTH1__PWUP_LOREF__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U) +#define SYNTH1__PWUP_LOREF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define SYNTH1__PWUP_LOREF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define SYNTH1__PWUP_LOREF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define SYNTH1__PWUP_LOREF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field PWD_LOMIX */ +#define SYNTH1__PWD_LOMIX__SHIFT 23 +#define SYNTH1__PWD_LOMIX__WIDTH 1 +#define SYNTH1__PWD_LOMIX__MASK 0x00800000U +#define SYNTH1__PWD_LOMIX__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) +#define SYNTH1__PWD_LOMIX__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) +#define SYNTH1__PWD_LOMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define SYNTH1__PWD_LOMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define SYNTH1__PWD_LOMIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define SYNTH1__PWD_LOMIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field PWD_LODIV */ +#define SYNTH1__PWD_LODIV__SHIFT 24 +#define SYNTH1__PWD_LODIV__WIDTH 1 +#define SYNTH1__PWD_LODIV__MASK 0x01000000U +#define SYNTH1__PWD_LODIV__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define SYNTH1__PWD_LODIV__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U) +#define SYNTH1__PWD_LODIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define SYNTH1__PWD_LODIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define SYNTH1__PWD_LODIV__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define SYNTH1__PWD_LODIV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field PWD_LOBUF5G */ +#define SYNTH1__PWD_LOBUF5G__SHIFT 25 +#define SYNTH1__PWD_LOBUF5G__WIDTH 1 +#define SYNTH1__PWD_LOBUF5G__MASK 0x02000000U +#define SYNTH1__PWD_LOBUF5G__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) +#define SYNTH1__PWD_LOBUF5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define SYNTH1__PWD_LOBUF5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define SYNTH1__PWD_LOBUF5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define SYNTH1__PWD_LOBUF5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define SYNTH1__PWD_LOBUF5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field PWD_LOBUF2G */ +#define SYNTH1__PWD_LOBUF2G__SHIFT 26 +#define SYNTH1__PWD_LOBUF2G__WIDTH 1 +#define SYNTH1__PWD_LOBUF2G__MASK 0x04000000U +#define SYNTH1__PWD_LOBUF2G__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) +#define SYNTH1__PWD_LOBUF2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define SYNTH1__PWD_LOBUF2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define SYNTH1__PWD_LOBUF2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define SYNTH1__PWD_LOBUF2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define SYNTH1__PWD_LOBUF2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field PWD_PRESC */ +#define SYNTH1__PWD_PRESC__SHIFT 27 +#define SYNTH1__PWD_PRESC__WIDTH 1 +#define SYNTH1__PWD_PRESC__MASK 0x08000000U +#define SYNTH1__PWD_PRESC__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) +#define SYNTH1__PWD_PRESC__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U) +#define SYNTH1__PWD_PRESC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define SYNTH1__PWD_PRESC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define SYNTH1__PWD_PRESC__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define SYNTH1__PWD_PRESC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field PWD_VCO */ +#define SYNTH1__PWD_VCO__SHIFT 28 +#define SYNTH1__PWD_VCO__WIDTH 1 +#define SYNTH1__PWD_VCO__MASK 0x10000000U +#define SYNTH1__PWD_VCO__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define SYNTH1__PWD_VCO__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define SYNTH1__PWD_VCO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define SYNTH1__PWD_VCO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define SYNTH1__PWD_VCO__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define SYNTH1__PWD_VCO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PWD_VCMON */ +#define SYNTH1__PWD_VCMON__SHIFT 29 +#define SYNTH1__PWD_VCMON__WIDTH 1 +#define SYNTH1__PWD_VCMON__MASK 0x20000000U +#define SYNTH1__PWD_VCMON__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define SYNTH1__PWD_VCMON__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define SYNTH1__PWD_VCMON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define SYNTH1__PWD_VCMON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define SYNTH1__PWD_VCMON__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define SYNTH1__PWD_VCMON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PWD_CP */ +#define SYNTH1__PWD_CP__SHIFT 30 +#define SYNTH1__PWD_CP__WIDTH 1 +#define SYNTH1__PWD_CP__MASK 0x40000000U +#define SYNTH1__PWD_CP__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define SYNTH1__PWD_CP__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define SYNTH1__PWD_CP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SYNTH1__PWD_CP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SYNTH1__PWD_CP__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SYNTH1__PWD_CP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PWD_BIAS */ +#define SYNTH1__PWD_BIAS__SHIFT 31 +#define SYNTH1__PWD_BIAS__WIDTH 1 +#define SYNTH1__PWD_BIAS__MASK 0x80000000U +#define SYNTH1__PWD_BIAS__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define SYNTH1__PWD_BIAS__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) +#define SYNTH1__PWD_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SYNTH1__PWD_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SYNTH1__PWD_BIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH1__PWD_BIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH1__TYPE u_int32_t +#define SYNTH1__READ 0xffffffffU +#define SYNTH1__WRITE 0xffffffffU + +#endif /* __SYNTH1_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH1 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH2 */ +#ifndef __SYNTH2_MACRO__ +#define __SYNTH2_MACRO__ + +/* macros for field CAPRANGE3 */ +#define SYNTH2__CAPRANGE3__SHIFT 0 +#define SYNTH2__CAPRANGE3__WIDTH 4 +#define SYNTH2__CAPRANGE3__MASK 0x0000000fU +#define SYNTH2__CAPRANGE3__READ(src) (u_int32_t)(src) & 0x0000000fU +#define SYNTH2__CAPRANGE3__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define SYNTH2__CAPRANGE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define SYNTH2__CAPRANGE3__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) + +/* macros for field CAPRANGE2 */ +#define SYNTH2__CAPRANGE2__SHIFT 4 +#define SYNTH2__CAPRANGE2__WIDTH 4 +#define SYNTH2__CAPRANGE2__MASK 0x000000f0U +#define SYNTH2__CAPRANGE2__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) +#define SYNTH2__CAPRANGE2__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) +#define SYNTH2__CAPRANGE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SYNTH2__CAPRANGE2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field CAPRANGE1 */ +#define SYNTH2__CAPRANGE1__SHIFT 8 +#define SYNTH2__CAPRANGE1__WIDTH 4 +#define SYNTH2__CAPRANGE1__MASK 0x00000f00U +#define SYNTH2__CAPRANGE1__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) +#define SYNTH2__CAPRANGE1__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) +#define SYNTH2__CAPRANGE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SYNTH2__CAPRANGE1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field LOOPLEAKCUR_INTN */ +#define SYNTH2__LOOPLEAKCUR_INTN__SHIFT 12 +#define SYNTH2__LOOPLEAKCUR_INTN__WIDTH 4 +#define SYNTH2__LOOPLEAKCUR_INTN__MASK 0x0000f000U +#define SYNTH2__LOOPLEAKCUR_INTN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define SYNTH2__LOOPLEAKCUR_INTN__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define SYNTH2__LOOPLEAKCUR_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define SYNTH2__LOOPLEAKCUR_INTN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field CPLOWLK_INTN */ +#define SYNTH2__CPLOWLK_INTN__SHIFT 16 +#define SYNTH2__CPLOWLK_INTN__WIDTH 1 +#define SYNTH2__CPLOWLK_INTN__MASK 0x00010000U +#define SYNTH2__CPLOWLK_INTN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define SYNTH2__CPLOWLK_INTN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define SYNTH2__CPLOWLK_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define SYNTH2__CPLOWLK_INTN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define SYNTH2__CPLOWLK_INTN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define SYNTH2__CPLOWLK_INTN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field CPSTEERING_EN_INTN */ +#define SYNTH2__CPSTEERING_EN_INTN__SHIFT 17 +#define SYNTH2__CPSTEERING_EN_INTN__WIDTH 1 +#define SYNTH2__CPSTEERING_EN_INTN__MASK 0x00020000U +#define SYNTH2__CPSTEERING_EN_INTN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define SYNTH2__CPSTEERING_EN_INTN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define SYNTH2__CPSTEERING_EN_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define SYNTH2__CPSTEERING_EN_INTN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define SYNTH2__CPSTEERING_EN_INTN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define SYNTH2__CPSTEERING_EN_INTN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field CPBIAS_INTN */ +#define SYNTH2__CPBIAS_INTN__SHIFT 18 +#define SYNTH2__CPBIAS_INTN__WIDTH 2 +#define SYNTH2__CPBIAS_INTN__MASK 0x000c0000U +#define SYNTH2__CPBIAS_INTN__READ(src) (((u_int32_t)(src) & 0x000c0000U) >> 18) +#define SYNTH2__CPBIAS_INTN__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define SYNTH2__CPBIAS_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define SYNTH2__CPBIAS_INTN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field VC_LOW_REF */ +#define SYNTH2__VC_LOW_REF__SHIFT 20 +#define SYNTH2__VC_LOW_REF__WIDTH 3 +#define SYNTH2__VC_LOW_REF__MASK 0x00700000U +#define SYNTH2__VC_LOW_REF__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) +#define SYNTH2__VC_LOW_REF__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) +#define SYNTH2__VC_LOW_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define SYNTH2__VC_LOW_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field VC_MID_REF */ +#define SYNTH2__VC_MID_REF__SHIFT 23 +#define SYNTH2__VC_MID_REF__WIDTH 3 +#define SYNTH2__VC_MID_REF__MASK 0x03800000U +#define SYNTH2__VC_MID_REF__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) +#define SYNTH2__VC_MID_REF__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) +#define SYNTH2__VC_MID_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define SYNTH2__VC_MID_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field VC_HI_REF */ +#define SYNTH2__VC_HI_REF__SHIFT 26 +#define SYNTH2__VC_HI_REF__WIDTH 3 +#define SYNTH2__VC_HI_REF__MASK 0x1c000000U +#define SYNTH2__VC_HI_REF__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define SYNTH2__VC_HI_REF__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define SYNTH2__VC_HI_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define SYNTH2__VC_HI_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field VC_CAL_REF */ +#define SYNTH2__VC_CAL_REF__SHIFT 29 +#define SYNTH2__VC_CAL_REF__WIDTH 3 +#define SYNTH2__VC_CAL_REF__MASK 0xe0000000U +#define SYNTH2__VC_CAL_REF__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define SYNTH2__VC_CAL_REF__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define SYNTH2__VC_CAL_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define SYNTH2__VC_CAL_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define SYNTH2__TYPE u_int32_t +#define SYNTH2__READ 0xffffffffU +#define SYNTH2__WRITE 0xffffffffU + +#endif /* __SYNTH2_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH2 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH3 */ +#ifndef __SYNTH3_MACRO__ +#define __SYNTH3_MACRO__ + +/* macros for field WAIT_VC_CHECK */ +#define SYNTH3__WAIT_VC_CHECK__SHIFT 0 +#define SYNTH3__WAIT_VC_CHECK__WIDTH 6 +#define SYNTH3__WAIT_VC_CHECK__MASK 0x0000003fU +#define SYNTH3__WAIT_VC_CHECK__READ(src) (u_int32_t)(src) & 0x0000003fU +#define SYNTH3__WAIT_VC_CHECK__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define SYNTH3__WAIT_VC_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define SYNTH3__WAIT_VC_CHECK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field WAIT_CAL_LIN */ +#define SYNTH3__WAIT_CAL_LIN__SHIFT 6 +#define SYNTH3__WAIT_CAL_LIN__WIDTH 6 +#define SYNTH3__WAIT_CAL_LIN__MASK 0x00000fc0U +#define SYNTH3__WAIT_CAL_LIN__READ(src) (((u_int32_t)(src) & 0x00000fc0U) >> 6) +#define SYNTH3__WAIT_CAL_LIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define SYNTH3__WAIT_CAL_LIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define SYNTH3__WAIT_CAL_LIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field WAIT_CAL_BIN */ +#define SYNTH3__WAIT_CAL_BIN__SHIFT 12 +#define SYNTH3__WAIT_CAL_BIN__WIDTH 6 +#define SYNTH3__WAIT_CAL_BIN__MASK 0x0003f000U +#define SYNTH3__WAIT_CAL_BIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define SYNTH3__WAIT_CAL_BIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define SYNTH3__WAIT_CAL_BIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define SYNTH3__WAIT_CAL_BIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field WAIT_PWRUP */ +#define SYNTH3__WAIT_PWRUP__SHIFT 18 +#define SYNTH3__WAIT_PWRUP__WIDTH 6 +#define SYNTH3__WAIT_PWRUP__MASK 0x00fc0000U +#define SYNTH3__WAIT_PWRUP__READ(src) (((u_int32_t)(src) & 0x00fc0000U) >> 18) +#define SYNTH3__WAIT_PWRUP__WRITE(src) (((u_int32_t)(src) << 18) & 0x00fc0000U) +#define SYNTH3__WAIT_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define SYNTH3__WAIT_PWRUP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field WAIT_SHORTR_PWRUP */ +#define SYNTH3__WAIT_SHORTR_PWRUP__SHIFT 24 +#define SYNTH3__WAIT_SHORTR_PWRUP__WIDTH 6 +#define SYNTH3__WAIT_SHORTR_PWRUP__MASK 0x3f000000U +#define SYNTH3__WAIT_SHORTR_PWRUP__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define SYNTH3__WAIT_SHORTR_PWRUP__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define SYNTH3__WAIT_SHORTR_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define SYNTH3__WAIT_SHORTR_PWRUP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) + +/* macros for field SEL_CLK_DIV2 */ +#define SYNTH3__SEL_CLK_DIV2__SHIFT 30 +#define SYNTH3__SEL_CLK_DIV2__WIDTH 1 +#define SYNTH3__SEL_CLK_DIV2__MASK 0x40000000U +#define SYNTH3__SEL_CLK_DIV2__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define SYNTH3__SEL_CLK_DIV2__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define SYNTH3__SEL_CLK_DIV2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SYNTH3__SEL_CLK_DIV2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SYNTH3__SEL_CLK_DIV2__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SYNTH3__SEL_CLK_DIV2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field DIS_CLK_XTAL */ +#define SYNTH3__DIS_CLK_XTAL__SHIFT 31 +#define SYNTH3__DIS_CLK_XTAL__WIDTH 1 +#define SYNTH3__DIS_CLK_XTAL__MASK 0x80000000U +#define SYNTH3__DIS_CLK_XTAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define SYNTH3__DIS_CLK_XTAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define SYNTH3__DIS_CLK_XTAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SYNTH3__DIS_CLK_XTAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SYNTH3__DIS_CLK_XTAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH3__DIS_CLK_XTAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH3__TYPE u_int32_t +#define SYNTH3__READ 0xffffffffU +#define SYNTH3__WRITE 0xffffffffU + +#endif /* __SYNTH3_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH3 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH4 */ +#ifndef __SYNTH4_MACRO__ +#define __SYNTH4_MACRO__ + +/* macros for field PS_SINGLE_PULSE */ +#define SYNTH4__PS_SINGLE_PULSE__SHIFT 0 +#define SYNTH4__PS_SINGLE_PULSE__WIDTH 1 +#define SYNTH4__PS_SINGLE_PULSE__MASK 0x00000001U +#define SYNTH4__PS_SINGLE_PULSE__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYNTH4__PS_SINGLE_PULSE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define SYNTH4__PS_SINGLE_PULSE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYNTH4__PS_SINGLE_PULSE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SYNTH4__PS_SINGLE_PULSE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYNTH4__PS_SINGLE_PULSE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LONGSHIFTSEL */ +#define SYNTH4__LONGSHIFTSEL__SHIFT 1 +#define SYNTH4__LONGSHIFTSEL__WIDTH 1 +#define SYNTH4__LONGSHIFTSEL__MASK 0x00000002U +#define SYNTH4__LONGSHIFTSEL__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define SYNTH4__LONGSHIFTSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define SYNTH4__LONGSHIFTSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define SYNTH4__LONGSHIFTSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define SYNTH4__LONGSHIFTSEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define SYNTH4__LONGSHIFTSEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field LOBUF5GTUNE_OVR */ +#define SYNTH4__LOBUF5GTUNE_OVR__SHIFT 2 +#define SYNTH4__LOBUF5GTUNE_OVR__WIDTH 2 +#define SYNTH4__LOBUF5GTUNE_OVR__MASK 0x0000000cU +#define SYNTH4__LOBUF5GTUNE_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define SYNTH4__LOBUF5GTUNE_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define SYNTH4__LOBUF5GTUNE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define SYNTH4__LOBUF5GTUNE_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field FORCE_LOBUF5GTUNE */ +#define SYNTH4__FORCE_LOBUF5GTUNE__SHIFT 4 +#define SYNTH4__FORCE_LOBUF5GTUNE__WIDTH 1 +#define SYNTH4__FORCE_LOBUF5GTUNE__MASK 0x00000010U +#define SYNTH4__FORCE_LOBUF5GTUNE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define SYNTH4__FORCE_LOBUF5GTUNE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define SYNTH4__FORCE_LOBUF5GTUNE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define SYNTH4__FORCE_LOBUF5GTUNE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define SYNTH4__FORCE_LOBUF5GTUNE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define SYNTH4__FORCE_LOBUF5GTUNE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PSCOUNT_FBSEL */ +#define SYNTH4__PSCOUNT_FBSEL__SHIFT 5 +#define SYNTH4__PSCOUNT_FBSEL__WIDTH 1 +#define SYNTH4__PSCOUNT_FBSEL__MASK 0x00000020U +#define SYNTH4__PSCOUNT_FBSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define SYNTH4__PSCOUNT_FBSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define SYNTH4__PSCOUNT_FBSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define SYNTH4__PSCOUNT_FBSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define SYNTH4__PSCOUNT_FBSEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define SYNTH4__PSCOUNT_FBSEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field SDM_DITHER1 */ +#define SYNTH4__SDM_DITHER1__SHIFT 6 +#define SYNTH4__SDM_DITHER1__WIDTH 2 +#define SYNTH4__SDM_DITHER1__MASK 0x000000c0U +#define SYNTH4__SDM_DITHER1__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6) +#define SYNTH4__SDM_DITHER1__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U) +#define SYNTH4__SDM_DITHER1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SYNTH4__SDM_DITHER1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field SDM_MODE */ +#define SYNTH4__SDM_MODE__SHIFT 8 +#define SYNTH4__SDM_MODE__WIDTH 1 +#define SYNTH4__SDM_MODE__MASK 0x00000100U +#define SYNTH4__SDM_MODE__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define SYNTH4__SDM_MODE__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) +#define SYNTH4__SDM_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define SYNTH4__SDM_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define SYNTH4__SDM_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define SYNTH4__SDM_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field SDM_DISABLE */ +#define SYNTH4__SDM_DISABLE__SHIFT 9 +#define SYNTH4__SDM_DISABLE__WIDTH 1 +#define SYNTH4__SDM_DISABLE__MASK 0x00000200U +#define SYNTH4__SDM_DISABLE__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define SYNTH4__SDM_DISABLE__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) +#define SYNTH4__SDM_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define SYNTH4__SDM_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define SYNTH4__SDM_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define SYNTH4__SDM_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field RESET_PRESC */ +#define SYNTH4__RESET_PRESC__SHIFT 10 +#define SYNTH4__RESET_PRESC__WIDTH 1 +#define SYNTH4__RESET_PRESC__MASK 0x00000400U +#define SYNTH4__RESET_PRESC__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define SYNTH4__RESET_PRESC__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define SYNTH4__RESET_PRESC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define SYNTH4__RESET_PRESC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define SYNTH4__RESET_PRESC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define SYNTH4__RESET_PRESC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field PRESCSEL */ +#define SYNTH4__PRESCSEL__SHIFT 11 +#define SYNTH4__PRESCSEL__WIDTH 2 +#define SYNTH4__PRESCSEL__MASK 0x00001800U +#define SYNTH4__PRESCSEL__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11) +#define SYNTH4__PRESCSEL__WRITE(src) (((u_int32_t)(src) << 11) & 0x00001800U) +#define SYNTH4__PRESCSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define SYNTH4__PRESCSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field PFD_DISABLE */ +#define SYNTH4__PFD_DISABLE__SHIFT 13 +#define SYNTH4__PFD_DISABLE__WIDTH 1 +#define SYNTH4__PFD_DISABLE__MASK 0x00002000U +#define SYNTH4__PFD_DISABLE__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) +#define SYNTH4__PFD_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define SYNTH4__PFD_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define SYNTH4__PFD_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define SYNTH4__PFD_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define SYNTH4__PFD_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field PFDDELAY_FRACN */ +#define SYNTH4__PFDDELAY_FRACN__SHIFT 14 +#define SYNTH4__PFDDELAY_FRACN__WIDTH 1 +#define SYNTH4__PFDDELAY_FRACN__MASK 0x00004000U +#define SYNTH4__PFDDELAY_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define SYNTH4__PFDDELAY_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define SYNTH4__PFDDELAY_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define SYNTH4__PFDDELAY_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define SYNTH4__PFDDELAY_FRACN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define SYNTH4__PFDDELAY_FRACN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field FORCE_LO_ON */ +#define SYNTH4__FORCE_LO_ON__SHIFT 15 +#define SYNTH4__FORCE_LO_ON__WIDTH 1 +#define SYNTH4__FORCE_LO_ON__MASK 0x00008000U +#define SYNTH4__FORCE_LO_ON__READ(src) (((u_int32_t)(src) & 0x00008000U) >> 15) +#define SYNTH4__FORCE_LO_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define SYNTH4__FORCE_LO_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define SYNTH4__FORCE_LO_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define SYNTH4__FORCE_LO_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define SYNTH4__FORCE_LO_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field CLKXTAL_EDGE_SEL */ +#define SYNTH4__CLKXTAL_EDGE_SEL__SHIFT 16 +#define SYNTH4__CLKXTAL_EDGE_SEL__WIDTH 1 +#define SYNTH4__CLKXTAL_EDGE_SEL__MASK 0x00010000U +#define SYNTH4__CLKXTAL_EDGE_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define SYNTH4__CLKXTAL_EDGE_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define SYNTH4__CLKXTAL_EDGE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define SYNTH4__CLKXTAL_EDGE_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define SYNTH4__CLKXTAL_EDGE_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define SYNTH4__CLKXTAL_EDGE_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field VCOCAPPULLUP */ +#define SYNTH4__VCOCAPPULLUP__SHIFT 17 +#define SYNTH4__VCOCAPPULLUP__WIDTH 1 +#define SYNTH4__VCOCAPPULLUP__MASK 0x00020000U +#define SYNTH4__VCOCAPPULLUP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define SYNTH4__VCOCAPPULLUP__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define SYNTH4__VCOCAPPULLUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define SYNTH4__VCOCAPPULLUP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define SYNTH4__VCOCAPPULLUP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define SYNTH4__VCOCAPPULLUP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field VCOCAP_OVR */ +#define SYNTH4__VCOCAP_OVR__SHIFT 18 +#define SYNTH4__VCOCAP_OVR__WIDTH 8 +#define SYNTH4__VCOCAP_OVR__MASK 0x03fc0000U +#define SYNTH4__VCOCAP_OVR__READ(src) (((u_int32_t)(src) & 0x03fc0000U) >> 18) +#define SYNTH4__VCOCAP_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x03fc0000U) +#define SYNTH4__VCOCAP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x03fc0000U) +#define SYNTH4__VCOCAP_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x03fc0000U))) + +/* macros for field FORCE_VCOCAP */ +#define SYNTH4__FORCE_VCOCAP__SHIFT 26 +#define SYNTH4__FORCE_VCOCAP__WIDTH 1 +#define SYNTH4__FORCE_VCOCAP__MASK 0x04000000U +#define SYNTH4__FORCE_VCOCAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define SYNTH4__FORCE_VCOCAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define SYNTH4__FORCE_VCOCAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define SYNTH4__FORCE_VCOCAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define SYNTH4__FORCE_VCOCAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define SYNTH4__FORCE_VCOCAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field FORCE_PINVC */ +#define SYNTH4__FORCE_PINVC__SHIFT 27 +#define SYNTH4__FORCE_PINVC__WIDTH 1 +#define SYNTH4__FORCE_PINVC__MASK 0x08000000U +#define SYNTH4__FORCE_PINVC__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) +#define SYNTH4__FORCE_PINVC__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define SYNTH4__FORCE_PINVC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define SYNTH4__FORCE_PINVC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define SYNTH4__FORCE_PINVC__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define SYNTH4__FORCE_PINVC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field SHORTR_UNTIL_LOCKED */ +#define SYNTH4__SHORTR_UNTIL_LOCKED__SHIFT 28 +#define SYNTH4__SHORTR_UNTIL_LOCKED__WIDTH 1 +#define SYNTH4__SHORTR_UNTIL_LOCKED__MASK 0x10000000U +#define SYNTH4__SHORTR_UNTIL_LOCKED__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define SYNTH4__SHORTR_UNTIL_LOCKED__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define SYNTH4__SHORTR_UNTIL_LOCKED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define SYNTH4__SHORTR_UNTIL_LOCKED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define SYNTH4__SHORTR_UNTIL_LOCKED__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define SYNTH4__SHORTR_UNTIL_LOCKED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field ALWAYS_SHORTR */ +#define SYNTH4__ALWAYS_SHORTR__SHIFT 29 +#define SYNTH4__ALWAYS_SHORTR__WIDTH 1 +#define SYNTH4__ALWAYS_SHORTR__MASK 0x20000000U +#define SYNTH4__ALWAYS_SHORTR__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define SYNTH4__ALWAYS_SHORTR__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define SYNTH4__ALWAYS_SHORTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define SYNTH4__ALWAYS_SHORTR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define SYNTH4__ALWAYS_SHORTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define SYNTH4__ALWAYS_SHORTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field DIS_LOSTVC */ +#define SYNTH4__DIS_LOSTVC__SHIFT 30 +#define SYNTH4__DIS_LOSTVC__WIDTH 1 +#define SYNTH4__DIS_LOSTVC__MASK 0x40000000U +#define SYNTH4__DIS_LOSTVC__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define SYNTH4__DIS_LOSTVC__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define SYNTH4__DIS_LOSTVC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SYNTH4__DIS_LOSTVC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SYNTH4__DIS_LOSTVC__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SYNTH4__DIS_LOSTVC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field DIS_LIN_CAPSEARCH */ +#define SYNTH4__DIS_LIN_CAPSEARCH__SHIFT 31 +#define SYNTH4__DIS_LIN_CAPSEARCH__WIDTH 1 +#define SYNTH4__DIS_LIN_CAPSEARCH__MASK 0x80000000U +#define SYNTH4__DIS_LIN_CAPSEARCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define SYNTH4__DIS_LIN_CAPSEARCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define SYNTH4__DIS_LIN_CAPSEARCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SYNTH4__DIS_LIN_CAPSEARCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SYNTH4__DIS_LIN_CAPSEARCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH4__DIS_LIN_CAPSEARCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH4__TYPE u_int32_t +#define SYNTH4__READ 0xffffffffU +#define SYNTH4__WRITE 0xffffffffU + +#endif /* __SYNTH4_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH4 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH5 */ +#ifndef __SYNTH5_MACRO__ +#define __SYNTH5_MACRO__ + +/* macros for field VCOBIAS */ +#define SYNTH5__VCOBIAS__SHIFT 0 +#define SYNTH5__VCOBIAS__WIDTH 2 +#define SYNTH5__VCOBIAS__MASK 0x00000003U +#define SYNTH5__VCOBIAS__READ(src) (u_int32_t)(src) & 0x00000003U +#define SYNTH5__VCOBIAS__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define SYNTH5__VCOBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SYNTH5__VCOBIAS__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field PWDB_ICLOBUF5G50 */ +#define SYNTH5__PWDB_ICLOBUF5G50__SHIFT 2 +#define SYNTH5__PWDB_ICLOBUF5G50__WIDTH 3 +#define SYNTH5__PWDB_ICLOBUF5G50__MASK 0x0000001cU +#define SYNTH5__PWDB_ICLOBUF5G50__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define SYNTH5__PWDB_ICLOBUF5G50__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define SYNTH5__PWDB_ICLOBUF5G50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define SYNTH5__PWDB_ICLOBUF5G50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field PWDB_ICLOBUF2G50 */ +#define SYNTH5__PWDB_ICLOBUF2G50__SHIFT 5 +#define SYNTH5__PWDB_ICLOBUF2G50__WIDTH 3 +#define SYNTH5__PWDB_ICLOBUF2G50__MASK 0x000000e0U +#define SYNTH5__PWDB_ICLOBUF2G50__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define SYNTH5__PWDB_ICLOBUF2G50__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define SYNTH5__PWDB_ICLOBUF2G50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define SYNTH5__PWDB_ICLOBUF2G50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field PWDB_ICVCO25 */ +#define SYNTH5__PWDB_ICVCO25__SHIFT 8 +#define SYNTH5__PWDB_ICVCO25__WIDTH 3 +#define SYNTH5__PWDB_ICVCO25__MASK 0x00000700U +#define SYNTH5__PWDB_ICVCO25__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) +#define SYNTH5__PWDB_ICVCO25__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define SYNTH5__PWDB_ICVCO25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define SYNTH5__PWDB_ICVCO25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field PWDB_ICVCOREG25 */ +#define SYNTH5__PWDB_ICVCOREG25__SHIFT 11 +#define SYNTH5__PWDB_ICVCOREG25__WIDTH 3 +#define SYNTH5__PWDB_ICVCOREG25__MASK 0x00003800U +#define SYNTH5__PWDB_ICVCOREG25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define SYNTH5__PWDB_ICVCOREG25__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define SYNTH5__PWDB_ICVCOREG25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define SYNTH5__PWDB_ICVCOREG25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field PWDB_IRVCOREG50 */ +#define SYNTH5__PWDB_IRVCOREG50__SHIFT 14 +#define SYNTH5__PWDB_IRVCOREG50__WIDTH 1 +#define SYNTH5__PWDB_IRVCOREG50__MASK 0x00004000U +#define SYNTH5__PWDB_IRVCOREG50__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define SYNTH5__PWDB_IRVCOREG50__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define SYNTH5__PWDB_IRVCOREG50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define SYNTH5__PWDB_IRVCOREG50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define SYNTH5__PWDB_IRVCOREG50__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define SYNTH5__PWDB_IRVCOREG50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field PWDB_ICLOMIX */ +#define SYNTH5__PWDB_ICLOMIX__SHIFT 15 +#define SYNTH5__PWDB_ICLOMIX__WIDTH 3 +#define SYNTH5__PWDB_ICLOMIX__MASK 0x00038000U +#define SYNTH5__PWDB_ICLOMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00038000U) >> 15) +#define SYNTH5__PWDB_ICLOMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00038000U) +#define SYNTH5__PWDB_ICLOMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define SYNTH5__PWDB_ICLOMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field PWDB_ICLODIV50 */ +#define SYNTH5__PWDB_ICLODIV50__SHIFT 18 +#define SYNTH5__PWDB_ICLODIV50__WIDTH 3 +#define SYNTH5__PWDB_ICLODIV50__MASK 0x001c0000U +#define SYNTH5__PWDB_ICLODIV50__READ(src) \ + (((u_int32_t)(src)\ + & 0x001c0000U) >> 18) +#define SYNTH5__PWDB_ICLODIV50__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x001c0000U) +#define SYNTH5__PWDB_ICLODIV50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define SYNTH5__PWDB_ICLODIV50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field PWDB_ICPRESC50 */ +#define SYNTH5__PWDB_ICPRESC50__SHIFT 21 +#define SYNTH5__PWDB_ICPRESC50__WIDTH 3 +#define SYNTH5__PWDB_ICPRESC50__MASK 0x00e00000U +#define SYNTH5__PWDB_ICPRESC50__READ(src) \ + (((u_int32_t)(src)\ + & 0x00e00000U) >> 21) +#define SYNTH5__PWDB_ICPRESC50__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00e00000U) +#define SYNTH5__PWDB_ICPRESC50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define SYNTH5__PWDB_ICPRESC50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field PWDB_IRVCMON25 */ +#define SYNTH5__PWDB_IRVCMON25__SHIFT 24 +#define SYNTH5__PWDB_IRVCMON25__WIDTH 3 +#define SYNTH5__PWDB_IRVCMON25__MASK 0x07000000U +#define SYNTH5__PWDB_IRVCMON25__READ(src) \ + (((u_int32_t)(src)\ + & 0x07000000U) >> 24) +#define SYNTH5__PWDB_IRVCMON25__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x07000000U) +#define SYNTH5__PWDB_IRVCMON25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define SYNTH5__PWDB_IRVCMON25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x07000000U))) + +/* macros for field PWDB_IRPFDCP */ +#define SYNTH5__PWDB_IRPFDCP__SHIFT 27 +#define SYNTH5__PWDB_IRPFDCP__WIDTH 3 +#define SYNTH5__PWDB_IRPFDCP__MASK 0x38000000U +#define SYNTH5__PWDB_IRPFDCP__READ(src) \ + (((u_int32_t)(src)\ + & 0x38000000U) >> 27) +#define SYNTH5__PWDB_IRPFDCP__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x38000000U) +#define SYNTH5__PWDB_IRPFDCP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x38000000U) | (((u_int32_t)(src) <<\ + 27) & 0x38000000U) +#define SYNTH5__PWDB_IRPFDCP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x38000000U))) + +/* macros for field SDM_DITHER2 */ +#define SYNTH5__SDM_DITHER2__SHIFT 30 +#define SYNTH5__SDM_DITHER2__WIDTH 2 +#define SYNTH5__SDM_DITHER2__MASK 0xc0000000U +#define SYNTH5__SDM_DITHER2__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) +#define SYNTH5__SDM_DITHER2__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define SYNTH5__SDM_DITHER2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define SYNTH5__SDM_DITHER2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define SYNTH5__TYPE u_int32_t +#define SYNTH5__READ 0xffffffffU +#define SYNTH5__WRITE 0xffffffffU + +#endif /* __SYNTH5_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH5 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH6 */ +#ifndef __SYNTH6_MACRO__ +#define __SYNTH6_MACRO__ + +/* macros for field LOBUF5GTUNE */ +#define SYNTH6__LOBUF5GTUNE__SHIFT 0 +#define SYNTH6__LOBUF5GTUNE__WIDTH 2 +#define SYNTH6__LOBUF5GTUNE__MASK 0x00000003U +#define SYNTH6__LOBUF5GTUNE__READ(src) (u_int32_t)(src) & 0x00000003U + +/* macros for field LOOP_IP */ +#define SYNTH6__LOOP_IP__SHIFT 2 +#define SYNTH6__LOOP_IP__WIDTH 7 +#define SYNTH6__LOOP_IP__MASK 0x000001fcU +#define SYNTH6__LOOP_IP__READ(src) (((u_int32_t)(src) & 0x000001fcU) >> 2) + +/* macros for field VC2LOW */ +#define SYNTH6__VC2LOW__SHIFT 9 +#define SYNTH6__VC2LOW__WIDTH 1 +#define SYNTH6__VC2LOW__MASK 0x00000200U +#define SYNTH6__VC2LOW__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define SYNTH6__VC2LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define SYNTH6__VC2LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field VC2HIGH */ +#define SYNTH6__VC2HIGH__SHIFT 10 +#define SYNTH6__VC2HIGH__WIDTH 1 +#define SYNTH6__VC2HIGH__MASK 0x00000400U +#define SYNTH6__VC2HIGH__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define SYNTH6__VC2HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define SYNTH6__VC2HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field RESET_SDM_B */ +#define SYNTH6__RESET_SDM_B__SHIFT 11 +#define SYNTH6__RESET_SDM_B__WIDTH 1 +#define SYNTH6__RESET_SDM_B__MASK 0x00000800U +#define SYNTH6__RESET_SDM_B__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define SYNTH6__RESET_SDM_B__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define SYNTH6__RESET_SDM_B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field RESET_PSCOUNTERS */ +#define SYNTH6__RESET_PSCOUNTERS__SHIFT 12 +#define SYNTH6__RESET_PSCOUNTERS__WIDTH 1 +#define SYNTH6__RESET_PSCOUNTERS__MASK 0x00001000U +#define SYNTH6__RESET_PSCOUNTERS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define SYNTH6__RESET_PSCOUNTERS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define SYNTH6__RESET_PSCOUNTERS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field RESET_PFD */ +#define SYNTH6__RESET_PFD__SHIFT 13 +#define SYNTH6__RESET_PFD__WIDTH 1 +#define SYNTH6__RESET_PFD__MASK 0x00002000U +#define SYNTH6__RESET_PFD__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) +#define SYNTH6__RESET_PFD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define SYNTH6__RESET_PFD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field RESET_RFD */ +#define SYNTH6__RESET_RFD__SHIFT 14 +#define SYNTH6__RESET_RFD__WIDTH 1 +#define SYNTH6__RESET_RFD__MASK 0x00004000U +#define SYNTH6__RESET_RFD__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) +#define SYNTH6__RESET_RFD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define SYNTH6__RESET_RFD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field SHORT_R */ +#define SYNTH6__SHORT_R__SHIFT 15 +#define SYNTH6__SHORT_R__WIDTH 1 +#define SYNTH6__SHORT_R__MASK 0x00008000U +#define SYNTH6__SHORT_R__READ(src) (((u_int32_t)(src) & 0x00008000U) >> 15) +#define SYNTH6__SHORT_R__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define SYNTH6__SHORT_R__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field VCO_CAP_ST */ +#define SYNTH6__VCO_CAP_ST__SHIFT 16 +#define SYNTH6__VCO_CAP_ST__WIDTH 8 +#define SYNTH6__VCO_CAP_ST__MASK 0x00ff0000U +#define SYNTH6__VCO_CAP_ST__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) + +/* macros for field PIN_VC */ +#define SYNTH6__PIN_VC__SHIFT 24 +#define SYNTH6__PIN_VC__WIDTH 1 +#define SYNTH6__PIN_VC__MASK 0x01000000U +#define SYNTH6__PIN_VC__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define SYNTH6__PIN_VC__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define SYNTH6__PIN_VC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field SYNTH_LOCK_VC_OK */ +#define SYNTH6__SYNTH_LOCK_VC_OK__SHIFT 25 +#define SYNTH6__SYNTH_LOCK_VC_OK__WIDTH 1 +#define SYNTH6__SYNTH_LOCK_VC_OK__MASK 0x02000000U +#define SYNTH6__SYNTH_LOCK_VC_OK__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define SYNTH6__SYNTH_LOCK_VC_OK__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define SYNTH6__SYNTH_LOCK_VC_OK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field CAP_SEARCH */ +#define SYNTH6__CAP_SEARCH__SHIFT 26 +#define SYNTH6__CAP_SEARCH__WIDTH 1 +#define SYNTH6__CAP_SEARCH__MASK 0x04000000U +#define SYNTH6__CAP_SEARCH__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) +#define SYNTH6__CAP_SEARCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define SYNTH6__CAP_SEARCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field SYNTH_SM_STATE */ +#define SYNTH6__SYNTH_SM_STATE__SHIFT 27 +#define SYNTH6__SYNTH_SM_STATE__WIDTH 4 +#define SYNTH6__SYNTH_SM_STATE__MASK 0x78000000U +#define SYNTH6__SYNTH_SM_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x78000000U) >> 27) + +/* macros for field SYNTH_ON */ +#define SYNTH6__SYNTH_ON__SHIFT 31 +#define SYNTH6__SYNTH_ON__WIDTH 1 +#define SYNTH6__SYNTH_ON__MASK 0x80000000U +#define SYNTH6__SYNTH_ON__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define SYNTH6__SYNTH_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH6__SYNTH_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH6__TYPE u_int32_t +#define SYNTH6__READ 0xffffffffU + +#endif /* __SYNTH6_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH6 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH7 */ +#ifndef __SYNTH7_MACRO__ +#define __SYNTH7_MACRO__ + +/* macros for field OVRCHANDECODER */ +#define SYNTH7__OVRCHANDECODER__SHIFT 0 +#define SYNTH7__OVRCHANDECODER__WIDTH 1 +#define SYNTH7__OVRCHANDECODER__MASK 0x00000001U +#define SYNTH7__OVRCHANDECODER__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYNTH7__OVRCHANDECODER__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define SYNTH7__OVRCHANDECODER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYNTH7__OVRCHANDECODER__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SYNTH7__OVRCHANDECODER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYNTH7__OVRCHANDECODER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field FORCE_FRACLSB */ +#define SYNTH7__FORCE_FRACLSB__SHIFT 1 +#define SYNTH7__FORCE_FRACLSB__WIDTH 1 +#define SYNTH7__FORCE_FRACLSB__MASK 0x00000002U +#define SYNTH7__FORCE_FRACLSB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define SYNTH7__FORCE_FRACLSB__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define SYNTH7__FORCE_FRACLSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define SYNTH7__FORCE_FRACLSB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define SYNTH7__FORCE_FRACLSB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define SYNTH7__FORCE_FRACLSB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field CHANFRAC */ +#define SYNTH7__CHANFRAC__SHIFT 2 +#define SYNTH7__CHANFRAC__WIDTH 17 +#define SYNTH7__CHANFRAC__MASK 0x0007fffcU +#define SYNTH7__CHANFRAC__READ(src) (((u_int32_t)(src) & 0x0007fffcU) >> 2) +#define SYNTH7__CHANFRAC__WRITE(src) (((u_int32_t)(src) << 2) & 0x0007fffcU) +#define SYNTH7__CHANFRAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0007fffcU) +#define SYNTH7__CHANFRAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0007fffcU))) + +/* macros for field CHANSEL */ +#define SYNTH7__CHANSEL__SHIFT 19 +#define SYNTH7__CHANSEL__WIDTH 9 +#define SYNTH7__CHANSEL__MASK 0x0ff80000U +#define SYNTH7__CHANSEL__READ(src) (((u_int32_t)(src) & 0x0ff80000U) >> 19) +#define SYNTH7__CHANSEL__WRITE(src) (((u_int32_t)(src) << 19) & 0x0ff80000U) +#define SYNTH7__CHANSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ff80000U) | (((u_int32_t)(src) <<\ + 19) & 0x0ff80000U) +#define SYNTH7__CHANSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x0ff80000U))) + +/* macros for field AMODEREFSEL */ +#define SYNTH7__AMODEREFSEL__SHIFT 28 +#define SYNTH7__AMODEREFSEL__WIDTH 2 +#define SYNTH7__AMODEREFSEL__MASK 0x30000000U +#define SYNTH7__AMODEREFSEL__READ(src) (((u_int32_t)(src) & 0x30000000U) >> 28) +#define SYNTH7__AMODEREFSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x30000000U) +#define SYNTH7__AMODEREFSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define SYNTH7__AMODEREFSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) + +/* macros for field FRACMODE */ +#define SYNTH7__FRACMODE__SHIFT 30 +#define SYNTH7__FRACMODE__WIDTH 1 +#define SYNTH7__FRACMODE__MASK 0x40000000U +#define SYNTH7__FRACMODE__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define SYNTH7__FRACMODE__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define SYNTH7__FRACMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SYNTH7__FRACMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SYNTH7__FRACMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SYNTH7__FRACMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field LOADSYNTHCHANNEL */ +#define SYNTH7__LOADSYNTHCHANNEL__SHIFT 31 +#define SYNTH7__LOADSYNTHCHANNEL__WIDTH 1 +#define SYNTH7__LOADSYNTHCHANNEL__MASK 0x80000000U +#define SYNTH7__LOADSYNTHCHANNEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define SYNTH7__LOADSYNTHCHANNEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define SYNTH7__LOADSYNTHCHANNEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SYNTH7__LOADSYNTHCHANNEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SYNTH7__LOADSYNTHCHANNEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH7__LOADSYNTHCHANNEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH7__TYPE u_int32_t +#define SYNTH7__READ 0xffffffffU +#define SYNTH7__WRITE 0xffffffffU + +#endif /* __SYNTH7_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH7 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH8 */ +#ifndef __SYNTH8_MACRO__ +#define __SYNTH8_MACRO__ + +/* macros for field CPSTEERING_EN_FRACN */ +#define SYNTH8__CPSTEERING_EN_FRACN__SHIFT 0 +#define SYNTH8__CPSTEERING_EN_FRACN__WIDTH 1 +#define SYNTH8__CPSTEERING_EN_FRACN__MASK 0x00000001U +#define SYNTH8__CPSTEERING_EN_FRACN__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYNTH8__CPSTEERING_EN_FRACN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define SYNTH8__CPSTEERING_EN_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYNTH8__CPSTEERING_EN_FRACN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SYNTH8__CPSTEERING_EN_FRACN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYNTH8__CPSTEERING_EN_FRACN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LOOP_ICPB */ +#define SYNTH8__LOOP_ICPB__SHIFT 1 +#define SYNTH8__LOOP_ICPB__WIDTH 7 +#define SYNTH8__LOOP_ICPB__MASK 0x000000feU +#define SYNTH8__LOOP_ICPB__READ(src) (((u_int32_t)(src) & 0x000000feU) >> 1) +#define SYNTH8__LOOP_ICPB__WRITE(src) (((u_int32_t)(src) << 1) & 0x000000feU) +#define SYNTH8__LOOP_ICPB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((u_int32_t)(src) <<\ + 1) & 0x000000feU) +#define SYNTH8__LOOP_ICPB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000000feU))) + +/* macros for field LOOP_CSB */ +#define SYNTH8__LOOP_CSB__SHIFT 8 +#define SYNTH8__LOOP_CSB__WIDTH 4 +#define SYNTH8__LOOP_CSB__MASK 0x00000f00U +#define SYNTH8__LOOP_CSB__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) +#define SYNTH8__LOOP_CSB__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) +#define SYNTH8__LOOP_CSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SYNTH8__LOOP_CSB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field LOOP_RSB */ +#define SYNTH8__LOOP_RSB__SHIFT 12 +#define SYNTH8__LOOP_RSB__WIDTH 5 +#define SYNTH8__LOOP_RSB__MASK 0x0001f000U +#define SYNTH8__LOOP_RSB__READ(src) (((u_int32_t)(src) & 0x0001f000U) >> 12) +#define SYNTH8__LOOP_RSB__WRITE(src) (((u_int32_t)(src) << 12) & 0x0001f000U) +#define SYNTH8__LOOP_RSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define SYNTH8__LOOP_RSB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field LOOP_CPB */ +#define SYNTH8__LOOP_CPB__SHIFT 17 +#define SYNTH8__LOOP_CPB__WIDTH 5 +#define SYNTH8__LOOP_CPB__MASK 0x003e0000U +#define SYNTH8__LOOP_CPB__READ(src) (((u_int32_t)(src) & 0x003e0000U) >> 17) +#define SYNTH8__LOOP_CPB__WRITE(src) (((u_int32_t)(src) << 17) & 0x003e0000U) +#define SYNTH8__LOOP_CPB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define SYNTH8__LOOP_CPB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field LOOP_3RD_ORDER_RB */ +#define SYNTH8__LOOP_3RD_ORDER_RB__SHIFT 22 +#define SYNTH8__LOOP_3RD_ORDER_RB__WIDTH 5 +#define SYNTH8__LOOP_3RD_ORDER_RB__MASK 0x07c00000U +#define SYNTH8__LOOP_3RD_ORDER_RB__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define SYNTH8__LOOP_3RD_ORDER_RB__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define SYNTH8__LOOP_3RD_ORDER_RB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define SYNTH8__LOOP_3RD_ORDER_RB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field REFDIVB */ +#define SYNTH8__REFDIVB__SHIFT 27 +#define SYNTH8__REFDIVB__WIDTH 5 +#define SYNTH8__REFDIVB__MASK 0xf8000000U +#define SYNTH8__REFDIVB__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) +#define SYNTH8__REFDIVB__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) +#define SYNTH8__REFDIVB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define SYNTH8__REFDIVB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define SYNTH8__TYPE u_int32_t +#define SYNTH8__READ 0xffffffffU +#define SYNTH8__WRITE 0xffffffffU + +#endif /* __SYNTH8_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH8 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH9 */ +#ifndef __SYNTH9_MACRO__ +#define __SYNTH9_MACRO__ + +/* macros for field PFDDELAY_INTN */ +#define SYNTH9__PFDDELAY_INTN__SHIFT 0 +#define SYNTH9__PFDDELAY_INTN__WIDTH 1 +#define SYNTH9__PFDDELAY_INTN__MASK 0x00000001U +#define SYNTH9__PFDDELAY_INTN__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYNTH9__PFDDELAY_INTN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define SYNTH9__PFDDELAY_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYNTH9__PFDDELAY_INTN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SYNTH9__PFDDELAY_INTN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYNTH9__PFDDELAY_INTN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field SLOPE_ICPA0 */ +#define SYNTH9__SLOPE_ICPA0__SHIFT 1 +#define SYNTH9__SLOPE_ICPA0__WIDTH 3 +#define SYNTH9__SLOPE_ICPA0__MASK 0x0000000eU +#define SYNTH9__SLOPE_ICPA0__READ(src) (((u_int32_t)(src) & 0x0000000eU) >> 1) +#define SYNTH9__SLOPE_ICPA0__WRITE(src) (((u_int32_t)(src) << 1) & 0x0000000eU) +#define SYNTH9__SLOPE_ICPA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define SYNTH9__SLOPE_ICPA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field LOOP_ICPA0 */ +#define SYNTH9__LOOP_ICPA0__SHIFT 4 +#define SYNTH9__LOOP_ICPA0__WIDTH 4 +#define SYNTH9__LOOP_ICPA0__MASK 0x000000f0U +#define SYNTH9__LOOP_ICPA0__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) +#define SYNTH9__LOOP_ICPA0__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) +#define SYNTH9__LOOP_ICPA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SYNTH9__LOOP_ICPA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field LOOP_CSA0 */ +#define SYNTH9__LOOP_CSA0__SHIFT 8 +#define SYNTH9__LOOP_CSA0__WIDTH 4 +#define SYNTH9__LOOP_CSA0__MASK 0x00000f00U +#define SYNTH9__LOOP_CSA0__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) +#define SYNTH9__LOOP_CSA0__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) +#define SYNTH9__LOOP_CSA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SYNTH9__LOOP_CSA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field LOOP_RSA0 */ +#define SYNTH9__LOOP_RSA0__SHIFT 12 +#define SYNTH9__LOOP_RSA0__WIDTH 5 +#define SYNTH9__LOOP_RSA0__MASK 0x0001f000U +#define SYNTH9__LOOP_RSA0__READ(src) (((u_int32_t)(src) & 0x0001f000U) >> 12) +#define SYNTH9__LOOP_RSA0__WRITE(src) (((u_int32_t)(src) << 12) & 0x0001f000U) +#define SYNTH9__LOOP_RSA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define SYNTH9__LOOP_RSA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field LOOP_CPA0 */ +#define SYNTH9__LOOP_CPA0__SHIFT 17 +#define SYNTH9__LOOP_CPA0__WIDTH 5 +#define SYNTH9__LOOP_CPA0__MASK 0x003e0000U +#define SYNTH9__LOOP_CPA0__READ(src) (((u_int32_t)(src) & 0x003e0000U) >> 17) +#define SYNTH9__LOOP_CPA0__WRITE(src) (((u_int32_t)(src) << 17) & 0x003e0000U) +#define SYNTH9__LOOP_CPA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define SYNTH9__LOOP_CPA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field LOOP_3RD_ORDER_RA */ +#define SYNTH9__LOOP_3RD_ORDER_RA__SHIFT 22 +#define SYNTH9__LOOP_3RD_ORDER_RA__WIDTH 5 +#define SYNTH9__LOOP_3RD_ORDER_RA__MASK 0x07c00000U +#define SYNTH9__LOOP_3RD_ORDER_RA__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define SYNTH9__LOOP_3RD_ORDER_RA__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define SYNTH9__LOOP_3RD_ORDER_RA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define SYNTH9__LOOP_3RD_ORDER_RA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field REFDIVA */ +#define SYNTH9__REFDIVA__SHIFT 27 +#define SYNTH9__REFDIVA__WIDTH 5 +#define SYNTH9__REFDIVA__MASK 0xf8000000U +#define SYNTH9__REFDIVA__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) +#define SYNTH9__REFDIVA__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) +#define SYNTH9__REFDIVA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define SYNTH9__REFDIVA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define SYNTH9__TYPE u_int32_t +#define SYNTH9__READ 0xffffffffU +#define SYNTH9__WRITE 0xffffffffU + +#endif /* __SYNTH9_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH9 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH10 */ +#ifndef __SYNTH10_MACRO__ +#define __SYNTH10_MACRO__ + +/* macros for field SPARE10A */ +#define SYNTH10__SPARE10A__SHIFT 0 +#define SYNTH10__SPARE10A__WIDTH 2 +#define SYNTH10__SPARE10A__MASK 0x00000003U +#define SYNTH10__SPARE10A__READ(src) (u_int32_t)(src) & 0x00000003U +#define SYNTH10__SPARE10A__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define SYNTH10__SPARE10A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SYNTH10__SPARE10A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field PWDB_ICLOBIAS50 */ +#define SYNTH10__PWDB_ICLOBIAS50__SHIFT 2 +#define SYNTH10__PWDB_ICLOBIAS50__WIDTH 3 +#define SYNTH10__PWDB_ICLOBIAS50__MASK 0x0000001cU +#define SYNTH10__PWDB_ICLOBIAS50__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define SYNTH10__PWDB_ICLOBIAS50__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define SYNTH10__PWDB_ICLOBIAS50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define SYNTH10__PWDB_ICLOBIAS50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field PWDB_IRSPARE25 */ +#define SYNTH10__PWDB_IRSPARE25__SHIFT 5 +#define SYNTH10__PWDB_IRSPARE25__WIDTH 3 +#define SYNTH10__PWDB_IRSPARE25__MASK 0x000000e0U +#define SYNTH10__PWDB_IRSPARE25__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define SYNTH10__PWDB_IRSPARE25__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define SYNTH10__PWDB_IRSPARE25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define SYNTH10__PWDB_IRSPARE25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field PWDB_ICSPARE25 */ +#define SYNTH10__PWDB_ICSPARE25__SHIFT 8 +#define SYNTH10__PWDB_ICSPARE25__WIDTH 3 +#define SYNTH10__PWDB_ICSPARE25__MASK 0x00000700U +#define SYNTH10__PWDB_ICSPARE25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define SYNTH10__PWDB_ICSPARE25__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define SYNTH10__PWDB_ICSPARE25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define SYNTH10__PWDB_ICSPARE25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field SLOPE_ICPA1 */ +#define SYNTH10__SLOPE_ICPA1__SHIFT 11 +#define SYNTH10__SLOPE_ICPA1__WIDTH 3 +#define SYNTH10__SLOPE_ICPA1__MASK 0x00003800U +#define SYNTH10__SLOPE_ICPA1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define SYNTH10__SLOPE_ICPA1__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define SYNTH10__SLOPE_ICPA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define SYNTH10__SLOPE_ICPA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field LOOP_ICPA1 */ +#define SYNTH10__LOOP_ICPA1__SHIFT 14 +#define SYNTH10__LOOP_ICPA1__WIDTH 4 +#define SYNTH10__LOOP_ICPA1__MASK 0x0003c000U +#define SYNTH10__LOOP_ICPA1__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14) +#define SYNTH10__LOOP_ICPA1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0003c000U) +#define SYNTH10__LOOP_ICPA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0003c000U) +#define SYNTH10__LOOP_ICPA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0003c000U))) + +/* macros for field LOOP_CSA1 */ +#define SYNTH10__LOOP_CSA1__SHIFT 18 +#define SYNTH10__LOOP_CSA1__WIDTH 4 +#define SYNTH10__LOOP_CSA1__MASK 0x003c0000U +#define SYNTH10__LOOP_CSA1__READ(src) (((u_int32_t)(src) & 0x003c0000U) >> 18) +#define SYNTH10__LOOP_CSA1__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U) +#define SYNTH10__LOOP_CSA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x003c0000U) +#define SYNTH10__LOOP_CSA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x003c0000U))) + +/* macros for field LOOP_RSA1 */ +#define SYNTH10__LOOP_RSA1__SHIFT 22 +#define SYNTH10__LOOP_RSA1__WIDTH 5 +#define SYNTH10__LOOP_RSA1__MASK 0x07c00000U +#define SYNTH10__LOOP_RSA1__READ(src) (((u_int32_t)(src) & 0x07c00000U) >> 22) +#define SYNTH10__LOOP_RSA1__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U) +#define SYNTH10__LOOP_RSA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define SYNTH10__LOOP_RSA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field LOOP_CPA1 */ +#define SYNTH10__LOOP_CPA1__SHIFT 27 +#define SYNTH10__LOOP_CPA1__WIDTH 5 +#define SYNTH10__LOOP_CPA1__MASK 0xf8000000U +#define SYNTH10__LOOP_CPA1__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) +#define SYNTH10__LOOP_CPA1__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) +#define SYNTH10__LOOP_CPA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define SYNTH10__LOOP_CPA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define SYNTH10__TYPE u_int32_t +#define SYNTH10__READ 0xffffffffU +#define SYNTH10__WRITE 0xffffffffU + +#endif /* __SYNTH10_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH10 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH11 */ +#ifndef __SYNTH11_MACRO__ +#define __SYNTH11_MACRO__ + +/* macros for field SPARE11A */ +#define SYNTH11__SPARE11A__SHIFT 0 +#define SYNTH11__SPARE11A__WIDTH 5 +#define SYNTH11__SPARE11A__MASK 0x0000001fU +#define SYNTH11__SPARE11A__READ(src) (u_int32_t)(src) & 0x0000001fU +#define SYNTH11__SPARE11A__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define SYNTH11__SPARE11A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define SYNTH11__SPARE11A__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field FORCE_LOBUF5G_ON */ +#define SYNTH11__FORCE_LOBUF5G_ON__SHIFT 5 +#define SYNTH11__FORCE_LOBUF5G_ON__WIDTH 1 +#define SYNTH11__FORCE_LOBUF5G_ON__MASK 0x00000020U +#define SYNTH11__FORCE_LOBUF5G_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define SYNTH11__FORCE_LOBUF5G_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define SYNTH11__FORCE_LOBUF5G_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define SYNTH11__FORCE_LOBUF5G_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define SYNTH11__FORCE_LOBUF5G_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define SYNTH11__FORCE_LOBUF5G_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field LOREFSEL */ +#define SYNTH11__LOREFSEL__SHIFT 6 +#define SYNTH11__LOREFSEL__WIDTH 2 +#define SYNTH11__LOREFSEL__MASK 0x000000c0U +#define SYNTH11__LOREFSEL__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6) +#define SYNTH11__LOREFSEL__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U) +#define SYNTH11__LOREFSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SYNTH11__LOREFSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field LOBUF2GTUNE */ +#define SYNTH11__LOBUF2GTUNE__SHIFT 8 +#define SYNTH11__LOBUF2GTUNE__WIDTH 2 +#define SYNTH11__LOBUF2GTUNE__MASK 0x00000300U +#define SYNTH11__LOBUF2GTUNE__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8) +#define SYNTH11__LOBUF2GTUNE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define SYNTH11__LOBUF2GTUNE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define SYNTH11__LOBUF2GTUNE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field CPSTEERING_MODE */ +#define SYNTH11__CPSTEERING_MODE__SHIFT 10 +#define SYNTH11__CPSTEERING_MODE__WIDTH 1 +#define SYNTH11__CPSTEERING_MODE__MASK 0x00000400U +#define SYNTH11__CPSTEERING_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define SYNTH11__CPSTEERING_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define SYNTH11__CPSTEERING_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define SYNTH11__CPSTEERING_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define SYNTH11__CPSTEERING_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define SYNTH11__CPSTEERING_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field SLOPE_ICPA2 */ +#define SYNTH11__SLOPE_ICPA2__SHIFT 11 +#define SYNTH11__SLOPE_ICPA2__WIDTH 3 +#define SYNTH11__SLOPE_ICPA2__MASK 0x00003800U +#define SYNTH11__SLOPE_ICPA2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define SYNTH11__SLOPE_ICPA2__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define SYNTH11__SLOPE_ICPA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define SYNTH11__SLOPE_ICPA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field LOOP_ICPA2 */ +#define SYNTH11__LOOP_ICPA2__SHIFT 14 +#define SYNTH11__LOOP_ICPA2__WIDTH 4 +#define SYNTH11__LOOP_ICPA2__MASK 0x0003c000U +#define SYNTH11__LOOP_ICPA2__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14) +#define SYNTH11__LOOP_ICPA2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0003c000U) +#define SYNTH11__LOOP_ICPA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0003c000U) +#define SYNTH11__LOOP_ICPA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0003c000U))) + +/* macros for field LOOP_CSA2 */ +#define SYNTH11__LOOP_CSA2__SHIFT 18 +#define SYNTH11__LOOP_CSA2__WIDTH 4 +#define SYNTH11__LOOP_CSA2__MASK 0x003c0000U +#define SYNTH11__LOOP_CSA2__READ(src) (((u_int32_t)(src) & 0x003c0000U) >> 18) +#define SYNTH11__LOOP_CSA2__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U) +#define SYNTH11__LOOP_CSA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x003c0000U) +#define SYNTH11__LOOP_CSA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x003c0000U))) + +/* macros for field LOOP_RSA2 */ +#define SYNTH11__LOOP_RSA2__SHIFT 22 +#define SYNTH11__LOOP_RSA2__WIDTH 5 +#define SYNTH11__LOOP_RSA2__MASK 0x07c00000U +#define SYNTH11__LOOP_RSA2__READ(src) (((u_int32_t)(src) & 0x07c00000U) >> 22) +#define SYNTH11__LOOP_RSA2__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U) +#define SYNTH11__LOOP_RSA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define SYNTH11__LOOP_RSA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field LOOP_CPA2 */ +#define SYNTH11__LOOP_CPA2__SHIFT 27 +#define SYNTH11__LOOP_CPA2__WIDTH 5 +#define SYNTH11__LOOP_CPA2__MASK 0xf8000000U +#define SYNTH11__LOOP_CPA2__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) +#define SYNTH11__LOOP_CPA2__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) +#define SYNTH11__LOOP_CPA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define SYNTH11__LOOP_CPA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define SYNTH11__TYPE u_int32_t +#define SYNTH11__READ 0xffffffffU +#define SYNTH11__WRITE 0xffffffffU + +#endif /* __SYNTH11_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH11 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH12 */ +#ifndef __SYNTH12_MACRO__ +#define __SYNTH12_MACRO__ + +/* macros for field SPARE12A */ +#define SYNTH12__SPARE12A__SHIFT 0 +#define SYNTH12__SPARE12A__WIDTH 10 +#define SYNTH12__SPARE12A__MASK 0x000003ffU +#define SYNTH12__SPARE12A__READ(src) (u_int32_t)(src) & 0x000003ffU +#define SYNTH12__SPARE12A__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define SYNTH12__SPARE12A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define SYNTH12__SPARE12A__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU))) + +/* macros for field LOOPLEAKCUR_FRACN */ +#define SYNTH12__LOOPLEAKCUR_FRACN__SHIFT 10 +#define SYNTH12__LOOPLEAKCUR_FRACN__WIDTH 4 +#define SYNTH12__LOOPLEAKCUR_FRACN__MASK 0x00003c00U +#define SYNTH12__LOOPLEAKCUR_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003c00U) >> 10) +#define SYNTH12__LOOPLEAKCUR_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00003c00U) +#define SYNTH12__LOOPLEAKCUR_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00003c00U) +#define SYNTH12__LOOPLEAKCUR_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00003c00U))) + +/* macros for field CPLOWLK_FRACN */ +#define SYNTH12__CPLOWLK_FRACN__SHIFT 14 +#define SYNTH12__CPLOWLK_FRACN__WIDTH 1 +#define SYNTH12__CPLOWLK_FRACN__MASK 0x00004000U +#define SYNTH12__CPLOWLK_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define SYNTH12__CPLOWLK_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define SYNTH12__CPLOWLK_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define SYNTH12__CPLOWLK_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define SYNTH12__CPLOWLK_FRACN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define SYNTH12__CPLOWLK_FRACN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field CPBIAS_FRACN */ +#define SYNTH12__CPBIAS_FRACN__SHIFT 15 +#define SYNTH12__CPBIAS_FRACN__WIDTH 2 +#define SYNTH12__CPBIAS_FRACN__MASK 0x00018000U +#define SYNTH12__CPBIAS_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00018000U) >> 15) +#define SYNTH12__CPBIAS_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00018000U) +#define SYNTH12__CPBIAS_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00018000U) | (((u_int32_t)(src) <<\ + 15) & 0x00018000U) +#define SYNTH12__CPBIAS_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00018000U))) + +/* macros for field SYNTHDIGOUTEN */ +#define SYNTH12__SYNTHDIGOUTEN__SHIFT 17 +#define SYNTH12__SYNTHDIGOUTEN__WIDTH 1 +#define SYNTH12__SYNTHDIGOUTEN__MASK 0x00020000U +#define SYNTH12__SYNTHDIGOUTEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define SYNTH12__SYNTHDIGOUTEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define SYNTH12__SYNTHDIGOUTEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define SYNTH12__SYNTHDIGOUTEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define SYNTH12__SYNTHDIGOUTEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define SYNTH12__SYNTHDIGOUTEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field STRCONT */ +#define SYNTH12__STRCONT__SHIFT 18 +#define SYNTH12__STRCONT__WIDTH 1 +#define SYNTH12__STRCONT__MASK 0x00040000U +#define SYNTH12__STRCONT__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define SYNTH12__STRCONT__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define SYNTH12__STRCONT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define SYNTH12__STRCONT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define SYNTH12__STRCONT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define SYNTH12__STRCONT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field VREFMUL3 */ +#define SYNTH12__VREFMUL3__SHIFT 19 +#define SYNTH12__VREFMUL3__WIDTH 4 +#define SYNTH12__VREFMUL3__MASK 0x00780000U +#define SYNTH12__VREFMUL3__READ(src) (((u_int32_t)(src) & 0x00780000U) >> 19) +#define SYNTH12__VREFMUL3__WRITE(src) (((u_int32_t)(src) << 19) & 0x00780000U) +#define SYNTH12__VREFMUL3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00780000U) | (((u_int32_t)(src) <<\ + 19) & 0x00780000U) +#define SYNTH12__VREFMUL3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00780000U))) + +/* macros for field VREFMUL2 */ +#define SYNTH12__VREFMUL2__SHIFT 23 +#define SYNTH12__VREFMUL2__WIDTH 4 +#define SYNTH12__VREFMUL2__MASK 0x07800000U +#define SYNTH12__VREFMUL2__READ(src) (((u_int32_t)(src) & 0x07800000U) >> 23) +#define SYNTH12__VREFMUL2__WRITE(src) (((u_int32_t)(src) << 23) & 0x07800000U) +#define SYNTH12__VREFMUL2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07800000U) | (((u_int32_t)(src) <<\ + 23) & 0x07800000U) +#define SYNTH12__VREFMUL2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x07800000U))) + +/* macros for field VREFMUL1 */ +#define SYNTH12__VREFMUL1__SHIFT 27 +#define SYNTH12__VREFMUL1__WIDTH 4 +#define SYNTH12__VREFMUL1__MASK 0x78000000U +#define SYNTH12__VREFMUL1__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define SYNTH12__VREFMUL1__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define SYNTH12__VREFMUL1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define SYNTH12__VREFMUL1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) + +/* macros for field CLK_DOUBLER_EN */ +#define SYNTH12__CLK_DOUBLER_EN__SHIFT 31 +#define SYNTH12__CLK_DOUBLER_EN__WIDTH 1 +#define SYNTH12__CLK_DOUBLER_EN__MASK 0x80000000U +#define SYNTH12__CLK_DOUBLER_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define SYNTH12__CLK_DOUBLER_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define SYNTH12__CLK_DOUBLER_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SYNTH12__CLK_DOUBLER_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SYNTH12__CLK_DOUBLER_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH12__CLK_DOUBLER_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH12__TYPE u_int32_t +#define SYNTH12__READ 0xffffffffU +#define SYNTH12__WRITE 0xffffffffU + +#endif /* __SYNTH12_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH12 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH13 */ +#ifndef __SYNTH13_MACRO__ +#define __SYNTH13_MACRO__ + +/* macros for field SPARE13A */ +#define SYNTH13__SPARE13A__SHIFT 0 +#define SYNTH13__SPARE13A__WIDTH 1 +#define SYNTH13__SPARE13A__MASK 0x00000001U +#define SYNTH13__SPARE13A__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYNTH13__SPARE13A__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define SYNTH13__SPARE13A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYNTH13__SPARE13A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define SYNTH13__SPARE13A__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYNTH13__SPARE13A__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field SLOPE_ICPA_FRACN */ +#define SYNTH13__SLOPE_ICPA_FRACN__SHIFT 1 +#define SYNTH13__SLOPE_ICPA_FRACN__WIDTH 3 +#define SYNTH13__SLOPE_ICPA_FRACN__MASK 0x0000000eU +#define SYNTH13__SLOPE_ICPA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define SYNTH13__SLOPE_ICPA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define SYNTH13__SLOPE_ICPA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define SYNTH13__SLOPE_ICPA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field LOOP_ICPA_FRACN */ +#define SYNTH13__LOOP_ICPA_FRACN__SHIFT 4 +#define SYNTH13__LOOP_ICPA_FRACN__WIDTH 4 +#define SYNTH13__LOOP_ICPA_FRACN__MASK 0x000000f0U +#define SYNTH13__LOOP_ICPA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define SYNTH13__LOOP_ICPA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define SYNTH13__LOOP_ICPA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SYNTH13__LOOP_ICPA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field LOOP_CSA_FRACN */ +#define SYNTH13__LOOP_CSA_FRACN__SHIFT 8 +#define SYNTH13__LOOP_CSA_FRACN__WIDTH 4 +#define SYNTH13__LOOP_CSA_FRACN__MASK 0x00000f00U +#define SYNTH13__LOOP_CSA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define SYNTH13__LOOP_CSA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define SYNTH13__LOOP_CSA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SYNTH13__LOOP_CSA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field LOOP_RSA_FRACN */ +#define SYNTH13__LOOP_RSA_FRACN__SHIFT 12 +#define SYNTH13__LOOP_RSA_FRACN__WIDTH 5 +#define SYNTH13__LOOP_RSA_FRACN__MASK 0x0001f000U +#define SYNTH13__LOOP_RSA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define SYNTH13__LOOP_RSA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define SYNTH13__LOOP_RSA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define SYNTH13__LOOP_RSA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field LOOP_CPA_FRACN */ +#define SYNTH13__LOOP_CPA_FRACN__SHIFT 17 +#define SYNTH13__LOOP_CPA_FRACN__WIDTH 5 +#define SYNTH13__LOOP_CPA_FRACN__MASK 0x003e0000U +#define SYNTH13__LOOP_CPA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define SYNTH13__LOOP_CPA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define SYNTH13__LOOP_CPA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define SYNTH13__LOOP_CPA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field LOOP_3RD_ORDER_RA_FRACN */ +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__SHIFT 22 +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__WIDTH 5 +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__MASK 0x07c00000U +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field REFDIVA_FRACN */ +#define SYNTH13__REFDIVA_FRACN__SHIFT 27 +#define SYNTH13__REFDIVA_FRACN__WIDTH 5 +#define SYNTH13__REFDIVA_FRACN__MASK 0xf8000000U +#define SYNTH13__REFDIVA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define SYNTH13__REFDIVA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define SYNTH13__REFDIVA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define SYNTH13__REFDIVA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define SYNTH13__TYPE u_int32_t +#define SYNTH13__READ 0xffffffffU +#define SYNTH13__WRITE 0xffffffffU + +#endif /* __SYNTH13_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH13 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH13__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH14 */ +#ifndef __SYNTH14_MACRO__ +#define __SYNTH14_MACRO__ + +/* macros for field SPARE14A */ +#define SYNTH14__SPARE14A__SHIFT 0 +#define SYNTH14__SPARE14A__WIDTH 2 +#define SYNTH14__SPARE14A__MASK 0x00000003U +#define SYNTH14__SPARE14A__READ(src) (u_int32_t)(src) & 0x00000003U +#define SYNTH14__SPARE14A__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define SYNTH14__SPARE14A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SYNTH14__SPARE14A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field LOBUF5GTUNE_3 */ +#define SYNTH14__LOBUF5GTUNE_3__SHIFT 2 +#define SYNTH14__LOBUF5GTUNE_3__WIDTH 2 +#define SYNTH14__LOBUF5GTUNE_3__MASK 0x0000000cU +#define SYNTH14__LOBUF5GTUNE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define SYNTH14__LOBUF5GTUNE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define SYNTH14__LOBUF5GTUNE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define SYNTH14__LOBUF5GTUNE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field LOBUF2GTUNE_3 */ +#define SYNTH14__LOBUF2GTUNE_3__SHIFT 4 +#define SYNTH14__LOBUF2GTUNE_3__WIDTH 2 +#define SYNTH14__LOBUF2GTUNE_3__MASK 0x00000030U +#define SYNTH14__LOBUF2GTUNE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define SYNTH14__LOBUF2GTUNE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define SYNTH14__LOBUF2GTUNE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define SYNTH14__LOBUF2GTUNE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field LOBUF5GTUNE_2 */ +#define SYNTH14__LOBUF5GTUNE_2__SHIFT 6 +#define SYNTH14__LOBUF5GTUNE_2__WIDTH 2 +#define SYNTH14__LOBUF5GTUNE_2__MASK 0x000000c0U +#define SYNTH14__LOBUF5GTUNE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define SYNTH14__LOBUF5GTUNE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define SYNTH14__LOBUF5GTUNE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SYNTH14__LOBUF5GTUNE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field LOBUF2GTUNE_2 */ +#define SYNTH14__LOBUF2GTUNE_2__SHIFT 8 +#define SYNTH14__LOBUF2GTUNE_2__WIDTH 2 +#define SYNTH14__LOBUF2GTUNE_2__MASK 0x00000300U +#define SYNTH14__LOBUF2GTUNE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define SYNTH14__LOBUF2GTUNE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define SYNTH14__LOBUF2GTUNE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define SYNTH14__LOBUF2GTUNE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field PWD_LOBUF5G_3 */ +#define SYNTH14__PWD_LOBUF5G_3__SHIFT 10 +#define SYNTH14__PWD_LOBUF5G_3__WIDTH 1 +#define SYNTH14__PWD_LOBUF5G_3__MASK 0x00000400U +#define SYNTH14__PWD_LOBUF5G_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define SYNTH14__PWD_LOBUF5G_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define SYNTH14__PWD_LOBUF5G_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define SYNTH14__PWD_LOBUF5G_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define SYNTH14__PWD_LOBUF5G_3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define SYNTH14__PWD_LOBUF5G_3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field PWD_LOBUF2G_3 */ +#define SYNTH14__PWD_LOBUF2G_3__SHIFT 11 +#define SYNTH14__PWD_LOBUF2G_3__WIDTH 1 +#define SYNTH14__PWD_LOBUF2G_3__MASK 0x00000800U +#define SYNTH14__PWD_LOBUF2G_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define SYNTH14__PWD_LOBUF2G_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define SYNTH14__PWD_LOBUF2G_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define SYNTH14__PWD_LOBUF2G_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define SYNTH14__PWD_LOBUF2G_3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define SYNTH14__PWD_LOBUF2G_3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field PWD_LOBUF5G_2 */ +#define SYNTH14__PWD_LOBUF5G_2__SHIFT 12 +#define SYNTH14__PWD_LOBUF5G_2__WIDTH 1 +#define SYNTH14__PWD_LOBUF5G_2__MASK 0x00001000U +#define SYNTH14__PWD_LOBUF5G_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define SYNTH14__PWD_LOBUF5G_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define SYNTH14__PWD_LOBUF5G_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define SYNTH14__PWD_LOBUF5G_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define SYNTH14__PWD_LOBUF5G_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define SYNTH14__PWD_LOBUF5G_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field PWD_LOBUF2G_2 */ +#define SYNTH14__PWD_LOBUF2G_2__SHIFT 13 +#define SYNTH14__PWD_LOBUF2G_2__WIDTH 1 +#define SYNTH14__PWD_LOBUF2G_2__MASK 0x00002000U +#define SYNTH14__PWD_LOBUF2G_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define SYNTH14__PWD_LOBUF2G_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define SYNTH14__PWD_LOBUF2G_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define SYNTH14__PWD_LOBUF2G_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define SYNTH14__PWD_LOBUF2G_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define SYNTH14__PWD_LOBUF2G_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field PWUPLO23_PD */ +#define SYNTH14__PWUPLO23_PD__SHIFT 14 +#define SYNTH14__PWUPLO23_PD__WIDTH 3 +#define SYNTH14__PWUPLO23_PD__MASK 0x0001c000U +#define SYNTH14__PWUPLO23_PD__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define SYNTH14__PWUPLO23_PD__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define SYNTH14__PWUPLO23_PD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define SYNTH14__PWUPLO23_PD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field PWDB_ICLOBUF5G50_3 */ +#define SYNTH14__PWDB_ICLOBUF5G50_3__SHIFT 17 +#define SYNTH14__PWDB_ICLOBUF5G50_3__WIDTH 3 +#define SYNTH14__PWDB_ICLOBUF5G50_3__MASK 0x000e0000U +#define SYNTH14__PWDB_ICLOBUF5G50_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define SYNTH14__PWDB_ICLOBUF5G50_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define SYNTH14__PWDB_ICLOBUF5G50_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define SYNTH14__PWDB_ICLOBUF5G50_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field PWDB_ICLOBUF2G50_3 */ +#define SYNTH14__PWDB_ICLOBUF2G50_3__SHIFT 20 +#define SYNTH14__PWDB_ICLOBUF2G50_3__WIDTH 3 +#define SYNTH14__PWDB_ICLOBUF2G50_3__MASK 0x00700000U +#define SYNTH14__PWDB_ICLOBUF2G50_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define SYNTH14__PWDB_ICLOBUF2G50_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define SYNTH14__PWDB_ICLOBUF2G50_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define SYNTH14__PWDB_ICLOBUF2G50_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field PWDB_ICLOBUF5G50_2 */ +#define SYNTH14__PWDB_ICLOBUF5G50_2__SHIFT 23 +#define SYNTH14__PWDB_ICLOBUF5G50_2__WIDTH 3 +#define SYNTH14__PWDB_ICLOBUF5G50_2__MASK 0x03800000U +#define SYNTH14__PWDB_ICLOBUF5G50_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define SYNTH14__PWDB_ICLOBUF5G50_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define SYNTH14__PWDB_ICLOBUF5G50_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define SYNTH14__PWDB_ICLOBUF5G50_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field PWDB_ICLOBUF2G50_2 */ +#define SYNTH14__PWDB_ICLOBUF2G50_2__SHIFT 26 +#define SYNTH14__PWDB_ICLOBUF2G50_2__WIDTH 3 +#define SYNTH14__PWDB_ICLOBUF2G50_2__MASK 0x1c000000U +#define SYNTH14__PWDB_ICLOBUF2G50_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define SYNTH14__PWDB_ICLOBUF2G50_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define SYNTH14__PWDB_ICLOBUF2G50_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define SYNTH14__PWDB_ICLOBUF2G50_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field PWDB_ICLVLSHFT */ +#define SYNTH14__PWDB_ICLVLSHFT__SHIFT 29 +#define SYNTH14__PWDB_ICLVLSHFT__WIDTH 3 +#define SYNTH14__PWDB_ICLVLSHFT__MASK 0xe0000000U +#define SYNTH14__PWDB_ICLVLSHFT__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define SYNTH14__PWDB_ICLVLSHFT__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define SYNTH14__PWDB_ICLVLSHFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define SYNTH14__PWDB_ICLVLSHFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define SYNTH14__TYPE u_int32_t +#define SYNTH14__READ 0xffffffffU +#define SYNTH14__WRITE 0xffffffffU + +#endif /* __SYNTH14_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_SYNTH14 */ +#define INST_RADIO65_REG_BLOCK__CH0_SYNTH14__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BIAS1 */ +#ifndef __BIAS1_MACRO__ +#define __BIAS1_MACRO__ + +/* macros for field SPARE1 */ +#define BIAS1__SPARE1__SHIFT 0 +#define BIAS1__SPARE1__WIDTH 3 +#define BIAS1__SPARE1__MASK 0x00000007U +#define BIAS1__SPARE1__READ(src) (u_int32_t)(src) & 0x00000007U +#define BIAS1__SPARE1__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define BIAS1__SPARE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define BIAS1__SPARE1__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) + +/* macros for field pwd_ic100pcie */ +#define BIAS1__PWD_IC100PCIE__SHIFT 3 +#define BIAS1__PWD_IC100PCIE__WIDTH 3 +#define BIAS1__PWD_IC100PCIE__MASK 0x00000038U +#define BIAS1__PWD_IC100PCIE__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3) +#define BIAS1__PWD_IC100PCIE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define BIAS1__PWD_IC100PCIE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define BIAS1__PWD_IC100PCIE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field pwd_ic25v2iQ */ +#define BIAS1__PWD_IC25V2IQ__SHIFT 6 +#define BIAS1__PWD_IC25V2IQ__WIDTH 3 +#define BIAS1__PWD_IC25V2IQ__MASK 0x000001c0U +#define BIAS1__PWD_IC25V2IQ__READ(src) (((u_int32_t)(src) & 0x000001c0U) >> 6) +#define BIAS1__PWD_IC25V2IQ__WRITE(src) (((u_int32_t)(src) << 6) & 0x000001c0U) +#define BIAS1__PWD_IC25V2IQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define BIAS1__PWD_IC25V2IQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field pwd_ic25v2iI */ +#define BIAS1__PWD_IC25V2II__SHIFT 9 +#define BIAS1__PWD_IC25V2II__WIDTH 3 +#define BIAS1__PWD_IC25V2II__MASK 0x00000e00U +#define BIAS1__PWD_IC25V2II__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) +#define BIAS1__PWD_IC25V2II__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U) +#define BIAS1__PWD_IC25V2II__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define BIAS1__PWD_IC25V2II__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field pwd_ic25bb */ +#define BIAS1__PWD_IC25BB__SHIFT 12 +#define BIAS1__PWD_IC25BB__WIDTH 3 +#define BIAS1__PWD_IC25BB__MASK 0x00007000U +#define BIAS1__PWD_IC25BB__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12) +#define BIAS1__PWD_IC25BB__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U) +#define BIAS1__PWD_IC25BB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define BIAS1__PWD_IC25BB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field pwd_ic25dac */ +#define BIAS1__PWD_IC25DAC__SHIFT 15 +#define BIAS1__PWD_IC25DAC__WIDTH 3 +#define BIAS1__PWD_IC25DAC__MASK 0x00038000U +#define BIAS1__PWD_IC25DAC__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) +#define BIAS1__PWD_IC25DAC__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) +#define BIAS1__PWD_IC25DAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define BIAS1__PWD_IC25DAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field pwd_ic25fir */ +#define BIAS1__PWD_IC25FIR__SHIFT 18 +#define BIAS1__PWD_IC25FIR__WIDTH 3 +#define BIAS1__PWD_IC25FIR__MASK 0x001c0000U +#define BIAS1__PWD_IC25FIR__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18) +#define BIAS1__PWD_IC25FIR__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U) +#define BIAS1__PWD_IC25FIR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define BIAS1__PWD_IC25FIR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field pwd_ic25adc */ +#define BIAS1__PWD_IC25ADC__SHIFT 21 +#define BIAS1__PWD_IC25ADC__WIDTH 3 +#define BIAS1__PWD_IC25ADC__MASK 0x00e00000U +#define BIAS1__PWD_IC25ADC__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21) +#define BIAS1__PWD_IC25ADC__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U) +#define BIAS1__PWD_IC25ADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define BIAS1__PWD_IC25ADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field bias_sel */ +#define BIAS1__BIAS_SEL__SHIFT 24 +#define BIAS1__BIAS_SEL__WIDTH 8 +#define BIAS1__BIAS_SEL__MASK 0xff000000U +#define BIAS1__BIAS_SEL__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) +#define BIAS1__BIAS_SEL__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) +#define BIAS1__BIAS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define BIAS1__BIAS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define BIAS1__TYPE u_int32_t +#define BIAS1__READ 0xffffffffU +#define BIAS1__WRITE 0xffffffffU + +#endif /* __BIAS1_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_BIAS1 */ +#define INST_RADIO65_REG_BLOCK__CH0_BIAS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BIAS2 */ +#ifndef __BIAS2_MACRO__ +#define __BIAS2_MACRO__ + +/* macros for field SPARE2 */ +#define BIAS2__SPARE2__SHIFT 0 +#define BIAS2__SPARE2__WIDTH 5 +#define BIAS2__SPARE2__MASK 0x0000001fU +#define BIAS2__SPARE2__READ(src) (u_int32_t)(src) & 0x0000001fU +#define BIAS2__SPARE2__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define BIAS2__SPARE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define BIAS2__SPARE2__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field pwd_ic25xtalreg */ +#define BIAS2__PWD_IC25XTALREG__SHIFT 5 +#define BIAS2__PWD_IC25XTALREG__WIDTH 3 +#define BIAS2__PWD_IC25XTALREG__MASK 0x000000e0U +#define BIAS2__PWD_IC25XTALREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define BIAS2__PWD_IC25XTALREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define BIAS2__PWD_IC25XTALREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define BIAS2__PWD_IC25XTALREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field pwd_ic25xtal */ +#define BIAS2__PWD_IC25XTAL__SHIFT 8 +#define BIAS2__PWD_IC25XTAL__WIDTH 3 +#define BIAS2__PWD_IC25XTAL__MASK 0x00000700U +#define BIAS2__PWD_IC25XTAL__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) +#define BIAS2__PWD_IC25XTAL__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U) +#define BIAS2__PWD_IC25XTAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define BIAS2__PWD_IC25XTAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field pwd_ic25txrf */ +#define BIAS2__PWD_IC25TXRF__SHIFT 11 +#define BIAS2__PWD_IC25TXRF__WIDTH 3 +#define BIAS2__PWD_IC25TXRF__MASK 0x00003800U +#define BIAS2__PWD_IC25TXRF__READ(src) (((u_int32_t)(src) & 0x00003800U) >> 11) +#define BIAS2__PWD_IC25TXRF__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define BIAS2__PWD_IC25TXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define BIAS2__PWD_IC25TXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field pwd_ic25rxrf */ +#define BIAS2__PWD_IC25RXRF__SHIFT 14 +#define BIAS2__PWD_IC25RXRF__WIDTH 3 +#define BIAS2__PWD_IC25RXRF__MASK 0x0001c000U +#define BIAS2__PWD_IC25RXRF__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) +#define BIAS2__PWD_IC25RXRF__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define BIAS2__PWD_IC25RXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define BIAS2__PWD_IC25RXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field pwd_ic25synth */ +#define BIAS2__PWD_IC25SYNTH__SHIFT 17 +#define BIAS2__PWD_IC25SYNTH__WIDTH 3 +#define BIAS2__PWD_IC25SYNTH__MASK 0x000e0000U +#define BIAS2__PWD_IC25SYNTH__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define BIAS2__PWD_IC25SYNTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define BIAS2__PWD_IC25SYNTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define BIAS2__PWD_IC25SYNTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field pwd_ic25pllreg */ +#define BIAS2__PWD_IC25PLLREG__SHIFT 20 +#define BIAS2__PWD_IC25PLLREG__WIDTH 3 +#define BIAS2__PWD_IC25PLLREG__MASK 0x00700000U +#define BIAS2__PWD_IC25PLLREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define BIAS2__PWD_IC25PLLREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define BIAS2__PWD_IC25PLLREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define BIAS2__PWD_IC25PLLREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field pwd_ic25pllcp2 */ +#define BIAS2__PWD_IC25PLLCP2__SHIFT 23 +#define BIAS2__PWD_IC25PLLCP2__WIDTH 3 +#define BIAS2__PWD_IC25PLLCP2__MASK 0x03800000U +#define BIAS2__PWD_IC25PLLCP2__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define BIAS2__PWD_IC25PLLCP2__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define BIAS2__PWD_IC25PLLCP2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define BIAS2__PWD_IC25PLLCP2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field pwd_ic25pllcp */ +#define BIAS2__PWD_IC25PLLCP__SHIFT 26 +#define BIAS2__PWD_IC25PLLCP__WIDTH 3 +#define BIAS2__PWD_IC25PLLCP__MASK 0x1c000000U +#define BIAS2__PWD_IC25PLLCP__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define BIAS2__PWD_IC25PLLCP__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define BIAS2__PWD_IC25PLLCP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define BIAS2__PWD_IC25PLLCP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field pwd_ic25pllgm */ +#define BIAS2__PWD_IC25PLLGM__SHIFT 29 +#define BIAS2__PWD_IC25PLLGM__WIDTH 3 +#define BIAS2__PWD_IC25PLLGM__MASK 0xe0000000U +#define BIAS2__PWD_IC25PLLGM__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define BIAS2__PWD_IC25PLLGM__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define BIAS2__PWD_IC25PLLGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define BIAS2__PWD_IC25PLLGM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define BIAS2__TYPE u_int32_t +#define BIAS2__READ 0xffffffffU +#define BIAS2__WRITE 0xffffffffU + +#endif /* __BIAS2_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_BIAS2 */ +#define INST_RADIO65_REG_BLOCK__CH0_BIAS2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BIAS3 */ +#ifndef __BIAS3_MACRO__ +#define __BIAS3_MACRO__ + +/* macros for field SPARE3 */ +#define BIAS3__SPARE3__SHIFT 0 +#define BIAS3__SPARE3__WIDTH 2 +#define BIAS3__SPARE3__MASK 0x00000003U +#define BIAS3__SPARE3__READ(src) (u_int32_t)(src) & 0x00000003U +#define BIAS3__SPARE3__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define BIAS3__SPARE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define BIAS3__SPARE3__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field pwd_ir25xtalreg */ +#define BIAS3__PWD_IR25XTALREG__SHIFT 2 +#define BIAS3__PWD_IR25XTALREG__WIDTH 3 +#define BIAS3__PWD_IR25XTALREG__MASK 0x0000001cU +#define BIAS3__PWD_IR25XTALREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define BIAS3__PWD_IR25XTALREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define BIAS3__PWD_IR25XTALREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define BIAS3__PWD_IR25XTALREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field pwd_ir25txrf */ +#define BIAS3__PWD_IR25TXRF__SHIFT 5 +#define BIAS3__PWD_IR25TXRF__WIDTH 3 +#define BIAS3__PWD_IR25TXRF__MASK 0x000000e0U +#define BIAS3__PWD_IR25TXRF__READ(src) (((u_int32_t)(src) & 0x000000e0U) >> 5) +#define BIAS3__PWD_IR25TXRF__WRITE(src) (((u_int32_t)(src) << 5) & 0x000000e0U) +#define BIAS3__PWD_IR25TXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define BIAS3__PWD_IR25TXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field pwd_ir25rxrf */ +#define BIAS3__PWD_IR25RXRF__SHIFT 8 +#define BIAS3__PWD_IR25RXRF__WIDTH 3 +#define BIAS3__PWD_IR25RXRF__MASK 0x00000700U +#define BIAS3__PWD_IR25RXRF__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) +#define BIAS3__PWD_IR25RXRF__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U) +#define BIAS3__PWD_IR25RXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define BIAS3__PWD_IR25RXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field pwd_ir25synth */ +#define BIAS3__PWD_IR25SYNTH__SHIFT 11 +#define BIAS3__PWD_IR25SYNTH__WIDTH 3 +#define BIAS3__PWD_IR25SYNTH__MASK 0x00003800U +#define BIAS3__PWD_IR25SYNTH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define BIAS3__PWD_IR25SYNTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define BIAS3__PWD_IR25SYNTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define BIAS3__PWD_IR25SYNTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field pwd_ir25pllreg */ +#define BIAS3__PWD_IR25PLLREG__SHIFT 14 +#define BIAS3__PWD_IR25PLLREG__WIDTH 3 +#define BIAS3__PWD_IR25PLLREG__MASK 0x0001c000U +#define BIAS3__PWD_IR25PLLREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define BIAS3__PWD_IR25PLLREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define BIAS3__PWD_IR25PLLREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define BIAS3__PWD_IR25PLLREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field pwd_ir25bb */ +#define BIAS3__PWD_IR25BB__SHIFT 17 +#define BIAS3__PWD_IR25BB__WIDTH 3 +#define BIAS3__PWD_IR25BB__MASK 0x000e0000U +#define BIAS3__PWD_IR25BB__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) +#define BIAS3__PWD_IR25BB__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) +#define BIAS3__PWD_IR25BB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define BIAS3__PWD_IR25BB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field pwd_ir50dac */ +#define BIAS3__PWD_IR50DAC__SHIFT 20 +#define BIAS3__PWD_IR50DAC__WIDTH 3 +#define BIAS3__PWD_IR50DAC__MASK 0x00700000U +#define BIAS3__PWD_IR50DAC__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) +#define BIAS3__PWD_IR50DAC__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) +#define BIAS3__PWD_IR50DAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define BIAS3__PWD_IR50DAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field pwd_ir25dac */ +#define BIAS3__PWD_IR25DAC__SHIFT 23 +#define BIAS3__PWD_IR25DAC__WIDTH 3 +#define BIAS3__PWD_IR25DAC__MASK 0x03800000U +#define BIAS3__PWD_IR25DAC__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) +#define BIAS3__PWD_IR25DAC__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) +#define BIAS3__PWD_IR25DAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define BIAS3__PWD_IR25DAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field pwd_ir25fir */ +#define BIAS3__PWD_IR25FIR__SHIFT 26 +#define BIAS3__PWD_IR25FIR__WIDTH 3 +#define BIAS3__PWD_IR25FIR__MASK 0x1c000000U +#define BIAS3__PWD_IR25FIR__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define BIAS3__PWD_IR25FIR__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define BIAS3__PWD_IR25FIR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define BIAS3__PWD_IR25FIR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field pwd_ir50adc */ +#define BIAS3__PWD_IR50ADC__SHIFT 29 +#define BIAS3__PWD_IR50ADC__WIDTH 3 +#define BIAS3__PWD_IR50ADC__MASK 0xe0000000U +#define BIAS3__PWD_IR50ADC__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define BIAS3__PWD_IR50ADC__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define BIAS3__PWD_IR50ADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define BIAS3__PWD_IR50ADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define BIAS3__TYPE u_int32_t +#define BIAS3__READ 0xffffffffU +#define BIAS3__WRITE 0xffffffffU + +#endif /* __BIAS3_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_BIAS3 */ +#define INST_RADIO65_REG_BLOCK__CH0_BIAS3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BIAS4 */ +#ifndef __BIAS4_MACRO__ +#define __BIAS4_MACRO__ + +/* macros for field SPARE4 */ +#define BIAS4__SPARE4__SHIFT 0 +#define BIAS4__SPARE4__WIDTH 14 +#define BIAS4__SPARE4__MASK 0x00003fffU +#define BIAS4__SPARE4__READ(src) (u_int32_t)(src) & 0x00003fffU +#define BIAS4__SPARE4__WRITE(src) ((u_int32_t)(src) & 0x00003fffU) +#define BIAS4__SPARE4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define BIAS4__SPARE4__VERIFY(src) (!(((u_int32_t)(src) & ~0x00003fffU))) + +/* macros for field pwd_ir25xpabias */ +#define BIAS4__PWD_IR25XPABIAS__SHIFT 14 +#define BIAS4__PWD_IR25XPABIAS__WIDTH 3 +#define BIAS4__PWD_IR25XPABIAS__MASK 0x0001c000U +#define BIAS4__PWD_IR25XPABIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define BIAS4__PWD_IR25XPABIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define BIAS4__PWD_IR25XPABIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define BIAS4__PWD_IR25XPABIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field pwd_ir25thermadc */ +#define BIAS4__PWD_IR25THERMADC__SHIFT 17 +#define BIAS4__PWD_IR25THERMADC__WIDTH 3 +#define BIAS4__PWD_IR25THERMADC__MASK 0x000e0000U +#define BIAS4__PWD_IR25THERMADC__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define BIAS4__PWD_IR25THERMADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define BIAS4__PWD_IR25THERMADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define BIAS4__PWD_IR25THERMADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field pwd_ir25otpreg */ +#define BIAS4__PWD_IR25OTPREG__SHIFT 20 +#define BIAS4__PWD_IR25OTPREG__WIDTH 3 +#define BIAS4__PWD_IR25OTPREG__MASK 0x00700000U +#define BIAS4__PWD_IR25OTPREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define BIAS4__PWD_IR25OTPREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define BIAS4__PWD_IR25OTPREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define BIAS4__PWD_IR25OTPREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field pwd_ic25xpabias */ +#define BIAS4__PWD_IC25XPABIAS__SHIFT 23 +#define BIAS4__PWD_IC25XPABIAS__WIDTH 3 +#define BIAS4__PWD_IC25XPABIAS__MASK 0x03800000U +#define BIAS4__PWD_IC25XPABIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define BIAS4__PWD_IC25XPABIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define BIAS4__PWD_IC25XPABIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define BIAS4__PWD_IC25XPABIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field pwd_ic25spareB */ +#define BIAS4__PWD_IC25SPAREB__SHIFT 26 +#define BIAS4__PWD_IC25SPAREB__WIDTH 3 +#define BIAS4__PWD_IC25SPAREB__MASK 0x1c000000U +#define BIAS4__PWD_IC25SPAREB__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define BIAS4__PWD_IC25SPAREB__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define BIAS4__PWD_IC25SPAREB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define BIAS4__PWD_IC25SPAREB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field pwd_ic25spareA */ +#define BIAS4__PWD_IC25SPAREA__SHIFT 29 +#define BIAS4__PWD_IC25SPAREA__WIDTH 3 +#define BIAS4__PWD_IC25SPAREA__MASK 0xe0000000U +#define BIAS4__PWD_IC25SPAREA__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define BIAS4__PWD_IC25SPAREA__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define BIAS4__PWD_IC25SPAREA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define BIAS4__PWD_IC25SPAREA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define BIAS4__TYPE u_int32_t +#define BIAS4__READ 0xffffffffU +#define BIAS4__WRITE 0xffffffffU + +#endif /* __BIAS4_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_BIAS4 */ +#define INST_RADIO65_REG_BLOCK__CH0_BIAS4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXTX1 */ +#ifndef __RXTX1_MACRO__ +#define __RXTX1_MACRO__ + +/* macros for field scfir_gain */ +#define RXTX1__SCFIR_GAIN__SHIFT 0 +#define RXTX1__SCFIR_GAIN__WIDTH 1 +#define RXTX1__SCFIR_GAIN__MASK 0x00000001U +#define RXTX1__SCFIR_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXTX1__SCFIR_GAIN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXTX1__SCFIR_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXTX1__SCFIR_GAIN__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define RXTX1__SCFIR_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXTX1__SCFIR_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field manrxgain */ +#define RXTX1__MANRXGAIN__SHIFT 1 +#define RXTX1__MANRXGAIN__WIDTH 1 +#define RXTX1__MANRXGAIN__MASK 0x00000002U +#define RXTX1__MANRXGAIN__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define RXTX1__MANRXGAIN__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define RXTX1__MANRXGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RXTX1__MANRXGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RXTX1__MANRXGAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RXTX1__MANRXGAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field agc_dbdac */ +#define RXTX1__AGC_DBDAC__SHIFT 2 +#define RXTX1__AGC_DBDAC__WIDTH 4 +#define RXTX1__AGC_DBDAC__MASK 0x0000003cU +#define RXTX1__AGC_DBDAC__READ(src) (((u_int32_t)(src) & 0x0000003cU) >> 2) +#define RXTX1__AGC_DBDAC__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000003cU) +#define RXTX1__AGC_DBDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000003cU) +#define RXTX1__AGC_DBDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000003cU))) + +/* macros for field ovr_agc_dbdac */ +#define RXTX1__OVR_AGC_DBDAC__SHIFT 6 +#define RXTX1__OVR_AGC_DBDAC__WIDTH 1 +#define RXTX1__OVR_AGC_DBDAC__MASK 0x00000040U +#define RXTX1__OVR_AGC_DBDAC__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define RXTX1__OVR_AGC_DBDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RXTX1__OVR_AGC_DBDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RXTX1__OVR_AGC_DBDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RXTX1__OVR_AGC_DBDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RXTX1__OVR_AGC_DBDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field enable_PAL */ +#define RXTX1__ENABLE_PAL__SHIFT 7 +#define RXTX1__ENABLE_PAL__WIDTH 1 +#define RXTX1__ENABLE_PAL__MASK 0x00000080U +#define RXTX1__ENABLE_PAL__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define RXTX1__ENABLE_PAL__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) +#define RXTX1__ENABLE_PAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RXTX1__ENABLE_PAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RXTX1__ENABLE_PAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RXTX1__ENABLE_PAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field enable_PAL_ovr */ +#define RXTX1__ENABLE_PAL_OVR__SHIFT 8 +#define RXTX1__ENABLE_PAL_OVR__WIDTH 1 +#define RXTX1__ENABLE_PAL_OVR__MASK 0x00000100U +#define RXTX1__ENABLE_PAL_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define RXTX1__ENABLE_PAL_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define RXTX1__ENABLE_PAL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RXTX1__ENABLE_PAL_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RXTX1__ENABLE_PAL_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RXTX1__ENABLE_PAL_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field tx1db_biquad */ +#define RXTX1__TX1DB_BIQUAD__SHIFT 9 +#define RXTX1__TX1DB_BIQUAD__WIDTH 3 +#define RXTX1__TX1DB_BIQUAD__MASK 0x00000e00U +#define RXTX1__TX1DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) +#define RXTX1__TX1DB_BIQUAD__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U) +#define RXTX1__TX1DB_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define RXTX1__TX1DB_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field tx6db_biquad */ +#define RXTX1__TX6DB_BIQUAD__SHIFT 12 +#define RXTX1__TX6DB_BIQUAD__WIDTH 2 +#define RXTX1__TX6DB_BIQUAD__MASK 0x00003000U +#define RXTX1__TX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00003000U) >> 12) +#define RXTX1__TX6DB_BIQUAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00003000U) +#define RXTX1__TX6DB_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((u_int32_t)(src) <<\ + 12) & 0x00003000U) +#define RXTX1__TX6DB_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00003000U))) + +/* macros for field padrvhalfgn2g */ +#define RXTX1__PADRVHALFGN2G__SHIFT 14 +#define RXTX1__PADRVHALFGN2G__WIDTH 1 +#define RXTX1__PADRVHALFGN2G__MASK 0x00004000U +#define RXTX1__PADRVHALFGN2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RXTX1__PADRVHALFGN2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RXTX1__PADRVHALFGN2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RXTX1__PADRVHALFGN2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RXTX1__PADRVHALFGN2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RXTX1__PADRVHALFGN2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field padrv2gn */ +#define RXTX1__PADRV2GN__SHIFT 15 +#define RXTX1__PADRV2GN__WIDTH 4 +#define RXTX1__PADRV2GN__MASK 0x00078000U +#define RXTX1__PADRV2GN__READ(src) (((u_int32_t)(src) & 0x00078000U) >> 15) +#define RXTX1__PADRV2GN__WRITE(src) (((u_int32_t)(src) << 15) & 0x00078000U) +#define RXTX1__PADRV2GN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00078000U) | (((u_int32_t)(src) <<\ + 15) & 0x00078000U) +#define RXTX1__PADRV2GN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00078000U))) + +/* macros for field padrv3gn5g */ +#define RXTX1__PADRV3GN5G__SHIFT 19 +#define RXTX1__PADRV3GN5G__WIDTH 4 +#define RXTX1__PADRV3GN5G__MASK 0x00780000U +#define RXTX1__PADRV3GN5G__READ(src) (((u_int32_t)(src) & 0x00780000U) >> 19) +#define RXTX1__PADRV3GN5G__WRITE(src) (((u_int32_t)(src) << 19) & 0x00780000U) +#define RXTX1__PADRV3GN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00780000U) | (((u_int32_t)(src) <<\ + 19) & 0x00780000U) +#define RXTX1__PADRV3GN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00780000U))) + +/* macros for field padrv4gn5g */ +#define RXTX1__PADRV4GN5G__SHIFT 23 +#define RXTX1__PADRV4GN5G__WIDTH 4 +#define RXTX1__PADRV4GN5G__MASK 0x07800000U +#define RXTX1__PADRV4GN5G__READ(src) (((u_int32_t)(src) & 0x07800000U) >> 23) +#define RXTX1__PADRV4GN5G__WRITE(src) (((u_int32_t)(src) << 23) & 0x07800000U) +#define RXTX1__PADRV4GN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07800000U) | (((u_int32_t)(src) <<\ + 23) & 0x07800000U) +#define RXTX1__PADRV4GN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x07800000U))) + +/* macros for field txbb_gc */ +#define RXTX1__TXBB_GC__SHIFT 27 +#define RXTX1__TXBB_GC__WIDTH 4 +#define RXTX1__TXBB_GC__MASK 0x78000000U +#define RXTX1__TXBB_GC__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define RXTX1__TXBB_GC__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define RXTX1__TXBB_GC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define RXTX1__TXBB_GC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) + +/* macros for field mantxgain */ +#define RXTX1__MANTXGAIN__SHIFT 31 +#define RXTX1__MANTXGAIN__WIDTH 1 +#define RXTX1__MANTXGAIN__MASK 0x80000000U +#define RXTX1__MANTXGAIN__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define RXTX1__MANTXGAIN__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) +#define RXTX1__MANTXGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RXTX1__MANTXGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RXTX1__MANTXGAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RXTX1__MANTXGAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RXTX1__TYPE u_int32_t +#define RXTX1__READ 0xffffffffU +#define RXTX1__WRITE 0xffffffffU + +#endif /* __RXTX1_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_RXTX1 */ +#define INST_RADIO65_REG_BLOCK__CH0_RXTX1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXTX2 */ +#ifndef __RXTX2_MACRO__ +#define __RXTX2_MACRO__ + +/* macros for field bmode */ +#define RXTX2__BMODE__SHIFT 0 +#define RXTX2__BMODE__WIDTH 1 +#define RXTX2__BMODE__MASK 0x00000001U +#define RXTX2__BMODE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXTX2__BMODE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXTX2__BMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXTX2__BMODE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define RXTX2__BMODE__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define RXTX2__BMODE__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) + +/* macros for field bmode_ovr */ +#define RXTX2__BMODE_OVR__SHIFT 1 +#define RXTX2__BMODE_OVR__WIDTH 1 +#define RXTX2__BMODE_OVR__MASK 0x00000002U +#define RXTX2__BMODE_OVR__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define RXTX2__BMODE_OVR__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define RXTX2__BMODE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RXTX2__BMODE_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RXTX2__BMODE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RXTX2__BMODE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field synthon */ +#define RXTX2__SYNTHON__SHIFT 2 +#define RXTX2__SYNTHON__WIDTH 1 +#define RXTX2__SYNTHON__MASK 0x00000004U +#define RXTX2__SYNTHON__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define RXTX2__SYNTHON__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define RXTX2__SYNTHON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RXTX2__SYNTHON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RXTX2__SYNTHON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RXTX2__SYNTHON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field synthon_ovr */ +#define RXTX2__SYNTHON_OVR__SHIFT 3 +#define RXTX2__SYNTHON_OVR__WIDTH 1 +#define RXTX2__SYNTHON_OVR__MASK 0x00000008U +#define RXTX2__SYNTHON_OVR__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define RXTX2__SYNTHON_OVR__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define RXTX2__SYNTHON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RXTX2__SYNTHON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RXTX2__SYNTHON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RXTX2__SYNTHON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BW_ST */ +#define RXTX2__BW_ST__SHIFT 4 +#define RXTX2__BW_ST__WIDTH 2 +#define RXTX2__BW_ST__MASK 0x00000030U +#define RXTX2__BW_ST__READ(src) (((u_int32_t)(src) & 0x00000030U) >> 4) +#define RXTX2__BW_ST__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000030U) +#define RXTX2__BW_ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define RXTX2__BW_ST__VERIFY(src) (!((((u_int32_t)(src) << 4) & ~0x00000030U))) + +/* macros for field BW_ST_ovr */ +#define RXTX2__BW_ST_OVR__SHIFT 6 +#define RXTX2__BW_ST_OVR__WIDTH 1 +#define RXTX2__BW_ST_OVR__MASK 0x00000040U +#define RXTX2__BW_ST_OVR__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define RXTX2__BW_ST_OVR__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) +#define RXTX2__BW_ST_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RXTX2__BW_ST_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RXTX2__BW_ST_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RXTX2__BW_ST_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field txon_ovr */ +#define RXTX2__TXON_OVR__SHIFT 7 +#define RXTX2__TXON_OVR__WIDTH 1 +#define RXTX2__TXON_OVR__MASK 0x00000080U +#define RXTX2__TXON_OVR__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define RXTX2__TXON_OVR__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) +#define RXTX2__TXON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RXTX2__TXON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RXTX2__TXON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RXTX2__TXON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field txon */ +#define RXTX2__TXON__SHIFT 8 +#define RXTX2__TXON__WIDTH 1 +#define RXTX2__TXON__MASK 0x00000100U +#define RXTX2__TXON__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define RXTX2__TXON__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) +#define RXTX2__TXON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RXTX2__TXON__VERIFY(src) (!((((u_int32_t)(src) << 8) & ~0x00000100U))) +#define RXTX2__TXON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RXTX2__TXON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field paon */ +#define RXTX2__PAON__SHIFT 9 +#define RXTX2__PAON__WIDTH 1 +#define RXTX2__PAON__MASK 0x00000200U +#define RXTX2__PAON__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define RXTX2__PAON__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) +#define RXTX2__PAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define RXTX2__PAON__VERIFY(src) (!((((u_int32_t)(src) << 9) & ~0x00000200U))) +#define RXTX2__PAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define RXTX2__PAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field paon_ovr */ +#define RXTX2__PAON_OVR__SHIFT 10 +#define RXTX2__PAON_OVR__WIDTH 1 +#define RXTX2__PAON_OVR__MASK 0x00000400U +#define RXTX2__PAON_OVR__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define RXTX2__PAON_OVR__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) +#define RXTX2__PAON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RXTX2__PAON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RXTX2__PAON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RXTX2__PAON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field rxon */ +#define RXTX2__RXON__SHIFT 11 +#define RXTX2__RXON__WIDTH 1 +#define RXTX2__RXON__MASK 0x00000800U +#define RXTX2__RXON__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define RXTX2__RXON__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define RXTX2__RXON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define RXTX2__RXON__VERIFY(src) (!((((u_int32_t)(src) << 11) & ~0x00000800U))) +#define RXTX2__RXON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define RXTX2__RXON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field rxon_ovr */ +#define RXTX2__RXON_OVR__SHIFT 12 +#define RXTX2__RXON_OVR__WIDTH 1 +#define RXTX2__RXON_OVR__MASK 0x00001000U +#define RXTX2__RXON_OVR__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) +#define RXTX2__RXON_OVR__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) +#define RXTX2__RXON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define RXTX2__RXON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define RXTX2__RXON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define RXTX2__RXON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field agcon */ +#define RXTX2__AGCON__SHIFT 13 +#define RXTX2__AGCON__WIDTH 1 +#define RXTX2__AGCON__MASK 0x00002000U +#define RXTX2__AGCON__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) +#define RXTX2__AGCON__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U) +#define RXTX2__AGCON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RXTX2__AGCON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RXTX2__AGCON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RXTX2__AGCON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field agcon_ovr */ +#define RXTX2__AGCON_OVR__SHIFT 14 +#define RXTX2__AGCON_OVR__WIDTH 1 +#define RXTX2__AGCON_OVR__MASK 0x00004000U +#define RXTX2__AGCON_OVR__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) +#define RXTX2__AGCON_OVR__WRITE(src) (((u_int32_t)(src) << 14) & 0x00004000U) +#define RXTX2__AGCON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RXTX2__AGCON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RXTX2__AGCON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RXTX2__AGCON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field txmod */ +#define RXTX2__TXMOD__SHIFT 15 +#define RXTX2__TXMOD__WIDTH 3 +#define RXTX2__TXMOD__MASK 0x00038000U +#define RXTX2__TXMOD__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) +#define RXTX2__TXMOD__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) +#define RXTX2__TXMOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define RXTX2__TXMOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field txmod_ovr */ +#define RXTX2__TXMOD_OVR__SHIFT 18 +#define RXTX2__TXMOD_OVR__WIDTH 1 +#define RXTX2__TXMOD_OVR__MASK 0x00040000U +#define RXTX2__TXMOD_OVR__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define RXTX2__TXMOD_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define RXTX2__TXMOD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define RXTX2__TXMOD_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define RXTX2__TXMOD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define RXTX2__TXMOD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field rx1db_biquad */ +#define RXTX2__RX1DB_BIQUAD__SHIFT 19 +#define RXTX2__RX1DB_BIQUAD__WIDTH 3 +#define RXTX2__RX1DB_BIQUAD__MASK 0x00380000U +#define RXTX2__RX1DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00380000U) >> 19) +#define RXTX2__RX1DB_BIQUAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define RXTX2__RX1DB_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define RXTX2__RX1DB_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field rx6db_biquad */ +#define RXTX2__RX6DB_BIQUAD__SHIFT 22 +#define RXTX2__RX6DB_BIQUAD__WIDTH 2 +#define RXTX2__RX6DB_BIQUAD__MASK 0x00c00000U +#define RXTX2__RX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00c00000U) >> 22) +#define RXTX2__RX6DB_BIQUAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00c00000U) +#define RXTX2__RX6DB_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x00c00000U) +#define RXTX2__RX6DB_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00c00000U))) + +/* macros for field mxrgain */ +#define RXTX2__MXRGAIN__SHIFT 24 +#define RXTX2__MXRGAIN__WIDTH 2 +#define RXTX2__MXRGAIN__MASK 0x03000000U +#define RXTX2__MXRGAIN__READ(src) (((u_int32_t)(src) & 0x03000000U) >> 24) +#define RXTX2__MXRGAIN__WRITE(src) (((u_int32_t)(src) << 24) & 0x03000000U) +#define RXTX2__MXRGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define RXTX2__MXRGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field vgagain */ +#define RXTX2__VGAGAIN__SHIFT 26 +#define RXTX2__VGAGAIN__WIDTH 3 +#define RXTX2__VGAGAIN__MASK 0x1c000000U +#define RXTX2__VGAGAIN__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define RXTX2__VGAGAIN__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define RXTX2__VGAGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RXTX2__VGAGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field lnagain */ +#define RXTX2__LNAGAIN__SHIFT 29 +#define RXTX2__LNAGAIN__WIDTH 3 +#define RXTX2__LNAGAIN__MASK 0xe0000000U +#define RXTX2__LNAGAIN__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define RXTX2__LNAGAIN__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define RXTX2__LNAGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RXTX2__LNAGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RXTX2__TYPE u_int32_t +#define RXTX2__READ 0xffffffffU +#define RXTX2__WRITE 0xffffffffU + +#endif /* __RXTX2_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_RXTX2 */ +#define INST_RADIO65_REG_BLOCK__CH0_RXTX2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXTX3 */ +#ifndef __RXTX3_MACRO__ +#define __RXTX3_MACRO__ + +/* macros for field xlnabias_pwd */ +#define RXTX3__XLNABIAS_PWD__SHIFT 0 +#define RXTX3__XLNABIAS_PWD__WIDTH 1 +#define RXTX3__XLNABIAS_PWD__MASK 0x00000001U +#define RXTX3__XLNABIAS_PWD__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXTX3__XLNABIAS_PWD__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXTX3__XLNABIAS_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXTX3__XLNABIAS_PWD__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define RXTX3__XLNABIAS_PWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXTX3__XLNABIAS_PWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field xlnaon */ +#define RXTX3__XLNAON__SHIFT 1 +#define RXTX3__XLNAON__WIDTH 1 +#define RXTX3__XLNAON__MASK 0x00000002U +#define RXTX3__XLNAON__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define RXTX3__XLNAON__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define RXTX3__XLNAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RXTX3__XLNAON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RXTX3__XLNAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RXTX3__XLNAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field xlnaon_ovr */ +#define RXTX3__XLNAON_OVR__SHIFT 2 +#define RXTX3__XLNAON_OVR__WIDTH 1 +#define RXTX3__XLNAON_OVR__MASK 0x00000004U +#define RXTX3__XLNAON_OVR__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define RXTX3__XLNAON_OVR__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define RXTX3__XLNAON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RXTX3__XLNAON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RXTX3__XLNAON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RXTX3__XLNAON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field dacFullScale */ +#define RXTX3__DACFULLSCALE__SHIFT 3 +#define RXTX3__DACFULLSCALE__WIDTH 1 +#define RXTX3__DACFULLSCALE__MASK 0x00000008U +#define RXTX3__DACFULLSCALE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define RXTX3__DACFULLSCALE__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define RXTX3__DACFULLSCALE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RXTX3__DACFULLSCALE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RXTX3__DACFULLSCALE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RXTX3__DACFULLSCALE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field dacrstb */ +#define RXTX3__DACRSTB__SHIFT 4 +#define RXTX3__DACRSTB__WIDTH 1 +#define RXTX3__DACRSTB__MASK 0x00000010U +#define RXTX3__DACRSTB__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) +#define RXTX3__DACRSTB__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) +#define RXTX3__DACRSTB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RXTX3__DACRSTB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RXTX3__DACRSTB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RXTX3__DACRSTB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field addacloopback */ +#define RXTX3__ADDACLOOPBACK__SHIFT 5 +#define RXTX3__ADDACLOOPBACK__WIDTH 1 +#define RXTX3__ADDACLOOPBACK__MASK 0x00000020U +#define RXTX3__ADDACLOOPBACK__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define RXTX3__ADDACLOOPBACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RXTX3__ADDACLOOPBACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RXTX3__ADDACLOOPBACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RXTX3__ADDACLOOPBACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RXTX3__ADDACLOOPBACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field adcshort */ +#define RXTX3__ADCSHORT__SHIFT 6 +#define RXTX3__ADCSHORT__WIDTH 1 +#define RXTX3__ADCSHORT__MASK 0x00000040U +#define RXTX3__ADCSHORT__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define RXTX3__ADCSHORT__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) +#define RXTX3__ADCSHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RXTX3__ADCSHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RXTX3__ADCSHORT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RXTX3__ADCSHORT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field dacpwd */ +#define RXTX3__DACPWD__SHIFT 7 +#define RXTX3__DACPWD__WIDTH 1 +#define RXTX3__DACPWD__MASK 0x00000080U +#define RXTX3__DACPWD__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define RXTX3__DACPWD__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) +#define RXTX3__DACPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RXTX3__DACPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RXTX3__DACPWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RXTX3__DACPWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field dacpwd_ovr */ +#define RXTX3__DACPWD_OVR__SHIFT 8 +#define RXTX3__DACPWD_OVR__WIDTH 1 +#define RXTX3__DACPWD_OVR__MASK 0x00000100U +#define RXTX3__DACPWD_OVR__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define RXTX3__DACPWD_OVR__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) +#define RXTX3__DACPWD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RXTX3__DACPWD_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RXTX3__DACPWD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RXTX3__DACPWD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field adcpwd */ +#define RXTX3__ADCPWD__SHIFT 9 +#define RXTX3__ADCPWD__WIDTH 1 +#define RXTX3__ADCPWD__MASK 0x00000200U +#define RXTX3__ADCPWD__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define RXTX3__ADCPWD__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) +#define RXTX3__ADCPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define RXTX3__ADCPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define RXTX3__ADCPWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define RXTX3__ADCPWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field adcpwd_ovr */ +#define RXTX3__ADCPWD_OVR__SHIFT 10 +#define RXTX3__ADCPWD_OVR__WIDTH 1 +#define RXTX3__ADCPWD_OVR__MASK 0x00000400U +#define RXTX3__ADCPWD_OVR__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define RXTX3__ADCPWD_OVR__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) +#define RXTX3__ADCPWD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RXTX3__ADCPWD_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RXTX3__ADCPWD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RXTX3__ADCPWD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field agc_caldac */ +#define RXTX3__AGC_CALDAC__SHIFT 11 +#define RXTX3__AGC_CALDAC__WIDTH 6 +#define RXTX3__AGC_CALDAC__MASK 0x0001f800U +#define RXTX3__AGC_CALDAC__READ(src) (((u_int32_t)(src) & 0x0001f800U) >> 11) +#define RXTX3__AGC_CALDAC__WRITE(src) (((u_int32_t)(src) << 11) & 0x0001f800U) +#define RXTX3__AGC_CALDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0001f800U) +#define RXTX3__AGC_CALDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0001f800U))) + +/* macros for field agc_cal */ +#define RXTX3__AGC_CAL__SHIFT 17 +#define RXTX3__AGC_CAL__WIDTH 1 +#define RXTX3__AGC_CAL__MASK 0x00020000U +#define RXTX3__AGC_CAL__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17) +#define RXTX3__AGC_CAL__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U) +#define RXTX3__AGC_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RXTX3__AGC_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RXTX3__AGC_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RXTX3__AGC_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field agc_cal_ovr */ +#define RXTX3__AGC_CAL_OVR__SHIFT 18 +#define RXTX3__AGC_CAL_OVR__WIDTH 1 +#define RXTX3__AGC_CAL_OVR__MASK 0x00040000U +#define RXTX3__AGC_CAL_OVR__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define RXTX3__AGC_CAL_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define RXTX3__AGC_CAL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define RXTX3__AGC_CAL_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define RXTX3__AGC_CAL_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define RXTX3__AGC_CAL_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field LOforcedon */ +#define RXTX3__LOFORCEDON__SHIFT 19 +#define RXTX3__LOFORCEDON__WIDTH 1 +#define RXTX3__LOFORCEDON__MASK 0x00080000U +#define RXTX3__LOFORCEDON__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) +#define RXTX3__LOFORCEDON__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) +#define RXTX3__LOFORCEDON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define RXTX3__LOFORCEDON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define RXTX3__LOFORCEDON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define RXTX3__LOFORCEDON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field calresidue */ +#define RXTX3__CALRESIDUE__SHIFT 20 +#define RXTX3__CALRESIDUE__WIDTH 1 +#define RXTX3__CALRESIDUE__MASK 0x00100000U +#define RXTX3__CALRESIDUE__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define RXTX3__CALRESIDUE__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) +#define RXTX3__CALRESIDUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define RXTX3__CALRESIDUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define RXTX3__CALRESIDUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define RXTX3__CALRESIDUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field calresidue_ovr */ +#define RXTX3__CALRESIDUE_OVR__SHIFT 21 +#define RXTX3__CALRESIDUE_OVR__WIDTH 1 +#define RXTX3__CALRESIDUE_OVR__MASK 0x00200000U +#define RXTX3__CALRESIDUE_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define RXTX3__CALRESIDUE_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define RXTX3__CALRESIDUE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define RXTX3__CALRESIDUE_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define RXTX3__CALRESIDUE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define RXTX3__CALRESIDUE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field calfc */ +#define RXTX3__CALFC__SHIFT 22 +#define RXTX3__CALFC__WIDTH 1 +#define RXTX3__CALFC__MASK 0x00400000U +#define RXTX3__CALFC__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22) +#define RXTX3__CALFC__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U) +#define RXTX3__CALFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define RXTX3__CALFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define RXTX3__CALFC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define RXTX3__CALFC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field calfc_ovr */ +#define RXTX3__CALFC_OVR__SHIFT 23 +#define RXTX3__CALFC_OVR__WIDTH 1 +#define RXTX3__CALFC_OVR__MASK 0x00800000U +#define RXTX3__CALFC_OVR__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) +#define RXTX3__CALFC_OVR__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) +#define RXTX3__CALFC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RXTX3__CALFC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RXTX3__CALFC_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RXTX3__CALFC_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field caltx */ +#define RXTX3__CALTX__SHIFT 24 +#define RXTX3__CALTX__WIDTH 1 +#define RXTX3__CALTX__MASK 0x01000000U +#define RXTX3__CALTX__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define RXTX3__CALTX__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U) +#define RXTX3__CALTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RXTX3__CALTX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RXTX3__CALTX__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RXTX3__CALTX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field caltx_ovr */ +#define RXTX3__CALTX_OVR__SHIFT 25 +#define RXTX3__CALTX_OVR__WIDTH 1 +#define RXTX3__CALTX_OVR__MASK 0x02000000U +#define RXTX3__CALTX_OVR__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) +#define RXTX3__CALTX_OVR__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U) +#define RXTX3__CALTX_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RXTX3__CALTX_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RXTX3__CALTX_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RXTX3__CALTX_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field caltxshift */ +#define RXTX3__CALTXSHIFT__SHIFT 26 +#define RXTX3__CALTXSHIFT__WIDTH 1 +#define RXTX3__CALTXSHIFT__MASK 0x04000000U +#define RXTX3__CALTXSHIFT__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) +#define RXTX3__CALTXSHIFT__WRITE(src) (((u_int32_t)(src) << 26) & 0x04000000U) +#define RXTX3__CALTXSHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RXTX3__CALTXSHIFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RXTX3__CALTXSHIFT__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RXTX3__CALTXSHIFT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field caltxshift_ovr */ +#define RXTX3__CALTXSHIFT_OVR__SHIFT 27 +#define RXTX3__CALTXSHIFT_OVR__WIDTH 1 +#define RXTX3__CALTXSHIFT_OVR__MASK 0x08000000U +#define RXTX3__CALTXSHIFT_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RXTX3__CALTXSHIFT_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RXTX3__CALTXSHIFT_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RXTX3__CALTXSHIFT_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RXTX3__CALTXSHIFT_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RXTX3__CALTXSHIFT_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field calpa */ +#define RXTX3__CALPA__SHIFT 28 +#define RXTX3__CALPA__WIDTH 1 +#define RXTX3__CALPA__MASK 0x10000000U +#define RXTX3__CALPA__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define RXTX3__CALPA__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define RXTX3__CALPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RXTX3__CALPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RXTX3__CALPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RXTX3__CALPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field calpa_ovr */ +#define RXTX3__CALPA_OVR__SHIFT 29 +#define RXTX3__CALPA_OVR__WIDTH 1 +#define RXTX3__CALPA_OVR__MASK 0x20000000U +#define RXTX3__CALPA_OVR__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define RXTX3__CALPA_OVR__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define RXTX3__CALPA_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RXTX3__CALPA_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RXTX3__CALPA_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RXTX3__CALPA_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field spuron */ +#define RXTX3__SPURON__SHIFT 30 +#define RXTX3__SPURON__WIDTH 1 +#define RXTX3__SPURON__MASK 0x40000000U +#define RXTX3__SPURON__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define RXTX3__SPURON__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define RXTX3__SPURON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RXTX3__SPURON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RXTX3__SPURON__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RXTX3__SPURON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PAL_lockedEn */ +#define RXTX3__PAL_LOCKEDEN__SHIFT 31 +#define RXTX3__PAL_LOCKEDEN__WIDTH 1 +#define RXTX3__PAL_LOCKEDEN__MASK 0x80000000U +#define RXTX3__PAL_LOCKEDEN__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define RXTX3__PAL_LOCKEDEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RXTX3__PAL_LOCKEDEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RXTX3__PAL_LOCKEDEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RXTX3__PAL_LOCKEDEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RXTX3__PAL_LOCKEDEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RXTX3__TYPE u_int32_t +#define RXTX3__READ 0xffffffffU +#define RXTX3__WRITE 0xffffffffU + +#endif /* __RXTX3_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_RXTX3 */ +#define INST_RADIO65_REG_BLOCK__CH0_RXTX3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXTX4 */ +#ifndef __RXTX4_MACRO__ +#define __RXTX4_MACRO__ + +/* macros for field SPARE4 */ +#define RXTX4__SPARE4__SHIFT 0 +#define RXTX4__SPARE4__WIDTH 23 +#define RXTX4__SPARE4__MASK 0x007fffffU +#define RXTX4__SPARE4__READ(src) (u_int32_t)(src) & 0x007fffffU +#define RXTX4__SPARE4__WRITE(src) ((u_int32_t)(src) & 0x007fffffU) +#define RXTX4__SPARE4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007fffffU) | ((u_int32_t)(src) &\ + 0x007fffffU) +#define RXTX4__SPARE4__VERIFY(src) (!(((u_int32_t)(src) & ~0x007fffffU))) + +/* macros for field testiq_on */ +#define RXTX4__TESTIQ_ON__SHIFT 23 +#define RXTX4__TESTIQ_ON__WIDTH 1 +#define RXTX4__TESTIQ_ON__MASK 0x00800000U +#define RXTX4__TESTIQ_ON__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) +#define RXTX4__TESTIQ_ON__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) +#define RXTX4__TESTIQ_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RXTX4__TESTIQ_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RXTX4__TESTIQ_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RXTX4__TESTIQ_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field testiq_bufen */ +#define RXTX4__TESTIQ_BUFEN__SHIFT 24 +#define RXTX4__TESTIQ_BUFEN__WIDTH 1 +#define RXTX4__TESTIQ_BUFEN__MASK 0x01000000U +#define RXTX4__TESTIQ_BUFEN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define RXTX4__TESTIQ_BUFEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RXTX4__TESTIQ_BUFEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RXTX4__TESTIQ_BUFEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RXTX4__TESTIQ_BUFEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RXTX4__TESTIQ_BUFEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field testiq_rsel */ +#define RXTX4__TESTIQ_RSEL__SHIFT 25 +#define RXTX4__TESTIQ_RSEL__WIDTH 1 +#define RXTX4__TESTIQ_RSEL__MASK 0x02000000U +#define RXTX4__TESTIQ_RSEL__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) +#define RXTX4__TESTIQ_RSEL__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U) +#define RXTX4__TESTIQ_RSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RXTX4__TESTIQ_RSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RXTX4__TESTIQ_RSEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RXTX4__TESTIQ_RSEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field turboADC */ +#define RXTX4__TURBOADC__SHIFT 26 +#define RXTX4__TURBOADC__WIDTH 1 +#define RXTX4__TURBOADC__MASK 0x04000000U +#define RXTX4__TURBOADC__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) +#define RXTX4__TURBOADC__WRITE(src) (((u_int32_t)(src) << 26) & 0x04000000U) +#define RXTX4__TURBOADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RXTX4__TURBOADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RXTX4__TURBOADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RXTX4__TURBOADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field turboADC_ovr */ +#define RXTX4__TURBOADC_OVR__SHIFT 27 +#define RXTX4__TURBOADC_OVR__WIDTH 1 +#define RXTX4__TURBOADC_OVR__MASK 0x08000000U +#define RXTX4__TURBOADC_OVR__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) +#define RXTX4__TURBOADC_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RXTX4__TURBOADC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RXTX4__TURBOADC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RXTX4__TURBOADC_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RXTX4__TURBOADC_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field thermOn */ +#define RXTX4__THERMON__SHIFT 28 +#define RXTX4__THERMON__WIDTH 1 +#define RXTX4__THERMON__MASK 0x10000000U +#define RXTX4__THERMON__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define RXTX4__THERMON__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define RXTX4__THERMON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RXTX4__THERMON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RXTX4__THERMON__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RXTX4__THERMON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field thermOn_ovr */ +#define RXTX4__THERMON_OVR__SHIFT 29 +#define RXTX4__THERMON_OVR__WIDTH 1 +#define RXTX4__THERMON_OVR__MASK 0x20000000U +#define RXTX4__THERMON_OVR__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define RXTX4__THERMON_OVR__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define RXTX4__THERMON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RXTX4__THERMON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RXTX4__THERMON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RXTX4__THERMON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field xlna_strength */ +#define RXTX4__XLNA_STRENGTH__SHIFT 30 +#define RXTX4__XLNA_STRENGTH__WIDTH 2 +#define RXTX4__XLNA_STRENGTH__MASK 0xc0000000U +#define RXTX4__XLNA_STRENGTH__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define RXTX4__XLNA_STRENGTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define RXTX4__XLNA_STRENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define RXTX4__XLNA_STRENGTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define RXTX4__TYPE u_int32_t +#define RXTX4__READ 0xffffffffU +#define RXTX4__WRITE 0xffffffffU + +#endif /* __RXTX4_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_RXTX4 */ +#define INST_RADIO65_REG_BLOCK__CH0_RXTX4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BB1 */ +#ifndef __BB1_MACRO__ +#define __BB1_MACRO__ + +/* macros for field I2V_CURR2X */ +#define BB1__I2V_CURR2X__SHIFT 0 +#define BB1__I2V_CURR2X__WIDTH 1 +#define BB1__I2V_CURR2X__MASK 0x00000001U +#define BB1__I2V_CURR2X__READ(src) (u_int32_t)(src) & 0x00000001U +#define BB1__I2V_CURR2X__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define BB1__I2V_CURR2X__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BB1__I2V_CURR2X__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define BB1__I2V_CURR2X__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BB1__I2V_CURR2X__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ENABLE_LOQ */ +#define BB1__ENABLE_LOQ__SHIFT 1 +#define BB1__ENABLE_LOQ__WIDTH 1 +#define BB1__ENABLE_LOQ__MASK 0x00000002U +#define BB1__ENABLE_LOQ__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define BB1__ENABLE_LOQ__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define BB1__ENABLE_LOQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define BB1__ENABLE_LOQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define BB1__ENABLE_LOQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define BB1__ENABLE_LOQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field FORCE_LOQ */ +#define BB1__FORCE_LOQ__SHIFT 2 +#define BB1__FORCE_LOQ__WIDTH 1 +#define BB1__FORCE_LOQ__MASK 0x00000004U +#define BB1__FORCE_LOQ__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define BB1__FORCE_LOQ__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define BB1__FORCE_LOQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define BB1__FORCE_LOQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define BB1__FORCE_LOQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define BB1__FORCE_LOQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field ENABLE_NOTCH */ +#define BB1__ENABLE_NOTCH__SHIFT 3 +#define BB1__ENABLE_NOTCH__WIDTH 1 +#define BB1__ENABLE_NOTCH__MASK 0x00000008U +#define BB1__ENABLE_NOTCH__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define BB1__ENABLE_NOTCH__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define BB1__ENABLE_NOTCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define BB1__ENABLE_NOTCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define BB1__ENABLE_NOTCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define BB1__ENABLE_NOTCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field FORCE_NOTCH */ +#define BB1__FORCE_NOTCH__SHIFT 4 +#define BB1__FORCE_NOTCH__WIDTH 1 +#define BB1__FORCE_NOTCH__MASK 0x00000010U +#define BB1__FORCE_NOTCH__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) +#define BB1__FORCE_NOTCH__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) +#define BB1__FORCE_NOTCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define BB1__FORCE_NOTCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define BB1__FORCE_NOTCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define BB1__FORCE_NOTCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field ENABLE_BIQUAD */ +#define BB1__ENABLE_BIQUAD__SHIFT 5 +#define BB1__ENABLE_BIQUAD__WIDTH 1 +#define BB1__ENABLE_BIQUAD__MASK 0x00000020U +#define BB1__ENABLE_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define BB1__ENABLE_BIQUAD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) +#define BB1__ENABLE_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define BB1__ENABLE_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define BB1__ENABLE_BIQUAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define BB1__ENABLE_BIQUAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field FORCE_BIQUAD */ +#define BB1__FORCE_BIQUAD__SHIFT 6 +#define BB1__FORCE_BIQUAD__WIDTH 1 +#define BB1__FORCE_BIQUAD__MASK 0x00000040U +#define BB1__FORCE_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define BB1__FORCE_BIQUAD__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) +#define BB1__FORCE_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define BB1__FORCE_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define BB1__FORCE_BIQUAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define BB1__FORCE_BIQUAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field ENABLE_OSDAC */ +#define BB1__ENABLE_OSDAC__SHIFT 7 +#define BB1__ENABLE_OSDAC__WIDTH 1 +#define BB1__ENABLE_OSDAC__MASK 0x00000080U +#define BB1__ENABLE_OSDAC__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define BB1__ENABLE_OSDAC__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) +#define BB1__ENABLE_OSDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define BB1__ENABLE_OSDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define BB1__ENABLE_OSDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define BB1__ENABLE_OSDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field FORCE_OSDAC */ +#define BB1__FORCE_OSDAC__SHIFT 8 +#define BB1__FORCE_OSDAC__WIDTH 1 +#define BB1__FORCE_OSDAC__MASK 0x00000100U +#define BB1__FORCE_OSDAC__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define BB1__FORCE_OSDAC__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) +#define BB1__FORCE_OSDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define BB1__FORCE_OSDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define BB1__FORCE_OSDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define BB1__FORCE_OSDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field ENABLE_V2I */ +#define BB1__ENABLE_V2I__SHIFT 9 +#define BB1__ENABLE_V2I__WIDTH 1 +#define BB1__ENABLE_V2I__MASK 0x00000200U +#define BB1__ENABLE_V2I__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define BB1__ENABLE_V2I__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) +#define BB1__ENABLE_V2I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define BB1__ENABLE_V2I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define BB1__ENABLE_V2I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define BB1__ENABLE_V2I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field FORCE_V2I */ +#define BB1__FORCE_V2I__SHIFT 10 +#define BB1__FORCE_V2I__WIDTH 1 +#define BB1__FORCE_V2I__MASK 0x00000400U +#define BB1__FORCE_V2I__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define BB1__FORCE_V2I__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) +#define BB1__FORCE_V2I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define BB1__FORCE_V2I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define BB1__FORCE_V2I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define BB1__FORCE_V2I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field ENABLE_I2V */ +#define BB1__ENABLE_I2V__SHIFT 11 +#define BB1__ENABLE_I2V__WIDTH 1 +#define BB1__ENABLE_I2V__MASK 0x00000800U +#define BB1__ENABLE_I2V__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define BB1__ENABLE_I2V__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define BB1__ENABLE_I2V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define BB1__ENABLE_I2V__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define BB1__ENABLE_I2V__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define BB1__ENABLE_I2V__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field FORCE_I2V */ +#define BB1__FORCE_I2V__SHIFT 12 +#define BB1__FORCE_I2V__WIDTH 1 +#define BB1__FORCE_I2V__MASK 0x00001000U +#define BB1__FORCE_I2V__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) +#define BB1__FORCE_I2V__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) +#define BB1__FORCE_I2V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define BB1__FORCE_I2V__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define BB1__FORCE_I2V__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define BB1__FORCE_I2V__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field CMSEL */ +#define BB1__CMSEL__SHIFT 13 +#define BB1__CMSEL__WIDTH 3 +#define BB1__CMSEL__MASK 0x0000e000U +#define BB1__CMSEL__READ(src) (((u_int32_t)(src) & 0x0000e000U) >> 13) +#define BB1__CMSEL__WRITE(src) (((u_int32_t)(src) << 13) & 0x0000e000U) +#define BB1__CMSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define BB1__CMSEL__VERIFY(src) (!((((u_int32_t)(src) << 13) & ~0x0000e000U))) + +/* macros for field ATBSEL */ +#define BB1__ATBSEL__SHIFT 16 +#define BB1__ATBSEL__WIDTH 2 +#define BB1__ATBSEL__MASK 0x00030000U +#define BB1__ATBSEL__READ(src) (((u_int32_t)(src) & 0x00030000U) >> 16) +#define BB1__ATBSEL__WRITE(src) (((u_int32_t)(src) << 16) & 0x00030000U) +#define BB1__ATBSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((u_int32_t)(src) <<\ + 16) & 0x00030000U) +#define BB1__ATBSEL__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x00030000U))) + +/* macros for field PD_OSDAC_CALTX_CALPA */ +#define BB1__PD_OSDAC_CALTX_CALPA__SHIFT 18 +#define BB1__PD_OSDAC_CALTX_CALPA__WIDTH 1 +#define BB1__PD_OSDAC_CALTX_CALPA__MASK 0x00040000U +#define BB1__PD_OSDAC_CALTX_CALPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define BB1__PD_OSDAC_CALTX_CALPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define BB1__PD_OSDAC_CALTX_CALPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define BB1__PD_OSDAC_CALTX_CALPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define BB1__PD_OSDAC_CALTX_CALPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define BB1__PD_OSDAC_CALTX_CALPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field OFSTCORRI2VQ */ +#define BB1__OFSTCORRI2VQ__SHIFT 19 +#define BB1__OFSTCORRI2VQ__WIDTH 5 +#define BB1__OFSTCORRI2VQ__MASK 0x00f80000U +#define BB1__OFSTCORRI2VQ__READ(src) (((u_int32_t)(src) & 0x00f80000U) >> 19) +#define BB1__OFSTCORRI2VQ__WRITE(src) (((u_int32_t)(src) << 19) & 0x00f80000U) +#define BB1__OFSTCORRI2VQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f80000U) | (((u_int32_t)(src) <<\ + 19) & 0x00f80000U) +#define BB1__OFSTCORRI2VQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00f80000U))) + +/* macros for field OFSTCORRI2VI */ +#define BB1__OFSTCORRI2VI__SHIFT 24 +#define BB1__OFSTCORRI2VI__WIDTH 5 +#define BB1__OFSTCORRI2VI__MASK 0x1f000000U +#define BB1__OFSTCORRI2VI__READ(src) (((u_int32_t)(src) & 0x1f000000U) >> 24) +#define BB1__OFSTCORRI2VI__WRITE(src) (((u_int32_t)(src) << 24) & 0x1f000000U) +#define BB1__OFSTCORRI2VI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x1f000000U) +#define BB1__OFSTCORRI2VI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x1f000000U))) + +/* macros for field LOCALOFFSET */ +#define BB1__LOCALOFFSET__SHIFT 29 +#define BB1__LOCALOFFSET__WIDTH 1 +#define BB1__LOCALOFFSET__MASK 0x20000000U +#define BB1__LOCALOFFSET__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define BB1__LOCALOFFSET__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define BB1__LOCALOFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define BB1__LOCALOFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define BB1__LOCALOFFSET__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define BB1__LOCALOFFSET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field RANGE_OSDAC */ +#define BB1__RANGE_OSDAC__SHIFT 30 +#define BB1__RANGE_OSDAC__WIDTH 2 +#define BB1__RANGE_OSDAC__MASK 0xc0000000U +#define BB1__RANGE_OSDAC__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) +#define BB1__RANGE_OSDAC__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U) +#define BB1__RANGE_OSDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define BB1__RANGE_OSDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define BB1__TYPE u_int32_t +#define BB1__READ 0xffffffffU +#define BB1__WRITE 0xffffffffU + +#endif /* __BB1_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_BB1 */ +#define INST_RADIO65_REG_BLOCK__CH0_BB1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BB2 */ +#ifndef __BB2_MACRO__ +#define __BB2_MACRO__ + +/* macros for field SPARE */ +#define BB2__SPARE__SHIFT 0 +#define BB2__SPARE__WIDTH 4 +#define BB2__SPARE__MASK 0x0000000fU +#define BB2__SPARE__READ(src) (u_int32_t)(src) & 0x0000000fU +#define BB2__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define BB2__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define BB2__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) + +/* macros for field MXR_HIGHGAINMASK */ +#define BB2__MXR_HIGHGAINMASK__SHIFT 4 +#define BB2__MXR_HIGHGAINMASK__WIDTH 4 +#define BB2__MXR_HIGHGAINMASK__MASK 0x000000f0U +#define BB2__MXR_HIGHGAINMASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define BB2__MXR_HIGHGAINMASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define BB2__MXR_HIGHGAINMASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define BB2__MXR_HIGHGAINMASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field SEL_TEST */ +#define BB2__SEL_TEST__SHIFT 8 +#define BB2__SEL_TEST__WIDTH 2 +#define BB2__SEL_TEST__MASK 0x00000300U +#define BB2__SEL_TEST__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8) +#define BB2__SEL_TEST__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000300U) +#define BB2__SEL_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define BB2__SEL_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field RCFILTER_CAP */ +#define BB2__RCFILTER_CAP__SHIFT 10 +#define BB2__RCFILTER_CAP__WIDTH 5 +#define BB2__RCFILTER_CAP__MASK 0x00007c00U +#define BB2__RCFILTER_CAP__READ(src) (((u_int32_t)(src) & 0x00007c00U) >> 10) +#define BB2__RCFILTER_CAP__WRITE(src) (((u_int32_t)(src) << 10) & 0x00007c00U) +#define BB2__RCFILTER_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define BB2__RCFILTER_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field OVERRIDE_RCFILTER_CAP */ +#define BB2__OVERRIDE_RCFILTER_CAP__SHIFT 15 +#define BB2__OVERRIDE_RCFILTER_CAP__WIDTH 1 +#define BB2__OVERRIDE_RCFILTER_CAP__MASK 0x00008000U +#define BB2__OVERRIDE_RCFILTER_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define BB2__OVERRIDE_RCFILTER_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define BB2__OVERRIDE_RCFILTER_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define BB2__OVERRIDE_RCFILTER_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define BB2__OVERRIDE_RCFILTER_CAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define BB2__OVERRIDE_RCFILTER_CAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field FNOTCH */ +#define BB2__FNOTCH__SHIFT 16 +#define BB2__FNOTCH__WIDTH 4 +#define BB2__FNOTCH__MASK 0x000f0000U +#define BB2__FNOTCH__READ(src) (((u_int32_t)(src) & 0x000f0000U) >> 16) +#define BB2__FNOTCH__WRITE(src) (((u_int32_t)(src) << 16) & 0x000f0000U) +#define BB2__FNOTCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define BB2__FNOTCH__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x000f0000U))) + +/* macros for field OVERRIDE_FNOTCH */ +#define BB2__OVERRIDE_FNOTCH__SHIFT 20 +#define BB2__OVERRIDE_FNOTCH__WIDTH 1 +#define BB2__OVERRIDE_FNOTCH__MASK 0x00100000U +#define BB2__OVERRIDE_FNOTCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define BB2__OVERRIDE_FNOTCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define BB2__OVERRIDE_FNOTCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define BB2__OVERRIDE_FNOTCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define BB2__OVERRIDE_FNOTCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define BB2__OVERRIDE_FNOTCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field FILTERFC */ +#define BB2__FILTERFC__SHIFT 21 +#define BB2__FILTERFC__WIDTH 5 +#define BB2__FILTERFC__MASK 0x03e00000U +#define BB2__FILTERFC__READ(src) (((u_int32_t)(src) & 0x03e00000U) >> 21) +#define BB2__FILTERFC__WRITE(src) (((u_int32_t)(src) << 21) & 0x03e00000U) +#define BB2__FILTERFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x03e00000U) +#define BB2__FILTERFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x03e00000U))) + +/* macros for field OVERRIDE_FILTERFC */ +#define BB2__OVERRIDE_FILTERFC__SHIFT 26 +#define BB2__OVERRIDE_FILTERFC__WIDTH 1 +#define BB2__OVERRIDE_FILTERFC__MASK 0x04000000U +#define BB2__OVERRIDE_FILTERFC__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define BB2__OVERRIDE_FILTERFC__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define BB2__OVERRIDE_FILTERFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define BB2__OVERRIDE_FILTERFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define BB2__OVERRIDE_FILTERFC__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define BB2__OVERRIDE_FILTERFC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field I2V2RXOUT_EN */ +#define BB2__I2V2RXOUT_EN__SHIFT 27 +#define BB2__I2V2RXOUT_EN__WIDTH 1 +#define BB2__I2V2RXOUT_EN__MASK 0x08000000U +#define BB2__I2V2RXOUT_EN__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) +#define BB2__I2V2RXOUT_EN__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U) +#define BB2__I2V2RXOUT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define BB2__I2V2RXOUT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define BB2__I2V2RXOUT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define BB2__I2V2RXOUT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field BQ2RXOUT_EN */ +#define BB2__BQ2RXOUT_EN__SHIFT 28 +#define BB2__BQ2RXOUT_EN__WIDTH 1 +#define BB2__BQ2RXOUT_EN__MASK 0x10000000U +#define BB2__BQ2RXOUT_EN__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define BB2__BQ2RXOUT_EN__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define BB2__BQ2RXOUT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define BB2__BQ2RXOUT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define BB2__BQ2RXOUT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define BB2__BQ2RXOUT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field RXIN2I2V_EN */ +#define BB2__RXIN2I2V_EN__SHIFT 29 +#define BB2__RXIN2I2V_EN__WIDTH 1 +#define BB2__RXIN2I2V_EN__MASK 0x20000000U +#define BB2__RXIN2I2V_EN__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define BB2__RXIN2I2V_EN__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define BB2__RXIN2I2V_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define BB2__RXIN2I2V_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define BB2__RXIN2I2V_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define BB2__RXIN2I2V_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field RXIN2BQ_EN */ +#define BB2__RXIN2BQ_EN__SHIFT 30 +#define BB2__RXIN2BQ_EN__WIDTH 1 +#define BB2__RXIN2BQ_EN__MASK 0x40000000U +#define BB2__RXIN2BQ_EN__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define BB2__RXIN2BQ_EN__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define BB2__RXIN2BQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define BB2__RXIN2BQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define BB2__RXIN2BQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define BB2__RXIN2BQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field SWITCH_OVERRIDE */ +#define BB2__SWITCH_OVERRIDE__SHIFT 31 +#define BB2__SWITCH_OVERRIDE__WIDTH 1 +#define BB2__SWITCH_OVERRIDE__MASK 0x80000000U +#define BB2__SWITCH_OVERRIDE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define BB2__SWITCH_OVERRIDE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define BB2__SWITCH_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define BB2__SWITCH_OVERRIDE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define BB2__SWITCH_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define BB2__SWITCH_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define BB2__TYPE u_int32_t +#define BB2__READ 0xffffffffU +#define BB2__WRITE 0xffffffffU + +#endif /* __BB2_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_BB2 */ +#define INST_RADIO65_REG_BLOCK__CH0_BB2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BB3 */ +#ifndef __BB3_MACRO__ +#define __BB3_MACRO__ + +/* macros for field SPARE */ +#define BB3__SPARE__SHIFT 0 +#define BB3__SPARE__WIDTH 8 +#define BB3__SPARE__MASK 0x000000ffU +#define BB3__SPARE__READ(src) (u_int32_t)(src) & 0x000000ffU +#define BB3__SPARE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define BB3__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define BB3__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field SEL_OFST_READBK */ +#define BB3__SEL_OFST_READBK__SHIFT 8 +#define BB3__SEL_OFST_READBK__WIDTH 2 +#define BB3__SEL_OFST_READBK__MASK 0x00000300U +#define BB3__SEL_OFST_READBK__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8) +#define BB3__SEL_OFST_READBK__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define BB3__SEL_OFST_READBK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define BB3__SEL_OFST_READBK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field OVERRIDE_RXONLY_FILTERFC */ +#define BB3__OVERRIDE_RXONLY_FILTERFC__SHIFT 10 +#define BB3__OVERRIDE_RXONLY_FILTERFC__WIDTH 1 +#define BB3__OVERRIDE_RXONLY_FILTERFC__MASK 0x00000400U +#define BB3__OVERRIDE_RXONLY_FILTERFC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define BB3__OVERRIDE_RXONLY_FILTERFC__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define BB3__OVERRIDE_RXONLY_FILTERFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define BB3__OVERRIDE_RXONLY_FILTERFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define BB3__OVERRIDE_RXONLY_FILTERFC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define BB3__OVERRIDE_RXONLY_FILTERFC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field RXONLY_FILTERFC */ +#define BB3__RXONLY_FILTERFC__SHIFT 11 +#define BB3__RXONLY_FILTERFC__WIDTH 5 +#define BB3__RXONLY_FILTERFC__MASK 0x0000f800U +#define BB3__RXONLY_FILTERFC__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f800U) >> 11) +#define BB3__RXONLY_FILTERFC__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x0000f800U) +#define BB3__RXONLY_FILTERFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0000f800U) +#define BB3__RXONLY_FILTERFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0000f800U))) + +/* macros for field FILTERFC */ +#define BB3__FILTERFC__SHIFT 16 +#define BB3__FILTERFC__WIDTH 5 +#define BB3__FILTERFC__MASK 0x001f0000U +#define BB3__FILTERFC__READ(src) (((u_int32_t)(src) & 0x001f0000U) >> 16) + +/* macros for field OFSTCORRI2VQ */ +#define BB3__OFSTCORRI2VQ__SHIFT 21 +#define BB3__OFSTCORRI2VQ__WIDTH 5 +#define BB3__OFSTCORRI2VQ__MASK 0x03e00000U +#define BB3__OFSTCORRI2VQ__READ(src) (((u_int32_t)(src) & 0x03e00000U) >> 21) + +/* macros for field OFSTCORRI2VI */ +#define BB3__OFSTCORRI2VI__SHIFT 26 +#define BB3__OFSTCORRI2VI__WIDTH 5 +#define BB3__OFSTCORRI2VI__MASK 0x7c000000U +#define BB3__OFSTCORRI2VI__READ(src) (((u_int32_t)(src) & 0x7c000000U) >> 26) + +/* macros for field EN_TXBBCONSTCUR */ +#define BB3__EN_TXBBCONSTCUR__SHIFT 31 +#define BB3__EN_TXBBCONSTCUR__WIDTH 1 +#define BB3__EN_TXBBCONSTCUR__MASK 0x80000000U +#define BB3__EN_TXBBCONSTCUR__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define BB3__EN_TXBBCONSTCUR__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define BB3__EN_TXBBCONSTCUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define BB3__EN_TXBBCONSTCUR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define BB3__EN_TXBBCONSTCUR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define BB3__EN_TXBBCONSTCUR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define BB3__TYPE u_int32_t +#define BB3__READ 0xffffffffU +#define BB3__WRITE 0xffffffffU + +#endif /* __BB3_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_BB3 */ +#define INST_RADIO65_REG_BLOCK__CH0_BB3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PLLCLKMODA */ +#ifndef __PLLCLKMODA_MACRO__ +#define __PLLCLKMODA_MACRO__ + +/* macros for field pwd_pllsdm */ +#define PLLCLKMODA__PWD_PLLSDM__SHIFT 0 +#define PLLCLKMODA__PWD_PLLSDM__WIDTH 1 +#define PLLCLKMODA__PWD_PLLSDM__MASK 0x00000001U +#define PLLCLKMODA__PWD_PLLSDM__READ(src) (u_int32_t)(src) & 0x00000001U +#define PLLCLKMODA__PWD_PLLSDM__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define PLLCLKMODA__PWD_PLLSDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PLLCLKMODA__PWD_PLLSDM__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PLLCLKMODA__PWD_PLLSDM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PLLCLKMODA__PWD_PLLSDM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field pwdpll */ +#define PLLCLKMODA__PWDPLL__SHIFT 1 +#define PLLCLKMODA__PWDPLL__WIDTH 1 +#define PLLCLKMODA__PWDPLL__MASK 0x00000002U +#define PLLCLKMODA__PWDPLL__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define PLLCLKMODA__PWDPLL__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define PLLCLKMODA__PWDPLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PLLCLKMODA__PWDPLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PLLCLKMODA__PWDPLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PLLCLKMODA__PWDPLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field pllfrac */ +#define PLLCLKMODA__PLLFRAC__SHIFT 2 +#define PLLCLKMODA__PLLFRAC__WIDTH 15 +#define PLLCLKMODA__PLLFRAC__MASK 0x0001fffcU +#define PLLCLKMODA__PLLFRAC__READ(src) (((u_int32_t)(src) & 0x0001fffcU) >> 2) +#define PLLCLKMODA__PLLFRAC__WRITE(src) (((u_int32_t)(src) << 2) & 0x0001fffcU) +#define PLLCLKMODA__PLLFRAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0001fffcU) +#define PLLCLKMODA__PLLFRAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0001fffcU))) + +/* macros for field refdiv */ +#define PLLCLKMODA__REFDIV__SHIFT 17 +#define PLLCLKMODA__REFDIV__WIDTH 4 +#define PLLCLKMODA__REFDIV__MASK 0x001e0000U +#define PLLCLKMODA__REFDIV__READ(src) (((u_int32_t)(src) & 0x001e0000U) >> 17) +#define PLLCLKMODA__REFDIV__WRITE(src) (((u_int32_t)(src) << 17) & 0x001e0000U) +#define PLLCLKMODA__REFDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x001e0000U) +#define PLLCLKMODA__REFDIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x001e0000U))) + +/* macros for field div */ +#define PLLCLKMODA__DIV__SHIFT 21 +#define PLLCLKMODA__DIV__WIDTH 10 +#define PLLCLKMODA__DIV__MASK 0x7fe00000U +#define PLLCLKMODA__DIV__READ(src) (((u_int32_t)(src) & 0x7fe00000U) >> 21) +#define PLLCLKMODA__DIV__WRITE(src) (((u_int32_t)(src) << 21) & 0x7fe00000U) +#define PLLCLKMODA__DIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x7fe00000U) +#define PLLCLKMODA__DIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x7fe00000U))) + +/* macros for field local_pll */ +#define PLLCLKMODA__LOCAL_PLL__SHIFT 31 +#define PLLCLKMODA__LOCAL_PLL__WIDTH 1 +#define PLLCLKMODA__LOCAL_PLL__MASK 0x80000000U +#define PLLCLKMODA__LOCAL_PLL__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define PLLCLKMODA__LOCAL_PLL__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define PLLCLKMODA__LOCAL_PLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define PLLCLKMODA__LOCAL_PLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define PLLCLKMODA__LOCAL_PLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define PLLCLKMODA__LOCAL_PLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define PLLCLKMODA__TYPE u_int32_t +#define PLLCLKMODA__READ 0xffffffffU +#define PLLCLKMODA__WRITE 0xffffffffU + +#endif /* __PLLCLKMODA_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_PLLCLKMODA */ +#define INST_RADIO65_REG_BLOCK__CH0_PLLCLKMODA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PLLCLKMODA2 */ +#ifndef __PLLCLKMODA2_MACRO__ +#define __PLLCLKMODA2_MACRO__ + +/* macros for field spare */ +#define PLLCLKMODA2__SPARE__SHIFT 0 +#define PLLCLKMODA2__SPARE__WIDTH 3 +#define PLLCLKMODA2__SPARE__MASK 0x00000007U +#define PLLCLKMODA2__SPARE__READ(src) (u_int32_t)(src) & 0x00000007U +#define PLLCLKMODA2__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define PLLCLKMODA2__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define PLLCLKMODA2__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) + +/* macros for field global_clk_en */ +#define PLLCLKMODA2__GLOBAL_CLK_EN__SHIFT 3 +#define PLLCLKMODA2__GLOBAL_CLK_EN__WIDTH 1 +#define PLLCLKMODA2__GLOBAL_CLK_EN__MASK 0x00000008U +#define PLLCLKMODA2__GLOBAL_CLK_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define PLLCLKMODA2__GLOBAL_CLK_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define PLLCLKMODA2__GLOBAL_CLK_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define PLLCLKMODA2__GLOBAL_CLK_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define PLLCLKMODA2__GLOBAL_CLK_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define PLLCLKMODA2__GLOBAL_CLK_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field adc_clk_sel */ +#define PLLCLKMODA2__ADC_CLK_SEL__SHIFT 4 +#define PLLCLKMODA2__ADC_CLK_SEL__WIDTH 4 +#define PLLCLKMODA2__ADC_CLK_SEL__MASK 0x000000f0U +#define PLLCLKMODA2__ADC_CLK_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define PLLCLKMODA2__ADC_CLK_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define PLLCLKMODA2__ADC_CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define PLLCLKMODA2__ADC_CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field local_clkmoda */ +#define PLLCLKMODA2__LOCAL_CLKMODA__SHIFT 8 +#define PLLCLKMODA2__LOCAL_CLKMODA__WIDTH 1 +#define PLLCLKMODA2__LOCAL_CLKMODA__MASK 0x00000100U +#define PLLCLKMODA2__LOCAL_CLKMODA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define PLLCLKMODA2__LOCAL_CLKMODA__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define PLLCLKMODA2__LOCAL_CLKMODA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define PLLCLKMODA2__LOCAL_CLKMODA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define PLLCLKMODA2__LOCAL_CLKMODA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define PLLCLKMODA2__LOCAL_CLKMODA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field pllbypass */ +#define PLLCLKMODA2__PLLBYPASS__SHIFT 9 +#define PLLCLKMODA2__PLLBYPASS__WIDTH 1 +#define PLLCLKMODA2__PLLBYPASS__MASK 0x00000200U +#define PLLCLKMODA2__PLLBYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define PLLCLKMODA2__PLLBYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define PLLCLKMODA2__PLLBYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define PLLCLKMODA2__PLLBYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define PLLCLKMODA2__PLLBYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define PLLCLKMODA2__PLLBYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field local_pllbypass */ +#define PLLCLKMODA2__LOCAL_PLLBYPASS__SHIFT 10 +#define PLLCLKMODA2__LOCAL_PLLBYPASS__WIDTH 1 +#define PLLCLKMODA2__LOCAL_PLLBYPASS__MASK 0x00000400U +#define PLLCLKMODA2__LOCAL_PLLBYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define PLLCLKMODA2__LOCAL_PLLBYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define PLLCLKMODA2__LOCAL_PLLBYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define PLLCLKMODA2__LOCAL_PLLBYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define PLLCLKMODA2__LOCAL_PLLBYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define PLLCLKMODA2__LOCAL_PLLBYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field pllatb */ +#define PLLCLKMODA2__PLLATB__SHIFT 11 +#define PLLCLKMODA2__PLLATB__WIDTH 2 +#define PLLCLKMODA2__PLLATB__MASK 0x00001800U +#define PLLCLKMODA2__PLLATB__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11) +#define PLLCLKMODA2__PLLATB__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00001800U) +#define PLLCLKMODA2__PLLATB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define PLLCLKMODA2__PLLATB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field pll_svreg */ +#define PLLCLKMODA2__PLL_SVREG__SHIFT 13 +#define PLLCLKMODA2__PLL_SVREG__WIDTH 1 +#define PLLCLKMODA2__PLL_SVREG__MASK 0x00002000U +#define PLLCLKMODA2__PLL_SVREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define PLLCLKMODA2__PLL_SVREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define PLLCLKMODA2__PLL_SVREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define PLLCLKMODA2__PLL_SVREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define PLLCLKMODA2__PLL_SVREG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define PLLCLKMODA2__PLL_SVREG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field hi_freq_en */ +#define PLLCLKMODA2__HI_FREQ_EN__SHIFT 14 +#define PLLCLKMODA2__HI_FREQ_EN__WIDTH 1 +#define PLLCLKMODA2__HI_FREQ_EN__MASK 0x00004000U +#define PLLCLKMODA2__HI_FREQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define PLLCLKMODA2__HI_FREQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define PLLCLKMODA2__HI_FREQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define PLLCLKMODA2__HI_FREQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define PLLCLKMODA2__HI_FREQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define PLLCLKMODA2__HI_FREQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field dac_clk_sel */ +#define PLLCLKMODA2__DAC_CLK_SEL__SHIFT 15 +#define PLLCLKMODA2__DAC_CLK_SEL__WIDTH 3 +#define PLLCLKMODA2__DAC_CLK_SEL__MASK 0x00038000U +#define PLLCLKMODA2__DAC_CLK_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00038000U) >> 15) +#define PLLCLKMODA2__DAC_CLK_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00038000U) +#define PLLCLKMODA2__DAC_CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define PLLCLKMODA2__DAC_CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field rst_warm_int_l */ +#define PLLCLKMODA2__RST_WARM_INT_L__SHIFT 18 +#define PLLCLKMODA2__RST_WARM_INT_L__WIDTH 1 +#define PLLCLKMODA2__RST_WARM_INT_L__MASK 0x00040000U +#define PLLCLKMODA2__RST_WARM_INT_L__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define PLLCLKMODA2__RST_WARM_INT_L__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define PLLCLKMODA2__RST_WARM_INT_L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define PLLCLKMODA2__RST_WARM_INT_L__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define PLLCLKMODA2__RST_WARM_INT_L__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define PLLCLKMODA2__RST_WARM_INT_L__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field pll_kvco */ +#define PLLCLKMODA2__PLL_KVCO__SHIFT 19 +#define PLLCLKMODA2__PLL_KVCO__WIDTH 2 +#define PLLCLKMODA2__PLL_KVCO__MASK 0x00180000U +#define PLLCLKMODA2__PLL_KVCO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00180000U) >> 19) +#define PLLCLKMODA2__PLL_KVCO__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00180000U) +#define PLLCLKMODA2__PLL_KVCO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((u_int32_t)(src) <<\ + 19) & 0x00180000U) +#define PLLCLKMODA2__PLL_KVCO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00180000U))) + +/* macros for field pllicp */ +#define PLLCLKMODA2__PLLICP__SHIFT 21 +#define PLLCLKMODA2__PLLICP__WIDTH 3 +#define PLLCLKMODA2__PLLICP__MASK 0x00e00000U +#define PLLCLKMODA2__PLLICP__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21) +#define PLLCLKMODA2__PLLICP__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00e00000U) +#define PLLCLKMODA2__PLLICP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define PLLCLKMODA2__PLLICP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field pllfilter */ +#define PLLCLKMODA2__PLLFILTER__SHIFT 24 +#define PLLCLKMODA2__PLLFILTER__WIDTH 8 +#define PLLCLKMODA2__PLLFILTER__MASK 0xff000000U +#define PLLCLKMODA2__PLLFILTER__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define PLLCLKMODA2__PLLFILTER__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define PLLCLKMODA2__PLLFILTER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define PLLCLKMODA2__PLLFILTER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define PLLCLKMODA2__TYPE u_int32_t +#define PLLCLKMODA2__READ 0xffffffffU +#define PLLCLKMODA2__WRITE 0xffffffffU + +#endif /* __PLLCLKMODA2_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_PLLCLKMODA2 */ +#define INST_RADIO65_REG_BLOCK__CH0_PLLCLKMODA2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TOP */ +#ifndef __TOP_MACRO__ +#define __TOP_MACRO__ + +/* macros for field sel_tempsensor */ +#define TOP__SEL_TEMPSENSOR__SHIFT 0 +#define TOP__SEL_TEMPSENSOR__WIDTH 1 +#define TOP__SEL_TEMPSENSOR__MASK 0x00000001U +#define TOP__SEL_TEMPSENSOR__READ(src) (u_int32_t)(src) & 0x00000001U +#define TOP__SEL_TEMPSENSOR__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TOP__SEL_TEMPSENSOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TOP__SEL_TEMPSENSOR__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TOP__SEL_TEMPSENSOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TOP__SEL_TEMPSENSOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field xpabias_bypass */ +#define TOP__XPABIAS_BYPASS__SHIFT 1 +#define TOP__XPABIAS_BYPASS__WIDTH 1 +#define TOP__XPABIAS_BYPASS__MASK 0x00000002U +#define TOP__XPABIAS_BYPASS__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define TOP__XPABIAS_BYPASS__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define TOP__XPABIAS_BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define TOP__XPABIAS_BYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define TOP__XPABIAS_BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TOP__XPABIAS_BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field testiq_rsel */ +#define TOP__TESTIQ_RSEL__SHIFT 2 +#define TOP__TESTIQ_RSEL__WIDTH 1 +#define TOP__TESTIQ_RSEL__MASK 0x00000004U +#define TOP__TESTIQ_RSEL__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define TOP__TESTIQ_RSEL__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define TOP__TESTIQ_RSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define TOP__TESTIQ_RSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define TOP__TESTIQ_RSEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TOP__TESTIQ_RSEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field clk107_en */ +#define TOP__CLK107_EN__SHIFT 3 +#define TOP__CLK107_EN__WIDTH 1 +#define TOP__CLK107_EN__MASK 0x00000008U +#define TOP__CLK107_EN__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define TOP__CLK107_EN__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define TOP__CLK107_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TOP__CLK107_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define TOP__CLK107_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TOP__CLK107_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field test_pad_en */ +#define TOP__TEST_PAD_EN__SHIFT 4 +#define TOP__TEST_PAD_EN__WIDTH 1 +#define TOP__TEST_PAD_EN__MASK 0x00000010U +#define TOP__TEST_PAD_EN__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) +#define TOP__TEST_PAD_EN__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) +#define TOP__TEST_PAD_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define TOP__TEST_PAD_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define TOP__TEST_PAD_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define TOP__TEST_PAD_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field pwdv2i */ +#define TOP__PWDV2I__SHIFT 5 +#define TOP__PWDV2I__WIDTH 1 +#define TOP__PWDV2I__MASK 0x00000020U +#define TOP__PWDV2I__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define TOP__PWDV2I__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) +#define TOP__PWDV2I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define TOP__PWDV2I__VERIFY(src) (!((((u_int32_t)(src) << 5) & ~0x00000020U))) +#define TOP__PWDV2I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define TOP__PWDV2I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field pwdbias */ +#define TOP__PWDBIAS__SHIFT 6 +#define TOP__PWDBIAS__WIDTH 1 +#define TOP__PWDBIAS__MASK 0x00000040U +#define TOP__PWDBIAS__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define TOP__PWDBIAS__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) +#define TOP__PWDBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define TOP__PWDBIAS__VERIFY(src) (!((((u_int32_t)(src) << 6) & ~0x00000040U))) +#define TOP__PWDBIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define TOP__PWDBIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field pwdbg */ +#define TOP__PWDBG__SHIFT 7 +#define TOP__PWDBG__WIDTH 1 +#define TOP__PWDBG__MASK 0x00000080U +#define TOP__PWDBG__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define TOP__PWDBG__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) +#define TOP__PWDBG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define TOP__PWDBG__VERIFY(src) (!((((u_int32_t)(src) << 7) & ~0x00000080U))) +#define TOP__PWDBG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define TOP__PWDBG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field xpabiaslvl */ +#define TOP__XPABIASLVL__SHIFT 8 +#define TOP__XPABIASLVL__WIDTH 2 +#define TOP__XPABIASLVL__MASK 0x00000300U +#define TOP__XPABIASLVL__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8) +#define TOP__XPABIASLVL__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000300U) +#define TOP__XPABIASLVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define TOP__XPABIASLVL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field xparegulator_en */ +#define TOP__XPAREGULATOR_EN__SHIFT 10 +#define TOP__XPAREGULATOR_EN__WIDTH 1 +#define TOP__XPAREGULATOR_EN__MASK 0x00000400U +#define TOP__XPAREGULATOR_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define TOP__XPAREGULATOR_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define TOP__XPAREGULATOR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TOP__XPAREGULATOR_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TOP__XPAREGULATOR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TOP__XPAREGULATOR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field spare */ +#define TOP__SPARE__SHIFT 11 +#define TOP__SPARE__WIDTH 2 +#define TOP__SPARE__MASK 0x00001800U +#define TOP__SPARE__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11) +#define TOP__SPARE__WRITE(src) (((u_int32_t)(src) << 11) & 0x00001800U) +#define TOP__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define TOP__SPARE__VERIFY(src) (!((((u_int32_t)(src) << 11) & ~0x00001800U))) + +/* macros for field adc_clk_sel_ch1 */ +#define TOP__ADC_CLK_SEL_CH1__SHIFT 13 +#define TOP__ADC_CLK_SEL_CH1__WIDTH 4 +#define TOP__ADC_CLK_SEL_CH1__MASK 0x0001e000U +#define TOP__ADC_CLK_SEL_CH1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001e000U) >> 13) +#define TOP__ADC_CLK_SEL_CH1__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0001e000U) +#define TOP__ADC_CLK_SEL_CH1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0001e000U) +#define TOP__ADC_CLK_SEL_CH1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0001e000U))) + +/* macros for field testiq_off */ +#define TOP__TESTIQ_OFF__SHIFT 17 +#define TOP__TESTIQ_OFF__WIDTH 1 +#define TOP__TESTIQ_OFF__MASK 0x00020000U +#define TOP__TESTIQ_OFF__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17) +#define TOP__TESTIQ_OFF__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U) +#define TOP__TESTIQ_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define TOP__TESTIQ_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define TOP__TESTIQ_OFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define TOP__TESTIQ_OFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field testiq_bufen */ +#define TOP__TESTIQ_BUFEN__SHIFT 18 +#define TOP__TESTIQ_BUFEN__WIDTH 1 +#define TOP__TESTIQ_BUFEN__MASK 0x00040000U +#define TOP__TESTIQ_BUFEN__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define TOP__TESTIQ_BUFEN__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define TOP__TESTIQ_BUFEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define TOP__TESTIQ_BUFEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define TOP__TESTIQ_BUFEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define TOP__TESTIQ_BUFEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field pad2gnd */ +#define TOP__PAD2GND__SHIFT 19 +#define TOP__PAD2GND__WIDTH 1 +#define TOP__PAD2GND__MASK 0x00080000U +#define TOP__PAD2GND__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) +#define TOP__PAD2GND__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) +#define TOP__PAD2GND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TOP__PAD2GND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TOP__PAD2GND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TOP__PAD2GND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field intH2pad */ +#define TOP__INTH2PAD__SHIFT 20 +#define TOP__INTH2PAD__WIDTH 1 +#define TOP__INTH2PAD__MASK 0x00100000U +#define TOP__INTH2PAD__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define TOP__INTH2PAD__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) +#define TOP__INTH2PAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TOP__INTH2PAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TOP__INTH2PAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TOP__INTH2PAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field intH2gnd */ +#define TOP__INTH2GND__SHIFT 21 +#define TOP__INTH2GND__WIDTH 1 +#define TOP__INTH2GND__MASK 0x00200000U +#define TOP__INTH2GND__READ(src) (((u_int32_t)(src) & 0x00200000U) >> 21) +#define TOP__INTH2GND__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U) +#define TOP__INTH2GND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define TOP__INTH2GND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define TOP__INTH2GND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define TOP__INTH2GND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field int2pad */ +#define TOP__INT2PAD__SHIFT 22 +#define TOP__INT2PAD__WIDTH 1 +#define TOP__INT2PAD__MASK 0x00400000U +#define TOP__INT2PAD__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22) +#define TOP__INT2PAD__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U) +#define TOP__INT2PAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TOP__INT2PAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TOP__INT2PAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TOP__INT2PAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field int2gnd */ +#define TOP__INT2GND__SHIFT 23 +#define TOP__INT2GND__WIDTH 1 +#define TOP__INT2GND__MASK 0x00800000U +#define TOP__INT2GND__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) +#define TOP__INT2GND__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) +#define TOP__INT2GND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TOP__INT2GND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TOP__INT2GND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TOP__INT2GND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field enBTclk */ +#define TOP__ENBTCLK__SHIFT 24 +#define TOP__ENBTCLK__WIDTH 1 +#define TOP__ENBTCLK__MASK 0x01000000U +#define TOP__ENBTCLK__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define TOP__ENBTCLK__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U) +#define TOP__ENBTCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TOP__ENBTCLK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TOP__ENBTCLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TOP__ENBTCLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field pwdPALclk */ +#define TOP__PWDPALCLK__SHIFT 25 +#define TOP__PWDPALCLK__WIDTH 1 +#define TOP__PWDPALCLK__MASK 0x02000000U +#define TOP__PWDPALCLK__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) +#define TOP__PWDPALCLK__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U) +#define TOP__PWDPALCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define TOP__PWDPALCLK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define TOP__PWDPALCLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define TOP__PWDPALCLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field inv_clk320_adc */ +#define TOP__INV_CLK320_ADC__SHIFT 26 +#define TOP__INV_CLK320_ADC__WIDTH 1 +#define TOP__INV_CLK320_ADC__MASK 0x04000000U +#define TOP__INV_CLK320_ADC__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) +#define TOP__INV_CLK320_ADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define TOP__INV_CLK320_ADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define TOP__INV_CLK320_ADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define TOP__INV_CLK320_ADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define TOP__INV_CLK320_ADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field flip_refclk40 */ +#define TOP__FLIP_REFCLK40__SHIFT 27 +#define TOP__FLIP_REFCLK40__WIDTH 1 +#define TOP__FLIP_REFCLK40__MASK 0x08000000U +#define TOP__FLIP_REFCLK40__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) +#define TOP__FLIP_REFCLK40__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U) +#define TOP__FLIP_REFCLK40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define TOP__FLIP_REFCLK40__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define TOP__FLIP_REFCLK40__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define TOP__FLIP_REFCLK40__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field flip_pllclk320 */ +#define TOP__FLIP_PLLCLK320__SHIFT 28 +#define TOP__FLIP_PLLCLK320__WIDTH 1 +#define TOP__FLIP_PLLCLK320__MASK 0x10000000U +#define TOP__FLIP_PLLCLK320__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define TOP__FLIP_PLLCLK320__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TOP__FLIP_PLLCLK320__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TOP__FLIP_PLLCLK320__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TOP__FLIP_PLLCLK320__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TOP__FLIP_PLLCLK320__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field flip_pllclk160 */ +#define TOP__FLIP_PLLCLK160__SHIFT 29 +#define TOP__FLIP_PLLCLK160__WIDTH 1 +#define TOP__FLIP_PLLCLK160__MASK 0x20000000U +#define TOP__FLIP_PLLCLK160__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define TOP__FLIP_PLLCLK160__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define TOP__FLIP_PLLCLK160__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define TOP__FLIP_PLLCLK160__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define TOP__FLIP_PLLCLK160__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define TOP__FLIP_PLLCLK160__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field clk_sel */ +#define TOP__CLK_SEL__SHIFT 30 +#define TOP__CLK_SEL__WIDTH 2 +#define TOP__CLK_SEL__MASK 0xc0000000U +#define TOP__CLK_SEL__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) +#define TOP__CLK_SEL__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U) +#define TOP__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define TOP__CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define TOP__TYPE u_int32_t +#define TOP__READ 0xffffffffU +#define TOP__WRITE 0xffffffffU + +#endif /* __TOP_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TOP */ +#define INST_RADIO65_REG_BLOCK__CH0_TOP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TOP2 */ +#ifndef __TOP2_MACRO__ +#define __TOP2_MACRO__ + +/* macros for field testtxiq_enbypass_b */ +#define TOP2__TESTTXIQ_ENBYPASS_B__SHIFT 0 +#define TOP2__TESTTXIQ_ENBYPASS_B__WIDTH 3 +#define TOP2__TESTTXIQ_ENBYPASS_B__MASK 0x00000007U +#define TOP2__TESTTXIQ_ENBYPASS_B__READ(src) (u_int32_t)(src) & 0x00000007U +#define TOP2__TESTTXIQ_ENBYPASS_B__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define TOP2__TESTTXIQ_ENBYPASS_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define TOP2__TESTTXIQ_ENBYPASS_B__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field dac_clk_sel_ch2 */ +#define TOP2__DAC_CLK_SEL_CH2__SHIFT 3 +#define TOP2__DAC_CLK_SEL_CH2__WIDTH 3 +#define TOP2__DAC_CLK_SEL_CH2__MASK 0x00000038U +#define TOP2__DAC_CLK_SEL_CH2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define TOP2__DAC_CLK_SEL_CH2__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define TOP2__DAC_CLK_SEL_CH2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define TOP2__DAC_CLK_SEL_CH2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field dac_clk_sel_ch1 */ +#define TOP2__DAC_CLK_SEL_CH1__SHIFT 6 +#define TOP2__DAC_CLK_SEL_CH1__WIDTH 3 +#define TOP2__DAC_CLK_SEL_CH1__MASK 0x000001c0U +#define TOP2__DAC_CLK_SEL_CH1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001c0U) >> 6) +#define TOP2__DAC_CLK_SEL_CH1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000001c0U) +#define TOP2__DAC_CLK_SEL_CH1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define TOP2__DAC_CLK_SEL_CH1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field testtxiq_rctrl */ +#define TOP2__TESTTXIQ_RCTRL__SHIFT 9 +#define TOP2__TESTTXIQ_RCTRL__WIDTH 3 +#define TOP2__TESTTXIQ_RCTRL__MASK 0x00000e00U +#define TOP2__TESTTXIQ_RCTRL__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) +#define TOP2__TESTTXIQ_RCTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define TOP2__TESTTXIQ_RCTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define TOP2__TESTTXIQ_RCTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field testtxiq_enloopback */ +#define TOP2__TESTTXIQ_ENLOOPBACK__SHIFT 12 +#define TOP2__TESTTXIQ_ENLOOPBACK__WIDTH 3 +#define TOP2__TESTTXIQ_ENLOOPBACK__MASK 0x00007000U +#define TOP2__TESTTXIQ_ENLOOPBACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007000U) >> 12) +#define TOP2__TESTTXIQ_ENLOOPBACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00007000U) +#define TOP2__TESTTXIQ_ENLOOPBACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define TOP2__TESTTXIQ_ENLOOPBACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field testtxiq_pwd */ +#define TOP2__TESTTXIQ_PWD__SHIFT 15 +#define TOP2__TESTTXIQ_PWD__WIDTH 3 +#define TOP2__TESTTXIQ_PWD__MASK 0x00038000U +#define TOP2__TESTTXIQ_PWD__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) +#define TOP2__TESTTXIQ_PWD__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) +#define TOP2__TESTTXIQ_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define TOP2__TESTTXIQ_PWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field dacpwd */ +#define TOP2__DACPWD__SHIFT 18 +#define TOP2__DACPWD__WIDTH 3 +#define TOP2__DACPWD__MASK 0x001c0000U +#define TOP2__DACPWD__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18) +#define TOP2__DACPWD__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U) +#define TOP2__DACPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define TOP2__DACPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field adcpwd */ +#define TOP2__ADCPWD__SHIFT 21 +#define TOP2__ADCPWD__WIDTH 3 +#define TOP2__ADCPWD__MASK 0x00e00000U +#define TOP2__ADCPWD__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21) +#define TOP2__ADCPWD__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U) +#define TOP2__ADCPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define TOP2__ADCPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field local_addacpwd */ +#define TOP2__LOCAL_ADDACPWD__SHIFT 24 +#define TOP2__LOCAL_ADDACPWD__WIDTH 1 +#define TOP2__LOCAL_ADDACPWD__MASK 0x01000000U +#define TOP2__LOCAL_ADDACPWD__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TOP2__LOCAL_ADDACPWD__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TOP2__LOCAL_ADDACPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TOP2__LOCAL_ADDACPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TOP2__LOCAL_ADDACPWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TOP2__LOCAL_ADDACPWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field local_xpaon */ +#define TOP2__LOCAL_XPAON__SHIFT 25 +#define TOP2__LOCAL_XPAON__WIDTH 1 +#define TOP2__LOCAL_XPAON__MASK 0x02000000U +#define TOP2__LOCAL_XPAON__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) +#define TOP2__LOCAL_XPAON__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U) +#define TOP2__LOCAL_XPAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define TOP2__LOCAL_XPAON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define TOP2__LOCAL_XPAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define TOP2__LOCAL_XPAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field xpa5on */ +#define TOP2__XPA5ON__SHIFT 26 +#define TOP2__XPA5ON__WIDTH 3 +#define TOP2__XPA5ON__MASK 0x1c000000U +#define TOP2__XPA5ON__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define TOP2__XPA5ON__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define TOP2__XPA5ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TOP2__XPA5ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field xpa2on */ +#define TOP2__XPA2ON__SHIFT 29 +#define TOP2__XPA2ON__WIDTH 3 +#define TOP2__XPA2ON__MASK 0xe0000000U +#define TOP2__XPA2ON__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define TOP2__XPA2ON__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define TOP2__XPA2ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define TOP2__XPA2ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define TOP2__TYPE u_int32_t +#define TOP2__READ 0xffffffffU +#define TOP2__WRITE 0xffffffffU + +#endif /* __TOP2_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_TOP2 */ +#define INST_RADIO65_REG_BLOCK__CH0_TOP2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::THERM */ +#ifndef __THERM_MACRO__ +#define __THERM_MACRO__ + +/* macros for field xpabiaslvl_MSB */ +#define THERM__XPABIASLVL_MSB__SHIFT 0 +#define THERM__XPABIASLVL_MSB__WIDTH 2 +#define THERM__XPABIASLVL_MSB__MASK 0x00000003U +#define THERM__XPABIASLVL_MSB__READ(src) (u_int32_t)(src) & 0x00000003U +#define THERM__XPABIASLVL_MSB__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define THERM__XPABIASLVL_MSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define THERM__XPABIASLVL_MSB__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field xpashort2gnd */ +#define THERM__XPASHORT2GND__SHIFT 2 +#define THERM__XPASHORT2GND__WIDTH 1 +#define THERM__XPASHORT2GND__MASK 0x00000004U +#define THERM__XPASHORT2GND__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define THERM__XPASHORT2GND__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define THERM__XPASHORT2GND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define THERM__XPASHORT2GND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define THERM__XPASHORT2GND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define THERM__XPASHORT2GND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field adc_clk_sel_ch2 */ +#define THERM__ADC_CLK_SEL_CH2__SHIFT 3 +#define THERM__ADC_CLK_SEL_CH2__WIDTH 4 +#define THERM__ADC_CLK_SEL_CH2__MASK 0x00000078U +#define THERM__ADC_CLK_SEL_CH2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000078U) >> 3) +#define THERM__ADC_CLK_SEL_CH2__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000078U) +#define THERM__ADC_CLK_SEL_CH2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000078U) | (((u_int32_t)(src) <<\ + 3) & 0x00000078U) +#define THERM__ADC_CLK_SEL_CH2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000078U))) + +/* macros for field sar_adc_done */ +#define THERM__SAR_ADC_DONE__SHIFT 7 +#define THERM__SAR_ADC_DONE__WIDTH 1 +#define THERM__SAR_ADC_DONE__MASK 0x00000080U +#define THERM__SAR_ADC_DONE__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define THERM__SAR_ADC_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define THERM__SAR_ADC_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field sar_adc_out */ +#define THERM__SAR_ADC_OUT__SHIFT 8 +#define THERM__SAR_ADC_OUT__WIDTH 8 +#define THERM__SAR_ADC_OUT__MASK 0x0000ff00U +#define THERM__SAR_ADC_OUT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) + +/* macros for field sar_dactest_code */ +#define THERM__SAR_DACTEST_CODE__SHIFT 16 +#define THERM__SAR_DACTEST_CODE__WIDTH 8 +#define THERM__SAR_DACTEST_CODE__MASK 0x00ff0000U +#define THERM__SAR_DACTEST_CODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define THERM__SAR_DACTEST_CODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define THERM__SAR_DACTEST_CODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define THERM__SAR_DACTEST_CODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field sar_dactest_en */ +#define THERM__SAR_DACTEST_EN__SHIFT 24 +#define THERM__SAR_DACTEST_EN__WIDTH 1 +#define THERM__SAR_DACTEST_EN__MASK 0x01000000U +#define THERM__SAR_DACTEST_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define THERM__SAR_DACTEST_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define THERM__SAR_DACTEST_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define THERM__SAR_DACTEST_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define THERM__SAR_DACTEST_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define THERM__SAR_DACTEST_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field sar_adccal_en */ +#define THERM__SAR_ADCCAL_EN__SHIFT 25 +#define THERM__SAR_ADCCAL_EN__WIDTH 1 +#define THERM__SAR_ADCCAL_EN__MASK 0x02000000U +#define THERM__SAR_ADCCAL_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define THERM__SAR_ADCCAL_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define THERM__SAR_ADCCAL_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define THERM__SAR_ADCCAL_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define THERM__SAR_ADCCAL_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define THERM__SAR_ADCCAL_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field thermsel */ +#define THERM__THERMSEL__SHIFT 26 +#define THERM__THERMSEL__WIDTH 2 +#define THERM__THERMSEL__MASK 0x0c000000U +#define THERM__THERMSEL__READ(src) (((u_int32_t)(src) & 0x0c000000U) >> 26) +#define THERM__THERMSEL__WRITE(src) (((u_int32_t)(src) << 26) & 0x0c000000U) +#define THERM__THERMSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define THERM__THERMSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) + +/* macros for field sar_slow_en */ +#define THERM__SAR_SLOW_EN__SHIFT 28 +#define THERM__SAR_SLOW_EN__WIDTH 1 +#define THERM__SAR_SLOW_EN__MASK 0x10000000U +#define THERM__SAR_SLOW_EN__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define THERM__SAR_SLOW_EN__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define THERM__SAR_SLOW_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define THERM__SAR_SLOW_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define THERM__SAR_SLOW_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define THERM__SAR_SLOW_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field thermstart */ +#define THERM__THERMSTART__SHIFT 29 +#define THERM__THERMSTART__WIDTH 1 +#define THERM__THERMSTART__MASK 0x20000000U +#define THERM__THERMSTART__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define THERM__THERMSTART__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define THERM__THERMSTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define THERM__THERMSTART__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define THERM__THERMSTART__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define THERM__THERMSTART__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field sar_autopwd_en */ +#define THERM__SAR_AUTOPWD_EN__SHIFT 30 +#define THERM__SAR_AUTOPWD_EN__WIDTH 1 +#define THERM__SAR_AUTOPWD_EN__MASK 0x40000000U +#define THERM__SAR_AUTOPWD_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define THERM__SAR_AUTOPWD_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define THERM__SAR_AUTOPWD_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define THERM__SAR_AUTOPWD_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define THERM__SAR_AUTOPWD_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define THERM__SAR_AUTOPWD_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field local_therm */ +#define THERM__LOCAL_THERM__SHIFT 31 +#define THERM__LOCAL_THERM__WIDTH 1 +#define THERM__LOCAL_THERM__MASK 0x80000000U +#define THERM__LOCAL_THERM__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define THERM__LOCAL_THERM__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) +#define THERM__LOCAL_THERM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define THERM__LOCAL_THERM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define THERM__LOCAL_THERM__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define THERM__LOCAL_THERM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define THERM__TYPE u_int32_t +#define THERM__READ 0xffffffffU +#define THERM__WRITE 0xffffffffU + +#endif /* __THERM_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_THERM */ +#define INST_RADIO65_REG_BLOCK__CH0_THERM__NUM 1 + +/* macros for BlueprintGlobalNameSpace::XTAL */ +#ifndef __XTAL_MACRO__ +#define __XTAL_MACRO__ + +/* macros for field spare */ +#define XTAL__SPARE__SHIFT 0 +#define XTAL__SPARE__WIDTH 6 +#define XTAL__SPARE__MASK 0x0000003fU +#define XTAL__SPARE__READ(src) (u_int32_t)(src) & 0x0000003fU +#define XTAL__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define XTAL__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define XTAL__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000003fU))) + +/* macros for field local_xtal */ +#define XTAL__LOCAL_XTAL__SHIFT 6 +#define XTAL__LOCAL_XTAL__WIDTH 1 +#define XTAL__LOCAL_XTAL__MASK 0x00000040U +#define XTAL__LOCAL_XTAL__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define XTAL__LOCAL_XTAL__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) +#define XTAL__LOCAL_XTAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define XTAL__LOCAL_XTAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define XTAL__LOCAL_XTAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define XTAL__LOCAL_XTAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field xtal_pwdclkin */ +#define XTAL__XTAL_PWDCLKIN__SHIFT 7 +#define XTAL__XTAL_PWDCLKIN__WIDTH 1 +#define XTAL__XTAL_PWDCLKIN__MASK 0x00000080U +#define XTAL__XTAL_PWDCLKIN__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define XTAL__XTAL_PWDCLKIN__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) +#define XTAL__XTAL_PWDCLKIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define XTAL__XTAL_PWDCLKIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define XTAL__XTAL_PWDCLKIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define XTAL__XTAL_PWDCLKIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field xtal_oscon */ +#define XTAL__XTAL_OSCON__SHIFT 8 +#define XTAL__XTAL_OSCON__WIDTH 1 +#define XTAL__XTAL_OSCON__MASK 0x00000100U +#define XTAL__XTAL_OSCON__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define XTAL__XTAL_OSCON__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) +#define XTAL__XTAL_OSCON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define XTAL__XTAL_OSCON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define XTAL__XTAL_OSCON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define XTAL__XTAL_OSCON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field xtal_selvreg */ +#define XTAL__XTAL_SELVREG__SHIFT 9 +#define XTAL__XTAL_SELVREG__WIDTH 1 +#define XTAL__XTAL_SELVREG__MASK 0x00000200U +#define XTAL__XTAL_SELVREG__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define XTAL__XTAL_SELVREG__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) +#define XTAL__XTAL_SELVREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define XTAL__XTAL_SELVREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define XTAL__XTAL_SELVREG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define XTAL__XTAL_SELVREG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field xtal_Lbias2x */ +#define XTAL__XTAL_LBIAS2X__SHIFT 10 +#define XTAL__XTAL_LBIAS2X__WIDTH 1 +#define XTAL__XTAL_LBIAS2X__MASK 0x00000400U +#define XTAL__XTAL_LBIAS2X__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define XTAL__XTAL_LBIAS2X__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) +#define XTAL__XTAL_LBIAS2X__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define XTAL__XTAL_LBIAS2X__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define XTAL__XTAL_LBIAS2X__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define XTAL__XTAL_LBIAS2X__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field xtal_bias2x */ +#define XTAL__XTAL_BIAS2X__SHIFT 11 +#define XTAL__XTAL_BIAS2X__WIDTH 1 +#define XTAL__XTAL_BIAS2X__MASK 0x00000800U +#define XTAL__XTAL_BIAS2X__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define XTAL__XTAL_BIAS2X__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define XTAL__XTAL_BIAS2X__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define XTAL__XTAL_BIAS2X__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define XTAL__XTAL_BIAS2X__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define XTAL__XTAL_BIAS2X__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field xtal_pwdclkD */ +#define XTAL__XTAL_PWDCLKD__SHIFT 12 +#define XTAL__XTAL_PWDCLKD__WIDTH 1 +#define XTAL__XTAL_PWDCLKD__MASK 0x00001000U +#define XTAL__XTAL_PWDCLKD__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) +#define XTAL__XTAL_PWDCLKD__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) +#define XTAL__XTAL_PWDCLKD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define XTAL__XTAL_PWDCLKD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define XTAL__XTAL_PWDCLKD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define XTAL__XTAL_PWDCLKD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field xtal_localbias */ +#define XTAL__XTAL_LOCALBIAS__SHIFT 13 +#define XTAL__XTAL_LOCALBIAS__WIDTH 1 +#define XTAL__XTAL_LOCALBIAS__MASK 0x00002000U +#define XTAL__XTAL_LOCALBIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define XTAL__XTAL_LOCALBIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define XTAL__XTAL_LOCALBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define XTAL__XTAL_LOCALBIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define XTAL__XTAL_LOCALBIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define XTAL__XTAL_LOCALBIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field xtal_shortXin */ +#define XTAL__XTAL_SHORTXIN__SHIFT 14 +#define XTAL__XTAL_SHORTXIN__WIDTH 1 +#define XTAL__XTAL_SHORTXIN__MASK 0x00004000U +#define XTAL__XTAL_SHORTXIN__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) +#define XTAL__XTAL_SHORTXIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define XTAL__XTAL_SHORTXIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define XTAL__XTAL_SHORTXIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define XTAL__XTAL_SHORTXIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define XTAL__XTAL_SHORTXIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field xtal_drvstr */ +#define XTAL__XTAL_DRVSTR__SHIFT 15 +#define XTAL__XTAL_DRVSTR__WIDTH 2 +#define XTAL__XTAL_DRVSTR__MASK 0x00018000U +#define XTAL__XTAL_DRVSTR__READ(src) (((u_int32_t)(src) & 0x00018000U) >> 15) +#define XTAL__XTAL_DRVSTR__WRITE(src) (((u_int32_t)(src) << 15) & 0x00018000U) +#define XTAL__XTAL_DRVSTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00018000U) | (((u_int32_t)(src) <<\ + 15) & 0x00018000U) +#define XTAL__XTAL_DRVSTR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00018000U))) + +/* macros for field xtal_capoutdac */ +#define XTAL__XTAL_CAPOUTDAC__SHIFT 17 +#define XTAL__XTAL_CAPOUTDAC__WIDTH 7 +#define XTAL__XTAL_CAPOUTDAC__MASK 0x00fe0000U +#define XTAL__XTAL_CAPOUTDAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fe0000U) >> 17) +#define XTAL__XTAL_CAPOUTDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00fe0000U) +#define XTAL__XTAL_CAPOUTDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x00fe0000U) +#define XTAL__XTAL_CAPOUTDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00fe0000U))) + +/* macros for field xtal_capindac */ +#define XTAL__XTAL_CAPINDAC__SHIFT 24 +#define XTAL__XTAL_CAPINDAC__WIDTH 7 +#define XTAL__XTAL_CAPINDAC__MASK 0x7f000000U +#define XTAL__XTAL_CAPINDAC__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24) +#define XTAL__XTAL_CAPINDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define XTAL__XTAL_CAPINDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define XTAL__XTAL_CAPINDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) + +/* macros for field tcxodet */ +#define XTAL__TCXODET__SHIFT 31 +#define XTAL__TCXODET__WIDTH 1 +#define XTAL__TCXODET__MASK 0x80000000U +#define XTAL__TCXODET__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define XTAL__TCXODET__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define XTAL__TCXODET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define XTAL__TYPE u_int32_t +#define XTAL__READ 0xffffffffU +#define XTAL__WRITE 0xffffffffU + +#endif /* __XTAL_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_XTAL */ +#define INST_RADIO65_REG_BLOCK__CH0_XTAL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rbist_cntrl_type */ +#ifndef __RBIST_CNTRL_TYPE_MACRO__ +#define __RBIST_CNTRL_TYPE_MACRO__ + +/* macros for field ate_tonegen_dc_enable */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__SHIFT 0 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__MASK 0x00000001U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ate_tonegen_tone0_enable */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__SHIFT 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__MASK 0x00000002U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field ate_tonegen_tone1_enable */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__SHIFT 2 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__MASK 0x00000004U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field ate_tonegen_lftone0_enable */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__SHIFT 3 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__MASK 0x00000008U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field ate_tonegen_linramp_enable_i */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__SHIFT 4 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__MASK 0x00000010U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field ate_tonegen_linramp_enable_q */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__SHIFT 5 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__MASK 0x00000020U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field ate_tonegen_prbs_enable_i */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__SHIFT 6 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__MASK 0x00000040U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field ate_tonegen_prbs_enable_q */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__SHIFT 7 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__MASK 0x00000080U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field ate_cmac_dc_write_to_cancel */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__SHIFT 8 +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__MASK 0x00000100U +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field ate_cmac_dc_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__SHIFT 9 +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__MASK 0x00000200U +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field ate_cmac_corr_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__SHIFT 10 +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__MASK 0x00000400U +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field ate_cmac_power_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__SHIFT 11 +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__MASK 0x00000800U +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field ate_cmac_iq_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__SHIFT 12 +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__MASK 0x00001000U +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field ate_cmac_i2q2_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__SHIFT 13 +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__MASK 0x00002000U +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field ate_cmac_power_hpf_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__SHIFT 14 +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__MASK 0x00004000U +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field ate_rxdac_calibrate */ +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__SHIFT 15 +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__MASK 0x00008000U +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field ate_rbist_enable */ +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__SHIFT 16 +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__MASK 0x00010000U +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) +#define RBIST_CNTRL_TYPE__TYPE u_int32_t +#define RBIST_CNTRL_TYPE__READ 0x0001ffffU +#define RBIST_CNTRL_TYPE__WRITE 0x0001ffffU + +#endif /* __RBIST_CNTRL_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_rbist_cntrl */ +#define INST_RADIO65_REG_BLOCK__CH0_RBIST_CNTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_dc_offset_type */ +#ifndef __TX_DC_OFFSET_TYPE_MACRO__ +#define __TX_DC_OFFSET_TYPE_MACRO__ + +/* macros for field ate_tonegen_dc_i */ +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__SHIFT 0 +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__WIDTH 11 +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__MASK 0x000007ffU +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__READ(src) \ + (u_int32_t)(src)\ + & 0x000007ffU +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000007ffU) +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000007ffU))) + +/* macros for field ate_tonegen_dc_q */ +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__SHIFT 16 +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__WIDTH 11 +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__MASK 0x07ff0000U +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) +#define TX_DC_OFFSET_TYPE__TYPE u_int32_t +#define TX_DC_OFFSET_TYPE__READ 0x07ff07ffU +#define TX_DC_OFFSET_TYPE__WRITE 0x07ff07ffU + +#endif /* __TX_DC_OFFSET_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_tx_dc_offset */ +#define INST_RADIO65_REG_BLOCK__CH0_TX_DC_OFFSET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_tonegen_type */ +#ifndef __TX_TONEGEN_TYPE_MACRO__ +#define __TX_TONEGEN_TYPE_MACRO__ + +/* macros for field ate_tonegen_tone_freq */ +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__SHIFT 0 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__WIDTH 7 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__MASK 0x0000007fU +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field ate_tonegen_tone_A_exp */ +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__SHIFT 8 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__WIDTH 4 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__MASK 0x00000f00U +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field ate_tonegen_tone_A_man */ +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__SHIFT 16 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__WIDTH 8 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__MASK 0x00ff0000U +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field ate_tonegen_tone_tau_k */ +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__SHIFT 24 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__WIDTH 7 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__MASK 0x7f000000U +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f000000U) >> 24) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) +#define TX_TONEGEN_TYPE__TYPE u_int32_t +#define TX_TONEGEN_TYPE__READ 0x7fff0f7fU +#define TX_TONEGEN_TYPE__WRITE 0x7fff0f7fU + +#endif /* __TX_TONEGEN_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_tx_tonegen0 */ +#define INST_RADIO65_REG_BLOCK__CH0_TX_TONEGEN0__NUM 1 + +/* macros for radio65_reg_block.ch0_tx_tonegen1 */ +#define INST_RADIO65_REG_BLOCK__CH0_TX_TONEGEN1__NUM 1 + +/* macros for radio65_reg_block.ch0_tx_lftonegen0 */ +#define INST_RADIO65_REG_BLOCK__CH0_TX_LFTONEGEN0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_linear_ramp_type */ +#ifndef __TX_LINEAR_RAMP_TYPE_MACRO__ +#define __TX_LINEAR_RAMP_TYPE_MACRO__ + +/* macros for field ate_tonegen_linramp_init */ +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__SHIFT 0 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__WIDTH 11 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__MASK 0x000007ffU +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__READ(src) \ + (u_int32_t)(src)\ + & 0x000007ffU +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000007ffU) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000007ffU))) + +/* macros for field ate_tonegen_linramp_dwell */ +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__SHIFT 12 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__WIDTH 10 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__MASK 0x003ff000U +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__READ(src) \ + (((u_int32_t)(src)\ + & 0x003ff000U) >> 12) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x003ff000U) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x003ff000U) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x003ff000U))) + +/* macros for field ate_tonegen_linramp_step */ +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__SHIFT 24 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__WIDTH 6 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__MASK 0x3f000000U +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define TX_LINEAR_RAMP_TYPE__TYPE u_int32_t +#define TX_LINEAR_RAMP_TYPE__READ 0x3f3ff7ffU +#define TX_LINEAR_RAMP_TYPE__WRITE 0x3f3ff7ffU + +#endif /* __TX_LINEAR_RAMP_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_tx_linear_ramp_i */ +#define INST_RADIO65_REG_BLOCK__CH0_TX_LINEAR_RAMP_I__NUM 1 + +/* macros for radio65_reg_block.ch0_tx_linear_ramp_q */ +#define INST_RADIO65_REG_BLOCK__CH0_TX_LINEAR_RAMP_Q__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_prbs_mag_type */ +#ifndef __TX_PRBS_MAG_TYPE_MACRO__ +#define __TX_PRBS_MAG_TYPE_MACRO__ + +/* macros for field ate_tonegen_prbs_magnitude_i */ +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__SHIFT 0 +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__WIDTH 10 +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__MASK 0x000003ffU +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field ate_tonegen_prbs_magnitude_q */ +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__SHIFT 16 +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__WIDTH 10 +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__MASK 0x03ff0000U +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x03ff0000U) >> 16) +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x03ff0000U) +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x03ff0000U) +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define TX_PRBS_MAG_TYPE__TYPE u_int32_t +#define TX_PRBS_MAG_TYPE__READ 0x03ff03ffU +#define TX_PRBS_MAG_TYPE__WRITE 0x03ff03ffU + +#endif /* __TX_PRBS_MAG_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_tx_prbs_mag */ +#define INST_RADIO65_REG_BLOCK__CH0_TX_PRBS_MAG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_prbs_seed_type */ +#ifndef __TX_PRBS_SEED_TYPE_MACRO__ +#define __TX_PRBS_SEED_TYPE_MACRO__ + +/* macros for field ate_tonegen_prbs_seed */ +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__SHIFT 0 +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__WIDTH 31 +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__MASK 0x7fffffffU +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__READ(src) \ + (u_int32_t)(src)\ + & 0x7fffffffU +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x7fffffffU) +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7fffffffU) | ((u_int32_t)(src) &\ + 0x7fffffffU) +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x7fffffffU))) +#define TX_PRBS_SEED_TYPE__TYPE u_int32_t +#define TX_PRBS_SEED_TYPE__READ 0x7fffffffU +#define TX_PRBS_SEED_TYPE__WRITE 0x7fffffffU + +#endif /* __TX_PRBS_SEED_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_tx_prbs_seed_i */ +#define INST_RADIO65_REG_BLOCK__CH0_TX_PRBS_SEED_I__NUM 1 + +/* macros for radio65_reg_block.ch0_tx_prbs_seed_q */ +#define INST_RADIO65_REG_BLOCK__CH0_TX_PRBS_SEED_Q__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_dc_cancel_type */ +#ifndef __CMAC_DC_CANCEL_TYPE_MACRO__ +#define __CMAC_DC_CANCEL_TYPE_MACRO__ + +/* macros for field ate_cmac_dc_cancel_i */ +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__SHIFT 0 +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__WIDTH 10 +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__MASK 0x000003ffU +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field ate_cmac_dc_cancel_q */ +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__SHIFT 16 +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__WIDTH 10 +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__MASK 0x03ff0000U +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x03ff0000U) >> 16) +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x03ff0000U) +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x03ff0000U) +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define CMAC_DC_CANCEL_TYPE__TYPE u_int32_t +#define CMAC_DC_CANCEL_TYPE__READ 0x03ff03ffU +#define CMAC_DC_CANCEL_TYPE__WRITE 0x03ff03ffU + +#endif /* __CMAC_DC_CANCEL_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_cmac_dc_cancel */ +#define INST_RADIO65_REG_BLOCK__CH0_CMAC_DC_CANCEL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_dc_offset_type */ +#ifndef __CMAC_DC_OFFSET_TYPE_MACRO__ +#define __CMAC_DC_OFFSET_TYPE_MACRO__ + +/* macros for field ate_cmac_dc_cycles */ +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__SHIFT 0 +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__WIDTH 4 +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__MASK 0x0000000fU +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define CMAC_DC_OFFSET_TYPE__TYPE u_int32_t +#define CMAC_DC_OFFSET_TYPE__READ 0x0000000fU +#define CMAC_DC_OFFSET_TYPE__WRITE 0x0000000fU + +#endif /* __CMAC_DC_OFFSET_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_cmac_dc_offset */ +#define INST_RADIO65_REG_BLOCK__CH0_CMAC_DC_OFFSET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_corr_type */ +#ifndef __CMAC_CORR_TYPE_MACRO__ +#define __CMAC_CORR_TYPE_MACRO__ + +/* macros for field ate_cmac_corr_cycles */ +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__SHIFT 0 +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__WIDTH 5 +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__MASK 0x0000001fU +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field ate_cmac_corr_freq */ +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__SHIFT 8 +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__WIDTH 6 +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__MASK 0x00003f00U +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) +#define CMAC_CORR_TYPE__TYPE u_int32_t +#define CMAC_CORR_TYPE__READ 0x00003f1fU +#define CMAC_CORR_TYPE__WRITE 0x00003f1fU + +#endif /* __CMAC_CORR_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_cmac_corr */ +#define INST_RADIO65_REG_BLOCK__CH0_CMAC_CORR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_power_type */ +#ifndef __CMAC_POWER_TYPE_MACRO__ +#define __CMAC_POWER_TYPE_MACRO__ + +/* macros for field ate_cmac_power_cycles */ +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__SHIFT 0 +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__WIDTH 4 +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__MASK 0x0000000fU +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define CMAC_POWER_TYPE__TYPE u_int32_t +#define CMAC_POWER_TYPE__READ 0x0000000fU +#define CMAC_POWER_TYPE__WRITE 0x0000000fU + +#endif /* __CMAC_POWER_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_cmac_power */ +#define INST_RADIO65_REG_BLOCK__CH0_CMAC_POWER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_cross_corr_type */ +#ifndef __CMAC_CROSS_CORR_TYPE_MACRO__ +#define __CMAC_CROSS_CORR_TYPE_MACRO__ + +/* macros for field ate_cmac_iq_cycles */ +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__SHIFT 0 +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__WIDTH 4 +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__MASK 0x0000000fU +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define CMAC_CROSS_CORR_TYPE__TYPE u_int32_t +#define CMAC_CROSS_CORR_TYPE__READ 0x0000000fU +#define CMAC_CROSS_CORR_TYPE__WRITE 0x0000000fU + +#endif /* __CMAC_CROSS_CORR_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_cmac_cross_corr */ +#define INST_RADIO65_REG_BLOCK__CH0_CMAC_CROSS_CORR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_i2q2_type */ +#ifndef __CMAC_I2Q2_TYPE_MACRO__ +#define __CMAC_I2Q2_TYPE_MACRO__ + +/* macros for field ate_cmac_i2q2_cycles */ +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__SHIFT 0 +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__WIDTH 4 +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__MASK 0x0000000fU +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define CMAC_I2Q2_TYPE__TYPE u_int32_t +#define CMAC_I2Q2_TYPE__READ 0x0000000fU +#define CMAC_I2Q2_TYPE__WRITE 0x0000000fU + +#endif /* __CMAC_I2Q2_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_cmac_i2q2 */ +#define INST_RADIO65_REG_BLOCK__CH0_CMAC_I2Q2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_power_hpf_type */ +#ifndef __CMAC_POWER_HPF_TYPE_MACRO__ +#define __CMAC_POWER_HPF_TYPE_MACRO__ + +/* macros for field ate_cmac_power_hpf_cycles */ +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__SHIFT 0 +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__WIDTH 4 +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__MASK 0x0000000fU +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field ate_cmac_power_hpf_wait */ +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__SHIFT 4 +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__WIDTH 4 +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__MASK 0x000000f0U +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) +#define CMAC_POWER_HPF_TYPE__TYPE u_int32_t +#define CMAC_POWER_HPF_TYPE__READ 0x000000ffU +#define CMAC_POWER_HPF_TYPE__WRITE 0x000000ffU + +#endif /* __CMAC_POWER_HPF_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_cmac_power_hpf */ +#define INST_RADIO65_REG_BLOCK__CH0_CMAC_POWER_HPF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rxdac_set1_type */ +#ifndef __RXDAC_SET1_TYPE_MACRO__ +#define __RXDAC_SET1_TYPE_MACRO__ + +/* macros for field ate_rxdac_mux */ +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__SHIFT 0 +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__WIDTH 2 +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__MASK 0x00000003U +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field ate_rxdac_hi_gain */ +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__SHIFT 4 +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__WIDTH 1 +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__MASK 0x00000010U +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field ate_rxdac_cal_wait */ +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__SHIFT 8 +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__WIDTH 6 +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__MASK 0x00003f00U +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field ate_rxdac_cal_measure_time */ +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__SHIFT 16 +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__WIDTH 4 +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__MASK 0x000f0000U +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) +#define RXDAC_SET1_TYPE__TYPE u_int32_t +#define RXDAC_SET1_TYPE__READ 0x000f3f13U +#define RXDAC_SET1_TYPE__WRITE 0x000f3f13U + +#endif /* __RXDAC_SET1_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_rxdac_set1 */ +#define INST_RADIO65_REG_BLOCK__CH0_RXDAC_SET1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rxdac_set2_type */ +#ifndef __RXDAC_SET2_TYPE_MACRO__ +#define __RXDAC_SET2_TYPE_MACRO__ + +/* macros for field ate_rxdac_i_hi */ +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__SHIFT 0 +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__WIDTH 5 +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__MASK 0x0000001fU +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field ate_rxdac_q_hi */ +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__SHIFT 8 +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__WIDTH 5 +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__MASK 0x00001f00U +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) + +/* macros for field ate_rxdac_i_low */ +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__SHIFT 16 +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__WIDTH 5 +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__MASK 0x001f0000U +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) + +/* macros for field ate_rxdac_q_low */ +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__SHIFT 24 +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__WIDTH 5 +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__MASK 0x1f000000U +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f000000U) >> 24) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x1f000000U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x1f000000U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x1f000000U))) +#define RXDAC_SET2_TYPE__TYPE u_int32_t +#define RXDAC_SET2_TYPE__READ 0x1f1f1f1fU +#define RXDAC_SET2_TYPE__WRITE 0x1f1f1f1fU + +#endif /* __RXDAC_SET2_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_rxdac_set2 */ +#define INST_RADIO65_REG_BLOCK__CH0_RXDAC_SET2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rxdac_long_shift_type */ +#ifndef __RXDAC_LONG_SHIFT_TYPE_MACRO__ +#define __RXDAC_LONG_SHIFT_TYPE_MACRO__ + +/* macros for field ate_rxdac_i_static */ +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__SHIFT 0 +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__WIDTH 5 +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__MASK 0x0000001fU +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field ate_rxdac_q_static */ +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__SHIFT 8 +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__WIDTH 5 +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__MASK 0x00001f00U +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) +#define RXDAC_LONG_SHIFT_TYPE__TYPE u_int32_t +#define RXDAC_LONG_SHIFT_TYPE__READ 0x00001f1fU +#define RXDAC_LONG_SHIFT_TYPE__WRITE 0x00001f1fU + +#endif /* __RXDAC_LONG_SHIFT_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_rxdac_long_shift */ +#define INST_RADIO65_REG_BLOCK__CH0_RXDAC_LONG_SHIFT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_results_type */ +#ifndef __CMAC_RESULTS_TYPE_MACRO__ +#define __CMAC_RESULTS_TYPE_MACRO__ + +/* macros for field ate_cmac_results */ +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__SHIFT 0 +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__WIDTH 32 +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__MASK 0xffffffffU +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CMAC_RESULTS_TYPE__TYPE u_int32_t +#define CMAC_RESULTS_TYPE__READ 0xffffffffU +#define CMAC_RESULTS_TYPE__WRITE 0xffffffffU + +#endif /* __CMAC_RESULTS_TYPE_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_cmac_results_i */ +#define INST_RADIO65_REG_BLOCK__CH0_CMAC_RESULTS_I__NUM 1 + +/* macros for radio65_reg_block.ch0_cmac_results_q */ +#define INST_RADIO65_REG_BLOCK__CH0_CMAC_RESULTS_Q__NUM 1 + +/* macros for radio65_reg_block.ch1_RXRF_BIAS1 */ +#define INST_RADIO65_REG_BLOCK__CH1_RXRF_BIAS1__NUM 1 + +/* macros for radio65_reg_block.ch1_RXRF_BIAS2 */ +#define INST_RADIO65_REG_BLOCK__CH1_RXRF_BIAS2__NUM 1 + +/* macros for radio65_reg_block.ch1_RXRF_GAINSTAGES */ +#define INST_RADIO65_REG_BLOCK__CH1_RXRF_GAINSTAGES__NUM 1 + +/* macros for radio65_reg_block.ch1_RXRF_AGC */ +#define INST_RADIO65_REG_BLOCK__CH1_RXRF_AGC__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF1 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF1__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF2 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF2__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF3 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF3__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF4 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF4__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF5 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF5__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF6 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF6__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF7 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF7__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF8 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF8__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF9 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF9__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF10 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF10__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF11 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF11__NUM 1 + +/* macros for radio65_reg_block.ch1_TXRF12 */ +#define INST_RADIO65_REG_BLOCK__CH1_TXRF12__NUM 1 + +/* macros for radio65_reg_block.ch1_RXTX1 */ +#define INST_RADIO65_REG_BLOCK__CH1_RXTX1__NUM 1 + +/* macros for radio65_reg_block.ch1_RXTX2 */ +#define INST_RADIO65_REG_BLOCK__CH1_RXTX2__NUM 1 + +/* macros for radio65_reg_block.ch1_RXTX3 */ +#define INST_RADIO65_REG_BLOCK__CH1_RXTX3__NUM 1 + +/* macros for radio65_reg_block.ch1_RXTX4 */ +#define INST_RADIO65_REG_BLOCK__CH1_RXTX4__NUM 1 + +/* macros for radio65_reg_block.ch1_BB1 */ +#define INST_RADIO65_REG_BLOCK__CH1_BB1__NUM 1 + +/* macros for radio65_reg_block.ch1_BB2 */ +#define INST_RADIO65_REG_BLOCK__CH1_BB2__NUM 1 + +/* macros for radio65_reg_block.ch1_BB3 */ +#define INST_RADIO65_REG_BLOCK__CH1_BB3__NUM 1 + +/* macros for radio65_reg_block.ch1_rbist_cntrl */ +#define INST_RADIO65_REG_BLOCK__CH1_RBIST_CNTRL__NUM 1 + +/* macros for radio65_reg_block.ch1_tx_dc_offset */ +#define INST_RADIO65_REG_BLOCK__CH1_TX_DC_OFFSET__NUM 1 + +/* macros for radio65_reg_block.ch1_tx_tonegen0 */ +#define INST_RADIO65_REG_BLOCK__CH1_TX_TONEGEN0__NUM 1 + +/* macros for radio65_reg_block.ch1_tx_tonegen1 */ +#define INST_RADIO65_REG_BLOCK__CH1_TX_TONEGEN1__NUM 1 + +/* macros for radio65_reg_block.ch1_tx_lftonegen0 */ +#define INST_RADIO65_REG_BLOCK__CH1_TX_LFTONEGEN0__NUM 1 + +/* macros for radio65_reg_block.ch1_tx_linear_ramp_i */ +#define INST_RADIO65_REG_BLOCK__CH1_TX_LINEAR_RAMP_I__NUM 1 + +/* macros for radio65_reg_block.ch1_tx_linear_ramp_q */ +#define INST_RADIO65_REG_BLOCK__CH1_TX_LINEAR_RAMP_Q__NUM 1 + +/* macros for radio65_reg_block.ch1_tx_prbs_mag */ +#define INST_RADIO65_REG_BLOCK__CH1_TX_PRBS_MAG__NUM 1 + +/* macros for radio65_reg_block.ch1_tx_prbs_seed_i */ +#define INST_RADIO65_REG_BLOCK__CH1_TX_PRBS_SEED_I__NUM 1 + +/* macros for radio65_reg_block.ch1_tx_prbs_seed_q */ +#define INST_RADIO65_REG_BLOCK__CH1_TX_PRBS_SEED_Q__NUM 1 + +/* macros for radio65_reg_block.ch1_cmac_dc_cancel */ +#define INST_RADIO65_REG_BLOCK__CH1_CMAC_DC_CANCEL__NUM 1 + +/* macros for radio65_reg_block.ch1_cmac_dc_offset */ +#define INST_RADIO65_REG_BLOCK__CH1_CMAC_DC_OFFSET__NUM 1 + +/* macros for radio65_reg_block.ch1_cmac_corr */ +#define INST_RADIO65_REG_BLOCK__CH1_CMAC_CORR__NUM 1 + +/* macros for radio65_reg_block.ch1_cmac_power */ +#define INST_RADIO65_REG_BLOCK__CH1_CMAC_POWER__NUM 1 + +/* macros for radio65_reg_block.ch1_cmac_cross_corr */ +#define INST_RADIO65_REG_BLOCK__CH1_CMAC_CROSS_CORR__NUM 1 + +/* macros for radio65_reg_block.ch1_cmac_i2q2 */ +#define INST_RADIO65_REG_BLOCK__CH1_CMAC_I2Q2__NUM 1 + +/* macros for radio65_reg_block.ch1_cmac_power_hpf */ +#define INST_RADIO65_REG_BLOCK__CH1_CMAC_POWER_HPF__NUM 1 + +/* macros for radio65_reg_block.ch1_rxdac_set1 */ +#define INST_RADIO65_REG_BLOCK__CH1_RXDAC_SET1__NUM 1 + +/* macros for radio65_reg_block.ch1_rxdac_set2 */ +#define INST_RADIO65_REG_BLOCK__CH1_RXDAC_SET2__NUM 1 + +/* macros for radio65_reg_block.ch1_rxdac_long_shift */ +#define INST_RADIO65_REG_BLOCK__CH1_RXDAC_LONG_SHIFT__NUM 1 + +/* macros for radio65_reg_block.ch1_cmac_results_i */ +#define INST_RADIO65_REG_BLOCK__CH1_CMAC_RESULTS_I__NUM 1 + +/* macros for radio65_reg_block.ch1_cmac_results_q */ +#define INST_RADIO65_REG_BLOCK__CH1_CMAC_RESULTS_Q__NUM 1 + +/* macros for radio65_reg_block.ch2_RXRF_BIAS1 */ +#define INST_RADIO65_REG_BLOCK__CH2_RXRF_BIAS1__NUM 1 + +/* macros for radio65_reg_block.ch2_RXRF_BIAS2 */ +#define INST_RADIO65_REG_BLOCK__CH2_RXRF_BIAS2__NUM 1 + +/* macros for radio65_reg_block.ch2_RXRF_GAINSTAGES */ +#define INST_RADIO65_REG_BLOCK__CH2_RXRF_GAINSTAGES__NUM 1 + +/* macros for radio65_reg_block.ch2_RXRF_AGC */ +#define INST_RADIO65_REG_BLOCK__CH2_RXRF_AGC__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF1 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF1__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF2 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF2__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF3 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF3__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF4 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF4__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF5 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF5__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF6 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF6__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF7 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF7__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF8 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF8__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF9 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF9__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF10 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF10__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF11 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF11__NUM 1 + +/* macros for radio65_reg_block.ch2_TXRF12 */ +#define INST_RADIO65_REG_BLOCK__CH2_TXRF12__NUM 1 + +/* macros for radio65_reg_block.ch2_RXTX1 */ +#define INST_RADIO65_REG_BLOCK__CH2_RXTX1__NUM 1 + +/* macros for radio65_reg_block.ch2_RXTX2 */ +#define INST_RADIO65_REG_BLOCK__CH2_RXTX2__NUM 1 + +/* macros for radio65_reg_block.ch2_RXTX3 */ +#define INST_RADIO65_REG_BLOCK__CH2_RXTX3__NUM 1 + +/* macros for radio65_reg_block.ch2_RXTX4 */ +#define INST_RADIO65_REG_BLOCK__CH2_RXTX4__NUM 1 + +/* macros for radio65_reg_block.ch2_BB1 */ +#define INST_RADIO65_REG_BLOCK__CH2_BB1__NUM 1 + +/* macros for radio65_reg_block.ch2_BB2 */ +#define INST_RADIO65_REG_BLOCK__CH2_BB2__NUM 1 + +/* macros for radio65_reg_block.ch2_BB3 */ +#define INST_RADIO65_REG_BLOCK__CH2_BB3__NUM 1 + +/* macros for radio65_reg_block.ch2_rbist_cntrl */ +#define INST_RADIO65_REG_BLOCK__CH2_RBIST_CNTRL__NUM 1 + +/* macros for radio65_reg_block.ch2_tx_dc_offset */ +#define INST_RADIO65_REG_BLOCK__CH2_TX_DC_OFFSET__NUM 1 + +/* macros for radio65_reg_block.ch2_tx_tonegen0 */ +#define INST_RADIO65_REG_BLOCK__CH2_TX_TONEGEN0__NUM 1 + +/* macros for radio65_reg_block.ch2_tx_tonegen1 */ +#define INST_RADIO65_REG_BLOCK__CH2_TX_TONEGEN1__NUM 1 + +/* macros for radio65_reg_block.ch2_tx_lftonegen0 */ +#define INST_RADIO65_REG_BLOCK__CH2_TX_LFTONEGEN0__NUM 1 + +/* macros for radio65_reg_block.ch2_tx_linear_ramp_i */ +#define INST_RADIO65_REG_BLOCK__CH2_TX_LINEAR_RAMP_I__NUM 1 + +/* macros for radio65_reg_block.ch2_tx_linear_ramp_q */ +#define INST_RADIO65_REG_BLOCK__CH2_TX_LINEAR_RAMP_Q__NUM 1 + +/* macros for radio65_reg_block.ch2_tx_prbs_mag */ +#define INST_RADIO65_REG_BLOCK__CH2_TX_PRBS_MAG__NUM 1 + +/* macros for radio65_reg_block.ch2_tx_prbs_seed_i */ +#define INST_RADIO65_REG_BLOCK__CH2_TX_PRBS_SEED_I__NUM 1 + +/* macros for radio65_reg_block.ch2_tx_prbs_seed_q */ +#define INST_RADIO65_REG_BLOCK__CH2_TX_PRBS_SEED_Q__NUM 1 + +/* macros for radio65_reg_block.ch2_cmac_dc_cancel */ +#define INST_RADIO65_REG_BLOCK__CH2_CMAC_DC_CANCEL__NUM 1 + +/* macros for radio65_reg_block.ch2_cmac_dc_offset */ +#define INST_RADIO65_REG_BLOCK__CH2_CMAC_DC_OFFSET__NUM 1 + +/* macros for radio65_reg_block.ch2_cmac_corr */ +#define INST_RADIO65_REG_BLOCK__CH2_CMAC_CORR__NUM 1 + +/* macros for radio65_reg_block.ch2_cmac_power */ +#define INST_RADIO65_REG_BLOCK__CH2_CMAC_POWER__NUM 1 + +/* macros for radio65_reg_block.ch2_cmac_cross_corr */ +#define INST_RADIO65_REG_BLOCK__CH2_CMAC_CROSS_CORR__NUM 1 + +/* macros for radio65_reg_block.ch2_cmac_i2q2 */ +#define INST_RADIO65_REG_BLOCK__CH2_CMAC_I2Q2__NUM 1 + +/* macros for radio65_reg_block.ch2_cmac_power_hpf */ +#define INST_RADIO65_REG_BLOCK__CH2_CMAC_POWER_HPF__NUM 1 + +/* macros for radio65_reg_block.ch2_rxdac_set1 */ +#define INST_RADIO65_REG_BLOCK__CH2_RXDAC_SET1__NUM 1 + +/* macros for radio65_reg_block.ch2_rxdac_set2 */ +#define INST_RADIO65_REG_BLOCK__CH2_RXDAC_SET2__NUM 1 + +/* macros for radio65_reg_block.ch2_rxdac_long_shift */ +#define INST_RADIO65_REG_BLOCK__CH2_RXDAC_LONG_SHIFT__NUM 1 + +/* macros for radio65_reg_block.ch2_cmac_results_i */ +#define INST_RADIO65_REG_BLOCK__CH2_CMAC_RESULTS_I__NUM 1 + +/* macros for radio65_reg_block.ch2_cmac_results_q */ +#define INST_RADIO65_REG_BLOCK__CH2_CMAC_RESULTS_Q__NUM 1 +#define RFILE_INST_MAC_DMA_REG_BLOCK__NUM 1 +#define RFILE_INST_MAC_QCU_REG_BLOCK__NUM 1 +#define RFILE_INST_MAC_DCU_REG_BLOCK__NUM 1 +#define RFILE_INST_HOST_INTF_REG_BLOCK__NUM 1 +#define RFILE_INST_EMULATION_MISC_REG_BLOCK__NUM 1 +#define RFILE_INST_DWC_PCIE_DBI_AXI_BLOCK__NUM 1 +#define RFILE_INST_RTC_REG_BLOCK__NUM 1 +#define RFILE_INST_RTC_SYNC_REG_BLOCK__NUM 1 +#define RFILE_INST_MERLIN2_0_RADIO_REG_MAP__NUM 1 +#define RFILE_INST_ANALOG_INTF_REG_CSR_BLOCK__NUM 1 +#define RFILE_INST_MAC_PCU_REG_BLOCK__NUM 1 +#define RFILE_INST_BB_REG_BLOCK__NUM 1 +#define RFILE_INST_SVD_REG_BLOCK__NUM 1 +#define RFILE_INST_EFUSE_REG_BLOCK__NUM 1 +#define RFILE_INST_RADIO65_REG_BLOCK__NUM 1 + +#define OSPREY_REG_MAP__VERSION \ + "/cad/local/lib/perl/Pinfo.pm\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/DWC_pcie_dbi_axi_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/analog_intf_reg_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/efuse_reg_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/host_intf_reg_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/merlin2_0_radio_reg_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/osprey_pcieconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/svd_reg_sysconfig.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/emulation_misc.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/merlin2_0_radio_reg_map.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/osprey_radio_reg.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/osprey_reg.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/env/blueprint/ath_ansic.pm\n\ + /trees/yli/yli-dev/chips/osprey/2.0/ip/pcie_axi/blueprint/DWC_pcie_ep.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/rtl/amba_mac/blueprint/rtc_sync_reg.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/rtl/amba_mac/svd/blueprint/svd_reg.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/rtl/apb_analog/analog_intf_reg.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/rtl/bb/blueprint/bb_reg_map.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/rtl/host_intf/rtl/blueprint/efuse_reg.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/rtl/host_intf/rtl/blueprint/host_intf_reg.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl\n\ + /trees/yli/yli-dev/chips/osprey/2.0/rtl/rtc/blueprint/rtc_reg.rdl" +#endif /* __REG_OSPREY_REG_MAP_MACRO_H__ */ diff --git a/hal/ar9300/poseidon_reg_map_macro.h b/hal/ar9300/poseidon_reg_map_macro.h new file mode 100644 index 000000000000..2656905fb1f5 --- /dev/null +++ b/hal/ar9300/poseidon_reg_map_macro.h @@ -0,0 +1,4334 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/* */ +/* File: /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/poseidon_reg_map_macro.h*/ +/* Creator: kcwo */ +/* Time: Tuesday Nov 2, 2010 [5:38:25 pm] */ +/* */ +/* Path: /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top */ +/* Arguments: /cad/denali/blueprint/3.7.3//Linux-64bit/blueprint -codegen */ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/env/blueprint/ath_ansic.codegen*/ +/* -ath_ansic -Wdesc -I */ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top -I*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint -I */ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/env/blueprint -I*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig*/ +/* -odir */ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top */ +/* -eval {$INCLUDE_SYSCONFIG_FILES=1} -eval */ +/* $WAR_EV58615_for_ansic_codegen=1 poseidon_reg.rdl */ +/* */ +/* Sources: /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/rtc/blueprint/rtc_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/host_intf/rtl/blueprint/host_intf_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/merlin2_0_radio_reg_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/poseidon_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/efuse_reg_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/merlin2_0_radio_reg_map.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/bb/blueprint/bb_reg_map.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/apb_analog/analog_intf_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/emulation_misc.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/pcie_phy_reg_csr.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/analog_intf_reg_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/poseidon_radio_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/host_intf/rtl/blueprint/efuse_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/amba_mac/svd/blueprint/svd_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/amba_mac/blueprint/rtc_sync_reg.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/pcie_phy_reg_csr_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl*/ +/* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/env/blueprint/ath_ansic.pm*/ +/* /cad/local/lib/perl/Pinfo.pm */ +/* */ +/* Blueprint: 3.7.3 (Fri Aug 29 12:39:16 PDT 2008) */ +/* Machine: zydasc19 */ +/* OS: Linux 2.6.9-78.0.8.ELsmp */ +/* Description: */ +/* */ +/*This Register Map contains the complete register set for Poseidon. */ +/* */ +/* Copyright (C) 2010 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ +/* */ + + +#ifndef __REG_POSEIDON_REG_MAP_MACRO_H__ +#define __REG_POSEIDON_REG_MAP_MACRO_H__ + +/* macros for BlueprintGlobalNameSpace::AXI_INTERCONNECT_CTRL */ +#ifndef __AXI_INTERCONNECT_CTRL_MACRO__ +#define __AXI_INTERCONNECT_CTRL_MACRO__ + +/* macros for field FORCE_SEL_ON */ +#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__SHIFT 0 +#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__WIDTH 1 +#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__MASK 0x00000001U +#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field SELECT_SLV_PCIE */ +#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__SHIFT 1 +#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__WIDTH 1 +#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__MASK 0x00000002U +#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SW_WOW_ENABLE */ +#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__SHIFT 2 +#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__WIDTH 1 +#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__MASK 0x00000004U +#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define AXI_INTERCONNECT_CTRL__TYPE u_int32_t +#define AXI_INTERCONNECT_CTRL__READ 0x00000007U +#define AXI_INTERCONNECT_CTRL__WRITE 0x00000007U + +#endif /* __AXI_INTERCONNECT_CTRL_MACRO__ */ + + +/* macros for host_intf_reg_block.AXI_INTERCONNECT_CTRL */ +#define INST_HOST_INTF_REG_BLOCK__AXI_INTERCONNECT_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_control_1 */ +#ifndef __GREEN_TX_CONTROL_1_MACRO__ +#define __GREEN_TX_CONTROL_1_MACRO__ + +/* macros for field green_tx_enable */ +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__SHIFT 0 +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__WIDTH 1 +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MASK 0x00000001U +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field green_cases */ +#define GREEN_TX_CONTROL_1__GREEN_CASES__SHIFT 1 +#define GREEN_TX_CONTROL_1__GREEN_CASES__WIDTH 1 +#define GREEN_TX_CONTROL_1__GREEN_CASES__MASK 0x00000002U +#define GREEN_TX_CONTROL_1__GREEN_CASES__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define GREEN_TX_CONTROL_1__GREEN_CASES__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define GREEN_TX_CONTROL_1__GREEN_CASES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define GREEN_TX_CONTROL_1__GREEN_CASES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define GREEN_TX_CONTROL_1__GREEN_CASES__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define GREEN_TX_CONTROL_1__GREEN_CASES__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define GREEN_TX_CONTROL_1__TYPE u_int32_t +#define GREEN_TX_CONTROL_1__READ 0x00000003U +#define GREEN_TX_CONTROL_1__WRITE 0x00000003U + +#endif /* __GREEN_TX_CONTROL_1_MACRO__ */ + +/* macros for BlueprintGlobalNameSpace::bb_reg_page_control */ +#ifndef __BB_REG_PAGE_CONTROL_MACRO__ +#define __BB_REG_PAGE_CONTROL_MACRO__ + +/* macros for field disable_bb_reg_page */ +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__SHIFT 0 +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__WIDTH 1 +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__MASK 0x00000001U +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field bb_register_page */ +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__SHIFT 1 +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__WIDTH 3 +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__MASK 0x0000000eU +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field direct_access_page */ +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__SHIFT 4 +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__WIDTH 1 +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__MASK 0x00000010U +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) +#define BB_REG_PAGE_CONTROL__TYPE u_int32_t +#define BB_REG_PAGE_CONTROL__READ 0x0000001fU +#define BB_REG_PAGE_CONTROL__WRITE 0x0000001fU + +#endif /* __BB_REG_PAGE_CONTROL_MACRO__ */ + + +/* macros for bb_reg_block.bb_bbb_reg_map.BB_bb_reg_page_control */ +#define INST_BB_REG_BLOCK__BB_BBB_REG_MAP__BB_BB_REG_PAGE_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::peak_det_ctrl_1 */ + +/* macros for field peak_det_tally_thr_low_0 */ +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__SHIFT 8 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__WIDTH 5 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MASK 0x00001f00U +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) + +/* macros for field peak_det_tally_thr_med_0 */ +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__SHIFT 13 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__WIDTH 5 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MASK 0x0003e000U +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003e000U) >> 13) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0003e000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0003e000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0003e000U))) + +/* macros for field peak_det_tally_thr_high_0 */ +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__SHIFT 18 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__WIDTH 5 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MASK 0x007c0000U +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x007c0000U) >> 18) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x007c0000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x007c0000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x007c0000U))) + +/* macros for bb_reg_block.bb_agc_reg_map.BB_peak_det_ctrl_1 */ + + +/* macros for BlueprintGlobalNameSpace::peak_det_ctrl_2 */ + +/* macros for field rf_gain_drop_db_low_0 */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__SHIFT 10 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MASK 0x00007c00U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field rf_gain_drop_db_med_0 */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__SHIFT 15 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MASK 0x000f8000U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field rf_gain_drop_db_high_0 */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__SHIFT 20 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MASK 0x01f00000U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field rf_gain_drop_db_non_0 */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__SHIFT 25 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MASK 0x3e000000U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) + +/* macros for field enable_rfsat_restart */ +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__SHIFT 30 +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__WIDTH 1 +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MASK 0x40000000U +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define PEAK_DET_CTRL_2__TYPE u_int32_t +#define PEAK_DET_CTRL_2__READ 0x7fffffffU +#define PEAK_DET_CTRL_2__WRITE 0x7fffffffU + +/* macros for bb_reg_block.bb_agc_reg_map.BB_peak_det_ctrl_2 */ + +/* macros for BlueprintGlobalNameSpace::bt_coex_1 */ +#ifndef __BT_COEX_1_MACRO__ +#define __BT_COEX_1_MACRO__ + +/* macros for field peak_det_tally_thr_low_1 */ +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__SHIFT 0 +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__WIDTH 5 +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MASK 0x0000001fU +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field peak_det_tally_thr_med_1 */ +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__SHIFT 5 +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__WIDTH 5 +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MASK 0x000003e0U +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field peak_det_tally_thr_high_1 */ +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__SHIFT 10 +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__WIDTH 5 +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MASK 0x00007c00U +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field rf_gain_drop_db_low_1 */ +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__SHIFT 15 +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__WIDTH 5 +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MASK 0x000f8000U +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field rf_gain_drop_db_med_1 */ +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__SHIFT 20 +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__WIDTH 5 +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MASK 0x01f00000U +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field rf_gain_drop_db_high_1 */ +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__SHIFT 25 +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__WIDTH 5 +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MASK 0x3e000000U +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) + +/* macros for field bt_tx_disable_NF_cal */ +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__SHIFT 30 +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__WIDTH 1 +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MASK 0x40000000U +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define BT_COEX_1__TYPE u_int32_t +#define BT_COEX_1__READ 0x7fffffffU +#define BT_COEX_1__WRITE 0x7fffffffU + +#endif /* __BT_COEX_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_bt_coex_1 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BT_COEX_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bt_coex_2 */ +#ifndef __BT_COEX_2_MACRO__ +#define __BT_COEX_2_MACRO__ + +/* macros for field peak_det_tally_thr_low_2 */ +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__SHIFT 0 +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__WIDTH 5 +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MASK 0x0000001fU +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field peak_det_tally_thr_med_2 */ +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__SHIFT 5 +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__WIDTH 5 +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MASK 0x000003e0U +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field peak_det_tally_thr_high_2 */ +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__SHIFT 10 +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__WIDTH 5 +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MASK 0x00007c00U +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field rf_gain_drop_db_low_2 */ +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__SHIFT 15 +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__WIDTH 5 +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MASK 0x000f8000U +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field rf_gain_drop_db_med_2 */ +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__SHIFT 20 +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__WIDTH 5 +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MASK 0x01f00000U +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field rf_gain_drop_db_high_2 */ +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__SHIFT 25 +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__WIDTH 5 +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MASK 0x3e000000U +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) + +/* macros for field rfsat_rx_rx */ +#define BT_COEX_2__RFSAT_RX_RX__SHIFT 30 +#define BT_COEX_2__RFSAT_RX_RX__WIDTH 2 +#define BT_COEX_2__RFSAT_RX_RX__MASK 0xc0000000U +#define BT_COEX_2__RFSAT_RX_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define BT_COEX_2__RFSAT_RX_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define BT_COEX_2__RFSAT_RX_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define BT_COEX_2__RFSAT_RX_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define BT_COEX_2__TYPE u_int32_t +#define BT_COEX_2__READ 0xffffffffU +#define BT_COEX_2__WRITE 0xffffffffU + +#endif /* __BT_COEX_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_bt_coex_2 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BT_COEX_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bt_coex_3 */ +#ifndef __BT_COEX_3_MACRO__ +#define __BT_COEX_3_MACRO__ + +/* macros for field rfsat_bt_srch_srch */ +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__SHIFT 0 +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MASK 0x00000003U +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__READ(src) (u_int32_t)(src) & 0x00000003U +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field rfsat_bt_rx_srch */ +#define BT_COEX_3__RFSAT_BT_RX_SRCH__SHIFT 2 +#define BT_COEX_3__RFSAT_BT_RX_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_BT_RX_SRCH__MASK 0x0000000cU +#define BT_COEX_3__RFSAT_BT_RX_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define BT_COEX_3__RFSAT_BT_RX_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define BT_COEX_3__RFSAT_BT_RX_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define BT_COEX_3__RFSAT_BT_RX_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field rfsat_bt_srch_rx */ +#define BT_COEX_3__RFSAT_BT_SRCH_RX__SHIFT 4 +#define BT_COEX_3__RFSAT_BT_SRCH_RX__WIDTH 2 +#define BT_COEX_3__RFSAT_BT_SRCH_RX__MASK 0x00000030U +#define BT_COEX_3__RFSAT_BT_SRCH_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define BT_COEX_3__RFSAT_BT_SRCH_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define BT_COEX_3__RFSAT_BT_SRCH_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define BT_COEX_3__RFSAT_BT_SRCH_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field rfsat_wlan_srch_srch */ +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__SHIFT 6 +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MASK 0x000000c0U +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field rfsat_wlan_rx_srch */ +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__SHIFT 8 +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MASK 0x00000300U +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field rfsat_wlan_srch_rx */ +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__SHIFT 10 +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__WIDTH 2 +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MASK 0x00000c00U +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) + +/* macros for field rfsat_eq_srch_srch */ +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__SHIFT 12 +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MASK 0x00003000U +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003000U) >> 12) +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00003000U) +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((u_int32_t)(src) <<\ + 12) & 0x00003000U) +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00003000U))) + +/* macros for field rfsat_eq_rx_srch */ +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__SHIFT 14 +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__MASK 0x0000c000U +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field rfsat_eq_srch_rx */ +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__SHIFT 16 +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__WIDTH 2 +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__MASK 0x00030000U +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00030000U) >> 16) +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00030000U) +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((u_int32_t)(src) <<\ + 16) & 0x00030000U) +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00030000U))) + +/* macros for field rf_gain_drop_db_non_1 */ +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__SHIFT 18 +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__WIDTH 5 +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MASK 0x007c0000U +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x007c0000U) >> 18) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x007c0000U) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x007c0000U) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x007c0000U))) + +/* macros for field rf_gain_drop_db_non_2 */ +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__SHIFT 23 +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__WIDTH 5 +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MASK 0x0f800000U +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f800000U) >> 23) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x0f800000U) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x0f800000U) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x0f800000U))) + +/* macros for field bt_rx_firpwr_incr */ +#define BT_COEX_3__BT_RX_FIRPWR_INCR__SHIFT 28 +#define BT_COEX_3__BT_RX_FIRPWR_INCR__WIDTH 4 +#define BT_COEX_3__BT_RX_FIRPWR_INCR__MASK 0xf0000000U +#define BT_COEX_3__BT_RX_FIRPWR_INCR__READ(src) \ + (((u_int32_t)(src)\ + & 0xf0000000U) >> 28) +#define BT_COEX_3__BT_RX_FIRPWR_INCR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0xf0000000U) +#define BT_COEX_3__BT_RX_FIRPWR_INCR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((u_int32_t)(src) <<\ + 28) & 0xf0000000U) +#define BT_COEX_3__BT_RX_FIRPWR_INCR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0xf0000000U))) +#define BT_COEX_3__TYPE u_int32_t +#define BT_COEX_3__READ 0xffffffffU +#define BT_COEX_3__WRITE 0xffffffffU + +#endif /* __BT_COEX_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_bt_coex_3 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BT_COEX_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bt_coex_4 */ +#ifndef __BT_COEX_4_MACRO__ +#define __BT_COEX_4_MACRO__ + +/* macros for field rfgain_eqv_lna_0 */ +#define BT_COEX_4__RFGAIN_EQV_LNA_0__SHIFT 0 +#define BT_COEX_4__RFGAIN_EQV_LNA_0__WIDTH 8 +#define BT_COEX_4__RFGAIN_EQV_LNA_0__MASK 0x000000ffU +#define BT_COEX_4__RFGAIN_EQV_LNA_0__READ(src) (u_int32_t)(src) & 0x000000ffU +#define BT_COEX_4__RFGAIN_EQV_LNA_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define BT_COEX_4__RFGAIN_EQV_LNA_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define BT_COEX_4__RFGAIN_EQV_LNA_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field rfgain_eqv_lna_1 */ +#define BT_COEX_4__RFGAIN_EQV_LNA_1__SHIFT 8 +#define BT_COEX_4__RFGAIN_EQV_LNA_1__WIDTH 8 +#define BT_COEX_4__RFGAIN_EQV_LNA_1__MASK 0x0000ff00U +#define BT_COEX_4__RFGAIN_EQV_LNA_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define BT_COEX_4__RFGAIN_EQV_LNA_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define BT_COEX_4__RFGAIN_EQV_LNA_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define BT_COEX_4__RFGAIN_EQV_LNA_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field rfgain_eqv_lna_2 */ +#define BT_COEX_4__RFGAIN_EQV_LNA_2__SHIFT 16 +#define BT_COEX_4__RFGAIN_EQV_LNA_2__WIDTH 8 +#define BT_COEX_4__RFGAIN_EQV_LNA_2__MASK 0x00ff0000U +#define BT_COEX_4__RFGAIN_EQV_LNA_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define BT_COEX_4__RFGAIN_EQV_LNA_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define BT_COEX_4__RFGAIN_EQV_LNA_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define BT_COEX_4__RFGAIN_EQV_LNA_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field rfgain_eqv_lna_3 */ +#define BT_COEX_4__RFGAIN_EQV_LNA_3__SHIFT 24 +#define BT_COEX_4__RFGAIN_EQV_LNA_3__WIDTH 8 +#define BT_COEX_4__RFGAIN_EQV_LNA_3__MASK 0xff000000U +#define BT_COEX_4__RFGAIN_EQV_LNA_3__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define BT_COEX_4__RFGAIN_EQV_LNA_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define BT_COEX_4__RFGAIN_EQV_LNA_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define BT_COEX_4__RFGAIN_EQV_LNA_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define BT_COEX_4__TYPE u_int32_t +#define BT_COEX_4__READ 0xffffffffU +#define BT_COEX_4__WRITE 0xffffffffU + +#endif /* __BT_COEX_4_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_bt_coex_4 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BT_COEX_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bt_coex_5 */ +#ifndef __BT_COEX_5_MACRO__ +#define __BT_COEX_5_MACRO__ + +/* macros for field rfgain_eqv_lna_4 */ +#define BT_COEX_5__RFGAIN_EQV_LNA_4__SHIFT 0 +#define BT_COEX_5__RFGAIN_EQV_LNA_4__WIDTH 8 +#define BT_COEX_5__RFGAIN_EQV_LNA_4__MASK 0x000000ffU +#define BT_COEX_5__RFGAIN_EQV_LNA_4__READ(src) (u_int32_t)(src) & 0x000000ffU +#define BT_COEX_5__RFGAIN_EQV_LNA_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define BT_COEX_5__RFGAIN_EQV_LNA_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define BT_COEX_5__RFGAIN_EQV_LNA_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field rfgain_eqv_lna_5 */ +#define BT_COEX_5__RFGAIN_EQV_LNA_5__SHIFT 8 +#define BT_COEX_5__RFGAIN_EQV_LNA_5__WIDTH 8 +#define BT_COEX_5__RFGAIN_EQV_LNA_5__MASK 0x0000ff00U +#define BT_COEX_5__RFGAIN_EQV_LNA_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define BT_COEX_5__RFGAIN_EQV_LNA_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define BT_COEX_5__RFGAIN_EQV_LNA_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define BT_COEX_5__RFGAIN_EQV_LNA_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field rfgain_eqv_lna_6 */ +#define BT_COEX_5__RFGAIN_EQV_LNA_6__SHIFT 16 +#define BT_COEX_5__RFGAIN_EQV_LNA_6__WIDTH 8 +#define BT_COEX_5__RFGAIN_EQV_LNA_6__MASK 0x00ff0000U +#define BT_COEX_5__RFGAIN_EQV_LNA_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define BT_COEX_5__RFGAIN_EQV_LNA_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define BT_COEX_5__RFGAIN_EQV_LNA_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define BT_COEX_5__RFGAIN_EQV_LNA_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field rfgain_eqv_lna_7 */ +#define BT_COEX_5__RFGAIN_EQV_LNA_7__SHIFT 24 +#define BT_COEX_5__RFGAIN_EQV_LNA_7__WIDTH 8 +#define BT_COEX_5__RFGAIN_EQV_LNA_7__MASK 0xff000000U +#define BT_COEX_5__RFGAIN_EQV_LNA_7__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define BT_COEX_5__RFGAIN_EQV_LNA_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define BT_COEX_5__RFGAIN_EQV_LNA_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define BT_COEX_5__RFGAIN_EQV_LNA_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define BT_COEX_5__TYPE u_int32_t +#define BT_COEX_5__READ 0xffffffffU +#define BT_COEX_5__WRITE 0xffffffffU + +#endif /* __BT_COEX_5_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_bt_coex_5 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_BT_COEX_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dc_cal_status_b0 */ +#ifndef __DC_CAL_STATUS_B0_MACRO__ +#define __DC_CAL_STATUS_B0_MACRO__ + +/* macros for field offsetC1I_0 */ +#define DC_CAL_STATUS_B0__OFFSETC1I_0__SHIFT 0 +#define DC_CAL_STATUS_B0__OFFSETC1I_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC1I_0__MASK 0x0000001fU +#define DC_CAL_STATUS_B0__OFFSETC1I_0__READ(src) (u_int32_t)(src) & 0x0000001fU + +/* macros for field offsetC1Q_0 */ +#define DC_CAL_STATUS_B0__OFFSETC1Q_0__SHIFT 5 +#define DC_CAL_STATUS_B0__OFFSETC1Q_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC1Q_0__MASK 0x000003e0U +#define DC_CAL_STATUS_B0__OFFSETC1Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) + +/* macros for field offsetC2I_0 */ +#define DC_CAL_STATUS_B0__OFFSETC2I_0__SHIFT 10 +#define DC_CAL_STATUS_B0__OFFSETC2I_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC2I_0__MASK 0x00007c00U +#define DC_CAL_STATUS_B0__OFFSETC2I_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) + +/* macros for field offsetC2Q_0 */ +#define DC_CAL_STATUS_B0__OFFSETC2Q_0__SHIFT 15 +#define DC_CAL_STATUS_B0__OFFSETC2Q_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC2Q_0__MASK 0x000f8000U +#define DC_CAL_STATUS_B0__OFFSETC2Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) + +/* macros for field offsetC3I_0 */ +#define DC_CAL_STATUS_B0__OFFSETC3I_0__SHIFT 20 +#define DC_CAL_STATUS_B0__OFFSETC3I_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC3I_0__MASK 0x01f00000U +#define DC_CAL_STATUS_B0__OFFSETC3I_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) + +/* macros for field offsetC3Q_0 */ +#define DC_CAL_STATUS_B0__OFFSETC3Q_0__SHIFT 25 +#define DC_CAL_STATUS_B0__OFFSETC3Q_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC3Q_0__MASK 0x3e000000U +#define DC_CAL_STATUS_B0__OFFSETC3Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define DC_CAL_STATUS_B0__TYPE u_int32_t +#define DC_CAL_STATUS_B0__READ 0x3fffffffU + +#endif /* __DC_CAL_STATUS_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_agc_reg_map.BB_dc_cal_status_b0 */ +#define INST_BB_REG_BLOCK__BB_AGC_REG_MAP__BB_DC_CAL_STATUS_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_sig_detect */ + +/* macros for field bbb_mrc_off_no_swap */ +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__SHIFT 23 +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__WIDTH 1 +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MASK 0x00800000U +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +#define BBB_SIG_DETECT__TYPE u_int32_t +#define BBB_SIG_DETECT__READ 0x80ffffffU +#define BBB_SIG_DETECT__WRITE 0x80ffffffU + +/* macros for BlueprintGlobalNameSpace::gen_controls */ + +/* macros for field enable_dac_async_fifo */ +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__SHIFT 11 +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__WIDTH 1 +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MASK 0x00000800U +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + + +/* macros for field static20_mode_ht40_packet_handling */ +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__SHIFT 15 +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__WIDTH 1 +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MASK 0x00008000U +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field static20_mode_ht40_packet_error_rpt */ +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__SHIFT 16 +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__WIDTH 1 +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MASK 0x00010000U +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field unsupp_ht_rate_threshold */ +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__SHIFT 18 +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__WIDTH 7 +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MASK 0x01fc0000U +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fc0000U) >> 18) +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x01fc0000U) +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x01fc0000U) +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x01fc0000U))) +#define GEN_CONTROLS__TYPE u_int32_t +#define GEN_CONTROLS__READ 0x01fdffffU +#define GEN_CONTROLS__WRITE 0x01fdffffU + +/* macros for bb_reg_block.bb_sm_reg_map.BB_gen_controls */ + +/* macros for BlueprintGlobalNameSpace::bb_reg_page_control */ +#ifndef __BB_REG_PAGE_CONTROL_MACRO__ +#define __BB_REG_PAGE_CONTROL_MACRO__ + +/* macros for field disable_bb_reg_page */ +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__SHIFT 0 +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__WIDTH 1 +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__MASK 0x00000001U +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BB_REG_PAGE_CONTROL__DISABLE_BB_REG_PAGE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field bb_register_page */ +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__SHIFT 1 +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__WIDTH 3 +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__MASK 0x0000000eU +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define BB_REG_PAGE_CONTROL__BB_REGISTER_PAGE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field direct_access_page */ +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__SHIFT 4 +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__WIDTH 1 +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__MASK 0x00000010U +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define BB_REG_PAGE_CONTROL__DIRECT_ACCESS_PAGE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) +#define BB_REG_PAGE_CONTROL__TYPE u_int32_t +#define BB_REG_PAGE_CONTROL__READ 0x0000001fU +#define BB_REG_PAGE_CONTROL__WRITE 0x0000001fU + +#endif /* __BB_REG_PAGE_CONTROL_MACRO__ */ + + +/* macros for bb_reg_block.bb_bbb_reg_map.BB_bb_reg_page_control */ +#define INST_BB_REG_BLOCK__BB_BBB_REG_MAP__BB_BB_REG_PAGE_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spectral_scan */ + + +/* macros for field spectral_scan_compressed_rpt */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__SHIFT 31 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MASK 0x80000000U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SPECTRAL_SCAN__TYPE u_int32_t +#define SPECTRAL_SCAN__READ 0xffffffffU +#define SPECTRAL_SCAN__WRITE 0xffffffffU + +/* macros for bb_reg_block.bb_sm_reg_map.BB_spectral_scan */ + +/* macros for BlueprintGlobalNameSpace::search_start_delay */ + + +/* macros for field rx_sounding_enable */ +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__SHIFT 14 +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__WIDTH 1 +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MASK 0x00004000U +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field rm_hcsd4svd */ +#define SEARCH_START_DELAY__RM_HCSD4SVD__SHIFT 15 +#define SEARCH_START_DELAY__RM_HCSD4SVD__WIDTH 1 +#define SEARCH_START_DELAY__RM_HCSD4SVD__MASK 0x00008000U +#define SEARCH_START_DELAY__RM_HCSD4SVD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define SEARCH_START_DELAY__RM_HCSD4SVD__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define SEARCH_START_DELAY__RM_HCSD4SVD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define SEARCH_START_DELAY__RM_HCSD4SVD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define SEARCH_START_DELAY__RM_HCSD4SVD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define SEARCH_START_DELAY__RM_HCSD4SVD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) +#define SEARCH_START_DELAY__TYPE u_int32_t +#define SEARCH_START_DELAY__READ 0x0000ffffU +#define SEARCH_START_DELAY__WRITE 0x0000ffffU + +/* macros for bb_reg_block.bb_sm_reg_map.BB_search_start_delay */ + +/* macros for BlueprintGlobalNameSpace::frame_control */ + +/* macros for field en_err_static20_mode_ht40_packet */ +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__SHIFT 19 +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MASK 0x00080000U +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for bb_reg_block.bb_sm_reg_map.BB_frame_control */ + +/* macros for BlueprintGlobalNameSpace::switch_table_com1 */ + +/* macros for field switch_table_com_spdt */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__SHIFT 20 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__MASK 0x00f00000U +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_SPDT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) +#define SWITCH_TABLE_COM1__TYPE u_int32_t +#define SWITCH_TABLE_COM1__READ 0x00ffffffU +#define SWITCH_TABLE_COM1__WRITE 0x00ffffffU + +/* macros for bb_reg_block.bb_sm_reg_map.BB_switch_table_com1 */ + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_rate12 */ + +/* macros for field use_per_packet_olpc_gain_delta_adj */ +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__SHIFT 7 +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__WIDTH 1 +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MASK 0x00000080U +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) +#define POWERTX_MAX__TYPE u_int32_t +#define POWERTX_MAX__READ 0x000000c0U +#define POWERTX_MAX__WRITE 0x000000c0U + +/* macros for bb_reg_block.bb_sm_reg_map.BB_powertx_max */ + +/* macros for BlueprintGlobalNameSpace::tx_forced_gain */ + + +/* macros for field forced_ob2G */ +#define TX_FORCED_GAIN__FORCED_OB2G__SHIFT 25 +#define TX_FORCED_GAIN__FORCED_OB2G__WIDTH 3 +#define TX_FORCED_GAIN__FORCED_OB2G__MASK 0x0e000000U +#define TX_FORCED_GAIN__FORCED_OB2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x0e000000U) >> 25) +#define TX_FORCED_GAIN__FORCED_OB2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x0e000000U) +#define TX_FORCED_GAIN__FORCED_OB2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x0e000000U) +#define TX_FORCED_GAIN__FORCED_OB2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x0e000000U))) + +/* macros for field forced_db2G */ +#define TX_FORCED_GAIN__FORCED_DB2G__SHIFT 28 +#define TX_FORCED_GAIN__FORCED_DB2G__WIDTH 3 +#define TX_FORCED_GAIN__FORCED_DB2G__MASK 0x70000000U +#define TX_FORCED_GAIN__FORCED_DB2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x70000000U) >> 28) +#define TX_FORCED_GAIN__FORCED_DB2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x70000000U) +#define TX_FORCED_GAIN__FORCED_DB2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x70000000U) | (((u_int32_t)(src) <<\ + 28) & 0x70000000U) +#define TX_FORCED_GAIN__FORCED_DB2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x70000000U))) + +/* macros for field forced_green_paprd_enable */ +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__SHIFT 31 +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__WIDTH 1 +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MASK 0x80000000U +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TX_FORCED_GAIN__TYPE u_int32_t +#define TX_FORCED_GAIN__READ 0xffffffffU +#define TX_FORCED_GAIN__WRITE 0xffffffffU + +/* macros for bb_reg_block.bb_sm_reg_map.BB_tx_forced_gain */ + +/* macros for BlueprintGlobalNameSpace::txiqcal_control_0 */ + + +/* macros for field enable_txiq_calibrate */ +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SHIFT 31 +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WIDTH 1 +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MASK 0x80000000U +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TXIQCAL_CONTROL_0__TYPE u_int32_t +#define TXIQCAL_CONTROL_0__READ 0xffffffffU +#define TXIQCAL_CONTROL_0__WRITE 0xffffffffU + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiqcal_control_0 */ + +/* macros for BlueprintGlobalNameSpace::txiqcal_control_0 */ + +/* macros for field enable_txiq_calibrate */ +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SHIFT 31 +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WIDTH 1 +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MASK 0x80000000U +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TXIQCAL_CONTROL_0__TYPE u_int32_t +#define TXIQCAL_CONTROL_0__READ 0xffffffffU +#define TXIQCAL_CONTROL_0__WRITE 0xffffffffU + +/* macros for bb_reg_block.bb_sm_reg_map.BB_txiqcal_control_0 */ + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_1_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_0_1_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_0_1_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_0_1_b0 */ +#define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_1_B0__PAPRD_PRE_POST_SCALING_0_1_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_0_1_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_0_1_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_1_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_0_1_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_0_1_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_1_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_1_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_1_1_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_1_1_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_1_1_b0 */ +#define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_1_B0__PAPRD_PRE_POST_SCALING_1_1_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_1_1_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_1_1_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_1_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_1_1_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_1_1_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_1_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_1_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_2_1_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_2_1_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_2_1_b0 */ +#define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_1_B0__PAPRD_PRE_POST_SCALING_2_1_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_2_1_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_2_1_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_1_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_2_1_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_2_1_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_1_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_1_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_3_1_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_3_1_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_3_1_b0 */ +#define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_1_B0__PAPRD_PRE_POST_SCALING_3_1_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_3_1_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_3_1_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_1_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_3_1_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_3_1_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_1_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_1_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_4_1_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_4_1_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_4_1_b0 */ +#define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_1_B0__PAPRD_PRE_POST_SCALING_4_1_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_4_1_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_4_1_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_1_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_4_1_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_4_1_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_1_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_1_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_5_1_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_5_1_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_5_1_b0 */ +#define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_1_B0__PAPRD_PRE_POST_SCALING_5_1_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_5_1_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_5_1_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_1_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_5_1_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_5_1_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_1_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_1_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_6_1_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_6_1_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_6_1_b0 */ +#define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_1_B0__PAPRD_PRE_POST_SCALING_6_1_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_6_1_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_6_1_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_1_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_6_1_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_6_1_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_1_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_1_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_7_1_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_7_1_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_7_1_b0 */ +#define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_1_B0__PAPRD_PRE_POST_SCALING_7_1_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_7_1_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_7_1_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_1_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_7_1_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_7_1_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_1_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_2_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_0_2_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_0_2_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_0_2_b0 */ +#define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_2_B0__PAPRD_PRE_POST_SCALING_0_2_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_0_2_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_0_2_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_2_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_0_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_0_2_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_2_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_2_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_1_2_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_1_2_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_1_2_b0 */ +#define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_2_B0__PAPRD_PRE_POST_SCALING_1_2_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_1_2_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_1_2_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_2_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_1_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_1_2_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_2_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_2_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_2_2_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_2_2_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_2_2_b0 */ +#define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_2_B0__PAPRD_PRE_POST_SCALING_2_2_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_2_2_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_2_2_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_2_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_2_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_2_2_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_2_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_2_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_3_2_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_3_2_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_3_2_b0 */ +#define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_2_B0__PAPRD_PRE_POST_SCALING_3_2_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_3_2_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_3_2_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_2_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_3_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_3_2_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_2_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_2_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_4_2_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_4_2_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_4_2_b0 */ +#define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_2_B0__PAPRD_PRE_POST_SCALING_4_2_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_4_2_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_4_2_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_2_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_4_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_4_2_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_2_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_2_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_5_2_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_5_2_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_5_2_b0 */ +#define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_2_B0__PAPRD_PRE_POST_SCALING_5_2_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_5_2_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_5_2_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_2_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_5_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_5_2_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_2_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_2_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_6_2_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_6_2_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_6_2_b0 */ +#define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_2_B0__PAPRD_PRE_POST_SCALING_6_2_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_6_2_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_6_2_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_2_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_6_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_6_2_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_2_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_2_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_7_2_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_7_2_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_7_2_b0 */ +#define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_2_B0__PAPRD_PRE_POST_SCALING_7_2_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_7_2_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_7_2_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_2_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_7_2_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_7_2_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_2_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_3_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_0_3_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_0_3_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_0_3_b0 */ +#define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_3_B0__PAPRD_PRE_POST_SCALING_0_3_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_0_3_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_0_3_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_3_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_0_3_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_0_3_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_3_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_3_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_1_3_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_1_3_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_1_3_b0 */ +#define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_3_B0__PAPRD_PRE_POST_SCALING_1_3_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_1_3_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_1_3_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_3_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_1_3_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_1_3_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_3_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_3_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_2_3_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_2_3_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_2_3_b0 */ +#define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_3_B0__PAPRD_PRE_POST_SCALING_2_3_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_2_3_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_2_3_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_3_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_2_3_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_2_3_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_3_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_3_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_3_3_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_3_3_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_3_3_b0 */ +#define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_3_B0__PAPRD_PRE_POST_SCALING_3_3_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_3_3_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_3_3_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_3_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_3_3_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_3_3_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_3_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_3_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_4_3_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_4_3_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_4_3_b0 */ +#define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_3_B0__PAPRD_PRE_POST_SCALING_4_3_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_4_3_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_4_3_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_3_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_4_3_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_4_3_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_3_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_3_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_5_3_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_5_3_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_5_3_b0 */ +#define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_3_B0__PAPRD_PRE_POST_SCALING_5_3_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_5_3_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_5_3_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_3_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_5_3_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_5_3_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_3_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_3_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_6_3_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_6_3_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_6_3_b0 */ +#define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_3_B0__PAPRD_PRE_POST_SCALING_6_3_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_6_3_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_6_3_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_3_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_6_3_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_6_3_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_3_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_3_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_7_3_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_7_3_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_7_3_b0 */ +#define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_3_B0__PAPRD_PRE_POST_SCALING_7_3_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_7_3_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_7_3_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_3_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_7_3_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_7_3_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_3_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_4_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_0_4_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_0_4_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_0_4_b0 */ +#define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_4_B0__PAPRD_PRE_POST_SCALING_0_4_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_0_4_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_0_4_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_4_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_0_4_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_0_4_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_4_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_4_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_1_4_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_1_4_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_1_4_b0 */ +#define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_4_B0__PAPRD_PRE_POST_SCALING_1_4_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_1_4_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_1_4_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_4_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_1_4_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_1_4_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_4_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_4_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_2_4_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_2_4_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_2_4_b0 */ +#define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_4_B0__PAPRD_PRE_POST_SCALING_2_4_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_2_4_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_2_4_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_4_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_2_4_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_2_4_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_4_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_4_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_3_4_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_3_4_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_3_4_b0 */ +#define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_4_B0__PAPRD_PRE_POST_SCALING_3_4_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_3_4_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_3_4_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_4_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_3_4_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_3_4_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_4_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_4_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_4_4_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_4_4_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_4_4_b0 */ +#define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_4_B0__PAPRD_PRE_POST_SCALING_4_4_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_4_4_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_4_4_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_4_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_4_4_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_4_4_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_4_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_4_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_5_4_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_5_4_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_5_4_b0 */ +#define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_4_B0__PAPRD_PRE_POST_SCALING_5_4_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_5_4_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_5_4_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_4_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_5_4_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_5_4_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_4_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_4_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_6_4_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_6_4_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_6_4_b0 */ +#define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_4_B0__PAPRD_PRE_POST_SCALING_6_4_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_6_4_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_6_4_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_4_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_6_4_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_6_4_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_4_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_4_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_7_4_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_7_4_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_7_4_b0 */ +#define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__MASK \ + 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_4_B0__PAPRD_PRE_POST_SCALING_7_4_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_7_4_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_7_4_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_4_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_7_4_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_pre_post_scale_7_4_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_4_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_power_at_am2am_cal_b0 */ +#ifndef __PAPRD_POWER_AT_AM2AM_CAL_B0_MACRO__ +#define __PAPRD_POWER_AT_AM2AM_CAL_B0_MACRO__ + +/* macros for field paprd_power_at_am2am_cal_1_b0 */ +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__SHIFT 0 +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__WIDTH 6 +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__MASK \ + 0x0000003fU +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_1_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field paprd_power_at_am2am_cal_2_b0 */ +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__SHIFT 6 +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__WIDTH 6 +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__MASK \ + 0x00000fc0U +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_2_B0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field paprd_power_at_am2am_cal_3_b0 */ +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__SHIFT 12 +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__WIDTH 6 +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__MASK \ + 0x0003f000U +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_3_B0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field paprd_power_at_am2am_cal_4_b0 */ +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__SHIFT 18 +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__WIDTH 6 +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__MASK \ + 0x00fc0000U +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__PAPRD_POWER_AT_AM2AM_CAL_4_B0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) +#define PAPRD_POWER_AT_AM2AM_CAL_B0__TYPE u_int32_t +#define PAPRD_POWER_AT_AM2AM_CAL_B0__READ 0x00ffffffU +#define PAPRD_POWER_AT_AM2AM_CAL_B0__WRITE 0x00ffffffU + +#endif /* __PAPRD_POWER_AT_AM2AM_CAL_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_power_at_am2am_cal_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_POWER_AT_AM2AM_CAL_B0__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::paprd_valid_obdb_b0 */ +#ifndef __PAPRD_VALID_OBDB_B0_MACRO__ +#define __PAPRD_VALID_OBDB_B0_MACRO__ + +/* macros for field paprd_valid_obdb_0_b0 */ +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__SHIFT 0 +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__WIDTH 6 +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__MASK 0x0000003fU +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_0_B0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field paprd_valid_obdb_1_b0 */ +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__SHIFT 6 +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__WIDTH 6 +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__MASK 0x00000fc0U +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_1_B0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field paprd_valid_obdb_2_b0 */ +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__SHIFT 12 +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__WIDTH 6 +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__MASK 0x0003f000U +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_2_B0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field paprd_valid_obdb_3_b0 */ +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__SHIFT 18 +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__WIDTH 6 +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__MASK 0x00fc0000U +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_3_B0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field paprd_valid_obdb_4_b0 */ +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__SHIFT 24 +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__WIDTH 6 +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__MASK 0x3f000000U +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define PAPRD_VALID_OBDB_B0__PAPRD_VALID_OBDB_4_B0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define PAPRD_VALID_OBDB_B0__TYPE u_int32_t +#define PAPRD_VALID_OBDB_B0__READ 0x3fffffffU +#define PAPRD_VALID_OBDB_B0__WRITE 0x3fffffffU + +#endif /* __PAPRD_VALID_OBDB_B0_MACRO__ */ + + +/* macros for bb_reg_block.bb_chn_ext_reg_map.BB_paprd_valid_obdb_b0 */ +#define INST_BB_REG_BLOCK__BB_CHN_EXT_REG_MAP__BB_PAPRD_VALID_OBDB_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_1 */ +#ifndef __GREEN_TX_GAIN_TAB_1_MACRO__ +#define __GREEN_TX_GAIN_TAB_1_MACRO__ + +/* macros for field green_tg_table1 */ +#define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__SHIFT 0 +#define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__WIDTH 7 +#define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_1__GREEN_TG_TABLE1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_1__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_1__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_1__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_1_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_1 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_2 */ +#ifndef __GREEN_TX_GAIN_TAB_2_MACRO__ +#define __GREEN_TX_GAIN_TAB_2_MACRO__ + +/* macros for field green_tg_table2 */ +#define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__SHIFT 0 +#define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__WIDTH 7 +#define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_2__GREEN_TG_TABLE2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_2__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_2__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_2__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_2_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_2 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_3 */ +#ifndef __GREEN_TX_GAIN_TAB_3_MACRO__ +#define __GREEN_TX_GAIN_TAB_3_MACRO__ + +/* macros for field green_tg_table3 */ +#define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__SHIFT 0 +#define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__WIDTH 7 +#define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_3__GREEN_TG_TABLE3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_3__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_3__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_3__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_3_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_3 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_4 */ +#ifndef __GREEN_TX_GAIN_TAB_4_MACRO__ +#define __GREEN_TX_GAIN_TAB_4_MACRO__ + +/* macros for field green_tg_table4 */ +#define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__SHIFT 0 +#define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__WIDTH 7 +#define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_4__GREEN_TG_TABLE4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_4__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_4__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_4__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_4_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_4 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_5 */ +#ifndef __GREEN_TX_GAIN_TAB_5_MACRO__ +#define __GREEN_TX_GAIN_TAB_5_MACRO__ + +/* macros for field green_tg_table5 */ +#define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__SHIFT 0 +#define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__WIDTH 7 +#define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_5__GREEN_TG_TABLE5__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_5__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_5__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_5__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_5_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_5 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_6 */ +#ifndef __GREEN_TX_GAIN_TAB_6_MACRO__ +#define __GREEN_TX_GAIN_TAB_6_MACRO__ + +/* macros for field green_tg_table6 */ +#define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__SHIFT 0 +#define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__WIDTH 7 +#define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_6__GREEN_TG_TABLE6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_6__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_6__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_6__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_6_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_6 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_7 */ +#ifndef __GREEN_TX_GAIN_TAB_7_MACRO__ +#define __GREEN_TX_GAIN_TAB_7_MACRO__ + +/* macros for field green_tg_table7 */ +#define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__SHIFT 0 +#define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__WIDTH 7 +#define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_7__GREEN_TG_TABLE7__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_7__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_7__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_7__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_7_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_7 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_8 */ +#ifndef __GREEN_TX_GAIN_TAB_8_MACRO__ +#define __GREEN_TX_GAIN_TAB_8_MACRO__ + +/* macros for field green_tg_table8 */ +#define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__SHIFT 0 +#define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__WIDTH 7 +#define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_8__GREEN_TG_TABLE8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_8__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_8__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_8__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_8_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_8 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_9 */ +#ifndef __GREEN_TX_GAIN_TAB_9_MACRO__ +#define __GREEN_TX_GAIN_TAB_9_MACRO__ + +/* macros for field green_tg_table9 */ +#define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__SHIFT 0 +#define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__WIDTH 7 +#define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_9__GREEN_TG_TABLE9__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_9__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_9__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_9__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_9_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_9 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_10 */ +#ifndef __GREEN_TX_GAIN_TAB_10_MACRO__ +#define __GREEN_TX_GAIN_TAB_10_MACRO__ + +/* macros for field green_tg_table10 */ +#define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__SHIFT 0 +#define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__WIDTH 7 +#define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_10__GREEN_TG_TABLE10__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_10__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_10__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_10__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_10_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_10 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_11 */ +#ifndef __GREEN_TX_GAIN_TAB_11_MACRO__ +#define __GREEN_TX_GAIN_TAB_11_MACRO__ + +/* macros for field green_tg_table11 */ +#define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__SHIFT 0 +#define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__WIDTH 7 +#define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_11__GREEN_TG_TABLE11__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_11__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_11__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_11__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_11_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_11 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_12 */ +#ifndef __GREEN_TX_GAIN_TAB_12_MACRO__ +#define __GREEN_TX_GAIN_TAB_12_MACRO__ + +/* macros for field green_tg_table12 */ +#define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__SHIFT 0 +#define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__WIDTH 7 +#define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_12__GREEN_TG_TABLE12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_12__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_12__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_12__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_12_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_12 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_13 */ +#ifndef __GREEN_TX_GAIN_TAB_13_MACRO__ +#define __GREEN_TX_GAIN_TAB_13_MACRO__ + +/* macros for field green_tg_table13 */ +#define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__SHIFT 0 +#define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__WIDTH 7 +#define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_13__GREEN_TG_TABLE13__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_13__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_13__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_13__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_13_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_13 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_13__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_14 */ +#ifndef __GREEN_TX_GAIN_TAB_14_MACRO__ +#define __GREEN_TX_GAIN_TAB_14_MACRO__ + +/* macros for field green_tg_table14 */ +#define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__SHIFT 0 +#define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__WIDTH 7 +#define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_14__GREEN_TG_TABLE14__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_14__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_14__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_14__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_14_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_14 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_14__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_15 */ +#ifndef __GREEN_TX_GAIN_TAB_15_MACRO__ +#define __GREEN_TX_GAIN_TAB_15_MACRO__ + +/* macros for field green_tg_table15 */ +#define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__SHIFT 0 +#define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__WIDTH 7 +#define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_15__GREEN_TG_TABLE15__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_15__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_15__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_15__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_15_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_15 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_15__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_16 */ +#ifndef __GREEN_TX_GAIN_TAB_16_MACRO__ +#define __GREEN_TX_GAIN_TAB_16_MACRO__ + +/* macros for field green_tg_table16 */ +#define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__SHIFT 0 +#define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__WIDTH 7 +#define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_16__GREEN_TG_TABLE16__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_16__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_16__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_16__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_16_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_16 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_17 */ +#ifndef __GREEN_TX_GAIN_TAB_17_MACRO__ +#define __GREEN_TX_GAIN_TAB_17_MACRO__ + +/* macros for field green_tg_table17 */ +#define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__SHIFT 0 +#define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__WIDTH 7 +#define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_17__GREEN_TG_TABLE17__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_17__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_17__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_17__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_17_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_17 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_17__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_18 */ +#ifndef __GREEN_TX_GAIN_TAB_18_MACRO__ +#define __GREEN_TX_GAIN_TAB_18_MACRO__ + +/* macros for field green_tg_table18 */ +#define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__SHIFT 0 +#define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__WIDTH 7 +#define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_18__GREEN_TG_TABLE18__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_18__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_18__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_18__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_18_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_18 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_18__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_19 */ +#ifndef __GREEN_TX_GAIN_TAB_19_MACRO__ +#define __GREEN_TX_GAIN_TAB_19_MACRO__ + +/* macros for field green_tg_table19 */ +#define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__SHIFT 0 +#define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__WIDTH 7 +#define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_19__GREEN_TG_TABLE19__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_19__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_19__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_19__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_19_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_19 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_19__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_20 */ +#ifndef __GREEN_TX_GAIN_TAB_20_MACRO__ +#define __GREEN_TX_GAIN_TAB_20_MACRO__ + +/* macros for field green_tg_table20 */ +#define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__SHIFT 0 +#define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__WIDTH 7 +#define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_20__GREEN_TG_TABLE20__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_20__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_20__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_20__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_20_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_20 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_21 */ +#ifndef __GREEN_TX_GAIN_TAB_21_MACRO__ +#define __GREEN_TX_GAIN_TAB_21_MACRO__ + +/* macros for field green_tg_table21 */ +#define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__SHIFT 0 +#define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__WIDTH 7 +#define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_21__GREEN_TG_TABLE21__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_21__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_21__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_21__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_21_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_21 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_21__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_22 */ +#ifndef __GREEN_TX_GAIN_TAB_22_MACRO__ +#define __GREEN_TX_GAIN_TAB_22_MACRO__ + +/* macros for field green_tg_table22 */ +#define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__SHIFT 0 +#define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__WIDTH 7 +#define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_22__GREEN_TG_TABLE22__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_22__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_22__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_22__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_22_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_22 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_22__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_23 */ +#ifndef __GREEN_TX_GAIN_TAB_23_MACRO__ +#define __GREEN_TX_GAIN_TAB_23_MACRO__ + +/* macros for field green_tg_table23 */ +#define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__SHIFT 0 +#define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__WIDTH 7 +#define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_23__GREEN_TG_TABLE23__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_23__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_23__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_23__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_23_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_23 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_23__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_24 */ +#ifndef __GREEN_TX_GAIN_TAB_24_MACRO__ +#define __GREEN_TX_GAIN_TAB_24_MACRO__ + +/* macros for field green_tg_table24 */ +#define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__SHIFT 0 +#define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__WIDTH 7 +#define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_24__GREEN_TG_TABLE24__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_24__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_24__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_24__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_24_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_24 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_24__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_25 */ +#ifndef __GREEN_TX_GAIN_TAB_25_MACRO__ +#define __GREEN_TX_GAIN_TAB_25_MACRO__ + +/* macros for field green_tg_table25 */ +#define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__SHIFT 0 +#define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__WIDTH 7 +#define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_25__GREEN_TG_TABLE25__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_25__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_25__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_25__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_25_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_25 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_25__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_26 */ +#ifndef __GREEN_TX_GAIN_TAB_26_MACRO__ +#define __GREEN_TX_GAIN_TAB_26_MACRO__ + +/* macros for field green_tg_table26 */ +#define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__SHIFT 0 +#define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__WIDTH 7 +#define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_26__GREEN_TG_TABLE26__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_26__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_26__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_26__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_26_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_26 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_26__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_27 */ +#ifndef __GREEN_TX_GAIN_TAB_27_MACRO__ +#define __GREEN_TX_GAIN_TAB_27_MACRO__ + +/* macros for field green_tg_table27 */ +#define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__SHIFT 0 +#define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__WIDTH 7 +#define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_27__GREEN_TG_TABLE27__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_27__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_27__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_27__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_27_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_27 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_27__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_28 */ +#ifndef __GREEN_TX_GAIN_TAB_28_MACRO__ +#define __GREEN_TX_GAIN_TAB_28_MACRO__ + +/* macros for field green_tg_table28 */ +#define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__SHIFT 0 +#define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__WIDTH 7 +#define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_28__GREEN_TG_TABLE28__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_28__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_28__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_28__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_28_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_28 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_28__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_29 */ +#ifndef __GREEN_TX_GAIN_TAB_29_MACRO__ +#define __GREEN_TX_GAIN_TAB_29_MACRO__ + +/* macros for field green_tg_table29 */ +#define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__SHIFT 0 +#define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__WIDTH 7 +#define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_29__GREEN_TG_TABLE29__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_29__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_29__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_29__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_29_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_29 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_29__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_30 */ +#ifndef __GREEN_TX_GAIN_TAB_30_MACRO__ +#define __GREEN_TX_GAIN_TAB_30_MACRO__ + +/* macros for field green_tg_table30 */ +#define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__SHIFT 0 +#define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__WIDTH 7 +#define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_30__GREEN_TG_TABLE30__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_30__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_30__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_30__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_30_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_30 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_30__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_31 */ +#ifndef __GREEN_TX_GAIN_TAB_31_MACRO__ +#define __GREEN_TX_GAIN_TAB_31_MACRO__ + +/* macros for field green_tg_table31 */ +#define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__SHIFT 0 +#define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__WIDTH 7 +#define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_31__GREEN_TG_TABLE31__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_31__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_31__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_31__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_31_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_31 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_31__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_gain_tab_32 */ +#ifndef __GREEN_TX_GAIN_TAB_32_MACRO__ +#define __GREEN_TX_GAIN_TAB_32_MACRO__ + +/* macros for field green_tg_table32 */ +#define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__SHIFT 0 +#define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__WIDTH 7 +#define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__MASK 0x0000007fU +#define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GREEN_TX_GAIN_TAB_32__GREEN_TG_TABLE32__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define GREEN_TX_GAIN_TAB_32__TYPE u_int32_t +#define GREEN_TX_GAIN_TAB_32__READ 0x0000007fU +#define GREEN_TX_GAIN_TAB_32__WRITE 0x0000007fU + +#endif /* __GREEN_TX_GAIN_TAB_32_MACRO__ */ + + +/* macros for bb_reg_block.bb_sm_ext_reg_map.BB_green_tx_gain_tab_32 */ +#define INST_BB_REG_BLOCK__BB_SM_EXT_REG_MAP__BB_GREEN_TX_GAIN_TAB_32__NUM 1 + + +/* macros for BlueprintGlobalNameSpace::PMU1 */ +#ifndef __PMU1_MACRO__ +#define __PMU1_MACRO__ + +/* macros for field pwd */ +#define PMU1__PWD__SHIFT 0 +#define PMU1__PWD__WIDTH 3 +#define PMU1__PWD__MASK 0x00000007U +#define PMU1__PWD__READ(src) (u_int32_t)(src) & 0x00000007U +#define PMU1__PWD__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define PMU1__PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define PMU1__PWD__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) + +/* macros for field Nfdiv */ +#define PMU1__NFDIV__SHIFT 3 +#define PMU1__NFDIV__WIDTH 1 +#define PMU1__NFDIV__MASK 0x00000008U +#define PMU1__NFDIV__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define PMU1__NFDIV__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define PMU1__NFDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define PMU1__NFDIV__VERIFY(src) (!((((u_int32_t)(src) << 3) & ~0x00000008U))) +#define PMU1__NFDIV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define PMU1__NFDIV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field Refv */ +#define PMU1__REFV__SHIFT 4 +#define PMU1__REFV__WIDTH 4 +#define PMU1__REFV__MASK 0x000000f0U +#define PMU1__REFV__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) +#define PMU1__REFV__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) +#define PMU1__REFV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define PMU1__REFV__VERIFY(src) (!((((u_int32_t)(src) << 4) & ~0x000000f0U))) + +/* macros for field Gm1 */ +#define PMU1__GM1__SHIFT 8 +#define PMU1__GM1__WIDTH 3 +#define PMU1__GM1__MASK 0x00000700U +#define PMU1__GM1__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) +#define PMU1__GM1__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U) +#define PMU1__GM1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define PMU1__GM1__VERIFY(src) (!((((u_int32_t)(src) << 8) & ~0x00000700U))) + +/* macros for field Classb */ +#define PMU1__CLASSB__SHIFT 11 +#define PMU1__CLASSB__WIDTH 3 +#define PMU1__CLASSB__MASK 0x00003800U +#define PMU1__CLASSB__READ(src) (((u_int32_t)(src) & 0x00003800U) >> 11) +#define PMU1__CLASSB__WRITE(src) (((u_int32_t)(src) << 11) & 0x00003800U) +#define PMU1__CLASSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define PMU1__CLASSB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field Cc */ +#define PMU1__CC__SHIFT 14 +#define PMU1__CC__WIDTH 3 +#define PMU1__CC__MASK 0x0001c000U +#define PMU1__CC__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) +#define PMU1__CC__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U) +#define PMU1__CC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define PMU1__CC__VERIFY(src) (!((((u_int32_t)(src) << 14) & ~0x0001c000U))) + +/* macros for field Rc */ +#define PMU1__RC__SHIFT 17 +#define PMU1__RC__WIDTH 3 +#define PMU1__RC__MASK 0x000e0000U +#define PMU1__RC__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) +#define PMU1__RC__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) +#define PMU1__RC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define PMU1__RC__VERIFY(src) (!((((u_int32_t)(src) << 17) & ~0x000e0000U))) + +/* macros for field Rampslope */ +#define PMU1__RAMPSLOPE__SHIFT 20 +#define PMU1__RAMPSLOPE__WIDTH 4 +#define PMU1__RAMPSLOPE__MASK 0x00f00000U +#define PMU1__RAMPSLOPE__READ(src) (((u_int32_t)(src) & 0x00f00000U) >> 20) +#define PMU1__RAMPSLOPE__WRITE(src) (((u_int32_t)(src) << 20) & 0x00f00000U) +#define PMU1__RAMPSLOPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define PMU1__RAMPSLOPE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) + +/* macros for field Segm */ +#define PMU1__SEGM__SHIFT 24 +#define PMU1__SEGM__WIDTH 2 +#define PMU1__SEGM__MASK 0x03000000U +#define PMU1__SEGM__READ(src) (((u_int32_t)(src) & 0x03000000U) >> 24) +#define PMU1__SEGM__WRITE(src) (((u_int32_t)(src) << 24) & 0x03000000U) +#define PMU1__SEGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define PMU1__SEGM__VERIFY(src) (!((((u_int32_t)(src) << 24) & ~0x03000000U))) + +/* macros for field UseLocalOsc */ +#define PMU1__USELOCALOSC__SHIFT 26 +#define PMU1__USELOCALOSC__WIDTH 1 +#define PMU1__USELOCALOSC__MASK 0x04000000U +#define PMU1__USELOCALOSC__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) +#define PMU1__USELOCALOSC__WRITE(src) (((u_int32_t)(src) << 26) & 0x04000000U) +#define PMU1__USELOCALOSC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define PMU1__USELOCALOSC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define PMU1__USELOCALOSC__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define PMU1__USELOCALOSC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field ForceXoscStable */ +#define PMU1__FORCEXOSCSTABLE__SHIFT 27 +#define PMU1__FORCEXOSCSTABLE__WIDTH 1 +#define PMU1__FORCEXOSCSTABLE__MASK 0x08000000U +#define PMU1__FORCEXOSCSTABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define PMU1__FORCEXOSCSTABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define PMU1__FORCEXOSCSTABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define PMU1__FORCEXOSCSTABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define PMU1__FORCEXOSCSTABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define PMU1__FORCEXOSCSTABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field SelFb */ +#define PMU1__SELFB__SHIFT 28 +#define PMU1__SELFB__WIDTH 1 +#define PMU1__SELFB__MASK 0x10000000U +#define PMU1__SELFB__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define PMU1__SELFB__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define PMU1__SELFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define PMU1__SELFB__VERIFY(src) (!((((u_int32_t)(src) << 28) & ~0x10000000U))) +#define PMU1__SELFB__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define PMU1__SELFB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field FilterFb */ +#define PMU1__FILTERFB__SHIFT 29 +#define PMU1__FILTERFB__WIDTH 3 +#define PMU1__FILTERFB__MASK 0xe0000000U +#define PMU1__FILTERFB__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define PMU1__FILTERFB__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define PMU1__FILTERFB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define PMU1__FILTERFB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define PMU1__TYPE u_int32_t +#define PMU1__READ 0xffffffffU +#define PMU1__WRITE 0xffffffffU + +#endif /* __PMU1_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_PMU1 */ +#define INST_RADIO65_REG_BLOCK__CH0_PMU1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PMU2 */ +#ifndef __PMU2_MACRO__ +#define __PMU2_MACRO__ + +/* macros for field SPARE2 */ +#define PMU2__SPARE2__SHIFT 0 +#define PMU2__SPARE2__WIDTH 19 +#define PMU2__SPARE2__MASK 0x0007ffffU +#define PMU2__SPARE2__READ(src) (u_int32_t)(src) & 0x0007ffffU +#define PMU2__SPARE2__WRITE(src) ((u_int32_t)(src) & 0x0007ffffU) +#define PMU2__SPARE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007ffffU) | ((u_int32_t)(src) &\ + 0x0007ffffU) +#define PMU2__SPARE2__VERIFY(src) (!(((u_int32_t)(src) & ~0x0007ffffU))) + +/* macros for field pwdlpo_pwd */ +#define PMU2__PWDLPO_PWD__SHIFT 19 +#define PMU2__PWDLPO_PWD__WIDTH 1 +#define PMU2__PWDLPO_PWD__MASK 0x00080000U +#define PMU2__PWDLPO_PWD__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) +#define PMU2__PWDLPO_PWD__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) +#define PMU2__PWDLPO_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define PMU2__PWDLPO_PWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define PMU2__PWDLPO_PWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define PMU2__PWDLPO_PWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field disc_ovr */ +#define PMU2__DISC_OVR__SHIFT 20 +#define PMU2__DISC_OVR__WIDTH 1 +#define PMU2__DISC_OVR__MASK 0x00100000U +#define PMU2__DISC_OVR__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define PMU2__DISC_OVR__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) +#define PMU2__DISC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define PMU2__DISC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define PMU2__DISC_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define PMU2__DISC_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field pgm */ +#define PMU2__PGM__SHIFT 21 +#define PMU2__PGM__WIDTH 1 +#define PMU2__PGM__MASK 0x00200000U +#define PMU2__PGM__READ(src) (((u_int32_t)(src) & 0x00200000U) >> 21) +#define PMU2__PGM__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U) +#define PMU2__PGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define PMU2__PGM__VERIFY(src) (!((((u_int32_t)(src) << 21) & ~0x00200000U))) +#define PMU2__PGM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define PMU2__PGM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field FilterVc */ +#define PMU2__FILTERVC__SHIFT 22 +#define PMU2__FILTERVC__WIDTH 3 +#define PMU2__FILTERVC__MASK 0x01c00000U +#define PMU2__FILTERVC__READ(src) (((u_int32_t)(src) & 0x01c00000U) >> 22) +#define PMU2__FILTERVC__WRITE(src) (((u_int32_t)(src) << 22) & 0x01c00000U) +#define PMU2__FILTERVC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x01c00000U) +#define PMU2__FILTERVC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x01c00000U))) + +/* macros for field Disc */ +#define PMU2__DISC__SHIFT 25 +#define PMU2__DISC__WIDTH 1 +#define PMU2__DISC__MASK 0x02000000U +#define PMU2__DISC__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) +#define PMU2__DISC__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U) +#define PMU2__DISC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define PMU2__DISC__VERIFY(src) (!((((u_int32_t)(src) << 25) & ~0x02000000U))) +#define PMU2__DISC__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define PMU2__DISC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field DiscDel */ +#define PMU2__DISCDEL__SHIFT 26 +#define PMU2__DISCDEL__WIDTH 3 +#define PMU2__DISCDEL__MASK 0x1c000000U +#define PMU2__DISCDEL__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define PMU2__DISCDEL__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define PMU2__DISCDEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define PMU2__DISCDEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field SPARE1 */ +#define PMU2__SPARE1__SHIFT 29 +#define PMU2__SPARE1__WIDTH 3 +#define PMU2__SPARE1__MASK 0xe0000000U +#define PMU2__SPARE1__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define PMU2__SPARE1__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define PMU2__SPARE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define PMU2__SPARE1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define PMU2__TYPE u_int32_t +#define PMU2__READ 0xffffffffU +#define PMU2__WRITE 0xffffffffU + +#endif /* __PMU2_MACRO__ */ + + +/* macros for radio65_reg_block.ch0_PMU2 */ +#define INST_RADIO65_REG_BLOCK__CH0_PMU2__NUM 1 + +#define POSEIDON_REG_MAP__VERSION \ + "/cad/local/lib/perl/Pinfo.pm\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/analog_intf_reg_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/efuse_reg_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/merlin2_0_radio_reg_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/pcie_phy_reg_csr_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/emulation_misc.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/merlin2_0_radio_reg_map.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/pcie_phy_reg_csr.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/poseidon_radio_reg.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/poseidon_reg.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/env/blueprint/ath_ansic.pm\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/amba_mac/blueprint/rtc_sync_reg.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/amba_mac/svd/blueprint/svd_reg.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/apb_analog/analog_intf_reg.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/bb/blueprint/bb_reg_map.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/host_intf/rtl/blueprint/efuse_reg.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/host_intf/rtl/blueprint/host_intf_reg.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl\n\ + /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/rtc/blueprint/rtc_reg.rdl" +#endif /* __REG_POSEIDON_REG_MAP_MACRO_H__ */ diff --git a/hal/ar9300/scorpion_reg_map.h b/hal/ar9300/scorpion_reg_map.h new file mode 100644 index 000000000000..8f06eca743e2 --- /dev/null +++ b/hal/ar9300/scorpion_reg_map.h @@ -0,0 +1,1356 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* */ +/* File: /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg_map.h*/ +/* Creator: irshad */ +/* Time: Wednesday Feb 15, 2012 [5:06:37 pm] */ +/* */ +/* Path: /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/ +/* Arguments: /cad/denali/blueprint/3.7.3//Linux-64bit/blueprint -dump */ +/* -codegen */ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.codegen*/ +/* -ath_ansic -Wdesc -I */ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/ +/* -I /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint */ +/* -I */ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint*/ +/* -I */ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig*/ +/* -odir */ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/ +/* -eval {$INCLUDE_SYSCONFIG_FILES=1} -eval */ +/* $WAR_EV58615_for_ansic_codegen=1 scorpion_reg.rdl */ +/* */ +/* Sources: /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/rtc/rtc_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/wmac_wrap/rtc_sync_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_radio_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/bb/blueprint/bb_reg_map.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/svd/svd_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.pm*/ +/* /cad/local/lib/perl/Pinfo.pm */ +/* */ +/* Blueprint: 3.7.3 (Fri Aug 29 12:39:16 PDT 2008) */ +/* Machine: rupavathi.users.atheros.com */ +/* OS: Linux 2.6.9-89.ELsmp */ +/* Description: */ +/* */ +/*This Register Map contains the complete register set for scorpion. */ +/* */ +/* Copyright (C) 2012 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ +/* */ + + +#ifndef __REG_SCORPION_REG_MAP_H__ +#define __REG_SCORPION_REG_MAP_H__ + +#include "scorpion_reg_map_macro.h" + +struct mac_dma_reg { + volatile char pad__0[0x8]; /* 0x0 - 0x8 */ + volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */ + volatile char pad__1[0x8]; /* 0xc - 0x14 */ + volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */ + volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */ + volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */ + volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */ + volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */ + volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */ + volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */ + volatile u_int32_t MAC_DMA_TXCFG; /* 0x30 - 0x34 */ + volatile u_int32_t MAC_DMA_RXCFG; /* 0x34 - 0x38 */ + volatile u_int32_t MAC_DMA_RXJLA; /* 0x38 - 0x3c */ + volatile char pad__2[0x4]; /* 0x3c - 0x40 */ + volatile u_int32_t MAC_DMA_MIBC; /* 0x40 - 0x44 */ + volatile u_int32_t MAC_DMA_TOPS; /* 0x44 - 0x48 */ + volatile u_int32_t MAC_DMA_RXNPTO; /* 0x48 - 0x4c */ + volatile u_int32_t MAC_DMA_TXNPTO; /* 0x4c - 0x50 */ + volatile u_int32_t MAC_DMA_RPGTO; /* 0x50 - 0x54 */ + volatile char pad__3[0x4]; /* 0x54 - 0x58 */ + volatile u_int32_t MAC_DMA_MACMISC; /* 0x58 - 0x5c */ + volatile u_int32_t MAC_DMA_INTER; /* 0x5c - 0x60 */ + volatile u_int32_t MAC_DMA_DATABUF; /* 0x60 - 0x64 */ + volatile u_int32_t MAC_DMA_GTT; /* 0x64 - 0x68 */ + volatile u_int32_t MAC_DMA_GTTM; /* 0x68 - 0x6c */ + volatile u_int32_t MAC_DMA_CST; /* 0x6c - 0x70 */ + volatile u_int32_t MAC_DMA_RXDP_SIZE; /* 0x70 - 0x74 */ + volatile u_int32_t MAC_DMA_RX_QUEUE_HP_RXDP; /* 0x74 - 0x78 */ + volatile u_int32_t MAC_DMA_RX_QUEUE_LP_RXDP; /* 0x78 - 0x7c */ + volatile char pad__4[0x4]; /* 0x7c - 0x80 */ + volatile u_int32_t MAC_DMA_ISR_P; /* 0x80 - 0x84 */ + volatile u_int32_t MAC_DMA_ISR_S0; /* 0x84 - 0x88 */ + volatile u_int32_t MAC_DMA_ISR_S1; /* 0x88 - 0x8c */ + volatile u_int32_t MAC_DMA_ISR_S2; /* 0x8c - 0x90 */ + volatile u_int32_t MAC_DMA_ISR_S3; /* 0x90 - 0x94 */ + volatile u_int32_t MAC_DMA_ISR_S4; /* 0x94 - 0x98 */ + volatile u_int32_t MAC_DMA_ISR_S5; /* 0x98 - 0x9c */ + volatile char pad__5[0x4]; /* 0x9c - 0xa0 */ + volatile u_int32_t MAC_DMA_IMR_P; /* 0xa0 - 0xa4 */ + volatile u_int32_t MAC_DMA_IMR_S0; /* 0xa4 - 0xa8 */ + volatile u_int32_t MAC_DMA_IMR_S1; /* 0xa8 - 0xac */ + volatile u_int32_t MAC_DMA_IMR_S2; /* 0xac - 0xb0 */ + volatile u_int32_t MAC_DMA_IMR_S3; /* 0xb0 - 0xb4 */ + volatile u_int32_t MAC_DMA_IMR_S4; /* 0xb4 - 0xb8 */ + volatile u_int32_t MAC_DMA_IMR_S5; /* 0xb8 - 0xbc */ + volatile char pad__6[0x4]; /* 0xbc - 0xc0 */ + volatile u_int32_t MAC_DMA_ISR_P_RAC; /* 0xc0 - 0xc4 */ + volatile u_int32_t MAC_DMA_ISR_S0_S; /* 0xc4 - 0xc8 */ + volatile u_int32_t MAC_DMA_ISR_S1_S; /* 0xc8 - 0xcc */ + volatile char pad__7[0x4]; /* 0xcc - 0xd0 */ + volatile u_int32_t MAC_DMA_ISR_S2_S; /* 0xd0 - 0xd4 */ + volatile u_int32_t MAC_DMA_ISR_S3_S; /* 0xd4 - 0xd8 */ + volatile u_int32_t MAC_DMA_ISR_S4_S; /* 0xd8 - 0xdc */ + volatile u_int32_t MAC_DMA_ISR_S5_S; /* 0xdc - 0xe0 */ + volatile u_int32_t MAC_DMA_DMADBG_0; /* 0xe0 - 0xe4 */ + volatile u_int32_t MAC_DMA_DMADBG_1; /* 0xe4 - 0xe8 */ + volatile u_int32_t MAC_DMA_DMADBG_2; /* 0xe8 - 0xec */ + volatile u_int32_t MAC_DMA_DMADBG_3; /* 0xec - 0xf0 */ + volatile u_int32_t MAC_DMA_DMADBG_4; /* 0xf0 - 0xf4 */ + volatile u_int32_t MAC_DMA_DMADBG_5; /* 0xf4 - 0xf8 */ + volatile u_int32_t MAC_DMA_DMADBG_6; /* 0xf8 - 0xfc */ + volatile u_int32_t MAC_DMA_DMADBG_7; /* 0xfc - 0x100 */ + volatile u_int32_t MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0; + /* 0x100 - 0x104 */ + volatile u_int32_t MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8; + /* 0x104 - 0x108 */ + volatile u_int32_t MAC_DMA_TIMT_0; /* 0x108 - 0x10c */ + volatile u_int32_t MAC_DMA_TIMT_1; /* 0x10c - 0x110 */ + volatile u_int32_t MAC_DMA_TIMT_2; /* 0x110 - 0x114 */ + volatile u_int32_t MAC_DMA_TIMT_3; /* 0x114 - 0x118 */ + volatile u_int32_t MAC_DMA_TIMT_4; /* 0x118 - 0x11c */ + volatile u_int32_t MAC_DMA_TIMT_5; /* 0x11c - 0x120 */ + volatile u_int32_t MAC_DMA_TIMT_6; /* 0x120 - 0x124 */ + volatile u_int32_t MAC_DMA_TIMT_7; /* 0x124 - 0x128 */ + volatile u_int32_t MAC_DMA_TIMT_8; /* 0x128 - 0x12c */ + volatile u_int32_t MAC_DMA_TIMT_9; /* 0x12c - 0x130 */ +}; + +struct mac_qcu_reg { + volatile u_int32_t MAC_QCU_TXDP[10]; /* 0x0 - 0x28 */ + volatile char pad__0[0x8]; /* 0x28 - 0x30 */ + volatile u_int32_t MAC_QCU_STATUS_RING_START; /* 0x30 - 0x34 */ + volatile u_int32_t MAC_QCU_STATUS_RING_END; /* 0x34 - 0x38 */ + volatile u_int32_t MAC_QCU_STATUS_RING_CURRENT; /* 0x38 - 0x3c */ + volatile char pad__1[0x4]; /* 0x3c - 0x40 */ + volatile u_int32_t MAC_QCU_TXE; /* 0x40 - 0x44 */ + volatile char pad__2[0x3c]; /* 0x44 - 0x80 */ + volatile u_int32_t MAC_QCU_TXD; /* 0x80 - 0x84 */ + volatile char pad__3[0x3c]; /* 0x84 - 0xc0 */ + volatile u_int32_t MAC_QCU_CBR[10]; /* 0xc0 - 0xe8 */ + volatile char pad__4[0x18]; /* 0xe8 - 0x100 */ + volatile u_int32_t MAC_QCU_RDYTIME[10]; /* 0x100 - 0x128 */ + volatile char pad__5[0x18]; /* 0x128 - 0x140 */ + volatile u_int32_t MAC_QCU_ONESHOT_ARM_SC; /* 0x140 - 0x144 */ + volatile char pad__6[0x3c]; /* 0x144 - 0x180 */ + volatile u_int32_t MAC_QCU_ONESHOT_ARM_CC; /* 0x180 - 0x184 */ + volatile char pad__7[0x3c]; /* 0x184 - 0x1c0 */ + volatile u_int32_t MAC_QCU_MISC[10]; /* 0x1c0 - 0x1e8 */ + volatile char pad__8[0x18]; /* 0x1e8 - 0x200 */ + volatile u_int32_t MAC_QCU_CNT[10]; /* 0x200 - 0x228 */ + volatile char pad__9[0x18]; /* 0x228 - 0x240 */ + volatile u_int32_t MAC_QCU_RDYTIME_SHDN; /* 0x240 - 0x244 */ + volatile u_int32_t MAC_QCU_DESC_CRC_CHK; /* 0x244 - 0x248 */ +}; + +struct mac_dcu_reg { + volatile u_int32_t MAC_DCU_QCUMASK[10]; /* 0x0 - 0x28 */ + volatile char pad__0[0x8]; /* 0x28 - 0x30 */ + volatile u_int32_t MAC_DCU_GBL_IFS_SIFS; /* 0x30 - 0x34 */ + volatile char pad__1[0x4]; /* 0x34 - 0x38 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU0_31_0; /* 0x38 - 0x3c */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU8_31_0; /* 0x3c - 0x40 */ + volatile u_int32_t MAC_DCU_LCL_IFS[10]; /* 0x40 - 0x68 */ + volatile char pad__2[0x8]; /* 0x68 - 0x70 */ + volatile u_int32_t MAC_DCU_GBL_IFS_SLOT; /* 0x70 - 0x74 */ + volatile char pad__3[0x4]; /* 0x74 - 0x78 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU0_63_32; /* 0x78 - 0x7c */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU8_63_32; /* 0x7c - 0x80 */ + volatile u_int32_t MAC_DCU_RETRY_LIMIT[10]; /* 0x80 - 0xa8 */ + volatile char pad__4[0x8]; /* 0xa8 - 0xb0 */ + volatile u_int32_t MAC_DCU_GBL_IFS_EIFS; /* 0xb0 - 0xb4 */ + volatile char pad__5[0x4]; /* 0xb4 - 0xb8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU0_95_64; /* 0xb8 - 0xbc */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU8_95_64; /* 0xbc - 0xc0 */ + volatile u_int32_t MAC_DCU_CHANNEL_TIME[10]; /* 0xc0 - 0xe8 */ + volatile char pad__6[0x8]; /* 0xe8 - 0xf0 */ + volatile u_int32_t MAC_DCU_GBL_IFS_MISC; /* 0xf0 - 0xf4 */ + volatile char pad__7[0x4]; /* 0xf4 - 0xf8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU0_127_96; + /* 0xf8 - 0xfc */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU8_127_96; + /* 0xfc - 0x100 */ + volatile u_int32_t MAC_DCU_MISC[10]; /* 0x100 - 0x128 */ + volatile char pad__8[0x10]; /* 0x128 - 0x138 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU1_31_0; /* 0x138 - 0x13c */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU9_31_0; /* 0x13c - 0x140 */ + volatile u_int32_t MAC_DCU_SEQ; /* 0x140 - 0x144 */ + volatile char pad__9[0x34]; /* 0x144 - 0x178 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU1_63_32; /* 0x178 - 0x17c */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU9_63_32; /* 0x17c - 0x180 */ + volatile char pad__10[0x38]; /* 0x180 - 0x1b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU1_95_64; /* 0x1b8 - 0x1bc */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU9_95_64; /* 0x1bc - 0x1c0 */ + volatile char pad__11[0x38]; /* 0x1c0 - 0x1f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU1_127_96; + /* 0x1f8 - 0x1fc */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU9_127_96; + /* 0x1fc - 0x200 */ + volatile char pad__12[0x38]; /* 0x200 - 0x238 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU2_31_0; /* 0x238 - 0x23c */ + volatile char pad__13[0x34]; /* 0x23c - 0x270 */ + volatile u_int32_t MAC_DCU_PAUSE; /* 0x270 - 0x274 */ + volatile char pad__14[0x4]; /* 0x274 - 0x278 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU2_63_32; /* 0x278 - 0x27c */ + volatile char pad__15[0x34]; /* 0x27c - 0x2b0 */ + volatile u_int32_t MAC_DCU_WOW_KACFG; /* 0x2b0 - 0x2b4 */ + volatile char pad__16[0x4]; /* 0x2b4 - 0x2b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU2_95_64; /* 0x2b8 - 0x2bc */ + volatile char pad__17[0x34]; /* 0x2bc - 0x2f0 */ + volatile u_int32_t MAC_DCU_TXSLOT; /* 0x2f0 - 0x2f4 */ + volatile char pad__18[0x4]; /* 0x2f4 - 0x2f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU2_127_96; + /* 0x2f8 - 0x2fc */ + volatile char pad__19[0x3c]; /* 0x2fc - 0x338 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU3_31_0; /* 0x338 - 0x33c */ + volatile char pad__20[0x3c]; /* 0x33c - 0x378 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU3_63_32; /* 0x378 - 0x37c */ + volatile char pad__21[0x3c]; /* 0x37c - 0x3b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU3_95_64; /* 0x3b8 - 0x3bc */ + volatile char pad__22[0x3c]; /* 0x3bc - 0x3f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU3_127_96; + /* 0x3f8 - 0x3fc */ + volatile char pad__23[0x3c]; /* 0x3fc - 0x438 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU4_31_0; /* 0x438 - 0x43c */ + volatile u_int32_t MAC_DCU_TXFILTER_CLEAR; /* 0x43c - 0x440 */ + volatile char pad__24[0x38]; /* 0x440 - 0x478 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU4_63_32; /* 0x478 - 0x47c */ + volatile u_int32_t MAC_DCU_TXFILTER_SET; /* 0x47c - 0x480 */ + volatile char pad__25[0x38]; /* 0x480 - 0x4b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU4_95_64; /* 0x4b8 - 0x4bc */ + volatile char pad__26[0x3c]; /* 0x4bc - 0x4f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU4_127_96; + /* 0x4f8 - 0x4fc */ + volatile char pad__27[0x3c]; /* 0x4fc - 0x538 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU5_31_0; /* 0x538 - 0x53c */ + volatile char pad__28[0x3c]; /* 0x53c - 0x578 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU5_63_32; /* 0x578 - 0x57c */ + volatile char pad__29[0x3c]; /* 0x57c - 0x5b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU5_95_64; /* 0x5b8 - 0x5bc */ + volatile char pad__30[0x3c]; /* 0x5bc - 0x5f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU5_127_96; + /* 0x5f8 - 0x5fc */ + volatile char pad__31[0x3c]; /* 0x5fc - 0x638 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU6_31_0; /* 0x638 - 0x63c */ + volatile char pad__32[0x3c]; /* 0x63c - 0x678 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU6_63_32; /* 0x678 - 0x67c */ + volatile char pad__33[0x3c]; /* 0x67c - 0x6b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU6_95_64; /* 0x6b8 - 0x6bc */ + volatile char pad__34[0x3c]; /* 0x6bc - 0x6f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU6_127_96; + /* 0x6f8 - 0x6fc */ + volatile char pad__35[0x3c]; /* 0x6fc - 0x738 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU7_31_0; /* 0x738 - 0x73c */ + volatile char pad__36[0x3c]; /* 0x73c - 0x778 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU7_63_32; /* 0x778 - 0x77c */ + volatile char pad__37[0x3c]; /* 0x77c - 0x7b8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU7_95_64; /* 0x7b8 - 0x7bc */ + volatile char pad__38[0x3c]; /* 0x7bc - 0x7f8 */ + volatile u_int32_t MAC_DCU_TXFILTER_DCU7_127_96; + /* 0x7f8 - 0x7fc */ + volatile char pad__39[0x704]; /* 0x7fc - 0xf00 */ + volatile u_int32_t MAC_SLEEP_STATUS; /* 0xf00 - 0xf04 */ + volatile u_int32_t MAC_LED_CONFIG; /* 0xf04 - 0xf08 */ +}; + +struct rtc_reg { + volatile u_int32_t RESET_CONTROL; /* 0x0 - 0x4 */ + volatile u_int32_t XTAL_CONTROL; /* 0x4 - 0x8 */ + volatile u_int32_t REG_CONTROL0; /* 0x8 - 0xc */ + volatile u_int32_t REG_CONTROL1; /* 0xc - 0x10 */ + volatile u_int32_t QUADRATURE; /* 0x10 - 0x14 */ + volatile u_int32_t PLL_CONTROL; /* 0x14 - 0x18 */ + volatile u_int32_t PLL_SETTLE; /* 0x18 - 0x1c */ + volatile u_int32_t XTAL_SETTLE; /* 0x1c - 0x20 */ + volatile u_int32_t CLOCK_OUT; /* 0x20 - 0x24 */ + volatile u_int32_t BIAS_OVERRIDE; /* 0x24 - 0x28 */ + volatile u_int32_t RESET_CAUSE; /* 0x28 - 0x2c */ + volatile u_int32_t SYSTEM_SLEEP; /* 0x2c - 0x30 */ + volatile u_int32_t MAC_SLEEP_CONTROL; /* 0x30 - 0x34 */ + volatile u_int32_t KEEP_AWAKE; /* 0x34 - 0x38 */ + volatile u_int32_t DERIVED_RTC_CLK; /* 0x38 - 0x3c */ + volatile u_int32_t PLL_CONTROL2; /* 0x3c - 0x40 */ +}; + +struct rtc_sync_reg { + volatile u_int32_t RTC_SYNC_RESET; /* 0x0 - 0x4 */ + volatile u_int32_t RTC_SYNC_STATUS; /* 0x4 - 0x8 */ + volatile u_int32_t RTC_SYNC_DERIVED; /* 0x8 - 0xc */ + volatile u_int32_t RTC_SYNC_FORCE_WAKE; /* 0xc - 0x10 */ + volatile u_int32_t RTC_SYNC_INTR_CAUSE; /* 0x10 - 0x14 */ + volatile u_int32_t RTC_SYNC_INTR_ENABLE; /* 0x14 - 0x18 */ + volatile u_int32_t RTC_SYNC_INTR_MASK; /* 0x18 - 0x1c */ +}; + +struct mac_pcu_reg { + volatile u_int32_t MAC_PCU_STA_ADDR_L32; /* 0x0 - 0x4 */ + volatile u_int32_t MAC_PCU_STA_ADDR_U16; /* 0x4 - 0x8 */ + volatile u_int32_t MAC_PCU_BSSID_L32; /* 0x8 - 0xc */ + volatile u_int32_t MAC_PCU_BSSID_U16; /* 0xc - 0x10 */ + volatile u_int32_t MAC_PCU_BCN_RSSI_AVE; /* 0x10 - 0x14 */ + volatile u_int32_t MAC_PCU_ACK_CTS_TIMEOUT; /* 0x14 - 0x18 */ + volatile u_int32_t MAC_PCU_BCN_RSSI_CTL; /* 0x18 - 0x1c */ + volatile u_int32_t MAC_PCU_USEC_LATENCY; /* 0x1c - 0x20 */ + volatile u_int32_t MAC_PCU_RESET_TSF; /* 0x20 - 0x24 */ + volatile char pad__0[0x14]; /* 0x24 - 0x38 */ + volatile u_int32_t MAC_PCU_MAX_CFP_DUR; /* 0x38 - 0x3c */ + volatile u_int32_t MAC_PCU_RX_FILTER; /* 0x3c - 0x40 */ + volatile u_int32_t MAC_PCU_MCAST_FILTER_L32; /* 0x40 - 0x44 */ + volatile u_int32_t MAC_PCU_MCAST_FILTER_U32; /* 0x44 - 0x48 */ + volatile u_int32_t MAC_PCU_DIAG_SW; /* 0x48 - 0x4c */ + volatile u_int32_t MAC_PCU_TSF_L32; /* 0x4c - 0x50 */ + volatile u_int32_t MAC_PCU_TSF_U32; /* 0x50 - 0x54 */ + volatile u_int32_t MAC_PCU_TST_ADDAC; /* 0x54 - 0x58 */ + volatile u_int32_t MAC_PCU_DEF_ANTENNA; /* 0x58 - 0x5c */ + volatile u_int32_t MAC_PCU_AES_MUTE_MASK_0; /* 0x5c - 0x60 */ + volatile u_int32_t MAC_PCU_AES_MUTE_MASK_1; /* 0x60 - 0x64 */ + volatile u_int32_t MAC_PCU_GATED_CLKS; /* 0x64 - 0x68 */ + volatile u_int32_t MAC_PCU_OBS_BUS_2; /* 0x68 - 0x6c */ + volatile u_int32_t MAC_PCU_OBS_BUS_1; /* 0x6c - 0x70 */ + volatile u_int32_t MAC_PCU_DYM_MIMO_PWR_SAVE; /* 0x70 - 0x74 */ + volatile u_int32_t MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB; + /* 0x74 - 0x78 */ + volatile u_int32_t MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB; + /* 0x78 - 0x7c */ + volatile char pad__1[0x4]; /* 0x7c - 0x80 */ + volatile u_int32_t MAC_PCU_LAST_BEACON_TSF; /* 0x80 - 0x84 */ + volatile u_int32_t MAC_PCU_NAV; /* 0x84 - 0x88 */ + volatile u_int32_t MAC_PCU_RTS_SUCCESS_CNT; /* 0x88 - 0x8c */ + volatile u_int32_t MAC_PCU_RTS_FAIL_CNT; /* 0x8c - 0x90 */ + volatile u_int32_t MAC_PCU_ACK_FAIL_CNT; /* 0x90 - 0x94 */ + volatile u_int32_t MAC_PCU_FCS_FAIL_CNT; /* 0x94 - 0x98 */ + volatile u_int32_t MAC_PCU_BEACON_CNT; /* 0x98 - 0x9c */ + volatile u_int32_t MAC_PCU_TDMA_SLOT_ALERT_CNTL; + /* 0x9c - 0xa0 */ + volatile u_int32_t MAC_PCU_BASIC_SET; /* 0xa0 - 0xa4 */ + volatile u_int32_t MAC_PCU_MGMT_SEQ; /* 0xa4 - 0xa8 */ + volatile u_int32_t MAC_PCU_BF_RPT1; /* 0xa8 - 0xac */ + volatile u_int32_t MAC_PCU_BF_RPT2; /* 0xac - 0xb0 */ + volatile u_int32_t MAC_PCU_TX_ANT_1; /* 0xb0 - 0xb4 */ + volatile u_int32_t MAC_PCU_TX_ANT_2; /* 0xb4 - 0xb8 */ + volatile u_int32_t MAC_PCU_TX_ANT_3; /* 0xb8 - 0xbc */ + volatile u_int32_t MAC_PCU_TX_ANT_4; /* 0xbc - 0xc0 */ + volatile u_int32_t MAC_PCU_XRMODE; /* 0xc0 - 0xc4 */ + volatile u_int32_t MAC_PCU_XRDEL; /* 0xc4 - 0xc8 */ + volatile u_int32_t MAC_PCU_XRTO; /* 0xc8 - 0xcc */ + volatile u_int32_t MAC_PCU_XRCRP; /* 0xcc - 0xd0 */ + volatile u_int32_t MAC_PCU_XRSTMP; /* 0xd0 - 0xd4 */ + volatile u_int32_t MAC_PCU_SLP1; /* 0xd4 - 0xd8 */ + volatile u_int32_t MAC_PCU_SLP2; /* 0xd8 - 0xdc */ + volatile u_int32_t MAC_PCU_SELF_GEN_DEFAULT; /* 0xdc - 0xe0 */ + volatile u_int32_t MAC_PCU_ADDR1_MASK_L32; /* 0xe0 - 0xe4 */ + volatile u_int32_t MAC_PCU_ADDR1_MASK_U16; /* 0xe4 - 0xe8 */ + volatile u_int32_t MAC_PCU_TPC; /* 0xe8 - 0xec */ + volatile u_int32_t MAC_PCU_TX_FRAME_CNT; /* 0xec - 0xf0 */ + volatile u_int32_t MAC_PCU_RX_FRAME_CNT; /* 0xf0 - 0xf4 */ + volatile u_int32_t MAC_PCU_RX_CLEAR_CNT; /* 0xf4 - 0xf8 */ + volatile u_int32_t MAC_PCU_CYCLE_CNT; /* 0xf8 - 0xfc */ + volatile u_int32_t MAC_PCU_QUIET_TIME_1; /* 0xfc - 0x100 */ + volatile u_int32_t MAC_PCU_QUIET_TIME_2; /* 0x100 - 0x104 */ + volatile char pad__2[0x4]; /* 0x104 - 0x108 */ + volatile u_int32_t MAC_PCU_QOS_NO_ACK; /* 0x108 - 0x10c */ + volatile u_int32_t MAC_PCU_PHY_ERROR_MASK; /* 0x10c - 0x110 */ + volatile u_int32_t MAC_PCU_XRLAT; /* 0x110 - 0x114 */ + volatile u_int32_t MAC_PCU_RXBUF; /* 0x114 - 0x118 */ + volatile u_int32_t MAC_PCU_MIC_QOS_CONTROL; /* 0x118 - 0x11c */ + volatile u_int32_t MAC_PCU_MIC_QOS_SELECT; /* 0x11c - 0x120 */ + volatile u_int32_t MAC_PCU_MISC_MODE; /* 0x120 - 0x124 */ + volatile u_int32_t MAC_PCU_FILTER_OFDM_CNT; /* 0x124 - 0x128 */ + volatile u_int32_t MAC_PCU_FILTER_CCK_CNT; /* 0x128 - 0x12c */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_1; /* 0x12c - 0x130 */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_1_MASK; /* 0x130 - 0x134 */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_2; /* 0x134 - 0x138 */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_2_MASK; /* 0x138 - 0x13c */ + volatile u_int32_t MAC_PCU_TSF_THRESHOLD; /* 0x13c - 0x140 */ + volatile u_int32_t MAC_PCU_MISC_MODE4; /* 0x140 - 0x144 */ + volatile u_int32_t MAC_PCU_PHY_ERROR_EIFS_MASK; /* 0x144 - 0x148 */ + volatile char pad__3[0x20]; /* 0x148 - 0x168 */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_3; /* 0x168 - 0x16c */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_3_MASK; /* 0x16c - 0x170 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_MODE; /* 0x170 - 0x174 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_WL_WEIGHTS0; + /* 0x174 - 0x178 */ + volatile u_int32_t MAC_PCU_HCF_TIMEOUT; /* 0x178 - 0x17c */ + volatile u_int32_t MAC_PCU_BLUETOOTH_MODE2; /* 0x17c - 0x180 */ + volatile u_int32_t MAC_PCU_GENERIC_TIMERS2[16]; /* 0x180 - 0x1c0 */ + volatile u_int32_t MAC_PCU_GENERIC_TIMERS2_MODE; + /* 0x1c0 - 0x1c4 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_WL_WEIGHTS1; + /* 0x1c4 - 0x1c8 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE; + /* 0x1c8 - 0x1cc */ + volatile u_int32_t MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY; + /* 0x1cc - 0x1d0 */ + volatile u_int32_t MAC_PCU_TXSIFS; /* 0x1d0 - 0x1d4 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_MODE3; /* 0x1d4 - 0x1d8 */ + volatile char pad__4[0x14]; /* 0x1d8 - 0x1ec */ + volatile u_int32_t MAC_PCU_TXOP_X; /* 0x1ec - 0x1f0 */ + volatile u_int32_t MAC_PCU_TXOP_0_3; /* 0x1f0 - 0x1f4 */ + volatile u_int32_t MAC_PCU_TXOP_4_7; /* 0x1f4 - 0x1f8 */ + volatile u_int32_t MAC_PCU_TXOP_8_11; /* 0x1f8 - 0x1fc */ + volatile u_int32_t MAC_PCU_TXOP_12_15; /* 0x1fc - 0x200 */ + volatile u_int32_t MAC_PCU_GENERIC_TIMERS[16]; /* 0x200 - 0x240 */ + volatile u_int32_t MAC_PCU_GENERIC_TIMERS_MODE; /* 0x240 - 0x244 */ + volatile u_int32_t MAC_PCU_SLP32_MODE; /* 0x244 - 0x248 */ + volatile u_int32_t MAC_PCU_SLP32_WAKE; /* 0x248 - 0x24c */ + volatile u_int32_t MAC_PCU_SLP32_INC; /* 0x24c - 0x250 */ + volatile u_int32_t MAC_PCU_SLP_MIB1; /* 0x250 - 0x254 */ + volatile u_int32_t MAC_PCU_SLP_MIB2; /* 0x254 - 0x258 */ + volatile u_int32_t MAC_PCU_SLP_MIB3; /* 0x258 - 0x25c */ + volatile u_int32_t MAC_PCU_WOW1; /* 0x25c - 0x260 */ + volatile u_int32_t MAC_PCU_WOW2; /* 0x260 - 0x264 */ + volatile u_int32_t MAC_PCU_LOGIC_ANALYZER; /* 0x264 - 0x268 */ + volatile u_int32_t MAC_PCU_LOGIC_ANALYZER_32L; /* 0x268 - 0x26c */ + volatile u_int32_t MAC_PCU_LOGIC_ANALYZER_16U; /* 0x26c - 0x270 */ + volatile u_int32_t MAC_PCU_WOW3_BEACON_FAIL; /* 0x270 - 0x274 */ + volatile u_int32_t MAC_PCU_WOW3_BEACON; /* 0x274 - 0x278 */ + volatile u_int32_t MAC_PCU_WOW3_KEEP_ALIVE; /* 0x278 - 0x27c */ + volatile u_int32_t MAC_PCU_WOW_KA; /* 0x27c - 0x280 */ + volatile char pad__5[0x4]; /* 0x280 - 0x284 */ + volatile u_int32_t PCU_1US; /* 0x284 - 0x288 */ + volatile u_int32_t PCU_KA; /* 0x288 - 0x28c */ + volatile u_int32_t WOW_EXACT; /* 0x28c - 0x290 */ + volatile char pad__6[0x4]; /* 0x290 - 0x294 */ + volatile u_int32_t PCU_WOW4; /* 0x294 - 0x298 */ + volatile u_int32_t PCU_WOW5; /* 0x298 - 0x29c */ + volatile u_int32_t MAC_PCU_PHY_ERR_CNT_MASK_CONT; + /* 0x29c - 0x2a0 */ + volatile char pad__7[0x60]; /* 0x2a0 - 0x300 */ + volatile u_int32_t MAC_PCU_AZIMUTH_MODE; /* 0x300 - 0x304 */ + volatile char pad__8[0x10]; /* 0x304 - 0x314 */ + volatile u_int32_t MAC_PCU_AZIMUTH_TIME_STAMP; /* 0x314 - 0x318 */ + volatile u_int32_t MAC_PCU_20_40_MODE; /* 0x318 - 0x31c */ + volatile u_int32_t MAC_PCU_H_XFER_TIMEOUT; /* 0x31c - 0x320 */ + volatile char pad__9[0x8]; /* 0x320 - 0x328 */ + volatile u_int32_t MAC_PCU_RX_CLEAR_DIFF_CNT; /* 0x328 - 0x32c */ + volatile u_int32_t MAC_PCU_SELF_GEN_ANTENNA_MASK; + /* 0x32c - 0x330 */ + volatile u_int32_t MAC_PCU_BA_BAR_CONTROL; /* 0x330 - 0x334 */ + volatile u_int32_t MAC_PCU_LEGACY_PLCP_SPOOF; /* 0x334 - 0x338 */ + volatile u_int32_t MAC_PCU_PHY_ERROR_MASK_CONT; /* 0x338 - 0x33c */ + volatile u_int32_t MAC_PCU_TX_TIMER; /* 0x33c - 0x340 */ + volatile u_int32_t MAC_PCU_TXBUF_CTRL; /* 0x340 - 0x344 */ + volatile u_int32_t MAC_PCU_MISC_MODE2; /* 0x344 - 0x348 */ + volatile u_int32_t MAC_PCU_ALT_AES_MUTE_MASK; /* 0x348 - 0x34c */ + volatile u_int32_t MAC_PCU_WOW6; /* 0x34c - 0x350 */ + volatile u_int32_t ASYNC_FIFO_REG1; /* 0x350 - 0x354 */ + volatile u_int32_t ASYNC_FIFO_REG2; /* 0x354 - 0x358 */ + volatile u_int32_t ASYNC_FIFO_REG3; /* 0x358 - 0x35c */ + volatile u_int32_t MAC_PCU_WOW5; /* 0x35c - 0x360 */ + volatile u_int32_t MAC_PCU_WOW_LENGTH1; /* 0x360 - 0x364 */ + volatile u_int32_t MAC_PCU_WOW_LENGTH2; /* 0x364 - 0x368 */ + volatile u_int32_t WOW_PATTERN_MATCH_LESS_THAN_256_BYTES; + /* 0x368 - 0x36c */ + volatile char pad__10[0x4]; /* 0x36c - 0x370 */ + volatile u_int32_t MAC_PCU_WOW4; /* 0x370 - 0x374 */ + volatile u_int32_t WOW2_EXACT; /* 0x374 - 0x378 */ + volatile u_int32_t PCU_WOW6; /* 0x378 - 0x37c */ + volatile u_int32_t PCU_WOW7; /* 0x37c - 0x380 */ + volatile u_int32_t MAC_PCU_WOW_LENGTH3; /* 0x380 - 0x384 */ + volatile u_int32_t MAC_PCU_WOW_LENGTH4; /* 0x384 - 0x388 */ + volatile u_int32_t MAC_PCU_LOCATION_MODE_CONTROL; + /* 0x388 - 0x38c */ + volatile u_int32_t MAC_PCU_LOCATION_MODE_TIMER; /* 0x38c - 0x390 */ + volatile u_int32_t MAC_PCU_TSF2_L32; /* 0x390 - 0x394 */ + volatile u_int32_t MAC_PCU_TSF2_U32; /* 0x394 - 0x398 */ + volatile u_int32_t MAC_PCU_BSSID2_L32; /* 0x398 - 0x39c */ + volatile u_int32_t MAC_PCU_BSSID2_U16; /* 0x39c - 0x3a0 */ + volatile u_int32_t MAC_PCU_DIRECT_CONNECT; /* 0x3a0 - 0x3a4 */ + volatile u_int32_t MAC_PCU_TID_TO_AC; /* 0x3a4 - 0x3a8 */ + volatile u_int32_t MAC_PCU_HP_QUEUE; /* 0x3a8 - 0x3ac */ + volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS0; + /* 0x3ac - 0x3b0 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS1; + /* 0x3b0 - 0x3b4 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS2; + /* 0x3b4 - 0x3b8 */ + volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS3; + /* 0x3b8 - 0x3bc */ + volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT0; /* 0x3bc - 0x3c0 */ + volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT1; /* 0x3c0 - 0x3c4 */ + volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT2; /* 0x3c4 - 0x3c8 */ + volatile u_int32_t MAC_PCU_HW_BCN_PROC1; /* 0x3c8 - 0x3cc */ + volatile u_int32_t MAC_PCU_HW_BCN_PROC2; /* 0x3cc - 0x3d0 */ + volatile u_int32_t MAC_PCU_MISC_MODE3; /* 0x3d0 - 0x3d4 */ + volatile u_int32_t MAC_PCU_FILTER_RSSI_AVE; /* 0x3d4 - 0x3d8 */ + volatile u_int32_t MAC_PCU_PHY_ERROR_AIFS_MASK; /* 0x3d8 - 0x3dc */ + volatile u_int32_t MAC_PCU_PS_FILTER; /* 0x3dc - 0x3e0 */ + volatile char pad__11[0x20]; /* 0x3e0 - 0x400 */ + volatile u_int32_t MAC_PCU_TXBUF_BA[64]; /* 0x400 - 0x500 */ + volatile char pad__12[0x300]; /* 0x500 - 0x800 */ + volatile u_int32_t MAC_PCU_KEY_CACHE[1024]; /* 0x800 - 0x1800 */ +}; + +struct chn_reg_map { + volatile u_int32_t BB_timing_controls_1; /* 0x0 - 0x4 */ + volatile u_int32_t BB_timing_controls_2; /* 0x4 - 0x8 */ + volatile u_int32_t BB_timing_controls_3; /* 0x8 - 0xc */ + volatile u_int32_t BB_timing_control_4; /* 0xc - 0x10 */ + volatile u_int32_t BB_timing_control_5; /* 0x10 - 0x14 */ + volatile u_int32_t BB_timing_control_6; /* 0x14 - 0x18 */ + volatile u_int32_t BB_timing_control_11; /* 0x18 - 0x1c */ + volatile u_int32_t BB_spur_mask_controls; /* 0x1c - 0x20 */ + volatile u_int32_t BB_find_signal_low; /* 0x20 - 0x24 */ + volatile u_int32_t BB_sfcorr; /* 0x24 - 0x28 */ + volatile u_int32_t BB_self_corr_low; /* 0x28 - 0x2c */ + volatile u_int32_t BB_ext_chan_scorr_thr; /* 0x2c - 0x30 */ + volatile u_int32_t BB_ext_chan_pwr_thr_2_b0; /* 0x30 - 0x34 */ + volatile u_int32_t BB_radar_detection; /* 0x34 - 0x38 */ + volatile u_int32_t BB_radar_detection_2; /* 0x38 - 0x3c */ + volatile u_int32_t BB_extension_radar; /* 0x3c - 0x40 */ + volatile char pad__0[0x40]; /* 0x40 - 0x80 */ + volatile u_int32_t BB_multichain_control; /* 0x80 - 0x84 */ + volatile u_int32_t BB_per_chain_csd; /* 0x84 - 0x88 */ + volatile char pad__1[0x18]; /* 0x88 - 0xa0 */ + volatile u_int32_t BB_tx_crc; /* 0xa0 - 0xa4 */ + volatile u_int32_t BB_tstdac_constant; /* 0xa4 - 0xa8 */ + volatile u_int32_t BB_spur_report_b0; /* 0xa8 - 0xac */ + volatile char pad__2[0x4]; /* 0xac - 0xb0 */ + volatile u_int32_t BB_txiqcal_control_3; /* 0xb0 - 0xb4 */ + volatile char pad__3[0x8]; /* 0xb4 - 0xbc */ + volatile u_int32_t BB_green_tx_control_1; /* 0xbc - 0xc0 */ + volatile u_int32_t BB_iq_adc_meas_0_b0; /* 0xc0 - 0xc4 */ + volatile u_int32_t BB_iq_adc_meas_1_b0; /* 0xc4 - 0xc8 */ + volatile u_int32_t BB_iq_adc_meas_2_b0; /* 0xc8 - 0xcc */ + volatile u_int32_t BB_iq_adc_meas_3_b0; /* 0xcc - 0xd0 */ + volatile u_int32_t BB_tx_phase_ramp_b0; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_adc_gain_dc_corr_b0; /* 0xd4 - 0xd8 */ + volatile char pad__4[0x4]; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_rx_iq_corr_b0; /* 0xdc - 0xe0 */ + volatile char pad__5[0x4]; /* 0xe0 - 0xe4 */ + volatile u_int32_t BB_paprd_am2am_mask; /* 0xe4 - 0xe8 */ + volatile u_int32_t BB_paprd_am2pm_mask; /* 0xe8 - 0xec */ + volatile u_int32_t BB_paprd_ht40_mask; /* 0xec - 0xf0 */ + volatile u_int32_t BB_paprd_ctrl0_b0; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_paprd_ctrl1_b0; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_pa_gain123_b0; /* 0xf8 - 0xfc */ + volatile u_int32_t BB_pa_gain45_b0; /* 0xfc - 0x100 */ + volatile u_int32_t BB_paprd_pre_post_scale_0_b0; + /* 0x100 - 0x104 */ + volatile u_int32_t BB_paprd_pre_post_scale_1_b0; + /* 0x104 - 0x108 */ + volatile u_int32_t BB_paprd_pre_post_scale_2_b0; + /* 0x108 - 0x10c */ + volatile u_int32_t BB_paprd_pre_post_scale_3_b0; + /* 0x10c - 0x110 */ + volatile u_int32_t BB_paprd_pre_post_scale_4_b0; + /* 0x110 - 0x114 */ + volatile u_int32_t BB_paprd_pre_post_scale_5_b0; + /* 0x114 - 0x118 */ + volatile u_int32_t BB_paprd_pre_post_scale_6_b0; + /* 0x118 - 0x11c */ + volatile u_int32_t BB_paprd_pre_post_scale_7_b0; + /* 0x11c - 0x120 */ + volatile u_int32_t BB_paprd_mem_tab_b0[120]; /* 0x120 - 0x300 */ + volatile u_int32_t BB_chan_info_chan_tab_b0[60]; + /* 0x300 - 0x3f0 */ + volatile u_int32_t BB_chn_tables_intf_addr; /* 0x3f0 - 0x3f4 */ + volatile u_int32_t BB_chn_tables_intf_data; /* 0x3f4 - 0x3f8 */ +}; + +struct mrc_reg_map { + volatile u_int32_t BB_timing_control_3a; /* 0x0 - 0x4 */ + volatile u_int32_t BB_ldpc_cntl1; /* 0x4 - 0x8 */ + volatile u_int32_t BB_ldpc_cntl2; /* 0x8 - 0xc */ + volatile u_int32_t BB_pilot_spur_mask; /* 0xc - 0x10 */ + volatile u_int32_t BB_chan_spur_mask; /* 0x10 - 0x14 */ + volatile u_int32_t BB_short_gi_delta_slope; /* 0x14 - 0x18 */ + volatile u_int32_t BB_ml_cntl1; /* 0x18 - 0x1c */ + volatile u_int32_t BB_ml_cntl2; /* 0x1c - 0x20 */ + volatile u_int32_t BB_tstadc; /* 0x20 - 0x24 */ +}; + +struct bbb_reg_map { + volatile u_int32_t BB_bbb_rx_ctrl_1; /* 0x0 - 0x4 */ + volatile u_int32_t BB_bbb_rx_ctrl_2; /* 0x4 - 0x8 */ + volatile u_int32_t BB_bbb_rx_ctrl_3; /* 0x8 - 0xc */ + volatile u_int32_t BB_bbb_rx_ctrl_4; /* 0xc - 0x10 */ + volatile u_int32_t BB_bbb_rx_ctrl_5; /* 0x10 - 0x14 */ + volatile u_int32_t BB_bbb_rx_ctrl_6; /* 0x14 - 0x18 */ + volatile u_int32_t BB_force_clken_cck; /* 0x18 - 0x1c */ +}; + +struct agc_reg_map { + volatile u_int32_t BB_settling_time; /* 0x0 - 0x4 */ + volatile u_int32_t BB_gain_force_max_gains_b0; /* 0x4 - 0x8 */ + volatile u_int32_t BB_gains_min_offsets; /* 0x8 - 0xc */ + volatile u_int32_t BB_desired_sigsize; /* 0xc - 0x10 */ + volatile u_int32_t BB_find_signal; /* 0x10 - 0x14 */ + volatile u_int32_t BB_agc; /* 0x14 - 0x18 */ + volatile u_int32_t BB_ext_atten_switch_ctl_b0; /* 0x18 - 0x1c */ + volatile u_int32_t BB_cca_b0; /* 0x1c - 0x20 */ + volatile u_int32_t BB_cca_ctrl_2_b0; /* 0x20 - 0x24 */ + volatile u_int32_t BB_restart; /* 0x24 - 0x28 */ + volatile u_int32_t BB_multichain_gain_ctrl; /* 0x28 - 0x2c */ + volatile u_int32_t BB_ext_chan_pwr_thr_1; /* 0x2c - 0x30 */ + volatile u_int32_t BB_ext_chan_detect_win; /* 0x30 - 0x34 */ + volatile u_int32_t BB_pwr_thr_20_40_det; /* 0x34 - 0x38 */ + volatile u_int32_t BB_rifs_srch; /* 0x38 - 0x3c */ + volatile u_int32_t BB_peak_det_ctrl_1; /* 0x3c - 0x40 */ + volatile u_int32_t BB_peak_det_ctrl_2; /* 0x40 - 0x44 */ + volatile u_int32_t BB_rx_gain_bounds_1; /* 0x44 - 0x48 */ + volatile u_int32_t BB_rx_gain_bounds_2; /* 0x48 - 0x4c */ + volatile u_int32_t BB_peak_det_cal_ctrl; /* 0x4c - 0x50 */ + volatile u_int32_t BB_agc_dig_dc_ctrl; /* 0x50 - 0x54 */ + volatile u_int32_t BB_bt_coex_1; /* 0x54 - 0x58 */ + volatile u_int32_t BB_bt_coex_2; /* 0x58 - 0x5c */ + volatile u_int32_t BB_bt_coex_3; /* 0x5c - 0x60 */ + volatile u_int32_t BB_bt_coex_4; /* 0x60 - 0x64 */ + volatile u_int32_t BB_bt_coex_5; /* 0x64 - 0x68 */ + volatile u_int32_t BB_redpwr_ctrl_1; /* 0x68 - 0x6c */ + volatile u_int32_t BB_redpwr_ctrl_2; /* 0x6c - 0x70 */ + volatile char pad__0[0x110]; /* 0x70 - 0x180 */ + volatile u_int32_t BB_rssi_b0; /* 0x180 - 0x184 */ + volatile u_int32_t BB_spur_est_cck_report_b0; /* 0x184 - 0x188 */ + volatile u_int32_t BB_agc_dig_dc_status_i_b0; /* 0x188 - 0x18c */ + volatile u_int32_t BB_agc_dig_dc_status_q_b0; /* 0x18c - 0x190 */ + volatile u_int32_t BB_dc_cal_status_b0; /* 0x190 - 0x194 */ + volatile char pad__1[0x2c]; /* 0x194 - 0x1c0 */ + volatile u_int32_t BB_bbb_sig_detect; /* 0x1c0 - 0x1c4 */ + volatile u_int32_t BB_bbb_dagc_ctrl; /* 0x1c4 - 0x1c8 */ + volatile u_int32_t BB_iqcorr_ctrl_cck; /* 0x1c8 - 0x1cc */ + volatile u_int32_t BB_cck_spur_mit; /* 0x1cc - 0x1d0 */ + volatile u_int32_t BB_mrc_cck_ctrl; /* 0x1d0 - 0x1d4 */ + volatile u_int32_t BB_cck_blocker_det; /* 0x1d4 - 0x1d8 */ + volatile char pad__2[0x28]; /* 0x1d8 - 0x200 */ + volatile u_int32_t BB_rx_ocgain[128]; /* 0x200 - 0x400 */ +}; + +struct sm_reg_map { + volatile u_int32_t BB_D2_chip_id; /* 0x0 - 0x4 */ + volatile u_int32_t BB_gen_controls; /* 0x4 - 0x8 */ + volatile u_int32_t BB_modes_select; /* 0x8 - 0xc */ + volatile u_int32_t BB_active; /* 0xc - 0x10 */ + volatile char pad__0[0x10]; /* 0x10 - 0x20 */ + volatile u_int32_t BB_vit_spur_mask_A; /* 0x20 - 0x24 */ + volatile u_int32_t BB_vit_spur_mask_B; /* 0x24 - 0x28 */ + volatile u_int32_t BB_spectral_scan; /* 0x28 - 0x2c */ + volatile u_int32_t BB_radar_bw_filter; /* 0x2c - 0x30 */ + volatile u_int32_t BB_search_start_delay; /* 0x30 - 0x34 */ + volatile u_int32_t BB_max_rx_length; /* 0x34 - 0x38 */ + volatile u_int32_t BB_frame_control; /* 0x38 - 0x3c */ + volatile u_int32_t BB_rfbus_request; /* 0x3c - 0x40 */ + volatile u_int32_t BB_rfbus_grant; /* 0x40 - 0x44 */ + volatile u_int32_t BB_rifs; /* 0x44 - 0x48 */ + volatile u_int32_t BB_spectral_scan_2; /* 0x48 - 0x4c */ + volatile char pad__1[0x4]; /* 0x4c - 0x50 */ + volatile u_int32_t BB_rx_clear_delay; /* 0x50 - 0x54 */ + volatile u_int32_t BB_analog_power_on_time; /* 0x54 - 0x58 */ + volatile u_int32_t BB_tx_timing_1; /* 0x58 - 0x5c */ + volatile u_int32_t BB_tx_timing_2; /* 0x5c - 0x60 */ + volatile u_int32_t BB_tx_timing_3; /* 0x60 - 0x64 */ + volatile u_int32_t BB_xpa_timing_control; /* 0x64 - 0x68 */ + volatile char pad__2[0x18]; /* 0x68 - 0x80 */ + volatile u_int32_t BB_misc_pa_control; /* 0x80 - 0x84 */ + volatile u_int32_t BB_switch_table_chn_b0; /* 0x84 - 0x88 */ + volatile u_int32_t BB_switch_table_com1; /* 0x88 - 0x8c */ + volatile u_int32_t BB_switch_table_com2; /* 0x8c - 0x90 */ + volatile char pad__3[0x10]; /* 0x90 - 0xa0 */ + volatile u_int32_t BB_multichain_enable; /* 0xa0 - 0xa4 */ + volatile char pad__4[0x1c]; /* 0xa4 - 0xc0 */ + volatile u_int32_t BB_cal_chain_mask; /* 0xc0 - 0xc4 */ + volatile u_int32_t BB_agc_control; /* 0xc4 - 0xc8 */ + volatile u_int32_t BB_iq_adc_cal_mode; /* 0xc8 - 0xcc */ + volatile u_int32_t BB_fcal_1; /* 0xcc - 0xd0 */ + volatile u_int32_t BB_fcal_2_b0; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_dft_tone_ctrl_b0; /* 0xd4 - 0xd8 */ + volatile u_int32_t BB_cl_cal_ctrl; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_cl_map_0_b0; /* 0xdc - 0xe0 */ + volatile u_int32_t BB_cl_map_1_b0; /* 0xe0 - 0xe4 */ + volatile u_int32_t BB_cl_map_2_b0; /* 0xe4 - 0xe8 */ + volatile u_int32_t BB_cl_map_3_b0; /* 0xe8 - 0xec */ + volatile u_int32_t BB_cl_map_pal_0_b0; /* 0xec - 0xf0 */ + volatile u_int32_t BB_cl_map_pal_1_b0; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_cl_map_pal_2_b0; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_cl_map_pal_3_b0; /* 0xf8 - 0xfc */ + volatile char pad__5[0x4]; /* 0xfc - 0x100 */ + volatile u_int32_t BB_cl_tab_b0[16]; /* 0x100 - 0x140 */ + volatile u_int32_t BB_synth_control; /* 0x140 - 0x144 */ + volatile u_int32_t BB_addac_clk_select; /* 0x144 - 0x148 */ + volatile u_int32_t BB_pll_cntl; /* 0x148 - 0x14c */ + volatile u_int32_t BB_analog_swap; /* 0x14c - 0x150 */ + volatile u_int32_t BB_addac_parallel_control; /* 0x150 - 0x154 */ + volatile char pad__6[0x4]; /* 0x154 - 0x158 */ + volatile u_int32_t BB_force_analog; /* 0x158 - 0x15c */ + volatile char pad__7[0x4]; /* 0x15c - 0x160 */ + volatile u_int32_t BB_test_controls; /* 0x160 - 0x164 */ + volatile u_int32_t BB_test_controls_status; /* 0x164 - 0x168 */ + volatile u_int32_t BB_tstdac; /* 0x168 - 0x16c */ + volatile u_int32_t BB_channel_status; /* 0x16c - 0x170 */ + volatile u_int32_t BB_chaninfo_ctrl; /* 0x170 - 0x174 */ + volatile u_int32_t BB_chan_info_noise_pwr; /* 0x174 - 0x178 */ + volatile u_int32_t BB_chan_info_gain_diff; /* 0x178 - 0x17c */ + volatile u_int32_t BB_chan_info_fine_timing; /* 0x17c - 0x180 */ + volatile u_int32_t BB_chan_info_gain_b0; /* 0x180 - 0x184 */ + volatile char pad__8[0xc]; /* 0x184 - 0x190 */ + volatile u_int32_t BB_scrambler_seed; /* 0x190 - 0x194 */ + volatile u_int32_t BB_bbb_tx_ctrl; /* 0x194 - 0x198 */ + volatile u_int32_t BB_bbb_txfir_0; /* 0x198 - 0x19c */ + volatile u_int32_t BB_bbb_txfir_1; /* 0x19c - 0x1a0 */ + volatile u_int32_t BB_bbb_txfir_2; /* 0x1a0 - 0x1a4 */ + volatile u_int32_t BB_heavy_clip_ctrl; /* 0x1a4 - 0x1a8 */ + volatile u_int32_t BB_heavy_clip_20; /* 0x1a8 - 0x1ac */ + volatile u_int32_t BB_heavy_clip_40; /* 0x1ac - 0x1b0 */ + volatile u_int32_t BB_illegal_tx_rate; /* 0x1b0 - 0x1b4 */ + volatile char pad__9[0xc]; /* 0x1b4 - 0x1c0 */ + volatile u_int32_t BB_powertx_rate1; /* 0x1c0 - 0x1c4 */ + volatile u_int32_t BB_powertx_rate2; /* 0x1c4 - 0x1c8 */ + volatile u_int32_t BB_powertx_rate3; /* 0x1c8 - 0x1cc */ + volatile u_int32_t BB_powertx_rate4; /* 0x1cc - 0x1d0 */ + volatile u_int32_t BB_powertx_rate5; /* 0x1d0 - 0x1d4 */ + volatile u_int32_t BB_powertx_rate6; /* 0x1d4 - 0x1d8 */ + volatile u_int32_t BB_powertx_rate7; /* 0x1d8 - 0x1dc */ + volatile u_int32_t BB_powertx_rate8; /* 0x1dc - 0x1e0 */ + volatile u_int32_t BB_powertx_rate9; /* 0x1e0 - 0x1e4 */ + volatile u_int32_t BB_powertx_rate10; /* 0x1e4 - 0x1e8 */ + volatile u_int32_t BB_powertx_rate11; /* 0x1e8 - 0x1ec */ + volatile u_int32_t BB_powertx_rate12; /* 0x1ec - 0x1f0 */ + volatile u_int32_t BB_powertx_max; /* 0x1f0 - 0x1f4 */ + volatile u_int32_t BB_powertx_sub; /* 0x1f4 - 0x1f8 */ + volatile u_int32_t BB_tpc_1; /* 0x1f8 - 0x1fc */ + volatile u_int32_t BB_tpc_2; /* 0x1fc - 0x200 */ + volatile u_int32_t BB_tpc_3; /* 0x200 - 0x204 */ + volatile u_int32_t BB_tpc_4_b0; /* 0x204 - 0x208 */ + volatile u_int32_t BB_tpc_5_b0; /* 0x208 - 0x20c */ + volatile u_int32_t BB_tpc_6_b0; /* 0x20c - 0x210 */ + volatile u_int32_t BB_tpc_7; /* 0x210 - 0x214 */ + volatile u_int32_t BB_tpc_8; /* 0x214 - 0x218 */ + volatile u_int32_t BB_tpc_9; /* 0x218 - 0x21c */ + volatile u_int32_t BB_tpc_10; /* 0x21c - 0x220 */ + volatile u_int32_t BB_tpc_11_b0; /* 0x220 - 0x224 */ + volatile u_int32_t BB_tpc_12; /* 0x224 - 0x228 */ + volatile u_int32_t BB_tpc_13; /* 0x228 - 0x22c */ + volatile u_int32_t BB_tpc_14; /* 0x22c - 0x230 */ + volatile u_int32_t BB_tpc_15; /* 0x230 - 0x234 */ + volatile u_int32_t BB_tpc_16; /* 0x234 - 0x238 */ + volatile u_int32_t BB_tpc_17; /* 0x238 - 0x23c */ + volatile u_int32_t BB_tpc_18; /* 0x23c - 0x240 */ + volatile u_int32_t BB_tpc_19_b0; /* 0x240 - 0x244 */ + volatile u_int32_t BB_tpc_20; /* 0x244 - 0x248 */ + volatile u_int32_t BB_therm_adc_1; /* 0x248 - 0x24c */ + volatile u_int32_t BB_therm_adc_2; /* 0x24c - 0x250 */ + volatile u_int32_t BB_therm_adc_3; /* 0x250 - 0x254 */ + volatile u_int32_t BB_therm_adc_4; /* 0x254 - 0x258 */ + volatile u_int32_t BB_tx_forced_gain; /* 0x258 - 0x25c */ + volatile char pad__10[0x24]; /* 0x25c - 0x280 */ + volatile u_int32_t BB_pdadc_tab_b0[32]; /* 0x280 - 0x300 */ + volatile u_int32_t BB_tx_gain_tab_1; /* 0x300 - 0x304 */ + volatile u_int32_t BB_tx_gain_tab_2; /* 0x304 - 0x308 */ + volatile u_int32_t BB_tx_gain_tab_3; /* 0x308 - 0x30c */ + volatile u_int32_t BB_tx_gain_tab_4; /* 0x30c - 0x310 */ + volatile u_int32_t BB_tx_gain_tab_5; /* 0x310 - 0x314 */ + volatile u_int32_t BB_tx_gain_tab_6; /* 0x314 - 0x318 */ + volatile u_int32_t BB_tx_gain_tab_7; /* 0x318 - 0x31c */ + volatile u_int32_t BB_tx_gain_tab_8; /* 0x31c - 0x320 */ + volatile u_int32_t BB_tx_gain_tab_9; /* 0x320 - 0x324 */ + volatile u_int32_t BB_tx_gain_tab_10; /* 0x324 - 0x328 */ + volatile u_int32_t BB_tx_gain_tab_11; /* 0x328 - 0x32c */ + volatile u_int32_t BB_tx_gain_tab_12; /* 0x32c - 0x330 */ + volatile u_int32_t BB_tx_gain_tab_13; /* 0x330 - 0x334 */ + volatile u_int32_t BB_tx_gain_tab_14; /* 0x334 - 0x338 */ + volatile u_int32_t BB_tx_gain_tab_15; /* 0x338 - 0x33c */ + volatile u_int32_t BB_tx_gain_tab_16; /* 0x33c - 0x340 */ + volatile u_int32_t BB_tx_gain_tab_17; /* 0x340 - 0x344 */ + volatile u_int32_t BB_tx_gain_tab_18; /* 0x344 - 0x348 */ + volatile u_int32_t BB_tx_gain_tab_19; /* 0x348 - 0x34c */ + volatile u_int32_t BB_tx_gain_tab_20; /* 0x34c - 0x350 */ + volatile u_int32_t BB_tx_gain_tab_21; /* 0x350 - 0x354 */ + volatile u_int32_t BB_tx_gain_tab_22; /* 0x354 - 0x358 */ + volatile u_int32_t BB_tx_gain_tab_23; /* 0x358 - 0x35c */ + volatile u_int32_t BB_tx_gain_tab_24; /* 0x35c - 0x360 */ + volatile u_int32_t BB_tx_gain_tab_25; /* 0x360 - 0x364 */ + volatile u_int32_t BB_tx_gain_tab_26; /* 0x364 - 0x368 */ + volatile u_int32_t BB_tx_gain_tab_27; /* 0x368 - 0x36c */ + volatile u_int32_t BB_tx_gain_tab_28; /* 0x36c - 0x370 */ + volatile u_int32_t BB_tx_gain_tab_29; /* 0x370 - 0x374 */ + volatile u_int32_t BB_tx_gain_tab_30; /* 0x374 - 0x378 */ + volatile u_int32_t BB_tx_gain_tab_31; /* 0x378 - 0x37c */ + volatile u_int32_t BB_tx_gain_tab_32; /* 0x37c - 0x380 */ + volatile u_int32_t BB_rtt_ctrl; /* 0x380 - 0x384 */ + volatile u_int32_t BB_rtt_table_sw_intf_b0; /* 0x384 - 0x388 */ + volatile u_int32_t BB_rtt_table_sw_intf_1_b0; /* 0x388 - 0x38c */ + volatile char pad__11[0x74]; /* 0x38c - 0x400 */ + volatile u_int32_t BB_caltx_gain_set_0; /* 0x400 - 0x404 */ + volatile u_int32_t BB_caltx_gain_set_2; /* 0x404 - 0x408 */ + volatile u_int32_t BB_caltx_gain_set_4; /* 0x408 - 0x40c */ + volatile u_int32_t BB_caltx_gain_set_6; /* 0x40c - 0x410 */ + volatile u_int32_t BB_caltx_gain_set_8; /* 0x410 - 0x414 */ + volatile u_int32_t BB_caltx_gain_set_10; /* 0x414 - 0x418 */ + volatile u_int32_t BB_caltx_gain_set_12; /* 0x418 - 0x41c */ + volatile u_int32_t BB_caltx_gain_set_14; /* 0x41c - 0x420 */ + volatile u_int32_t BB_caltx_gain_set_16; /* 0x420 - 0x424 */ + volatile u_int32_t BB_caltx_gain_set_18; /* 0x424 - 0x428 */ + volatile u_int32_t BB_caltx_gain_set_20; /* 0x428 - 0x42c */ + volatile u_int32_t BB_caltx_gain_set_22; /* 0x42c - 0x430 */ + volatile u_int32_t BB_caltx_gain_set_24; /* 0x430 - 0x434 */ + volatile u_int32_t BB_caltx_gain_set_26; /* 0x434 - 0x438 */ + volatile u_int32_t BB_caltx_gain_set_28; /* 0x438 - 0x43c */ + volatile u_int32_t BB_caltx_gain_set_30; /* 0x43c - 0x440 */ + volatile char pad__12[0x4]; /* 0x440 - 0x444 */ + volatile u_int32_t BB_txiqcal_control_0; /* 0x444 - 0x448 */ + volatile u_int32_t BB_txiqcal_control_1; /* 0x448 - 0x44c */ + volatile u_int32_t BB_txiqcal_control_2; /* 0x44c - 0x450 */ + volatile u_int32_t BB_txiq_corr_coeff_01_b0; /* 0x450 - 0x454 */ + volatile u_int32_t BB_txiq_corr_coeff_23_b0; /* 0x454 - 0x458 */ + volatile u_int32_t BB_txiq_corr_coeff_45_b0; /* 0x458 - 0x45c */ + volatile u_int32_t BB_txiq_corr_coeff_67_b0; /* 0x45c - 0x460 */ + volatile u_int32_t BB_txiq_corr_coeff_89_b0; /* 0x460 - 0x464 */ + volatile u_int32_t BB_txiq_corr_coeff_ab_b0; /* 0x464 - 0x468 */ + volatile u_int32_t BB_txiq_corr_coeff_cd_b0; /* 0x468 - 0x46c */ + volatile u_int32_t BB_txiq_corr_coeff_ef_b0; /* 0x46c - 0x470 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_0; /* 0x470 - 0x474 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_4; /* 0x474 - 0x478 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_8; /* 0x478 - 0x47c */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_12; /* 0x47c - 0x480 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_16; /* 0x480 - 0x484 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_20; /* 0x484 - 0x488 */ + volatile u_int32_t BB_cal_rxbb_gain_tbl_24; /* 0x488 - 0x48c */ + volatile u_int32_t BB_txiqcal_status_b0; /* 0x48c - 0x490 */ + volatile u_int32_t BB_paprd_trainer_cntl1; /* 0x490 - 0x494 */ + volatile u_int32_t BB_paprd_trainer_cntl2; /* 0x494 - 0x498 */ + volatile u_int32_t BB_paprd_trainer_cntl3; /* 0x498 - 0x49c */ + volatile u_int32_t BB_paprd_trainer_cntl4; /* 0x49c - 0x4a0 */ + volatile u_int32_t BB_paprd_trainer_stat1; /* 0x4a0 - 0x4a4 */ + volatile u_int32_t BB_paprd_trainer_stat2; /* 0x4a4 - 0x4a8 */ + volatile u_int32_t BB_paprd_trainer_stat3; /* 0x4a8 - 0x4ac */ + volatile char pad__13[0x114]; /* 0x4ac - 0x5c0 */ + volatile u_int32_t BB_watchdog_status; /* 0x5c0 - 0x5c4 */ + volatile u_int32_t BB_watchdog_ctrl_1; /* 0x5c4 - 0x5c8 */ + volatile u_int32_t BB_watchdog_ctrl_2; /* 0x5c8 - 0x5cc */ + volatile u_int32_t BB_bluetooth_cntl; /* 0x5cc - 0x5d0 */ + volatile u_int32_t BB_phyonly_warm_reset; /* 0x5d0 - 0x5d4 */ + volatile u_int32_t BB_phyonly_control; /* 0x5d4 - 0x5d8 */ + volatile char pad__14[0x4]; /* 0x5d8 - 0x5dc */ + volatile u_int32_t BB_eco_ctrl; /* 0x5dc - 0x5e0 */ + volatile char pad__15[0x10]; /* 0x5e0 - 0x5f0 */ + volatile u_int32_t BB_tables_intf_addr_b0; /* 0x5f0 - 0x5f4 */ + volatile u_int32_t BB_tables_intf_data_b0; /* 0x5f4 - 0x5f8 */ +}; + +struct chn1_reg_map { + volatile char pad__0[0x30]; /* 0x0 - 0x30 */ + volatile u_int32_t BB_ext_chan_pwr_thr_2_b1; /* 0x30 - 0x34 */ + volatile char pad__1[0x74]; /* 0x34 - 0xa8 */ + volatile u_int32_t BB_spur_report_b1; /* 0xa8 - 0xac */ + volatile char pad__2[0x14]; /* 0xac - 0xc0 */ + volatile u_int32_t BB_iq_adc_meas_0_b1; /* 0xc0 - 0xc4 */ + volatile u_int32_t BB_iq_adc_meas_1_b1; /* 0xc4 - 0xc8 */ + volatile u_int32_t BB_iq_adc_meas_2_b1; /* 0xc8 - 0xcc */ + volatile u_int32_t BB_iq_adc_meas_3_b1; /* 0xcc - 0xd0 */ + volatile u_int32_t BB_tx_phase_ramp_b1; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_adc_gain_dc_corr_b1; /* 0xd4 - 0xd8 */ + volatile char pad__3[0x4]; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_rx_iq_corr_b1; /* 0xdc - 0xe0 */ + volatile char pad__4[0x10]; /* 0xe0 - 0xf0 */ + volatile u_int32_t BB_paprd_ctrl0_b1; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_paprd_ctrl1_b1; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_pa_gain123_b1; /* 0xf8 - 0xfc */ + volatile u_int32_t BB_pa_gain45_b1; /* 0xfc - 0x100 */ + volatile u_int32_t BB_paprd_pre_post_scale_0_b1; + /* 0x100 - 0x104 */ + volatile u_int32_t BB_paprd_pre_post_scale_1_b1; + /* 0x104 - 0x108 */ + volatile u_int32_t BB_paprd_pre_post_scale_2_b1; + /* 0x108 - 0x10c */ + volatile u_int32_t BB_paprd_pre_post_scale_3_b1; + /* 0x10c - 0x110 */ + volatile u_int32_t BB_paprd_pre_post_scale_4_b1; + /* 0x110 - 0x114 */ + volatile u_int32_t BB_paprd_pre_post_scale_5_b1; + /* 0x114 - 0x118 */ + volatile u_int32_t BB_paprd_pre_post_scale_6_b1; + /* 0x118 - 0x11c */ + volatile u_int32_t BB_paprd_pre_post_scale_7_b1; + /* 0x11c - 0x120 */ + volatile u_int32_t BB_paprd_mem_tab_b1[120]; /* 0x120 - 0x300 */ + volatile u_int32_t BB_chan_info_chan_tab_b1[60]; + /* 0x300 - 0x3f0 */ + volatile u_int32_t BB_chn1_tables_intf_addr; /* 0x3f0 - 0x3f4 */ + volatile u_int32_t BB_chn1_tables_intf_data; /* 0x3f4 - 0x3f8 */ +}; + +struct agc1_reg_map { + volatile char pad__0[0x4]; /* 0x0 - 0x4 */ + volatile u_int32_t BB_gain_force_max_gains_b1; /* 0x4 - 0x8 */ + volatile char pad__1[0x10]; /* 0x8 - 0x18 */ + volatile u_int32_t BB_ext_atten_switch_ctl_b1; /* 0x18 - 0x1c */ + volatile u_int32_t BB_cca_b1; /* 0x1c - 0x20 */ + volatile u_int32_t BB_cca_ctrl_2_b1; /* 0x20 - 0x24 */ + volatile char pad__2[0x15c]; /* 0x24 - 0x180 */ + volatile u_int32_t BB_rssi_b1; /* 0x180 - 0x184 */ + volatile u_int32_t BB_spur_est_cck_report_b1; /* 0x184 - 0x188 */ + volatile u_int32_t BB_agc_dig_dc_status_i_b1; /* 0x188 - 0x18c */ + volatile u_int32_t BB_agc_dig_dc_status_q_b1; /* 0x18c - 0x190 */ + volatile u_int32_t BB_dc_cal_status_b1; /* 0x190 - 0x194 */ + volatile char pad__3[0x6c]; /* 0x194 - 0x200 */ + volatile u_int32_t BB_rx_ocgain2[128]; /* 0x200 - 0x400 */ +}; + +struct sm1_reg_map { + volatile char pad__0[0x84]; /* 0x0 - 0x84 */ + volatile u_int32_t BB_switch_table_chn_b1; /* 0x84 - 0x88 */ + volatile char pad__1[0x48]; /* 0x88 - 0xd0 */ + volatile u_int32_t BB_fcal_2_b1; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_dft_tone_ctrl_b1; /* 0xd4 - 0xd8 */ + volatile char pad__2[0x4]; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_cl_map_0_b1; /* 0xdc - 0xe0 */ + volatile u_int32_t BB_cl_map_1_b1; /* 0xe0 - 0xe4 */ + volatile u_int32_t BB_cl_map_2_b1; /* 0xe4 - 0xe8 */ + volatile u_int32_t BB_cl_map_3_b1; /* 0xe8 - 0xec */ + volatile u_int32_t BB_cl_map_pal_0_b1; /* 0xec - 0xf0 */ + volatile u_int32_t BB_cl_map_pal_1_b1; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_cl_map_pal_2_b1; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_cl_map_pal_3_b1; /* 0xf8 - 0xfc */ + volatile char pad__3[0x4]; /* 0xfc - 0x100 */ + volatile u_int32_t BB_cl_tab_b1[16]; /* 0x100 - 0x140 */ + volatile char pad__4[0x40]; /* 0x140 - 0x180 */ + volatile u_int32_t BB_chan_info_gain_b1; /* 0x180 - 0x184 */ + volatile char pad__5[0x80]; /* 0x184 - 0x204 */ + volatile u_int32_t BB_tpc_4_b1; /* 0x204 - 0x208 */ + volatile u_int32_t BB_tpc_5_b1; /* 0x208 - 0x20c */ + volatile u_int32_t BB_tpc_6_b1; /* 0x20c - 0x210 */ + volatile char pad__6[0x10]; /* 0x210 - 0x220 */ + volatile u_int32_t BB_tpc_11_b1; /* 0x220 - 0x224 */ + volatile char pad__7[0x1c]; /* 0x224 - 0x240 */ + volatile u_int32_t BB_tpc_19_b1; /* 0x240 - 0x244 */ + volatile char pad__8[0x3c]; /* 0x244 - 0x280 */ + volatile u_int32_t BB_pdadc_tab_b1[32]; /* 0x280 - 0x300 */ + volatile char pad__9[0x84]; /* 0x300 - 0x384 */ + volatile u_int32_t BB_rtt_table_sw_intf_b1; /* 0x384 - 0x388 */ + volatile u_int32_t BB_rtt_table_sw_intf_1_b1; /* 0x388 - 0x38c */ + volatile char pad__10[0xc4]; /* 0x38c - 0x450 */ + volatile u_int32_t BB_txiq_corr_coeff_01_b1; /* 0x450 - 0x454 */ + volatile u_int32_t BB_txiq_corr_coeff_23_b1; /* 0x454 - 0x458 */ + volatile u_int32_t BB_txiq_corr_coeff_45_b1; /* 0x458 - 0x45c */ + volatile u_int32_t BB_txiq_corr_coeff_67_b1; /* 0x45c - 0x460 */ + volatile u_int32_t BB_txiq_corr_coeff_89_b1; /* 0x460 - 0x464 */ + volatile u_int32_t BB_txiq_corr_coeff_ab_b1; /* 0x464 - 0x468 */ + volatile u_int32_t BB_txiq_corr_coeff_cd_b1; /* 0x468 - 0x46c */ + volatile u_int32_t BB_txiq_corr_coeff_ef_b1; /* 0x46c - 0x470 */ + volatile char pad__11[0x1c]; /* 0x470 - 0x48c */ + volatile u_int32_t BB_txiqcal_status_b1; /* 0x48c - 0x490 */ + volatile char pad__12[0x160]; /* 0x490 - 0x5f0 */ + volatile u_int32_t BB_tables_intf_addr_b1; /* 0x5f0 - 0x5f4 */ + volatile u_int32_t BB_tables_intf_data_b1; /* 0x5f4 - 0x5f8 */ +}; + +struct chn2_reg_map { + volatile char pad__0[0x30]; /* 0x0 - 0x30 */ + volatile u_int32_t BB_ext_chan_pwr_thr_2_b2; /* 0x30 - 0x34 */ + volatile char pad__1[0x74]; /* 0x34 - 0xa8 */ + volatile u_int32_t BB_spur_report_b2; /* 0xa8 - 0xac */ + volatile char pad__2[0x14]; /* 0xac - 0xc0 */ + volatile u_int32_t BB_iq_adc_meas_0_b2; /* 0xc0 - 0xc4 */ + volatile u_int32_t BB_iq_adc_meas_1_b2; /* 0xc4 - 0xc8 */ + volatile u_int32_t BB_iq_adc_meas_2_b2; /* 0xc8 - 0xcc */ + volatile u_int32_t BB_iq_adc_meas_3_b2; /* 0xcc - 0xd0 */ + volatile u_int32_t BB_tx_phase_ramp_b2; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_adc_gain_dc_corr_b2; /* 0xd4 - 0xd8 */ + volatile char pad__3[0x4]; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_rx_iq_corr_b2; /* 0xdc - 0xe0 */ + volatile char pad__4[0x10]; /* 0xe0 - 0xf0 */ + volatile u_int32_t BB_paprd_ctrl0_b2; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_paprd_ctrl1_b2; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_pa_gain123_b2; /* 0xf8 - 0xfc */ + volatile u_int32_t BB_pa_gain45_b2; /* 0xfc - 0x100 */ + volatile u_int32_t BB_paprd_pre_post_scale_0_b2; + /* 0x100 - 0x104 */ + volatile u_int32_t BB_paprd_pre_post_scale_1_b2; + /* 0x104 - 0x108 */ + volatile u_int32_t BB_paprd_pre_post_scale_2_b2; + /* 0x108 - 0x10c */ + volatile u_int32_t BB_paprd_pre_post_scale_3_b2; + /* 0x10c - 0x110 */ + volatile u_int32_t BB_paprd_pre_post_scale_4_b2; + /* 0x110 - 0x114 */ + volatile u_int32_t BB_paprd_pre_post_scale_5_b2; + /* 0x114 - 0x118 */ + volatile u_int32_t BB_paprd_pre_post_scale_6_b2; + /* 0x118 - 0x11c */ + volatile u_int32_t BB_paprd_pre_post_scale_7_b2; + /* 0x11c - 0x120 */ + volatile u_int32_t BB_paprd_mem_tab_b2[120]; /* 0x120 - 0x300 */ + volatile u_int32_t BB_chan_info_chan_tab_b2[60]; + /* 0x300 - 0x3f0 */ + volatile u_int32_t BB_chn2_tables_intf_addr; /* 0x3f0 - 0x3f4 */ + volatile u_int32_t BB_chn2_tables_intf_data; /* 0x3f4 - 0x3f8 */ +}; + +struct agc2_reg_map { + volatile char pad__0[0x4]; /* 0x0 - 0x4 */ + volatile u_int32_t BB_gain_force_max_gains_b2; /* 0x4 - 0x8 */ + volatile char pad__1[0x10]; /* 0x8 - 0x18 */ + volatile u_int32_t BB_ext_atten_switch_ctl_b2; /* 0x18 - 0x1c */ + volatile u_int32_t BB_cca_b2; /* 0x1c - 0x20 */ + volatile u_int32_t BB_cca_ctrl_2_b2; /* 0x20 - 0x24 */ + volatile char pad__2[0x15c]; /* 0x24 - 0x180 */ + volatile u_int32_t BB_rssi_b2; /* 0x180 - 0x184 */ + volatile char pad__3[0x4]; /* 0x184 - 0x188 */ + volatile u_int32_t BB_agc_dig_dc_status_i_b2; /* 0x188 - 0x18c */ + volatile u_int32_t BB_agc_dig_dc_status_q_b2; /* 0x18c - 0x190 */ + volatile u_int32_t BB_dc_cal_status_b2; /* 0x190 - 0x194 */ +}; + +struct sm2_reg_map { + volatile char pad__0[0x84]; /* 0x0 - 0x84 */ + volatile u_int32_t BB_switch_table_chn_b2; /* 0x84 - 0x88 */ + volatile char pad__1[0x48]; /* 0x88 - 0xd0 */ + volatile u_int32_t BB_fcal_2_b2; /* 0xd0 - 0xd4 */ + volatile u_int32_t BB_dft_tone_ctrl_b2; /* 0xd4 - 0xd8 */ + volatile char pad__2[0x4]; /* 0xd8 - 0xdc */ + volatile u_int32_t BB_cl_map_0_b2; /* 0xdc - 0xe0 */ + volatile u_int32_t BB_cl_map_1_b2; /* 0xe0 - 0xe4 */ + volatile u_int32_t BB_cl_map_2_b2; /* 0xe4 - 0xe8 */ + volatile u_int32_t BB_cl_map_3_b2; /* 0xe8 - 0xec */ + volatile u_int32_t BB_cl_map_pal_0_b2; /* 0xec - 0xf0 */ + volatile u_int32_t BB_cl_map_pal_1_b2; /* 0xf0 - 0xf4 */ + volatile u_int32_t BB_cl_map_pal_2_b2; /* 0xf4 - 0xf8 */ + volatile u_int32_t BB_cl_map_pal_3_b2; /* 0xf8 - 0xfc */ + volatile char pad__3[0x4]; /* 0xfc - 0x100 */ + volatile u_int32_t BB_cl_tab_b2[16]; /* 0x100 - 0x140 */ + volatile char pad__4[0x40]; /* 0x140 - 0x180 */ + volatile u_int32_t BB_chan_info_gain_b2; /* 0x180 - 0x184 */ + volatile char pad__5[0x80]; /* 0x184 - 0x204 */ + volatile u_int32_t BB_tpc_4_b2; /* 0x204 - 0x208 */ + volatile u_int32_t BB_tpc_5_b2; /* 0x208 - 0x20c */ + volatile u_int32_t BB_tpc_6_b2; /* 0x20c - 0x210 */ + volatile char pad__6[0x10]; /* 0x210 - 0x220 */ + volatile u_int32_t BB_tpc_11_b2; /* 0x220 - 0x224 */ + volatile char pad__7[0x1c]; /* 0x224 - 0x240 */ + volatile u_int32_t BB_tpc_19_b2; /* 0x240 - 0x244 */ + volatile char pad__8[0x3c]; /* 0x244 - 0x280 */ + volatile u_int32_t BB_pdadc_tab_b2[32]; /* 0x280 - 0x300 */ + volatile char pad__9[0x84]; /* 0x300 - 0x384 */ + volatile u_int32_t BB_rtt_table_sw_intf_b2; /* 0x384 - 0x388 */ + volatile u_int32_t BB_rtt_table_sw_intf_1_b2; /* 0x388 - 0x38c */ + volatile char pad__10[0xc4]; /* 0x38c - 0x450 */ + volatile u_int32_t BB_txiq_corr_coeff_01_b2; /* 0x450 - 0x454 */ + volatile u_int32_t BB_txiq_corr_coeff_23_b2; /* 0x454 - 0x458 */ + volatile u_int32_t BB_txiq_corr_coeff_45_b2; /* 0x458 - 0x45c */ + volatile u_int32_t BB_txiq_corr_coeff_67_b2; /* 0x45c - 0x460 */ + volatile u_int32_t BB_txiq_corr_coeff_89_b2; /* 0x460 - 0x464 */ + volatile u_int32_t BB_txiq_corr_coeff_ab_b2; /* 0x464 - 0x468 */ + volatile u_int32_t BB_txiq_corr_coeff_cd_b2; /* 0x468 - 0x46c */ + volatile u_int32_t BB_txiq_corr_coeff_ef_b2; /* 0x46c - 0x470 */ + volatile char pad__11[0x1c]; /* 0x470 - 0x48c */ + volatile u_int32_t BB_txiqcal_status_b2; /* 0x48c - 0x490 */ + volatile char pad__12[0x160]; /* 0x490 - 0x5f0 */ + volatile u_int32_t BB_tables_intf_addr_b2; /* 0x5f0 - 0x5f4 */ + volatile u_int32_t BB_tables_intf_data_b2; /* 0x5f4 - 0x5f8 */ +}; + +struct chn3_reg_map { + volatile u_int32_t BB_dummy1[256]; /* 0x0 - 0x400 */ +}; + +struct agc3_reg_map { + volatile u_int32_t BB_dummy; /* 0x0 - 0x4 */ + volatile char pad__0[0x17c]; /* 0x4 - 0x180 */ + volatile u_int32_t BB_rssi_b3; /* 0x180 - 0x184 */ +}; + +struct sm3_reg_map { + volatile u_int32_t BB_dummy2[384]; /* 0x0 - 0x600 */ +}; + +struct bb_reg_map { + struct chn_reg_map bb_chn_reg_map; /* 0x0 - 0x3f8 */ + volatile char pad__0[0x8]; /* 0x3f8 - 0x400 */ + struct mrc_reg_map bb_mrc_reg_map; /* 0x400 - 0x424 */ + volatile char pad__1[0xdc]; /* 0x424 - 0x500 */ + struct bbb_reg_map bb_bbb_reg_map; /* 0x500 - 0x51c */ + volatile char pad__2[0xe4]; /* 0x51c - 0x600 */ + struct agc_reg_map bb_agc_reg_map; /* 0x600 - 0xa00 */ + struct sm_reg_map bb_sm_reg_map; /* 0xa00 - 0xff8 */ + volatile char pad__3[0x8]; /* 0xff8 - 0x1000 */ + struct chn1_reg_map bb_chn1_reg_map; /* 0x1000 - 0x13c8 */ + volatile char pad__4[0x238]; /* 0x13c8 - 0x1600 */ + struct agc1_reg_map bb_agc1_reg_map; /* 0x1600 - 0x19fc */ + volatile char pad__5[0x4]; /* 0x19fc - 0x1a00 */ + struct sm1_reg_map bb_sm1_reg_map; /* 0x1a00 - 0x1f74 */ + volatile char pad__6[0x8c]; /* 0x1f74 - 0x2000 */ + struct chn2_reg_map bb_chn2_reg_map; /* 0x2000 - 0x23c8 */ + volatile char pad__7[0x238]; /* 0x23c8 - 0x2600 */ + struct agc2_reg_map bb_agc2_reg_map; /* 0x2600 - 0x2790 */ + volatile char pad__8[0x270]; /* 0x2790 - 0x2a00 */ + struct sm2_reg_map bb_sm2_reg_map; /* 0x2a00 - 0x2f74 */ + volatile char pad__9[0x8c]; /* 0x2f74 - 0x3000 */ + struct chn3_reg_map bb_chn3_reg_map; /* 0x3000 - 0x3400 */ + volatile char pad__10[0x200]; /* 0x3400 - 0x3600 */ + struct agc3_reg_map bb_agc3_reg_map; /* 0x3600 - 0x3784 */ + volatile char pad__11[0x27c]; /* 0x3784 - 0x3a00 */ + struct sm3_reg_map bb_sm3_reg_map; /* 0x3a00 - 0x4000 */ +}; + +struct mac_pcu_buf_reg { + volatile u_int32_t MAC_PCU_BUF[2048]; /* 0x0 - 0x2000 */ +}; + +struct svd_reg { + volatile u_int32_t TXBF_DBG; /* 0x0 - 0x4 */ + volatile u_int32_t TXBF; /* 0x4 - 0x8 */ + volatile u_int32_t TXBF_TIMER; /* 0x8 - 0xc */ + volatile u_int32_t TXBF_SW; /* 0xc - 0x10 */ + volatile u_int32_t TXBF_SM; /* 0x10 - 0x14 */ + volatile u_int32_t TXBF1_CNTL; /* 0x14 - 0x18 */ + volatile u_int32_t TXBF2_CNTL; /* 0x18 - 0x1c */ + volatile u_int32_t TXBF3_CNTL; /* 0x1c - 0x20 */ + volatile u_int32_t TXBF4_CNTL; /* 0x20 - 0x24 */ + volatile u_int32_t TXBF5_CNTL; /* 0x24 - 0x28 */ + volatile u_int32_t TXBF6_CNTL; /* 0x28 - 0x2c */ + volatile u_int32_t TXBF7_CNTL; /* 0x2c - 0x30 */ + volatile u_int32_t TXBF8_CNTL; /* 0x30 - 0x34 */ + volatile char pad__0[0xfcc]; /* 0x34 - 0x1000 */ + volatile u_int32_t RC0[118]; /* 0x1000 - 0x11d8 */ + volatile char pad__1[0x28]; /* 0x11d8 - 0x1200 */ + volatile u_int32_t RC1[118]; /* 0x1200 - 0x13d8 */ + volatile char pad__2[0x28]; /* 0x13d8 - 0x1400 */ + volatile u_int32_t SVD_MEM0[114]; /* 0x1400 - 0x15c8 */ + volatile char pad__3[0x38]; /* 0x15c8 - 0x1600 */ + volatile u_int32_t SVD_MEM1[114]; /* 0x1600 - 0x17c8 */ + volatile char pad__4[0x38]; /* 0x17c8 - 0x1800 */ + volatile u_int32_t SVD_MEM2[114]; /* 0x1800 - 0x19c8 */ + volatile char pad__5[0x38]; /* 0x19c8 - 0x1a00 */ + volatile u_int32_t SVD_MEM3[114]; /* 0x1a00 - 0x1bc8 */ + volatile char pad__6[0x38]; /* 0x1bc8 - 0x1c00 */ + volatile u_int32_t SVD_MEM4[114]; /* 0x1c00 - 0x1dc8 */ + volatile char pad__7[0x638]; /* 0x1dc8 - 0x2400 */ + volatile u_int32_t CVCACHE[512]; /* 0x2400 - 0x2c00 */ +}; + +struct radio65_reg { + volatile u_int32_t ch0_RXRF_BIAS1; /* 0x0 - 0x4 */ + volatile u_int32_t ch0_RXRF_BIAS2; /* 0x4 - 0x8 */ + volatile u_int32_t ch0_RXRF_GAINSTAGES; /* 0x8 - 0xc */ + volatile u_int32_t ch0_RXRF_AGC; /* 0xc - 0x10 */ + volatile char pad__0[0x30]; /* 0x10 - 0x40 */ + volatile u_int32_t ch0_TXRF1; /* 0x40 - 0x44 */ + volatile u_int32_t ch0_TXRF2; /* 0x44 - 0x48 */ + volatile u_int32_t ch0_TXRF3; /* 0x48 - 0x4c */ + volatile u_int32_t ch0_TXRF4; /* 0x4c - 0x50 */ + volatile u_int32_t ch0_TXRF5; /* 0x50 - 0x54 */ + volatile u_int32_t ch0_TXRF6; /* 0x54 - 0x58 */ + volatile char pad__1[0x28]; /* 0x58 - 0x80 */ + volatile u_int32_t ch0_SYNTH1; /* 0x80 - 0x84 */ + volatile u_int32_t ch0_SYNTH2; /* 0x84 - 0x88 */ + volatile u_int32_t ch0_SYNTH3; /* 0x88 - 0x8c */ + volatile u_int32_t ch0_SYNTH4; /* 0x8c - 0x90 */ + volatile u_int32_t ch0_SYNTH5; /* 0x90 - 0x94 */ + volatile u_int32_t ch0_SYNTH6; /* 0x94 - 0x98 */ + volatile u_int32_t ch0_SYNTH7; /* 0x98 - 0x9c */ + volatile u_int32_t ch0_SYNTH8; /* 0x9c - 0xa0 */ + volatile u_int32_t ch0_SYNTH9; /* 0xa0 - 0xa4 */ + volatile u_int32_t ch0_SYNTH10; /* 0xa4 - 0xa8 */ + volatile u_int32_t ch0_SYNTH11; /* 0xa8 - 0xac */ + volatile u_int32_t ch0_SYNTH12; /* 0xac - 0xb0 */ + volatile u_int32_t ch0_SYNTH13; /* 0xb0 - 0xb4 */ + volatile u_int32_t ch0_SYNTH14; /* 0xb4 - 0xb8 */ + volatile char pad__2[0x8]; /* 0xb8 - 0xc0 */ + volatile u_int32_t ch0_BIAS1; /* 0xc0 - 0xc4 */ + volatile u_int32_t ch0_BIAS2; /* 0xc4 - 0xc8 */ + volatile u_int32_t ch0_BIAS3; /* 0xc8 - 0xcc */ + volatile u_int32_t ch0_BIAS4; /* 0xcc - 0xd0 */ + volatile char pad__3[0x30]; /* 0xd0 - 0x100 */ + volatile u_int32_t ch0_RXTX1; /* 0x100 - 0x104 */ + volatile u_int32_t ch0_RXTX2; /* 0x104 - 0x108 */ + volatile u_int32_t ch0_RXTX3; /* 0x108 - 0x10c */ + volatile u_int32_t ch0_RXTX4; /* 0x10c - 0x110 */ + volatile char pad__4[0x30]; /* 0x110 - 0x140 */ + volatile u_int32_t ch0_BB1; /* 0x140 - 0x144 */ + volatile u_int32_t ch0_BB2; /* 0x144 - 0x148 */ + volatile u_int32_t ch0_BB3; /* 0x148 - 0x14c */ + volatile char pad__5[0x34]; /* 0x14c - 0x180 */ + volatile u_int32_t ch0_BB_PLL; /* 0x180 - 0x184 */ + volatile u_int32_t ch0_BB_PLL2; /* 0x184 - 0x188 */ + volatile u_int32_t ch0_BB_PLL3; /* 0x188 - 0x18c */ + volatile u_int32_t ch0_BB_PLL4; /* 0x18c - 0x190 */ + volatile char pad__6[0x30]; /* 0x190 - 0x1c0 */ + volatile u_int32_t ch0_CPU_PLL; /* 0x1c0 - 0x1c4 */ + volatile u_int32_t ch0_CPU_PLL2; /* 0x1c4 - 0x1c8 */ + volatile u_int32_t ch0_CPU_PLL3; /* 0x1c8 - 0x1cc */ + volatile u_int32_t ch0_CPU_PLL4; /* 0x1cc - 0x1d0 */ + volatile char pad__7[0x30]; /* 0x1d0 - 0x200 */ + volatile u_int32_t ch0_AUDIO_PLL; /* 0x200 - 0x204 */ + volatile u_int32_t ch0_AUDIO_PLL2; /* 0x204 - 0x208 */ + volatile u_int32_t ch0_AUDIO_PLL3; /* 0x208 - 0x20c */ + volatile u_int32_t ch0_AUDIO_PLL4; /* 0x20c - 0x210 */ + volatile char pad__8[0x30]; /* 0x210 - 0x240 */ + volatile u_int32_t ch0_DDR_PLL; /* 0x240 - 0x244 */ + volatile u_int32_t ch0_DDR_PLL2; /* 0x244 - 0x248 */ + volatile u_int32_t ch0_DDR_PLL3; /* 0x248 - 0x24c */ + volatile u_int32_t ch0_DDR_PLL4; /* 0x24c - 0x250 */ + volatile char pad__9[0x30]; /* 0x250 - 0x280 */ + volatile u_int32_t ch0_TOP; /* 0x280 - 0x284 */ + volatile u_int32_t ch0_TOP2; /* 0x284 - 0x288 */ + volatile u_int32_t ch0_TOP3; /* 0x288 - 0x28c */ + volatile u_int32_t ch0_THERM; /* 0x28c - 0x290 */ + volatile u_int32_t ch0_XTAL; /* 0x290 - 0x294 */ + volatile char pad__10[0xec]; /* 0x294 - 0x380 */ + volatile u_int32_t ch0_rbist_cntrl; /* 0x380 - 0x384 */ + volatile u_int32_t ch0_tx_dc_offset; /* 0x384 - 0x388 */ + volatile u_int32_t ch0_tx_tonegen0; /* 0x388 - 0x38c */ + volatile u_int32_t ch0_tx_tonegen1; /* 0x38c - 0x390 */ + volatile u_int32_t ch0_tx_lftonegen0; /* 0x390 - 0x394 */ + volatile u_int32_t ch0_tx_linear_ramp_i; /* 0x394 - 0x398 */ + volatile u_int32_t ch0_tx_linear_ramp_q; /* 0x398 - 0x39c */ + volatile u_int32_t ch0_tx_prbs_mag; /* 0x39c - 0x3a0 */ + volatile u_int32_t ch0_tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */ + volatile u_int32_t ch0_tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */ + volatile u_int32_t ch0_cmac_dc_cancel; /* 0x3a8 - 0x3ac */ + volatile u_int32_t ch0_cmac_dc_offset; /* 0x3ac - 0x3b0 */ + volatile u_int32_t ch0_cmac_corr; /* 0x3b0 - 0x3b4 */ + volatile u_int32_t ch0_cmac_power; /* 0x3b4 - 0x3b8 */ + volatile u_int32_t ch0_cmac_cross_corr; /* 0x3b8 - 0x3bc */ + volatile u_int32_t ch0_cmac_i2q2; /* 0x3bc - 0x3c0 */ + volatile u_int32_t ch0_cmac_power_hpf; /* 0x3c0 - 0x3c4 */ + volatile u_int32_t ch0_rxdac_set1; /* 0x3c4 - 0x3c8 */ + volatile u_int32_t ch0_rxdac_set2; /* 0x3c8 - 0x3cc */ + volatile u_int32_t ch0_rxdac_long_shift; /* 0x3cc - 0x3d0 */ + volatile u_int32_t ch0_cmac_results_i; /* 0x3d0 - 0x3d4 */ + volatile u_int32_t ch0_cmac_results_q; /* 0x3d4 - 0x3d8 */ + volatile char pad__11[0x28]; /* 0x3d8 - 0x400 */ + volatile u_int32_t ch1_RXRF_BIAS1; /* 0x400 - 0x404 */ + volatile u_int32_t ch1_RXRF_BIAS2; /* 0x404 - 0x408 */ + volatile u_int32_t ch1_RXRF_GAINSTAGES; /* 0x408 - 0x40c */ + volatile u_int32_t ch1_RXRF_AGC; /* 0x40c - 0x410 */ + volatile char pad__12[0x30]; /* 0x410 - 0x440 */ + volatile u_int32_t ch1_TXRF1; /* 0x440 - 0x444 */ + volatile u_int32_t ch1_TXRF2; /* 0x444 - 0x448 */ + volatile u_int32_t ch1_TXRF3; /* 0x448 - 0x44c */ + volatile u_int32_t ch1_TXRF4; /* 0x44c - 0x450 */ + volatile u_int32_t ch1_TXRF5; /* 0x450 - 0x454 */ + volatile u_int32_t ch1_TXRF6; /* 0x454 - 0x458 */ + volatile char pad__13[0xa8]; /* 0x458 - 0x500 */ + volatile u_int32_t ch1_RXTX1; /* 0x500 - 0x504 */ + volatile u_int32_t ch1_RXTX2; /* 0x504 - 0x508 */ + volatile u_int32_t ch1_RXTX3; /* 0x508 - 0x50c */ + volatile u_int32_t ch1_RXTX4; /* 0x50c - 0x510 */ + volatile char pad__14[0x30]; /* 0x510 - 0x540 */ + volatile u_int32_t ch1_BB1; /* 0x540 - 0x544 */ + volatile u_int32_t ch1_BB2; /* 0x544 - 0x548 */ + volatile u_int32_t ch1_BB3; /* 0x548 - 0x54c */ + volatile char pad__15[0x234]; /* 0x54c - 0x780 */ + volatile u_int32_t ch1_rbist_cntrl; /* 0x780 - 0x784 */ + volatile u_int32_t ch1_tx_dc_offset; /* 0x784 - 0x788 */ + volatile u_int32_t ch1_tx_tonegen0; /* 0x788 - 0x78c */ + volatile u_int32_t ch1_tx_tonegen1; /* 0x78c - 0x790 */ + volatile u_int32_t ch1_tx_lftonegen0; /* 0x790 - 0x794 */ + volatile u_int32_t ch1_tx_linear_ramp_i; /* 0x794 - 0x798 */ + volatile u_int32_t ch1_tx_linear_ramp_q; /* 0x798 - 0x79c */ + volatile u_int32_t ch1_tx_prbs_mag; /* 0x79c - 0x7a0 */ + volatile u_int32_t ch1_tx_prbs_seed_i; /* 0x7a0 - 0x7a4 */ + volatile u_int32_t ch1_tx_prbs_seed_q; /* 0x7a4 - 0x7a8 */ + volatile u_int32_t ch1_cmac_dc_cancel; /* 0x7a8 - 0x7ac */ + volatile u_int32_t ch1_cmac_dc_offset; /* 0x7ac - 0x7b0 */ + volatile u_int32_t ch1_cmac_corr; /* 0x7b0 - 0x7b4 */ + volatile u_int32_t ch1_cmac_power; /* 0x7b4 - 0x7b8 */ + volatile u_int32_t ch1_cmac_cross_corr; /* 0x7b8 - 0x7bc */ + volatile u_int32_t ch1_cmac_i2q2; /* 0x7bc - 0x7c0 */ + volatile u_int32_t ch1_cmac_power_hpf; /* 0x7c0 - 0x7c4 */ + volatile u_int32_t ch1_rxdac_set1; /* 0x7c4 - 0x7c8 */ + volatile u_int32_t ch1_rxdac_set2; /* 0x7c8 - 0x7cc */ + volatile u_int32_t ch1_rxdac_long_shift; /* 0x7cc - 0x7d0 */ + volatile u_int32_t ch1_cmac_results_i; /* 0x7d0 - 0x7d4 */ + volatile u_int32_t ch1_cmac_results_q; /* 0x7d4 - 0x7d8 */ + volatile char pad__16[0x28]; /* 0x7d8 - 0x800 */ + volatile u_int32_t ch2_RXRF_BIAS1; /* 0x800 - 0x804 */ + volatile u_int32_t ch2_RXRF_BIAS2; /* 0x804 - 0x808 */ + volatile u_int32_t ch2_RXRF_GAINSTAGES; /* 0x808 - 0x80c */ + volatile u_int32_t ch2_RXRF_AGC; /* 0x80c - 0x810 */ + volatile char pad__17[0x30]; /* 0x810 - 0x840 */ + volatile u_int32_t ch2_TXRF1; /* 0x840 - 0x844 */ + volatile u_int32_t ch2_TXRF2; /* 0x844 - 0x848 */ + volatile u_int32_t ch2_TXRF3; /* 0x848 - 0x84c */ + volatile u_int32_t ch2_TXRF4; /* 0x84c - 0x850 */ + volatile u_int32_t ch2_TXRF5; /* 0x850 - 0x854 */ + volatile u_int32_t ch2_TXRF6; /* 0x854 - 0x858 */ + volatile char pad__18[0xa8]; /* 0x858 - 0x900 */ + volatile u_int32_t ch2_RXTX1; /* 0x900 - 0x904 */ + volatile u_int32_t ch2_RXTX2; /* 0x904 - 0x908 */ + volatile u_int32_t ch2_RXTX3; /* 0x908 - 0x90c */ + volatile u_int32_t ch2_RXTX4; /* 0x90c - 0x910 */ + volatile char pad__19[0x30]; /* 0x910 - 0x940 */ + volatile u_int32_t ch2_BB1; /* 0x940 - 0x944 */ + volatile u_int32_t ch2_BB2; /* 0x944 - 0x948 */ + volatile u_int32_t ch2_BB3; /* 0x948 - 0x94c */ + volatile char pad__20[0x234]; /* 0x94c - 0xb80 */ + volatile u_int32_t ch2_rbist_cntrl; /* 0xb80 - 0xb84 */ + volatile u_int32_t ch2_tx_dc_offset; /* 0xb84 - 0xb88 */ + volatile u_int32_t ch2_tx_tonegen0; /* 0xb88 - 0xb8c */ + volatile u_int32_t ch2_tx_tonegen1; /* 0xb8c - 0xb90 */ + volatile u_int32_t ch2_tx_lftonegen0; /* 0xb90 - 0xb94 */ + volatile u_int32_t ch2_tx_linear_ramp_i; /* 0xb94 - 0xb98 */ + volatile u_int32_t ch2_tx_linear_ramp_q; /* 0xb98 - 0xb9c */ + volatile u_int32_t ch2_tx_prbs_mag; /* 0xb9c - 0xba0 */ + volatile u_int32_t ch2_tx_prbs_seed_i; /* 0xba0 - 0xba4 */ + volatile u_int32_t ch2_tx_prbs_seed_q; /* 0xba4 - 0xba8 */ + volatile u_int32_t ch2_cmac_dc_cancel; /* 0xba8 - 0xbac */ + volatile u_int32_t ch2_cmac_dc_offset; /* 0xbac - 0xbb0 */ + volatile u_int32_t ch2_cmac_corr; /* 0xbb0 - 0xbb4 */ + volatile u_int32_t ch2_cmac_power; /* 0xbb4 - 0xbb8 */ + volatile u_int32_t ch2_cmac_cross_corr; /* 0xbb8 - 0xbbc */ + volatile u_int32_t ch2_cmac_i2q2; /* 0xbbc - 0xbc0 */ + volatile u_int32_t ch2_cmac_power_hpf; /* 0xbc0 - 0xbc4 */ + volatile u_int32_t ch2_rxdac_set1; /* 0xbc4 - 0xbc8 */ + volatile u_int32_t ch2_rxdac_set2; /* 0xbc8 - 0xbcc */ + volatile u_int32_t ch2_rxdac_long_shift; /* 0xbcc - 0xbd0 */ + volatile u_int32_t ch2_cmac_results_i; /* 0xbd0 - 0xbd4 */ + volatile u_int32_t ch2_cmac_results_q; /* 0xbd4 - 0xbd8 */ +}; + +struct scorpion_reg_map { + struct mac_dma_reg mac_dma_reg_map; /* 0x0 - 0x128 */ + volatile char pad__0[0x6d8]; /* 0x128 - 0x800 */ + struct mac_qcu_reg mac_qcu_reg_map; /* 0x800 - 0xa48 */ + volatile char pad__1[0x5b8]; /* 0xa48 - 0x1000 */ + struct mac_dcu_reg mac_dcu_reg_map; /* 0x1000 - 0x1f08 */ + volatile char pad__2[0x50f8]; /* 0x1f08 - 0x7000 */ + struct rtc_reg rtc_reg_map; /* 0x7000 - 0x7040 */ + struct rtc_sync_reg rtc_sync_reg_map; /* 0x7040 - 0x705c */ + volatile char pad__3[0xfa4]; /* 0x705c - 0x8000 */ + struct mac_pcu_reg mac_pcu_reg_map; /* 0x8000 - 0x9800 */ + struct bb_reg_map bb_reg_map; /* 0x9800 - 0xd800 */ + volatile char pad__4[0x800]; /* 0xd800 - 0xe000 */ + struct mac_pcu_buf_reg mac_pcu_buf_reg_map; /* 0xe000 - 0x10000 */ + struct svd_reg svd_reg_map; /* 0x10000 - 0x12c00 */ + volatile char pad__5[0x3400]; /* 0x12c00 - 0x16000 */ + struct radio65_reg radio65_reg_map; /* 0x16000 - 0x16bd8 */ +}; + +#endif /* __REG_SCORPION_REG_MAP_H__ */ diff --git a/hal/ar9300/scorpion_reg_map_macro.h b/hal/ar9300/scorpion_reg_map_macro.h new file mode 100644 index 000000000000..4adea9232219 --- /dev/null +++ b/hal/ar9300/scorpion_reg_map_macro.h @@ -0,0 +1,66519 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/* */ +/* File: /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg_map_macro.h*/ +/* Creator: irshad */ +/* Time: Wednesday Feb 15, 2012 [5:06:37 pm] */ +/* */ +/* Path: /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/ +/* Arguments: /cad/denali/blueprint/3.7.3//Linux-64bit/blueprint -dump */ +/* -codegen */ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.codegen*/ +/* -ath_ansic -Wdesc -I */ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/ +/* -I /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint */ +/* -I */ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint*/ +/* -I */ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig*/ +/* -odir */ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/ +/* -eval {$INCLUDE_SYSCONFIG_FILES=1} -eval */ +/* $WAR_EV58615_for_ansic_codegen=1 scorpion_reg.rdl */ +/* */ +/* Sources: /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/rtc/rtc_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/wmac_wrap/rtc_sync_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_radio_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/bb/blueprint/bb_reg_map.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/svd/svd_reg.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl*/ +/* /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.pm*/ +/* /cad/local/lib/perl/Pinfo.pm */ +/* */ +/* Blueprint: 3.7.3 (Fri Aug 29 12:39:16 PDT 2008) */ +/* Machine: rupavathi.users.atheros.com */ +/* OS: Linux 2.6.9-89.ELsmp */ +/* Description: */ +/* */ +/*This Register Map contains the complete register set for scorpion. */ +/* */ +/* Copyright (C) 2012 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ +/* */ + + +#ifndef __REG_SCORPION_REG_MAP_MACRO_H__ +#define __REG_SCORPION_REG_MAP_MACRO_H__ + + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_CR */ +#ifndef __MAC_DMA_CR_MACRO__ +#define __MAC_DMA_CR_MACRO__ + +/* macros for field RXE_LP */ +#define MAC_DMA_CR__RXE_LP__SHIFT 2 +#define MAC_DMA_CR__RXE_LP__WIDTH 1 +#define MAC_DMA_CR__RXE_LP__MASK 0x00000004U +#define MAC_DMA_CR__RXE_LP__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define MAC_DMA_CR__RXE_LP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_DMA_CR__RXE_LP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field RXE_HP */ +#define MAC_DMA_CR__RXE_HP__SHIFT 3 +#define MAC_DMA_CR__RXE_HP__WIDTH 1 +#define MAC_DMA_CR__RXE_HP__MASK 0x00000008U +#define MAC_DMA_CR__RXE_HP__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define MAC_DMA_CR__RXE_HP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_DMA_CR__RXE_HP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field RXD */ +#define MAC_DMA_CR__RXD__SHIFT 5 +#define MAC_DMA_CR__RXD__WIDTH 1 +#define MAC_DMA_CR__RXD__MASK 0x00000020U +#define MAC_DMA_CR__RXD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define MAC_DMA_CR__RXD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) +#define MAC_DMA_CR__RXD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_DMA_CR__RXD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_DMA_CR__RXD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_DMA_CR__RXD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field SWI */ +#define MAC_DMA_CR__SWI__SHIFT 6 +#define MAC_DMA_CR__SWI__WIDTH 1 +#define MAC_DMA_CR__SWI__MASK 0x00000040U +#define MAC_DMA_CR__SWI__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define MAC_DMA_CR__SWI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_DMA_CR__SWI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field SPARE */ +#define MAC_DMA_CR__SPARE__SHIFT 7 +#define MAC_DMA_CR__SPARE__WIDTH 4 +#define MAC_DMA_CR__SPARE__MASK 0x00000780U +#define MAC_DMA_CR__SPARE__READ(src) (((u_int32_t)(src) & 0x00000780U) >> 7) +#define MAC_DMA_CR__SPARE__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000780U) +#define MAC_DMA_CR__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000780U) | (((u_int32_t)(src) <<\ + 7) & 0x00000780U) +#define MAC_DMA_CR__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000780U))) +#define MAC_DMA_CR__TYPE u_int32_t +#define MAC_DMA_CR__READ 0x000007ecU +#define MAC_DMA_CR__WRITE 0x000007ecU + +#endif /* __MAC_DMA_CR_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_CR */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_CR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_CFG */ +#ifndef __MAC_DMA_CFG_MACRO__ +#define __MAC_DMA_CFG_MACRO__ + +/* macros for field BE_MODE_XMIT_DESC */ +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__SHIFT 0 +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WIDTH 1 +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MASK 0x00000001U +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field BE_MODE_XMIT_DATA */ +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__SHIFT 1 +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WIDTH 1 +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MASK 0x00000002U +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field BE_MODE_RCV_DESC */ +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__SHIFT 2 +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__WIDTH 1 +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__MASK 0x00000004U +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_DMA_CFG__BE_MODE_RCV_DESC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field BE_MODE_RCV_DATA */ +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__SHIFT 3 +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__WIDTH 1 +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__MASK 0x00000008U +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_DMA_CFG__BE_MODE_RCV_DATA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BE_MODE_MMR */ +#define MAC_DMA_CFG__BE_MODE_MMR__SHIFT 4 +#define MAC_DMA_CFG__BE_MODE_MMR__WIDTH 1 +#define MAC_DMA_CFG__BE_MODE_MMR__MASK 0x00000010U +#define MAC_DMA_CFG__BE_MODE_MMR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_DMA_CFG__BE_MODE_MMR__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_DMA_CFG__BE_MODE_MMR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_DMA_CFG__BE_MODE_MMR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_DMA_CFG__BE_MODE_MMR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_DMA_CFG__BE_MODE_MMR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field ADHOC */ +#define MAC_DMA_CFG__ADHOC__SHIFT 5 +#define MAC_DMA_CFG__ADHOC__WIDTH 1 +#define MAC_DMA_CFG__ADHOC__MASK 0x00000020U +#define MAC_DMA_CFG__ADHOC__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define MAC_DMA_CFG__ADHOC__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) +#define MAC_DMA_CFG__ADHOC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_DMA_CFG__ADHOC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_DMA_CFG__ADHOC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_DMA_CFG__ADHOC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field PHY_OK */ +#define MAC_DMA_CFG__PHY_OK__SHIFT 8 +#define MAC_DMA_CFG__PHY_OK__WIDTH 1 +#define MAC_DMA_CFG__PHY_OK__MASK 0x00000100U +#define MAC_DMA_CFG__PHY_OK__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define MAC_DMA_CFG__PHY_OK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_DMA_CFG__PHY_OK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field EEPROM_BUSY */ +#define MAC_DMA_CFG__EEPROM_BUSY__SHIFT 9 +#define MAC_DMA_CFG__EEPROM_BUSY__WIDTH 1 +#define MAC_DMA_CFG__EEPROM_BUSY__MASK 0x00000200U +#define MAC_DMA_CFG__EEPROM_BUSY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_DMA_CFG__EEPROM_BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_DMA_CFG__EEPROM_BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field CLKGATE_DIS */ +#define MAC_DMA_CFG__CLKGATE_DIS__SHIFT 10 +#define MAC_DMA_CFG__CLKGATE_DIS__WIDTH 1 +#define MAC_DMA_CFG__CLKGATE_DIS__MASK 0x00000400U +#define MAC_DMA_CFG__CLKGATE_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_DMA_CFG__CLKGATE_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_DMA_CFG__CLKGATE_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_DMA_CFG__CLKGATE_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_DMA_CFG__CLKGATE_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_DMA_CFG__CLKGATE_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field HALT_REQ */ +#define MAC_DMA_CFG__HALT_REQ__SHIFT 11 +#define MAC_DMA_CFG__HALT_REQ__WIDTH 1 +#define MAC_DMA_CFG__HALT_REQ__MASK 0x00000800U +#define MAC_DMA_CFG__HALT_REQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_DMA_CFG__HALT_REQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_DMA_CFG__HALT_REQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_DMA_CFG__HALT_REQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_DMA_CFG__HALT_REQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_DMA_CFG__HALT_REQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field HALT_ACK */ +#define MAC_DMA_CFG__HALT_ACK__SHIFT 12 +#define MAC_DMA_CFG__HALT_ACK__WIDTH 1 +#define MAC_DMA_CFG__HALT_ACK__MASK 0x00001000U +#define MAC_DMA_CFG__HALT_ACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_DMA_CFG__HALT_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_DMA_CFG__HALT_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field REQ_Q_FULL_THRESHOLD */ +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__SHIFT 17 +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WIDTH 2 +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MASK 0x00060000U +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00060000U) >> 17) +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00060000U) +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((u_int32_t)(src) <<\ + 17) & 0x00060000U) +#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00060000U))) + +/* macros for field MISSING_TX_INTR_FIX_ENABLE */ +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__SHIFT 19 +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WIDTH 1 +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MASK 0x00080000U +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field LEGACY_INT_MIT_MODE_ENABLE */ +#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__SHIFT 20 +#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__WIDTH 1 +#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__MASK 0x00100000U +#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field RESET_INT_MIT_CNTRS */ +#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__SHIFT 21 +#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__WIDTH 1 +#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__MASK 0x00200000U +#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) +#define MAC_DMA_CFG__TYPE u_int32_t +#define MAC_DMA_CFG__READ 0x003e1f3fU +#define MAC_DMA_CFG__WRITE 0x003e1f3fU + +#endif /* __MAC_DMA_CFG_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_CFG */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_CFG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXBUFPTR_THRESH */ +#ifndef __MAC_DMA_RXBUFPTR_THRESH_MACRO__ +#define __MAC_DMA_RXBUFPTR_THRESH_MACRO__ + +/* macros for field HP_DATA */ +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__SHIFT 0 +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WIDTH 4 +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MASK 0x0000000fU +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field LP_DATA */ +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__SHIFT 8 +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WIDTH 7 +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MASK 0x00007f00U +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007f00U) >> 8) +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00007f00U) +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00007f00U) +#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00007f00U))) +#define MAC_DMA_RXBUFPTR_THRESH__TYPE u_int32_t +#define MAC_DMA_RXBUFPTR_THRESH__READ 0x00007f0fU +#define MAC_DMA_RXBUFPTR_THRESH__WRITE 0x00007f0fU + +#endif /* __MAC_DMA_RXBUFPTR_THRESH_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_RXBUFPTR_THRESH */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXBUFPTR_THRESH__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXDPPTR_THRESH */ +#ifndef __MAC_DMA_TXDPPTR_THRESH_MACRO__ +#define __MAC_DMA_TXDPPTR_THRESH_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_TXDPPTR_THRESH__DATA__SHIFT 0 +#define MAC_DMA_TXDPPTR_THRESH__DATA__WIDTH 4 +#define MAC_DMA_TXDPPTR_THRESH__DATA__MASK 0x0000000fU +#define MAC_DMA_TXDPPTR_THRESH__DATA__READ(src) (u_int32_t)(src) & 0x0000000fU +#define MAC_DMA_TXDPPTR_THRESH__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_DMA_TXDPPTR_THRESH__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_DMA_TXDPPTR_THRESH__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define MAC_DMA_TXDPPTR_THRESH__TYPE u_int32_t +#define MAC_DMA_TXDPPTR_THRESH__READ 0x0000000fU +#define MAC_DMA_TXDPPTR_THRESH__WRITE 0x0000000fU + +#endif /* __MAC_DMA_TXDPPTR_THRESH_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TXDPPTR_THRESH */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TXDPPTR_THRESH__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_MIRT */ +#ifndef __MAC_DMA_MIRT_MACRO__ +#define __MAC_DMA_MIRT_MACRO__ + +/* macros for field RATE_THRESH */ +#define MAC_DMA_MIRT__RATE_THRESH__SHIFT 0 +#define MAC_DMA_MIRT__RATE_THRESH__WIDTH 16 +#define MAC_DMA_MIRT__RATE_THRESH__MASK 0x0000ffffU +#define MAC_DMA_MIRT__RATE_THRESH__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_DMA_MIRT__RATE_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_DMA_MIRT__RATE_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_MIRT__RATE_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DMA_MIRT__TYPE u_int32_t +#define MAC_DMA_MIRT__READ 0x0000ffffU +#define MAC_DMA_MIRT__WRITE 0x0000ffffU + +#endif /* __MAC_DMA_MIRT_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_MIRT */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_MIRT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_GLOBAL_IER */ +#ifndef __MAC_DMA_GLOBAL_IER_MACRO__ +#define __MAC_DMA_GLOBAL_IER_MACRO__ + +/* macros for field ENABLE */ +#define MAC_DMA_GLOBAL_IER__ENABLE__SHIFT 0 +#define MAC_DMA_GLOBAL_IER__ENABLE__WIDTH 1 +#define MAC_DMA_GLOBAL_IER__ENABLE__MASK 0x00000001U +#define MAC_DMA_GLOBAL_IER__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_DMA_GLOBAL_IER__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_DMA_GLOBAL_IER__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_DMA_GLOBAL_IER__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_DMA_GLOBAL_IER__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DMA_GLOBAL_IER__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define MAC_DMA_GLOBAL_IER__TYPE u_int32_t +#define MAC_DMA_GLOBAL_IER__READ 0x00000001U +#define MAC_DMA_GLOBAL_IER__WRITE 0x00000001U + +#endif /* __MAC_DMA_GLOBAL_IER_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_GLOBAL_IER */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_GLOBAL_IER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_alias */ +#ifndef __MAC_DMA_TIMT_ALIAS_MACRO__ +#define __MAC_DMA_TIMT_ALIAS_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT_ALIAS__TYPE u_int32_t +#define MAC_DMA_TIMT_ALIAS__READ 0xffffffffU +#define MAC_DMA_TIMT_ALIAS__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_ALIAS_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TIMT */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RIMT */ +#ifndef __MAC_DMA_RIMT_MACRO__ +#define __MAC_DMA_RIMT_MACRO__ + +/* macros for field RX_LAST_PKT_THRESH */ +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field RX_FIRST_PKT_THRESH */ +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_RIMT__TYPE u_int32_t +#define MAC_DMA_RIMT__READ 0xffffffffU +#define MAC_DMA_RIMT__WRITE 0xffffffffU + +#endif /* __MAC_DMA_RIMT_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_RIMT */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_RIMT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXCFG */ +#ifndef __MAC_DMA_TXCFG_MACRO__ +#define __MAC_DMA_TXCFG_MACRO__ + +/* macros for field DMA_SIZE */ +#define MAC_DMA_TXCFG__DMA_SIZE__SHIFT 0 +#define MAC_DMA_TXCFG__DMA_SIZE__WIDTH 3 +#define MAC_DMA_TXCFG__DMA_SIZE__MASK 0x00000007U +#define MAC_DMA_TXCFG__DMA_SIZE__READ(src) (u_int32_t)(src) & 0x00000007U +#define MAC_DMA_TXCFG__DMA_SIZE__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define MAC_DMA_TXCFG__DMA_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MAC_DMA_TXCFG__DMA_SIZE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field TRIGLVL */ +#define MAC_DMA_TXCFG__TRIGLVL__SHIFT 4 +#define MAC_DMA_TXCFG__TRIGLVL__WIDTH 6 +#define MAC_DMA_TXCFG__TRIGLVL__MASK 0x000003f0U +#define MAC_DMA_TXCFG__TRIGLVL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define MAC_DMA_TXCFG__TRIGLVL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define MAC_DMA_TXCFG__TRIGLVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define MAC_DMA_TXCFG__TRIGLVL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field JUMBO_EN */ +#define MAC_DMA_TXCFG__JUMBO_EN__SHIFT 10 +#define MAC_DMA_TXCFG__JUMBO_EN__WIDTH 1 +#define MAC_DMA_TXCFG__JUMBO_EN__MASK 0x00000400U +#define MAC_DMA_TXCFG__JUMBO_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_DMA_TXCFG__JUMBO_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_DMA_TXCFG__JUMBO_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_DMA_TXCFG__JUMBO_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_DMA_TXCFG__JUMBO_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_DMA_TXCFG__JUMBO_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field BCN_PAST_ATIM_DIS */ +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__SHIFT 11 +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WIDTH 1 +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MASK 0x00000800U +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field ATIM_DEFER_DIS */ +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__SHIFT 12 +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WIDTH 1 +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MASK 0x00001000U +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field RTCI_DIS */ +#define MAC_DMA_TXCFG__RTCI_DIS__SHIFT 14 +#define MAC_DMA_TXCFG__RTCI_DIS__WIDTH 1 +#define MAC_DMA_TXCFG__RTCI_DIS__MASK 0x00004000U +#define MAC_DMA_TXCFG__RTCI_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define MAC_DMA_TXCFG__RTCI_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define MAC_DMA_TXCFG__RTCI_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define MAC_DMA_TXCFG__RTCI_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define MAC_DMA_TXCFG__RTCI_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define MAC_DMA_TXCFG__RTCI_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field DIS_RETRY_UNDERRUN */ +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__SHIFT 17 +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WIDTH 1 +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MASK 0x00020000U +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field DIS_CW_INC_QUIET_COLL */ +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__SHIFT 18 +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WIDTH 1 +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MASK 0x00040000U +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field RTS_FAIL_EXCESSIVE_RETRIES */ +#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__SHIFT 19 +#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__WIDTH 1 +#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__MASK 0x00080000U +#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) +#define MAC_DMA_TXCFG__TYPE u_int32_t +#define MAC_DMA_TXCFG__READ 0x000e5ff7U +#define MAC_DMA_TXCFG__WRITE 0x000e5ff7U + +#endif /* __MAC_DMA_TXCFG_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TXCFG */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TXCFG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXCFG */ +#ifndef __MAC_DMA_RXCFG_MACRO__ +#define __MAC_DMA_RXCFG_MACRO__ + +/* macros for field DMA_SIZE */ +#define MAC_DMA_RXCFG__DMA_SIZE__SHIFT 0 +#define MAC_DMA_RXCFG__DMA_SIZE__WIDTH 3 +#define MAC_DMA_RXCFG__DMA_SIZE__MASK 0x00000007U +#define MAC_DMA_RXCFG__DMA_SIZE__READ(src) (u_int32_t)(src) & 0x00000007U +#define MAC_DMA_RXCFG__DMA_SIZE__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define MAC_DMA_RXCFG__DMA_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MAC_DMA_RXCFG__DMA_SIZE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field ZERO_LEN_DMA_EN */ +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__SHIFT 3 +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WIDTH 2 +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MASK 0x00000018U +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000018U) >> 3) +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000018U) +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000018U) | (((u_int32_t)(src) <<\ + 3) & 0x00000018U) +#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000018U))) + +/* macros for field JUMBO_EN */ +#define MAC_DMA_RXCFG__JUMBO_EN__SHIFT 5 +#define MAC_DMA_RXCFG__JUMBO_EN__WIDTH 1 +#define MAC_DMA_RXCFG__JUMBO_EN__MASK 0x00000020U +#define MAC_DMA_RXCFG__JUMBO_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_DMA_RXCFG__JUMBO_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_DMA_RXCFG__JUMBO_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_DMA_RXCFG__JUMBO_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_DMA_RXCFG__JUMBO_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_DMA_RXCFG__JUMBO_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field JUMBO_WRAP_EN */ +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__SHIFT 6 +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WIDTH 1 +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MASK 0x00000040U +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field SLEEP_RX_PEND_EN */ +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__SHIFT 7 +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WIDTH 1 +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MASK 0x00000080U +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) +#define MAC_DMA_RXCFG__TYPE u_int32_t +#define MAC_DMA_RXCFG__READ 0x000000ffU +#define MAC_DMA_RXCFG__WRITE 0x000000ffU + +#endif /* __MAC_DMA_RXCFG_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_RXCFG */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXCFG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXJLA */ +#ifndef __MAC_DMA_RXJLA_MACRO__ +#define __MAC_DMA_RXJLA_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_RXJLA__DATA__SHIFT 2 +#define MAC_DMA_RXJLA__DATA__WIDTH 30 +#define MAC_DMA_RXJLA__DATA__MASK 0xfffffffcU +#define MAC_DMA_RXJLA__DATA__READ(src) (((u_int32_t)(src) & 0xfffffffcU) >> 2) +#define MAC_DMA_RXJLA__TYPE u_int32_t +#define MAC_DMA_RXJLA__READ 0xfffffffcU + +#endif /* __MAC_DMA_RXJLA_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_RXJLA */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXJLA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_MIBC */ +#ifndef __MAC_DMA_MIBC_MACRO__ +#define __MAC_DMA_MIBC_MACRO__ + +/* macros for field WARNING */ +#define MAC_DMA_MIBC__WARNING__SHIFT 0 +#define MAC_DMA_MIBC__WARNING__WIDTH 1 +#define MAC_DMA_MIBC__WARNING__MASK 0x00000001U +#define MAC_DMA_MIBC__WARNING__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_DMA_MIBC__WARNING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DMA_MIBC__WARNING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field FREEZE */ +#define MAC_DMA_MIBC__FREEZE__SHIFT 1 +#define MAC_DMA_MIBC__FREEZE__WIDTH 1 +#define MAC_DMA_MIBC__FREEZE__MASK 0x00000002U +#define MAC_DMA_MIBC__FREEZE__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define MAC_DMA_MIBC__FREEZE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_DMA_MIBC__FREEZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_DMA_MIBC__FREEZE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_DMA_MIBC__FREEZE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_DMA_MIBC__FREEZE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field CLEAR */ +#define MAC_DMA_MIBC__CLEAR__SHIFT 2 +#define MAC_DMA_MIBC__CLEAR__WIDTH 1 +#define MAC_DMA_MIBC__CLEAR__MASK 0x00000004U +#define MAC_DMA_MIBC__CLEAR__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define MAC_DMA_MIBC__CLEAR__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define MAC_DMA_MIBC__CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_DMA_MIBC__CLEAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_DMA_MIBC__CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_DMA_MIBC__CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field STROBE */ +#define MAC_DMA_MIBC__STROBE__SHIFT 3 +#define MAC_DMA_MIBC__STROBE__WIDTH 1 +#define MAC_DMA_MIBC__STROBE__MASK 0x00000008U +#define MAC_DMA_MIBC__STROBE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define MAC_DMA_MIBC__STROBE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_DMA_MIBC__STROBE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define MAC_DMA_MIBC__TYPE u_int32_t +#define MAC_DMA_MIBC__READ 0x0000000fU +#define MAC_DMA_MIBC__WRITE 0x0000000fU + +#endif /* __MAC_DMA_MIBC_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_MIBC */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_MIBC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TOPS */ +#ifndef __MAC_DMA_TOPS_MACRO__ +#define __MAC_DMA_TOPS_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_DMA_TOPS__TIMEOUT__SHIFT 0 +#define MAC_DMA_TOPS__TIMEOUT__WIDTH 16 +#define MAC_DMA_TOPS__TIMEOUT__MASK 0x0000ffffU +#define MAC_DMA_TOPS__TIMEOUT__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_DMA_TOPS__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_DMA_TOPS__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TOPS__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DMA_TOPS__TYPE u_int32_t +#define MAC_DMA_TOPS__READ 0x0000ffffU +#define MAC_DMA_TOPS__WRITE 0x0000ffffU + +#endif /* __MAC_DMA_TOPS_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TOPS */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TOPS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXNPTO */ +#ifndef __MAC_DMA_RXNPTO_MACRO__ +#define __MAC_DMA_RXNPTO_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_DMA_RXNPTO__TIMEOUT__SHIFT 0 +#define MAC_DMA_RXNPTO__TIMEOUT__WIDTH 10 +#define MAC_DMA_RXNPTO__TIMEOUT__MASK 0x000003ffU +#define MAC_DMA_RXNPTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DMA_RXNPTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DMA_RXNPTO__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DMA_RXNPTO__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_DMA_RXNPTO__TYPE u_int32_t +#define MAC_DMA_RXNPTO__READ 0x000003ffU +#define MAC_DMA_RXNPTO__WRITE 0x000003ffU + +#endif /* __MAC_DMA_RXNPTO_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_RXNPTO */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXNPTO__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXNPTO */ +#ifndef __MAC_DMA_TXNPTO_MACRO__ +#define __MAC_DMA_TXNPTO_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_DMA_TXNPTO__TIMEOUT__SHIFT 0 +#define MAC_DMA_TXNPTO__TIMEOUT__WIDTH 10 +#define MAC_DMA_TXNPTO__TIMEOUT__MASK 0x000003ffU +#define MAC_DMA_TXNPTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DMA_TXNPTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DMA_TXNPTO__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DMA_TXNPTO__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field MASK */ +#define MAC_DMA_TXNPTO__MASK__SHIFT 10 +#define MAC_DMA_TXNPTO__MASK__WIDTH 10 +#define MAC_DMA_TXNPTO__MASK__MASK 0x000ffc00U +#define MAC_DMA_TXNPTO__MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define MAC_DMA_TXNPTO__MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define MAC_DMA_TXNPTO__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define MAC_DMA_TXNPTO__MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) +#define MAC_DMA_TXNPTO__TYPE u_int32_t +#define MAC_DMA_TXNPTO__READ 0x000fffffU +#define MAC_DMA_TXNPTO__WRITE 0x000fffffU + +#endif /* __MAC_DMA_TXNPTO_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TXNPTO */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TXNPTO__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RPGTO */ +#ifndef __MAC_DMA_RPGTO_MACRO__ +#define __MAC_DMA_RPGTO_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_DMA_RPGTO__TIMEOUT__SHIFT 0 +#define MAC_DMA_RPGTO__TIMEOUT__WIDTH 10 +#define MAC_DMA_RPGTO__TIMEOUT__MASK 0x000003ffU +#define MAC_DMA_RPGTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DMA_RPGTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DMA_RPGTO__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DMA_RPGTO__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_DMA_RPGTO__TYPE u_int32_t +#define MAC_DMA_RPGTO__READ 0x000003ffU +#define MAC_DMA_RPGTO__WRITE 0x000003ffU + +#endif /* __MAC_DMA_RPGTO_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_RPGTO */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_RPGTO__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_MACMISC */ +#ifndef __MAC_DMA_MACMISC_MACRO__ +#define __MAC_DMA_MACMISC_MACRO__ + +/* macros for field FORCE_PCI_EXT */ +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__SHIFT 4 +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__WIDTH 1 +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__MASK 0x00000010U +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_DMA_MACMISC__FORCE_PCI_EXT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field DMA_OBS_MUXSEL */ +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__SHIFT 5 +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WIDTH 4 +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MASK 0x000001e0U +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001e0U) >> 5) +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000001e0U) +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000001e0U) +#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000001e0U))) + +/* macros for field MISC_OBS_MUXSEL */ +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__SHIFT 9 +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WIDTH 3 +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MASK 0x00000e00U +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000e00U) >> 9) +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field MISC_F2_OBS_LOW_MUXSEL */ +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__SHIFT 12 +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WIDTH 3 +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MASK 0x00007000U +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007000U) >> 12) +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00007000U) +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field MISC_F2_OBS_HIGH_MUXSEL */ +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__SHIFT 15 +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WIDTH 3 +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MASK 0x00038000U +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00038000U) >> 15) +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00038000U) +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) +#define MAC_DMA_MACMISC__TYPE u_int32_t +#define MAC_DMA_MACMISC__READ 0x0003fff0U +#define MAC_DMA_MACMISC__WRITE 0x0003fff0U + +#endif /* __MAC_DMA_MACMISC_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_MACMISC */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_MACMISC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_INTER */ +#ifndef __MAC_DMA_INTER_MACRO__ +#define __MAC_DMA_INTER_MACRO__ + +/* macros for field REQ */ +#define MAC_DMA_INTER__REQ__SHIFT 0 +#define MAC_DMA_INTER__REQ__WIDTH 1 +#define MAC_DMA_INTER__REQ__MASK 0x00000001U +#define MAC_DMA_INTER__REQ__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_DMA_INTER__REQ__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_DMA_INTER__REQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_DMA_INTER__REQ__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define MAC_DMA_INTER__REQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DMA_INTER__REQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field MSI_RX_SRC */ +#define MAC_DMA_INTER__MSI_RX_SRC__SHIFT 1 +#define MAC_DMA_INTER__MSI_RX_SRC__WIDTH 2 +#define MAC_DMA_INTER__MSI_RX_SRC__MASK 0x00000006U +#define MAC_DMA_INTER__MSI_RX_SRC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000006U) >> 1) +#define MAC_DMA_INTER__MSI_RX_SRC__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000006U) +#define MAC_DMA_INTER__MSI_RX_SRC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((u_int32_t)(src) <<\ + 1) & 0x00000006U) +#define MAC_DMA_INTER__MSI_RX_SRC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000006U))) + +/* macros for field MSI_TX_SRC */ +#define MAC_DMA_INTER__MSI_TX_SRC__SHIFT 3 +#define MAC_DMA_INTER__MSI_TX_SRC__WIDTH 2 +#define MAC_DMA_INTER__MSI_TX_SRC__MASK 0x00000018U +#define MAC_DMA_INTER__MSI_TX_SRC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000018U) >> 3) +#define MAC_DMA_INTER__MSI_TX_SRC__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000018U) +#define MAC_DMA_INTER__MSI_TX_SRC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000018U) | (((u_int32_t)(src) <<\ + 3) & 0x00000018U) +#define MAC_DMA_INTER__MSI_TX_SRC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000018U))) +#define MAC_DMA_INTER__TYPE u_int32_t +#define MAC_DMA_INTER__READ 0x0000001fU +#define MAC_DMA_INTER__WRITE 0x0000001fU + +#endif /* __MAC_DMA_INTER_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_INTER */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_INTER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DATABUF */ +#ifndef __MAC_DMA_DATABUF_MACRO__ +#define __MAC_DMA_DATABUF_MACRO__ + +/* macros for field LEN */ +#define MAC_DMA_DATABUF__LEN__SHIFT 0 +#define MAC_DMA_DATABUF__LEN__WIDTH 12 +#define MAC_DMA_DATABUF__LEN__MASK 0x00000fffU +#define MAC_DMA_DATABUF__LEN__READ(src) (u_int32_t)(src) & 0x00000fffU +#define MAC_DMA_DATABUF__LEN__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) +#define MAC_DMA_DATABUF__LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define MAC_DMA_DATABUF__LEN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) +#define MAC_DMA_DATABUF__TYPE u_int32_t +#define MAC_DMA_DATABUF__READ 0x00000fffU +#define MAC_DMA_DATABUF__WRITE 0x00000fffU + +#endif /* __MAC_DMA_DATABUF_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_DATABUF */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_DATABUF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_GTT */ +#ifndef __MAC_DMA_GTT_MACRO__ +#define __MAC_DMA_GTT_MACRO__ + +/* macros for field COUNT */ +#define MAC_DMA_GTT__COUNT__SHIFT 0 +#define MAC_DMA_GTT__COUNT__WIDTH 16 +#define MAC_DMA_GTT__COUNT__MASK 0x0000ffffU +#define MAC_DMA_GTT__COUNT__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_DMA_GTT__COUNT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_DMA_GTT__COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_GTT__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU))) + +/* macros for field LIMIT */ +#define MAC_DMA_GTT__LIMIT__SHIFT 16 +#define MAC_DMA_GTT__LIMIT__WIDTH 16 +#define MAC_DMA_GTT__LIMIT__MASK 0xffff0000U +#define MAC_DMA_GTT__LIMIT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16) +#define MAC_DMA_GTT__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U) +#define MAC_DMA_GTT__LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_GTT__LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_GTT__TYPE u_int32_t +#define MAC_DMA_GTT__READ 0xffffffffU +#define MAC_DMA_GTT__WRITE 0xffffffffU + +#endif /* __MAC_DMA_GTT_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_GTT */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_GTT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_GTTM */ +#ifndef __MAC_DMA_GTTM_MACRO__ +#define __MAC_DMA_GTTM_MACRO__ + +/* macros for field USEC_STROBE */ +#define MAC_DMA_GTTM__USEC_STROBE__SHIFT 0 +#define MAC_DMA_GTTM__USEC_STROBE__WIDTH 1 +#define MAC_DMA_GTTM__USEC_STROBE__MASK 0x00000001U +#define MAC_DMA_GTTM__USEC_STROBE__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_DMA_GTTM__USEC_STROBE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_DMA_GTTM__USEC_STROBE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_DMA_GTTM__USEC_STROBE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_DMA_GTTM__USEC_STROBE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DMA_GTTM__USEC_STROBE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field IGNORE_CHAN_IDLE */ +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__SHIFT 1 +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WIDTH 1 +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MASK 0x00000002U +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field RESET_ON_CHAN_IDLE */ +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__SHIFT 2 +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WIDTH 1 +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MASK 0x00000004U +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field CST_USEC_STROBE */ +#define MAC_DMA_GTTM__CST_USEC_STROBE__SHIFT 3 +#define MAC_DMA_GTTM__CST_USEC_STROBE__WIDTH 1 +#define MAC_DMA_GTTM__CST_USEC_STROBE__MASK 0x00000008U +#define MAC_DMA_GTTM__CST_USEC_STROBE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_DMA_GTTM__CST_USEC_STROBE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_DMA_GTTM__CST_USEC_STROBE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_DMA_GTTM__CST_USEC_STROBE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_DMA_GTTM__CST_USEC_STROBE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_DMA_GTTM__CST_USEC_STROBE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field DISABLE_QCU_FR_ACTIVE_GTT */ +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__SHIFT 4 +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WIDTH 1 +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MASK 0x00000010U +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field DISABLE_QCU_FR_ACTIVE_BT */ +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__SHIFT 5 +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WIDTH 1 +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MASK 0x00000020U +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define MAC_DMA_GTTM__TYPE u_int32_t +#define MAC_DMA_GTTM__READ 0x0000003fU +#define MAC_DMA_GTTM__WRITE 0x0000003fU + +#endif /* __MAC_DMA_GTTM_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_GTTM */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_GTTM__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_CST */ +#ifndef __MAC_DMA_CST_MACRO__ +#define __MAC_DMA_CST_MACRO__ + +/* macros for field COUNT */ +#define MAC_DMA_CST__COUNT__SHIFT 0 +#define MAC_DMA_CST__COUNT__WIDTH 16 +#define MAC_DMA_CST__COUNT__MASK 0x0000ffffU +#define MAC_DMA_CST__COUNT__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_DMA_CST__COUNT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_DMA_CST__COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_CST__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU))) + +/* macros for field LIMIT */ +#define MAC_DMA_CST__LIMIT__SHIFT 16 +#define MAC_DMA_CST__LIMIT__WIDTH 16 +#define MAC_DMA_CST__LIMIT__MASK 0xffff0000U +#define MAC_DMA_CST__LIMIT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16) +#define MAC_DMA_CST__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U) +#define MAC_DMA_CST__LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_CST__LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_CST__TYPE u_int32_t +#define MAC_DMA_CST__READ 0xffffffffU +#define MAC_DMA_CST__WRITE 0xffffffffU + +#endif /* __MAC_DMA_CST_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_CST */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_CST__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXDP_SIZE */ +#ifndef __MAC_DMA_RXDP_SIZE_MACRO__ +#define __MAC_DMA_RXDP_SIZE_MACRO__ + +/* macros for field LP */ +#define MAC_DMA_RXDP_SIZE__LP__SHIFT 0 +#define MAC_DMA_RXDP_SIZE__LP__WIDTH 8 +#define MAC_DMA_RXDP_SIZE__LP__MASK 0x000000ffU +#define MAC_DMA_RXDP_SIZE__LP__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field HP */ +#define MAC_DMA_RXDP_SIZE__HP__SHIFT 8 +#define MAC_DMA_RXDP_SIZE__HP__WIDTH 5 +#define MAC_DMA_RXDP_SIZE__HP__MASK 0x00001f00U +#define MAC_DMA_RXDP_SIZE__HP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define MAC_DMA_RXDP_SIZE__TYPE u_int32_t +#define MAC_DMA_RXDP_SIZE__READ 0x00001fffU + +#endif /* __MAC_DMA_RXDP_SIZE_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_RXDP_SIZE */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXDP_SIZE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RX_QUEUE_HP_RXDP */ +#ifndef __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__ +#define __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__ + +/* macros for field ADDR */ +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__SHIFT 0 +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WIDTH 32 +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MASK 0xffffffffU +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_RX_QUEUE_HP_RXDP__TYPE u_int32_t +#define MAC_DMA_RX_QUEUE_HP_RXDP__READ 0xffffffffU +#define MAC_DMA_RX_QUEUE_HP_RXDP__WRITE 0xffffffffU + +#endif /* __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_RX_QUEUE_HP_RXDP */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_RX_QUEUE_HP_RXDP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_RX_QUEUE_LP_RXDP */ +#ifndef __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__ +#define __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__ + +/* macros for field ADDR */ +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__SHIFT 0 +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WIDTH 32 +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MASK 0xffffffffU +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_RX_QUEUE_LP_RXDP__TYPE u_int32_t +#define MAC_DMA_RX_QUEUE_LP_RXDP__READ 0xffffffffU +#define MAC_DMA_RX_QUEUE_LP_RXDP__WRITE 0xffffffffU + +#endif /* __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_RX_QUEUE_LP_RXDP */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_RX_QUEUE_LP_RXDP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_P */ +#ifndef __MAC_DMA_ISR_P_MACRO__ +#define __MAC_DMA_ISR_P_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_P__DATA__SHIFT 0 +#define MAC_DMA_ISR_P__DATA__WIDTH 32 +#define MAC_DMA_ISR_P__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_P__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_P__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_P__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_P__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define MAC_DMA_ISR_P__TYPE u_int32_t +#define MAC_DMA_ISR_P__READ 0xffffffffU +#define MAC_DMA_ISR_P__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_P_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_P */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_P__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S0 */ +#ifndef __MAC_DMA_ISR_S0_MACRO__ +#define __MAC_DMA_ISR_S0_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S0__DATA__SHIFT 0 +#define MAC_DMA_ISR_S0__DATA__WIDTH 32 +#define MAC_DMA_ISR_S0__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S0__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S0__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S0__TYPE u_int32_t +#define MAC_DMA_ISR_S0__READ 0xffffffffU +#define MAC_DMA_ISR_S0__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S0_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S0 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S1 */ +#ifndef __MAC_DMA_ISR_S1_MACRO__ +#define __MAC_DMA_ISR_S1_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S1__DATA__SHIFT 0 +#define MAC_DMA_ISR_S1__DATA__WIDTH 32 +#define MAC_DMA_ISR_S1__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S1__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S1__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S1__TYPE u_int32_t +#define MAC_DMA_ISR_S1__READ 0xffffffffU +#define MAC_DMA_ISR_S1__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S1_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S1 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S2 */ +#ifndef __MAC_DMA_ISR_S2_MACRO__ +#define __MAC_DMA_ISR_S2_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S2__DATA__SHIFT 0 +#define MAC_DMA_ISR_S2__DATA__WIDTH 32 +#define MAC_DMA_ISR_S2__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S2__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S2__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S2__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S2__TYPE u_int32_t +#define MAC_DMA_ISR_S2__READ 0xffffffffU +#define MAC_DMA_ISR_S2__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S2_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S2 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S3 */ +#ifndef __MAC_DMA_ISR_S3_MACRO__ +#define __MAC_DMA_ISR_S3_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S3__DATA__SHIFT 0 +#define MAC_DMA_ISR_S3__DATA__WIDTH 32 +#define MAC_DMA_ISR_S3__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S3__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S3__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S3__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S3__TYPE u_int32_t +#define MAC_DMA_ISR_S3__READ 0xffffffffU +#define MAC_DMA_ISR_S3__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S3_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S3 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S4 */ +#ifndef __MAC_DMA_ISR_S4_MACRO__ +#define __MAC_DMA_ISR_S4_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S4__DATA__SHIFT 0 +#define MAC_DMA_ISR_S4__DATA__WIDTH 32 +#define MAC_DMA_ISR_S4__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S4__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S4__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S4__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S4__TYPE u_int32_t +#define MAC_DMA_ISR_S4__READ 0xffffffffU +#define MAC_DMA_ISR_S4__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S4_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S4 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S5 */ +#ifndef __MAC_DMA_ISR_S5_MACRO__ +#define __MAC_DMA_ISR_S5_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_S5__DATA__SHIFT 0 +#define MAC_DMA_ISR_S5__DATA__WIDTH 32 +#define MAC_DMA_ISR_S5__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_S5__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S5__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_ISR_S5__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_ISR_S5__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_ISR_S5__TYPE u_int32_t +#define MAC_DMA_ISR_S5__READ 0xffffffffU +#define MAC_DMA_ISR_S5__WRITE 0xffffffffU + +#endif /* __MAC_DMA_ISR_S5_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S5 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_P */ +#ifndef __MAC_DMA_IMR_P_MACRO__ +#define __MAC_DMA_IMR_P_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_P__MASK__SHIFT 0 +#define MAC_DMA_IMR_P__MASK__WIDTH 32 +#define MAC_DMA_IMR_P__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_P__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_P__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_P__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_P__MASK__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define MAC_DMA_IMR_P__TYPE u_int32_t +#define MAC_DMA_IMR_P__READ 0xffffffffU +#define MAC_DMA_IMR_P__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_P_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_IMR_P */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_P__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S0 */ +#ifndef __MAC_DMA_IMR_S0_MACRO__ +#define __MAC_DMA_IMR_S0_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_S0__MASK__SHIFT 0 +#define MAC_DMA_IMR_S0__MASK__WIDTH 32 +#define MAC_DMA_IMR_S0__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_S0__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S0__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S0__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S0__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S0__TYPE u_int32_t +#define MAC_DMA_IMR_S0__READ 0xffffffffU +#define MAC_DMA_IMR_S0__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S0_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_IMR_S0 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S1 */ +#ifndef __MAC_DMA_IMR_S1_MACRO__ +#define __MAC_DMA_IMR_S1_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_IMR_S1__DATA__SHIFT 0 +#define MAC_DMA_IMR_S1__DATA__WIDTH 32 +#define MAC_DMA_IMR_S1__DATA__MASK 0xffffffffU +#define MAC_DMA_IMR_S1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S1__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S1__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S1__TYPE u_int32_t +#define MAC_DMA_IMR_S1__READ 0xffffffffU +#define MAC_DMA_IMR_S1__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S1_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_IMR_S1 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S2 */ +#ifndef __MAC_DMA_IMR_S2_MACRO__ +#define __MAC_DMA_IMR_S2_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_S2__MASK__SHIFT 0 +#define MAC_DMA_IMR_S2__MASK__WIDTH 32 +#define MAC_DMA_IMR_S2__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_S2__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S2__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S2__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S2__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S2__TYPE u_int32_t +#define MAC_DMA_IMR_S2__READ 0xffffffffU +#define MAC_DMA_IMR_S2__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S2_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_IMR_S2 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S3 */ +#ifndef __MAC_DMA_IMR_S3_MACRO__ +#define __MAC_DMA_IMR_S3_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_S3__MASK__SHIFT 0 +#define MAC_DMA_IMR_S3__MASK__WIDTH 32 +#define MAC_DMA_IMR_S3__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_S3__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S3__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S3__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S3__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S3__TYPE u_int32_t +#define MAC_DMA_IMR_S3__READ 0xffffffffU +#define MAC_DMA_IMR_S3__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S3_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_IMR_S3 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S4 */ +#ifndef __MAC_DMA_IMR_S4_MACRO__ +#define __MAC_DMA_IMR_S4_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_S4__MASK__SHIFT 0 +#define MAC_DMA_IMR_S4__MASK__WIDTH 32 +#define MAC_DMA_IMR_S4__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_S4__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S4__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S4__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S4__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S4__TYPE u_int32_t +#define MAC_DMA_IMR_S4__READ 0xffffffffU +#define MAC_DMA_IMR_S4__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S4_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_IMR_S4 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S5 */ +#ifndef __MAC_DMA_IMR_S5_MACRO__ +#define __MAC_DMA_IMR_S5_MACRO__ + +/* macros for field MASK */ +#define MAC_DMA_IMR_S5__MASK__SHIFT 0 +#define MAC_DMA_IMR_S5__MASK__WIDTH 32 +#define MAC_DMA_IMR_S5__MASK__MASK 0xffffffffU +#define MAC_DMA_IMR_S5__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_IMR_S5__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DMA_IMR_S5__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DMA_IMR_S5__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DMA_IMR_S5__TYPE u_int32_t +#define MAC_DMA_IMR_S5__READ 0xffffffffU +#define MAC_DMA_IMR_S5__WRITE 0xffffffffU + +#endif /* __MAC_DMA_IMR_S5_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_IMR_S5 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_P_RAC */ +#ifndef __MAC_DMA_ISR_P_RAC_MACRO__ +#define __MAC_DMA_ISR_P_RAC_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_ISR_P_RAC__DATA__SHIFT 0 +#define MAC_DMA_ISR_P_RAC__DATA__WIDTH 32 +#define MAC_DMA_ISR_P_RAC__DATA__MASK 0xffffffffU +#define MAC_DMA_ISR_P_RAC__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_P_RAC__TYPE u_int32_t +#define MAC_DMA_ISR_P_RAC__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_P_RAC_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_P_RAC */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_P_RAC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S0_S */ +#ifndef __MAC_DMA_ISR_S0_S_MACRO__ +#define __MAC_DMA_ISR_S0_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S0_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S0_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S0_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S0_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S0_S__TYPE u_int32_t +#define MAC_DMA_ISR_S0_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S0_S_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S0_S */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S0_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S1_S */ +#ifndef __MAC_DMA_ISR_S1_S_MACRO__ +#define __MAC_DMA_ISR_S1_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S1_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S1_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S1_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S1_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S1_S__TYPE u_int32_t +#define MAC_DMA_ISR_S1_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S1_S_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S1_S */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S1_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S2_S */ +#ifndef __MAC_DMA_ISR_S2_S_MACRO__ +#define __MAC_DMA_ISR_S2_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S2_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S2_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S2_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S2_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S2_S__TYPE u_int32_t +#define MAC_DMA_ISR_S2_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S2_S_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S2_S */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S2_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S3_S */ +#ifndef __MAC_DMA_ISR_S3_S_MACRO__ +#define __MAC_DMA_ISR_S3_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S3_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S3_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S3_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S3_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S3_S__TYPE u_int32_t +#define MAC_DMA_ISR_S3_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S3_S_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S3_S */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S3_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S4_S */ +#ifndef __MAC_DMA_ISR_S4_S_MACRO__ +#define __MAC_DMA_ISR_S4_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S4_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S4_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S4_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S4_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S4_S__TYPE u_int32_t +#define MAC_DMA_ISR_S4_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S4_S_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S4_S */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S4_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S5_S */ +#ifndef __MAC_DMA_ISR_S5_S_MACRO__ +#define __MAC_DMA_ISR_S5_S_MACRO__ + +/* macros for field SHADOW */ +#define MAC_DMA_ISR_S5_S__SHADOW__SHIFT 0 +#define MAC_DMA_ISR_S5_S__SHADOW__WIDTH 32 +#define MAC_DMA_ISR_S5_S__SHADOW__MASK 0xffffffffU +#define MAC_DMA_ISR_S5_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_ISR_S5_S__TYPE u_int32_t +#define MAC_DMA_ISR_S5_S__READ 0xffffffffU + +#endif /* __MAC_DMA_ISR_S5_S_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_ISR_S5_S */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S5_S__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_0 */ +#ifndef __MAC_DMA_DMADBG_0_MACRO__ +#define __MAC_DMA_DMADBG_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_0__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_0__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_0__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_0__TYPE u_int32_t +#define MAC_DMA_DMADBG_0__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_0_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_0 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_1 */ +#ifndef __MAC_DMA_DMADBG_1_MACRO__ +#define __MAC_DMA_DMADBG_1_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_1__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_1__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_1__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_1__TYPE u_int32_t +#define MAC_DMA_DMADBG_1__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_1_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_1 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_2 */ +#ifndef __MAC_DMA_DMADBG_2_MACRO__ +#define __MAC_DMA_DMADBG_2_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_2__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_2__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_2__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_2__TYPE u_int32_t +#define MAC_DMA_DMADBG_2__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_2_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_2 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_3 */ +#ifndef __MAC_DMA_DMADBG_3_MACRO__ +#define __MAC_DMA_DMADBG_3_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_3__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_3__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_3__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_3__TYPE u_int32_t +#define MAC_DMA_DMADBG_3__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_3_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_3 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_4 */ +#ifndef __MAC_DMA_DMADBG_4_MACRO__ +#define __MAC_DMA_DMADBG_4_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_4__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_4__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_4__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_4__TYPE u_int32_t +#define MAC_DMA_DMADBG_4__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_4_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_4 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_5 */ +#ifndef __MAC_DMA_DMADBG_5_MACRO__ +#define __MAC_DMA_DMADBG_5_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_5__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_5__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_5__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_5__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_5__TYPE u_int32_t +#define MAC_DMA_DMADBG_5__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_5_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_5 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_6 */ +#ifndef __MAC_DMA_DMADBG_6_MACRO__ +#define __MAC_DMA_DMADBG_6_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_6__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_6__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_6__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_6__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_6__TYPE u_int32_t +#define MAC_DMA_DMADBG_6__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_6_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_6 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_7 */ +#ifndef __MAC_DMA_DMADBG_7_MACRO__ +#define __MAC_DMA_DMADBG_7_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_DMADBG_7__DATA__SHIFT 0 +#define MAC_DMA_DMADBG_7__DATA__WIDTH 32 +#define MAC_DMA_DMADBG_7__DATA__MASK 0xffffffffU +#define MAC_DMA_DMADBG_7__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DMA_DMADBG_7__TYPE u_int32_t +#define MAC_DMA_DMADBG_7__READ 0xffffffffU + +#endif /* __MAC_DMA_DMADBG_7_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_7 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0 */ +#ifndef __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__ +#define __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__SHIFT 0 +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__WIDTH 32 +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__MASK 0xffffffffU +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__TYPE u_int32_t +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__READ 0xffffffffU + +#endif /* __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8 */ +#ifndef __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__ +#define __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__ + +/* macros for field DATA */ +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__SHIFT 0 +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__WIDTH 8 +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__MASK 0x000000ffU +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__TYPE u_int32_t +#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__READ 0x000000ffU + +#endif /* __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_0 */ +#ifndef __MAC_DMA_TIMT_0_MACRO__ +#define __MAC_DMA_TIMT_0_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT_0__TYPE u_int32_t +#define MAC_DMA_TIMT_0__READ 0xffffffffU +#define MAC_DMA_TIMT_0__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_0_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TIMT_0 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_1 */ +#ifndef __MAC_DMA_TIMT_1_MACRO__ +#define __MAC_DMA_TIMT_1_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT_1__TYPE u_int32_t +#define MAC_DMA_TIMT_1__READ 0xffffffffU +#define MAC_DMA_TIMT_1__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_1_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TIMT_1 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_2 */ +#ifndef __MAC_DMA_TIMT_2_MACRO__ +#define __MAC_DMA_TIMT_2_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT_2__TYPE u_int32_t +#define MAC_DMA_TIMT_2__READ 0xffffffffU +#define MAC_DMA_TIMT_2__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_2_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TIMT_2 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_3 */ +#ifndef __MAC_DMA_TIMT_3_MACRO__ +#define __MAC_DMA_TIMT_3_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT_3__TYPE u_int32_t +#define MAC_DMA_TIMT_3__READ 0xffffffffU +#define MAC_DMA_TIMT_3__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_3_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TIMT_3 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_4 */ +#ifndef __MAC_DMA_TIMT_4_MACRO__ +#define __MAC_DMA_TIMT_4_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT_4__TYPE u_int32_t +#define MAC_DMA_TIMT_4__READ 0xffffffffU +#define MAC_DMA_TIMT_4__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_4_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TIMT_4 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_5 */ +#ifndef __MAC_DMA_TIMT_5_MACRO__ +#define __MAC_DMA_TIMT_5_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT_5__TYPE u_int32_t +#define MAC_DMA_TIMT_5__READ 0xffffffffU +#define MAC_DMA_TIMT_5__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_5_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TIMT_5 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_6 */ +#ifndef __MAC_DMA_TIMT_6_MACRO__ +#define __MAC_DMA_TIMT_6_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT_6__TYPE u_int32_t +#define MAC_DMA_TIMT_6__READ 0xffffffffU +#define MAC_DMA_TIMT_6__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_6_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TIMT_6 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_7 */ +#ifndef __MAC_DMA_TIMT_7_MACRO__ +#define __MAC_DMA_TIMT_7_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT_7__TYPE u_int32_t +#define MAC_DMA_TIMT_7__READ 0xffffffffU +#define MAC_DMA_TIMT_7__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_7_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TIMT_7 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_8 */ +#ifndef __MAC_DMA_TIMT_8_MACRO__ +#define __MAC_DMA_TIMT_8_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT_8__TYPE u_int32_t +#define MAC_DMA_TIMT_8__READ 0xffffffffU +#define MAC_DMA_TIMT_8__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_8_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TIMT_8 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_9 */ +#ifndef __MAC_DMA_TIMT_9_MACRO__ +#define __MAC_DMA_TIMT_9_MACRO__ + +/* macros for field TX_LAST_PKT_THRESH */ +#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__SHIFT 0 +#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__MASK 0x0000ffffU +#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field TX_FIRST_PKT_THRESH */ +#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__SHIFT 16 +#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__WIDTH 16 +#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__MASK 0xffff0000U +#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_DMA_TIMT_9__TYPE u_int32_t +#define MAC_DMA_TIMT_9__READ 0xffffffffU +#define MAC_DMA_TIMT_9__WRITE 0xffffffffU + +#endif /* __MAC_DMA_TIMT_9_MACRO__ */ + + +/* macros for mac_dma_reg_map.MAC_DMA_TIMT_9 */ +#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXDP */ +#ifndef __MAC_QCU_TXDP_MACRO__ +#define __MAC_QCU_TXDP_MACRO__ + +/* macros for field DATA */ +#define MAC_QCU_TXDP__DATA__SHIFT 0 +#define MAC_QCU_TXDP__DATA__WIDTH 32 +#define MAC_QCU_TXDP__DATA__MASK 0xffffffffU +#define MAC_QCU_TXDP__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_QCU_TXDP__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_QCU_TXDP__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_QCU_TXDP__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define MAC_QCU_TXDP__TYPE u_int32_t +#define MAC_QCU_TXDP__READ 0xffffffffU +#define MAC_QCU_TXDP__WRITE 0xffffffffU + +#endif /* __MAC_QCU_TXDP_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_TXDP */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_TXDP__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_START */ +#ifndef __MAC_QCU_STATUS_RING_START_MACRO__ +#define __MAC_QCU_STATUS_RING_START_MACRO__ + +/* macros for field ADDR */ +#define MAC_QCU_STATUS_RING_START__ADDR__SHIFT 0 +#define MAC_QCU_STATUS_RING_START__ADDR__WIDTH 32 +#define MAC_QCU_STATUS_RING_START__ADDR__MASK 0xffffffffU +#define MAC_QCU_STATUS_RING_START__ADDR__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_QCU_STATUS_RING_START__ADDR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_QCU_STATUS_RING_START__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_QCU_STATUS_RING_START__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_QCU_STATUS_RING_START__TYPE u_int32_t +#define MAC_QCU_STATUS_RING_START__READ 0xffffffffU +#define MAC_QCU_STATUS_RING_START__WRITE 0xffffffffU + +#endif /* __MAC_QCU_STATUS_RING_START_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_START */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_START__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_END */ +#ifndef __MAC_QCU_STATUS_RING_END_MACRO__ +#define __MAC_QCU_STATUS_RING_END_MACRO__ + +/* macros for field ADDR */ +#define MAC_QCU_STATUS_RING_END__ADDR__SHIFT 0 +#define MAC_QCU_STATUS_RING_END__ADDR__WIDTH 32 +#define MAC_QCU_STATUS_RING_END__ADDR__MASK 0xffffffffU +#define MAC_QCU_STATUS_RING_END__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_QCU_STATUS_RING_END__ADDR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_QCU_STATUS_RING_END__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_QCU_STATUS_RING_END__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_QCU_STATUS_RING_END__TYPE u_int32_t +#define MAC_QCU_STATUS_RING_END__READ 0xffffffffU +#define MAC_QCU_STATUS_RING_END__WRITE 0xffffffffU + +#endif /* __MAC_QCU_STATUS_RING_END_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_END */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_END__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_CURRENT */ +#ifndef __MAC_QCU_STATUS_RING_CURRENT_MACRO__ +#define __MAC_QCU_STATUS_RING_CURRENT_MACRO__ + +/* macros for field ADDRESS */ +#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__SHIFT 0 +#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__WIDTH 32 +#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__MASK 0xffffffffU +#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_QCU_STATUS_RING_CURRENT__TYPE u_int32_t +#define MAC_QCU_STATUS_RING_CURRENT__READ 0xffffffffU + +#endif /* __MAC_QCU_STATUS_RING_CURRENT_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_CURRENT */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_CURRENT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXE */ +#ifndef __MAC_QCU_TXE_MACRO__ +#define __MAC_QCU_TXE_MACRO__ + +/* macros for field DATA */ +#define MAC_QCU_TXE__DATA__SHIFT 0 +#define MAC_QCU_TXE__DATA__WIDTH 10 +#define MAC_QCU_TXE__DATA__MASK 0x000003ffU +#define MAC_QCU_TXE__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_QCU_TXE__TYPE u_int32_t +#define MAC_QCU_TXE__READ 0x000003ffU + +#endif /* __MAC_QCU_TXE_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_TXE */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_TXE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXD */ +#ifndef __MAC_QCU_TXD_MACRO__ +#define __MAC_QCU_TXD_MACRO__ + +/* macros for field DATA */ +#define MAC_QCU_TXD__DATA__SHIFT 0 +#define MAC_QCU_TXD__DATA__WIDTH 10 +#define MAC_QCU_TXD__DATA__MASK 0x000003ffU +#define MAC_QCU_TXD__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_QCU_TXD__DATA__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_QCU_TXD__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_QCU_TXD__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU))) + +/* macros for field SPARE */ +#define MAC_QCU_TXD__SPARE__SHIFT 10 +#define MAC_QCU_TXD__SPARE__WIDTH 4 +#define MAC_QCU_TXD__SPARE__MASK 0x00003c00U +#define MAC_QCU_TXD__SPARE__READ(src) (((u_int32_t)(src) & 0x00003c00U) >> 10) +#define MAC_QCU_TXD__SPARE__WRITE(src) (((u_int32_t)(src) << 10) & 0x00003c00U) +#define MAC_QCU_TXD__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00003c00U) +#define MAC_QCU_TXD__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00003c00U))) +#define MAC_QCU_TXD__TYPE u_int32_t +#define MAC_QCU_TXD__READ 0x00003fffU +#define MAC_QCU_TXD__WRITE 0x00003fffU + +#endif /* __MAC_QCU_TXD_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_TXD */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_TXD__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_CBR */ +#ifndef __MAC_QCU_CBR_MACRO__ +#define __MAC_QCU_CBR_MACRO__ + +/* macros for field INTERVAL */ +#define MAC_QCU_CBR__INTERVAL__SHIFT 0 +#define MAC_QCU_CBR__INTERVAL__WIDTH 24 +#define MAC_QCU_CBR__INTERVAL__MASK 0x00ffffffU +#define MAC_QCU_CBR__INTERVAL__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_QCU_CBR__INTERVAL__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) +#define MAC_QCU_CBR__INTERVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_QCU_CBR__INTERVAL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) + +/* macros for field OVF_THRESH */ +#define MAC_QCU_CBR__OVF_THRESH__SHIFT 24 +#define MAC_QCU_CBR__OVF_THRESH__WIDTH 8 +#define MAC_QCU_CBR__OVF_THRESH__MASK 0xff000000U +#define MAC_QCU_CBR__OVF_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_QCU_CBR__OVF_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_QCU_CBR__OVF_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_QCU_CBR__OVF_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_QCU_CBR__TYPE u_int32_t +#define MAC_QCU_CBR__READ 0xffffffffU +#define MAC_QCU_CBR__WRITE 0xffffffffU + +#endif /* __MAC_QCU_CBR_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_CBR */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_CBR__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_RDYTIME */ +#ifndef __MAC_QCU_RDYTIME_MACRO__ +#define __MAC_QCU_RDYTIME_MACRO__ + +/* macros for field DURATION */ +#define MAC_QCU_RDYTIME__DURATION__SHIFT 0 +#define MAC_QCU_RDYTIME__DURATION__WIDTH 24 +#define MAC_QCU_RDYTIME__DURATION__MASK 0x00ffffffU +#define MAC_QCU_RDYTIME__DURATION__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_QCU_RDYTIME__DURATION__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) +#define MAC_QCU_RDYTIME__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_QCU_RDYTIME__DURATION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) + +/* macros for field EN */ +#define MAC_QCU_RDYTIME__EN__SHIFT 24 +#define MAC_QCU_RDYTIME__EN__WIDTH 1 +#define MAC_QCU_RDYTIME__EN__MASK 0x01000000U +#define MAC_QCU_RDYTIME__EN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define MAC_QCU_RDYTIME__EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_QCU_RDYTIME__EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_QCU_RDYTIME__EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_QCU_RDYTIME__EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_QCU_RDYTIME__EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define MAC_QCU_RDYTIME__TYPE u_int32_t +#define MAC_QCU_RDYTIME__READ 0x01ffffffU +#define MAC_QCU_RDYTIME__WRITE 0x01ffffffU + +#endif /* __MAC_QCU_RDYTIME_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_RDYTIME */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_RDYTIME__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_ONESHOT_ARM_SC */ +#ifndef __MAC_QCU_ONESHOT_ARM_SC_MACRO__ +#define __MAC_QCU_ONESHOT_ARM_SC_MACRO__ + +/* macros for field SET */ +#define MAC_QCU_ONESHOT_ARM_SC__SET__SHIFT 0 +#define MAC_QCU_ONESHOT_ARM_SC__SET__WIDTH 10 +#define MAC_QCU_ONESHOT_ARM_SC__SET__MASK 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_SC__SET__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_SC__SET__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define MAC_QCU_ONESHOT_ARM_SC__SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_QCU_ONESHOT_ARM_SC__SET__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_QCU_ONESHOT_ARM_SC__TYPE u_int32_t +#define MAC_QCU_ONESHOT_ARM_SC__READ 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_SC__WRITE 0x000003ffU + +#endif /* __MAC_QCU_ONESHOT_ARM_SC_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_ONESHOT_ARM_SC */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_ONESHOT_ARM_SC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_ONESHOT_ARM_CC */ +#ifndef __MAC_QCU_ONESHOT_ARM_CC_MACRO__ +#define __MAC_QCU_ONESHOT_ARM_CC_MACRO__ + +/* macros for field CLEAR */ +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__SHIFT 0 +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WIDTH 10 +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MASK 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_QCU_ONESHOT_ARM_CC__TYPE u_int32_t +#define MAC_QCU_ONESHOT_ARM_CC__READ 0x000003ffU +#define MAC_QCU_ONESHOT_ARM_CC__WRITE 0x000003ffU + +#endif /* __MAC_QCU_ONESHOT_ARM_CC_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_ONESHOT_ARM_CC */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_ONESHOT_ARM_CC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_MISC */ +#ifndef __MAC_QCU_MISC_MACRO__ +#define __MAC_QCU_MISC_MACRO__ + +/* macros for field FSP */ +#define MAC_QCU_MISC__FSP__SHIFT 0 +#define MAC_QCU_MISC__FSP__WIDTH 4 +#define MAC_QCU_MISC__FSP__MASK 0x0000000fU +#define MAC_QCU_MISC__FSP__READ(src) (u_int32_t)(src) & 0x0000000fU +#define MAC_QCU_MISC__FSP__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define MAC_QCU_MISC__FSP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_QCU_MISC__FSP__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) + +/* macros for field ONESHOT_EN */ +#define MAC_QCU_MISC__ONESHOT_EN__SHIFT 4 +#define MAC_QCU_MISC__ONESHOT_EN__WIDTH 1 +#define MAC_QCU_MISC__ONESHOT_EN__MASK 0x00000010U +#define MAC_QCU_MISC__ONESHOT_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_QCU_MISC__ONESHOT_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_QCU_MISC__ONESHOT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_QCU_MISC__ONESHOT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_QCU_MISC__ONESHOT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_QCU_MISC__ONESHOT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field CBR_EXP_INC_DIS_NOFR */ +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__SHIFT 5 +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WIDTH 1 +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MASK 0x00000020U +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field CBR_EXP_INC_DIS_NOBCNFR */ +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__SHIFT 6 +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WIDTH 1 +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MASK 0x00000040U +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field IS_BCN */ +#define MAC_QCU_MISC__IS_BCN__SHIFT 7 +#define MAC_QCU_MISC__IS_BCN__WIDTH 1 +#define MAC_QCU_MISC__IS_BCN__MASK 0x00000080U +#define MAC_QCU_MISC__IS_BCN__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define MAC_QCU_MISC__IS_BCN__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_QCU_MISC__IS_BCN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_QCU_MISC__IS_BCN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_QCU_MISC__IS_BCN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_QCU_MISC__IS_BCN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field CBR_EXP_INC_LIMIT */ +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__SHIFT 8 +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WIDTH 1 +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MASK 0x00000100U +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field TXE_CLR_ON_CBR_END */ +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__SHIFT 9 +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WIDTH 1 +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MASK 0x00000200U +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field MMR_CBR_EXP_CNT_CLR_EN */ +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__SHIFT 10 +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WIDTH 1 +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MASK 0x00000400U +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field FR_ABORT_REQ_EN */ +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__SHIFT 11 +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__WIDTH 1 +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__MASK 0x00000800U +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_QCU_MISC__FR_ABORT_REQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) +#define MAC_QCU_MISC__TYPE u_int32_t +#define MAC_QCU_MISC__READ 0x00000fffU +#define MAC_QCU_MISC__WRITE 0x00000fffU + +#endif /* __MAC_QCU_MISC_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_MISC */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_MISC__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_CNT */ +#ifndef __MAC_QCU_CNT_MACRO__ +#define __MAC_QCU_CNT_MACRO__ + +/* macros for field FR_PEND */ +#define MAC_QCU_CNT__FR_PEND__SHIFT 0 +#define MAC_QCU_CNT__FR_PEND__WIDTH 2 +#define MAC_QCU_CNT__FR_PEND__MASK 0x00000003U +#define MAC_QCU_CNT__FR_PEND__READ(src) (u_int32_t)(src) & 0x00000003U + +/* macros for field CBR_EXP */ +#define MAC_QCU_CNT__CBR_EXP__SHIFT 8 +#define MAC_QCU_CNT__CBR_EXP__WIDTH 8 +#define MAC_QCU_CNT__CBR_EXP__MASK 0x0000ff00U +#define MAC_QCU_CNT__CBR_EXP__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define MAC_QCU_CNT__TYPE u_int32_t +#define MAC_QCU_CNT__READ 0x0000ff03U + +#endif /* __MAC_QCU_CNT_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_CNT */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_CNT__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_RDYTIME_SHDN */ +#ifndef __MAC_QCU_RDYTIME_SHDN_MACRO__ +#define __MAC_QCU_RDYTIME_SHDN_MACRO__ + +/* macros for field SHUTDOWN */ +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__SHIFT 0 +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WIDTH 10 +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MASK 0x000003ffU +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_QCU_RDYTIME_SHDN__TYPE u_int32_t +#define MAC_QCU_RDYTIME_SHDN__READ 0x000003ffU +#define MAC_QCU_RDYTIME_SHDN__WRITE 0x000003ffU +#define MAC_QCU_RDYTIME_SHDN__WOCLR 0x000003ffU + +#endif /* __MAC_QCU_RDYTIME_SHDN_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_RDYTIME_SHDN */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_RDYTIME_SHDN__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_QCU_DESC_CRC_CHK */ +#ifndef __MAC_QCU_DESC_CRC_CHK_MACRO__ +#define __MAC_QCU_DESC_CRC_CHK_MACRO__ + +/* macros for field EN */ +#define MAC_QCU_DESC_CRC_CHK__EN__SHIFT 0 +#define MAC_QCU_DESC_CRC_CHK__EN__WIDTH 1 +#define MAC_QCU_DESC_CRC_CHK__EN__MASK 0x00000001U +#define MAC_QCU_DESC_CRC_CHK__EN__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_QCU_DESC_CRC_CHK__EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_QCU_DESC_CRC_CHK__EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_QCU_DESC_CRC_CHK__EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_QCU_DESC_CRC_CHK__EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_QCU_DESC_CRC_CHK__EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define MAC_QCU_DESC_CRC_CHK__TYPE u_int32_t +#define MAC_QCU_DESC_CRC_CHK__READ 0x00000001U +#define MAC_QCU_DESC_CRC_CHK__WRITE 0x00000001U + +#endif /* __MAC_QCU_DESC_CRC_CHK_MACRO__ */ + + +/* macros for mac_qcu_reg_map.MAC_QCU_DESC_CRC_CHK */ +#define INST_MAC_QCU_REG_MAP__MAC_QCU_DESC_CRC_CHK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_QCUMASK */ +#ifndef __MAC_DCU_QCUMASK_MACRO__ +#define __MAC_DCU_QCUMASK_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_QCUMASK__DATA__SHIFT 0 +#define MAC_DCU_QCUMASK__DATA__WIDTH 10 +#define MAC_DCU_QCUMASK__DATA__MASK 0x000003ffU +#define MAC_DCU_QCUMASK__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DCU_QCUMASK__DATA__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DCU_QCUMASK__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DCU_QCUMASK__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define MAC_DCU_QCUMASK__TYPE u_int32_t +#define MAC_DCU_QCUMASK__READ 0x000003ffU +#define MAC_DCU_QCUMASK__WRITE 0x000003ffU + +#endif /* __MAC_DCU_QCUMASK_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_QCUMASK */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_QCUMASK__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_SIFS */ +#ifndef __MAC_DCU_GBL_IFS_SIFS_MACRO__ +#define __MAC_DCU_GBL_IFS_SIFS_MACRO__ + +/* macros for field DURATION */ +#define MAC_DCU_GBL_IFS_SIFS__DURATION__SHIFT 0 +#define MAC_DCU_GBL_IFS_SIFS__DURATION__WIDTH 16 +#define MAC_DCU_GBL_IFS_SIFS__DURATION__MASK 0x0000ffffU +#define MAC_DCU_GBL_IFS_SIFS__DURATION__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DCU_GBL_IFS_SIFS__DURATION__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DCU_GBL_IFS_SIFS__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DCU_GBL_IFS_SIFS__DURATION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DCU_GBL_IFS_SIFS__TYPE u_int32_t +#define MAC_DCU_GBL_IFS_SIFS__READ 0x0000ffffU +#define MAC_DCU_GBL_IFS_SIFS__WRITE 0x0000ffffU + +#endif /* __MAC_DCU_GBL_IFS_SIFS_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_SIFS */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_SIFS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_DCU0_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU0_31_0__READ 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_31_0__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_31_0 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU8_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_31_0 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_LCL_IFS */ +#ifndef __MAC_DCU_LCL_IFS_MACRO__ +#define __MAC_DCU_LCL_IFS_MACRO__ + +/* macros for field CW_MIN */ +#define MAC_DCU_LCL_IFS__CW_MIN__SHIFT 0 +#define MAC_DCU_LCL_IFS__CW_MIN__WIDTH 10 +#define MAC_DCU_LCL_IFS__CW_MIN__MASK 0x000003ffU +#define MAC_DCU_LCL_IFS__CW_MIN__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DCU_LCL_IFS__CW_MIN__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DCU_LCL_IFS__CW_MIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DCU_LCL_IFS__CW_MIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field CW_MAX */ +#define MAC_DCU_LCL_IFS__CW_MAX__SHIFT 10 +#define MAC_DCU_LCL_IFS__CW_MAX__WIDTH 10 +#define MAC_DCU_LCL_IFS__CW_MAX__MASK 0x000ffc00U +#define MAC_DCU_LCL_IFS__CW_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define MAC_DCU_LCL_IFS__CW_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define MAC_DCU_LCL_IFS__CW_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define MAC_DCU_LCL_IFS__CW_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field AIFS */ +#define MAC_DCU_LCL_IFS__AIFS__SHIFT 20 +#define MAC_DCU_LCL_IFS__AIFS__WIDTH 8 +#define MAC_DCU_LCL_IFS__AIFS__MASK 0x0ff00000U +#define MAC_DCU_LCL_IFS__AIFS__READ(src) \ + (((u_int32_t)(src)\ + & 0x0ff00000U) >> 20) +#define MAC_DCU_LCL_IFS__AIFS__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x0ff00000U) +#define MAC_DCU_LCL_IFS__AIFS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x0ff00000U) +#define MAC_DCU_LCL_IFS__AIFS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x0ff00000U))) + +/* macros for field LONG_AIFS */ +#define MAC_DCU_LCL_IFS__LONG_AIFS__SHIFT 28 +#define MAC_DCU_LCL_IFS__LONG_AIFS__WIDTH 1 +#define MAC_DCU_LCL_IFS__LONG_AIFS__MASK 0x10000000U +#define MAC_DCU_LCL_IFS__LONG_AIFS__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_DCU_LCL_IFS__LONG_AIFS__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_DCU_LCL_IFS__LONG_AIFS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_DCU_LCL_IFS__LONG_AIFS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_DCU_LCL_IFS__LONG_AIFS__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_DCU_LCL_IFS__LONG_AIFS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) +#define MAC_DCU_LCL_IFS__TYPE u_int32_t +#define MAC_DCU_LCL_IFS__READ 0x1fffffffU +#define MAC_DCU_LCL_IFS__WRITE 0x1fffffffU + +#endif /* __MAC_DCU_LCL_IFS_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_LCL_IFS */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_LCL_IFS__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_SLOT */ +#ifndef __MAC_DCU_GBL_IFS_SLOT_MACRO__ +#define __MAC_DCU_GBL_IFS_SLOT_MACRO__ + +/* macros for field DURATION */ +#define MAC_DCU_GBL_IFS_SLOT__DURATION__SHIFT 0 +#define MAC_DCU_GBL_IFS_SLOT__DURATION__WIDTH 16 +#define MAC_DCU_GBL_IFS_SLOT__DURATION__MASK 0x0000ffffU +#define MAC_DCU_GBL_IFS_SLOT__DURATION__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DCU_GBL_IFS_SLOT__DURATION__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DCU_GBL_IFS_SLOT__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DCU_GBL_IFS_SLOT__DURATION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DCU_GBL_IFS_SLOT__TYPE u_int32_t +#define MAC_DCU_GBL_IFS_SLOT__READ 0x0000ffffU +#define MAC_DCU_GBL_IFS_SLOT__WRITE 0x0000ffffU + +#endif /* __MAC_DCU_GBL_IFS_SLOT_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_SLOT */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_SLOT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_DCU0_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU0_63_32__READ 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_63_32__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_63_32 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU8_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_63_32 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_RETRY_LIMIT */ +#ifndef __MAC_DCU_RETRY_LIMIT_MACRO__ +#define __MAC_DCU_RETRY_LIMIT_MACRO__ + +/* macros for field FRFL */ +#define MAC_DCU_RETRY_LIMIT__FRFL__SHIFT 0 +#define MAC_DCU_RETRY_LIMIT__FRFL__WIDTH 4 +#define MAC_DCU_RETRY_LIMIT__FRFL__MASK 0x0000000fU +#define MAC_DCU_RETRY_LIMIT__FRFL__READ(src) (u_int32_t)(src) & 0x0000000fU +#define MAC_DCU_RETRY_LIMIT__FRFL__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define MAC_DCU_RETRY_LIMIT__FRFL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_DCU_RETRY_LIMIT__FRFL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field SRFL */ +#define MAC_DCU_RETRY_LIMIT__SRFL__SHIFT 8 +#define MAC_DCU_RETRY_LIMIT__SRFL__WIDTH 6 +#define MAC_DCU_RETRY_LIMIT__SRFL__MASK 0x00003f00U +#define MAC_DCU_RETRY_LIMIT__SRFL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define MAC_DCU_RETRY_LIMIT__SRFL__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define MAC_DCU_RETRY_LIMIT__SRFL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define MAC_DCU_RETRY_LIMIT__SRFL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field SDFL */ +#define MAC_DCU_RETRY_LIMIT__SDFL__SHIFT 14 +#define MAC_DCU_RETRY_LIMIT__SDFL__WIDTH 6 +#define MAC_DCU_RETRY_LIMIT__SDFL__MASK 0x000fc000U +#define MAC_DCU_RETRY_LIMIT__SDFL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) +#define MAC_DCU_RETRY_LIMIT__SDFL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x000fc000U) +#define MAC_DCU_RETRY_LIMIT__SDFL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x000fc000U) +#define MAC_DCU_RETRY_LIMIT__SDFL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x000fc000U))) +#define MAC_DCU_RETRY_LIMIT__TYPE u_int32_t +#define MAC_DCU_RETRY_LIMIT__READ 0x000fff0fU +#define MAC_DCU_RETRY_LIMIT__WRITE 0x000fff0fU + +#endif /* __MAC_DCU_RETRY_LIMIT_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_RETRY_LIMIT */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_RETRY_LIMIT__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_EIFS */ +#ifndef __MAC_DCU_GBL_IFS_EIFS_MACRO__ +#define __MAC_DCU_GBL_IFS_EIFS_MACRO__ + +/* macros for field DURATION */ +#define MAC_DCU_GBL_IFS_EIFS__DURATION__SHIFT 0 +#define MAC_DCU_GBL_IFS_EIFS__DURATION__WIDTH 16 +#define MAC_DCU_GBL_IFS_EIFS__DURATION__MASK 0x0000ffffU +#define MAC_DCU_GBL_IFS_EIFS__DURATION__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_DCU_GBL_IFS_EIFS__DURATION__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_DCU_GBL_IFS_EIFS__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DCU_GBL_IFS_EIFS__DURATION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DCU_GBL_IFS_EIFS__TYPE u_int32_t +#define MAC_DCU_GBL_IFS_EIFS__READ 0x0000ffffU +#define MAC_DCU_GBL_IFS_EIFS__WRITE 0x0000ffffU + +#endif /* __MAC_DCU_GBL_IFS_EIFS_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_EIFS */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_EIFS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_DCU0_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU0_95_64__READ 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_95_64__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_95_64 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU8_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_95_64 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_CHANNEL_TIME */ +#ifndef __MAC_DCU_CHANNEL_TIME_MACRO__ +#define __MAC_DCU_CHANNEL_TIME_MACRO__ + +/* macros for field DURATION */ +#define MAC_DCU_CHANNEL_TIME__DURATION__SHIFT 0 +#define MAC_DCU_CHANNEL_TIME__DURATION__WIDTH 20 +#define MAC_DCU_CHANNEL_TIME__DURATION__MASK 0x000fffffU +#define MAC_DCU_CHANNEL_TIME__DURATION__READ(src) \ + (u_int32_t)(src)\ + & 0x000fffffU +#define MAC_DCU_CHANNEL_TIME__DURATION__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000fffffU) +#define MAC_DCU_CHANNEL_TIME__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffffU) | ((u_int32_t)(src) &\ + 0x000fffffU) +#define MAC_DCU_CHANNEL_TIME__DURATION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000fffffU))) + +/* macros for field ENABLE */ +#define MAC_DCU_CHANNEL_TIME__ENABLE__SHIFT 20 +#define MAC_DCU_CHANNEL_TIME__ENABLE__WIDTH 1 +#define MAC_DCU_CHANNEL_TIME__ENABLE__MASK 0x00100000U +#define MAC_DCU_CHANNEL_TIME__ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_DCU_CHANNEL_TIME__ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_DCU_CHANNEL_TIME__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_DCU_CHANNEL_TIME__ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_DCU_CHANNEL_TIME__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_DCU_CHANNEL_TIME__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) +#define MAC_DCU_CHANNEL_TIME__TYPE u_int32_t +#define MAC_DCU_CHANNEL_TIME__READ 0x001fffffU +#define MAC_DCU_CHANNEL_TIME__WRITE 0x001fffffU + +#endif /* __MAC_DCU_CHANNEL_TIME_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_CHANNEL_TIME */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_CHANNEL_TIME__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_MISC */ +#ifndef __MAC_DCU_GBL_IFS_MISC_MACRO__ +#define __MAC_DCU_GBL_IFS_MISC_MACRO__ + +/* macros for field LFSR_SLICE_SEL */ +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__SHIFT 0 +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WIDTH 3 +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MASK 0x00000007U +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field TURBO_MODE */ +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__SHIFT 3 +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MASK 0x00000008U +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field SIFS_DUR_USEC */ +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__SHIFT 4 +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WIDTH 6 +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MASK 0x000003f0U +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field ARB_DLY */ +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__SHIFT 20 +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WIDTH 2 +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MASK 0x00300000U +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00300000U) >> 20) +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00300000U) +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((u_int32_t)(src) <<\ + 20) & 0x00300000U) +#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00300000U))) + +/* macros for field SIFS_RST_UNCOND */ +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__SHIFT 22 +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MASK 0x00400000U +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field AIFS_RST_UNCOND */ +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__SHIFT 23 +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MASK 0x00800000U +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field LFSR_SLICE_RANDOM_DIS */ +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__SHIFT 24 +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MASK 0x01000000U +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field CHAN_SLOT_WIN_DUR */ +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__SHIFT 25 +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WIDTH 2 +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MASK 0x06000000U +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field CHAN_SLOT_ALWAYS */ +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__SHIFT 27 +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MASK 0x08000000U +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field IGNORE_BACKOFF */ +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__SHIFT 28 +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MASK 0x10000000U +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field SLOT_COUNT_RST_UNCOND */ +#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__SHIFT 29 +#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__WIDTH 1 +#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__MASK 0x20000000U +#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define MAC_DCU_GBL_IFS_MISC__TYPE u_int32_t +#define MAC_DCU_GBL_IFS_MISC__READ 0x3ff003ffU +#define MAC_DCU_GBL_IFS_MISC__WRITE 0x3ff003ffU + +#endif /* __MAC_DCU_GBL_IFS_MISC_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_MISC */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_MISC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_DCU0_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU0_127_96__READ 0xffffffffU +#define MAC_DCU_TXFILTER_DCU0_127_96__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_127_96 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU8_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU8_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_127_96 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_MISC */ +#ifndef __MAC_DCU_MISC_MACRO__ +#define __MAC_DCU_MISC_MACRO__ + +/* macros for field BKOFF_THRESH */ +#define MAC_DCU_MISC__BKOFF_THRESH__SHIFT 0 +#define MAC_DCU_MISC__BKOFF_THRESH__WIDTH 6 +#define MAC_DCU_MISC__BKOFF_THRESH__MASK 0x0000003fU +#define MAC_DCU_MISC__BKOFF_THRESH__READ(src) (u_int32_t)(src) & 0x0000003fU +#define MAC_DCU_MISC__BKOFF_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define MAC_DCU_MISC__BKOFF_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define MAC_DCU_MISC__BKOFF_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field SFC_RST_AT_TS_END_EN */ +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__SHIFT 6 +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WIDTH 1 +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MASK 0x00000040U +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field CW_RST_AT_TS_END_DIS */ +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__SHIFT 7 +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WIDTH 1 +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MASK 0x00000080U +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field FRAG_BURST_WAIT_QCU_EN */ +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__SHIFT 8 +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WIDTH 1 +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MASK 0x00000100U +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field FRAG_BURST_BKOFF_EN */ +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__SHIFT 9 +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WIDTH 1 +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MASK 0x00000200U +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field HCF_POLL_EN */ +#define MAC_DCU_MISC__HCF_POLL_EN__SHIFT 11 +#define MAC_DCU_MISC__HCF_POLL_EN__WIDTH 1 +#define MAC_DCU_MISC__HCF_POLL_EN__MASK 0x00000800U +#define MAC_DCU_MISC__HCF_POLL_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_DCU_MISC__HCF_POLL_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_DCU_MISC__HCF_POLL_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_DCU_MISC__HCF_POLL_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_DCU_MISC__HCF_POLL_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_DCU_MISC__HCF_POLL_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field BKOFF_PF */ +#define MAC_DCU_MISC__BKOFF_PF__SHIFT 12 +#define MAC_DCU_MISC__BKOFF_PF__WIDTH 1 +#define MAC_DCU_MISC__BKOFF_PF__MASK 0x00001000U +#define MAC_DCU_MISC__BKOFF_PF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_DCU_MISC__BKOFF_PF__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_DCU_MISC__BKOFF_PF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_DCU_MISC__BKOFF_PF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_DCU_MISC__BKOFF_PF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_DCU_MISC__BKOFF_PF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field VIRT_COLL_POLICY */ +#define MAC_DCU_MISC__VIRT_COLL_POLICY__SHIFT 14 +#define MAC_DCU_MISC__VIRT_COLL_POLICY__WIDTH 2 +#define MAC_DCU_MISC__VIRT_COLL_POLICY__MASK 0x0000c000U +#define MAC_DCU_MISC__VIRT_COLL_POLICY__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define MAC_DCU_MISC__VIRT_COLL_POLICY__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define MAC_DCU_MISC__VIRT_COLL_POLICY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define MAC_DCU_MISC__VIRT_COLL_POLICY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field IS_BCN */ +#define MAC_DCU_MISC__IS_BCN__SHIFT 16 +#define MAC_DCU_MISC__IS_BCN__WIDTH 1 +#define MAC_DCU_MISC__IS_BCN__MASK 0x00010000U +#define MAC_DCU_MISC__IS_BCN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_DCU_MISC__IS_BCN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_DCU_MISC__IS_BCN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_DCU_MISC__IS_BCN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_DCU_MISC__IS_BCN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_DCU_MISC__IS_BCN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field ARB_LOCKOUT_IF_EN */ +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__SHIFT 17 +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WIDTH 1 +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MASK 0x00020000U +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field LOCKOUT_GBL_EN */ +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__SHIFT 18 +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__WIDTH 1 +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__MASK 0x00040000U +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_DCU_MISC__LOCKOUT_GBL_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field LOCKOUT_IGNORE */ +#define MAC_DCU_MISC__LOCKOUT_IGNORE__SHIFT 19 +#define MAC_DCU_MISC__LOCKOUT_IGNORE__WIDTH 1 +#define MAC_DCU_MISC__LOCKOUT_IGNORE__MASK 0x00080000U +#define MAC_DCU_MISC__LOCKOUT_IGNORE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_DCU_MISC__LOCKOUT_IGNORE__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_DCU_MISC__LOCKOUT_IGNORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_DCU_MISC__LOCKOUT_IGNORE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_DCU_MISC__LOCKOUT_IGNORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_DCU_MISC__LOCKOUT_IGNORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field SEQNUM_FREEZE */ +#define MAC_DCU_MISC__SEQNUM_FREEZE__SHIFT 20 +#define MAC_DCU_MISC__SEQNUM_FREEZE__WIDTH 1 +#define MAC_DCU_MISC__SEQNUM_FREEZE__MASK 0x00100000U +#define MAC_DCU_MISC__SEQNUM_FREEZE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_DCU_MISC__SEQNUM_FREEZE__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_DCU_MISC__SEQNUM_FREEZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_DCU_MISC__SEQNUM_FREEZE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_DCU_MISC__SEQNUM_FREEZE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_DCU_MISC__SEQNUM_FREEZE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field POST_BKOFF_SKIP */ +#define MAC_DCU_MISC__POST_BKOFF_SKIP__SHIFT 21 +#define MAC_DCU_MISC__POST_BKOFF_SKIP__WIDTH 1 +#define MAC_DCU_MISC__POST_BKOFF_SKIP__MASK 0x00200000U +#define MAC_DCU_MISC__POST_BKOFF_SKIP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_DCU_MISC__POST_BKOFF_SKIP__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_DCU_MISC__POST_BKOFF_SKIP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_DCU_MISC__POST_BKOFF_SKIP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_DCU_MISC__POST_BKOFF_SKIP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_DCU_MISC__POST_BKOFF_SKIP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field VIRT_COLL_CW_INC_EN */ +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__SHIFT 22 +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WIDTH 1 +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MASK 0x00400000U +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field RETRY_ON_BLOWN_IFS_EN */ +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__SHIFT 23 +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WIDTH 1 +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MASK 0x00800000U +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field SIFS_BURST_CHAN_BUSY_IGNORE */ +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__SHIFT 24 +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WIDTH 1 +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MASK 0x01000000U +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define MAC_DCU_MISC__TYPE u_int32_t +#define MAC_DCU_MISC__READ 0x01ffdbffU +#define MAC_DCU_MISC__WRITE 0x01ffdbffU + +#endif /* __MAC_DCU_MISC_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_MISC */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_MISC__NUM 10 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU1_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_31_0 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU9_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_31_0 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_SEQ */ +#ifndef __MAC_DCU_SEQ_MACRO__ +#define __MAC_DCU_SEQ_MACRO__ + +/* macros for field NUM */ +#define MAC_DCU_SEQ__NUM__SHIFT 0 +#define MAC_DCU_SEQ__NUM__WIDTH 32 +#define MAC_DCU_SEQ__NUM__MASK 0xffffffffU +#define MAC_DCU_SEQ__NUM__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DCU_SEQ__NUM__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DCU_SEQ__NUM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_SEQ__NUM__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define MAC_DCU_SEQ__TYPE u_int32_t +#define MAC_DCU_SEQ__READ 0xffffffffU +#define MAC_DCU_SEQ__WRITE 0xffffffffU + +#endif /* __MAC_DCU_SEQ_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_SEQ */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_SEQ__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU1_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_63_32 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU9_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_63_32 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU1_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_95_64 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU9_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_95_64 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU1_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU1_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_127_96 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU9_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU9_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_127_96 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU2_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_31_0 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_PAUSE */ +#ifndef __MAC_DCU_PAUSE_MACRO__ +#define __MAC_DCU_PAUSE_MACRO__ + +/* macros for field REQUEST */ +#define MAC_DCU_PAUSE__REQUEST__SHIFT 0 +#define MAC_DCU_PAUSE__REQUEST__WIDTH 10 +#define MAC_DCU_PAUSE__REQUEST__MASK 0x000003ffU +#define MAC_DCU_PAUSE__REQUEST__READ(src) (u_int32_t)(src) & 0x000003ffU +#define MAC_DCU_PAUSE__REQUEST__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define MAC_DCU_PAUSE__REQUEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define MAC_DCU_PAUSE__REQUEST__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field STATUS */ +#define MAC_DCU_PAUSE__STATUS__SHIFT 16 +#define MAC_DCU_PAUSE__STATUS__WIDTH 1 +#define MAC_DCU_PAUSE__STATUS__MASK 0x00010000U +#define MAC_DCU_PAUSE__STATUS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_DCU_PAUSE__STATUS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_DCU_PAUSE__STATUS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field SPARE */ +#define MAC_DCU_PAUSE__SPARE__SHIFT 17 +#define MAC_DCU_PAUSE__SPARE__WIDTH 4 +#define MAC_DCU_PAUSE__SPARE__MASK 0x001e0000U +#define MAC_DCU_PAUSE__SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0x001e0000U) >> 17) +#define MAC_DCU_PAUSE__SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x001e0000U) +#define MAC_DCU_PAUSE__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x001e0000U) +#define MAC_DCU_PAUSE__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x001e0000U))) +#define MAC_DCU_PAUSE__TYPE u_int32_t +#define MAC_DCU_PAUSE__READ 0x001f03ffU +#define MAC_DCU_PAUSE__WRITE 0x001f03ffU + +#endif /* __MAC_DCU_PAUSE_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_PAUSE */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_PAUSE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU2_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_63_32 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_WOW_KACFG */ +#ifndef __MAC_DCU_WOW_KACFG_MACRO__ +#define __MAC_DCU_WOW_KACFG_MACRO__ + +/* macros for field TX_EN */ +#define MAC_DCU_WOW_KACFG__TX_EN__SHIFT 0 +#define MAC_DCU_WOW_KACFG__TX_EN__WIDTH 1 +#define MAC_DCU_WOW_KACFG__TX_EN__MASK 0x00000001U +#define MAC_DCU_WOW_KACFG__TX_EN__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_DCU_WOW_KACFG__TX_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_DCU_WOW_KACFG__TX_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_DCU_WOW_KACFG__TX_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_DCU_WOW_KACFG__TX_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_DCU_WOW_KACFG__TX_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field TIM_EN */ +#define MAC_DCU_WOW_KACFG__TIM_EN__SHIFT 1 +#define MAC_DCU_WOW_KACFG__TIM_EN__WIDTH 1 +#define MAC_DCU_WOW_KACFG__TIM_EN__MASK 0x00000002U +#define MAC_DCU_WOW_KACFG__TIM_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_DCU_WOW_KACFG__TIM_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_DCU_WOW_KACFG__TIM_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_DCU_WOW_KACFG__TIM_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_DCU_WOW_KACFG__TIM_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_DCU_WOW_KACFG__TIM_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field BCN_CNT */ +#define MAC_DCU_WOW_KACFG__BCN_CNT__SHIFT 4 +#define MAC_DCU_WOW_KACFG__BCN_CNT__WIDTH 8 +#define MAC_DCU_WOW_KACFG__BCN_CNT__MASK 0x00000ff0U +#define MAC_DCU_WOW_KACFG__BCN_CNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000ff0U) >> 4) +#define MAC_DCU_WOW_KACFG__BCN_CNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000ff0U) +#define MAC_DCU_WOW_KACFG__BCN_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000ff0U) | (((u_int32_t)(src) <<\ + 4) & 0x00000ff0U) +#define MAC_DCU_WOW_KACFG__BCN_CNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000ff0U))) + +/* macros for field RX_TIMEOUT_CNT */ +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__SHIFT 12 +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WIDTH 12 +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MASK 0x00fff000U +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fff000U) >> 12) +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00fff000U) +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fff000U) | (((u_int32_t)(src) <<\ + 12) & 0x00fff000U) +#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00fff000U))) +#define MAC_DCU_WOW_KACFG__TYPE u_int32_t +#define MAC_DCU_WOW_KACFG__READ 0x00fffff3U +#define MAC_DCU_WOW_KACFG__WRITE 0x00fffff3U + +#endif /* __MAC_DCU_WOW_KACFG_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_WOW_KACFG */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_WOW_KACFG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU2_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_95_64 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXSLOT */ +#ifndef __MAC_DCU_TXSLOT_MACRO__ +#define __MAC_DCU_TXSLOT_MACRO__ + +/* macros for field MASK */ +#define MAC_DCU_TXSLOT__MASK__SHIFT 0 +#define MAC_DCU_TXSLOT__MASK__WIDTH 16 +#define MAC_DCU_TXSLOT__MASK__MASK 0x0000ffffU +#define MAC_DCU_TXSLOT__MASK__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_DCU_TXSLOT__MASK__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_DCU_TXSLOT__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_DCU_TXSLOT__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_DCU_TXSLOT__TYPE u_int32_t +#define MAC_DCU_TXSLOT__READ 0x0000ffffU +#define MAC_DCU_TXSLOT__WRITE 0x0000ffffU + +#endif /* __MAC_DCU_TXSLOT_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXSLOT */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXSLOT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU2_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU2_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_127_96 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU3_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_31_0 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU3_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_63_32 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU3_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_95_64 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU3_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU3_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_127_96 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU4_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_31_0 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_CLEAR */ +#ifndef __MAC_DCU_TXFILTER_CLEAR_MACRO__ +#define __MAC_DCU_TXFILTER_CLEAR_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_CLEAR__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_CLEAR__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_CLEAR__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_CLEAR__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DCU_TXFILTER_CLEAR__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_DCU_TXFILTER_CLEAR__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_CLEAR__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_CLEAR__TYPE u_int32_t +#define MAC_DCU_TXFILTER_CLEAR__READ 0xffffffffU +#define MAC_DCU_TXFILTER_CLEAR__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_CLEAR_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_CLEAR */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_CLEAR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU4_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_63_32 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_SET */ +#ifndef __MAC_DCU_TXFILTER_SET_MACRO__ +#define __MAC_DCU_TXFILTER_SET_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_SET__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_SET__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_SET__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_SET__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_DCU_TXFILTER_SET__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_DCU_TXFILTER_SET__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_DCU_TXFILTER_SET__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_DCU_TXFILTER_SET__TYPE u_int32_t +#define MAC_DCU_TXFILTER_SET__READ 0xffffffffU +#define MAC_DCU_TXFILTER_SET__WRITE 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_SET_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_SET */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_SET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU4_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_95_64 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU4_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU4_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_127_96 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU5_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_31_0 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU5_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_63_32 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU5_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_95_64 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU5_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU5_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_127_96 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU6_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_31_0 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU6_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_63_32 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU6_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_95_64 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU6_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU6_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_127_96 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_31_0 */ +#ifndef __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__ +#define __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_31_0__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU7_31_0__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_31_0 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_31_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_63_32 */ +#ifndef __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__ +#define __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_63_32__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU7_63_32__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_63_32 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_63_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_95_64 */ +#ifndef __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__ +#define __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_95_64__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU7_95_64__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_95_64 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_95_64__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_127_96 */ +#ifndef __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__ +#define __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__ + +/* macros for field DATA */ +#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__SHIFT 0 +#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__WIDTH 32 +#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__MASK 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_DCU_TXFILTER_DCU7_127_96__TYPE u_int32_t +#define MAC_DCU_TXFILTER_DCU7_127_96__READ 0xffffffffU + +#endif /* __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_127_96 */ +#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_127_96__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_SLEEP_STATUS */ +#ifndef __MAC_SLEEP_STATUS_MACRO__ +#define __MAC_SLEEP_STATUS_MACRO__ + +/* macros for field DATA */ +#define MAC_SLEEP_STATUS__DATA__SHIFT 0 +#define MAC_SLEEP_STATUS__DATA__WIDTH 32 +#define MAC_SLEEP_STATUS__DATA__MASK 0xffffffffU +#define MAC_SLEEP_STATUS__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_SLEEP_STATUS__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_SLEEP_STATUS__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_SLEEP_STATUS__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_SLEEP_STATUS__TYPE u_int32_t +#define MAC_SLEEP_STATUS__READ 0xffffffffU +#define MAC_SLEEP_STATUS__WRITE 0xffffffffU + +#endif /* __MAC_SLEEP_STATUS_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_SLEEP_STATUS */ +#define INST_MAC_DCU_REG_MAP__MAC_SLEEP_STATUS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_LED_CONFIG */ +#ifndef __MAC_LED_CONFIG_MACRO__ +#define __MAC_LED_CONFIG_MACRO__ + +/* macros for field DATA */ +#define MAC_LED_CONFIG__DATA__SHIFT 0 +#define MAC_LED_CONFIG__DATA__WIDTH 32 +#define MAC_LED_CONFIG__DATA__MASK 0xffffffffU +#define MAC_LED_CONFIG__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_LED_CONFIG__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_LED_CONFIG__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_LED_CONFIG__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_LED_CONFIG__TYPE u_int32_t +#define MAC_LED_CONFIG__READ 0xffffffffU +#define MAC_LED_CONFIG__WRITE 0xffffffffU + +#endif /* __MAC_LED_CONFIG_MACRO__ */ + + +/* macros for mac_dcu_reg_map.MAC_LED_CONFIG */ +#define INST_MAC_DCU_REG_MAP__MAC_LED_CONFIG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RESET_CONTROL */ +#ifndef __RESET_CONTROL_MACRO__ +#define __RESET_CONTROL_MACRO__ + +/* macros for field MAC_WARM_RST */ +#define RESET_CONTROL__MAC_WARM_RST__SHIFT 0 +#define RESET_CONTROL__MAC_WARM_RST__WIDTH 1 +#define RESET_CONTROL__MAC_WARM_RST__MASK 0x00000001U +#define RESET_CONTROL__MAC_WARM_RST__READ(src) (u_int32_t)(src) & 0x00000001U +#define RESET_CONTROL__MAC_WARM_RST__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RESET_CONTROL__MAC_WARM_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RESET_CONTROL__MAC_WARM_RST__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RESET_CONTROL__MAC_WARM_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RESET_CONTROL__MAC_WARM_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field MAC_COLD_RST */ +#define RESET_CONTROL__MAC_COLD_RST__SHIFT 1 +#define RESET_CONTROL__MAC_COLD_RST__WIDTH 1 +#define RESET_CONTROL__MAC_COLD_RST__MASK 0x00000002U +#define RESET_CONTROL__MAC_COLD_RST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RESET_CONTROL__MAC_COLD_RST__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RESET_CONTROL__MAC_COLD_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RESET_CONTROL__MAC_COLD_RST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RESET_CONTROL__MAC_COLD_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RESET_CONTROL__MAC_COLD_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field WARM_RST */ +#define RESET_CONTROL__WARM_RST__SHIFT 2 +#define RESET_CONTROL__WARM_RST__WIDTH 1 +#define RESET_CONTROL__WARM_RST__MASK 0x00000004U +#define RESET_CONTROL__WARM_RST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RESET_CONTROL__WARM_RST__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RESET_CONTROL__WARM_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RESET_CONTROL__WARM_RST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RESET_CONTROL__WARM_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RESET_CONTROL__WARM_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field COLD_RST */ +#define RESET_CONTROL__COLD_RST__SHIFT 3 +#define RESET_CONTROL__COLD_RST__WIDTH 1 +#define RESET_CONTROL__COLD_RST__MASK 0x00000008U +#define RESET_CONTROL__COLD_RST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RESET_CONTROL__COLD_RST__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RESET_CONTROL__COLD_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RESET_CONTROL__COLD_RST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RESET_CONTROL__COLD_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RESET_CONTROL__COLD_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define RESET_CONTROL__TYPE u_int32_t +#define RESET_CONTROL__READ 0x0000000fU +#define RESET_CONTROL__WRITE 0x0000000fU + +#endif /* __RESET_CONTROL_MACRO__ */ + + +/* macros for rtc_reg_map.RESET_CONTROL */ +#define INST_RTC_REG_MAP__RESET_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::XTAL_CONTROL */ +#ifndef __XTAL_CONTROL_MACRO__ +#define __XTAL_CONTROL_MACRO__ + +/* macros for field TCXO */ +#define XTAL_CONTROL__TCXO__SHIFT 0 +#define XTAL_CONTROL__TCXO__WIDTH 1 +#define XTAL_CONTROL__TCXO__MASK 0x00000001U +#define XTAL_CONTROL__TCXO__READ(src) (u_int32_t)(src) & 0x00000001U +#define XTAL_CONTROL__TCXO__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define XTAL_CONTROL__TCXO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define XTAL_CONTROL__TCXO__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define XTAL_CONTROL__TCXO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define XTAL_CONTROL__TCXO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define XTAL_CONTROL__TYPE u_int32_t +#define XTAL_CONTROL__READ 0x00000001U +#define XTAL_CONTROL__WRITE 0x00000001U + +#endif /* __XTAL_CONTROL_MACRO__ */ + + +/* macros for rtc_reg_map.XTAL_CONTROL */ +#define INST_RTC_REG_MAP__XTAL_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::REG_CONTROL0 */ +#ifndef __REG_CONTROL0_MACRO__ +#define __REG_CONTROL0_MACRO__ + +/* macros for field SWREG_BITS */ +#define REG_CONTROL0__SWREG_BITS__SHIFT 0 +#define REG_CONTROL0__SWREG_BITS__WIDTH 32 +#define REG_CONTROL0__SWREG_BITS__MASK 0xffffffffU +#define REG_CONTROL0__SWREG_BITS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define REG_CONTROL0__SWREG_BITS__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define REG_CONTROL0__SWREG_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define REG_CONTROL0__SWREG_BITS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define REG_CONTROL0__TYPE u_int32_t +#define REG_CONTROL0__READ 0xffffffffU +#define REG_CONTROL0__WRITE 0xffffffffU + +#endif /* __REG_CONTROL0_MACRO__ */ + + +/* macros for rtc_reg_map.REG_CONTROL0 */ +#define INST_RTC_REG_MAP__REG_CONTROL0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::REG_CONTROL1 */ +#ifndef __REG_CONTROL1_MACRO__ +#define __REG_CONTROL1_MACRO__ + +/* macros for field SWREG_PROGRAM */ +#define REG_CONTROL1__SWREG_PROGRAM__SHIFT 0 +#define REG_CONTROL1__SWREG_PROGRAM__WIDTH 1 +#define REG_CONTROL1__SWREG_PROGRAM__MASK 0x00000001U +#define REG_CONTROL1__SWREG_PROGRAM__READ(src) (u_int32_t)(src) & 0x00000001U +#define REG_CONTROL1__SWREG_PROGRAM__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define REG_CONTROL1__SWREG_PROGRAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define REG_CONTROL1__SWREG_PROGRAM__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define REG_CONTROL1__SWREG_PROGRAM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define REG_CONTROL1__SWREG_PROGRAM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field OTPREG_LVL */ +#define REG_CONTROL1__OTPREG_LVL__SHIFT 1 +#define REG_CONTROL1__OTPREG_LVL__WIDTH 2 +#define REG_CONTROL1__OTPREG_LVL__MASK 0x00000006U +#define REG_CONTROL1__OTPREG_LVL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000006U) >> 1) +#define REG_CONTROL1__OTPREG_LVL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000006U) +#define REG_CONTROL1__OTPREG_LVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000006U) | (((u_int32_t)(src) <<\ + 1) & 0x00000006U) +#define REG_CONTROL1__OTPREG_LVL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000006U))) +#define REG_CONTROL1__TYPE u_int32_t +#define REG_CONTROL1__READ 0x00000007U +#define REG_CONTROL1__WRITE 0x00000007U + +#endif /* __REG_CONTROL1_MACRO__ */ + + +/* macros for rtc_reg_map.REG_CONTROL1 */ +#define INST_RTC_REG_MAP__REG_CONTROL1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::QUADRATURE */ +#ifndef __QUADRATURE_MACRO__ +#define __QUADRATURE_MACRO__ + +/* macros for field DAC */ +#define QUADRATURE__DAC__SHIFT 0 +#define QUADRATURE__DAC__WIDTH 3 +#define QUADRATURE__DAC__MASK 0x00000007U +#define QUADRATURE__DAC__READ(src) (u_int32_t)(src) & 0x00000007U +#define QUADRATURE__DAC__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define QUADRATURE__DAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define QUADRATURE__DAC__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) + +/* macros for field ADC */ +#define QUADRATURE__ADC__SHIFT 4 +#define QUADRATURE__ADC__WIDTH 4 +#define QUADRATURE__ADC__MASK 0x000000f0U +#define QUADRATURE__ADC__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) +#define QUADRATURE__ADC__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) +#define QUADRATURE__ADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define QUADRATURE__ADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) +#define QUADRATURE__TYPE u_int32_t +#define QUADRATURE__READ 0x000000f7U +#define QUADRATURE__WRITE 0x000000f7U + +#endif /* __QUADRATURE_MACRO__ */ + + +/* macros for rtc_reg_map.QUADRATURE */ +#define INST_RTC_REG_MAP__QUADRATURE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PLL_CONTROL */ +#ifndef __PLL_CONTROL_MACRO__ +#define __PLL_CONTROL_MACRO__ + +/* macros for field DIV_INT */ +#define PLL_CONTROL__DIV_INT__SHIFT 0 +#define PLL_CONTROL__DIV_INT__WIDTH 6 +#define PLL_CONTROL__DIV_INT__MASK 0x0000003fU +#define PLL_CONTROL__DIV_INT__READ(src) (u_int32_t)(src) & 0x0000003fU +#define PLL_CONTROL__DIV_INT__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define PLL_CONTROL__DIV_INT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define PLL_CONTROL__DIV_INT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field DIV_FRAC */ +#define PLL_CONTROL__DIV_FRAC__SHIFT 6 +#define PLL_CONTROL__DIV_FRAC__WIDTH 14 +#define PLL_CONTROL__DIV_FRAC__MASK 0x000fffc0U +#define PLL_CONTROL__DIV_FRAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fffc0U) >> 6) +#define PLL_CONTROL__DIV_FRAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000fffc0U) +#define PLL_CONTROL__DIV_FRAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffc0U) | (((u_int32_t)(src) <<\ + 6) & 0x000fffc0U) +#define PLL_CONTROL__DIV_FRAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000fffc0U))) + +/* macros for field REFDIV */ +#define PLL_CONTROL__REFDIV__SHIFT 20 +#define PLL_CONTROL__REFDIV__WIDTH 5 +#define PLL_CONTROL__REFDIV__MASK 0x01f00000U +#define PLL_CONTROL__REFDIV__READ(src) (((u_int32_t)(src) & 0x01f00000U) >> 20) +#define PLL_CONTROL__REFDIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define PLL_CONTROL__REFDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define PLL_CONTROL__REFDIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field CLK_SEL */ +#define PLL_CONTROL__CLK_SEL__SHIFT 25 +#define PLL_CONTROL__CLK_SEL__WIDTH 2 +#define PLL_CONTROL__CLK_SEL__MASK 0x06000000U +#define PLL_CONTROL__CLK_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define PLL_CONTROL__CLK_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define PLL_CONTROL__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define PLL_CONTROL__CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field BYPASS */ +#define PLL_CONTROL__BYPASS__SHIFT 27 +#define PLL_CONTROL__BYPASS__WIDTH 1 +#define PLL_CONTROL__BYPASS__MASK 0x08000000U +#define PLL_CONTROL__BYPASS__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) +#define PLL_CONTROL__BYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define PLL_CONTROL__BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define PLL_CONTROL__BYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define PLL_CONTROL__BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define PLL_CONTROL__BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field UPDATING */ +#define PLL_CONTROL__UPDATING__SHIFT 28 +#define PLL_CONTROL__UPDATING__WIDTH 1 +#define PLL_CONTROL__UPDATING__MASK 0x10000000U +#define PLL_CONTROL__UPDATING__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define PLL_CONTROL__UPDATING__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define PLL_CONTROL__UPDATING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field NOPWD */ +#define PLL_CONTROL__NOPWD__SHIFT 29 +#define PLL_CONTROL__NOPWD__WIDTH 1 +#define PLL_CONTROL__NOPWD__MASK 0x20000000U +#define PLL_CONTROL__NOPWD__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define PLL_CONTROL__NOPWD__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define PLL_CONTROL__NOPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define PLL_CONTROL__NOPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define PLL_CONTROL__NOPWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define PLL_CONTROL__NOPWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field MAC_OVERRIDE */ +#define PLL_CONTROL__MAC_OVERRIDE__SHIFT 30 +#define PLL_CONTROL__MAC_OVERRIDE__WIDTH 1 +#define PLL_CONTROL__MAC_OVERRIDE__MASK 0x40000000U +#define PLL_CONTROL__MAC_OVERRIDE__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define PLL_CONTROL__MAC_OVERRIDE__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define PLL_CONTROL__MAC_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define PLL_CONTROL__MAC_OVERRIDE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define PLL_CONTROL__MAC_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define PLL_CONTROL__MAC_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define PLL_CONTROL__TYPE u_int32_t +#define PLL_CONTROL__READ 0x7fffffffU +#define PLL_CONTROL__WRITE 0x7fffffffU + +#endif /* __PLL_CONTROL_MACRO__ */ + + +/* macros for rtc_reg_map.PLL_CONTROL */ +#define INST_RTC_REG_MAP__PLL_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PLL_SETTLE */ +#ifndef __PLL_SETTLE_MACRO__ +#define __PLL_SETTLE_MACRO__ + +/* macros for field TIME */ +#define PLL_SETTLE__TIME__SHIFT 0 +#define PLL_SETTLE__TIME__WIDTH 11 +#define PLL_SETTLE__TIME__MASK 0x000007ffU +#define PLL_SETTLE__TIME__READ(src) (u_int32_t)(src) & 0x000007ffU +#define PLL_SETTLE__TIME__WRITE(src) ((u_int32_t)(src) & 0x000007ffU) +#define PLL_SETTLE__TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define PLL_SETTLE__TIME__VERIFY(src) (!(((u_int32_t)(src) & ~0x000007ffU))) +#define PLL_SETTLE__TYPE u_int32_t +#define PLL_SETTLE__READ 0x000007ffU +#define PLL_SETTLE__WRITE 0x000007ffU + +#endif /* __PLL_SETTLE_MACRO__ */ + + +/* macros for rtc_reg_map.PLL_SETTLE */ +#define INST_RTC_REG_MAP__PLL_SETTLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::XTAL_SETTLE */ +#ifndef __XTAL_SETTLE_MACRO__ +#define __XTAL_SETTLE_MACRO__ + +/* macros for field TIME */ +#define XTAL_SETTLE__TIME__SHIFT 0 +#define XTAL_SETTLE__TIME__WIDTH 7 +#define XTAL_SETTLE__TIME__MASK 0x0000007fU +#define XTAL_SETTLE__TIME__READ(src) (u_int32_t)(src) & 0x0000007fU +#define XTAL_SETTLE__TIME__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) +#define XTAL_SETTLE__TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define XTAL_SETTLE__TIME__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU))) +#define XTAL_SETTLE__TYPE u_int32_t +#define XTAL_SETTLE__READ 0x0000007fU +#define XTAL_SETTLE__WRITE 0x0000007fU + +#endif /* __XTAL_SETTLE_MACRO__ */ + + +/* macros for rtc_reg_map.XTAL_SETTLE */ +#define INST_RTC_REG_MAP__XTAL_SETTLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::CLOCK_OUT */ +#ifndef __CLOCK_OUT_MACRO__ +#define __CLOCK_OUT_MACRO__ + +/* macros for field SELECT */ +#define CLOCK_OUT__SELECT__SHIFT 0 +#define CLOCK_OUT__SELECT__WIDTH 4 +#define CLOCK_OUT__SELECT__MASK 0x0000000fU +#define CLOCK_OUT__SELECT__READ(src) (u_int32_t)(src) & 0x0000000fU +#define CLOCK_OUT__SELECT__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define CLOCK_OUT__SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CLOCK_OUT__SELECT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) + +/* macros for field DELAY */ +#define CLOCK_OUT__DELAY__SHIFT 4 +#define CLOCK_OUT__DELAY__WIDTH 3 +#define CLOCK_OUT__DELAY__MASK 0x00000070U +#define CLOCK_OUT__DELAY__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4) +#define CLOCK_OUT__DELAY__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000070U) +#define CLOCK_OUT__DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define CLOCK_OUT__DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) +#define CLOCK_OUT__TYPE u_int32_t +#define CLOCK_OUT__READ 0x0000007fU +#define CLOCK_OUT__WRITE 0x0000007fU + +#endif /* __CLOCK_OUT_MACRO__ */ + + +/* macros for rtc_reg_map.CLOCK_OUT */ +#define INST_RTC_REG_MAP__CLOCK_OUT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BIAS_OVERRIDE */ +#ifndef __BIAS_OVERRIDE_MACRO__ +#define __BIAS_OVERRIDE_MACRO__ + +/* macros for field ON */ +#define BIAS_OVERRIDE__ON__SHIFT 0 +#define BIAS_OVERRIDE__ON__WIDTH 1 +#define BIAS_OVERRIDE__ON__MASK 0x00000001U +#define BIAS_OVERRIDE__ON__READ(src) (u_int32_t)(src) & 0x00000001U +#define BIAS_OVERRIDE__ON__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define BIAS_OVERRIDE__ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BIAS_OVERRIDE__ON__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define BIAS_OVERRIDE__ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BIAS_OVERRIDE__ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define BIAS_OVERRIDE__TYPE u_int32_t +#define BIAS_OVERRIDE__READ 0x00000001U +#define BIAS_OVERRIDE__WRITE 0x00000001U + +#endif /* __BIAS_OVERRIDE_MACRO__ */ + + +/* macros for rtc_reg_map.BIAS_OVERRIDE */ +#define INST_RTC_REG_MAP__BIAS_OVERRIDE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RESET_CAUSE */ +#ifndef __RESET_CAUSE_MACRO__ +#define __RESET_CAUSE_MACRO__ + +/* macros for field LAST */ +#define RESET_CAUSE__LAST__SHIFT 0 +#define RESET_CAUSE__LAST__WIDTH 2 +#define RESET_CAUSE__LAST__MASK 0x00000003U +#define RESET_CAUSE__LAST__READ(src) (u_int32_t)(src) & 0x00000003U +#define RESET_CAUSE__TYPE u_int32_t +#define RESET_CAUSE__READ 0x00000003U + +#endif /* __RESET_CAUSE_MACRO__ */ + + +/* macros for rtc_reg_map.RESET_CAUSE */ +#define INST_RTC_REG_MAP__RESET_CAUSE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYSTEM_SLEEP */ +#ifndef __SYSTEM_SLEEP_MACRO__ +#define __SYSTEM_SLEEP_MACRO__ + +/* macros for field DISABLE */ +#define SYSTEM_SLEEP__DISABLE__SHIFT 0 +#define SYSTEM_SLEEP__DISABLE__WIDTH 1 +#define SYSTEM_SLEEP__DISABLE__MASK 0x00000001U +#define SYSTEM_SLEEP__DISABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYSTEM_SLEEP__DISABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define SYSTEM_SLEEP__DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYSTEM_SLEEP__DISABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SYSTEM_SLEEP__DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYSTEM_SLEEP__DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LIGHT */ +#define SYSTEM_SLEEP__LIGHT__SHIFT 1 +#define SYSTEM_SLEEP__LIGHT__WIDTH 1 +#define SYSTEM_SLEEP__LIGHT__MASK 0x00000002U +#define SYSTEM_SLEEP__LIGHT__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define SYSTEM_SLEEP__LIGHT__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define SYSTEM_SLEEP__LIGHT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define SYSTEM_SLEEP__LIGHT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define SYSTEM_SLEEP__LIGHT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define SYSTEM_SLEEP__LIGHT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field MAC_IF */ +#define SYSTEM_SLEEP__MAC_IF__SHIFT 2 +#define SYSTEM_SLEEP__MAC_IF__WIDTH 1 +#define SYSTEM_SLEEP__MAC_IF__MASK 0x00000004U +#define SYSTEM_SLEEP__MAC_IF__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define SYSTEM_SLEEP__MAC_IF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define SYSTEM_SLEEP__MAC_IF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define SYSTEM_SLEEP__TYPE u_int32_t +#define SYSTEM_SLEEP__READ 0x00000007U +#define SYSTEM_SLEEP__WRITE 0x00000007U + +#endif /* __SYSTEM_SLEEP_MACRO__ */ + + +/* macros for rtc_reg_map.SYSTEM_SLEEP */ +#define INST_RTC_REG_MAP__SYSTEM_SLEEP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_SLEEP_CONTROL */ +#ifndef __MAC_SLEEP_CONTROL_MACRO__ +#define __MAC_SLEEP_CONTROL_MACRO__ + +/* macros for field ENABLE */ +#define MAC_SLEEP_CONTROL__ENABLE__SHIFT 0 +#define MAC_SLEEP_CONTROL__ENABLE__WIDTH 2 +#define MAC_SLEEP_CONTROL__ENABLE__MASK 0x00000003U +#define MAC_SLEEP_CONTROL__ENABLE__READ(src) (u_int32_t)(src) & 0x00000003U +#define MAC_SLEEP_CONTROL__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define MAC_SLEEP_CONTROL__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define MAC_SLEEP_CONTROL__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) +#define MAC_SLEEP_CONTROL__TYPE u_int32_t +#define MAC_SLEEP_CONTROL__READ 0x00000003U +#define MAC_SLEEP_CONTROL__WRITE 0x00000003U + +#endif /* __MAC_SLEEP_CONTROL_MACRO__ */ + + +/* macros for rtc_reg_map.MAC_SLEEP_CONTROL */ +#define INST_RTC_REG_MAP__MAC_SLEEP_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::KEEP_AWAKE */ +#ifndef __KEEP_AWAKE_MACRO__ +#define __KEEP_AWAKE_MACRO__ + +/* macros for field COUNT */ +#define KEEP_AWAKE__COUNT__SHIFT 0 +#define KEEP_AWAKE__COUNT__WIDTH 8 +#define KEEP_AWAKE__COUNT__MASK 0x000000ffU +#define KEEP_AWAKE__COUNT__READ(src) (u_int32_t)(src) & 0x000000ffU +#define KEEP_AWAKE__COUNT__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define KEEP_AWAKE__COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define KEEP_AWAKE__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) +#define KEEP_AWAKE__TYPE u_int32_t +#define KEEP_AWAKE__READ 0x000000ffU +#define KEEP_AWAKE__WRITE 0x000000ffU + +#endif /* __KEEP_AWAKE_MACRO__ */ + + +/* macros for rtc_reg_map.KEEP_AWAKE */ +#define INST_RTC_REG_MAP__KEEP_AWAKE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DERIVED_RTC_CLK */ +#ifndef __DERIVED_RTC_CLK_MACRO__ +#define __DERIVED_RTC_CLK_MACRO__ + +/* macros for field PERIOD */ +#define DERIVED_RTC_CLK__PERIOD__SHIFT 1 +#define DERIVED_RTC_CLK__PERIOD__WIDTH 15 +#define DERIVED_RTC_CLK__PERIOD__MASK 0x0000fffeU +#define DERIVED_RTC_CLK__PERIOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fffeU) >> 1) +#define DERIVED_RTC_CLK__PERIOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000fffeU) +#define DERIVED_RTC_CLK__PERIOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fffeU) | (((u_int32_t)(src) <<\ + 1) & 0x0000fffeU) +#define DERIVED_RTC_CLK__PERIOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000fffeU))) + +/* macros for field EXTERNAL_DETECT */ +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__SHIFT 18 +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__WIDTH 1 +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__MASK 0x00040000U +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define DERIVED_RTC_CLK__EXTERNAL_DETECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) +#define DERIVED_RTC_CLK__TYPE u_int32_t +#define DERIVED_RTC_CLK__READ 0x0004fffeU +#define DERIVED_RTC_CLK__WRITE 0x0004fffeU + +#endif /* __DERIVED_RTC_CLK_MACRO__ */ + + +/* macros for rtc_reg_map.DERIVED_RTC_CLK */ +#define INST_RTC_REG_MAP__DERIVED_RTC_CLK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PLL_CONTROL2 */ +#ifndef __PLL_CONTROL2_MACRO__ +#define __PLL_CONTROL2_MACRO__ + +/* macros for field DIV_INT */ +#define PLL_CONTROL2__DIV_INT__SHIFT 0 +#define PLL_CONTROL2__DIV_INT__WIDTH 3 +#define PLL_CONTROL2__DIV_INT__MASK 0x00000007U +#define PLL_CONTROL2__DIV_INT__READ(src) (u_int32_t)(src) & 0x00000007U +#define PLL_CONTROL2__DIV_INT__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define PLL_CONTROL2__DIV_INT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define PLL_CONTROL2__DIV_INT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field DIV_FRAC */ +#define PLL_CONTROL2__DIV_FRAC__SHIFT 3 +#define PLL_CONTROL2__DIV_FRAC__WIDTH 4 +#define PLL_CONTROL2__DIV_FRAC__MASK 0x00000078U +#define PLL_CONTROL2__DIV_FRAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000078U) >> 3) +#define PLL_CONTROL2__DIV_FRAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000078U) +#define PLL_CONTROL2__DIV_FRAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000078U) | (((u_int32_t)(src) <<\ + 3) & 0x00000078U) +#define PLL_CONTROL2__DIV_FRAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000078U))) +#define PLL_CONTROL2__TYPE u_int32_t +#define PLL_CONTROL2__READ 0x0000007fU +#define PLL_CONTROL2__WRITE 0x0000007fU + +#endif /* __PLL_CONTROL2_MACRO__ */ + + +/* macros for rtc_reg_map.PLL_CONTROL2 */ +#define INST_RTC_REG_MAP__PLL_CONTROL2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_RESET */ +#ifndef __RTC_SYNC_RESET_MACRO__ +#define __RTC_SYNC_RESET_MACRO__ + +/* macros for field RESET_L */ +#define RTC_SYNC_RESET__RESET_L__SHIFT 0 +#define RTC_SYNC_RESET__RESET_L__WIDTH 1 +#define RTC_SYNC_RESET__RESET_L__MASK 0x00000001U +#define RTC_SYNC_RESET__RESET_L__READ(src) (u_int32_t)(src) & 0x00000001U +#define RTC_SYNC_RESET__RESET_L__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RTC_SYNC_RESET__RESET_L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTC_SYNC_RESET__RESET_L__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTC_SYNC_RESET__RESET_L__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_RESET__RESET_L__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define RTC_SYNC_RESET__TYPE u_int32_t +#define RTC_SYNC_RESET__READ 0x00000001U +#define RTC_SYNC_RESET__WRITE 0x00000001U + +#endif /* __RTC_SYNC_RESET_MACRO__ */ + + +/* macros for rtc_sync_reg_map.RTC_SYNC_RESET */ +#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_RESET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_STATUS */ +#ifndef __RTC_SYNC_STATUS_MACRO__ +#define __RTC_SYNC_STATUS_MACRO__ + +/* macros for field SHUTDOWN_STATE */ +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__SHIFT 0 +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__WIDTH 1 +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__MASK 0x00000001U +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_STATUS__SHUTDOWN_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ON_STATE */ +#define RTC_SYNC_STATUS__ON_STATE__SHIFT 1 +#define RTC_SYNC_STATUS__ON_STATE__WIDTH 1 +#define RTC_SYNC_STATUS__ON_STATE__MASK 0x00000002U +#define RTC_SYNC_STATUS__ON_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_STATUS__ON_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_STATUS__ON_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SLEEP_STATE */ +#define RTC_SYNC_STATUS__SLEEP_STATE__SHIFT 2 +#define RTC_SYNC_STATUS__SLEEP_STATE__WIDTH 1 +#define RTC_SYNC_STATUS__SLEEP_STATE__MASK 0x00000004U +#define RTC_SYNC_STATUS__SLEEP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RTC_SYNC_STATUS__SLEEP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RTC_SYNC_STATUS__SLEEP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field WAKEUP_STATE */ +#define RTC_SYNC_STATUS__WAKEUP_STATE__SHIFT 3 +#define RTC_SYNC_STATUS__WAKEUP_STATE__WIDTH 1 +#define RTC_SYNC_STATUS__WAKEUP_STATE__MASK 0x00000008U +#define RTC_SYNC_STATUS__WAKEUP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RTC_SYNC_STATUS__WAKEUP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RTC_SYNC_STATUS__WAKEUP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field WRESET */ +#define RTC_SYNC_STATUS__WRESET__SHIFT 4 +#define RTC_SYNC_STATUS__WRESET__WIDTH 1 +#define RTC_SYNC_STATUS__WRESET__MASK 0x00000010U +#define RTC_SYNC_STATUS__WRESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RTC_SYNC_STATUS__WRESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RTC_SYNC_STATUS__WRESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PLL_CHANGING */ +#define RTC_SYNC_STATUS__PLL_CHANGING__SHIFT 5 +#define RTC_SYNC_STATUS__PLL_CHANGING__WIDTH 1 +#define RTC_SYNC_STATUS__PLL_CHANGING__MASK 0x00000020U +#define RTC_SYNC_STATUS__PLL_CHANGING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RTC_SYNC_STATUS__PLL_CHANGING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RTC_SYNC_STATUS__PLL_CHANGING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define RTC_SYNC_STATUS__TYPE u_int32_t +#define RTC_SYNC_STATUS__READ 0x0000003fU + +#endif /* __RTC_SYNC_STATUS_MACRO__ */ + + +/* macros for rtc_sync_reg_map.RTC_SYNC_STATUS */ +#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_STATUS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_DERIVED */ +#ifndef __RTC_SYNC_DERIVED_MACRO__ +#define __RTC_SYNC_DERIVED_MACRO__ + +/* macros for field BYPASS */ +#define RTC_SYNC_DERIVED__BYPASS__SHIFT 0 +#define RTC_SYNC_DERIVED__BYPASS__WIDTH 1 +#define RTC_SYNC_DERIVED__BYPASS__MASK 0x00000001U +#define RTC_SYNC_DERIVED__BYPASS__READ(src) (u_int32_t)(src) & 0x00000001U +#define RTC_SYNC_DERIVED__BYPASS__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RTC_SYNC_DERIVED__BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTC_SYNC_DERIVED__BYPASS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTC_SYNC_DERIVED__BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_DERIVED__BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field FORCE */ +#define RTC_SYNC_DERIVED__FORCE__SHIFT 1 +#define RTC_SYNC_DERIVED__FORCE__WIDTH 1 +#define RTC_SYNC_DERIVED__FORCE__MASK 0x00000002U +#define RTC_SYNC_DERIVED__FORCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_DERIVED__FORCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTC_SYNC_DERIVED__FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTC_SYNC_DERIVED__FORCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTC_SYNC_DERIVED__FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_DERIVED__FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define RTC_SYNC_DERIVED__TYPE u_int32_t +#define RTC_SYNC_DERIVED__READ 0x00000003U +#define RTC_SYNC_DERIVED__WRITE 0x00000003U + +#endif /* __RTC_SYNC_DERIVED_MACRO__ */ + + +/* macros for rtc_sync_reg_map.RTC_SYNC_DERIVED */ +#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_DERIVED__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_FORCE_WAKE */ +#ifndef __RTC_SYNC_FORCE_WAKE_MACRO__ +#define __RTC_SYNC_FORCE_WAKE_MACRO__ + +/* macros for field ENABLE */ +#define RTC_SYNC_FORCE_WAKE__ENABLE__SHIFT 0 +#define RTC_SYNC_FORCE_WAKE__ENABLE__WIDTH 1 +#define RTC_SYNC_FORCE_WAKE__ENABLE__MASK 0x00000001U +#define RTC_SYNC_FORCE_WAKE__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RTC_SYNC_FORCE_WAKE__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_FORCE_WAKE__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field INTR */ +#define RTC_SYNC_FORCE_WAKE__INTR__SHIFT 1 +#define RTC_SYNC_FORCE_WAKE__INTR__WIDTH 1 +#define RTC_SYNC_FORCE_WAKE__INTR__MASK 0x00000002U +#define RTC_SYNC_FORCE_WAKE__INTR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_FORCE_WAKE__INTR__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTC_SYNC_FORCE_WAKE__INTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTC_SYNC_FORCE_WAKE__INTR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTC_SYNC_FORCE_WAKE__INTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_FORCE_WAKE__INTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define RTC_SYNC_FORCE_WAKE__TYPE u_int32_t +#define RTC_SYNC_FORCE_WAKE__READ 0x00000003U +#define RTC_SYNC_FORCE_WAKE__WRITE 0x00000003U + +#endif /* __RTC_SYNC_FORCE_WAKE_MACRO__ */ + + +/* macros for rtc_sync_reg_map.RTC_SYNC_FORCE_WAKE */ +#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_FORCE_WAKE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_CAUSE */ +#ifndef __RTC_SYNC_INTR_CAUSE_MACRO__ +#define __RTC_SYNC_INTR_CAUSE_MACRO__ + +/* macros for field SHUTDOWN_STATE */ +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__SHIFT 0 +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MASK 0x00000001U +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ON_STATE */ +#define RTC_SYNC_INTR_CAUSE__ON_STATE__SHIFT 1 +#define RTC_SYNC_INTR_CAUSE__ON_STATE__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__ON_STATE__MASK 0x00000002U +#define RTC_SYNC_INTR_CAUSE__ON_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_INTR_CAUSE__ON_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTC_SYNC_INTR_CAUSE__ON_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTC_SYNC_INTR_CAUSE__ON_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTC_SYNC_INTR_CAUSE__ON_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_INTR_CAUSE__ON_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SLEEP_STATE */ +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__SHIFT 2 +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MASK 0x00000004U +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field WAKEUP_STATE */ +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__SHIFT 3 +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MASK 0x00000008U +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field SLEEP_ACCESS */ +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__SHIFT 4 +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MASK 0x00000010U +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PLL_CHANGING */ +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__SHIFT 5 +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WIDTH 1 +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MASK 0x00000020U +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define RTC_SYNC_INTR_CAUSE__TYPE u_int32_t +#define RTC_SYNC_INTR_CAUSE__READ 0x0000003fU +#define RTC_SYNC_INTR_CAUSE__WRITE 0x0000003fU + +#endif /* __RTC_SYNC_INTR_CAUSE_MACRO__ */ + + +/* macros for rtc_sync_reg_map.RTC_SYNC_INTR_CAUSE */ +#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_CAUSE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_ENABLE */ +#ifndef __RTC_SYNC_INTR_ENABLE_MACRO__ +#define __RTC_SYNC_INTR_ENABLE_MACRO__ + +/* macros for field SHUTDOWN_STATE */ +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__SHIFT 0 +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MASK 0x00000001U +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ON_STATE */ +#define RTC_SYNC_INTR_ENABLE__ON_STATE__SHIFT 1 +#define RTC_SYNC_INTR_ENABLE__ON_STATE__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__ON_STATE__MASK 0x00000002U +#define RTC_SYNC_INTR_ENABLE__ON_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_INTR_ENABLE__ON_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTC_SYNC_INTR_ENABLE__ON_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTC_SYNC_INTR_ENABLE__ON_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTC_SYNC_INTR_ENABLE__ON_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_INTR_ENABLE__ON_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SLEEP_STATE */ +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__SHIFT 2 +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MASK 0x00000004U +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field WAKEUP_STATE */ +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__SHIFT 3 +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MASK 0x00000008U +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field SLEEP_ACCESS */ +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__SHIFT 4 +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MASK 0x00000010U +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PLL_CHANGING */ +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__SHIFT 5 +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WIDTH 1 +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MASK 0x00000020U +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define RTC_SYNC_INTR_ENABLE__TYPE u_int32_t +#define RTC_SYNC_INTR_ENABLE__READ 0x0000003fU +#define RTC_SYNC_INTR_ENABLE__WRITE 0x0000003fU + +#endif /* __RTC_SYNC_INTR_ENABLE_MACRO__ */ + + +/* macros for rtc_sync_reg_map.RTC_SYNC_INTR_ENABLE */ +#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_ENABLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_MASK */ +#ifndef __RTC_SYNC_INTR_MASK_MACRO__ +#define __RTC_SYNC_INTR_MASK_MACRO__ + +/* macros for field SHUTDOWN_STATE */ +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__SHIFT 0 +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WIDTH 1 +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MASK 0x00000001U +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ON_STATE */ +#define RTC_SYNC_INTR_MASK__ON_STATE__SHIFT 1 +#define RTC_SYNC_INTR_MASK__ON_STATE__WIDTH 1 +#define RTC_SYNC_INTR_MASK__ON_STATE__MASK 0x00000002U +#define RTC_SYNC_INTR_MASK__ON_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTC_SYNC_INTR_MASK__ON_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTC_SYNC_INTR_MASK__ON_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTC_SYNC_INTR_MASK__ON_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTC_SYNC_INTR_MASK__ON_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTC_SYNC_INTR_MASK__ON_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SLEEP_STATE */ +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__SHIFT 2 +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__MASK 0x00000004U +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RTC_SYNC_INTR_MASK__SLEEP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field WAKEUP_STATE */ +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__SHIFT 3 +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WIDTH 1 +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MASK 0x00000008U +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field SLEEP_ACCESS */ +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__SHIFT 4 +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WIDTH 1 +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MASK 0x00000010U +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PLL_CHANGING */ +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__SHIFT 5 +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__WIDTH 1 +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__MASK 0x00000020U +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RTC_SYNC_INTR_MASK__PLL_CHANGING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define RTC_SYNC_INTR_MASK__TYPE u_int32_t +#define RTC_SYNC_INTR_MASK__READ 0x0000003fU +#define RTC_SYNC_INTR_MASK__WRITE 0x0000003fU + +#endif /* __RTC_SYNC_INTR_MASK_MACRO__ */ + + +/* macros for rtc_sync_reg_map.RTC_SYNC_INTR_MASK */ +#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_STA_ADDR_L32 */ +#ifndef __MAC_PCU_STA_ADDR_L32_MACRO__ +#define __MAC_PCU_STA_ADDR_L32_MACRO__ + +/* macros for field ADDR_31_0 */ +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__SHIFT 0 +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WIDTH 32 +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MASK 0xffffffffU +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_STA_ADDR_L32__TYPE u_int32_t +#define MAC_PCU_STA_ADDR_L32__READ 0xffffffffU +#define MAC_PCU_STA_ADDR_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_STA_ADDR_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_STA_ADDR_L32 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_STA_ADDR_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_STA_ADDR_U16 */ +#ifndef __MAC_PCU_STA_ADDR_U16_MACRO__ +#define __MAC_PCU_STA_ADDR_U16_MACRO__ + +/* macros for field ADDR_47_32 */ +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__SHIFT 0 +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WIDTH 16 +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MASK 0x0000ffffU +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field STA_AP */ +#define MAC_PCU_STA_ADDR_U16__STA_AP__SHIFT 16 +#define MAC_PCU_STA_ADDR_U16__STA_AP__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__STA_AP__MASK 0x00010000U +#define MAC_PCU_STA_ADDR_U16__STA_AP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_STA_ADDR_U16__STA_AP__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_STA_ADDR_U16__STA_AP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_STA_ADDR_U16__STA_AP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_STA_ADDR_U16__STA_AP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_STA_ADDR_U16__STA_AP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field ADHOC */ +#define MAC_PCU_STA_ADDR_U16__ADHOC__SHIFT 17 +#define MAC_PCU_STA_ADDR_U16__ADHOC__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__ADHOC__MASK 0x00020000U +#define MAC_PCU_STA_ADDR_U16__ADHOC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_STA_ADDR_U16__ADHOC__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_STA_ADDR_U16__ADHOC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_STA_ADDR_U16__ADHOC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_STA_ADDR_U16__ADHOC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_STA_ADDR_U16__ADHOC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field PW_SAVE */ +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__SHIFT 18 +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__MASK 0x00040000U +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_STA_ADDR_U16__PW_SAVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field KEYSRCH_DIS */ +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__SHIFT 19 +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MASK 0x00080000U +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field PCF */ +#define MAC_PCU_STA_ADDR_U16__PCF__SHIFT 20 +#define MAC_PCU_STA_ADDR_U16__PCF__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__PCF__MASK 0x00100000U +#define MAC_PCU_STA_ADDR_U16__PCF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_STA_ADDR_U16__PCF__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_STA_ADDR_U16__PCF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_STA_ADDR_U16__PCF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_STA_ADDR_U16__PCF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_STA_ADDR_U16__PCF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field USE_DEFANT */ +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__SHIFT 21 +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MASK 0x00200000U +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field DEFANT_UPDATE */ +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__SHIFT 22 +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MASK 0x00400000U +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field RTS_USE_DEF */ +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__SHIFT 23 +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MASK 0x00800000U +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field ACKCTS_6MB */ +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__SHIFT 24 +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MASK 0x01000000U +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field BASE_RATE_11B */ +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__SHIFT 25 +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MASK 0x02000000U +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field SECTOR_SELF_GEN */ +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__SHIFT 26 +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MASK 0x04000000U +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field CRPT_MIC_ENABLE */ +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__SHIFT 27 +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MASK 0x08000000U +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field KSRCH_MODE */ +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__SHIFT 28 +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MASK 0x10000000U +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PRESERVE_SEQNUM */ +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__SHIFT 29 +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MASK 0x20000000U +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field CBCIV_ENDIAN */ +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__SHIFT 30 +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MASK 0x40000000U +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field ADHOC_MCAST_SEARCH */ +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__SHIFT 31 +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WIDTH 1 +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MASK 0x80000000U +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define MAC_PCU_STA_ADDR_U16__TYPE u_int32_t +#define MAC_PCU_STA_ADDR_U16__READ 0xffffffffU +#define MAC_PCU_STA_ADDR_U16__WRITE 0xffffffffU + +#endif /* __MAC_PCU_STA_ADDR_U16_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_STA_ADDR_U16 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_STA_ADDR_U16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID_L32 */ +#ifndef __MAC_PCU_BSSID_L32_MACRO__ +#define __MAC_PCU_BSSID_L32_MACRO__ + +/* macros for field ADDR */ +#define MAC_PCU_BSSID_L32__ADDR__SHIFT 0 +#define MAC_PCU_BSSID_L32__ADDR__WIDTH 32 +#define MAC_PCU_BSSID_L32__ADDR__MASK 0xffffffffU +#define MAC_PCU_BSSID_L32__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_BSSID_L32__ADDR__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_BSSID_L32__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BSSID_L32__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BSSID_L32__TYPE u_int32_t +#define MAC_PCU_BSSID_L32__READ 0xffffffffU +#define MAC_PCU_BSSID_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BSSID_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BSSID_L32 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID_U16 */ +#ifndef __MAC_PCU_BSSID_U16_MACRO__ +#define __MAC_PCU_BSSID_U16_MACRO__ + +/* macros for field ADDR */ +#define MAC_PCU_BSSID_U16__ADDR__SHIFT 0 +#define MAC_PCU_BSSID_U16__ADDR__WIDTH 16 +#define MAC_PCU_BSSID_U16__ADDR__MASK 0x0000ffffU +#define MAC_PCU_BSSID_U16__ADDR__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_BSSID_U16__ADDR__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_PCU_BSSID_U16__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_BSSID_U16__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field AID */ +#define MAC_PCU_BSSID_U16__AID__SHIFT 16 +#define MAC_PCU_BSSID_U16__AID__WIDTH 11 +#define MAC_PCU_BSSID_U16__AID__MASK 0x07ff0000U +#define MAC_PCU_BSSID_U16__AID__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define MAC_PCU_BSSID_U16__AID__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define MAC_PCU_BSSID_U16__AID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define MAC_PCU_BSSID_U16__AID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) +#define MAC_PCU_BSSID_U16__TYPE u_int32_t +#define MAC_PCU_BSSID_U16__READ 0x07ffffffU +#define MAC_PCU_BSSID_U16__WRITE 0x07ffffffU + +#endif /* __MAC_PCU_BSSID_U16_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BSSID_U16 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID_U16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BCN_RSSI_AVE */ +#ifndef __MAC_PCU_BCN_RSSI_AVE_MACRO__ +#define __MAC_PCU_BCN_RSSI_AVE_MACRO__ + +/* macros for field AVE_VALUE */ +#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__SHIFT 0 +#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__WIDTH 12 +#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__MASK 0x00000fffU +#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU + +/* macros for field SPARE */ +#define MAC_PCU_BCN_RSSI_AVE__SPARE__SHIFT 12 +#define MAC_PCU_BCN_RSSI_AVE__SPARE__WIDTH 8 +#define MAC_PCU_BCN_RSSI_AVE__SPARE__MASK 0x000ff000U +#define MAC_PCU_BCN_RSSI_AVE__SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ff000U) >> 12) +#define MAC_PCU_BCN_RSSI_AVE__SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x000ff000U) +#define MAC_PCU_BCN_RSSI_AVE__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x000ff000U) +#define MAC_PCU_BCN_RSSI_AVE__SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x000ff000U))) +#define MAC_PCU_BCN_RSSI_AVE__TYPE u_int32_t +#define MAC_PCU_BCN_RSSI_AVE__READ 0x000fffffU +#define MAC_PCU_BCN_RSSI_AVE__WRITE 0x000fffffU + +#endif /* __MAC_PCU_BCN_RSSI_AVE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BCN_RSSI_AVE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BCN_RSSI_AVE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_ACK_CTS_TIMEOUT */ +#ifndef __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__ +#define __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__ + +/* macros for field ACK_TIMEOUT */ +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__SHIFT 0 +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WIDTH 14 +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MASK 0x00003fffU +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field CTS_TIMEOUT */ +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__SHIFT 16 +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WIDTH 14 +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MASK 0x3fff0000U +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0x3fff0000U) >> 16) +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x3fff0000U) +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x3fff0000U) +#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x3fff0000U))) +#define MAC_PCU_ACK_CTS_TIMEOUT__TYPE u_int32_t +#define MAC_PCU_ACK_CTS_TIMEOUT__READ 0x3fff3fffU +#define MAC_PCU_ACK_CTS_TIMEOUT__WRITE 0x3fff3fffU + +#endif /* __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_ACK_CTS_TIMEOUT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_ACK_CTS_TIMEOUT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BCN_RSSI_CTL */ +#ifndef __MAC_PCU_BCN_RSSI_CTL_MACRO__ +#define __MAC_PCU_BCN_RSSI_CTL_MACRO__ + +/* macros for field RSSI_THRESH */ +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__SHIFT 0 +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WIDTH 8 +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MASK 0x000000ffU +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field MISS_THRESH */ +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__SHIFT 8 +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WIDTH 8 +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MASK 0x0000ff00U +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field WEIGHT */ +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__SHIFT 24 +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WIDTH 5 +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MASK 0x1f000000U +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f000000U) >> 24) +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x1f000000U) +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x1f000000U) +#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x1f000000U))) + +/* macros for field RESET */ +#define MAC_PCU_BCN_RSSI_CTL__RESET__SHIFT 29 +#define MAC_PCU_BCN_RSSI_CTL__RESET__WIDTH 1 +#define MAC_PCU_BCN_RSSI_CTL__RESET__MASK 0x20000000U +#define MAC_PCU_BCN_RSSI_CTL__RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_BCN_RSSI_CTL__RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_BCN_RSSI_CTL__RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_BCN_RSSI_CTL__RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_BCN_RSSI_CTL__RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_BCN_RSSI_CTL__RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define MAC_PCU_BCN_RSSI_CTL__TYPE u_int32_t +#define MAC_PCU_BCN_RSSI_CTL__READ 0x3f00ffffU +#define MAC_PCU_BCN_RSSI_CTL__WRITE 0x3f00ffffU + +#endif /* __MAC_PCU_BCN_RSSI_CTL_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BCN_RSSI_CTL */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BCN_RSSI_CTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_USEC_LATENCY */ +#ifndef __MAC_PCU_USEC_LATENCY_MACRO__ +#define __MAC_PCU_USEC_LATENCY_MACRO__ + +/* macros for field USEC */ +#define MAC_PCU_USEC_LATENCY__USEC__SHIFT 0 +#define MAC_PCU_USEC_LATENCY__USEC__WIDTH 8 +#define MAC_PCU_USEC_LATENCY__USEC__MASK 0x000000ffU +#define MAC_PCU_USEC_LATENCY__USEC__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_USEC_LATENCY__USEC__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_USEC_LATENCY__USEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_USEC_LATENCY__USEC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field TX_LATENCY */ +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__SHIFT 14 +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__WIDTH 9 +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__MASK 0x007fc000U +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__READ(src) \ + (((u_int32_t)(src)\ + & 0x007fc000U) >> 14) +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x007fc000U) +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x007fc000U) +#define MAC_PCU_USEC_LATENCY__TX_LATENCY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x007fc000U))) + +/* macros for field RX_LATENCY */ +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__SHIFT 23 +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__WIDTH 6 +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__MASK 0x1f800000U +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f800000U) >> 23) +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x1f800000U) +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x1f800000U) +#define MAC_PCU_USEC_LATENCY__RX_LATENCY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x1f800000U))) +#define MAC_PCU_USEC_LATENCY__TYPE u_int32_t +#define MAC_PCU_USEC_LATENCY__READ 0x1fffc0ffU +#define MAC_PCU_USEC_LATENCY__WRITE 0x1fffc0ffU + +#endif /* __MAC_PCU_USEC_LATENCY_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_USEC_LATENCY */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_USEC_LATENCY__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RESET_TSF */ +#ifndef __MAC_PCU_RESET_TSF_MACRO__ +#define __MAC_PCU_RESET_TSF_MACRO__ + +/* macros for field ONE_SHOT */ +#define MAC_PCU_RESET_TSF__ONE_SHOT__SHIFT 24 +#define MAC_PCU_RESET_TSF__ONE_SHOT__WIDTH 1 +#define MAC_PCU_RESET_TSF__ONE_SHOT__MASK 0x01000000U +#define MAC_PCU_RESET_TSF__ONE_SHOT__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_RESET_TSF__ONE_SHOT__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_RESET_TSF__ONE_SHOT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_RESET_TSF__ONE_SHOT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_RESET_TSF__ONE_SHOT__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_RESET_TSF__ONE_SHOT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field ONE_SHOT2 */ +#define MAC_PCU_RESET_TSF__ONE_SHOT2__SHIFT 25 +#define MAC_PCU_RESET_TSF__ONE_SHOT2__WIDTH 1 +#define MAC_PCU_RESET_TSF__ONE_SHOT2__MASK 0x02000000U +#define MAC_PCU_RESET_TSF__ONE_SHOT2__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_RESET_TSF__ONE_SHOT2__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_RESET_TSF__ONE_SHOT2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_RESET_TSF__ONE_SHOT2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_RESET_TSF__ONE_SHOT2__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_RESET_TSF__ONE_SHOT2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) +#define MAC_PCU_RESET_TSF__TYPE u_int32_t +#define MAC_PCU_RESET_TSF__READ 0x03000000U +#define MAC_PCU_RESET_TSF__WRITE 0x03000000U + +#endif /* __MAC_PCU_RESET_TSF_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_RESET_TSF */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_RESET_TSF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MAX_CFP_DUR */ +#ifndef __MAC_PCU_MAX_CFP_DUR_MACRO__ +#define __MAC_PCU_MAX_CFP_DUR_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_MAX_CFP_DUR__VALUE__SHIFT 0 +#define MAC_PCU_MAX_CFP_DUR__VALUE__WIDTH 16 +#define MAC_PCU_MAX_CFP_DUR__VALUE__MASK 0x0000ffffU +#define MAC_PCU_MAX_CFP_DUR__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_MAX_CFP_DUR__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_PCU_MAX_CFP_DUR__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_MAX_CFP_DUR__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field USEC_FRAC_NUMERATOR */ +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__SHIFT 16 +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WIDTH 4 +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MASK 0x000f0000U +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field USEC_FRAC_DENOMINATOR */ +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__SHIFT 24 +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WIDTH 4 +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MASK 0x0f000000U +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) +#define MAC_PCU_MAX_CFP_DUR__TYPE u_int32_t +#define MAC_PCU_MAX_CFP_DUR__READ 0x0f0fffffU +#define MAC_PCU_MAX_CFP_DUR__WRITE 0x0f0fffffU + +#endif /* __MAC_PCU_MAX_CFP_DUR_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_MAX_CFP_DUR */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_MAX_CFP_DUR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_FILTER */ +#ifndef __MAC_PCU_RX_FILTER_MACRO__ +#define __MAC_PCU_RX_FILTER_MACRO__ + +/* macros for field UNICAST */ +#define MAC_PCU_RX_FILTER__UNICAST__SHIFT 0 +#define MAC_PCU_RX_FILTER__UNICAST__WIDTH 1 +#define MAC_PCU_RX_FILTER__UNICAST__MASK 0x00000001U +#define MAC_PCU_RX_FILTER__UNICAST__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_RX_FILTER__UNICAST__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_PCU_RX_FILTER__UNICAST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_RX_FILTER__UNICAST__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_RX_FILTER__UNICAST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_RX_FILTER__UNICAST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field MULTICAST */ +#define MAC_PCU_RX_FILTER__MULTICAST__SHIFT 1 +#define MAC_PCU_RX_FILTER__MULTICAST__WIDTH 1 +#define MAC_PCU_RX_FILTER__MULTICAST__MASK 0x00000002U +#define MAC_PCU_RX_FILTER__MULTICAST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_RX_FILTER__MULTICAST__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_RX_FILTER__MULTICAST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_RX_FILTER__MULTICAST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_RX_FILTER__MULTICAST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_RX_FILTER__MULTICAST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field BROADCAST */ +#define MAC_PCU_RX_FILTER__BROADCAST__SHIFT 2 +#define MAC_PCU_RX_FILTER__BROADCAST__WIDTH 1 +#define MAC_PCU_RX_FILTER__BROADCAST__MASK 0x00000004U +#define MAC_PCU_RX_FILTER__BROADCAST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_RX_FILTER__BROADCAST__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_RX_FILTER__BROADCAST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_RX_FILTER__BROADCAST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_RX_FILTER__BROADCAST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_RX_FILTER__BROADCAST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field CONTROL */ +#define MAC_PCU_RX_FILTER__CONTROL__SHIFT 3 +#define MAC_PCU_RX_FILTER__CONTROL__WIDTH 1 +#define MAC_PCU_RX_FILTER__CONTROL__MASK 0x00000008U +#define MAC_PCU_RX_FILTER__CONTROL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_RX_FILTER__CONTROL__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_RX_FILTER__CONTROL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_RX_FILTER__CONTROL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_RX_FILTER__CONTROL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_RX_FILTER__CONTROL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BEACON */ +#define MAC_PCU_RX_FILTER__BEACON__SHIFT 4 +#define MAC_PCU_RX_FILTER__BEACON__WIDTH 1 +#define MAC_PCU_RX_FILTER__BEACON__MASK 0x00000010U +#define MAC_PCU_RX_FILTER__BEACON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_RX_FILTER__BEACON__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_RX_FILTER__BEACON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_RX_FILTER__BEACON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_RX_FILTER__BEACON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_RX_FILTER__BEACON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PROMISCUOUS */ +#define MAC_PCU_RX_FILTER__PROMISCUOUS__SHIFT 5 +#define MAC_PCU_RX_FILTER__PROMISCUOUS__WIDTH 1 +#define MAC_PCU_RX_FILTER__PROMISCUOUS__MASK 0x00000020U +#define MAC_PCU_RX_FILTER__PROMISCUOUS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_RX_FILTER__PROMISCUOUS__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_RX_FILTER__PROMISCUOUS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_RX_FILTER__PROMISCUOUS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_RX_FILTER__PROMISCUOUS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_RX_FILTER__PROMISCUOUS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field XR_POLL */ +#define MAC_PCU_RX_FILTER__XR_POLL__SHIFT 6 +#define MAC_PCU_RX_FILTER__XR_POLL__WIDTH 1 +#define MAC_PCU_RX_FILTER__XR_POLL__MASK 0x00000040U +#define MAC_PCU_RX_FILTER__XR_POLL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_RX_FILTER__XR_POLL__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_RX_FILTER__XR_POLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_RX_FILTER__XR_POLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_RX_FILTER__XR_POLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_RX_FILTER__XR_POLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field PROBE_REQ */ +#define MAC_PCU_RX_FILTER__PROBE_REQ__SHIFT 7 +#define MAC_PCU_RX_FILTER__PROBE_REQ__WIDTH 1 +#define MAC_PCU_RX_FILTER__PROBE_REQ__MASK 0x00000080U +#define MAC_PCU_RX_FILTER__PROBE_REQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_RX_FILTER__PROBE_REQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_RX_FILTER__PROBE_REQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_RX_FILTER__PROBE_REQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_RX_FILTER__PROBE_REQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_RX_FILTER__PROBE_REQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field SYNC_FRAME */ +#define MAC_PCU_RX_FILTER__SYNC_FRAME__SHIFT 8 +#define MAC_PCU_RX_FILTER__SYNC_FRAME__WIDTH 1 +#define MAC_PCU_RX_FILTER__SYNC_FRAME__MASK 0x00000100U +#define MAC_PCU_RX_FILTER__SYNC_FRAME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_RX_FILTER__SYNC_FRAME__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_RX_FILTER__SYNC_FRAME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_RX_FILTER__SYNC_FRAME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_RX_FILTER__SYNC_FRAME__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_RX_FILTER__SYNC_FRAME__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field MY_BEACON */ +#define MAC_PCU_RX_FILTER__MY_BEACON__SHIFT 9 +#define MAC_PCU_RX_FILTER__MY_BEACON__WIDTH 1 +#define MAC_PCU_RX_FILTER__MY_BEACON__MASK 0x00000200U +#define MAC_PCU_RX_FILTER__MY_BEACON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_RX_FILTER__MY_BEACON__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_RX_FILTER__MY_BEACON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_RX_FILTER__MY_BEACON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_RX_FILTER__MY_BEACON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_RX_FILTER__MY_BEACON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field COMPRESSED_BAR */ +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__SHIFT 10 +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WIDTH 1 +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MASK 0x00000400U +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field COMPRESSED_BA */ +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__SHIFT 11 +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__WIDTH 1 +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__MASK 0x00000800U +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_RX_FILTER__COMPRESSED_BA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field UNCOMPRESSED_BA_BAR */ +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__SHIFT 12 +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WIDTH 1 +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MASK 0x00001000U +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field ASSUME_RADAR */ +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__SHIFT 13 +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__WIDTH 1 +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__MASK 0x00002000U +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define MAC_PCU_RX_FILTER__ASSUME_RADAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field PS_POLL */ +#define MAC_PCU_RX_FILTER__PS_POLL__SHIFT 14 +#define MAC_PCU_RX_FILTER__PS_POLL__WIDTH 1 +#define MAC_PCU_RX_FILTER__PS_POLL__MASK 0x00004000U +#define MAC_PCU_RX_FILTER__PS_POLL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define MAC_PCU_RX_FILTER__PS_POLL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define MAC_PCU_RX_FILTER__PS_POLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define MAC_PCU_RX_FILTER__PS_POLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define MAC_PCU_RX_FILTER__PS_POLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define MAC_PCU_RX_FILTER__PS_POLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field MCAST_BCAST_ALL */ +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__SHIFT 15 +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WIDTH 1 +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MASK 0x00008000U +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field RST_DLMTR_CNT_DISABLE */ +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__SHIFT 16 +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WIDTH 1 +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MASK 0x00010000U +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field HW_BCN_PROC_ENABLE */ +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__SHIFT 17 +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WIDTH 1 +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MASK 0x00020000U +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field MGMT_ACTION_MCAST */ +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__SHIFT 18 +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WIDTH 1 +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MASK 0x00040000U +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field CONTROL_WRAPPER */ +#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__SHIFT 19 +#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__WIDTH 1 +#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__MASK 0x00080000U +#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field FROM_TO_DS */ +#define MAC_PCU_RX_FILTER__FROM_TO_DS__SHIFT 20 +#define MAC_PCU_RX_FILTER__FROM_TO_DS__WIDTH 1 +#define MAC_PCU_RX_FILTER__FROM_TO_DS__MASK 0x00100000U +#define MAC_PCU_RX_FILTER__FROM_TO_DS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_RX_FILTER__FROM_TO_DS__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_RX_FILTER__FROM_TO_DS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_RX_FILTER__FROM_TO_DS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_RX_FILTER__FROM_TO_DS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_RX_FILTER__FROM_TO_DS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) +#define MAC_PCU_RX_FILTER__TYPE u_int32_t +#define MAC_PCU_RX_FILTER__READ 0x001fffffU +#define MAC_PCU_RX_FILTER__WRITE 0x001fffffU + +#endif /* __MAC_PCU_RX_FILTER_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_RX_FILTER */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_FILTER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MCAST_FILTER_L32 */ +#ifndef __MAC_PCU_MCAST_FILTER_L32_MACRO__ +#define __MAC_PCU_MCAST_FILTER_L32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_MCAST_FILTER_L32__VALUE__SHIFT 0 +#define MAC_PCU_MCAST_FILTER_L32__VALUE__WIDTH 32 +#define MAC_PCU_MCAST_FILTER_L32__VALUE__MASK 0xffffffffU +#define MAC_PCU_MCAST_FILTER_L32__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_MCAST_FILTER_L32__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_MCAST_FILTER_L32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_MCAST_FILTER_L32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_MCAST_FILTER_L32__TYPE u_int32_t +#define MAC_PCU_MCAST_FILTER_L32__READ 0xffffffffU +#define MAC_PCU_MCAST_FILTER_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_MCAST_FILTER_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_MCAST_FILTER_L32 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_MCAST_FILTER_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MCAST_FILTER_U32 */ +#ifndef __MAC_PCU_MCAST_FILTER_U32_MACRO__ +#define __MAC_PCU_MCAST_FILTER_U32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_MCAST_FILTER_U32__VALUE__SHIFT 0 +#define MAC_PCU_MCAST_FILTER_U32__VALUE__WIDTH 32 +#define MAC_PCU_MCAST_FILTER_U32__VALUE__MASK 0xffffffffU +#define MAC_PCU_MCAST_FILTER_U32__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_MCAST_FILTER_U32__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_MCAST_FILTER_U32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_MCAST_FILTER_U32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_MCAST_FILTER_U32__TYPE u_int32_t +#define MAC_PCU_MCAST_FILTER_U32__READ 0xffffffffU +#define MAC_PCU_MCAST_FILTER_U32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_MCAST_FILTER_U32_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_MCAST_FILTER_U32 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_MCAST_FILTER_U32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_DIAG_SW */ +#ifndef __MAC_PCU_DIAG_SW_MACRO__ +#define __MAC_PCU_DIAG_SW_MACRO__ + +/* macros for field INVALID_KEY_NO_ACK */ +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__SHIFT 0 +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WIDTH 1 +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MASK 0x00000001U +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field NO_ACK */ +#define MAC_PCU_DIAG_SW__NO_ACK__SHIFT 1 +#define MAC_PCU_DIAG_SW__NO_ACK__WIDTH 1 +#define MAC_PCU_DIAG_SW__NO_ACK__MASK 0x00000002U +#define MAC_PCU_DIAG_SW__NO_ACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_DIAG_SW__NO_ACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_DIAG_SW__NO_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_DIAG_SW__NO_ACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_DIAG_SW__NO_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_DIAG_SW__NO_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field NO_CTS */ +#define MAC_PCU_DIAG_SW__NO_CTS__SHIFT 2 +#define MAC_PCU_DIAG_SW__NO_CTS__WIDTH 1 +#define MAC_PCU_DIAG_SW__NO_CTS__MASK 0x00000004U +#define MAC_PCU_DIAG_SW__NO_CTS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_DIAG_SW__NO_CTS__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_DIAG_SW__NO_CTS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_DIAG_SW__NO_CTS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_DIAG_SW__NO_CTS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_DIAG_SW__NO_CTS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field NO_ENCRYPT */ +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__SHIFT 3 +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__WIDTH 1 +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__MASK 0x00000008U +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_DIAG_SW__NO_ENCRYPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field NO_DECRYPT */ +#define MAC_PCU_DIAG_SW__NO_DECRYPT__SHIFT 4 +#define MAC_PCU_DIAG_SW__NO_DECRYPT__WIDTH 1 +#define MAC_PCU_DIAG_SW__NO_DECRYPT__MASK 0x00000010U +#define MAC_PCU_DIAG_SW__NO_DECRYPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_DIAG_SW__NO_DECRYPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_DIAG_SW__NO_DECRYPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_DIAG_SW__NO_DECRYPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_DIAG_SW__NO_DECRYPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_DIAG_SW__NO_DECRYPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field HALT_RX */ +#define MAC_PCU_DIAG_SW__HALT_RX__SHIFT 5 +#define MAC_PCU_DIAG_SW__HALT_RX__WIDTH 1 +#define MAC_PCU_DIAG_SW__HALT_RX__MASK 0x00000020U +#define MAC_PCU_DIAG_SW__HALT_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_DIAG_SW__HALT_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_DIAG_SW__HALT_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_DIAG_SW__HALT_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_DIAG_SW__HALT_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_DIAG_SW__HALT_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field LOOP_BACK */ +#define MAC_PCU_DIAG_SW__LOOP_BACK__SHIFT 6 +#define MAC_PCU_DIAG_SW__LOOP_BACK__WIDTH 1 +#define MAC_PCU_DIAG_SW__LOOP_BACK__MASK 0x00000040U +#define MAC_PCU_DIAG_SW__LOOP_BACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_DIAG_SW__LOOP_BACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_DIAG_SW__LOOP_BACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_DIAG_SW__LOOP_BACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_DIAG_SW__LOOP_BACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_DIAG_SW__LOOP_BACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field CORRUPT_FCS */ +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__SHIFT 7 +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__WIDTH 1 +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__MASK 0x00000080U +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_DIAG_SW__CORRUPT_FCS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field DUMP_CHAN_INFO */ +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__SHIFT 8 +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WIDTH 1 +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MASK 0x00000100U +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field ACCEPT_NON_V0 */ +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__SHIFT 17 +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WIDTH 1 +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MASK 0x00020000U +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field OBS_SEL_1_0 */ +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__SHIFT 18 +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WIDTH 2 +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MASK 0x000c0000U +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000c0000U) >> 18) +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field RX_CLEAR_HIGH */ +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__SHIFT 20 +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WIDTH 1 +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MASK 0x00100000U +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field IGNORE_NAV */ +#define MAC_PCU_DIAG_SW__IGNORE_NAV__SHIFT 21 +#define MAC_PCU_DIAG_SW__IGNORE_NAV__WIDTH 1 +#define MAC_PCU_DIAG_SW__IGNORE_NAV__MASK 0x00200000U +#define MAC_PCU_DIAG_SW__IGNORE_NAV__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_DIAG_SW__IGNORE_NAV__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_DIAG_SW__IGNORE_NAV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_DIAG_SW__IGNORE_NAV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_DIAG_SW__IGNORE_NAV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_DIAG_SW__IGNORE_NAV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field CHAN_IDLE_HIGH */ +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__SHIFT 22 +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WIDTH 1 +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MASK 0x00400000U +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field PHYERR_ENABLE_EIFS_CTL */ +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__SHIFT 23 +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WIDTH 1 +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MASK 0x00800000U +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field DUAL_CHAIN_CHAN_INFO */ +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__SHIFT 24 +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WIDTH 1 +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MASK 0x01000000U +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field FORCE_RX_ABORT */ +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__SHIFT 25 +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WIDTH 1 +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MASK 0x02000000U +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field SATURATE_CYCLE_CNT */ +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__SHIFT 26 +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WIDTH 1 +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MASK 0x04000000U +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field OBS_SEL_2 */ +#define MAC_PCU_DIAG_SW__OBS_SEL_2__SHIFT 27 +#define MAC_PCU_DIAG_SW__OBS_SEL_2__WIDTH 1 +#define MAC_PCU_DIAG_SW__OBS_SEL_2__MASK 0x08000000U +#define MAC_PCU_DIAG_SW__OBS_SEL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_PCU_DIAG_SW__OBS_SEL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_PCU_DIAG_SW__OBS_SEL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_PCU_DIAG_SW__OBS_SEL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_PCU_DIAG_SW__OBS_SEL_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_PCU_DIAG_SW__OBS_SEL_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field RX_CLEAR_CTL_LOW */ +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__SHIFT 28 +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WIDTH 1 +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MASK 0x10000000U +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field RX_CLEAR_EXT_LOW */ +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__SHIFT 29 +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WIDTH 1 +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MASK 0x20000000U +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field DEBUG_MODE */ +#define MAC_PCU_DIAG_SW__DEBUG_MODE__SHIFT 30 +#define MAC_PCU_DIAG_SW__DEBUG_MODE__WIDTH 2 +#define MAC_PCU_DIAG_SW__DEBUG_MODE__MASK 0xc0000000U +#define MAC_PCU_DIAG_SW__DEBUG_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define MAC_PCU_DIAG_SW__DEBUG_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define MAC_PCU_DIAG_SW__DEBUG_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define MAC_PCU_DIAG_SW__DEBUG_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define MAC_PCU_DIAG_SW__TYPE u_int32_t +#define MAC_PCU_DIAG_SW__READ 0xfffe01ffU +#define MAC_PCU_DIAG_SW__WRITE 0xfffe01ffU + +#endif /* __MAC_PCU_DIAG_SW_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_DIAG_SW */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_DIAG_SW__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_L32 */ +#ifndef __MAC_PCU_TSF_L32_MACRO__ +#define __MAC_PCU_TSF_L32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TSF_L32__VALUE__SHIFT 0 +#define MAC_PCU_TSF_L32__VALUE__WIDTH 32 +#define MAC_PCU_TSF_L32__VALUE__MASK 0xffffffffU +#define MAC_PCU_TSF_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TSF_L32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TSF_L32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TSF_L32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TSF_L32__TYPE u_int32_t +#define MAC_PCU_TSF_L32__READ 0xffffffffU +#define MAC_PCU_TSF_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TSF_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TSF_L32 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_U32 */ +#ifndef __MAC_PCU_TSF_U32_MACRO__ +#define __MAC_PCU_TSF_U32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TSF_U32__VALUE__SHIFT 0 +#define MAC_PCU_TSF_U32__VALUE__WIDTH 32 +#define MAC_PCU_TSF_U32__VALUE__MASK 0xffffffffU +#define MAC_PCU_TSF_U32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TSF_U32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TSF_U32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TSF_U32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TSF_U32__TYPE u_int32_t +#define MAC_PCU_TSF_U32__READ 0xffffffffU +#define MAC_PCU_TSF_U32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TSF_U32_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TSF_U32 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_U32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TST_ADDAC */ +#ifndef __MAC_PCU_TST_ADDAC_MACRO__ +#define __MAC_PCU_TST_ADDAC_MACRO__ + +/* macros for field CONT_TX */ +#define MAC_PCU_TST_ADDAC__CONT_TX__SHIFT 0 +#define MAC_PCU_TST_ADDAC__CONT_TX__WIDTH 1 +#define MAC_PCU_TST_ADDAC__CONT_TX__MASK 0x00000001U +#define MAC_PCU_TST_ADDAC__CONT_TX__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_TST_ADDAC__CONT_TX__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_PCU_TST_ADDAC__CONT_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_TST_ADDAC__CONT_TX__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_TST_ADDAC__CONT_TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_TST_ADDAC__CONT_TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field TESTMODE */ +#define MAC_PCU_TST_ADDAC__TESTMODE__SHIFT 1 +#define MAC_PCU_TST_ADDAC__TESTMODE__WIDTH 1 +#define MAC_PCU_TST_ADDAC__TESTMODE__MASK 0x00000002U +#define MAC_PCU_TST_ADDAC__TESTMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_TST_ADDAC__TESTMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_TST_ADDAC__TESTMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_TST_ADDAC__TESTMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_TST_ADDAC__TESTMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_TST_ADDAC__TESTMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field LOOP */ +#define MAC_PCU_TST_ADDAC__LOOP__SHIFT 2 +#define MAC_PCU_TST_ADDAC__LOOP__WIDTH 1 +#define MAC_PCU_TST_ADDAC__LOOP__MASK 0x00000004U +#define MAC_PCU_TST_ADDAC__LOOP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_TST_ADDAC__LOOP__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_TST_ADDAC__LOOP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_TST_ADDAC__LOOP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_TST_ADDAC__LOOP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_TST_ADDAC__LOOP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field LOOP_LEN */ +#define MAC_PCU_TST_ADDAC__LOOP_LEN__SHIFT 3 +#define MAC_PCU_TST_ADDAC__LOOP_LEN__WIDTH 11 +#define MAC_PCU_TST_ADDAC__LOOP_LEN__MASK 0x00003ff8U +#define MAC_PCU_TST_ADDAC__LOOP_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003ff8U) >> 3) +#define MAC_PCU_TST_ADDAC__LOOP_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00003ff8U) +#define MAC_PCU_TST_ADDAC__LOOP_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003ff8U) | (((u_int32_t)(src) <<\ + 3) & 0x00003ff8U) +#define MAC_PCU_TST_ADDAC__LOOP_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00003ff8U))) + +/* macros for field UPPER_8B */ +#define MAC_PCU_TST_ADDAC__UPPER_8B__SHIFT 14 +#define MAC_PCU_TST_ADDAC__UPPER_8B__WIDTH 1 +#define MAC_PCU_TST_ADDAC__UPPER_8B__MASK 0x00004000U +#define MAC_PCU_TST_ADDAC__UPPER_8B__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define MAC_PCU_TST_ADDAC__UPPER_8B__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define MAC_PCU_TST_ADDAC__UPPER_8B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define MAC_PCU_TST_ADDAC__UPPER_8B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define MAC_PCU_TST_ADDAC__UPPER_8B__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define MAC_PCU_TST_ADDAC__UPPER_8B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field SAMPLE_SIZE_2K */ +#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__SHIFT 15 +#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__WIDTH 1 +#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__MASK 0x00008000U +#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field TRIG_SEL */ +#define MAC_PCU_TST_ADDAC__TRIG_SEL__SHIFT 16 +#define MAC_PCU_TST_ADDAC__TRIG_SEL__WIDTH 1 +#define MAC_PCU_TST_ADDAC__TRIG_SEL__MASK 0x00010000U +#define MAC_PCU_TST_ADDAC__TRIG_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_TST_ADDAC__TRIG_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_TST_ADDAC__TRIG_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_TST_ADDAC__TRIG_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_TST_ADDAC__TRIG_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_TST_ADDAC__TRIG_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field TRIG_POLARITY */ +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__SHIFT 17 +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WIDTH 1 +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MASK 0x00020000U +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field CONT_TEST */ +#define MAC_PCU_TST_ADDAC__CONT_TEST__SHIFT 18 +#define MAC_PCU_TST_ADDAC__CONT_TEST__WIDTH 1 +#define MAC_PCU_TST_ADDAC__CONT_TEST__MASK 0x00040000U +#define MAC_PCU_TST_ADDAC__CONT_TEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_TST_ADDAC__CONT_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_TST_ADDAC__CONT_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field TEST_CAPTURE */ +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__SHIFT 19 +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WIDTH 1 +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MASK 0x00080000U +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field TEST_ARM */ +#define MAC_PCU_TST_ADDAC__TEST_ARM__SHIFT 20 +#define MAC_PCU_TST_ADDAC__TEST_ARM__WIDTH 1 +#define MAC_PCU_TST_ADDAC__TEST_ARM__MASK 0x00100000U +#define MAC_PCU_TST_ADDAC__TEST_ARM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_TST_ADDAC__TEST_ARM__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_TST_ADDAC__TEST_ARM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_TST_ADDAC__TEST_ARM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_TST_ADDAC__TEST_ARM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_TST_ADDAC__TEST_ARM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) +#define MAC_PCU_TST_ADDAC__TYPE u_int32_t +#define MAC_PCU_TST_ADDAC__READ 0x001fffffU +#define MAC_PCU_TST_ADDAC__WRITE 0x001fffffU + +#endif /* __MAC_PCU_TST_ADDAC_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TST_ADDAC */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TST_ADDAC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_DEF_ANTENNA */ +#ifndef __MAC_PCU_DEF_ANTENNA_MACRO__ +#define __MAC_PCU_DEF_ANTENNA_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_DEF_ANTENNA__VALUE__SHIFT 0 +#define MAC_PCU_DEF_ANTENNA__VALUE__WIDTH 24 +#define MAC_PCU_DEF_ANTENNA__VALUE__MASK 0x00ffffffU +#define MAC_PCU_DEF_ANTENNA__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_PCU_DEF_ANTENNA__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) +#define MAC_PCU_DEF_ANTENNA__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_DEF_ANTENNA__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) + +/* macros for field TX_DEF_ANT_SEL */ +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__SHIFT 24 +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MASK 0x01000000U +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field SLOW_TX_ANT_EN */ +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__SHIFT 25 +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MASK 0x02000000U +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field TX_CUR_ANT */ +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__SHIFT 26 +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MASK 0x04000000U +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field FAST_DEF_ANT */ +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__SHIFT 27 +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MASK 0x08000000U +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field RX_LNA_CONFIG_SEL */ +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__SHIFT 28 +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MASK 0x10000000U +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field FAST_TX_ANT_EN */ +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__SHIFT 29 +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MASK 0x20000000U +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field RX_ANT_EN */ +#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__SHIFT 30 +#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__MASK 0x40000000U +#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field RX_ANT_DIV_ON */ +#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__SHIFT 31 +#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__WIDTH 1 +#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__MASK 0x80000000U +#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define MAC_PCU_DEF_ANTENNA__TYPE u_int32_t +#define MAC_PCU_DEF_ANTENNA__READ 0xffffffffU +#define MAC_PCU_DEF_ANTENNA__WRITE 0xffffffffU + +#endif /* __MAC_PCU_DEF_ANTENNA_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_DEF_ANTENNA */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_DEF_ANTENNA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AES_MUTE_MASK_0 */ +#ifndef __MAC_PCU_AES_MUTE_MASK_0_MACRO__ +#define __MAC_PCU_AES_MUTE_MASK_0_MACRO__ + +/* macros for field FC */ +#define MAC_PCU_AES_MUTE_MASK_0__FC__SHIFT 0 +#define MAC_PCU_AES_MUTE_MASK_0__FC__WIDTH 16 +#define MAC_PCU_AES_MUTE_MASK_0__FC__MASK 0x0000ffffU +#define MAC_PCU_AES_MUTE_MASK_0__FC__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_AES_MUTE_MASK_0__FC__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_AES_MUTE_MASK_0__FC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_AES_MUTE_MASK_0__FC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field QOS */ +#define MAC_PCU_AES_MUTE_MASK_0__QOS__SHIFT 16 +#define MAC_PCU_AES_MUTE_MASK_0__QOS__WIDTH 16 +#define MAC_PCU_AES_MUTE_MASK_0__QOS__MASK 0xffff0000U +#define MAC_PCU_AES_MUTE_MASK_0__QOS__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_AES_MUTE_MASK_0__QOS__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_AES_MUTE_MASK_0__QOS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_AES_MUTE_MASK_0__QOS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_AES_MUTE_MASK_0__TYPE u_int32_t +#define MAC_PCU_AES_MUTE_MASK_0__READ 0xffffffffU +#define MAC_PCU_AES_MUTE_MASK_0__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AES_MUTE_MASK_0_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_AES_MUTE_MASK_0 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_AES_MUTE_MASK_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AES_MUTE_MASK_1 */ +#ifndef __MAC_PCU_AES_MUTE_MASK_1_MACRO__ +#define __MAC_PCU_AES_MUTE_MASK_1_MACRO__ + +/* macros for field SEQ */ +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__SHIFT 0 +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__WIDTH 16 +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__MASK 0x0000ffffU +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_AES_MUTE_MASK_1__SEQ__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field FC_MGMT */ +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__SHIFT 16 +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WIDTH 16 +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MASK 0xffff0000U +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_AES_MUTE_MASK_1__TYPE u_int32_t +#define MAC_PCU_AES_MUTE_MASK_1__READ 0xffffffffU +#define MAC_PCU_AES_MUTE_MASK_1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AES_MUTE_MASK_1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_AES_MUTE_MASK_1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_AES_MUTE_MASK_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_GATED_CLKS */ +#ifndef __MAC_PCU_GATED_CLKS_MACRO__ +#define __MAC_PCU_GATED_CLKS_MACRO__ + +/* macros for field GATED_TX */ +#define MAC_PCU_GATED_CLKS__GATED_TX__SHIFT 1 +#define MAC_PCU_GATED_CLKS__GATED_TX__WIDTH 1 +#define MAC_PCU_GATED_CLKS__GATED_TX__MASK 0x00000002U +#define MAC_PCU_GATED_CLKS__GATED_TX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_GATED_CLKS__GATED_TX__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_GATED_CLKS__GATED_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_GATED_CLKS__GATED_TX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_GATED_CLKS__GATED_TX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_GATED_CLKS__GATED_TX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field GATED_RX */ +#define MAC_PCU_GATED_CLKS__GATED_RX__SHIFT 2 +#define MAC_PCU_GATED_CLKS__GATED_RX__WIDTH 1 +#define MAC_PCU_GATED_CLKS__GATED_RX__MASK 0x00000004U +#define MAC_PCU_GATED_CLKS__GATED_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_GATED_CLKS__GATED_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_GATED_CLKS__GATED_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_GATED_CLKS__GATED_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_GATED_CLKS__GATED_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_GATED_CLKS__GATED_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field GATED_REG */ +#define MAC_PCU_GATED_CLKS__GATED_REG__SHIFT 3 +#define MAC_PCU_GATED_CLKS__GATED_REG__WIDTH 1 +#define MAC_PCU_GATED_CLKS__GATED_REG__MASK 0x00000008U +#define MAC_PCU_GATED_CLKS__GATED_REG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_GATED_CLKS__GATED_REG__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_GATED_CLKS__GATED_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_GATED_CLKS__GATED_REG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_GATED_CLKS__GATED_REG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_GATED_CLKS__GATED_REG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define MAC_PCU_GATED_CLKS__TYPE u_int32_t +#define MAC_PCU_GATED_CLKS__READ 0x0000000eU +#define MAC_PCU_GATED_CLKS__WRITE 0x0000000eU + +#endif /* __MAC_PCU_GATED_CLKS_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_GATED_CLKS */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_GATED_CLKS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_OBS_BUS_2 */ +#ifndef __MAC_PCU_OBS_BUS_2_MACRO__ +#define __MAC_PCU_OBS_BUS_2_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_OBS_BUS_2__VALUE__SHIFT 0 +#define MAC_PCU_OBS_BUS_2__VALUE__WIDTH 18 +#define MAC_PCU_OBS_BUS_2__VALUE__MASK 0x0003ffffU +#define MAC_PCU_OBS_BUS_2__VALUE__READ(src) (u_int32_t)(src) & 0x0003ffffU + +/* macros for field WCF_STATE */ +#define MAC_PCU_OBS_BUS_2__WCF_STATE__SHIFT 18 +#define MAC_PCU_OBS_BUS_2__WCF_STATE__WIDTH 4 +#define MAC_PCU_OBS_BUS_2__WCF_STATE__MASK 0x003c0000U +#define MAC_PCU_OBS_BUS_2__WCF_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x003c0000U) >> 18) + +/* macros for field WCF0_FULL */ +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__SHIFT 22 +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__WIDTH 1 +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__MASK 0x00400000U +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_OBS_BUS_2__WCF0_FULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field WCF1_FULL */ +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__SHIFT 23 +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__WIDTH 1 +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__MASK 0x00800000U +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_OBS_BUS_2__WCF1_FULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field WCF_COUNT */ +#define MAC_PCU_OBS_BUS_2__WCF_COUNT__SHIFT 24 +#define MAC_PCU_OBS_BUS_2__WCF_COUNT__WIDTH 5 +#define MAC_PCU_OBS_BUS_2__WCF_COUNT__MASK 0x1f000000U +#define MAC_PCU_OBS_BUS_2__WCF_COUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f000000U) >> 24) + +/* macros for field MACBB_ALL_AWAKE */ +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__SHIFT 29 +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__WIDTH 1 +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__MASK 0x20000000U +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define MAC_PCU_OBS_BUS_2__TYPE u_int32_t +#define MAC_PCU_OBS_BUS_2__READ 0x3fffffffU + +#endif /* __MAC_PCU_OBS_BUS_2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_OBS_BUS_2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_OBS_BUS_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_OBS_BUS_1 */ +#ifndef __MAC_PCU_OBS_BUS_1_MACRO__ +#define __MAC_PCU_OBS_BUS_1_MACRO__ + +/* macros for field PCU_DIRECTED */ +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__SHIFT 0 +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__MASK 0x00000001U +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PCU_RX_END */ +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__SHIFT 1 +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__MASK 0x00000002U +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_OBS_BUS_1__PCU_RX_END__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field RX_WEP */ +#define MAC_PCU_OBS_BUS_1__RX_WEP__SHIFT 2 +#define MAC_PCU_OBS_BUS_1__RX_WEP__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__RX_WEP__MASK 0x00000004U +#define MAC_PCU_OBS_BUS_1__RX_WEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_OBS_BUS_1__RX_WEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_OBS_BUS_1__RX_WEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field RX_MY_BEACON */ +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__SHIFT 3 +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__MASK 0x00000008U +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field FILTER_PASS */ +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__SHIFT 4 +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__MASK 0x00000010U +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_OBS_BUS_1__FILTER_PASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field TX_HCF */ +#define MAC_PCU_OBS_BUS_1__TX_HCF__SHIFT 5 +#define MAC_PCU_OBS_BUS_1__TX_HCF__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__TX_HCF__MASK 0x00000020U +#define MAC_PCU_OBS_BUS_1__TX_HCF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_OBS_BUS_1__TX_HCF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_OBS_BUS_1__TX_HCF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field TM_QUIET_TIME */ +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__SHIFT 6 +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__MASK 0x00000040U +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field PCU_CHANNEL_IDLE */ +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__SHIFT 7 +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__MASK 0x00000080U +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field TX_HOLD */ +#define MAC_PCU_OBS_BUS_1__TX_HOLD__SHIFT 8 +#define MAC_PCU_OBS_BUS_1__TX_HOLD__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__TX_HOLD__MASK 0x00000100U +#define MAC_PCU_OBS_BUS_1__TX_HOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_OBS_BUS_1__TX_HOLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_OBS_BUS_1__TX_HOLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field TX_FRAME */ +#define MAC_PCU_OBS_BUS_1__TX_FRAME__SHIFT 9 +#define MAC_PCU_OBS_BUS_1__TX_FRAME__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__TX_FRAME__MASK 0x00000200U +#define MAC_PCU_OBS_BUS_1__TX_FRAME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_OBS_BUS_1__TX_FRAME__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_OBS_BUS_1__TX_FRAME__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field RX_FRAME */ +#define MAC_PCU_OBS_BUS_1__RX_FRAME__SHIFT 10 +#define MAC_PCU_OBS_BUS_1__RX_FRAME__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__RX_FRAME__MASK 0x00000400U +#define MAC_PCU_OBS_BUS_1__RX_FRAME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_PCU_OBS_BUS_1__RX_FRAME__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_PCU_OBS_BUS_1__RX_FRAME__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field RX_CLEAR */ +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__SHIFT 11 +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__WIDTH 1 +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__MASK 0x00000800U +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_OBS_BUS_1__RX_CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field WEP_STATE */ +#define MAC_PCU_OBS_BUS_1__WEP_STATE__SHIFT 12 +#define MAC_PCU_OBS_BUS_1__WEP_STATE__WIDTH 6 +#define MAC_PCU_OBS_BUS_1__WEP_STATE__MASK 0x0003f000U +#define MAC_PCU_OBS_BUS_1__WEP_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) + +/* macros for field RX_STATE */ +#define MAC_PCU_OBS_BUS_1__RX_STATE__SHIFT 20 +#define MAC_PCU_OBS_BUS_1__RX_STATE__WIDTH 5 +#define MAC_PCU_OBS_BUS_1__RX_STATE__MASK 0x01f00000U +#define MAC_PCU_OBS_BUS_1__RX_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) + +/* macros for field TX_STATE */ +#define MAC_PCU_OBS_BUS_1__TX_STATE__SHIFT 25 +#define MAC_PCU_OBS_BUS_1__TX_STATE__WIDTH 6 +#define MAC_PCU_OBS_BUS_1__TX_STATE__MASK 0x7e000000U +#define MAC_PCU_OBS_BUS_1__TX_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x7e000000U) >> 25) +#define MAC_PCU_OBS_BUS_1__TYPE u_int32_t +#define MAC_PCU_OBS_BUS_1__READ 0x7ff3ffffU + +#endif /* __MAC_PCU_OBS_BUS_1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_OBS_BUS_1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_OBS_BUS_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_DYM_MIMO_PWR_SAVE */ +#ifndef __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__ +#define __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__ + +/* macros for field USE_MAC_CTRL */ +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__SHIFT 0 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WIDTH 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MASK 0x00000001U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field HW_CTRL_EN */ +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__SHIFT 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WIDTH 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MASK 0x00000002U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field SW_CHAIN_MASK_SEL */ +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__SHIFT 2 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WIDTH 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MASK 0x00000004U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field LOW_PWR_CHAIN_MASK */ +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__SHIFT 4 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WIDTH 3 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MASK 0x00000070U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000070U) >> 4) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field HI_PWR_CHAIN_MASK */ +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__SHIFT 8 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WIDTH 3 +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MASK 0x00000700U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) +#define MAC_PCU_DYM_MIMO_PWR_SAVE__TYPE u_int32_t +#define MAC_PCU_DYM_MIMO_PWR_SAVE__READ 0x00000777U +#define MAC_PCU_DYM_MIMO_PWR_SAVE__WRITE 0x00000777U + +#endif /* __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_DYM_MIMO_PWR_SAVE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_DYM_MIMO_PWR_SAVE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB */ +#ifndef __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__ +#define __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__SHIFT 0 +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WIDTH 32 +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MASK 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__TYPE u_int32_t +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__READ 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB */ +#ifndef __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__ +#define __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__SHIFT 0 +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WIDTH 32 +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MASK 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__TYPE u_int32_t +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__READ 0xffffffffU +#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__NUM \ + 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LAST_BEACON_TSF */ +#ifndef __MAC_PCU_LAST_BEACON_TSF_MACRO__ +#define __MAC_PCU_LAST_BEACON_TSF_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_LAST_BEACON_TSF__VALUE__SHIFT 0 +#define MAC_PCU_LAST_BEACON_TSF__VALUE__WIDTH 32 +#define MAC_PCU_LAST_BEACON_TSF__VALUE__MASK 0xffffffffU +#define MAC_PCU_LAST_BEACON_TSF__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_LAST_BEACON_TSF__TYPE u_int32_t +#define MAC_PCU_LAST_BEACON_TSF__READ 0xffffffffU + +#endif /* __MAC_PCU_LAST_BEACON_TSF_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_LAST_BEACON_TSF */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_LAST_BEACON_TSF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_NAV */ +#ifndef __MAC_PCU_NAV_MACRO__ +#define __MAC_PCU_NAV_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_NAV__VALUE__SHIFT 0 +#define MAC_PCU_NAV__VALUE__WIDTH 26 +#define MAC_PCU_NAV__VALUE__MASK 0x03ffffffU +#define MAC_PCU_NAV__VALUE__READ(src) (u_int32_t)(src) & 0x03ffffffU +#define MAC_PCU_NAV__VALUE__WRITE(src) ((u_int32_t)(src) & 0x03ffffffU) +#define MAC_PCU_NAV__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ffffffU) | ((u_int32_t)(src) &\ + 0x03ffffffU) +#define MAC_PCU_NAV__VALUE__VERIFY(src) (!(((u_int32_t)(src) & ~0x03ffffffU))) +#define MAC_PCU_NAV__TYPE u_int32_t +#define MAC_PCU_NAV__READ 0x03ffffffU +#define MAC_PCU_NAV__WRITE 0x03ffffffU + +#endif /* __MAC_PCU_NAV_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_NAV */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_NAV__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RTS_SUCCESS_CNT */ +#ifndef __MAC_PCU_RTS_SUCCESS_CNT_MACRO__ +#define __MAC_PCU_RTS_SUCCESS_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__SHIFT 0 +#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__WIDTH 16 +#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_PCU_RTS_SUCCESS_CNT__TYPE u_int32_t +#define MAC_PCU_RTS_SUCCESS_CNT__READ 0x0000ffffU + +#endif /* __MAC_PCU_RTS_SUCCESS_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_RTS_SUCCESS_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_RTS_SUCCESS_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RTS_FAIL_CNT */ +#ifndef __MAC_PCU_RTS_FAIL_CNT_MACRO__ +#define __MAC_PCU_RTS_FAIL_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_RTS_FAIL_CNT__VALUE__SHIFT 0 +#define MAC_PCU_RTS_FAIL_CNT__VALUE__WIDTH 16 +#define MAC_PCU_RTS_FAIL_CNT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_RTS_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_RTS_FAIL_CNT__TYPE u_int32_t +#define MAC_PCU_RTS_FAIL_CNT__READ 0x0000ffffU + +#endif /* __MAC_PCU_RTS_FAIL_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_RTS_FAIL_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_RTS_FAIL_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_ACK_FAIL_CNT */ +#ifndef __MAC_PCU_ACK_FAIL_CNT_MACRO__ +#define __MAC_PCU_ACK_FAIL_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_ACK_FAIL_CNT__VALUE__SHIFT 0 +#define MAC_PCU_ACK_FAIL_CNT__VALUE__WIDTH 16 +#define MAC_PCU_ACK_FAIL_CNT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_ACK_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_ACK_FAIL_CNT__TYPE u_int32_t +#define MAC_PCU_ACK_FAIL_CNT__READ 0x0000ffffU + +#endif /* __MAC_PCU_ACK_FAIL_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_ACK_FAIL_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_ACK_FAIL_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_FCS_FAIL_CNT */ +#ifndef __MAC_PCU_FCS_FAIL_CNT_MACRO__ +#define __MAC_PCU_FCS_FAIL_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_FCS_FAIL_CNT__VALUE__SHIFT 0 +#define MAC_PCU_FCS_FAIL_CNT__VALUE__WIDTH 16 +#define MAC_PCU_FCS_FAIL_CNT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_FCS_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_FCS_FAIL_CNT__TYPE u_int32_t +#define MAC_PCU_FCS_FAIL_CNT__READ 0x0000ffffU + +#endif /* __MAC_PCU_FCS_FAIL_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_FCS_FAIL_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_FCS_FAIL_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BEACON_CNT */ +#ifndef __MAC_PCU_BEACON_CNT_MACRO__ +#define __MAC_PCU_BEACON_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BEACON_CNT__VALUE__SHIFT 0 +#define MAC_PCU_BEACON_CNT__VALUE__WIDTH 16 +#define MAC_PCU_BEACON_CNT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_BEACON_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_BEACON_CNT__TYPE u_int32_t +#define MAC_PCU_BEACON_CNT__READ 0x0000ffffU + +#endif /* __MAC_PCU_BEACON_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BEACON_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BEACON_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_SLOT_ALERT_CNTL */ +#ifndef __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__ +#define __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__SHIFT 0 +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WIDTH 16 +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MASK 0x0000ffffU +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__TYPE u_int32_t +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__READ 0x0000ffffU +#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TDMA_SLOT_ALERT_CNTL */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_SLOT_ALERT_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BASIC_SET */ +#ifndef __MAC_PCU_BASIC_SET_MACRO__ +#define __MAC_PCU_BASIC_SET_MACRO__ + +/* macros for field MCS */ +#define MAC_PCU_BASIC_SET__MCS__SHIFT 0 +#define MAC_PCU_BASIC_SET__MCS__WIDTH 32 +#define MAC_PCU_BASIC_SET__MCS__MASK 0xffffffffU +#define MAC_PCU_BASIC_SET__MCS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_BASIC_SET__MCS__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_BASIC_SET__MCS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BASIC_SET__MCS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BASIC_SET__TYPE u_int32_t +#define MAC_PCU_BASIC_SET__READ 0xffffffffU +#define MAC_PCU_BASIC_SET__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BASIC_SET_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BASIC_SET */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BASIC_SET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MGMT_SEQ */ +#ifndef __MAC_PCU_MGMT_SEQ_MACRO__ +#define __MAC_PCU_MGMT_SEQ_MACRO__ + +/* macros for field MIN */ +#define MAC_PCU_MGMT_SEQ__MIN__SHIFT 0 +#define MAC_PCU_MGMT_SEQ__MIN__WIDTH 12 +#define MAC_PCU_MGMT_SEQ__MIN__MASK 0x00000fffU +#define MAC_PCU_MGMT_SEQ__MIN__READ(src) (u_int32_t)(src) & 0x00000fffU +#define MAC_PCU_MGMT_SEQ__MIN__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) +#define MAC_PCU_MGMT_SEQ__MIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define MAC_PCU_MGMT_SEQ__MIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field MAX */ +#define MAC_PCU_MGMT_SEQ__MAX__SHIFT 16 +#define MAC_PCU_MGMT_SEQ__MAX__WIDTH 12 +#define MAC_PCU_MGMT_SEQ__MAX__MASK 0x0fff0000U +#define MAC_PCU_MGMT_SEQ__MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fff0000U) >> 16) +#define MAC_PCU_MGMT_SEQ__MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x0fff0000U) +#define MAC_PCU_MGMT_SEQ__MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x0fff0000U) +#define MAC_PCU_MGMT_SEQ__MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x0fff0000U))) +#define MAC_PCU_MGMT_SEQ__TYPE u_int32_t +#define MAC_PCU_MGMT_SEQ__READ 0x0fff0fffU +#define MAC_PCU_MGMT_SEQ__WRITE 0x0fff0fffU + +#endif /* __MAC_PCU_MGMT_SEQ_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_MGMT_SEQ */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_MGMT_SEQ__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BF_RPT1 */ +#ifndef __MAC_PCU_BF_RPT1_MACRO__ +#define __MAC_PCU_BF_RPT1_MACRO__ + +/* macros for field V_ACTION_VALUE */ +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__SHIFT 0 +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WIDTH 8 +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MASK 0x000000ffU +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field CV_ACTION_VALUE */ +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__SHIFT 8 +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WIDTH 8 +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MASK 0x0000ff00U +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field CATEGORY_VALUE */ +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__SHIFT 16 +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WIDTH 8 +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MASK 0x00ff0000U +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field FRAME_SUBTYPE_VALUE */ +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__SHIFT 24 +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WIDTH 4 +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MASK 0x0f000000U +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) + +/* macros for field FRAME_TYPE_VALUE */ +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__SHIFT 28 +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WIDTH 2 +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MASK 0x30000000U +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x30000000U) >> 28) +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x30000000U) +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) +#define MAC_PCU_BF_RPT1__TYPE u_int32_t +#define MAC_PCU_BF_RPT1__READ 0x3fffffffU +#define MAC_PCU_BF_RPT1__WRITE 0x3fffffffU + +#endif /* __MAC_PCU_BF_RPT1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BF_RPT1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BF_RPT1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BF_RPT2 */ +#ifndef __MAC_PCU_BF_RPT2_MACRO__ +#define __MAC_PCU_BF_RPT2_MACRO__ + +/* macros for field FRAME_SUBTYPE_VALUE */ +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__SHIFT 0 +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WIDTH 4 +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MASK 0x0000000fU +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define MAC_PCU_BF_RPT2__TYPE u_int32_t +#define MAC_PCU_BF_RPT2__READ 0x0000000fU +#define MAC_PCU_BF_RPT2__WRITE 0x0000000fU + +#endif /* __MAC_PCU_BF_RPT2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BF_RPT2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BF_RPT2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_1 */ +#ifndef __MAC_PCU_TX_ANT_1_MACRO__ +#define __MAC_PCU_TX_ANT_1_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TX_ANT_1__VALUE__SHIFT 0 +#define MAC_PCU_TX_ANT_1__VALUE__WIDTH 32 +#define MAC_PCU_TX_ANT_1__VALUE__MASK 0xffffffffU +#define MAC_PCU_TX_ANT_1__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TX_ANT_1__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TX_ANT_1__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TX_ANT_1__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TX_ANT_1__TYPE u_int32_t +#define MAC_PCU_TX_ANT_1__READ 0xffffffffU +#define MAC_PCU_TX_ANT_1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TX_ANT_1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_2 */ +#ifndef __MAC_PCU_TX_ANT_2_MACRO__ +#define __MAC_PCU_TX_ANT_2_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TX_ANT_2__VALUE__SHIFT 0 +#define MAC_PCU_TX_ANT_2__VALUE__WIDTH 32 +#define MAC_PCU_TX_ANT_2__VALUE__MASK 0xffffffffU +#define MAC_PCU_TX_ANT_2__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TX_ANT_2__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TX_ANT_2__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TX_ANT_2__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TX_ANT_2__TYPE u_int32_t +#define MAC_PCU_TX_ANT_2__READ 0xffffffffU +#define MAC_PCU_TX_ANT_2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TX_ANT_2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_3 */ +#ifndef __MAC_PCU_TX_ANT_3_MACRO__ +#define __MAC_PCU_TX_ANT_3_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TX_ANT_3__VALUE__SHIFT 0 +#define MAC_PCU_TX_ANT_3__VALUE__WIDTH 32 +#define MAC_PCU_TX_ANT_3__VALUE__MASK 0xffffffffU +#define MAC_PCU_TX_ANT_3__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TX_ANT_3__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TX_ANT_3__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TX_ANT_3__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TX_ANT_3__TYPE u_int32_t +#define MAC_PCU_TX_ANT_3__READ 0xffffffffU +#define MAC_PCU_TX_ANT_3__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TX_ANT_3_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_3 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_4 */ +#ifndef __MAC_PCU_TX_ANT_4_MACRO__ +#define __MAC_PCU_TX_ANT_4_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TX_ANT_4__VALUE__SHIFT 0 +#define MAC_PCU_TX_ANT_4__VALUE__WIDTH 32 +#define MAC_PCU_TX_ANT_4__VALUE__MASK 0xffffffffU +#define MAC_PCU_TX_ANT_4__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TX_ANT_4__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TX_ANT_4__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TX_ANT_4__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TX_ANT_4__TYPE u_int32_t +#define MAC_PCU_TX_ANT_4__READ 0xffffffffU +#define MAC_PCU_TX_ANT_4__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TX_ANT_4_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_4 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRMODE */ +#ifndef __MAC_PCU_XRMODE_MACRO__ +#define __MAC_PCU_XRMODE_MACRO__ + +/* macros for field POLL_TYPE */ +#define MAC_PCU_XRMODE__POLL_TYPE__SHIFT 0 +#define MAC_PCU_XRMODE__POLL_TYPE__WIDTH 6 +#define MAC_PCU_XRMODE__POLL_TYPE__MASK 0x0000003fU +#define MAC_PCU_XRMODE__POLL_TYPE__READ(src) (u_int32_t)(src) & 0x0000003fU +#define MAC_PCU_XRMODE__POLL_TYPE__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define MAC_PCU_XRMODE__POLL_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define MAC_PCU_XRMODE__POLL_TYPE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field WAIT_FOR_POLL */ +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__SHIFT 7 +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__WIDTH 1 +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__MASK 0x00000080U +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_XRMODE__WAIT_FOR_POLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field FRAME_HOLD */ +#define MAC_PCU_XRMODE__FRAME_HOLD__SHIFT 20 +#define MAC_PCU_XRMODE__FRAME_HOLD__WIDTH 12 +#define MAC_PCU_XRMODE__FRAME_HOLD__MASK 0xfff00000U +#define MAC_PCU_XRMODE__FRAME_HOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0xfff00000U) >> 20) +#define MAC_PCU_XRMODE__FRAME_HOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0xfff00000U) +#define MAC_PCU_XRMODE__FRAME_HOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfff00000U) | (((u_int32_t)(src) <<\ + 20) & 0xfff00000U) +#define MAC_PCU_XRMODE__FRAME_HOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0xfff00000U))) +#define MAC_PCU_XRMODE__TYPE u_int32_t +#define MAC_PCU_XRMODE__READ 0xfff000bfU +#define MAC_PCU_XRMODE__WRITE 0xfff000bfU + +#endif /* __MAC_PCU_XRMODE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_XRMODE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRMODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRDEL */ +#ifndef __MAC_PCU_XRDEL_MACRO__ +#define __MAC_PCU_XRDEL_MACRO__ + +/* macros for field SLOT_DELAY */ +#define MAC_PCU_XRDEL__SLOT_DELAY__SHIFT 0 +#define MAC_PCU_XRDEL__SLOT_DELAY__WIDTH 16 +#define MAC_PCU_XRDEL__SLOT_DELAY__MASK 0x0000ffffU +#define MAC_PCU_XRDEL__SLOT_DELAY__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_XRDEL__SLOT_DELAY__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_PCU_XRDEL__SLOT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_XRDEL__SLOT_DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field CHIRP_DATA_DELAY */ +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__SHIFT 16 +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WIDTH 16 +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MASK 0xffff0000U +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_XRDEL__TYPE u_int32_t +#define MAC_PCU_XRDEL__READ 0xffffffffU +#define MAC_PCU_XRDEL__WRITE 0xffffffffU + +#endif /* __MAC_PCU_XRDEL_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_XRDEL */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRDEL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRTO */ +#ifndef __MAC_PCU_XRTO_MACRO__ +#define __MAC_PCU_XRTO_MACRO__ + +/* macros for field CHIRP_TIMEOUT */ +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__SHIFT 0 +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__WIDTH 16 +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__MASK 0x0000ffffU +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_XRTO__CHIRP_TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field POLL_TIMEOUT */ +#define MAC_PCU_XRTO__POLL_TIMEOUT__SHIFT 16 +#define MAC_PCU_XRTO__POLL_TIMEOUT__WIDTH 16 +#define MAC_PCU_XRTO__POLL_TIMEOUT__MASK 0xffff0000U +#define MAC_PCU_XRTO__POLL_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_XRTO__POLL_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_XRTO__POLL_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_XRTO__POLL_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_XRTO__TYPE u_int32_t +#define MAC_PCU_XRTO__READ 0xffffffffU +#define MAC_PCU_XRTO__WRITE 0xffffffffU + +#endif /* __MAC_PCU_XRTO_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_XRTO */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRTO__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRCRP */ +#ifndef __MAC_PCU_XRCRP_MACRO__ +#define __MAC_PCU_XRCRP_MACRO__ + +/* macros for field SEND_CHIRP */ +#define MAC_PCU_XRCRP__SEND_CHIRP__SHIFT 0 +#define MAC_PCU_XRCRP__SEND_CHIRP__WIDTH 1 +#define MAC_PCU_XRCRP__SEND_CHIRP__MASK 0x00000001U +#define MAC_PCU_XRCRP__SEND_CHIRP__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_XRCRP__SEND_CHIRP__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_PCU_XRCRP__SEND_CHIRP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_XRCRP__SEND_CHIRP__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_XRCRP__SEND_CHIRP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_XRCRP__SEND_CHIRP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field CHIRP_GAP */ +#define MAC_PCU_XRCRP__CHIRP_GAP__SHIFT 16 +#define MAC_PCU_XRCRP__CHIRP_GAP__WIDTH 16 +#define MAC_PCU_XRCRP__CHIRP_GAP__MASK 0xffff0000U +#define MAC_PCU_XRCRP__CHIRP_GAP__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_XRCRP__CHIRP_GAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_XRCRP__CHIRP_GAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_XRCRP__CHIRP_GAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_XRCRP__TYPE u_int32_t +#define MAC_PCU_XRCRP__READ 0xffff0001U +#define MAC_PCU_XRCRP__WRITE 0xffff0001U + +#endif /* __MAC_PCU_XRCRP_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_XRCRP */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRCRP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRSTMP */ +#ifndef __MAC_PCU_XRSTMP_MACRO__ +#define __MAC_PCU_XRSTMP_MACRO__ + +/* macros for field RX_ABORT_RSSI */ +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__SHIFT 0 +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WIDTH 1 +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MASK 0x00000001U +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RX_ABORT_BSSID */ +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__SHIFT 1 +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WIDTH 1 +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MASK 0x00000002U +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field TX_STOMP_RSSI */ +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__SHIFT 2 +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WIDTH 1 +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MASK 0x00000004U +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field TX_STOMP_BSSID */ +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__SHIFT 3 +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WIDTH 1 +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MASK 0x00000008U +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field TX_STOMP_DATA */ +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__SHIFT 4 +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__WIDTH 1 +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__MASK 0x00000010U +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_XRSTMP__TX_STOMP_DATA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field RX_ABORT_DATA */ +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__SHIFT 5 +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__WIDTH 1 +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__MASK 0x00000020U +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_XRSTMP__RX_ABORT_DATA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field TX_STOMP_RSSI_THRESH */ +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__SHIFT 8 +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WIDTH 8 +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MASK 0x0000ff00U +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field RX_ABORT_RSSI_THRESH */ +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__SHIFT 16 +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WIDTH 8 +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MASK 0x00ff0000U +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MAC_PCU_XRSTMP__TYPE u_int32_t +#define MAC_PCU_XRSTMP__READ 0x00ffff3fU +#define MAC_PCU_XRSTMP__WRITE 0x00ffff3fU + +#endif /* __MAC_PCU_XRSTMP_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_XRSTMP */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRSTMP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP1 */ +#ifndef __MAC_PCU_SLP1_MACRO__ +#define __MAC_PCU_SLP1_MACRO__ + +/* macros for field ASSUME_DTIM */ +#define MAC_PCU_SLP1__ASSUME_DTIM__SHIFT 19 +#define MAC_PCU_SLP1__ASSUME_DTIM__WIDTH 1 +#define MAC_PCU_SLP1__ASSUME_DTIM__MASK 0x00080000U +#define MAC_PCU_SLP1__ASSUME_DTIM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_SLP1__ASSUME_DTIM__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_SLP1__ASSUME_DTIM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_SLP1__ASSUME_DTIM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_SLP1__ASSUME_DTIM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_SLP1__ASSUME_DTIM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field CAB_TIMEOUT */ +#define MAC_PCU_SLP1__CAB_TIMEOUT__SHIFT 21 +#define MAC_PCU_SLP1__CAB_TIMEOUT__WIDTH 11 +#define MAC_PCU_SLP1__CAB_TIMEOUT__MASK 0xffe00000U +#define MAC_PCU_SLP1__CAB_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0xffe00000U) >> 21) +#define MAC_PCU_SLP1__CAB_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0xffe00000U) +#define MAC_PCU_SLP1__CAB_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffe00000U) | (((u_int32_t)(src) <<\ + 21) & 0xffe00000U) +#define MAC_PCU_SLP1__CAB_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0xffe00000U))) +#define MAC_PCU_SLP1__TYPE u_int32_t +#define MAC_PCU_SLP1__READ 0xffe80000U +#define MAC_PCU_SLP1__WRITE 0xffe80000U + +#endif /* __MAC_PCU_SLP1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_SLP1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP2 */ +#ifndef __MAC_PCU_SLP2_MACRO__ +#define __MAC_PCU_SLP2_MACRO__ + +/* macros for field BEACON_TIMEOUT */ +#define MAC_PCU_SLP2__BEACON_TIMEOUT__SHIFT 21 +#define MAC_PCU_SLP2__BEACON_TIMEOUT__WIDTH 11 +#define MAC_PCU_SLP2__BEACON_TIMEOUT__MASK 0xffe00000U +#define MAC_PCU_SLP2__BEACON_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0xffe00000U) >> 21) +#define MAC_PCU_SLP2__BEACON_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0xffe00000U) +#define MAC_PCU_SLP2__BEACON_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffe00000U) | (((u_int32_t)(src) <<\ + 21) & 0xffe00000U) +#define MAC_PCU_SLP2__BEACON_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0xffe00000U))) +#define MAC_PCU_SLP2__TYPE u_int32_t +#define MAC_PCU_SLP2__READ 0xffe00000U +#define MAC_PCU_SLP2__WRITE 0xffe00000U + +#endif /* __MAC_PCU_SLP2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_SLP2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SELF_GEN_DEFAULT */ +#ifndef __MAC_PCU_SELF_GEN_DEFAULT_MACRO__ +#define __MAC_PCU_SELF_GEN_DEFAULT_MACRO__ + +/* macros for field MMSS */ +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__SHIFT 0 +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WIDTH 3 +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MASK 0x00000007U +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field CEC */ +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__SHIFT 3 +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__WIDTH 2 +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__MASK 0x00000018U +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000018U) >> 3) +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000018U) +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000018U) | (((u_int32_t)(src) <<\ + 3) & 0x00000018U) +#define MAC_PCU_SELF_GEN_DEFAULT__CEC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000018U))) + +/* macros for field STAGGER_SOUNDING */ +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__SHIFT 5 +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WIDTH 1 +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MASK 0x00000020U +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define MAC_PCU_SELF_GEN_DEFAULT__TYPE u_int32_t +#define MAC_PCU_SELF_GEN_DEFAULT__READ 0x0000003fU +#define MAC_PCU_SELF_GEN_DEFAULT__WRITE 0x0000003fU + +#endif /* __MAC_PCU_SELF_GEN_DEFAULT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_SELF_GEN_DEFAULT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_SELF_GEN_DEFAULT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_ADDR1_MASK_L32 */ +#ifndef __MAC_PCU_ADDR1_MASK_L32_MACRO__ +#define __MAC_PCU_ADDR1_MASK_L32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_ADDR1_MASK_L32__VALUE__SHIFT 0 +#define MAC_PCU_ADDR1_MASK_L32__VALUE__WIDTH 32 +#define MAC_PCU_ADDR1_MASK_L32__VALUE__MASK 0xffffffffU +#define MAC_PCU_ADDR1_MASK_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_ADDR1_MASK_L32__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_ADDR1_MASK_L32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_ADDR1_MASK_L32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_ADDR1_MASK_L32__TYPE u_int32_t +#define MAC_PCU_ADDR1_MASK_L32__READ 0xffffffffU +#define MAC_PCU_ADDR1_MASK_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_ADDR1_MASK_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_ADDR1_MASK_L32 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_ADDR1_MASK_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_ADDR1_MASK_U16 */ +#ifndef __MAC_PCU_ADDR1_MASK_U16_MACRO__ +#define __MAC_PCU_ADDR1_MASK_U16_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_ADDR1_MASK_U16__VALUE__SHIFT 0 +#define MAC_PCU_ADDR1_MASK_U16__VALUE__WIDTH 16 +#define MAC_PCU_ADDR1_MASK_U16__VALUE__MASK 0x0000ffffU +#define MAC_PCU_ADDR1_MASK_U16__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_ADDR1_MASK_U16__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_ADDR1_MASK_U16__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_ADDR1_MASK_U16__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_ADDR1_MASK_U16__TYPE u_int32_t +#define MAC_PCU_ADDR1_MASK_U16__READ 0x0000ffffU +#define MAC_PCU_ADDR1_MASK_U16__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_ADDR1_MASK_U16_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_ADDR1_MASK_U16 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_ADDR1_MASK_U16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TPC */ +#ifndef __MAC_PCU_TPC_MACRO__ +#define __MAC_PCU_TPC_MACRO__ + +/* macros for field ACK_PWR */ +#define MAC_PCU_TPC__ACK_PWR__SHIFT 0 +#define MAC_PCU_TPC__ACK_PWR__WIDTH 6 +#define MAC_PCU_TPC__ACK_PWR__MASK 0x0000003fU +#define MAC_PCU_TPC__ACK_PWR__READ(src) (u_int32_t)(src) & 0x0000003fU +#define MAC_PCU_TPC__ACK_PWR__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define MAC_PCU_TPC__ACK_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define MAC_PCU_TPC__ACK_PWR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field CTS_PWR */ +#define MAC_PCU_TPC__CTS_PWR__SHIFT 8 +#define MAC_PCU_TPC__CTS_PWR__WIDTH 6 +#define MAC_PCU_TPC__CTS_PWR__MASK 0x00003f00U +#define MAC_PCU_TPC__CTS_PWR__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8) +#define MAC_PCU_TPC__CTS_PWR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define MAC_PCU_TPC__CTS_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define MAC_PCU_TPC__CTS_PWR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field CHIRP_PWR */ +#define MAC_PCU_TPC__CHIRP_PWR__SHIFT 16 +#define MAC_PCU_TPC__CHIRP_PWR__WIDTH 6 +#define MAC_PCU_TPC__CHIRP_PWR__MASK 0x003f0000U +#define MAC_PCU_TPC__CHIRP_PWR__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define MAC_PCU_TPC__CHIRP_PWR__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define MAC_PCU_TPC__CHIRP_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define MAC_PCU_TPC__CHIRP_PWR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field RPT_PWR */ +#define MAC_PCU_TPC__RPT_PWR__SHIFT 24 +#define MAC_PCU_TPC__RPT_PWR__WIDTH 6 +#define MAC_PCU_TPC__RPT_PWR__MASK 0x3f000000U +#define MAC_PCU_TPC__RPT_PWR__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define MAC_PCU_TPC__RPT_PWR__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define MAC_PCU_TPC__RPT_PWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define MAC_PCU_TPC__RPT_PWR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define MAC_PCU_TPC__TYPE u_int32_t +#define MAC_PCU_TPC__READ 0x3f3f3f3fU +#define MAC_PCU_TPC__WRITE 0x3f3f3f3fU + +#endif /* __MAC_PCU_TPC_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TPC */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TPC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_FRAME_CNT */ +#ifndef __MAC_PCU_TX_FRAME_CNT_MACRO__ +#define __MAC_PCU_TX_FRAME_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TX_FRAME_CNT__VALUE__SHIFT 0 +#define MAC_PCU_TX_FRAME_CNT__VALUE__WIDTH 32 +#define MAC_PCU_TX_FRAME_CNT__VALUE__MASK 0xffffffffU +#define MAC_PCU_TX_FRAME_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TX_FRAME_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_TX_FRAME_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TX_FRAME_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TX_FRAME_CNT__TYPE u_int32_t +#define MAC_PCU_TX_FRAME_CNT__READ 0xffffffffU +#define MAC_PCU_TX_FRAME_CNT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TX_FRAME_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TX_FRAME_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_FRAME_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_FRAME_CNT */ +#ifndef __MAC_PCU_RX_FRAME_CNT_MACRO__ +#define __MAC_PCU_RX_FRAME_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_RX_FRAME_CNT__VALUE__SHIFT 0 +#define MAC_PCU_RX_FRAME_CNT__VALUE__WIDTH 32 +#define MAC_PCU_RX_FRAME_CNT__VALUE__MASK 0xffffffffU +#define MAC_PCU_RX_FRAME_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_RX_FRAME_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_RX_FRAME_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_RX_FRAME_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_RX_FRAME_CNT__TYPE u_int32_t +#define MAC_PCU_RX_FRAME_CNT__READ 0xffffffffU +#define MAC_PCU_RX_FRAME_CNT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_RX_FRAME_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_RX_FRAME_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_FRAME_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_CLEAR_CNT */ +#ifndef __MAC_PCU_RX_CLEAR_CNT_MACRO__ +#define __MAC_PCU_RX_CLEAR_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_RX_CLEAR_CNT__VALUE__SHIFT 0 +#define MAC_PCU_RX_CLEAR_CNT__VALUE__WIDTH 32 +#define MAC_PCU_RX_CLEAR_CNT__VALUE__MASK 0xffffffffU +#define MAC_PCU_RX_CLEAR_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_RX_CLEAR_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_RX_CLEAR_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_RX_CLEAR_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_RX_CLEAR_CNT__TYPE u_int32_t +#define MAC_PCU_RX_CLEAR_CNT__READ 0xffffffffU +#define MAC_PCU_RX_CLEAR_CNT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_RX_CLEAR_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_RX_CLEAR_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_CLEAR_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_CYCLE_CNT */ +#ifndef __MAC_PCU_CYCLE_CNT_MACRO__ +#define __MAC_PCU_CYCLE_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_CYCLE_CNT__VALUE__SHIFT 0 +#define MAC_PCU_CYCLE_CNT__VALUE__WIDTH 32 +#define MAC_PCU_CYCLE_CNT__VALUE__MASK 0xffffffffU +#define MAC_PCU_CYCLE_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_CYCLE_CNT__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_CYCLE_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_CYCLE_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_CYCLE_CNT__TYPE u_int32_t +#define MAC_PCU_CYCLE_CNT__READ 0xffffffffU +#define MAC_PCU_CYCLE_CNT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_CYCLE_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_CYCLE_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_CYCLE_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_QUIET_TIME_1 */ +#ifndef __MAC_PCU_QUIET_TIME_1_MACRO__ +#define __MAC_PCU_QUIET_TIME_1_MACRO__ + +/* macros for field ACK_CTS_ENABLE */ +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__SHIFT 17 +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WIDTH 1 +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MASK 0x00020000U +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) +#define MAC_PCU_QUIET_TIME_1__TYPE u_int32_t +#define MAC_PCU_QUIET_TIME_1__READ 0x00020000U +#define MAC_PCU_QUIET_TIME_1__WRITE 0x00020000U + +#endif /* __MAC_PCU_QUIET_TIME_1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_QUIET_TIME_1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_QUIET_TIME_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_QUIET_TIME_2 */ +#ifndef __MAC_PCU_QUIET_TIME_2_MACRO__ +#define __MAC_PCU_QUIET_TIME_2_MACRO__ + +/* macros for field DURATION */ +#define MAC_PCU_QUIET_TIME_2__DURATION__SHIFT 16 +#define MAC_PCU_QUIET_TIME_2__DURATION__WIDTH 16 +#define MAC_PCU_QUIET_TIME_2__DURATION__MASK 0xffff0000U +#define MAC_PCU_QUIET_TIME_2__DURATION__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_QUIET_TIME_2__DURATION__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_QUIET_TIME_2__DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_QUIET_TIME_2__DURATION__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_QUIET_TIME_2__TYPE u_int32_t +#define MAC_PCU_QUIET_TIME_2__READ 0xffff0000U +#define MAC_PCU_QUIET_TIME_2__WRITE 0xffff0000U + +#endif /* __MAC_PCU_QUIET_TIME_2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_QUIET_TIME_2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_QUIET_TIME_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_QOS_NO_ACK */ +#ifndef __MAC_PCU_QOS_NO_ACK_MACRO__ +#define __MAC_PCU_QOS_NO_ACK_MACRO__ + +/* macros for field TWO_BIT_VALUES */ +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__SHIFT 0 +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WIDTH 4 +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MASK 0x0000000fU +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field BIT_OFFSET */ +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__SHIFT 4 +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WIDTH 3 +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MASK 0x00000070U +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000070U) >> 4) +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field BYTE_OFFSET */ +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__SHIFT 7 +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WIDTH 2 +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MASK 0x00000180U +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000180U) >> 7) +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000180U) +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000180U) | (((u_int32_t)(src) <<\ + 7) & 0x00000180U) +#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000180U))) +#define MAC_PCU_QOS_NO_ACK__TYPE u_int32_t +#define MAC_PCU_QOS_NO_ACK__READ 0x000001ffU +#define MAC_PCU_QOS_NO_ACK__WRITE 0x000001ffU + +#endif /* __MAC_PCU_QOS_NO_ACK_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_QOS_NO_ACK */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_QOS_NO_ACK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_MASK */ +#ifndef __MAC_PCU_PHY_ERROR_MASK_MACRO__ +#define __MAC_PCU_PHY_ERROR_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERROR_MASK__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERROR_MASK__VALUE__WIDTH 32 +#define MAC_PCU_PHY_ERROR_MASK__VALUE__MASK 0xffffffffU +#define MAC_PCU_PHY_ERROR_MASK__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_PHY_ERROR_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_PHY_ERROR_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_PHY_ERROR_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_PHY_ERROR_MASK__TYPE u_int32_t +#define MAC_PCU_PHY_ERROR_MASK__READ 0xffffffffU +#define MAC_PCU_PHY_ERROR_MASK__WRITE 0xffffffffU + +#endif /* __MAC_PCU_PHY_ERROR_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_MASK */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRLAT */ +#ifndef __MAC_PCU_XRLAT_MACRO__ +#define __MAC_PCU_XRLAT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_XRLAT__VALUE__SHIFT 0 +#define MAC_PCU_XRLAT__VALUE__WIDTH 12 +#define MAC_PCU_XRLAT__VALUE__MASK 0x00000fffU +#define MAC_PCU_XRLAT__VALUE__READ(src) (u_int32_t)(src) & 0x00000fffU +#define MAC_PCU_XRLAT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) +#define MAC_PCU_XRLAT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define MAC_PCU_XRLAT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) +#define MAC_PCU_XRLAT__TYPE u_int32_t +#define MAC_PCU_XRLAT__READ 0x00000fffU +#define MAC_PCU_XRLAT__WRITE 0x00000fffU + +#endif /* __MAC_PCU_XRLAT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_XRLAT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRLAT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RXBUF */ +#ifndef __MAC_PCU_RXBUF_MACRO__ +#define __MAC_PCU_RXBUF_MACRO__ + +/* macros for field HIGH_PRIORITY_THRSHD */ +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__SHIFT 0 +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WIDTH 11 +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MASK 0x000007ffU +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__READ(src) \ + (u_int32_t)(src)\ + & 0x000007ffU +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000007ffU) +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000007ffU))) + +/* macros for field REG_RD_ENABLE */ +#define MAC_PCU_RXBUF__REG_RD_ENABLE__SHIFT 11 +#define MAC_PCU_RXBUF__REG_RD_ENABLE__WIDTH 1 +#define MAC_PCU_RXBUF__REG_RD_ENABLE__MASK 0x00000800U +#define MAC_PCU_RXBUF__REG_RD_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_RXBUF__REG_RD_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_RXBUF__REG_RD_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_RXBUF__REG_RD_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_RXBUF__REG_RD_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_RXBUF__REG_RD_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) +#define MAC_PCU_RXBUF__TYPE u_int32_t +#define MAC_PCU_RXBUF__READ 0x00000fffU +#define MAC_PCU_RXBUF__WRITE 0x00000fffU + +#endif /* __MAC_PCU_RXBUF_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_RXBUF */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_RXBUF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MIC_QOS_CONTROL */ +#ifndef __MAC_PCU_MIC_QOS_CONTROL_MACRO__ +#define __MAC_PCU_MIC_QOS_CONTROL_MACRO__ + +/* macros for field VALUE_0 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__SHIFT 0 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MASK 0x00000003U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field VALUE_1 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__SHIFT 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MASK 0x0000000cU +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field VALUE_2 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__SHIFT 4 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MASK 0x00000030U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field VALUE_3 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__SHIFT 6 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MASK 0x000000c0U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field VALUE_4 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__SHIFT 8 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MASK 0x00000300U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field VALUE_5 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__SHIFT 10 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MASK 0x00000c00U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) + +/* macros for field VALUE_6 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__SHIFT 12 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MASK 0x00003000U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003000U) >> 12) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00003000U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((u_int32_t)(src) <<\ + 12) & 0x00003000U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00003000U))) + +/* macros for field VALUE_7 */ +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__SHIFT 14 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WIDTH 2 +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MASK 0x0000c000U +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field ENABLE */ +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__SHIFT 16 +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WIDTH 1 +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MASK 0x00010000U +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) +#define MAC_PCU_MIC_QOS_CONTROL__TYPE u_int32_t +#define MAC_PCU_MIC_QOS_CONTROL__READ 0x0001ffffU +#define MAC_PCU_MIC_QOS_CONTROL__WRITE 0x0001ffffU + +#endif /* __MAC_PCU_MIC_QOS_CONTROL_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_MIC_QOS_CONTROL */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_MIC_QOS_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MIC_QOS_SELECT */ +#ifndef __MAC_PCU_MIC_QOS_SELECT_MACRO__ +#define __MAC_PCU_MIC_QOS_SELECT_MACRO__ + +/* macros for field VALUE_0 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__SHIFT 0 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MASK 0x0000000fU +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field VALUE_1 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__SHIFT 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MASK 0x000000f0U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field VALUE_2 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__SHIFT 8 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MASK 0x00000f00U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field VALUE_3 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__SHIFT 12 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MASK 0x0000f000U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field VALUE_4 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__SHIFT 16 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MASK 0x000f0000U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field VALUE_5 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__SHIFT 20 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MASK 0x00f00000U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) + +/* macros for field VALUE_6 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__SHIFT 24 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MASK 0x0f000000U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) + +/* macros for field VALUE_7 */ +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__SHIFT 28 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WIDTH 4 +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MASK 0xf0000000U +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__READ(src) \ + (((u_int32_t)(src)\ + & 0xf0000000U) >> 28) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0xf0000000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((u_int32_t)(src) <<\ + 28) & 0xf0000000U) +#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0xf0000000U))) +#define MAC_PCU_MIC_QOS_SELECT__TYPE u_int32_t +#define MAC_PCU_MIC_QOS_SELECT__READ 0xffffffffU +#define MAC_PCU_MIC_QOS_SELECT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_MIC_QOS_SELECT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_MIC_QOS_SELECT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_MIC_QOS_SELECT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE */ +#ifndef __MAC_PCU_MISC_MODE_MACRO__ +#define __MAC_PCU_MISC_MODE_MACRO__ + +/* macros for field BSSID_MATCH_FORCE */ +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__SHIFT 0 +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WIDTH 1 +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MASK 0x00000001U +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field DEBUG_MODE_AD */ +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__SHIFT 1 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WIDTH 1 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MASK 0x00000002U +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field MIC_NEW_LOCATION_ENABLE */ +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__SHIFT 2 +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MASK 0x00000004U +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field TX_ADD_TSF */ +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__SHIFT 3 +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__WIDTH 1 +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__MASK 0x00000008U +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_MISC_MODE__TX_ADD_TSF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field CCK_SIFS_MODE */ +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__SHIFT 4 +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WIDTH 1 +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MASK 0x00000010U +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field RXSM2SVD_PRE_RST */ +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__SHIFT 5 +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WIDTH 1 +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MASK 0x00000020U +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field RCV_DELAY_SOUNDING_IM_TXBF */ +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__SHIFT 6 +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WIDTH 1 +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MASK 0x00000040U +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field DEBUG_MODE_BA_BITMAP */ +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__SHIFT 9 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WIDTH 1 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MASK 0x00000200U +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field DEBUG_MODE_SIFS */ +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__SHIFT 10 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WIDTH 1 +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MASK 0x00000400U +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field KC_RX_ANT_UPDATE */ +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__SHIFT 11 +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WIDTH 1 +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MASK 0x00000800U +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field TXOP_TBTT_LIMIT_ENABLE */ +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__SHIFT 12 +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MASK 0x00001000U +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field MISS_BEACON_IN_SLEEP */ +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__SHIFT 14 +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WIDTH 1 +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MASK 0x00004000U +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field FORCE_QUIET_COLLISION */ +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__SHIFT 18 +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WIDTH 1 +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MASK 0x00040000U +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field BT_ANT_PREVENTS_RX */ +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__SHIFT 20 +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WIDTH 1 +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MASK 0x00100000U +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field TBTT_PROTECT */ +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__SHIFT 21 +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__WIDTH 1 +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__MASK 0x00200000U +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_MISC_MODE__TBTT_PROTECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field HCF_POLL_CANCELS_NAV */ +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__SHIFT 22 +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WIDTH 1 +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MASK 0x00400000U +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field RX_HCF_POLL_ENABLE */ +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__SHIFT 23 +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MASK 0x00800000U +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field CLEAR_VMF */ +#define MAC_PCU_MISC_MODE__CLEAR_VMF__SHIFT 24 +#define MAC_PCU_MISC_MODE__CLEAR_VMF__WIDTH 1 +#define MAC_PCU_MISC_MODE__CLEAR_VMF__MASK 0x01000000U +#define MAC_PCU_MISC_MODE__CLEAR_VMF__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_MISC_MODE__CLEAR_VMF__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_MISC_MODE__CLEAR_VMF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_MISC_MODE__CLEAR_VMF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_MISC_MODE__CLEAR_VMF__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_MISC_MODE__CLEAR_VMF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field CLEAR_FIRST_HCF */ +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__SHIFT 25 +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WIDTH 1 +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MASK 0x02000000U +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field CLEAR_BA_VALID */ +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__SHIFT 26 +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WIDTH 1 +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MASK 0x04000000U +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field SEL_EVM */ +#define MAC_PCU_MISC_MODE__SEL_EVM__SHIFT 27 +#define MAC_PCU_MISC_MODE__SEL_EVM__WIDTH 1 +#define MAC_PCU_MISC_MODE__SEL_EVM__MASK 0x08000000U +#define MAC_PCU_MISC_MODE__SEL_EVM__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_PCU_MISC_MODE__SEL_EVM__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_PCU_MISC_MODE__SEL_EVM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_PCU_MISC_MODE__SEL_EVM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_PCU_MISC_MODE__SEL_EVM__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_PCU_MISC_MODE__SEL_EVM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field ALWAYS_PERFORM_KEY_SEARCH */ +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__SHIFT 28 +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WIDTH 1 +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MASK 0x10000000U +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field USE_EOP_PTR_FOR_DMA_WR */ +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__SHIFT 29 +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WIDTH 1 +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MASK 0x20000000U +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field DEBUG_MODE */ +#define MAC_PCU_MISC_MODE__DEBUG_MODE__SHIFT 30 +#define MAC_PCU_MISC_MODE__DEBUG_MODE__WIDTH 2 +#define MAC_PCU_MISC_MODE__DEBUG_MODE__MASK 0xc0000000U +#define MAC_PCU_MISC_MODE__DEBUG_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define MAC_PCU_MISC_MODE__DEBUG_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define MAC_PCU_MISC_MODE__DEBUG_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define MAC_PCU_MISC_MODE__TYPE u_int32_t +#define MAC_PCU_MISC_MODE__READ 0xfff45e7fU +#define MAC_PCU_MISC_MODE__WRITE 0xfff45e7fU + +#endif /* __MAC_PCU_MISC_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_OFDM_CNT */ +#ifndef __MAC_PCU_FILTER_OFDM_CNT_MACRO__ +#define __MAC_PCU_FILTER_OFDM_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__SHIFT 0 +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__WIDTH 24 +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__MASK 0x00ffffffU +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x00ffffffU +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_FILTER_OFDM_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define MAC_PCU_FILTER_OFDM_CNT__TYPE u_int32_t +#define MAC_PCU_FILTER_OFDM_CNT__READ 0x00ffffffU +#define MAC_PCU_FILTER_OFDM_CNT__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_FILTER_OFDM_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_FILTER_OFDM_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_OFDM_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_CCK_CNT */ +#ifndef __MAC_PCU_FILTER_CCK_CNT_MACRO__ +#define __MAC_PCU_FILTER_CCK_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_FILTER_CCK_CNT__VALUE__SHIFT 0 +#define MAC_PCU_FILTER_CCK_CNT__VALUE__WIDTH 24 +#define MAC_PCU_FILTER_CCK_CNT__VALUE__MASK 0x00ffffffU +#define MAC_PCU_FILTER_CCK_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_PCU_FILTER_CCK_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define MAC_PCU_FILTER_CCK_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_FILTER_CCK_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define MAC_PCU_FILTER_CCK_CNT__TYPE u_int32_t +#define MAC_PCU_FILTER_CCK_CNT__READ 0x00ffffffU +#define MAC_PCU_FILTER_CCK_CNT__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_FILTER_CCK_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_FILTER_CCK_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_CCK_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_1 */ +#ifndef __MAC_PCU_PHY_ERR_CNT_1_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_1_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__WIDTH 24 +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__MASK 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_1__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define MAC_PCU_PHY_ERR_CNT_1__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_1__READ 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_1__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_1_MASK */ +#ifndef __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WIDTH 32 +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MASK 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_PHY_ERR_CNT_1_MASK__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_1_MASK__READ 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_1_MASK__WRITE 0xffffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_1_MASK */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_1_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_2 */ +#ifndef __MAC_PCU_PHY_ERR_CNT_2_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_2_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__WIDTH 24 +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__MASK 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_2__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define MAC_PCU_PHY_ERR_CNT_2__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_2__READ 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_2__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_2_MASK */ +#ifndef __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WIDTH 32 +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MASK 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_PHY_ERR_CNT_2_MASK__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_2_MASK__READ 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_2_MASK__WRITE 0xffffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_2_MASK */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_2_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_THRESHOLD */ +#ifndef __MAC_PCU_TSF_THRESHOLD_MACRO__ +#define __MAC_PCU_TSF_THRESHOLD_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TSF_THRESHOLD__VALUE__SHIFT 0 +#define MAC_PCU_TSF_THRESHOLD__VALUE__WIDTH 16 +#define MAC_PCU_TSF_THRESHOLD__VALUE__MASK 0x0000ffffU +#define MAC_PCU_TSF_THRESHOLD__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_TSF_THRESHOLD__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_TSF_THRESHOLD__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_TSF_THRESHOLD__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_TSF_THRESHOLD__TYPE u_int32_t +#define MAC_PCU_TSF_THRESHOLD__READ 0x0000ffffU +#define MAC_PCU_TSF_THRESHOLD__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_TSF_THRESHOLD_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TSF_THRESHOLD */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_THRESHOLD__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE4 */ +#ifndef __MAC_PCU_MISC_MODE4_MACRO__ +#define __MAC_PCU_MISC_MODE4_MACRO__ + +/* macros for field EV_85395_FIX_DISABLE */ +#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__SHIFT 0 +#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__MASK 0x00000001U +#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field MIN_AVAILABLE_FIFO_DEPTH */ +#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__SHIFT 1 +#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__WIDTH 12 +#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__MASK 0x00001ffeU +#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001ffeU) >> 1) +#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00001ffeU) +#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001ffeU) | (((u_int32_t)(src) <<\ + 1) & 0x00001ffeU) +#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00001ffeU))) + +/* macros for field EV_83864_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__SHIFT 13 +#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__MASK 0x00002000U +#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) +#define MAC_PCU_MISC_MODE4__TYPE u_int32_t +#define MAC_PCU_MISC_MODE4__READ 0x00003fffU +#define MAC_PCU_MISC_MODE4__WRITE 0x00003fffU + +#endif /* __MAC_PCU_MISC_MODE4_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE4 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_EIFS_MASK */ +#ifndef __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__ +#define __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WIDTH 32 +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MASK 0xffffffffU +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_PHY_ERROR_EIFS_MASK__TYPE u_int32_t +#define MAC_PCU_PHY_ERROR_EIFS_MASK__READ 0xffffffffU +#define MAC_PCU_PHY_ERROR_EIFS_MASK__WRITE 0xffffffffU + +#endif /* __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_EIFS_MASK */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_EIFS_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_3 */ +#ifndef __MAC_PCU_PHY_ERR_CNT_3_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_3_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__WIDTH 24 +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__MASK 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define MAC_PCU_PHY_ERR_CNT_3__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define MAC_PCU_PHY_ERR_CNT_3__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_3__READ 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_3__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_3_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_3 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_3_MASK */ +#ifndef __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WIDTH 32 +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MASK 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_PHY_ERR_CNT_3_MASK__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_3_MASK__READ 0xffffffffU +#define MAC_PCU_PHY_ERR_CNT_3_MASK__WRITE 0xffffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_3_MASK */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_3_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE */ +#ifndef __MAC_PCU_BLUETOOTH_MODE_MACRO__ +#define __MAC_PCU_BLUETOOTH_MODE_MACRO__ + +/* macros for field TIME_EXTEND */ +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__SHIFT 0 +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MASK 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field TX_STATE_EXTEND */ +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__SHIFT 8 +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MASK 0x00000100U +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field TX_FRAME_EXTEND */ +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__SHIFT 9 +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MASK 0x00000200U +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field MODE */ +#define MAC_PCU_BLUETOOTH_MODE__MODE__SHIFT 10 +#define MAC_PCU_BLUETOOTH_MODE__MODE__WIDTH 2 +#define MAC_PCU_BLUETOOTH_MODE__MODE__MASK 0x00000c00U +#define MAC_PCU_BLUETOOTH_MODE__MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define MAC_PCU_BLUETOOTH_MODE__MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define MAC_PCU_BLUETOOTH_MODE__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define MAC_PCU_BLUETOOTH_MODE__MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) + +/* macros for field QUIET */ +#define MAC_PCU_BLUETOOTH_MODE__QUIET__SHIFT 12 +#define MAC_PCU_BLUETOOTH_MODE__QUIET__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE__QUIET__MASK 0x00001000U +#define MAC_PCU_BLUETOOTH_MODE__QUIET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_BLUETOOTH_MODE__QUIET__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_BLUETOOTH_MODE__QUIET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_BLUETOOTH_MODE__QUIET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_BLUETOOTH_MODE__QUIET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_BLUETOOTH_MODE__QUIET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field QCU_THRESH */ +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__SHIFT 13 +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WIDTH 4 +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MASK 0x0001e000U +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001e000U) >> 13) +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0001e000U) +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0001e000U) +#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0001e000U))) + +/* macros for field RX_CLEAR_POLARITY */ +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__SHIFT 17 +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MASK 0x00020000U +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field PRIORITY_TIME */ +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__SHIFT 18 +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WIDTH 6 +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MASK 0x00fc0000U +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field FIRST_SLOT_TIME */ +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__SHIFT 24 +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MASK 0xff000000U +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_BLUETOOTH_MODE__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_MODE__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_MODE__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_WL_WEIGHTS0 */ +#ifndef __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__ +#define __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_WL_WEIGHTS0 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_WL_WEIGHTS0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_HCF_TIMEOUT */ +#ifndef __MAC_PCU_HCF_TIMEOUT_MACRO__ +#define __MAC_PCU_HCF_TIMEOUT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_HCF_TIMEOUT__VALUE__SHIFT 0 +#define MAC_PCU_HCF_TIMEOUT__VALUE__WIDTH 16 +#define MAC_PCU_HCF_TIMEOUT__VALUE__MASK 0x0000ffffU +#define MAC_PCU_HCF_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_HCF_TIMEOUT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_PCU_HCF_TIMEOUT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_HCF_TIMEOUT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_HCF_TIMEOUT__TYPE u_int32_t +#define MAC_PCU_HCF_TIMEOUT__READ 0x0000ffffU +#define MAC_PCU_HCF_TIMEOUT__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_HCF_TIMEOUT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_HCF_TIMEOUT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_HCF_TIMEOUT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE2 */ +#ifndef __MAC_PCU_BLUETOOTH_MODE2_MACRO__ +#define __MAC_PCU_BLUETOOTH_MODE2_MACRO__ + +/* macros for field BCN_MISS_THRESH */ +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__SHIFT 0 +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MASK 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field BCN_MISS_CNT */ +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__SHIFT 8 +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__MASK 0x0000ff00U +#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field HOLD_RX_CLEAR */ +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__SHIFT 16 +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MASK 0x00010000U +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field SLEEP_ALLOW_BT_ACCESS */ +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__SHIFT 17 +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MASK 0x00020000U +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field PROTECT_BT_AFTER_WAKEUP */ +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__SHIFT 19 +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MASK 0x00080000U +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field DISABLE_BT_ANT */ +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__SHIFT 20 +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MASK 0x00100000U +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field QUIET_2_WIRE */ +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__SHIFT 21 +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MASK 0x00200000U +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field WL_ACTIVE_MODE */ +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__SHIFT 22 +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WIDTH 2 +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MASK 0x00c00000U +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00c00000U) >> 22) +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00c00000U) +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x00c00000U) +#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00c00000U))) + +/* macros for field WL_TXRX_SEPARATE */ +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__SHIFT 24 +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MASK 0x01000000U +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field RS_DISCARD_EXTEND */ +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__SHIFT 25 +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MASK 0x02000000U +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field TSF_BT_ACTIVE_CTRL */ +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__SHIFT 26 +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WIDTH 2 +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MASK 0x0c000000U +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0c000000U) >> 26) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x0c000000U) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) + +/* macros for field TSF_BT_PRIORITY_CTRL */ +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__SHIFT 28 +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WIDTH 2 +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MASK 0x30000000U +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x30000000U) >> 28) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x30000000U) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) + +/* macros for field INTERRUPT_ENABLE */ +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__SHIFT 30 +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MASK 0x40000000U +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PHY_ERR_BT_COLL_ENABLE */ +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__SHIFT 31 +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MASK 0x80000000U +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define MAC_PCU_BLUETOOTH_MODE2__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_MODE2__READ 0xfffbffffU +#define MAC_PCU_BLUETOOTH_MODE2__WRITE 0xfffbffffU + +#endif /* __MAC_PCU_BLUETOOTH_MODE2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS2 */ +#ifndef __MAC_PCU_GENERIC_TIMERS2_MACRO__ +#define __MAC_PCU_GENERIC_TIMERS2_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_GENERIC_TIMERS2__DATA__SHIFT 0 +#define MAC_PCU_GENERIC_TIMERS2__DATA__WIDTH 32 +#define MAC_PCU_GENERIC_TIMERS2__DATA__MASK 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS2__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_GENERIC_TIMERS2__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_GENERIC_TIMERS2__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_GENERIC_TIMERS2__TYPE u_int32_t +#define MAC_PCU_GENERIC_TIMERS2__READ 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_GENERIC_TIMERS2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS2__NUM 16 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS2_MODE */ +#ifndef __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__ +#define __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__ + +/* macros for field ENABLE */ +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__SHIFT 0 +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WIDTH 8 +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MASK 0x000000ffU +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field OVERFLOW_INDEX */ +#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__SHIFT 8 +#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__WIDTH 3 +#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__MASK 0x00000700U +#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define MAC_PCU_GENERIC_TIMERS2_MODE__TYPE u_int32_t +#define MAC_PCU_GENERIC_TIMERS2_MODE__READ 0x000007ffU +#define MAC_PCU_GENERIC_TIMERS2_MODE__WRITE 0x000007ffU + +#endif /* __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS2_MODE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS2_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_WL_WEIGHTS1 */ +#ifndef __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__ +#define __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_WL_WEIGHTS1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_WL_WEIGHTS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE */ +#ifndef __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__ +#define __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__READ 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY */ +#ifndef __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__ +#define __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__READ 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXSIFS */ +#ifndef __MAC_PCU_TXSIFS_MACRO__ +#define __MAC_PCU_TXSIFS_MACRO__ + +/* macros for field SIFS_TIME */ +#define MAC_PCU_TXSIFS__SIFS_TIME__SHIFT 0 +#define MAC_PCU_TXSIFS__SIFS_TIME__WIDTH 8 +#define MAC_PCU_TXSIFS__SIFS_TIME__MASK 0x000000ffU +#define MAC_PCU_TXSIFS__SIFS_TIME__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXSIFS__SIFS_TIME__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_TXSIFS__SIFS_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXSIFS__SIFS_TIME__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field TX_LATENCY */ +#define MAC_PCU_TXSIFS__TX_LATENCY__SHIFT 8 +#define MAC_PCU_TXSIFS__TX_LATENCY__WIDTH 4 +#define MAC_PCU_TXSIFS__TX_LATENCY__MASK 0x00000f00U +#define MAC_PCU_TXSIFS__TX_LATENCY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define MAC_PCU_TXSIFS__TX_LATENCY__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define MAC_PCU_TXSIFS__TX_LATENCY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define MAC_PCU_TXSIFS__TX_LATENCY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field ACK_SHIFT */ +#define MAC_PCU_TXSIFS__ACK_SHIFT__SHIFT 12 +#define MAC_PCU_TXSIFS__ACK_SHIFT__WIDTH 3 +#define MAC_PCU_TXSIFS__ACK_SHIFT__MASK 0x00007000U +#define MAC_PCU_TXSIFS__ACK_SHIFT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007000U) >> 12) +#define MAC_PCU_TXSIFS__ACK_SHIFT__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00007000U) +#define MAC_PCU_TXSIFS__ACK_SHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define MAC_PCU_TXSIFS__ACK_SHIFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) +#define MAC_PCU_TXSIFS__TYPE u_int32_t +#define MAC_PCU_TXSIFS__READ 0x00007fffU +#define MAC_PCU_TXSIFS__WRITE 0x00007fffU + +#endif /* __MAC_PCU_TXSIFS_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TXSIFS */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXSIFS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE3 */ +#ifndef __MAC_PCU_BLUETOOTH_MODE3_MACRO__ +#define __MAC_PCU_BLUETOOTH_MODE3_MACRO__ + +/* macros for field WL_ACTIVE_TIME */ +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__SHIFT 0 +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MASK 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field WL_QC_TIME */ +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__SHIFT 8 +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WIDTH 8 +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MASK 0x0000ff00U +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field ALLOW_CONCURRENT_ACCESS */ +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__SHIFT 16 +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WIDTH 4 +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MASK 0x000f0000U +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field AGC_SATURATION_CNT_ENABLE */ +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__SHIFT 20 +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WIDTH 1 +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MASK 0x00100000U +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) +#define MAC_PCU_BLUETOOTH_MODE3__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_MODE3__READ 0x001fffffU +#define MAC_PCU_BLUETOOTH_MODE3__WRITE 0x001fffffU + +#endif /* __MAC_PCU_BLUETOOTH_MODE3_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE3 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_X */ +#ifndef __MAC_PCU_TXOP_X_MACRO__ +#define __MAC_PCU_TXOP_X_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TXOP_X__VALUE__SHIFT 0 +#define MAC_PCU_TXOP_X__VALUE__WIDTH 8 +#define MAC_PCU_TXOP_X__VALUE__MASK 0x000000ffU +#define MAC_PCU_TXOP_X__VALUE__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXOP_X__VALUE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_TXOP_X__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXOP_X__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) +#define MAC_PCU_TXOP_X__TYPE u_int32_t +#define MAC_PCU_TXOP_X__READ 0x000000ffU +#define MAC_PCU_TXOP_X__WRITE 0x000000ffU + +#endif /* __MAC_PCU_TXOP_X_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_X */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_X__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_0_3 */ +#ifndef __MAC_PCU_TXOP_0_3_MACRO__ +#define __MAC_PCU_TXOP_0_3_MACRO__ + +/* macros for field VALUE_0 */ +#define MAC_PCU_TXOP_0_3__VALUE_0__SHIFT 0 +#define MAC_PCU_TXOP_0_3__VALUE_0__WIDTH 8 +#define MAC_PCU_TXOP_0_3__VALUE_0__MASK 0x000000ffU +#define MAC_PCU_TXOP_0_3__VALUE_0__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXOP_0_3__VALUE_0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_TXOP_0_3__VALUE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXOP_0_3__VALUE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field VALUE_1 */ +#define MAC_PCU_TXOP_0_3__VALUE_1__SHIFT 8 +#define MAC_PCU_TXOP_0_3__VALUE_1__WIDTH 8 +#define MAC_PCU_TXOP_0_3__VALUE_1__MASK 0x0000ff00U +#define MAC_PCU_TXOP_0_3__VALUE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_TXOP_0_3__VALUE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_0_3__VALUE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_0_3__VALUE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field VALUE_2 */ +#define MAC_PCU_TXOP_0_3__VALUE_2__SHIFT 16 +#define MAC_PCU_TXOP_0_3__VALUE_2__WIDTH 8 +#define MAC_PCU_TXOP_0_3__VALUE_2__MASK 0x00ff0000U +#define MAC_PCU_TXOP_0_3__VALUE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_TXOP_0_3__VALUE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_0_3__VALUE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_0_3__VALUE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field VALUE_3 */ +#define MAC_PCU_TXOP_0_3__VALUE_3__SHIFT 24 +#define MAC_PCU_TXOP_0_3__VALUE_3__WIDTH 8 +#define MAC_PCU_TXOP_0_3__VALUE_3__MASK 0xff000000U +#define MAC_PCU_TXOP_0_3__VALUE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_TXOP_0_3__VALUE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_TXOP_0_3__VALUE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_TXOP_0_3__VALUE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_TXOP_0_3__TYPE u_int32_t +#define MAC_PCU_TXOP_0_3__READ 0xffffffffU +#define MAC_PCU_TXOP_0_3__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TXOP_0_3_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_0_3 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_0_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_4_7 */ +#ifndef __MAC_PCU_TXOP_4_7_MACRO__ +#define __MAC_PCU_TXOP_4_7_MACRO__ + +/* macros for field VALUE_4 */ +#define MAC_PCU_TXOP_4_7__VALUE_4__SHIFT 0 +#define MAC_PCU_TXOP_4_7__VALUE_4__WIDTH 8 +#define MAC_PCU_TXOP_4_7__VALUE_4__MASK 0x000000ffU +#define MAC_PCU_TXOP_4_7__VALUE_4__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXOP_4_7__VALUE_4__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_TXOP_4_7__VALUE_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXOP_4_7__VALUE_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field VALUE_5 */ +#define MAC_PCU_TXOP_4_7__VALUE_5__SHIFT 8 +#define MAC_PCU_TXOP_4_7__VALUE_5__WIDTH 8 +#define MAC_PCU_TXOP_4_7__VALUE_5__MASK 0x0000ff00U +#define MAC_PCU_TXOP_4_7__VALUE_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_TXOP_4_7__VALUE_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_4_7__VALUE_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_4_7__VALUE_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field VALUE_6 */ +#define MAC_PCU_TXOP_4_7__VALUE_6__SHIFT 16 +#define MAC_PCU_TXOP_4_7__VALUE_6__WIDTH 8 +#define MAC_PCU_TXOP_4_7__VALUE_6__MASK 0x00ff0000U +#define MAC_PCU_TXOP_4_7__VALUE_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_TXOP_4_7__VALUE_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_4_7__VALUE_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_4_7__VALUE_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field VALUE_7 */ +#define MAC_PCU_TXOP_4_7__VALUE_7__SHIFT 24 +#define MAC_PCU_TXOP_4_7__VALUE_7__WIDTH 8 +#define MAC_PCU_TXOP_4_7__VALUE_7__MASK 0xff000000U +#define MAC_PCU_TXOP_4_7__VALUE_7__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_TXOP_4_7__VALUE_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_TXOP_4_7__VALUE_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_TXOP_4_7__VALUE_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_TXOP_4_7__TYPE u_int32_t +#define MAC_PCU_TXOP_4_7__READ 0xffffffffU +#define MAC_PCU_TXOP_4_7__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TXOP_4_7_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_4_7 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_4_7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_8_11 */ +#ifndef __MAC_PCU_TXOP_8_11_MACRO__ +#define __MAC_PCU_TXOP_8_11_MACRO__ + +/* macros for field VALUE_8 */ +#define MAC_PCU_TXOP_8_11__VALUE_8__SHIFT 0 +#define MAC_PCU_TXOP_8_11__VALUE_8__WIDTH 8 +#define MAC_PCU_TXOP_8_11__VALUE_8__MASK 0x000000ffU +#define MAC_PCU_TXOP_8_11__VALUE_8__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXOP_8_11__VALUE_8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_TXOP_8_11__VALUE_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXOP_8_11__VALUE_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field VALUE_9 */ +#define MAC_PCU_TXOP_8_11__VALUE_9__SHIFT 8 +#define MAC_PCU_TXOP_8_11__VALUE_9__WIDTH 8 +#define MAC_PCU_TXOP_8_11__VALUE_9__MASK 0x0000ff00U +#define MAC_PCU_TXOP_8_11__VALUE_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_TXOP_8_11__VALUE_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_8_11__VALUE_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_8_11__VALUE_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field VALUE_10 */ +#define MAC_PCU_TXOP_8_11__VALUE_10__SHIFT 16 +#define MAC_PCU_TXOP_8_11__VALUE_10__WIDTH 8 +#define MAC_PCU_TXOP_8_11__VALUE_10__MASK 0x00ff0000U +#define MAC_PCU_TXOP_8_11__VALUE_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_TXOP_8_11__VALUE_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_8_11__VALUE_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_8_11__VALUE_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field VALUE_11 */ +#define MAC_PCU_TXOP_8_11__VALUE_11__SHIFT 24 +#define MAC_PCU_TXOP_8_11__VALUE_11__WIDTH 8 +#define MAC_PCU_TXOP_8_11__VALUE_11__MASK 0xff000000U +#define MAC_PCU_TXOP_8_11__VALUE_11__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_TXOP_8_11__VALUE_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_TXOP_8_11__VALUE_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_TXOP_8_11__VALUE_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_TXOP_8_11__TYPE u_int32_t +#define MAC_PCU_TXOP_8_11__READ 0xffffffffU +#define MAC_PCU_TXOP_8_11__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TXOP_8_11_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_8_11 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_8_11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_12_15 */ +#ifndef __MAC_PCU_TXOP_12_15_MACRO__ +#define __MAC_PCU_TXOP_12_15_MACRO__ + +/* macros for field VALUE_12 */ +#define MAC_PCU_TXOP_12_15__VALUE_12__SHIFT 0 +#define MAC_PCU_TXOP_12_15__VALUE_12__WIDTH 8 +#define MAC_PCU_TXOP_12_15__VALUE_12__MASK 0x000000ffU +#define MAC_PCU_TXOP_12_15__VALUE_12__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_TXOP_12_15__VALUE_12__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_TXOP_12_15__VALUE_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_TXOP_12_15__VALUE_12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field VALUE_13 */ +#define MAC_PCU_TXOP_12_15__VALUE_13__SHIFT 8 +#define MAC_PCU_TXOP_12_15__VALUE_13__WIDTH 8 +#define MAC_PCU_TXOP_12_15__VALUE_13__MASK 0x0000ff00U +#define MAC_PCU_TXOP_12_15__VALUE_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_TXOP_12_15__VALUE_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_12_15__VALUE_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_TXOP_12_15__VALUE_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field VALUE_14 */ +#define MAC_PCU_TXOP_12_15__VALUE_14__SHIFT 16 +#define MAC_PCU_TXOP_12_15__VALUE_14__WIDTH 8 +#define MAC_PCU_TXOP_12_15__VALUE_14__MASK 0x00ff0000U +#define MAC_PCU_TXOP_12_15__VALUE_14__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_TXOP_12_15__VALUE_14__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_12_15__VALUE_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_TXOP_12_15__VALUE_14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field VALUE_15 */ +#define MAC_PCU_TXOP_12_15__VALUE_15__SHIFT 24 +#define MAC_PCU_TXOP_12_15__VALUE_15__WIDTH 8 +#define MAC_PCU_TXOP_12_15__VALUE_15__MASK 0xff000000U +#define MAC_PCU_TXOP_12_15__VALUE_15__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_TXOP_12_15__VALUE_15__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_TXOP_12_15__VALUE_15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_TXOP_12_15__VALUE_15__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_TXOP_12_15__TYPE u_int32_t +#define MAC_PCU_TXOP_12_15__READ 0xffffffffU +#define MAC_PCU_TXOP_12_15__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TXOP_12_15_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_12_15 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_12_15__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS */ +#ifndef __MAC_PCU_GENERIC_TIMERS_MACRO__ +#define __MAC_PCU_GENERIC_TIMERS_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_GENERIC_TIMERS__DATA__SHIFT 0 +#define MAC_PCU_GENERIC_TIMERS__DATA__WIDTH 32 +#define MAC_PCU_GENERIC_TIMERS__DATA__MASK 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS__DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_GENERIC_TIMERS__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_GENERIC_TIMERS__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_GENERIC_TIMERS__TYPE u_int32_t +#define MAC_PCU_GENERIC_TIMERS__READ 0xffffffffU +#define MAC_PCU_GENERIC_TIMERS__WRITE 0xffffffffU + +#endif /* __MAC_PCU_GENERIC_TIMERS_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS__NUM 16 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS_MODE */ +#ifndef __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__ +#define __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__ + +/* macros for field ENABLE */ +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__SHIFT 0 +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WIDTH 8 +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MASK 0x000000ffU +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field OVERFLOW_INDEX */ +#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__SHIFT 8 +#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__WIDTH 3 +#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__MASK 0x00000700U +#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) + +/* macros for field THRESH */ +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__SHIFT 12 +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WIDTH 20 +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MASK 0xfffff000U +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0xfffff000U) >> 12) +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0xfffff000U) +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffff000U) | (((u_int32_t)(src) <<\ + 12) & 0xfffff000U) +#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0xfffff000U))) +#define MAC_PCU_GENERIC_TIMERS_MODE__TYPE u_int32_t +#define MAC_PCU_GENERIC_TIMERS_MODE__READ 0xfffff7ffU +#define MAC_PCU_GENERIC_TIMERS_MODE__WRITE 0xfffff7ffU + +#endif /* __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS_MODE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_MODE */ +#ifndef __MAC_PCU_SLP32_MODE_MACRO__ +#define __MAC_PCU_SLP32_MODE_MACRO__ + +/* macros for field HALF_CLK_LATENCY */ +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__SHIFT 0 +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WIDTH 20 +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MASK 0x000fffffU +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__READ(src) \ + (u_int32_t)(src)\ + & 0x000fffffU +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000fffffU) +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffffU) | ((u_int32_t)(src) &\ + 0x000fffffU) +#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000fffffU))) + +/* macros for field ENABLE */ +#define MAC_PCU_SLP32_MODE__ENABLE__SHIFT 20 +#define MAC_PCU_SLP32_MODE__ENABLE__WIDTH 1 +#define MAC_PCU_SLP32_MODE__ENABLE__MASK 0x00100000U +#define MAC_PCU_SLP32_MODE__ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_SLP32_MODE__ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_SLP32_MODE__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_SLP32_MODE__ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_SLP32_MODE__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_SLP32_MODE__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field TSF_WRITE_STATUS */ +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__SHIFT 21 +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__WIDTH 1 +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__MASK 0x00200000U +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field DISABLE_32KHZ */ +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__SHIFT 22 +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WIDTH 1 +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MASK 0x00400000U +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field FORCE_BIAS_BLOCK_ON */ +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__SHIFT 23 +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WIDTH 1 +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MASK 0x00800000U +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field TSF2_WRITE_STATUS */ +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__SHIFT 24 +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__WIDTH 1 +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__MASK 0x01000000U +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define MAC_PCU_SLP32_MODE__TYPE u_int32_t +#define MAC_PCU_SLP32_MODE__READ 0x01ffffffU +#define MAC_PCU_SLP32_MODE__WRITE 0x01ffffffU + +#endif /* __MAC_PCU_SLP32_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_SLP32_MODE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_WAKE */ +#ifndef __MAC_PCU_SLP32_WAKE_MACRO__ +#define __MAC_PCU_SLP32_WAKE_MACRO__ + +/* macros for field XTL_TIME */ +#define MAC_PCU_SLP32_WAKE__XTL_TIME__SHIFT 0 +#define MAC_PCU_SLP32_WAKE__XTL_TIME__WIDTH 16 +#define MAC_PCU_SLP32_WAKE__XTL_TIME__MASK 0x0000ffffU +#define MAC_PCU_SLP32_WAKE__XTL_TIME__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_SLP32_WAKE__XTL_TIME__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_SLP32_WAKE__XTL_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_SLP32_WAKE__XTL_TIME__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_SLP32_WAKE__TYPE u_int32_t +#define MAC_PCU_SLP32_WAKE__READ 0x0000ffffU +#define MAC_PCU_SLP32_WAKE__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_SLP32_WAKE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_SLP32_WAKE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_WAKE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_INC */ +#ifndef __MAC_PCU_SLP32_INC_MACRO__ +#define __MAC_PCU_SLP32_INC_MACRO__ + +/* macros for field TSF_INC */ +#define MAC_PCU_SLP32_INC__TSF_INC__SHIFT 0 +#define MAC_PCU_SLP32_INC__TSF_INC__WIDTH 20 +#define MAC_PCU_SLP32_INC__TSF_INC__MASK 0x000fffffU +#define MAC_PCU_SLP32_INC__TSF_INC__READ(src) (u_int32_t)(src) & 0x000fffffU +#define MAC_PCU_SLP32_INC__TSF_INC__WRITE(src) ((u_int32_t)(src) & 0x000fffffU) +#define MAC_PCU_SLP32_INC__TSF_INC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffffU) | ((u_int32_t)(src) &\ + 0x000fffffU) +#define MAC_PCU_SLP32_INC__TSF_INC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000fffffU))) +#define MAC_PCU_SLP32_INC__TYPE u_int32_t +#define MAC_PCU_SLP32_INC__READ 0x000fffffU +#define MAC_PCU_SLP32_INC__WRITE 0x000fffffU + +#endif /* __MAC_PCU_SLP32_INC_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_SLP32_INC */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_INC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB1 */ +#ifndef __MAC_PCU_SLP_MIB1_MACRO__ +#define __MAC_PCU_SLP_MIB1_MACRO__ + +/* macros for field SLEEP_CNT */ +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__SHIFT 0 +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__WIDTH 32 +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__MASK 0xffffffffU +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_SLP_MIB1__SLEEP_CNT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_SLP_MIB1__TYPE u_int32_t +#define MAC_PCU_SLP_MIB1__READ 0xffffffffU +#define MAC_PCU_SLP_MIB1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_SLP_MIB1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB2 */ +#ifndef __MAC_PCU_SLP_MIB2_MACRO__ +#define __MAC_PCU_SLP_MIB2_MACRO__ + +/* macros for field CYCLE_CNT */ +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__SHIFT 0 +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__WIDTH 32 +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__MASK 0xffffffffU +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_SLP_MIB2__CYCLE_CNT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_SLP_MIB2__TYPE u_int32_t +#define MAC_PCU_SLP_MIB2__READ 0xffffffffU +#define MAC_PCU_SLP_MIB2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_SLP_MIB2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB3 */ +#ifndef __MAC_PCU_SLP_MIB3_MACRO__ +#define __MAC_PCU_SLP_MIB3_MACRO__ + +/* macros for field CLR_CNT */ +#define MAC_PCU_SLP_MIB3__CLR_CNT__SHIFT 0 +#define MAC_PCU_SLP_MIB3__CLR_CNT__WIDTH 1 +#define MAC_PCU_SLP_MIB3__CLR_CNT__MASK 0x00000001U +#define MAC_PCU_SLP_MIB3__CLR_CNT__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_SLP_MIB3__CLR_CNT__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_PCU_SLP_MIB3__CLR_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_SLP_MIB3__CLR_CNT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_SLP_MIB3__CLR_CNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_SLP_MIB3__CLR_CNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PENDING */ +#define MAC_PCU_SLP_MIB3__PENDING__SHIFT 1 +#define MAC_PCU_SLP_MIB3__PENDING__WIDTH 1 +#define MAC_PCU_SLP_MIB3__PENDING__MASK 0x00000002U +#define MAC_PCU_SLP_MIB3__PENDING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_SLP_MIB3__PENDING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_SLP_MIB3__PENDING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define MAC_PCU_SLP_MIB3__TYPE u_int32_t +#define MAC_PCU_SLP_MIB3__READ 0x00000003U +#define MAC_PCU_SLP_MIB3__WRITE 0x00000003U + +#endif /* __MAC_PCU_SLP_MIB3_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB3 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW1 */ +#ifndef __MAC_PCU_WOW1_MACRO__ +#define __MAC_PCU_WOW1_MACRO__ + +/* macros for field PATTERN_ENABLE */ +#define MAC_PCU_WOW1__PATTERN_ENABLE__SHIFT 0 +#define MAC_PCU_WOW1__PATTERN_ENABLE__WIDTH 8 +#define MAC_PCU_WOW1__PATTERN_ENABLE__MASK 0x000000ffU +#define MAC_PCU_WOW1__PATTERN_ENABLE__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_WOW1__PATTERN_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW1__PATTERN_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW1__PATTERN_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_DETECT */ +#define MAC_PCU_WOW1__PATTERN_DETECT__SHIFT 8 +#define MAC_PCU_WOW1__PATTERN_DETECT__WIDTH 8 +#define MAC_PCU_WOW1__PATTERN_DETECT__MASK 0x0000ff00U +#define MAC_PCU_WOW1__PATTERN_DETECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field MAGIC_ENABLE */ +#define MAC_PCU_WOW1__MAGIC_ENABLE__SHIFT 16 +#define MAC_PCU_WOW1__MAGIC_ENABLE__WIDTH 1 +#define MAC_PCU_WOW1__MAGIC_ENABLE__MASK 0x00010000U +#define MAC_PCU_WOW1__MAGIC_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_WOW1__MAGIC_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_WOW1__MAGIC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_WOW1__MAGIC_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_WOW1__MAGIC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_WOW1__MAGIC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field MAGIC_DETECT */ +#define MAC_PCU_WOW1__MAGIC_DETECT__SHIFT 17 +#define MAC_PCU_WOW1__MAGIC_DETECT__WIDTH 1 +#define MAC_PCU_WOW1__MAGIC_DETECT__MASK 0x00020000U +#define MAC_PCU_WOW1__MAGIC_DETECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_WOW1__MAGIC_DETECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_WOW1__MAGIC_DETECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field INTR_ENABLE */ +#define MAC_PCU_WOW1__INTR_ENABLE__SHIFT 18 +#define MAC_PCU_WOW1__INTR_ENABLE__WIDTH 1 +#define MAC_PCU_WOW1__INTR_ENABLE__MASK 0x00040000U +#define MAC_PCU_WOW1__INTR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_WOW1__INTR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_WOW1__INTR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_WOW1__INTR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_WOW1__INTR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_WOW1__INTR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field INTR_DETECT */ +#define MAC_PCU_WOW1__INTR_DETECT__SHIFT 19 +#define MAC_PCU_WOW1__INTR_DETECT__WIDTH 1 +#define MAC_PCU_WOW1__INTR_DETECT__MASK 0x00080000U +#define MAC_PCU_WOW1__INTR_DETECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_WOW1__INTR_DETECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_WOW1__INTR_DETECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field KEEP_ALIVE_FAIL */ +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__SHIFT 20 +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__WIDTH 1 +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__MASK 0x00100000U +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field BEACON_FAIL */ +#define MAC_PCU_WOW1__BEACON_FAIL__SHIFT 21 +#define MAC_PCU_WOW1__BEACON_FAIL__WIDTH 1 +#define MAC_PCU_WOW1__BEACON_FAIL__MASK 0x00200000U +#define MAC_PCU_WOW1__BEACON_FAIL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_WOW1__BEACON_FAIL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_WOW1__BEACON_FAIL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field CW_BITS */ +#define MAC_PCU_WOW1__CW_BITS__SHIFT 28 +#define MAC_PCU_WOW1__CW_BITS__WIDTH 4 +#define MAC_PCU_WOW1__CW_BITS__MASK 0xf0000000U +#define MAC_PCU_WOW1__CW_BITS__READ(src) \ + (((u_int32_t)(src)\ + & 0xf0000000U) >> 28) +#define MAC_PCU_WOW1__CW_BITS__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0xf0000000U) +#define MAC_PCU_WOW1__CW_BITS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((u_int32_t)(src) <<\ + 28) & 0xf0000000U) +#define MAC_PCU_WOW1__CW_BITS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0xf0000000U))) +#define MAC_PCU_WOW1__TYPE u_int32_t +#define MAC_PCU_WOW1__READ 0xf03fffffU +#define MAC_PCU_WOW1__WRITE 0xf03fffffU + +#endif /* __MAC_PCU_WOW1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW2 */ +#ifndef __MAC_PCU_WOW2_MACRO__ +#define __MAC_PCU_WOW2_MACRO__ + +/* macros for field AIFS */ +#define MAC_PCU_WOW2__AIFS__SHIFT 0 +#define MAC_PCU_WOW2__AIFS__WIDTH 8 +#define MAC_PCU_WOW2__AIFS__MASK 0x000000ffU +#define MAC_PCU_WOW2__AIFS__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_WOW2__AIFS__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define MAC_PCU_WOW2__AIFS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW2__AIFS__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field SLOT */ +#define MAC_PCU_WOW2__SLOT__SHIFT 8 +#define MAC_PCU_WOW2__SLOT__WIDTH 8 +#define MAC_PCU_WOW2__SLOT__MASK 0x0000ff00U +#define MAC_PCU_WOW2__SLOT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW2__SLOT__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define MAC_PCU_WOW2__SLOT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_WOW2__SLOT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field TRY_CNT */ +#define MAC_PCU_WOW2__TRY_CNT__SHIFT 16 +#define MAC_PCU_WOW2__TRY_CNT__WIDTH 8 +#define MAC_PCU_WOW2__TRY_CNT__MASK 0x00ff0000U +#define MAC_PCU_WOW2__TRY_CNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_WOW2__TRY_CNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_WOW2__TRY_CNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_WOW2__TRY_CNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MAC_PCU_WOW2__TYPE u_int32_t +#define MAC_PCU_WOW2__READ 0x00ffffffU +#define MAC_PCU_WOW2__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_WOW2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER */ +#ifndef __MAC_PCU_LOGIC_ANALYZER_MACRO__ +#define __MAC_PCU_LOGIC_ANALYZER_MACRO__ + +/* macros for field HOLD */ +#define MAC_PCU_LOGIC_ANALYZER__HOLD__SHIFT 0 +#define MAC_PCU_LOGIC_ANALYZER__HOLD__WIDTH 1 +#define MAC_PCU_LOGIC_ANALYZER__HOLD__MASK 0x00000001U +#define MAC_PCU_LOGIC_ANALYZER__HOLD__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_LOGIC_ANALYZER__HOLD__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_LOGIC_ANALYZER__HOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_LOGIC_ANALYZER__HOLD__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_LOGIC_ANALYZER__HOLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_LOGIC_ANALYZER__HOLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field CLEAR */ +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__SHIFT 1 +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__WIDTH 1 +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__MASK 0x00000002U +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_LOGIC_ANALYZER__CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field STATE */ +#define MAC_PCU_LOGIC_ANALYZER__STATE__SHIFT 2 +#define MAC_PCU_LOGIC_ANALYZER__STATE__WIDTH 1 +#define MAC_PCU_LOGIC_ANALYZER__STATE__MASK 0x00000004U +#define MAC_PCU_LOGIC_ANALYZER__STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_LOGIC_ANALYZER__STATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_LOGIC_ANALYZER__STATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field ENABLE */ +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__SHIFT 3 +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__WIDTH 1 +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__MASK 0x00000008U +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_LOGIC_ANALYZER__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field QCU_SEL */ +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__SHIFT 4 +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WIDTH 4 +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MASK 0x000000f0U +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field INT_ADDR */ +#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__SHIFT 8 +#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__WIDTH 10 +#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__MASK 0x0003ff00U +#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003ff00U) >> 8) + +/* macros for field DIAG_MODE */ +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__SHIFT 18 +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WIDTH 14 +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MASK 0xfffc0000U +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0xfffc0000U) >> 18) +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0xfffc0000U) +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffc0000U) | (((u_int32_t)(src) <<\ + 18) & 0xfffc0000U) +#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0xfffc0000U))) +#define MAC_PCU_LOGIC_ANALYZER__TYPE u_int32_t +#define MAC_PCU_LOGIC_ANALYZER__READ 0xffffffffU +#define MAC_PCU_LOGIC_ANALYZER__WRITE 0xffffffffU + +#endif /* __MAC_PCU_LOGIC_ANALYZER_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER_32L */ +#ifndef __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__ +#define __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__ + +/* macros for field MASK */ +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__SHIFT 0 +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WIDTH 32 +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MASK 0xffffffffU +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_LOGIC_ANALYZER_32L__TYPE u_int32_t +#define MAC_PCU_LOGIC_ANALYZER_32L__READ 0xffffffffU +#define MAC_PCU_LOGIC_ANALYZER_32L__WRITE 0xffffffffU + +#endif /* __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER_32L */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER_32L__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER_16U */ +#ifndef __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__ +#define __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__ + +/* macros for field MASK */ +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__SHIFT 0 +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WIDTH 16 +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MASK 0x0000ffffU +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_LOGIC_ANALYZER_16U__TYPE u_int32_t +#define MAC_PCU_LOGIC_ANALYZER_16U__READ 0x0000ffffU +#define MAC_PCU_LOGIC_ANALYZER_16U__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER_16U */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER_16U__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_BEACON_FAIL */ +#ifndef __MAC_PCU_WOW3_BEACON_FAIL_MACRO__ +#define __MAC_PCU_WOW3_BEACON_FAIL_MACRO__ + +/* macros for field ENABLE */ +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__SHIFT 0 +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WIDTH 1 +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MASK 0x00000001U +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define MAC_PCU_WOW3_BEACON_FAIL__TYPE u_int32_t +#define MAC_PCU_WOW3_BEACON_FAIL__READ 0x00000001U +#define MAC_PCU_WOW3_BEACON_FAIL__WRITE 0x00000001U + +#endif /* __MAC_PCU_WOW3_BEACON_FAIL_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW3_BEACON_FAIL */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_BEACON_FAIL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_BEACON */ +#ifndef __MAC_PCU_WOW3_BEACON_MACRO__ +#define __MAC_PCU_WOW3_BEACON_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_PCU_WOW3_BEACON__TIMEOUT__SHIFT 0 +#define MAC_PCU_WOW3_BEACON__TIMEOUT__WIDTH 32 +#define MAC_PCU_WOW3_BEACON__TIMEOUT__MASK 0xffffffffU +#define MAC_PCU_WOW3_BEACON__TIMEOUT__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_WOW3_BEACON__TIMEOUT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_WOW3_BEACON__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_WOW3_BEACON__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_WOW3_BEACON__TYPE u_int32_t +#define MAC_PCU_WOW3_BEACON__READ 0xffffffffU +#define MAC_PCU_WOW3_BEACON__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW3_BEACON_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW3_BEACON */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_BEACON__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_KEEP_ALIVE */ +#ifndef __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__ +#define __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__ + +/* macros for field TIMEOUT */ +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__SHIFT 0 +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WIDTH 32 +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MASK 0xffffffffU +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_WOW3_KEEP_ALIVE__TYPE u_int32_t +#define MAC_PCU_WOW3_KEEP_ALIVE__READ 0xffffffffU +#define MAC_PCU_WOW3_KEEP_ALIVE__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW3_KEEP_ALIVE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_KEEP_ALIVE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_KA */ +#ifndef __MAC_PCU_WOW_KA_MACRO__ +#define __MAC_PCU_WOW_KA_MACRO__ + +/* macros for field AUTO_DISABLE */ +#define MAC_PCU_WOW_KA__AUTO_DISABLE__SHIFT 0 +#define MAC_PCU_WOW_KA__AUTO_DISABLE__WIDTH 1 +#define MAC_PCU_WOW_KA__AUTO_DISABLE__MASK 0x00000001U +#define MAC_PCU_WOW_KA__AUTO_DISABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_WOW_KA__AUTO_DISABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_WOW_KA__AUTO_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_WOW_KA__AUTO_DISABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_WOW_KA__AUTO_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_WOW_KA__AUTO_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field FAIL_DISABLE */ +#define MAC_PCU_WOW_KA__FAIL_DISABLE__SHIFT 1 +#define MAC_PCU_WOW_KA__FAIL_DISABLE__WIDTH 1 +#define MAC_PCU_WOW_KA__FAIL_DISABLE__MASK 0x00000002U +#define MAC_PCU_WOW_KA__FAIL_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_WOW_KA__FAIL_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_WOW_KA__FAIL_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_WOW_KA__FAIL_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_WOW_KA__FAIL_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_WOW_KA__FAIL_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field BKOFF_CS_ENABLE */ +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__SHIFT 2 +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WIDTH 1 +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MASK 0x00000004U +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define MAC_PCU_WOW_KA__TYPE u_int32_t +#define MAC_PCU_WOW_KA__READ 0x00000007U +#define MAC_PCU_WOW_KA__WRITE 0x00000007U + +#endif /* __MAC_PCU_WOW_KA_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW_KA */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_KA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_1US */ +#ifndef __PCU_1US_MACRO__ +#define __PCU_1US_MACRO__ + +/* macros for field SCALER */ +#define PCU_1US__SCALER__SHIFT 0 +#define PCU_1US__SCALER__WIDTH 7 +#define PCU_1US__SCALER__MASK 0x0000007fU +#define PCU_1US__SCALER__READ(src) (u_int32_t)(src) & 0x0000007fU +#define PCU_1US__SCALER__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) +#define PCU_1US__SCALER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define PCU_1US__SCALER__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU))) +#define PCU_1US__TYPE u_int32_t +#define PCU_1US__READ 0x0000007fU +#define PCU_1US__WRITE 0x0000007fU + +#endif /* __PCU_1US_MACRO__ */ + + +/* macros for mac_pcu_reg_map.PCU_1US */ +#define INST_MAC_PCU_REG_MAP__PCU_1US__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_KA */ +#ifndef __PCU_KA_MACRO__ +#define __PCU_KA_MACRO__ + +/* macros for field DEL */ +#define PCU_KA__DEL__SHIFT 0 +#define PCU_KA__DEL__WIDTH 12 +#define PCU_KA__DEL__MASK 0x00000fffU +#define PCU_KA__DEL__READ(src) (u_int32_t)(src) & 0x00000fffU +#define PCU_KA__DEL__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) +#define PCU_KA__DEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define PCU_KA__DEL__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000fffU))) +#define PCU_KA__TYPE u_int32_t +#define PCU_KA__READ 0x00000fffU +#define PCU_KA__WRITE 0x00000fffU + +#endif /* __PCU_KA_MACRO__ */ + + +/* macros for mac_pcu_reg_map.PCU_KA */ +#define INST_MAC_PCU_REG_MAP__PCU_KA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::WOW_EXACT */ +#ifndef __WOW_EXACT_MACRO__ +#define __WOW_EXACT_MACRO__ + +/* macros for field LENGTH */ +#define WOW_EXACT__LENGTH__SHIFT 0 +#define WOW_EXACT__LENGTH__WIDTH 8 +#define WOW_EXACT__LENGTH__MASK 0x000000ffU +#define WOW_EXACT__LENGTH__READ(src) (u_int32_t)(src) & 0x000000ffU +#define WOW_EXACT__LENGTH__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define WOW_EXACT__LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define WOW_EXACT__LENGTH__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET */ +#define WOW_EXACT__OFFSET__SHIFT 8 +#define WOW_EXACT__OFFSET__WIDTH 8 +#define WOW_EXACT__OFFSET__MASK 0x0000ff00U +#define WOW_EXACT__OFFSET__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define WOW_EXACT__OFFSET__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define WOW_EXACT__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WOW_EXACT__OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WOW_EXACT__TYPE u_int32_t +#define WOW_EXACT__READ 0x0000ffffU +#define WOW_EXACT__WRITE 0x0000ffffU + +#endif /* __WOW_EXACT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.WOW_EXACT */ +#define INST_MAC_PCU_REG_MAP__WOW_EXACT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_WOW4 */ +#ifndef __PCU_WOW4_MACRO__ +#define __PCU_WOW4_MACRO__ + +/* macros for field OFFSET0 */ +#define PCU_WOW4__OFFSET0__SHIFT 0 +#define PCU_WOW4__OFFSET0__WIDTH 8 +#define PCU_WOW4__OFFSET0__MASK 0x000000ffU +#define PCU_WOW4__OFFSET0__READ(src) (u_int32_t)(src) & 0x000000ffU +#define PCU_WOW4__OFFSET0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define PCU_WOW4__OFFSET0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define PCU_WOW4__OFFSET0__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET1 */ +#define PCU_WOW4__OFFSET1__SHIFT 8 +#define PCU_WOW4__OFFSET1__WIDTH 8 +#define PCU_WOW4__OFFSET1__MASK 0x0000ff00U +#define PCU_WOW4__OFFSET1__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define PCU_WOW4__OFFSET1__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define PCU_WOW4__OFFSET1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PCU_WOW4__OFFSET1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field OFFSET2 */ +#define PCU_WOW4__OFFSET2__SHIFT 16 +#define PCU_WOW4__OFFSET2__WIDTH 8 +#define PCU_WOW4__OFFSET2__MASK 0x00ff0000U +#define PCU_WOW4__OFFSET2__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) +#define PCU_WOW4__OFFSET2__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) +#define PCU_WOW4__OFFSET2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PCU_WOW4__OFFSET2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field OFFSET3 */ +#define PCU_WOW4__OFFSET3__SHIFT 24 +#define PCU_WOW4__OFFSET3__WIDTH 8 +#define PCU_WOW4__OFFSET3__MASK 0xff000000U +#define PCU_WOW4__OFFSET3__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) +#define PCU_WOW4__OFFSET3__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) +#define PCU_WOW4__OFFSET3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define PCU_WOW4__OFFSET3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define PCU_WOW4__TYPE u_int32_t +#define PCU_WOW4__READ 0xffffffffU +#define PCU_WOW4__WRITE 0xffffffffU + +#endif /* __PCU_WOW4_MACRO__ */ + + +/* macros for mac_pcu_reg_map.PCU_WOW4 */ +#define INST_MAC_PCU_REG_MAP__PCU_WOW4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_WOW5 */ +#ifndef __PCU_WOW5_MACRO__ +#define __PCU_WOW5_MACRO__ + +/* macros for field OFFSET4 */ +#define PCU_WOW5__OFFSET4__SHIFT 0 +#define PCU_WOW5__OFFSET4__WIDTH 8 +#define PCU_WOW5__OFFSET4__MASK 0x000000ffU +#define PCU_WOW5__OFFSET4__READ(src) (u_int32_t)(src) & 0x000000ffU +#define PCU_WOW5__OFFSET4__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define PCU_WOW5__OFFSET4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define PCU_WOW5__OFFSET4__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET5 */ +#define PCU_WOW5__OFFSET5__SHIFT 8 +#define PCU_WOW5__OFFSET5__WIDTH 8 +#define PCU_WOW5__OFFSET5__MASK 0x0000ff00U +#define PCU_WOW5__OFFSET5__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define PCU_WOW5__OFFSET5__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define PCU_WOW5__OFFSET5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PCU_WOW5__OFFSET5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field OFFSET6 */ +#define PCU_WOW5__OFFSET6__SHIFT 16 +#define PCU_WOW5__OFFSET6__WIDTH 8 +#define PCU_WOW5__OFFSET6__MASK 0x00ff0000U +#define PCU_WOW5__OFFSET6__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) +#define PCU_WOW5__OFFSET6__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) +#define PCU_WOW5__OFFSET6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PCU_WOW5__OFFSET6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field OFFSET7 */ +#define PCU_WOW5__OFFSET7__SHIFT 24 +#define PCU_WOW5__OFFSET7__WIDTH 8 +#define PCU_WOW5__OFFSET7__MASK 0xff000000U +#define PCU_WOW5__OFFSET7__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) +#define PCU_WOW5__OFFSET7__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) +#define PCU_WOW5__OFFSET7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define PCU_WOW5__OFFSET7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define PCU_WOW5__TYPE u_int32_t +#define PCU_WOW5__READ 0xffffffffU +#define PCU_WOW5__WRITE 0xffffffffU + +#endif /* __PCU_WOW5_MACRO__ */ + + +/* macros for mac_pcu_reg_map.PCU_WOW5 */ +#define INST_MAC_PCU_REG_MAP__PCU_WOW5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_MASK_CONT */ +#ifndef __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__ +#define __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__ + +/* macros for field MASK1 */ +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__SHIFT 0 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WIDTH 8 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MASK 0x000000ffU +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field MASK2 */ +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__SHIFT 8 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WIDTH 8 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MASK 0x0000ff00U +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field MASK3 */ +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__SHIFT 16 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WIDTH 8 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MASK 0x00ff0000U +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__TYPE u_int32_t +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__READ 0x00ffffffU +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__WRITE 0x00ffffffU + +#endif /* __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_MASK_CONT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_MASK_CONT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AZIMUTH_MODE */ +#ifndef __MAC_PCU_AZIMUTH_MODE_MACRO__ +#define __MAC_PCU_AZIMUTH_MODE_MACRO__ + +/* macros for field DISABLE_TSF_UPDATE */ +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__SHIFT 0 +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MASK 0x00000001U +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field KEY_SEARCH_AD1 */ +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__SHIFT 1 +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MASK 0x00000002U +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field TX_TSF_STATUS_SEL */ +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__SHIFT 2 +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MASK 0x00000004U +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field RX_TSF_STATUS_SEL */ +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__SHIFT 3 +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MASK 0x00000008U +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field CLK_EN */ +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__SHIFT 4 +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__MASK 0x00000010U +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_AZIMUTH_MODE__CLK_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field TX_DESC_EN */ +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__SHIFT 5 +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MASK 0x00000020U +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field ACK_CTS_MATCH_TX_AD2 */ +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__SHIFT 6 +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MASK 0x00000040U +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field BA_USES_AD1 */ +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__SHIFT 7 +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MASK 0x00000080U +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field WMAC_CLK_SEL */ +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__SHIFT 8 +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MASK 0x00000100U +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field FILTER_PASS_HOLD */ +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__SHIFT 9 +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MASK 0x00000200U +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field PROXY_STA_FIX1_ENABLE */ +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__SHIFT 10 +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__MASK 0x00000400U +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field PROXY_STA_FIX2_ENABLE */ +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__SHIFT 11 +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__MASK 0x00000800U +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field PROXY_STA_FIX3_ENABLE */ +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__SHIFT 12 +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__WIDTH 1 +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__MASK 0x00001000U +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) +#define MAC_PCU_AZIMUTH_MODE__TYPE u_int32_t +#define MAC_PCU_AZIMUTH_MODE__READ 0x00001fffU +#define MAC_PCU_AZIMUTH_MODE__WRITE 0x00001fffU + +#endif /* __MAC_PCU_AZIMUTH_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_AZIMUTH_MODE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_AZIMUTH_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AZIMUTH_TIME_STAMP */ +#ifndef __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__ +#define __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__SHIFT 0 +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WIDTH 32 +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MASK 0xffffffffU +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_AZIMUTH_TIME_STAMP__TYPE u_int32_t +#define MAC_PCU_AZIMUTH_TIME_STAMP__READ 0xffffffffU +#define MAC_PCU_AZIMUTH_TIME_STAMP__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_AZIMUTH_TIME_STAMP */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_AZIMUTH_TIME_STAMP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_20_40_MODE */ +#ifndef __MAC_PCU_20_40_MODE_MACRO__ +#define __MAC_PCU_20_40_MODE_MACRO__ + +/* macros for field JOINED_RX_CLEAR */ +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__SHIFT 0 +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WIDTH 1 +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MASK 0x00000001U +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field EXT_PIFS_ENABLE */ +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__SHIFT 1 +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WIDTH 1 +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MASK 0x00000002U +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field TX_HT20_ON_EXT_BUSY */ +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__SHIFT 2 +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WIDTH 1 +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MASK 0x00000004U +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field SWAMPED_FORCES_RX_CLEAR_CTL_IDLE */ +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__SHIFT 3 +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WIDTH 1 +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MASK 0x00000008U +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field PIFS_CYCLES */ +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__SHIFT 4 +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__WIDTH 12 +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__MASK 0x0000fff0U +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fff0U) >> 4) +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x0000fff0U) +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fff0U) | (((u_int32_t)(src) <<\ + 4) & 0x0000fff0U) +#define MAC_PCU_20_40_MODE__PIFS_CYCLES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x0000fff0U))) +#define MAC_PCU_20_40_MODE__TYPE u_int32_t +#define MAC_PCU_20_40_MODE__READ 0x0000ffffU +#define MAC_PCU_20_40_MODE__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_20_40_MODE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_20_40_MODE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_20_40_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_H_XFER_TIMEOUT */ +#ifndef __MAC_PCU_H_XFER_TIMEOUT_MACRO__ +#define __MAC_PCU_H_XFER_TIMEOUT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__SHIFT 0 +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__WIDTH 5 +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__MASK 0x0000001fU +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000001fU +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define MAC_PCU_H_XFER_TIMEOUT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field DISABLE */ +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__SHIFT 5 +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WIDTH 1 +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MASK 0x00000020U +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field EXTXBF_IMMEDIATE_RESP */ +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__SHIFT 6 +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WIDTH 1 +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MASK 0x00000040U +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field DELAY_EXTXBF_ONLY_UPLOAD_H */ +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__SHIFT 7 +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WIDTH 1 +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MASK 0x00000080U +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field EXTXBF_NOACK_NORPT */ +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__SHIFT 8 +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WIDTH 1 +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MASK 0x00000100U +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) +#define MAC_PCU_H_XFER_TIMEOUT__TYPE u_int32_t +#define MAC_PCU_H_XFER_TIMEOUT__READ 0x000001ffU +#define MAC_PCU_H_XFER_TIMEOUT__WRITE 0x000001ffU + +#endif /* __MAC_PCU_H_XFER_TIMEOUT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_H_XFER_TIMEOUT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_H_XFER_TIMEOUT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_CLEAR_DIFF_CNT */ +#ifndef __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__ +#define __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__SHIFT 0 +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WIDTH 32 +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MASK 0xffffffffU +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_RX_CLEAR_DIFF_CNT__TYPE u_int32_t +#define MAC_PCU_RX_CLEAR_DIFF_CNT__READ 0xffffffffU +#define MAC_PCU_RX_CLEAR_DIFF_CNT__WRITE 0xffffffffU + +#endif /* __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_RX_CLEAR_DIFF_CNT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_CLEAR_DIFF_CNT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_SELF_GEN_ANTENNA_MASK */ +#ifndef __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__ +#define __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__SHIFT 0 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WIDTH 3 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MASK 0x00000007U +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field ONE_RESP_EN */ +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__SHIFT 3 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__WIDTH 1 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__MASK 0x00000008U +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field FORCE_CHAIN_0 */ +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__SHIFT 4 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__WIDTH 1 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__MASK 0x00000010U +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__TYPE u_int32_t +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__READ 0x0000001fU +#define MAC_PCU_SELF_GEN_ANTENNA_MASK__WRITE 0x0000001fU + +#endif /* __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_SELF_GEN_ANTENNA_MASK */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_SELF_GEN_ANTENNA_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BA_BAR_CONTROL */ +#ifndef __MAC_PCU_BA_BAR_CONTROL_MACRO__ +#define __MAC_PCU_BA_BAR_CONTROL_MACRO__ + +/* macros for field COMPRESSED_OFFSET */ +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__SHIFT 0 +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WIDTH 4 +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MASK 0x0000000fU +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field ACK_POLICY_OFFSET */ +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__SHIFT 4 +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WIDTH 4 +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MASK 0x000000f0U +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field COMPRESSED_VALUE */ +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__SHIFT 8 +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WIDTH 1 +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MASK 0x00000100U +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field ACK_POLICY_VALUE */ +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__SHIFT 9 +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WIDTH 1 +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MASK 0x00000200U +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field FORCE_NO_MATCH */ +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__SHIFT 10 +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WIDTH 1 +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MASK 0x00000400U +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field TX_BA_CLEAR_BA_VALID */ +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__SHIFT 11 +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WIDTH 1 +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MASK 0x00000800U +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field UPDATE_BA_BITMAP_QOS_NULL */ +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__SHIFT 12 +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WIDTH 1 +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MASK 0x00001000U +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) +#define MAC_PCU_BA_BAR_CONTROL__TYPE u_int32_t +#define MAC_PCU_BA_BAR_CONTROL__READ 0x00001fffU +#define MAC_PCU_BA_BAR_CONTROL__WRITE 0x00001fffU + +#endif /* __MAC_PCU_BA_BAR_CONTROL_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BA_BAR_CONTROL */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BA_BAR_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LEGACY_PLCP_SPOOF */ +#ifndef __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__ +#define __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__ + +/* macros for field EIFS_MINUS_DIFS */ +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__SHIFT 0 +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WIDTH 8 +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MASK 0x000000ffU +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field MIN_LENGTH */ +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__SHIFT 8 +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WIDTH 5 +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MASK 0x00001f00U +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) +#define MAC_PCU_LEGACY_PLCP_SPOOF__TYPE u_int32_t +#define MAC_PCU_LEGACY_PLCP_SPOOF__READ 0x00001fffU +#define MAC_PCU_LEGACY_PLCP_SPOOF__WRITE 0x00001fffU + +#endif /* __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_LEGACY_PLCP_SPOOF */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_LEGACY_PLCP_SPOOF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_MASK_CONT */ +#ifndef __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__ +#define __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__ + +/* macros for field MASK_VALUE */ +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WIDTH 8 +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MASK 0x000000ffU +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field EIFS_VALUE */ +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__SHIFT 16 +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WIDTH 8 +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MASK 0x00ff0000U +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field AIFS_VALUE */ +#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__SHIFT 24 +#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__WIDTH 8 +#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__MASK 0xff000000U +#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_PHY_ERROR_MASK_CONT__TYPE u_int32_t +#define MAC_PCU_PHY_ERROR_MASK_CONT__READ 0xffff00ffU +#define MAC_PCU_PHY_ERROR_MASK_CONT__WRITE 0xffff00ffU + +#endif /* __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_MASK_CONT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_MASK_CONT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_TIMER */ +#ifndef __MAC_PCU_TX_TIMER_MACRO__ +#define __MAC_PCU_TX_TIMER_MACRO__ + +/* macros for field TX_TIMER */ +#define MAC_PCU_TX_TIMER__TX_TIMER__SHIFT 0 +#define MAC_PCU_TX_TIMER__TX_TIMER__WIDTH 15 +#define MAC_PCU_TX_TIMER__TX_TIMER__MASK 0x00007fffU +#define MAC_PCU_TX_TIMER__TX_TIMER__READ(src) (u_int32_t)(src) & 0x00007fffU +#define MAC_PCU_TX_TIMER__TX_TIMER__WRITE(src) ((u_int32_t)(src) & 0x00007fffU) +#define MAC_PCU_TX_TIMER__TX_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007fffU) | ((u_int32_t)(src) &\ + 0x00007fffU) +#define MAC_PCU_TX_TIMER__TX_TIMER__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00007fffU))) + +/* macros for field TX_TIMER_ENABLE */ +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__SHIFT 15 +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WIDTH 1 +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MASK 0x00008000U +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field RIFS_TIMER */ +#define MAC_PCU_TX_TIMER__RIFS_TIMER__SHIFT 16 +#define MAC_PCU_TX_TIMER__RIFS_TIMER__WIDTH 4 +#define MAC_PCU_TX_TIMER__RIFS_TIMER__MASK 0x000f0000U +#define MAC_PCU_TX_TIMER__RIFS_TIMER__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define MAC_PCU_TX_TIMER__RIFS_TIMER__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define MAC_PCU_TX_TIMER__RIFS_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define MAC_PCU_TX_TIMER__RIFS_TIMER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field QUIET_TIMER */ +#define MAC_PCU_TX_TIMER__QUIET_TIMER__SHIFT 20 +#define MAC_PCU_TX_TIMER__QUIET_TIMER__WIDTH 5 +#define MAC_PCU_TX_TIMER__QUIET_TIMER__MASK 0x01f00000U +#define MAC_PCU_TX_TIMER__QUIET_TIMER__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define MAC_PCU_TX_TIMER__QUIET_TIMER__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define MAC_PCU_TX_TIMER__QUIET_TIMER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define MAC_PCU_TX_TIMER__QUIET_TIMER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field QUIET_TIMER_ENABLE */ +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__SHIFT 25 +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WIDTH 1 +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MASK 0x02000000U +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) +#define MAC_PCU_TX_TIMER__TYPE u_int32_t +#define MAC_PCU_TX_TIMER__READ 0x03ffffffU +#define MAC_PCU_TX_TIMER__WRITE 0x03ffffffU + +#endif /* __MAC_PCU_TX_TIMER_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TX_TIMER */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_TIMER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXBUF_CTRL */ +#ifndef __MAC_PCU_TXBUF_CTRL_MACRO__ +#define __MAC_PCU_TXBUF_CTRL_MACRO__ + +/* macros for field USABLE_ENTRIES */ +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__SHIFT 0 +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WIDTH 12 +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MASK 0x00000fffU +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field TX_FIFO_WRAP_ENABLE */ +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__SHIFT 16 +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WIDTH 1 +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MASK 0x00010000U +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) +#define MAC_PCU_TXBUF_CTRL__TYPE u_int32_t +#define MAC_PCU_TXBUF_CTRL__READ 0x00010fffU +#define MAC_PCU_TXBUF_CTRL__WRITE 0x00010fffU + +#endif /* __MAC_PCU_TXBUF_CTRL_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TXBUF_CTRL */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXBUF_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE2 */ +#ifndef __MAC_PCU_MISC_MODE2_MACRO__ +#define __MAC_PCU_MISC_MODE2_MACRO__ + +/* macros for field BUG_21532_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__SHIFT 0 +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MASK 0x00000001U +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field MGMT_CRYPTO_ENABLE */ +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__SHIFT 1 +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MASK 0x00000002U +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field NO_CRYPTO_FOR_NON_DATA_PKT */ +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__SHIFT 2 +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WIDTH 1 +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MASK 0x00000004U +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field BUG_58603_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__SHIFT 3 +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MASK 0x00000008U +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BUG_58057_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__SHIFT 4 +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MASK 0x00000010U +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field RESERVED_0 */ +#define MAC_PCU_MISC_MODE2__RESERVED_0__SHIFT 5 +#define MAC_PCU_MISC_MODE2__RESERVED_0__WIDTH 1 +#define MAC_PCU_MISC_MODE2__RESERVED_0__MASK 0x00000020U +#define MAC_PCU_MISC_MODE2__RESERVED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_MISC_MODE2__RESERVED_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE2__RESERVED_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE2__RESERVED_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_MISC_MODE2__RESERVED_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_MISC_MODE2__RESERVED_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field ADHOC_MCAST_KEYID_ENABLE */ +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__SHIFT 6 +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MASK 0x00000040U +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field CFP_IGNORE */ +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__SHIFT 7 +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__MASK 0x00000080U +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_MISC_MODE2__CFP_IGNORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field MGMT_QOS */ +#define MAC_PCU_MISC_MODE2__MGMT_QOS__SHIFT 8 +#define MAC_PCU_MISC_MODE2__MGMT_QOS__WIDTH 8 +#define MAC_PCU_MISC_MODE2__MGMT_QOS__MASK 0x0000ff00U +#define MAC_PCU_MISC_MODE2__MGMT_QOS__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_MISC_MODE2__MGMT_QOS__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_MISC_MODE2__MGMT_QOS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_MISC_MODE2__MGMT_QOS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field ENABLE_LOAD_NAV_BEACON_DURATION */ +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__SHIFT 16 +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WIDTH 1 +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MASK 0x00010000U +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field AGG_WEP */ +#define MAC_PCU_MISC_MODE2__AGG_WEP__SHIFT 17 +#define MAC_PCU_MISC_MODE2__AGG_WEP__WIDTH 1 +#define MAC_PCU_MISC_MODE2__AGG_WEP__MASK 0x00020000U +#define MAC_PCU_MISC_MODE2__AGG_WEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_MISC_MODE2__AGG_WEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_MISC_MODE2__AGG_WEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_MISC_MODE2__AGG_WEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_MISC_MODE2__AGG_WEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_MISC_MODE2__AGG_WEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field BC_MC_WAPI_MODE */ +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__SHIFT 18 +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MASK 0x00040000U +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field DUR_ACCOUNT_BY_BA */ +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__SHIFT 19 +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WIDTH 1 +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MASK 0x00080000U +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field BUG_28676 */ +#define MAC_PCU_MISC_MODE2__BUG_28676__SHIFT 20 +#define MAC_PCU_MISC_MODE2__BUG_28676__WIDTH 1 +#define MAC_PCU_MISC_MODE2__BUG_28676__MASK 0x00100000U +#define MAC_PCU_MISC_MODE2__BUG_28676__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_MISC_MODE2__BUG_28676__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_MISC_MODE2__BUG_28676__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_MISC_MODE2__BUG_28676__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_MISC_MODE2__BUG_28676__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_MISC_MODE2__BUG_28676__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field CLEAR_MORE_FRAG */ +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__SHIFT 21 +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WIDTH 1 +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MASK 0x00200000U +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field IGNORE_TXOP_1ST_PKT */ +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__SHIFT 22 +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WIDTH 1 +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MASK 0x00400000U +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field MPDU_DENSITY_STS_FIX */ +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__SHIFT 23 +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WIDTH 1 +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MASK 0x00800000U +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field MPDU_DENSITY_WAIT_WEP */ +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__SHIFT 24 +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WIDTH 1 +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MASK 0x01000000U +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field RCV_TIMESTAMP_FIX */ +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__SHIFT 25 +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WIDTH 1 +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MASK 0x02000000U +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field PM_FIELD_FOR_NON_CTRL */ +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__SHIFT 26 +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WIDTH 1 +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MASK 0x04000000U +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field DECOUPLE_DECRYPTION */ +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__SHIFT 27 +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WIDTH 1 +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MASK 0x08000000U +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field H_TO_SW_DEBUG_MODE */ +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__SHIFT 28 +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WIDTH 1 +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MASK 0x10000000U +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field TXBF_ACT_RPT_DONE_PASS */ +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__SHIFT 29 +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WIDTH 1 +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MASK 0x20000000U +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PCU_LOOP_TXBF */ +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__SHIFT 30 +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WIDTH 1 +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MASK 0x40000000U +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field CLEAR_WEP_TXBUSY_ON_TXURN */ +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__SHIFT 31 +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WIDTH 1 +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MASK 0x80000000U +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define MAC_PCU_MISC_MODE2__TYPE u_int32_t +#define MAC_PCU_MISC_MODE2__READ 0xffffffffU +#define MAC_PCU_MISC_MODE2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_MISC_MODE2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_ALT_AES_MUTE_MASK */ +#ifndef __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__ +#define __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__ + +/* macros for field QOS */ +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__SHIFT 16 +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WIDTH 16 +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MASK 0xffff0000U +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define MAC_PCU_ALT_AES_MUTE_MASK__TYPE u_int32_t +#define MAC_PCU_ALT_AES_MUTE_MASK__READ 0xffff0000U +#define MAC_PCU_ALT_AES_MUTE_MASK__WRITE 0xffff0000U + +#endif /* __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_ALT_AES_MUTE_MASK */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_ALT_AES_MUTE_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW6 */ +#ifndef __MAC_PCU_WOW6_MACRO__ +#define __MAC_PCU_WOW6_MACRO__ + +/* macros for field RXBUF_START_ADDR */ +#define MAC_PCU_WOW6__RXBUF_START_ADDR__SHIFT 0 +#define MAC_PCU_WOW6__RXBUF_START_ADDR__WIDTH 16 +#define MAC_PCU_WOW6__RXBUF_START_ADDR__MASK 0x0000ffffU +#define MAC_PCU_WOW6__RXBUF_START_ADDR__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define MAC_PCU_WOW6__TYPE u_int32_t +#define MAC_PCU_WOW6__READ 0x0000ffffU + +#endif /* __MAC_PCU_WOW6_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW6 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG1 */ +#ifndef __ASYNC_FIFO_REG1_MACRO__ +#define __ASYNC_FIFO_REG1_MACRO__ + +/* macros for field DBG */ +#define ASYNC_FIFO_REG1__DBG__SHIFT 0 +#define ASYNC_FIFO_REG1__DBG__WIDTH 30 +#define ASYNC_FIFO_REG1__DBG__MASK 0x3fffffffU +#define ASYNC_FIFO_REG1__DBG__READ(src) (u_int32_t)(src) & 0x3fffffffU +#define ASYNC_FIFO_REG1__DBG__WRITE(src) ((u_int32_t)(src) & 0x3fffffffU) +#define ASYNC_FIFO_REG1__DBG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fffffffU) | ((u_int32_t)(src) &\ + 0x3fffffffU) +#define ASYNC_FIFO_REG1__DBG__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x3fffffffU))) +#define ASYNC_FIFO_REG1__TYPE u_int32_t +#define ASYNC_FIFO_REG1__READ 0x3fffffffU +#define ASYNC_FIFO_REG1__WRITE 0x3fffffffU + +#endif /* __ASYNC_FIFO_REG1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.ASYNC_FIFO_REG1 */ +#define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG2 */ +#ifndef __ASYNC_FIFO_REG2_MACRO__ +#define __ASYNC_FIFO_REG2_MACRO__ + +/* macros for field DBG */ +#define ASYNC_FIFO_REG2__DBG__SHIFT 0 +#define ASYNC_FIFO_REG2__DBG__WIDTH 28 +#define ASYNC_FIFO_REG2__DBG__MASK 0x0fffffffU +#define ASYNC_FIFO_REG2__DBG__READ(src) (u_int32_t)(src) & 0x0fffffffU +#define ASYNC_FIFO_REG2__DBG__WRITE(src) ((u_int32_t)(src) & 0x0fffffffU) +#define ASYNC_FIFO_REG2__DBG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffffffU) | ((u_int32_t)(src) &\ + 0x0fffffffU) +#define ASYNC_FIFO_REG2__DBG__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0fffffffU))) +#define ASYNC_FIFO_REG2__TYPE u_int32_t +#define ASYNC_FIFO_REG2__READ 0x0fffffffU +#define ASYNC_FIFO_REG2__WRITE 0x0fffffffU + +#endif /* __ASYNC_FIFO_REG2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.ASYNC_FIFO_REG2 */ +#define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG3 */ +#ifndef __ASYNC_FIFO_REG3_MACRO__ +#define __ASYNC_FIFO_REG3_MACRO__ + +/* macros for field DBG */ +#define ASYNC_FIFO_REG3__DBG__SHIFT 0 +#define ASYNC_FIFO_REG3__DBG__WIDTH 10 +#define ASYNC_FIFO_REG3__DBG__MASK 0x000003ffU +#define ASYNC_FIFO_REG3__DBG__READ(src) (u_int32_t)(src) & 0x000003ffU +#define ASYNC_FIFO_REG3__DBG__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define ASYNC_FIFO_REG3__DBG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define ASYNC_FIFO_REG3__DBG__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field DATAPATH_SEL */ +#define ASYNC_FIFO_REG3__DATAPATH_SEL__SHIFT 10 +#define ASYNC_FIFO_REG3__DATAPATH_SEL__WIDTH 1 +#define ASYNC_FIFO_REG3__DATAPATH_SEL__MASK 0x00000400U +#define ASYNC_FIFO_REG3__DATAPATH_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define ASYNC_FIFO_REG3__DATAPATH_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define ASYNC_FIFO_REG3__DATAPATH_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define ASYNC_FIFO_REG3__DATAPATH_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define ASYNC_FIFO_REG3__DATAPATH_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define ASYNC_FIFO_REG3__DATAPATH_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field SFT_RST_N */ +#define ASYNC_FIFO_REG3__SFT_RST_N__SHIFT 31 +#define ASYNC_FIFO_REG3__SFT_RST_N__WIDTH 1 +#define ASYNC_FIFO_REG3__SFT_RST_N__MASK 0x80000000U +#define ASYNC_FIFO_REG3__SFT_RST_N__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define ASYNC_FIFO_REG3__SFT_RST_N__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define ASYNC_FIFO_REG3__SFT_RST_N__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define ASYNC_FIFO_REG3__SFT_RST_N__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define ASYNC_FIFO_REG3__SFT_RST_N__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define ASYNC_FIFO_REG3__SFT_RST_N__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define ASYNC_FIFO_REG3__TYPE u_int32_t +#define ASYNC_FIFO_REG3__READ 0x800007ffU +#define ASYNC_FIFO_REG3__WRITE 0x800007ffU + +#endif /* __ASYNC_FIFO_REG3_MACRO__ */ + + +/* macros for mac_pcu_reg_map.ASYNC_FIFO_REG3 */ +#define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW5 */ +#ifndef __MAC_PCU_WOW5_MACRO__ +#define __MAC_PCU_WOW5_MACRO__ + +/* macros for field RX_ABORT_ENABLE */ +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__SHIFT 0 +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__WIDTH 16 +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__MASK 0x0000ffffU +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_WOW5__RX_ABORT_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define MAC_PCU_WOW5__TYPE u_int32_t +#define MAC_PCU_WOW5__READ 0x0000ffffU +#define MAC_PCU_WOW5__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_WOW5_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW5 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH1 */ +#ifndef __MAC_PCU_WOW_LENGTH1_MACRO__ +#define __MAC_PCU_WOW_LENGTH1_MACRO__ + +/* macros for field PATTERN_3 */ +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__SHIFT 0 +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__WIDTH 8 +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__MASK 0x000000ffU +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW_LENGTH1__PATTERN_3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_2 */ +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__SHIFT 8 +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__WIDTH 8 +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__MASK 0x0000ff00U +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field PATTERN_1 */ +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__SHIFT 16 +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__WIDTH 8 +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__MASK 0x00ff0000U +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field PATTERN_0 */ +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__SHIFT 24 +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__WIDTH 8 +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__MASK 0xff000000U +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH1__PATTERN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_WOW_LENGTH1__TYPE u_int32_t +#define MAC_PCU_WOW_LENGTH1__READ 0xffffffffU +#define MAC_PCU_WOW_LENGTH1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW_LENGTH1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH2 */ +#ifndef __MAC_PCU_WOW_LENGTH2_MACRO__ +#define __MAC_PCU_WOW_LENGTH2_MACRO__ + +/* macros for field PATTERN_7 */ +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__SHIFT 0 +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__WIDTH 8 +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__MASK 0x000000ffU +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW_LENGTH2__PATTERN_7__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_6 */ +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__SHIFT 8 +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__WIDTH 8 +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__MASK 0x0000ff00U +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field PATTERN_5 */ +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__SHIFT 16 +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__WIDTH 8 +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__MASK 0x00ff0000U +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field PATTERN_4 */ +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__SHIFT 24 +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__WIDTH 8 +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__MASK 0xff000000U +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH2__PATTERN_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_WOW_LENGTH2__TYPE u_int32_t +#define MAC_PCU_WOW_LENGTH2__READ 0xffffffffU +#define MAC_PCU_WOW_LENGTH2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW_LENGTH2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::WOW_PATTERN_MATCH_LESS_THAN_256_BYTES */ +#ifndef __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__ +#define __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__ + +/* macros for field EN */ +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__SHIFT 0 +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WIDTH 16 +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MASK 0x0000ffffU +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__TYPE u_int32_t +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__READ 0x0000ffffU +#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__WRITE 0x0000ffffU + +#endif /* __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__ */ + + +/* macros for mac_pcu_reg_map.WOW_PATTERN_MATCH_LESS_THAN_256_BYTES */ +#define INST_MAC_PCU_REG_MAP__WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW4 */ +#ifndef __MAC_PCU_WOW4_MACRO__ +#define __MAC_PCU_WOW4_MACRO__ + +/* macros for field PATTERN_ENABLE */ +#define MAC_PCU_WOW4__PATTERN_ENABLE__SHIFT 0 +#define MAC_PCU_WOW4__PATTERN_ENABLE__WIDTH 8 +#define MAC_PCU_WOW4__PATTERN_ENABLE__MASK 0x000000ffU +#define MAC_PCU_WOW4__PATTERN_ENABLE__READ(src) (u_int32_t)(src) & 0x000000ffU +#define MAC_PCU_WOW4__PATTERN_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW4__PATTERN_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW4__PATTERN_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_DETECT */ +#define MAC_PCU_WOW4__PATTERN_DETECT__SHIFT 8 +#define MAC_PCU_WOW4__PATTERN_DETECT__WIDTH 8 +#define MAC_PCU_WOW4__PATTERN_DETECT__MASK 0x0000ff00U +#define MAC_PCU_WOW4__PATTERN_DETECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW4__TYPE u_int32_t +#define MAC_PCU_WOW4__READ 0x0000ffffU +#define MAC_PCU_WOW4__WRITE 0x0000ffffU + +#endif /* __MAC_PCU_WOW4_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW4 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::WOW2_EXACT */ +#ifndef __WOW2_EXACT_MACRO__ +#define __WOW2_EXACT_MACRO__ + +/* macros for field LENGTH */ +#define WOW2_EXACT__LENGTH__SHIFT 0 +#define WOW2_EXACT__LENGTH__WIDTH 8 +#define WOW2_EXACT__LENGTH__MASK 0x000000ffU +#define WOW2_EXACT__LENGTH__READ(src) (u_int32_t)(src) & 0x000000ffU +#define WOW2_EXACT__LENGTH__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define WOW2_EXACT__LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define WOW2_EXACT__LENGTH__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET */ +#define WOW2_EXACT__OFFSET__SHIFT 8 +#define WOW2_EXACT__OFFSET__WIDTH 8 +#define WOW2_EXACT__OFFSET__MASK 0x0000ff00U +#define WOW2_EXACT__OFFSET__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define WOW2_EXACT__OFFSET__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define WOW2_EXACT__OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define WOW2_EXACT__OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define WOW2_EXACT__TYPE u_int32_t +#define WOW2_EXACT__READ 0x0000ffffU +#define WOW2_EXACT__WRITE 0x0000ffffU + +#endif /* __WOW2_EXACT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.WOW2_EXACT */ +#define INST_MAC_PCU_REG_MAP__WOW2_EXACT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_WOW6 */ +#ifndef __PCU_WOW6_MACRO__ +#define __PCU_WOW6_MACRO__ + +/* macros for field OFFSET8 */ +#define PCU_WOW6__OFFSET8__SHIFT 0 +#define PCU_WOW6__OFFSET8__WIDTH 8 +#define PCU_WOW6__OFFSET8__MASK 0x000000ffU +#define PCU_WOW6__OFFSET8__READ(src) (u_int32_t)(src) & 0x000000ffU +#define PCU_WOW6__OFFSET8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define PCU_WOW6__OFFSET8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define PCU_WOW6__OFFSET8__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET9 */ +#define PCU_WOW6__OFFSET9__SHIFT 8 +#define PCU_WOW6__OFFSET9__WIDTH 8 +#define PCU_WOW6__OFFSET9__MASK 0x0000ff00U +#define PCU_WOW6__OFFSET9__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define PCU_WOW6__OFFSET9__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define PCU_WOW6__OFFSET9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PCU_WOW6__OFFSET9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field OFFSET10 */ +#define PCU_WOW6__OFFSET10__SHIFT 16 +#define PCU_WOW6__OFFSET10__WIDTH 8 +#define PCU_WOW6__OFFSET10__MASK 0x00ff0000U +#define PCU_WOW6__OFFSET10__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) +#define PCU_WOW6__OFFSET10__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) +#define PCU_WOW6__OFFSET10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PCU_WOW6__OFFSET10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field OFFSET11 */ +#define PCU_WOW6__OFFSET11__SHIFT 24 +#define PCU_WOW6__OFFSET11__WIDTH 8 +#define PCU_WOW6__OFFSET11__MASK 0xff000000U +#define PCU_WOW6__OFFSET11__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) +#define PCU_WOW6__OFFSET11__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) +#define PCU_WOW6__OFFSET11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define PCU_WOW6__OFFSET11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define PCU_WOW6__TYPE u_int32_t +#define PCU_WOW6__READ 0xffffffffU +#define PCU_WOW6__WRITE 0xffffffffU + +#endif /* __PCU_WOW6_MACRO__ */ + + +/* macros for mac_pcu_reg_map.PCU_WOW6 */ +#define INST_MAC_PCU_REG_MAP__PCU_WOW6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::PCU_WOW7 */ +#ifndef __PCU_WOW7_MACRO__ +#define __PCU_WOW7_MACRO__ + +/* macros for field OFFSET12 */ +#define PCU_WOW7__OFFSET12__SHIFT 0 +#define PCU_WOW7__OFFSET12__WIDTH 8 +#define PCU_WOW7__OFFSET12__MASK 0x000000ffU +#define PCU_WOW7__OFFSET12__READ(src) (u_int32_t)(src) & 0x000000ffU +#define PCU_WOW7__OFFSET12__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define PCU_WOW7__OFFSET12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define PCU_WOW7__OFFSET12__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field OFFSET13 */ +#define PCU_WOW7__OFFSET13__SHIFT 8 +#define PCU_WOW7__OFFSET13__WIDTH 8 +#define PCU_WOW7__OFFSET13__MASK 0x0000ff00U +#define PCU_WOW7__OFFSET13__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define PCU_WOW7__OFFSET13__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) +#define PCU_WOW7__OFFSET13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define PCU_WOW7__OFFSET13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field OFFSET14 */ +#define PCU_WOW7__OFFSET14__SHIFT 16 +#define PCU_WOW7__OFFSET14__WIDTH 8 +#define PCU_WOW7__OFFSET14__MASK 0x00ff0000U +#define PCU_WOW7__OFFSET14__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) +#define PCU_WOW7__OFFSET14__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) +#define PCU_WOW7__OFFSET14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PCU_WOW7__OFFSET14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field OFFSET15 */ +#define PCU_WOW7__OFFSET15__SHIFT 24 +#define PCU_WOW7__OFFSET15__WIDTH 8 +#define PCU_WOW7__OFFSET15__MASK 0xff000000U +#define PCU_WOW7__OFFSET15__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) +#define PCU_WOW7__OFFSET15__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) +#define PCU_WOW7__OFFSET15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define PCU_WOW7__OFFSET15__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define PCU_WOW7__TYPE u_int32_t +#define PCU_WOW7__READ 0xffffffffU +#define PCU_WOW7__WRITE 0xffffffffU + +#endif /* __PCU_WOW7_MACRO__ */ + + +/* macros for mac_pcu_reg_map.PCU_WOW7 */ +#define INST_MAC_PCU_REG_MAP__PCU_WOW7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH3 */ +#ifndef __MAC_PCU_WOW_LENGTH3_MACRO__ +#define __MAC_PCU_WOW_LENGTH3_MACRO__ + +/* macros for field PATTERN_11 */ +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__SHIFT 0 +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__WIDTH 8 +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__MASK 0x000000ffU +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW_LENGTH3__PATTERN_11__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_10 */ +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__SHIFT 8 +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__WIDTH 8 +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__MASK 0x0000ff00U +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field PATTERN_9 */ +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__SHIFT 16 +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__WIDTH 8 +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__MASK 0x00ff0000U +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field PATTERN_8 */ +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__SHIFT 24 +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__WIDTH 8 +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__MASK 0xff000000U +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH3__PATTERN_8__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_WOW_LENGTH3__TYPE u_int32_t +#define MAC_PCU_WOW_LENGTH3__READ 0xffffffffU +#define MAC_PCU_WOW_LENGTH3__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW_LENGTH3_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH3 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH4 */ +#ifndef __MAC_PCU_WOW_LENGTH4_MACRO__ +#define __MAC_PCU_WOW_LENGTH4_MACRO__ + +/* macros for field PATTERN_15 */ +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__SHIFT 0 +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__WIDTH 8 +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__MASK 0x000000ffU +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_WOW_LENGTH4__PATTERN_15__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field PATTERN_14 */ +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__SHIFT 8 +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__WIDTH 8 +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__MASK 0x0000ff00U +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field PATTERN_13 */ +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__SHIFT 16 +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__WIDTH 8 +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__MASK 0x00ff0000U +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field PATTERN_12 */ +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__SHIFT 24 +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__WIDTH 8 +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__MASK 0xff000000U +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_WOW_LENGTH4__PATTERN_12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_WOW_LENGTH4__TYPE u_int32_t +#define MAC_PCU_WOW_LENGTH4__READ 0xffffffffU +#define MAC_PCU_WOW_LENGTH4__WRITE 0xffffffffU + +#endif /* __MAC_PCU_WOW_LENGTH4_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH4 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOCATION_MODE_CONTROL */ +#ifndef __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__ +#define __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__ + +/* macros for field ENABLE */ +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__SHIFT 0 +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WIDTH 1 +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MASK 0x00000001U +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field UPLOAD_H_DISABLE */ +#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__SHIFT 1 +#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__WIDTH 1 +#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__MASK 0x00000002U +#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define MAC_PCU_LOCATION_MODE_CONTROL__TYPE u_int32_t +#define MAC_PCU_LOCATION_MODE_CONTROL__READ 0x00000003U +#define MAC_PCU_LOCATION_MODE_CONTROL__WRITE 0x00000003U + +#endif /* __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_LOCATION_MODE_CONTROL */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOCATION_MODE_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOCATION_MODE_TIMER */ +#ifndef __MAC_PCU_LOCATION_MODE_TIMER_MACRO__ +#define __MAC_PCU_LOCATION_MODE_TIMER_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__SHIFT 0 +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WIDTH 32 +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MASK 0xffffffffU +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_LOCATION_MODE_TIMER__TYPE u_int32_t +#define MAC_PCU_LOCATION_MODE_TIMER__READ 0xffffffffU +#define MAC_PCU_LOCATION_MODE_TIMER__WRITE 0xffffffffU + +#endif /* __MAC_PCU_LOCATION_MODE_TIMER_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_LOCATION_MODE_TIMER */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOCATION_MODE_TIMER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF2_L32 */ +#ifndef __MAC_PCU_TSF2_L32_MACRO__ +#define __MAC_PCU_TSF2_L32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TSF2_L32__VALUE__SHIFT 0 +#define MAC_PCU_TSF2_L32__VALUE__WIDTH 32 +#define MAC_PCU_TSF2_L32__VALUE__MASK 0xffffffffU +#define MAC_PCU_TSF2_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TSF2_L32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TSF2_L32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TSF2_L32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TSF2_L32__TYPE u_int32_t +#define MAC_PCU_TSF2_L32__READ 0xffffffffU +#define MAC_PCU_TSF2_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TSF2_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TSF2_L32 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF2_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF2_U32 */ +#ifndef __MAC_PCU_TSF2_U32_MACRO__ +#define __MAC_PCU_TSF2_U32_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_TSF2_U32__VALUE__SHIFT 0 +#define MAC_PCU_TSF2_U32__VALUE__WIDTH 32 +#define MAC_PCU_TSF2_U32__VALUE__MASK 0xffffffffU +#define MAC_PCU_TSF2_U32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TSF2_U32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TSF2_U32__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TSF2_U32__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TSF2_U32__TYPE u_int32_t +#define MAC_PCU_TSF2_U32__READ 0xffffffffU +#define MAC_PCU_TSF2_U32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TSF2_U32_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TSF2_U32 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF2_U32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID2_L32 */ +#ifndef __MAC_PCU_BSSID2_L32_MACRO__ +#define __MAC_PCU_BSSID2_L32_MACRO__ + +/* macros for field ADDR */ +#define MAC_PCU_BSSID2_L32__ADDR__SHIFT 0 +#define MAC_PCU_BSSID2_L32__ADDR__WIDTH 32 +#define MAC_PCU_BSSID2_L32__ADDR__MASK 0xffffffffU +#define MAC_PCU_BSSID2_L32__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_BSSID2_L32__ADDR__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_BSSID2_L32__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BSSID2_L32__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BSSID2_L32__TYPE u_int32_t +#define MAC_PCU_BSSID2_L32__READ 0xffffffffU +#define MAC_PCU_BSSID2_L32__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BSSID2_L32_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BSSID2_L32 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID2_L32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID2_U16 */ +#ifndef __MAC_PCU_BSSID2_U16_MACRO__ +#define __MAC_PCU_BSSID2_U16_MACRO__ + +/* macros for field ADDR */ +#define MAC_PCU_BSSID2_U16__ADDR__SHIFT 0 +#define MAC_PCU_BSSID2_U16__ADDR__WIDTH 16 +#define MAC_PCU_BSSID2_U16__ADDR__MASK 0x0000ffffU +#define MAC_PCU_BSSID2_U16__ADDR__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define MAC_PCU_BSSID2_U16__ADDR__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define MAC_PCU_BSSID2_U16__ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define MAC_PCU_BSSID2_U16__ADDR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field ENABLE */ +#define MAC_PCU_BSSID2_U16__ENABLE__SHIFT 16 +#define MAC_PCU_BSSID2_U16__ENABLE__WIDTH 1 +#define MAC_PCU_BSSID2_U16__ENABLE__MASK 0x00010000U +#define MAC_PCU_BSSID2_U16__ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_BSSID2_U16__ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_BSSID2_U16__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_BSSID2_U16__ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_BSSID2_U16__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_BSSID2_U16__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) +#define MAC_PCU_BSSID2_U16__TYPE u_int32_t +#define MAC_PCU_BSSID2_U16__READ 0x0001ffffU +#define MAC_PCU_BSSID2_U16__WRITE 0x0001ffffU + +#endif /* __MAC_PCU_BSSID2_U16_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BSSID2_U16 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID2_U16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_DIRECT_CONNECT */ +#ifndef __MAC_PCU_DIRECT_CONNECT_MACRO__ +#define __MAC_PCU_DIRECT_CONNECT_MACRO__ + +/* macros for field AP_STA_ENABLE */ +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__SHIFT 0 +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MASK 0x00000001U +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field TBTT_TIMER_0_8_SEL */ +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__SHIFT 4 +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MASK 0x00000010U +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field DMA_BALERT_TIMER_1_9_SEL */ +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__SHIFT 5 +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MASK 0x00000020U +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field SW_BALERT_TIMER_2_10_SEL */ +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__SHIFT 6 +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MASK 0x00000040U +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field HCF_TO_TIMER_3_11_SEL */ +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__SHIFT 7 +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MASK 0x00000080U +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field NEXT_TIM_TIMER_4_12_SEL */ +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__SHIFT 8 +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MASK 0x00000100U +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field NEXT_DTIM_TIMER_5_13_SEL */ +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__SHIFT 9 +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MASK 0x00000200U +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field QUIET_TM_TIMER_6_14_SEL */ +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__SHIFT 10 +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MASK 0x00000400U +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field TBTT2_TIMER_0_8_SEL */ +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__SHIFT 11 +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MASK 0x00000800U +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field AP_TSF_1_2_SEL */ +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__SHIFT 12 +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MASK 0x00001000U +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field STA_TSF_1_2_SEL */ +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__SHIFT 13 +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MASK 0x00002000U +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field BC_MC_WAPI_MODE2_EN */ +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__SHIFT 14 +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__MASK 0x00004000U +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field BC_MC_WAPI_MODE_AP_SEL */ +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__SHIFT 15 +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__MASK 0x00008000U +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field DESC_SVD_TSF_SEL_EN */ +#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__SHIFT 16 +#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__WIDTH 1 +#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__MASK 0x00010000U +#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) +#define MAC_PCU_DIRECT_CONNECT__TYPE u_int32_t +#define MAC_PCU_DIRECT_CONNECT__READ 0x0001fff1U +#define MAC_PCU_DIRECT_CONNECT__WRITE 0x0001fff1U + +#endif /* __MAC_PCU_DIRECT_CONNECT_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_DIRECT_CONNECT */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_DIRECT_CONNECT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TID_TO_AC */ +#ifndef __MAC_PCU_TID_TO_AC_MACRO__ +#define __MAC_PCU_TID_TO_AC_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_TID_TO_AC__DATA__SHIFT 0 +#define MAC_PCU_TID_TO_AC__DATA__WIDTH 32 +#define MAC_PCU_TID_TO_AC__DATA__MASK 0xffffffffU +#define MAC_PCU_TID_TO_AC__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TID_TO_AC__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TID_TO_AC__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TID_TO_AC__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TID_TO_AC__TYPE u_int32_t +#define MAC_PCU_TID_TO_AC__READ 0xffffffffU +#define MAC_PCU_TID_TO_AC__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TID_TO_AC_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TID_TO_AC */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TID_TO_AC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_HP_QUEUE */ +#ifndef __MAC_PCU_HP_QUEUE_MACRO__ +#define __MAC_PCU_HP_QUEUE_MACRO__ + +/* macros for field ENABLE */ +#define MAC_PCU_HP_QUEUE__ENABLE__SHIFT 0 +#define MAC_PCU_HP_QUEUE__ENABLE__WIDTH 1 +#define MAC_PCU_HP_QUEUE__ENABLE__MASK 0x00000001U +#define MAC_PCU_HP_QUEUE__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_HP_QUEUE__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_PCU_HP_QUEUE__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_HP_QUEUE__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_HP_QUEUE__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_HP_QUEUE__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field AC_MASK_BE */ +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__SHIFT 1 +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__WIDTH 1 +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__MASK 0x00000002U +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_HP_QUEUE__AC_MASK_BE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field AC_MASK_BK */ +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__SHIFT 2 +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__WIDTH 1 +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__MASK 0x00000004U +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_HP_QUEUE__AC_MASK_BK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field AC_MASK_VI */ +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__SHIFT 3 +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__WIDTH 1 +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__MASK 0x00000008U +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_HP_QUEUE__AC_MASK_VI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field AC_MASK_VO */ +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__SHIFT 4 +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__WIDTH 1 +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__MASK 0x00000010U +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_HP_QUEUE__AC_MASK_VO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field HPQON_UAPSD */ +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__SHIFT 5 +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WIDTH 1 +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MASK 0x00000020U +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field FRAME_FILTER_ENABLE0 */ +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__SHIFT 6 +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WIDTH 1 +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MASK 0x00000040U +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field FRAME_BSSID_MATCH0 */ +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__SHIFT 7 +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WIDTH 1 +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MASK 0x00000080U +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field FRAME_TYPE0 */ +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__SHIFT 8 +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WIDTH 2 +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MASK 0x00000300U +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field FRAME_TYPE_MASK0 */ +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__SHIFT 10 +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WIDTH 2 +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MASK 0x00000c00U +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) + +/* macros for field FRAME_SUBTYPE0 */ +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__SHIFT 12 +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WIDTH 4 +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MASK 0x0000f000U +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field FRAME_SUBTYPE_MASK0 */ +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__SHIFT 16 +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WIDTH 4 +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MASK 0x000f0000U +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field UAPSD_EN */ +#define MAC_PCU_HP_QUEUE__UAPSD_EN__SHIFT 20 +#define MAC_PCU_HP_QUEUE__UAPSD_EN__WIDTH 1 +#define MAC_PCU_HP_QUEUE__UAPSD_EN__MASK 0x00100000U +#define MAC_PCU_HP_QUEUE__UAPSD_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_HP_QUEUE__UAPSD_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_HP_QUEUE__UAPSD_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_HP_QUEUE__UAPSD_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_HP_QUEUE__UAPSD_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_HP_QUEUE__UAPSD_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field PM_CHANGE */ +#define MAC_PCU_HP_QUEUE__PM_CHANGE__SHIFT 21 +#define MAC_PCU_HP_QUEUE__PM_CHANGE__WIDTH 1 +#define MAC_PCU_HP_QUEUE__PM_CHANGE__MASK 0x00200000U +#define MAC_PCU_HP_QUEUE__PM_CHANGE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_HP_QUEUE__PM_CHANGE__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_HP_QUEUE__PM_CHANGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_HP_QUEUE__PM_CHANGE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_HP_QUEUE__PM_CHANGE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_HP_QUEUE__PM_CHANGE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field NON_UAPSD_EN */ +#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__SHIFT 22 +#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__WIDTH 1 +#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__MASK 0x00400000U +#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) +#define MAC_PCU_HP_QUEUE__TYPE u_int32_t +#define MAC_PCU_HP_QUEUE__READ 0x007fffffU +#define MAC_PCU_HP_QUEUE__WRITE 0x007fffffU + +#endif /* __MAC_PCU_HP_QUEUE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_HP_QUEUE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_HP_QUEUE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS0 */ +#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__ +#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS0 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS1 */ +#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__ +#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS2 */ +#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__ +#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS3 */ +#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__ +#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__SHIFT 0 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WIDTH 32 +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MASK 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__TYPE u_int32_t +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__READ 0xffffffffU +#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS3 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT0 */ +#ifndef __MAC_PCU_AGC_SATURATION_CNT0_MACRO__ +#define __MAC_PCU_AGC_SATURATION_CNT0_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__SHIFT 0 +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WIDTH 32 +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MASK 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_AGC_SATURATION_CNT0__TYPE u_int32_t +#define MAC_PCU_AGC_SATURATION_CNT0__READ 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT0__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AGC_SATURATION_CNT0_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT0 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT1 */ +#ifndef __MAC_PCU_AGC_SATURATION_CNT1_MACRO__ +#define __MAC_PCU_AGC_SATURATION_CNT1_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__SHIFT 0 +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WIDTH 32 +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MASK 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_AGC_SATURATION_CNT1__TYPE u_int32_t +#define MAC_PCU_AGC_SATURATION_CNT1__READ 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AGC_SATURATION_CNT1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT2 */ +#ifndef __MAC_PCU_AGC_SATURATION_CNT2_MACRO__ +#define __MAC_PCU_AGC_SATURATION_CNT2_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__SHIFT 0 +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WIDTH 32 +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MASK 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_AGC_SATURATION_CNT2__TYPE u_int32_t +#define MAC_PCU_AGC_SATURATION_CNT2__READ 0xffffffffU +#define MAC_PCU_AGC_SATURATION_CNT2__WRITE 0xffffffffU + +#endif /* __MAC_PCU_AGC_SATURATION_CNT2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_HW_BCN_PROC1 */ +#ifndef __MAC_PCU_HW_BCN_PROC1_MACRO__ +#define __MAC_PCU_HW_BCN_PROC1_MACRO__ + +/* macros for field CRC_ENABLE */ +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__SHIFT 0 +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MASK 0x00000001U +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RESET_CRC */ +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__SHIFT 1 +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MASK 0x00000002U +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field EXCLUDE_BCN_INTVL */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__SHIFT 2 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MASK 0x00000004U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field EXCLUDE_CAP_INFO */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__SHIFT 3 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MASK 0x00000008U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field EXCLUDE_TIM_ELM */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__SHIFT 4 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MASK 0x00000010U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field EXCLUDE_ELM0 */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__SHIFT 5 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MASK 0x00000020U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field EXCLUDE_ELM1 */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__SHIFT 6 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MASK 0x00000040U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field EXCLUDE_ELM2 */ +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__SHIFT 7 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MASK 0x00000080U +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field ELM0_ID */ +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__SHIFT 8 +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WIDTH 8 +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MASK 0x0000ff00U +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field ELM1_ID */ +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__SHIFT 16 +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WIDTH 8 +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MASK 0x00ff0000U +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field ELM2_ID */ +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__SHIFT 24 +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WIDTH 8 +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MASK 0xff000000U +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define MAC_PCU_HW_BCN_PROC1__TYPE u_int32_t +#define MAC_PCU_HW_BCN_PROC1__READ 0xffffffffU +#define MAC_PCU_HW_BCN_PROC1__WRITE 0xffffffffU + +#endif /* __MAC_PCU_HW_BCN_PROC1_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_HW_BCN_PROC1 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_HW_BCN_PROC1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_HW_BCN_PROC2 */ +#ifndef __MAC_PCU_HW_BCN_PROC2_MACRO__ +#define __MAC_PCU_HW_BCN_PROC2_MACRO__ + +/* macros for field FILTER_INTERVAL_ENABLE */ +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__SHIFT 0 +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MASK 0x00000001U +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RESET_INTERVAL */ +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__SHIFT 1 +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MASK 0x00000002U +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field EXCLUDE_ELM3 */ +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__SHIFT 2 +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WIDTH 1 +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MASK 0x00000004U +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field FILTER_INTERVAL */ +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__SHIFT 8 +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WIDTH 8 +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MASK 0x0000ff00U +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field ELM3_ID */ +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__SHIFT 16 +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WIDTH 8 +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MASK 0x00ff0000U +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define MAC_PCU_HW_BCN_PROC2__TYPE u_int32_t +#define MAC_PCU_HW_BCN_PROC2__READ 0x00ffff07U +#define MAC_PCU_HW_BCN_PROC2__WRITE 0x00ffff07U + +#endif /* __MAC_PCU_HW_BCN_PROC2_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_HW_BCN_PROC2 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_HW_BCN_PROC2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE3 */ +#ifndef __MAC_PCU_MISC_MODE3_MACRO__ +#define __MAC_PCU_MISC_MODE3_MACRO__ + +/* macros for field BUG_55702_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__SHIFT 0 +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MASK 0x00000001U +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field AES_3STREAM */ +#define MAC_PCU_MISC_MODE3__AES_3STREAM__SHIFT 1 +#define MAC_PCU_MISC_MODE3__AES_3STREAM__WIDTH 1 +#define MAC_PCU_MISC_MODE3__AES_3STREAM__MASK 0x00000002U +#define MAC_PCU_MISC_MODE3__AES_3STREAM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_MISC_MODE3__AES_3STREAM__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE3__AES_3STREAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_MISC_MODE3__AES_3STREAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_MISC_MODE3__AES_3STREAM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_MISC_MODE3__AES_3STREAM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field REGULAR_SOUNDING */ +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__SHIFT 2 +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WIDTH 1 +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MASK 0x00000004U +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field BUG_58011_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__SHIFT 3 +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MASK 0x00000008U +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BUG_56991_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__SHIFT 4 +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MASK 0x00000010U +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field WOW_ADDR1_MASK_ENABLE */ +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__SHIFT 5 +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MASK 0x00000020U +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field BUG_61936_FIX_ENABLE */ +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__SHIFT 6 +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MASK 0x00000040U +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field CHECK_LENGTH_FOR_BA */ +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__SHIFT 7 +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WIDTH 1 +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MASK 0x00000080U +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field BA_FRAME_LENGTH */ +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__SHIFT 8 +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WIDTH 8 +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MASK 0x0000ff00U +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field MATCH_TID_FOR_BA */ +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__SHIFT 16 +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WIDTH 1 +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MASK 0x00010000U +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field WAPI_ORDER_MASK */ +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__SHIFT 17 +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WIDTH 1 +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MASK 0x00020000U +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field BB_LDPC_EN */ +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__SHIFT 18 +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WIDTH 1 +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MASK 0x00040000U +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field SELF_GEN_SMOOTHING */ +#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__SHIFT 19 +#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__WIDTH 1 +#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__MASK 0x00080000U +#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field SMOOTHING_FORCE */ +#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__SHIFT 20 +#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__MASK 0x00100000U +#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field KEY_MISS_FIX */ +#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__SHIFT 21 +#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__WIDTH 1 +#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__MASK 0x00200000U +#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field RESERVED1 */ +#define MAC_PCU_MISC_MODE3__RESERVED1__SHIFT 22 +#define MAC_PCU_MISC_MODE3__RESERVED1__WIDTH 4 +#define MAC_PCU_MISC_MODE3__RESERVED1__MASK 0x03c00000U +#define MAC_PCU_MISC_MODE3__RESERVED1__READ(src) \ + (((u_int32_t)(src)\ + & 0x03c00000U) >> 22) +#define MAC_PCU_MISC_MODE3__RESERVED1__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x03c00000U) +#define MAC_PCU_MISC_MODE3__RESERVED1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x03c00000U) +#define MAC_PCU_MISC_MODE3__RESERVED1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x03c00000U))) + +/* macros for field PHY_ERROR_AIFS_MASK_ENABLE */ +#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__SHIFT 26 +#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__MASK 0x04000000U +#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field RESERVED */ +#define MAC_PCU_MISC_MODE3__RESERVED__SHIFT 27 +#define MAC_PCU_MISC_MODE3__RESERVED__WIDTH 3 +#define MAC_PCU_MISC_MODE3__RESERVED__MASK 0x38000000U +#define MAC_PCU_MISC_MODE3__RESERVED__READ(src) \ + (((u_int32_t)(src)\ + & 0x38000000U) >> 27) +#define MAC_PCU_MISC_MODE3__RESERVED__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x38000000U) +#define MAC_PCU_MISC_MODE3__RESERVED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x38000000U) | (((u_int32_t)(src) <<\ + 27) & 0x38000000U) +#define MAC_PCU_MISC_MODE3__RESERVED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x38000000U))) + +/* macros for field PER_STA_WEP_ENTRY_ENABLE */ +#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__SHIFT 30 +#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__WIDTH 1 +#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__MASK 0x40000000U +#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field BC_MC_WAPI_MODE2 */ +#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__SHIFT 31 +#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__WIDTH 1 +#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__MASK 0x80000000U +#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define MAC_PCU_MISC_MODE3__TYPE u_int32_t +#define MAC_PCU_MISC_MODE3__READ 0xffffffffU +#define MAC_PCU_MISC_MODE3__WRITE 0xffffffffU + +#endif /* __MAC_PCU_MISC_MODE3_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE3 */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_RSSI_AVE */ +#ifndef __MAC_PCU_FILTER_RSSI_AVE_MACRO__ +#define __MAC_PCU_FILTER_RSSI_AVE_MACRO__ + +/* macros for field AVE_VALUE */ +#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__SHIFT 0 +#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__WIDTH 8 +#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__MASK 0x000000ffU +#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field NUM_FRAMES_EXPONENT */ +#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__SHIFT 8 +#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__WIDTH 3 +#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__MASK 0x00000700U +#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field ENABLE */ +#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__SHIFT 11 +#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__WIDTH 1 +#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__MASK 0x00000800U +#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field RESET */ +#define MAC_PCU_FILTER_RSSI_AVE__RESET__SHIFT 12 +#define MAC_PCU_FILTER_RSSI_AVE__RESET__WIDTH 1 +#define MAC_PCU_FILTER_RSSI_AVE__RESET__MASK 0x00001000U +#define MAC_PCU_FILTER_RSSI_AVE__RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define MAC_PCU_FILTER_RSSI_AVE__RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define MAC_PCU_FILTER_RSSI_AVE__RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define MAC_PCU_FILTER_RSSI_AVE__RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define MAC_PCU_FILTER_RSSI_AVE__RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define MAC_PCU_FILTER_RSSI_AVE__RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) +#define MAC_PCU_FILTER_RSSI_AVE__TYPE u_int32_t +#define MAC_PCU_FILTER_RSSI_AVE__READ 0x00001fffU +#define MAC_PCU_FILTER_RSSI_AVE__WRITE 0x00001fffU + +#endif /* __MAC_PCU_FILTER_RSSI_AVE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_FILTER_RSSI_AVE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_RSSI_AVE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_AIFS_MASK */ +#ifndef __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__ +#define __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__ + +/* macros for field VALUE */ +#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__SHIFT 0 +#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__WIDTH 32 +#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__MASK 0xffffffffU +#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_PHY_ERROR_AIFS_MASK__TYPE u_int32_t +#define MAC_PCU_PHY_ERROR_AIFS_MASK__READ 0xffffffffU +#define MAC_PCU_PHY_ERROR_AIFS_MASK__WRITE 0xffffffffU + +#endif /* __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_AIFS_MASK */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_AIFS_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_PS_FILTER */ +#ifndef __MAC_PCU_PS_FILTER_MACRO__ +#define __MAC_PCU_PS_FILTER_MACRO__ + +/* macros for field ENABLE */ +#define MAC_PCU_PS_FILTER__ENABLE__SHIFT 0 +#define MAC_PCU_PS_FILTER__ENABLE__WIDTH 1 +#define MAC_PCU_PS_FILTER__ENABLE__MASK 0x00000001U +#define MAC_PCU_PS_FILTER__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U +#define MAC_PCU_PS_FILTER__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MAC_PCU_PS_FILTER__ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MAC_PCU_PS_FILTER__ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MAC_PCU_PS_FILTER__ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MAC_PCU_PS_FILTER__ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PS_SAVE_ENABLE */ +#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__SHIFT 1 +#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__WIDTH 1 +#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__MASK 0x00000002U +#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define MAC_PCU_PS_FILTER__TYPE u_int32_t +#define MAC_PCU_PS_FILTER__READ 0x00000003U +#define MAC_PCU_PS_FILTER__WRITE 0x00000003U + +#endif /* __MAC_PCU_PS_FILTER_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_PS_FILTER */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_PS_FILTER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXBUF_BA */ +#ifndef __MAC_PCU_TXBUF_BA_MACRO__ +#define __MAC_PCU_TXBUF_BA_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_TXBUF_BA__DATA__SHIFT 0 +#define MAC_PCU_TXBUF_BA__DATA__WIDTH 32 +#define MAC_PCU_TXBUF_BA__DATA__MASK 0xffffffffU +#define MAC_PCU_TXBUF_BA__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_TXBUF_BA__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_TXBUF_BA__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_TXBUF_BA__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_TXBUF_BA__TYPE u_int32_t +#define MAC_PCU_TXBUF_BA__READ 0xffffffffU +#define MAC_PCU_TXBUF_BA__WRITE 0xffffffffU + +#endif /* __MAC_PCU_TXBUF_BA_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_TXBUF_BA */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXBUF_BA__NUM 64 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_KEY_CACHE */ +#ifndef __MAC_PCU_KEY_CACHE_MACRO__ +#define __MAC_PCU_KEY_CACHE_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_KEY_CACHE__DATA__SHIFT 0 +#define MAC_PCU_KEY_CACHE__DATA__WIDTH 32 +#define MAC_PCU_KEY_CACHE__DATA__MASK 0xffffffffU +#define MAC_PCU_KEY_CACHE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_KEY_CACHE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_KEY_CACHE__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_KEY_CACHE__DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define MAC_PCU_KEY_CACHE__TYPE u_int32_t +#define MAC_PCU_KEY_CACHE__READ 0xffffffffU +#define MAC_PCU_KEY_CACHE__WRITE 0xffffffffU + +#endif /* __MAC_PCU_KEY_CACHE_MACRO__ */ + + +/* macros for mac_pcu_reg_map.MAC_PCU_KEY_CACHE */ +#define INST_MAC_PCU_REG_MAP__MAC_PCU_KEY_CACHE__NUM 1024 + +/* macros for BlueprintGlobalNameSpace::timing_controls_1 */ +#ifndef __TIMING_CONTROLS_1_MACRO__ +#define __TIMING_CONTROLS_1_MACRO__ + +/* macros for field ste_thr */ +#define TIMING_CONTROLS_1__STE_THR__SHIFT 0 +#define TIMING_CONTROLS_1__STE_THR__WIDTH 7 +#define TIMING_CONTROLS_1__STE_THR__MASK 0x0000007fU +#define TIMING_CONTROLS_1__STE_THR__READ(src) (u_int32_t)(src) & 0x0000007fU +#define TIMING_CONTROLS_1__STE_THR__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) +#define TIMING_CONTROLS_1__STE_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define TIMING_CONTROLS_1__STE_THR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field ste_to_long1 */ +#define TIMING_CONTROLS_1__STE_TO_LONG1__SHIFT 7 +#define TIMING_CONTROLS_1__STE_TO_LONG1__WIDTH 6 +#define TIMING_CONTROLS_1__STE_TO_LONG1__MASK 0x00001f80U +#define TIMING_CONTROLS_1__STE_TO_LONG1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f80U) >> 7) +#define TIMING_CONTROLS_1__STE_TO_LONG1__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00001f80U) +#define TIMING_CONTROLS_1__STE_TO_LONG1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00001f80U) +#define TIMING_CONTROLS_1__STE_TO_LONG1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00001f80U))) + +/* macros for field timing_backoff */ +#define TIMING_CONTROLS_1__TIMING_BACKOFF__SHIFT 13 +#define TIMING_CONTROLS_1__TIMING_BACKOFF__WIDTH 4 +#define TIMING_CONTROLS_1__TIMING_BACKOFF__MASK 0x0001e000U +#define TIMING_CONTROLS_1__TIMING_BACKOFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001e000U) >> 13) +#define TIMING_CONTROLS_1__TIMING_BACKOFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0001e000U) +#define TIMING_CONTROLS_1__TIMING_BACKOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0001e000U) +#define TIMING_CONTROLS_1__TIMING_BACKOFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0001e000U))) + +/* macros for field enable_ht_fine_ppm */ +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__SHIFT 17 +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WIDTH 1 +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MASK 0x00020000U +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field ht_fine_ppm_stream */ +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__SHIFT 18 +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WIDTH 2 +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MASK 0x000c0000U +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__READ(src) \ + (((u_int32_t)(src)\ + & 0x000c0000U) >> 18) +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field ht_fine_ppm_qam */ +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__SHIFT 20 +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WIDTH 2 +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MASK 0x00300000U +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00300000U) >> 20) +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00300000U) +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((u_int32_t)(src) <<\ + 20) & 0x00300000U) +#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00300000U))) + +/* macros for field enable_long_chanfil */ +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__SHIFT 22 +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WIDTH 1 +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MASK 0x00400000U +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field enable_rx_stbc */ +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__SHIFT 23 +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__WIDTH 1 +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__MASK 0x00800000U +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TIMING_CONTROLS_1__ENABLE_RX_STBC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field enable_channel_filter */ +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__SHIFT 24 +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WIDTH 1 +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MASK 0x01000000U +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field false_alarm */ +#define TIMING_CONTROLS_1__FALSE_ALARM__SHIFT 25 +#define TIMING_CONTROLS_1__FALSE_ALARM__WIDTH 2 +#define TIMING_CONTROLS_1__FALSE_ALARM__MASK 0x06000000U +#define TIMING_CONTROLS_1__FALSE_ALARM__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define TIMING_CONTROLS_1__FALSE_ALARM__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define TIMING_CONTROLS_1__FALSE_ALARM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define TIMING_CONTROLS_1__FALSE_ALARM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field enable_long_rescale */ +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__SHIFT 27 +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WIDTH 1 +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MASK 0x08000000U +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field timing_leak_enable */ +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__SHIFT 28 +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WIDTH 1 +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MASK 0x10000000U +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field coarse_ppm_select */ +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__SHIFT 29 +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WIDTH 2 +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MASK 0x60000000U +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x60000000U) >> 29) +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x60000000U) +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x60000000U) | (((u_int32_t)(src) <<\ + 29) & 0x60000000U) +#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x60000000U))) + +/* macros for field fft_scaling */ +#define TIMING_CONTROLS_1__FFT_SCALING__SHIFT 31 +#define TIMING_CONTROLS_1__FFT_SCALING__WIDTH 1 +#define TIMING_CONTROLS_1__FFT_SCALING__MASK 0x80000000U +#define TIMING_CONTROLS_1__FFT_SCALING__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TIMING_CONTROLS_1__FFT_SCALING__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TIMING_CONTROLS_1__FFT_SCALING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TIMING_CONTROLS_1__FFT_SCALING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TIMING_CONTROLS_1__FFT_SCALING__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TIMING_CONTROLS_1__FFT_SCALING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TIMING_CONTROLS_1__TYPE u_int32_t +#define TIMING_CONTROLS_1__READ 0xffffffffU +#define TIMING_CONTROLS_1__WRITE 0xffffffffU + +#endif /* __TIMING_CONTROLS_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_1 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_controls_2 */ +#ifndef __TIMING_CONTROLS_2_MACRO__ +#define __TIMING_CONTROLS_2_MACRO__ + +/* macros for field forced_delta_phi_symbol */ +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__SHIFT 0 +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WIDTH 12 +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MASK 0x00000fffU +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field force_delta_phi_symbol */ +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__SHIFT 12 +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WIDTH 1 +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MASK 0x00001000U +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field enable_magnitude_track */ +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__SHIFT 13 +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MASK 0x00002000U +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field enable_slope_filter */ +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__SHIFT 14 +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MASK 0x00004000U +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field enable_offset_filter */ +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__SHIFT 15 +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MASK 0x00008000U +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field dc_off_deltaf_thres */ +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__SHIFT 16 +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WIDTH 7 +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MASK 0x007f0000U +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x007f0000U) +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x007f0000U) +#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x007f0000U))) + +/* macros for field dc_off_tim_const */ +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__SHIFT 24 +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WIDTH 3 +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MASK 0x07000000U +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__READ(src) \ + (((u_int32_t)(src)\ + & 0x07000000U) >> 24) +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x07000000U) +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x07000000U))) + +/* macros for field enable_dc_offset */ +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__SHIFT 27 +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MASK 0x08000000U +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field enable_dc_offset_track */ +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__SHIFT 28 +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MASK 0x10000000U +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field enable_weighting */ +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__SHIFT 29 +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MASK 0x20000000U +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field traceback128 */ +#define TIMING_CONTROLS_2__TRACEBACK128__SHIFT 30 +#define TIMING_CONTROLS_2__TRACEBACK128__WIDTH 1 +#define TIMING_CONTROLS_2__TRACEBACK128__MASK 0x40000000U +#define TIMING_CONTROLS_2__TRACEBACK128__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define TIMING_CONTROLS_2__TRACEBACK128__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define TIMING_CONTROLS_2__TRACEBACK128__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define TIMING_CONTROLS_2__TRACEBACK128__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define TIMING_CONTROLS_2__TRACEBACK128__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define TIMING_CONTROLS_2__TRACEBACK128__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field enable_ht_fine_timing */ +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__SHIFT 31 +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WIDTH 1 +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MASK 0x80000000U +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TIMING_CONTROLS_2__TYPE u_int32_t +#define TIMING_CONTROLS_2__READ 0xff7fffffU +#define TIMING_CONTROLS_2__WRITE 0xff7fffffU + +#endif /* __TIMING_CONTROLS_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_2 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_controls_3 */ +#ifndef __TIMING_CONTROLS_3_MACRO__ +#define __TIMING_CONTROLS_3_MACRO__ + +/* macros for field ppm_rescue_interval */ +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__SHIFT 0 +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WIDTH 8 +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MASK 0x000000ffU +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field enable_ppm_rescue */ +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__SHIFT 8 +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WIDTH 1 +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MASK 0x00000100U +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field enable_fine_ppm */ +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__SHIFT 9 +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WIDTH 1 +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MASK 0x00000200U +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field enable_fine_interp */ +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__SHIFT 10 +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WIDTH 1 +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MASK 0x00000400U +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field continuous_ppm_rescue */ +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__SHIFT 11 +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WIDTH 1 +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MASK 0x00000800U +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field enable_df_chanest */ +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__SHIFT 12 +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WIDTH 1 +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MASK 0x00001000U +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field delta_slope_coef_exp */ +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__SHIFT 13 +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WIDTH 4 +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MASK 0x0001e000U +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001e000U) >> 13) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0001e000U) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0001e000U) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0001e000U))) + +/* macros for field delta_slope_coef_man */ +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__SHIFT 17 +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WIDTH 15 +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MASK 0xfffe0000U +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__READ(src) \ + (((u_int32_t)(src)\ + & 0xfffe0000U) >> 17) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0xfffe0000U) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffe0000U) | (((u_int32_t)(src) <<\ + 17) & 0xfffe0000U) +#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0xfffe0000U))) +#define TIMING_CONTROLS_3__TYPE u_int32_t +#define TIMING_CONTROLS_3__READ 0xffffffffU +#define TIMING_CONTROLS_3__WRITE 0xffffffffU + +#endif /* __TIMING_CONTROLS_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_3 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_control_4 */ +#ifndef __TIMING_CONTROL_4_MACRO__ +#define __TIMING_CONTROL_4_MACRO__ + +/* macros for field cal_lg_count_max */ +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__SHIFT 12 +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WIDTH 4 +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MASK 0x0000f000U +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field do_gain_dc_iq_cal */ +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__SHIFT 16 +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WIDTH 1 +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MASK 0x00010000U +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field use_pilot_track_df */ +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__SHIFT 17 +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WIDTH 4 +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MASK 0x001e0000U +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__READ(src) \ + (((u_int32_t)(src)\ + & 0x001e0000U) >> 17) +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x001e0000U) +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x001e0000U) +#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x001e0000U))) + +/* macros for field early_trigger_thr */ +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__SHIFT 21 +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WIDTH 7 +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MASK 0x0fe00000U +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fe00000U) >> 21) +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x0fe00000U) +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x0fe00000U) +#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x0fe00000U))) + +/* macros for field enable_pilot_mask */ +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__SHIFT 28 +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WIDTH 1 +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MASK 0x10000000U +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field enable_chan_mask */ +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__SHIFT 29 +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WIDTH 1 +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MASK 0x20000000U +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field enable_spur_filter */ +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__SHIFT 30 +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WIDTH 1 +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MASK 0x40000000U +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field enable_spur_rssi */ +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__SHIFT 31 +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WIDTH 1 +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MASK 0x80000000U +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TIMING_CONTROL_4__TYPE u_int32_t +#define TIMING_CONTROL_4__READ 0xfffff000U +#define TIMING_CONTROL_4__WRITE 0xfffff000U + +#endif /* __TIMING_CONTROL_4_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_4 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_control_5 */ +#ifndef __TIMING_CONTROL_5_MACRO__ +#define __TIMING_CONTROL_5_MACRO__ + +/* macros for field enable_cycpwr_thr1 */ +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__SHIFT 0 +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WIDTH 1 +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MASK 0x00000001U +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cycpwr_thr1 */ +#define TIMING_CONTROL_5__CYCPWR_THR1__SHIFT 1 +#define TIMING_CONTROL_5__CYCPWR_THR1__WIDTH 7 +#define TIMING_CONTROL_5__CYCPWR_THR1__MASK 0x000000feU +#define TIMING_CONTROL_5__CYCPWR_THR1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000feU) >> 1) +#define TIMING_CONTROL_5__CYCPWR_THR1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000000feU) +#define TIMING_CONTROL_5__CYCPWR_THR1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((u_int32_t)(src) <<\ + 1) & 0x000000feU) +#define TIMING_CONTROL_5__CYCPWR_THR1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000000feU))) + +/* macros for field enable_rssi_thr1a */ +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__SHIFT 15 +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WIDTH 1 +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MASK 0x00008000U +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field rssi_thr1a */ +#define TIMING_CONTROL_5__RSSI_THR1A__SHIFT 16 +#define TIMING_CONTROL_5__RSSI_THR1A__WIDTH 7 +#define TIMING_CONTROL_5__RSSI_THR1A__MASK 0x007f0000U +#define TIMING_CONTROL_5__RSSI_THR1A__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) +#define TIMING_CONTROL_5__RSSI_THR1A__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x007f0000U) +#define TIMING_CONTROL_5__RSSI_THR1A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x007f0000U) +#define TIMING_CONTROL_5__RSSI_THR1A__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x007f0000U))) + +/* macros for field long_sc_thresh_hi_rssi */ +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__SHIFT 23 +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__WIDTH 7 +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__MASK 0x3f800000U +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f800000U) >> 23) +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x3f800000U) +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x3f800000U) +#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x3f800000U))) + +/* macros for field forced_agc_str_pri */ +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__SHIFT 30 +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__WIDTH 1 +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__MASK 0x40000000U +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field forced_agc_str_pri_en */ +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__SHIFT 31 +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__WIDTH 1 +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__MASK 0x80000000U +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TIMING_CONTROL_5__TYPE u_int32_t +#define TIMING_CONTROL_5__READ 0xffff80ffU +#define TIMING_CONTROL_5__WRITE 0xffff80ffU + +#endif /* __TIMING_CONTROL_5_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_5 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_control_6 */ +#ifndef __TIMING_CONTROL_6_MACRO__ +#define __TIMING_CONTROL_6_MACRO__ + +/* macros for field hi_rssi_thresh */ +#define TIMING_CONTROL_6__HI_RSSI_THRESH__SHIFT 0 +#define TIMING_CONTROL_6__HI_RSSI_THRESH__WIDTH 8 +#define TIMING_CONTROL_6__HI_RSSI_THRESH__MASK 0x000000ffU +#define TIMING_CONTROL_6__HI_RSSI_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define TIMING_CONTROL_6__HI_RSSI_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TIMING_CONTROL_6__HI_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TIMING_CONTROL_6__HI_RSSI_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field early_trigger_thr_hi_rssi */ +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__SHIFT 8 +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__WIDTH 7 +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__MASK 0x00007f00U +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007f00U) >> 8) +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00007f00U) +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00007f00U) +#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00007f00U))) + +/* macros for field ofdm_xcorr_thresh */ +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__SHIFT 15 +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__WIDTH 6 +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__MASK 0x001f8000U +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f8000U) >> 15) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x001f8000U) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x001f8000U) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x001f8000U))) + +/* macros for field ofdm_xcorr_thresh_hi_rssi */ +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__SHIFT 21 +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__WIDTH 7 +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__MASK 0x0fe00000U +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fe00000U) >> 21) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x0fe00000U) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x0fe00000U) +#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x0fe00000U))) + +/* macros for field long_medium_ratio_thr */ +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__SHIFT 28 +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__WIDTH 4 +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__MASK 0xf0000000U +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0xf0000000U) >> 28) +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0xf0000000U) +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((u_int32_t)(src) <<\ + 28) & 0xf0000000U) +#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0xf0000000U))) +#define TIMING_CONTROL_6__TYPE u_int32_t +#define TIMING_CONTROL_6__READ 0xffffffffU +#define TIMING_CONTROL_6__WRITE 0xffffffffU + +#endif /* __TIMING_CONTROL_6_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_6 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_control_11 */ +#ifndef __TIMING_CONTROL_11_MACRO__ +#define __TIMING_CONTROL_11_MACRO__ + +/* macros for field spur_delta_phase */ +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__SHIFT 0 +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__WIDTH 20 +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__MASK 0x000fffffU +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__READ(src) \ + (u_int32_t)(src)\ + & 0x000fffffU +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000fffffU) +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fffffU) | ((u_int32_t)(src) &\ + 0x000fffffU) +#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000fffffU))) + +/* macros for field spur_freq_sd */ +#define TIMING_CONTROL_11__SPUR_FREQ_SD__SHIFT 20 +#define TIMING_CONTROL_11__SPUR_FREQ_SD__WIDTH 10 +#define TIMING_CONTROL_11__SPUR_FREQ_SD__MASK 0x3ff00000U +#define TIMING_CONTROL_11__SPUR_FREQ_SD__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ff00000U) >> 20) +#define TIMING_CONTROL_11__SPUR_FREQ_SD__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x3ff00000U) +#define TIMING_CONTROL_11__SPUR_FREQ_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x3ff00000U) +#define TIMING_CONTROL_11__SPUR_FREQ_SD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x3ff00000U))) + +/* macros for field use_spur_filter_in_agc */ +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__SHIFT 30 +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__WIDTH 1 +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__MASK 0x40000000U +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field use_spur_filter_in_selfcor */ +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__SHIFT 31 +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__WIDTH 1 +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__MASK 0x80000000U +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TIMING_CONTROL_11__TYPE u_int32_t +#define TIMING_CONTROL_11__READ 0xffffffffU +#define TIMING_CONTROL_11__WRITE 0xffffffffU + +#endif /* __TIMING_CONTROL_11_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_11 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_mask_controls */ +#ifndef __SPUR_MASK_CONTROLS_MACRO__ +#define __SPUR_MASK_CONTROLS_MACRO__ + +/* macros for field spur_rssi_thresh */ +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__SHIFT 0 +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__WIDTH 8 +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__MASK 0x000000ffU +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field en_vit_spur_rssi */ +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__SHIFT 8 +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__WIDTH 1 +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__MASK 0x00000100U +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field enable_mask_ppm */ +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__SHIFT 17 +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__WIDTH 1 +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__MASK 0x00020000U +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field mask_rate_cntl */ +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__SHIFT 18 +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__WIDTH 8 +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__MASK 0x03fc0000U +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__READ(src) \ + (((u_int32_t)(src)\ + & 0x03fc0000U) >> 18) +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x03fc0000U) +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x03fc0000U) +#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x03fc0000U))) + +/* macros for field enable_nf_rssi_spur_mit */ +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__SHIFT 26 +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__WIDTH 1 +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__MASK 0x04000000U +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) +#define SPUR_MASK_CONTROLS__TYPE u_int32_t +#define SPUR_MASK_CONTROLS__READ 0x07fe01ffU +#define SPUR_MASK_CONTROLS__WRITE 0x07fe01ffU + +#endif /* __SPUR_MASK_CONTROLS_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_spur_mask_controls */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SPUR_MASK_CONTROLS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::find_signal_low */ +#ifndef __FIND_SIGNAL_LOW_MACRO__ +#define __FIND_SIGNAL_LOW_MACRO__ + +/* macros for field relstep_low */ +#define FIND_SIGNAL_LOW__RELSTEP_LOW__SHIFT 0 +#define FIND_SIGNAL_LOW__RELSTEP_LOW__WIDTH 6 +#define FIND_SIGNAL_LOW__RELSTEP_LOW__MASK 0x0000003fU +#define FIND_SIGNAL_LOW__RELSTEP_LOW__READ(src) (u_int32_t)(src) & 0x0000003fU +#define FIND_SIGNAL_LOW__RELSTEP_LOW__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define FIND_SIGNAL_LOW__RELSTEP_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define FIND_SIGNAL_LOW__RELSTEP_LOW__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field firstep_low */ +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__SHIFT 6 +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__WIDTH 6 +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__MASK 0x00000fc0U +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define FIND_SIGNAL_LOW__FIRSTEP_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field firpwr_low */ +#define FIND_SIGNAL_LOW__FIRPWR_LOW__SHIFT 12 +#define FIND_SIGNAL_LOW__FIRPWR_LOW__WIDTH 8 +#define FIND_SIGNAL_LOW__FIRPWR_LOW__MASK 0x000ff000U +#define FIND_SIGNAL_LOW__FIRPWR_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ff000U) >> 12) +#define FIND_SIGNAL_LOW__FIRPWR_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x000ff000U) +#define FIND_SIGNAL_LOW__FIRPWR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x000ff000U) +#define FIND_SIGNAL_LOW__FIRPWR_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x000ff000U))) + +/* macros for field ycok_max_low */ +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__SHIFT 20 +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__WIDTH 4 +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__MASK 0x00f00000U +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) + +/* macros for field long_sc_thresh */ +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__SHIFT 24 +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__WIDTH 7 +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__MASK 0x7f000000U +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f000000U) >> 24) +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define FIND_SIGNAL_LOW__LONG_SC_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) +#define FIND_SIGNAL_LOW__TYPE u_int32_t +#define FIND_SIGNAL_LOW__READ 0x7fffffffU +#define FIND_SIGNAL_LOW__WRITE 0x7fffffffU + +#endif /* __FIND_SIGNAL_LOW_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_find_signal_low */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_FIND_SIGNAL_LOW__NUM 1 + +/* macros for BlueprintGlobalNameSpace::sfcorr */ +#ifndef __SFCORR_MACRO__ +#define __SFCORR_MACRO__ + +/* macros for field m2count_thr */ +#define SFCORR__M2COUNT_THR__SHIFT 0 +#define SFCORR__M2COUNT_THR__WIDTH 5 +#define SFCORR__M2COUNT_THR__MASK 0x0000001fU +#define SFCORR__M2COUNT_THR__READ(src) (u_int32_t)(src) & 0x0000001fU +#define SFCORR__M2COUNT_THR__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define SFCORR__M2COUNT_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define SFCORR__M2COUNT_THR__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field adcsat_thresh */ +#define SFCORR__ADCSAT_THRESH__SHIFT 5 +#define SFCORR__ADCSAT_THRESH__WIDTH 6 +#define SFCORR__ADCSAT_THRESH__MASK 0x000007e0U +#define SFCORR__ADCSAT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x000007e0U) >> 5) +#define SFCORR__ADCSAT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000007e0U) +#define SFCORR__ADCSAT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000007e0U) +#define SFCORR__ADCSAT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000007e0U))) + +/* macros for field adcsat_icount */ +#define SFCORR__ADCSAT_ICOUNT__SHIFT 11 +#define SFCORR__ADCSAT_ICOUNT__WIDTH 6 +#define SFCORR__ADCSAT_ICOUNT__MASK 0x0001f800U +#define SFCORR__ADCSAT_ICOUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f800U) >> 11) +#define SFCORR__ADCSAT_ICOUNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x0001f800U) +#define SFCORR__ADCSAT_ICOUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0001f800U) +#define SFCORR__ADCSAT_ICOUNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0001f800U))) + +/* macros for field m1_thres */ +#define SFCORR__M1_THRES__SHIFT 17 +#define SFCORR__M1_THRES__WIDTH 7 +#define SFCORR__M1_THRES__MASK 0x00fe0000U +#define SFCORR__M1_THRES__READ(src) (((u_int32_t)(src) & 0x00fe0000U) >> 17) +#define SFCORR__M1_THRES__WRITE(src) (((u_int32_t)(src) << 17) & 0x00fe0000U) +#define SFCORR__M1_THRES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x00fe0000U) +#define SFCORR__M1_THRES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00fe0000U))) + +/* macros for field m2_thres */ +#define SFCORR__M2_THRES__SHIFT 24 +#define SFCORR__M2_THRES__WIDTH 7 +#define SFCORR__M2_THRES__MASK 0x7f000000U +#define SFCORR__M2_THRES__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24) +#define SFCORR__M2_THRES__WRITE(src) (((u_int32_t)(src) << 24) & 0x7f000000U) +#define SFCORR__M2_THRES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define SFCORR__M2_THRES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) +#define SFCORR__TYPE u_int32_t +#define SFCORR__READ 0x7fffffffU +#define SFCORR__WRITE 0x7fffffffU + +#endif /* __SFCORR_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_sfcorr */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SFCORR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::self_corr_low */ +#ifndef __SELF_CORR_LOW_MACRO__ +#define __SELF_CORR_LOW_MACRO__ + +/* macros for field use_self_corr_low */ +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__SHIFT 0 +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__WIDTH 1 +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__MASK 0x00000001U +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SELF_CORR_LOW__USE_SELF_CORR_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field m1count_max_low */ +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__SHIFT 1 +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__WIDTH 7 +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__MASK 0x000000feU +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000feU) >> 1) +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000000feU) +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((u_int32_t)(src) <<\ + 1) & 0x000000feU) +#define SELF_CORR_LOW__M1COUNT_MAX_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000000feU))) + +/* macros for field m2count_thr_low */ +#define SELF_CORR_LOW__M2COUNT_THR_LOW__SHIFT 8 +#define SELF_CORR_LOW__M2COUNT_THR_LOW__WIDTH 6 +#define SELF_CORR_LOW__M2COUNT_THR_LOW__MASK 0x00003f00U +#define SELF_CORR_LOW__M2COUNT_THR_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define SELF_CORR_LOW__M2COUNT_THR_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define SELF_CORR_LOW__M2COUNT_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define SELF_CORR_LOW__M2COUNT_THR_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field m1_thresh_low */ +#define SELF_CORR_LOW__M1_THRESH_LOW__SHIFT 14 +#define SELF_CORR_LOW__M1_THRESH_LOW__WIDTH 7 +#define SELF_CORR_LOW__M1_THRESH_LOW__MASK 0x001fc000U +#define SELF_CORR_LOW__M1_THRESH_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x001fc000U) >> 14) +#define SELF_CORR_LOW__M1_THRESH_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x001fc000U) +#define SELF_CORR_LOW__M1_THRESH_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x001fc000U) +#define SELF_CORR_LOW__M1_THRESH_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x001fc000U))) + +/* macros for field m2_thresh_low */ +#define SELF_CORR_LOW__M2_THRESH_LOW__SHIFT 21 +#define SELF_CORR_LOW__M2_THRESH_LOW__WIDTH 7 +#define SELF_CORR_LOW__M2_THRESH_LOW__MASK 0x0fe00000U +#define SELF_CORR_LOW__M2_THRESH_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fe00000U) >> 21) +#define SELF_CORR_LOW__M2_THRESH_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x0fe00000U) +#define SELF_CORR_LOW__M2_THRESH_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x0fe00000U) +#define SELF_CORR_LOW__M2_THRESH_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x0fe00000U))) +#define SELF_CORR_LOW__TYPE u_int32_t +#define SELF_CORR_LOW__READ 0x0fffffffU +#define SELF_CORR_LOW__WRITE 0x0fffffffU + +#endif /* __SELF_CORR_LOW_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_self_corr_low */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SELF_CORR_LOW__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_scorr_thr */ +#ifndef __EXT_CHAN_SCORR_THR_MACRO__ +#define __EXT_CHAN_SCORR_THR_MACRO__ + +/* macros for field m1_thres_ext */ +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__SHIFT 0 +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__WIDTH 7 +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__MASK 0x0000007fU +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field m2_thres_ext */ +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__SHIFT 7 +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__WIDTH 7 +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__MASK 0x00003f80U +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f80U) >> 7) +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00003f80U) +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00003f80U) +#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00003f80U))) + +/* macros for field m1_thres_low_ext */ +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__SHIFT 14 +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__WIDTH 7 +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__MASK 0x001fc000U +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x001fc000U) >> 14) +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x001fc000U) +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x001fc000U) +#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x001fc000U))) + +/* macros for field m2_thres_low_ext */ +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__SHIFT 21 +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__WIDTH 7 +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__MASK 0x0fe00000U +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fe00000U) >> 21) +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x0fe00000U) +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x0fe00000U) +#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x0fe00000U))) + +/* macros for field spur_subchannel_sd */ +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__SHIFT 28 +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__WIDTH 1 +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__MASK 0x10000000U +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) +#define EXT_CHAN_SCORR_THR__TYPE u_int32_t +#define EXT_CHAN_SCORR_THR__READ 0x1fffffffU +#define EXT_CHAN_SCORR_THR__WRITE 0x1fffffffU + +#endif /* __EXT_CHAN_SCORR_THR_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_ext_chan_scorr_thr */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_EXT_CHAN_SCORR_THR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b0 */ +#ifndef __EXT_CHAN_PWR_THR_2_B0_MACRO__ +#define __EXT_CHAN_PWR_THR_2_B0_MACRO__ + +/* macros for field cf_maxCCApwr_ext_0 */ +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__SHIFT 0 +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__MASK 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field cycpwr_thr1_ext */ +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__SHIFT 9 +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__WIDTH 7 +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__MASK 0x0000fe00U +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fe00U) >> 9) +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x0000fe00U) +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fe00U) | (((u_int32_t)(src) <<\ + 9) & 0x0000fe00U) +#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x0000fe00U))) + +/* macros for field minCCApwr_ext_0 */ +#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__SHIFT 16 +#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__MASK 0x01ff0000U +#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01ff0000U) >> 16) +#define EXT_CHAN_PWR_THR_2_B0__TYPE u_int32_t +#define EXT_CHAN_PWR_THR_2_B0__READ 0x01ffffffU +#define EXT_CHAN_PWR_THR_2_B0__WRITE 0x01ffffffU + +#endif /* __EXT_CHAN_PWR_THR_2_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_ext_chan_pwr_thr_2_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::radar_detection */ +#ifndef __RADAR_DETECTION_MACRO__ +#define __RADAR_DETECTION_MACRO__ + +/* macros for field pulse_detect_enable */ +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__SHIFT 0 +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__WIDTH 1 +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__MASK 0x00000001U +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADAR_DETECTION__PULSE_DETECT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field pulse_in_band_thresh */ +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__SHIFT 1 +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__WIDTH 5 +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__MASK 0x0000003eU +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000003eU) +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000003eU) +#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000003eU))) + +/* macros for field pulse_rssi_thresh */ +#define RADAR_DETECTION__PULSE_RSSI_THRESH__SHIFT 6 +#define RADAR_DETECTION__PULSE_RSSI_THRESH__WIDTH 6 +#define RADAR_DETECTION__PULSE_RSSI_THRESH__MASK 0x00000fc0U +#define RADAR_DETECTION__PULSE_RSSI_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define RADAR_DETECTION__PULSE_RSSI_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define RADAR_DETECTION__PULSE_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define RADAR_DETECTION__PULSE_RSSI_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field pulse_height_thresh */ +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__SHIFT 12 +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__WIDTH 6 +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__MASK 0x0003f000U +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field radar_rssi_thresh */ +#define RADAR_DETECTION__RADAR_RSSI_THRESH__SHIFT 18 +#define RADAR_DETECTION__RADAR_RSSI_THRESH__WIDTH 6 +#define RADAR_DETECTION__RADAR_RSSI_THRESH__MASK 0x00fc0000U +#define RADAR_DETECTION__RADAR_RSSI_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define RADAR_DETECTION__RADAR_RSSI_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define RADAR_DETECTION__RADAR_RSSI_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define RADAR_DETECTION__RADAR_RSSI_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field radar_firpwr_thresh */ +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__SHIFT 24 +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__WIDTH 7 +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__MASK 0x7f000000U +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f000000U) >> 24) +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) + +/* macros for field enable_radar_fft */ +#define RADAR_DETECTION__ENABLE_RADAR_FFT__SHIFT 31 +#define RADAR_DETECTION__ENABLE_RADAR_FFT__WIDTH 1 +#define RADAR_DETECTION__ENABLE_RADAR_FFT__MASK 0x80000000U +#define RADAR_DETECTION__ENABLE_RADAR_FFT__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RADAR_DETECTION__ENABLE_RADAR_FFT__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RADAR_DETECTION__ENABLE_RADAR_FFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RADAR_DETECTION__ENABLE_RADAR_FFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RADAR_DETECTION__ENABLE_RADAR_FFT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RADAR_DETECTION__ENABLE_RADAR_FFT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RADAR_DETECTION__TYPE u_int32_t +#define RADAR_DETECTION__READ 0xffffffffU +#define RADAR_DETECTION__WRITE 0xffffffffU + +#endif /* __RADAR_DETECTION_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_radar_detection */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_RADAR_DETECTION__NUM 1 + +/* macros for BlueprintGlobalNameSpace::radar_detection_2 */ +#ifndef __RADAR_DETECTION_2_MACRO__ +#define __RADAR_DETECTION_2_MACRO__ + +/* macros for field radar_length_max */ +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__SHIFT 0 +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__WIDTH 8 +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__MASK 0x000000ffU +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field pulse_relstep_thresh */ +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__SHIFT 8 +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__WIDTH 5 +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__MASK 0x00001f00U +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) + +/* macros for field enable_pulse_relstep_check */ +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__SHIFT 13 +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__WIDTH 1 +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__MASK 0x00002000U +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field enable_max_radar_rssi */ +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__SHIFT 14 +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__WIDTH 1 +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__MASK 0x00004000U +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field enable_block_radar_check */ +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__SHIFT 15 +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__WIDTH 1 +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__MASK 0x00008000U +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field radar_relpwr_thresh */ +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__SHIFT 16 +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__WIDTH 6 +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__MASK 0x003f0000U +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field radar_use_firpwr_128 */ +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__SHIFT 22 +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__WIDTH 1 +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__MASK 0x00400000U +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field enable_radar_relpwr_check */ +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__SHIFT 23 +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__WIDTH 1 +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__MASK 0x00800000U +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field cf_radar_bin_thresh_sel */ +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__SHIFT 24 +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__WIDTH 3 +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__MASK 0x07000000U +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x07000000U) >> 24) +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x07000000U) +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x07000000U))) + +/* macros for field enable_pulse_gc_count_check */ +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__SHIFT 27 +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__WIDTH 1 +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__MASK 0x08000000U +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) +#define RADAR_DETECTION_2__TYPE u_int32_t +#define RADAR_DETECTION_2__READ 0x0fffffffU +#define RADAR_DETECTION_2__WRITE 0x0fffffffU + +#endif /* __RADAR_DETECTION_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_radar_detection_2 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_RADAR_DETECTION_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::extension_radar */ +#ifndef __EXTENSION_RADAR_MACRO__ +#define __EXTENSION_RADAR_MACRO__ + +/* macros for field blocker40_max_radar */ +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__SHIFT 8 +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__WIDTH 6 +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__MASK 0x00003f00U +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field enable_ext_radar */ +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__SHIFT 14 +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__WIDTH 1 +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__MASK 0x00004000U +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define EXTENSION_RADAR__ENABLE_EXT_RADAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field radar_dc_pwr_thresh */ +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__SHIFT 15 +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__WIDTH 8 +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__MASK 0x007f8000U +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f8000U) >> 15) +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x007f8000U) +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x007f8000U) +#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x007f8000U))) + +/* macros for field radar_lb_dc_cap */ +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__SHIFT 23 +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__WIDTH 8 +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__MASK 0x7f800000U +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f800000U) >> 23) +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x7f800000U) +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x7f800000U) +#define EXTENSION_RADAR__RADAR_LB_DC_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x7f800000U))) + +/* macros for field disable_adcsat_hold */ +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__SHIFT 31 +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__WIDTH 1 +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__MASK 0x80000000U +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define EXTENSION_RADAR__TYPE u_int32_t +#define EXTENSION_RADAR__READ 0xffffff00U +#define EXTENSION_RADAR__WRITE 0xffffff00U + +#endif /* __EXTENSION_RADAR_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_extension_radar */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_EXTENSION_RADAR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::multichain_control */ +#ifndef __MULTICHAIN_CONTROL_MACRO__ +#define __MULTICHAIN_CONTROL_MACRO__ + +/* macros for field force_analog_gain_diff */ +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__SHIFT 0 +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__WIDTH 1 +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__MASK 0x00000001U +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field forced_gain_diff_01 */ +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__SHIFT 1 +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__WIDTH 7 +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__MASK 0x000000feU +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000feU) >> 1) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000000feU) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((u_int32_t)(src) <<\ + 1) & 0x000000feU) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000000feU))) + +/* macros for field sync_synthon */ +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__SHIFT 8 +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__WIDTH 1 +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__MASK 0x00000100U +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MULTICHAIN_CONTROL__SYNC_SYNTHON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field use_posedge_refclk */ +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__SHIFT 9 +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__WIDTH 1 +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__MASK 0x00000200U +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field cf_short_sat */ +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__SHIFT 10 +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__WIDTH 11 +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__MASK 0x001ffc00U +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__READ(src) \ + (((u_int32_t)(src)\ + & 0x001ffc00U) >> 10) +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x001ffc00U) +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x001ffc00U) +#define MULTICHAIN_CONTROL__CF_SHORT_SAT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x001ffc00U))) + +/* macros for field forced_gain_diff_02 */ +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__SHIFT 22 +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__WIDTH 7 +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__MASK 0x1fc00000U +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__READ(src) \ + (((u_int32_t)(src)\ + & 0x1fc00000U) >> 22) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x1fc00000U) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x1fc00000U) +#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x1fc00000U))) + +/* macros for field force_sigma_zero */ +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__SHIFT 29 +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__WIDTH 1 +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__MASK 0x20000000U +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define MULTICHAIN_CONTROL__TYPE u_int32_t +#define MULTICHAIN_CONTROL__READ 0x3fdfffffU +#define MULTICHAIN_CONTROL__WRITE 0x3fdfffffU + +#endif /* __MULTICHAIN_CONTROL_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_multichain_control */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_MULTICHAIN_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::per_chain_csd */ +#ifndef __PER_CHAIN_CSD_MACRO__ +#define __PER_CHAIN_CSD_MACRO__ + +/* macros for field csd_chn1_2chains */ +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__SHIFT 0 +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__WIDTH 5 +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__MASK 0x0000001fU +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field csd_chn1_3chains */ +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__SHIFT 5 +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__WIDTH 5 +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__MASK 0x000003e0U +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field csd_chn2_3chains */ +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__SHIFT 10 +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__WIDTH 5 +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__MASK 0x00007c00U +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) +#define PER_CHAIN_CSD__TYPE u_int32_t +#define PER_CHAIN_CSD__READ 0x00007fffU +#define PER_CHAIN_CSD__WRITE 0x00007fffU + +#endif /* __PER_CHAIN_CSD_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_per_chain_csd */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PER_CHAIN_CSD__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_crc */ +#ifndef __TX_CRC_MACRO__ +#define __TX_CRC_MACRO__ + +/* macros for field tx_crc */ +#define TX_CRC__TX_CRC__SHIFT 0 +#define TX_CRC__TX_CRC__WIDTH 16 +#define TX_CRC__TX_CRC__MASK 0x0000ffffU +#define TX_CRC__TX_CRC__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define TX_CRC__TYPE u_int32_t +#define TX_CRC__READ 0x0000ffffU + +#endif /* __TX_CRC_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_tx_crc */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TX_CRC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tstdac_constant */ +#ifndef __TSTDAC_CONSTANT_MACRO__ +#define __TSTDAC_CONSTANT_MACRO__ + +/* macros for field cf_tstdac_constant_i */ +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__SHIFT 0 +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__WIDTH 11 +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__MASK 0x000007ffU +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__READ(src) \ + (u_int32_t)(src)\ + & 0x000007ffU +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000007ffU) +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000007ffU))) + +/* macros for field cf_tstdac_constant_q */ +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__SHIFT 11 +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__WIDTH 11 +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__MASK 0x003ff800U +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x003ff800U) >> 11) +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x003ff800U) +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003ff800U) | (((u_int32_t)(src) <<\ + 11) & 0x003ff800U) +#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x003ff800U))) +#define TSTDAC_CONSTANT__TYPE u_int32_t +#define TSTDAC_CONSTANT__READ 0x003fffffU +#define TSTDAC_CONSTANT__WRITE 0x003fffffU + +#endif /* __TSTDAC_CONSTANT_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_tstdac_constant */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TSTDAC_CONSTANT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_report_b0 */ +#ifndef __SPUR_REPORT_B0_MACRO__ +#define __SPUR_REPORT_B0_MACRO__ + +/* macros for field spur_est_i_0 */ +#define SPUR_REPORT_B0__SPUR_EST_I_0__SHIFT 0 +#define SPUR_REPORT_B0__SPUR_EST_I_0__WIDTH 8 +#define SPUR_REPORT_B0__SPUR_EST_I_0__MASK 0x000000ffU +#define SPUR_REPORT_B0__SPUR_EST_I_0__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field spur_est_q_0 */ +#define SPUR_REPORT_B0__SPUR_EST_Q_0__SHIFT 8 +#define SPUR_REPORT_B0__SPUR_EST_Q_0__WIDTH 8 +#define SPUR_REPORT_B0__SPUR_EST_Q_0__MASK 0x0000ff00U +#define SPUR_REPORT_B0__SPUR_EST_Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field power_with_spur_removed_0 */ +#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__SHIFT 16 +#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__WIDTH 16 +#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__MASK 0xffff0000U +#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define SPUR_REPORT_B0__TYPE u_int32_t +#define SPUR_REPORT_B0__READ 0xffffffffU + +#endif /* __SPUR_REPORT_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_spur_report_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SPUR_REPORT_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_control_3 */ +#ifndef __TXIQCAL_CONTROL_3_MACRO__ +#define __TXIQCAL_CONTROL_3_MACRO__ + +/* macros for field pwr_high_db */ +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__SHIFT 0 +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__WIDTH 6 +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__MASK 0x0000003fU +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field pwr_low_db */ +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__SHIFT 6 +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__WIDTH 6 +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__MASK 0x00000fc0U +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TXIQCAL_CONTROL_3__PWR_LOW_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field iqcal_tone_phs_step */ +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__SHIFT 12 +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__WIDTH 10 +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__MASK 0x003ff000U +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x003ff000U) >> 12) +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x003ff000U) +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x003ff000U) +#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x003ff000U))) + +/* macros for field dc_est_len */ +#define TXIQCAL_CONTROL_3__DC_EST_LEN__SHIFT 22 +#define TXIQCAL_CONTROL_3__DC_EST_LEN__WIDTH 2 +#define TXIQCAL_CONTROL_3__DC_EST_LEN__MASK 0x00c00000U +#define TXIQCAL_CONTROL_3__DC_EST_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00c00000U) >> 22) +#define TXIQCAL_CONTROL_3__DC_EST_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00c00000U) +#define TXIQCAL_CONTROL_3__DC_EST_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x00c00000U) +#define TXIQCAL_CONTROL_3__DC_EST_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00c00000U))) + +/* macros for field adc_sat_len */ +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__SHIFT 24 +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__WIDTH 1 +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__MASK 0x01000000U +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field adc_sat_sel */ +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__SHIFT 25 +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__WIDTH 2 +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__MASK 0x06000000U +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field iqcal_meas_len */ +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__SHIFT 27 +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__WIDTH 2 +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__MASK 0x18000000U +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x18000000U) >> 27) +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x18000000U) +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((u_int32_t)(src) <<\ + 27) & 0x18000000U) +#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x18000000U))) + +/* macros for field desired_size_db */ +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__SHIFT 29 +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__WIDTH 2 +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__MASK 0x60000000U +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x60000000U) >> 29) +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x60000000U) +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x60000000U) | (((u_int32_t)(src) <<\ + 29) & 0x60000000U) +#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x60000000U))) + +/* macros for field tx_iqcorr_en */ +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__SHIFT 31 +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__WIDTH 1 +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__MASK 0x80000000U +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TXIQCAL_CONTROL_3__TYPE u_int32_t +#define TXIQCAL_CONTROL_3__READ 0xffffffffU +#define TXIQCAL_CONTROL_3__WRITE 0xffffffffU + +#endif /* __TXIQCAL_CONTROL_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_txiqcal_control_3 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TXIQCAL_CONTROL_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::green_tx_control_1 */ +#ifndef __GREEN_TX_CONTROL_1_MACRO__ +#define __GREEN_TX_CONTROL_1_MACRO__ + +/* macros for field green_tx_enable */ +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__SHIFT 0 +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__WIDTH 1 +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MASK 0x00000001U +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field green_cases */ +#define GREEN_TX_CONTROL_1__GREEN_CASES__SHIFT 1 +#define GREEN_TX_CONTROL_1__GREEN_CASES__WIDTH 1 +#define GREEN_TX_CONTROL_1__GREEN_CASES__MASK 0x00000002U +#define GREEN_TX_CONTROL_1__GREEN_CASES__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define GREEN_TX_CONTROL_1__GREEN_CASES__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define GREEN_TX_CONTROL_1__GREEN_CASES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define GREEN_TX_CONTROL_1__GREEN_CASES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define GREEN_TX_CONTROL_1__GREEN_CASES__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define GREEN_TX_CONTROL_1__GREEN_CASES__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define GREEN_TX_CONTROL_1__TYPE u_int32_t +#define GREEN_TX_CONTROL_1__READ 0x00000003U +#define GREEN_TX_CONTROL_1__WRITE 0x00000003U + +#endif /* __GREEN_TX_CONTROL_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_green_tx_control_1 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_GREEN_TX_CONTROL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b0 */ +#ifndef __IQ_ADC_MEAS_0_B0_MACRO__ +#define __IQ_ADC_MEAS_0_B0_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_0_0 */ +#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__SHIFT 0 +#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__WIDTH 32 +#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__MASK 0xffffffffU +#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_0_B0__TYPE u_int32_t +#define IQ_ADC_MEAS_0_B0__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_0_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_0_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_0_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b0 */ +#ifndef __IQ_ADC_MEAS_1_B0_MACRO__ +#define __IQ_ADC_MEAS_1_B0_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_1_0 */ +#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__SHIFT 0 +#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__WIDTH 32 +#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__MASK 0xffffffffU +#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_1_B0__TYPE u_int32_t +#define IQ_ADC_MEAS_1_B0__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_1_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_1_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_1_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b0 */ +#ifndef __IQ_ADC_MEAS_2_B0_MACRO__ +#define __IQ_ADC_MEAS_2_B0_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_2_0 */ +#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__SHIFT 0 +#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__WIDTH 32 +#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__MASK 0xffffffffU +#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_2_B0__TYPE u_int32_t +#define IQ_ADC_MEAS_2_B0__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_2_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_2_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b0 */ +#ifndef __IQ_ADC_MEAS_3_B0_MACRO__ +#define __IQ_ADC_MEAS_3_B0_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_3_0 */ +#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__SHIFT 0 +#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__WIDTH 32 +#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__MASK 0xffffffffU +#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_3_B0__TYPE u_int32_t +#define IQ_ADC_MEAS_3_B0__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_3_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_3_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_3_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b0 */ +#ifndef __TX_PHASE_RAMP_B0_MACRO__ +#define __TX_PHASE_RAMP_B0_MACRO__ + +/* macros for field cf_phase_ramp_enable_0 */ +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__SHIFT 0 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__WIDTH 1 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__MASK 0x00000001U +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_phase_ramp_bias_0 */ +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__SHIFT 1 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__WIDTH 6 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__MASK 0x0000007eU +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000007eU) >> 1) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000007eU))) + +/* macros for field cf_phase_ramp_init_0 */ +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__SHIFT 7 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__WIDTH 10 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__MASK 0x0001ff80U +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001ff80U) >> 7) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ff80U) | (((u_int32_t)(src) <<\ + 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x0001ff80U))) + +/* macros for field cf_phase_ramp_alpha_0 */ +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__SHIFT 17 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__WIDTH 8 +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__MASK 0x01fe0000U +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fe0000U) >> 17) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x01fe0000U))) +#define TX_PHASE_RAMP_B0__TYPE u_int32_t +#define TX_PHASE_RAMP_B0__READ 0x01ffffffU +#define TX_PHASE_RAMP_B0__WRITE 0x01ffffffU + +#endif /* __TX_PHASE_RAMP_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_tx_phase_ramp_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TX_PHASE_RAMP_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b0 */ +#ifndef __ADC_GAIN_DC_CORR_B0_MACRO__ +#define __ADC_GAIN_DC_CORR_B0_MACRO__ + +/* macros for field adc_gain_corr_q_coeff_0 */ +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__SHIFT 0 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__WIDTH 6 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__MASK 0x0000003fU +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field adc_gain_corr_i_coeff_0 */ +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__SHIFT 6 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__WIDTH 6 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__MASK 0x00000fc0U +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field adc_dc_corr_q_coeff_0 */ +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__SHIFT 12 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__WIDTH 9 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__MASK 0x001ff000U +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x001ff000U) >> 12) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x001ff000U))) + +/* macros for field adc_dc_corr_i_coeff_0 */ +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__SHIFT 21 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__WIDTH 9 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__MASK 0x3fe00000U +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x3fe00000U) >> 21) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x3fe00000U))) + +/* macros for field adc_gain_corr_enable */ +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__SHIFT 30 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__WIDTH 1 +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__MASK 0x40000000U +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field adc_dc_corr_enable */ +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__SHIFT 31 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__WIDTH 1 +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__MASK 0x80000000U +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define ADC_GAIN_DC_CORR_B0__TYPE u_int32_t +#define ADC_GAIN_DC_CORR_B0__READ 0xffffffffU +#define ADC_GAIN_DC_CORR_B0__WRITE 0xffffffffU + +#endif /* __ADC_GAIN_DC_CORR_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_adc_gain_dc_corr_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_ADC_GAIN_DC_CORR_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b0 */ +#ifndef __RX_IQ_CORR_B0_MACRO__ +#define __RX_IQ_CORR_B0_MACRO__ + +/* macros for field rx_iqcorr_q_q_coff_0 */ +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__SHIFT 0 +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__WIDTH 7 +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__MASK 0x0000007fU +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field rx_iqcorr_q_i_coff_0 */ +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__SHIFT 7 +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__WIDTH 7 +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__MASK 0x00003f80U +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f80U) >> 7) +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00003f80U) +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00003f80U) +#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00003f80U))) + +/* macros for field rx_iqcorr_enable */ +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__SHIFT 14 +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__WIDTH 1 +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__MASK 0x00004000U +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field loopback_iqcorr_q_q_coff_0 */ +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__SHIFT 15 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__WIDTH 7 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__MASK 0x003f8000U +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f8000U) >> 15) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x003f8000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x003f8000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x003f8000U))) + +/* macros for field loopback_iqcorr_q_i_coff_0 */ +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__SHIFT 22 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__WIDTH 7 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__MASK 0x1fc00000U +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x1fc00000U) >> 22) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x1fc00000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x1fc00000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x1fc00000U))) + +/* macros for field loopback_iqcorr_enable */ +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__SHIFT 29 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__WIDTH 1 +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__MASK 0x20000000U +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define RX_IQ_CORR_B0__TYPE u_int32_t +#define RX_IQ_CORR_B0__READ 0x3fffffffU +#define RX_IQ_CORR_B0__WRITE 0x3fffffffU + +#endif /* __RX_IQ_CORR_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_rx_iq_corr_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_RX_IQ_CORR_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_am2am_mask */ +#ifndef __PAPRD_AM2AM_MASK_MACRO__ +#define __PAPRD_AM2AM_MASK_MACRO__ + +/* macros for field paprd_am2am_mask */ +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__SHIFT 0 +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__WIDTH 25 +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__MASK 0x01ffffffU +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x01ffffffU +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x01ffffffU) +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01ffffffU) | ((u_int32_t)(src) &\ + 0x01ffffffU) +#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x01ffffffU))) +#define PAPRD_AM2AM_MASK__TYPE u_int32_t +#define PAPRD_AM2AM_MASK__READ 0x01ffffffU +#define PAPRD_AM2AM_MASK__WRITE 0x01ffffffU + +#endif /* __PAPRD_AM2AM_MASK_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_am2am_mask */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_AM2AM_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_am2pm_mask */ +#ifndef __PAPRD_AM2PM_MASK_MACRO__ +#define __PAPRD_AM2PM_MASK_MACRO__ + +/* macros for field paprd_am2pm_mask */ +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__SHIFT 0 +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__WIDTH 25 +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__MASK 0x01ffffffU +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x01ffffffU +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x01ffffffU) +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01ffffffU) | ((u_int32_t)(src) &\ + 0x01ffffffU) +#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x01ffffffU))) +#define PAPRD_AM2PM_MASK__TYPE u_int32_t +#define PAPRD_AM2PM_MASK__READ 0x01ffffffU +#define PAPRD_AM2PM_MASK__WRITE 0x01ffffffU + +#endif /* __PAPRD_AM2PM_MASK_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_am2pm_mask */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_AM2PM_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ht40_mask */ +#ifndef __PAPRD_HT40_MASK_MACRO__ +#define __PAPRD_HT40_MASK_MACRO__ + +/* macros for field paprd_ht40_mask */ +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__SHIFT 0 +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__WIDTH 25 +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__MASK 0x01ffffffU +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x01ffffffU +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x01ffffffU) +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01ffffffU) | ((u_int32_t)(src) &\ + 0x01ffffffU) +#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x01ffffffU))) +#define PAPRD_HT40_MASK__TYPE u_int32_t +#define PAPRD_HT40_MASK__READ 0x01ffffffU +#define PAPRD_HT40_MASK__WRITE 0x01ffffffU + +#endif /* __PAPRD_HT40_MASK_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_ht40_mask */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_HT40_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b0 */ +#ifndef __PAPRD_CTRL0_B0_MACRO__ +#define __PAPRD_CTRL0_B0_MACRO__ + +/* macros for field paprd_enable_0 */ +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__SHIFT 0 +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__WIDTH 1 +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__MASK 0x00000001U +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_use_single_table_0 */ +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__SHIFT 1 +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__WIDTH 1 +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__MASK 0x00000002U +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_valid_gain_0 */ +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__SHIFT 2 +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__WIDTH 25 +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__MASK 0x07fffffcU +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fffffcU) >> 2) +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fffffcU) | (((u_int32_t)(src) <<\ + 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x07fffffcU))) + +/* macros for field paprd_mag_thrsh_0 */ +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__SHIFT 27 +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__WIDTH 5 +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__MASK 0xf8000000U +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define PAPRD_CTRL0_B0__TYPE u_int32_t +#define PAPRD_CTRL0_B0__READ 0xffffffffU +#define PAPRD_CTRL0_B0__WRITE 0xffffffffU + +#endif /* __PAPRD_CTRL0_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_ctrl0_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_CTRL0_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b0 */ +#ifndef __PAPRD_CTRL1_B0_MACRO__ +#define __PAPRD_CTRL1_B0_MACRO__ + +/* macros for field paprd_adaptive_scaling_enable_0 */ +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__SHIFT 0 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__WIDTH 1 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__MASK 0x00000001U +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_am2am_enable_0 */ +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__SHIFT 1 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__WIDTH 1 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__MASK 0x00000002U +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_adaptive_am2pm_enable_0 */ +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__SHIFT 2 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__WIDTH 1 +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__MASK 0x00000004U +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field paprd_power_at_am2am_cal_0 */ +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__SHIFT 3 +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__WIDTH 6 +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__MASK 0x000001f8U +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001f8U) >> 3) +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000001f8U) +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000001f8U) +#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000001f8U))) + +/* macros for field pa_gain_scale_factor_0 */ +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__SHIFT 9 +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__WIDTH 8 +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__MASK 0x0001fe00U +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fe00U) >> 9) +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((u_int32_t)(src) <<\ + 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x0001fe00U))) + +/* macros for field paprd_mag_scale_factor_0 */ +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__SHIFT 17 +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__WIDTH 10 +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__MASK 0x07fe0000U +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fe0000U) >> 17) +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x07fe0000U))) + +/* macros for field paprd_trainer_iandq_sel_0 */ +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__SHIFT 27 +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__WIDTH 1 +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__MASK 0x08000000U +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) +#define PAPRD_CTRL1_B0__TYPE u_int32_t +#define PAPRD_CTRL1_B0__READ 0x0fffffffU +#define PAPRD_CTRL1_B0__WRITE 0x0fffffffU + +#endif /* __PAPRD_CTRL1_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_ctrl1_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_CTRL1_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain123_b0 */ +#ifndef __PA_GAIN123_B0_MACRO__ +#define __PA_GAIN123_B0_MACRO__ + +/* macros for field pa_gain1_0 */ +#define PA_GAIN123_B0__PA_GAIN1_0__SHIFT 0 +#define PA_GAIN123_B0__PA_GAIN1_0__WIDTH 10 +#define PA_GAIN123_B0__PA_GAIN1_0__MASK 0x000003ffU +#define PA_GAIN123_B0__PA_GAIN1_0__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN123_B0__PA_GAIN1_0__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN123_B0__PA_GAIN1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN123_B0__PA_GAIN1_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain2_0 */ +#define PA_GAIN123_B0__PA_GAIN2_0__SHIFT 10 +#define PA_GAIN123_B0__PA_GAIN2_0__WIDTH 10 +#define PA_GAIN123_B0__PA_GAIN2_0__MASK 0x000ffc00U +#define PA_GAIN123_B0__PA_GAIN2_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN123_B0__PA_GAIN2_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN123_B0__PA_GAIN2_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN123_B0__PA_GAIN2_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field pa_gain3_0 */ +#define PA_GAIN123_B0__PA_GAIN3_0__SHIFT 20 +#define PA_GAIN123_B0__PA_GAIN3_0__WIDTH 10 +#define PA_GAIN123_B0__PA_GAIN3_0__MASK 0x3ff00000U +#define PA_GAIN123_B0__PA_GAIN3_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ff00000U) >> 20) +#define PA_GAIN123_B0__PA_GAIN3_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x3ff00000U) +#define PA_GAIN123_B0__PA_GAIN3_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x3ff00000U) +#define PA_GAIN123_B0__PA_GAIN3_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define PA_GAIN123_B0__TYPE u_int32_t +#define PA_GAIN123_B0__READ 0x3fffffffU +#define PA_GAIN123_B0__WRITE 0x3fffffffU + +#endif /* __PA_GAIN123_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_pa_gain123_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PA_GAIN123_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain45_b0 */ +#ifndef __PA_GAIN45_B0_MACRO__ +#define __PA_GAIN45_B0_MACRO__ + +/* macros for field pa_gain4_0 */ +#define PA_GAIN45_B0__PA_GAIN4_0__SHIFT 0 +#define PA_GAIN45_B0__PA_GAIN4_0__WIDTH 10 +#define PA_GAIN45_B0__PA_GAIN4_0__MASK 0x000003ffU +#define PA_GAIN45_B0__PA_GAIN4_0__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN45_B0__PA_GAIN4_0__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN45_B0__PA_GAIN4_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN45_B0__PA_GAIN4_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain5_0 */ +#define PA_GAIN45_B0__PA_GAIN5_0__SHIFT 10 +#define PA_GAIN45_B0__PA_GAIN5_0__WIDTH 10 +#define PA_GAIN45_B0__PA_GAIN5_0__MASK 0x000ffc00U +#define PA_GAIN45_B0__PA_GAIN5_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN45_B0__PA_GAIN5_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN45_B0__PA_GAIN5_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN45_B0__PA_GAIN5_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field paprd_adaptive_table_valid_0 */ +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__SHIFT 20 +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__WIDTH 5 +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__MASK 0x01f00000U +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) +#define PA_GAIN45_B0__TYPE u_int32_t +#define PA_GAIN45_B0__READ 0x01ffffffU +#define PA_GAIN45_B0__WRITE 0x01ffffffU + +#endif /* __PA_GAIN45_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_pa_gain45_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PA_GAIN45_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_0_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_0_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_0_0 */ +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_0_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_0_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_0_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_0_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_1_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_1_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_1_0 */ +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_1_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_1_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_1_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_1_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_2_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_2_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_2_0 */ +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_2_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_2_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_2_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_2_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_3_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_3_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_3_0 */ +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_3_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_3_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_3_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_3_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_4_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_4_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_4_0 */ +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_4_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_4_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_4_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_4_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_5_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_5_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_5_0 */ +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_5_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_5_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_5_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_5_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_6_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_6_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_6_0 */ +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_6_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_6_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_6_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_6_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b0 */ +#ifndef __PAPRD_PRE_POST_SCALE_7_B0_MACRO__ +#define __PAPRD_PRE_POST_SCALE_7_B0_MACRO__ + +/* macros for field paprd_pre_post_scaling_7_0 */ +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_7_B0__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_7_B0__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B0__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_7_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_7_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */ +#ifndef __PAPRD_MEM_TAB_MACRO__ +#define __PAPRD_MEM_TAB_MACRO__ + +/* macros for field paprd_mem */ +#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT 0 +#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH 22 +#define PAPRD_MEM_TAB__PAPRD_MEM__MASK 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((u_int32_t)(src) &\ + 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x003fffffU))) +#define PAPRD_MEM_TAB__TYPE u_int32_t +#define PAPRD_MEM_TAB__READ 0x003fffffU +#define PAPRD_MEM_TAB__WRITE 0x003fffffU + +#endif /* __PAPRD_MEM_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_mem_tab_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_MEM_TAB_B0__NUM 120 + +/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */ +#ifndef __CHAN_INFO_CHAN_TAB_MACRO__ +#define __CHAN_INFO_CHAN_TAB_MACRO__ + +/* macros for field chaninfo_word */ +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT 0 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH 32 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK 0xffffffffU +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define CHAN_INFO_CHAN_TAB__TYPE u_int32_t +#define CHAN_INFO_CHAN_TAB__READ 0xffffffffU + +#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_chan_info_chan_tab_b0 */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B0__NUM 60 + +/* macros for BlueprintGlobalNameSpace::chn_tables_intf_addr */ +#ifndef __CHN_TABLES_INTF_ADDR_MACRO__ +#define __CHN_TABLES_INTF_ADDR_MACRO__ + +/* macros for field chn_tables_addr */ +#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__SHIFT 2 +#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__WIDTH 16 +#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__MASK 0x0003fffcU +#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fffcU) >> 2) +#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0003fffcU) +#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0003fffcU) +#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0003fffcU))) + +/* macros for field chn_addr_auto_incr */ +#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__SHIFT 31 +#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__WIDTH 1 +#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__MASK 0x80000000U +#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define CHN_TABLES_INTF_ADDR__TYPE u_int32_t +#define CHN_TABLES_INTF_ADDR__READ 0x8003fffcU +#define CHN_TABLES_INTF_ADDR__WRITE 0x8003fffcU + +#endif /* __CHN_TABLES_INTF_ADDR_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_chn_tables_intf_addr */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_CHN_TABLES_INTF_ADDR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chn_tables_intf_data */ +#ifndef __CHN_TABLES_INTF_DATA_MACRO__ +#define __CHN_TABLES_INTF_DATA_MACRO__ + +/* macros for field chn_tables_data */ +#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__SHIFT 0 +#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__WIDTH 32 +#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__MASK 0xffffffffU +#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CHN_TABLES_INTF_DATA__TYPE u_int32_t +#define CHN_TABLES_INTF_DATA__READ 0xffffffffU +#define CHN_TABLES_INTF_DATA__WRITE 0xffffffffU + +#endif /* __CHN_TABLES_INTF_DATA_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn_reg_map.BB_chn_tables_intf_data */ +#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_CHN_TABLES_INTF_DATA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::timing_control_3a */ +#ifndef __TIMING_CONTROL_3A_MACRO__ +#define __TIMING_CONTROL_3A_MACRO__ + +/* macros for field ste_thr_hi_rssi */ +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__SHIFT 0 +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__WIDTH 7 +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__MASK 0x0000007fU +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field use_htsig1_20_40_bw_value */ +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__SHIFT 7 +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__WIDTH 1 +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__MASK 0x00000080U +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) +#define TIMING_CONTROL_3A__TYPE u_int32_t +#define TIMING_CONTROL_3A__READ 0x000000ffU +#define TIMING_CONTROL_3A__WRITE 0x000000ffU + +#endif /* __TIMING_CONTROL_3A_MACRO__ */ + + +/* macros for bb_reg_map.bb_mrc_reg_map.BB_timing_control_3a */ +#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_TIMING_CONTROL_3A__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ldpc_cntl1 */ +#ifndef __LDPC_CNTL1_MACRO__ +#define __LDPC_CNTL1_MACRO__ + +/* macros for field ldpc_llr_scaling0 */ +#define LDPC_CNTL1__LDPC_LLR_SCALING0__SHIFT 0 +#define LDPC_CNTL1__LDPC_LLR_SCALING0__WIDTH 32 +#define LDPC_CNTL1__LDPC_LLR_SCALING0__MASK 0xffffffffU +#define LDPC_CNTL1__LDPC_LLR_SCALING0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define LDPC_CNTL1__LDPC_LLR_SCALING0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define LDPC_CNTL1__LDPC_LLR_SCALING0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define LDPC_CNTL1__LDPC_LLR_SCALING0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define LDPC_CNTL1__TYPE u_int32_t +#define LDPC_CNTL1__READ 0xffffffffU +#define LDPC_CNTL1__WRITE 0xffffffffU + +#endif /* __LDPC_CNTL1_MACRO__ */ + + +/* macros for bb_reg_map.bb_mrc_reg_map.BB_ldpc_cntl1 */ +#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_LDPC_CNTL1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ldpc_cntl2 */ +#ifndef __LDPC_CNTL2_MACRO__ +#define __LDPC_CNTL2_MACRO__ + +/* macros for field ldpc_llr_scaling1 */ +#define LDPC_CNTL2__LDPC_LLR_SCALING1__SHIFT 0 +#define LDPC_CNTL2__LDPC_LLR_SCALING1__WIDTH 16 +#define LDPC_CNTL2__LDPC_LLR_SCALING1__MASK 0x0000ffffU +#define LDPC_CNTL2__LDPC_LLR_SCALING1__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define LDPC_CNTL2__LDPC_LLR_SCALING1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000ffffU) +#define LDPC_CNTL2__LDPC_LLR_SCALING1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define LDPC_CNTL2__LDPC_LLR_SCALING1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000ffffU))) + +/* macros for field ldpc_latency */ +#define LDPC_CNTL2__LDPC_LATENCY__SHIFT 16 +#define LDPC_CNTL2__LDPC_LATENCY__WIDTH 11 +#define LDPC_CNTL2__LDPC_LATENCY__MASK 0x07ff0000U +#define LDPC_CNTL2__LDPC_LATENCY__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define LDPC_CNTL2__LDPC_LATENCY__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define LDPC_CNTL2__LDPC_LATENCY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define LDPC_CNTL2__LDPC_LATENCY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) +#define LDPC_CNTL2__TYPE u_int32_t +#define LDPC_CNTL2__READ 0x07ffffffU +#define LDPC_CNTL2__WRITE 0x07ffffffU + +#endif /* __LDPC_CNTL2_MACRO__ */ + + +/* macros for bb_reg_map.bb_mrc_reg_map.BB_ldpc_cntl2 */ +#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_LDPC_CNTL2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pilot_spur_mask */ +#ifndef __PILOT_SPUR_MASK_MACRO__ +#define __PILOT_SPUR_MASK_MACRO__ + +/* macros for field cf_pilot_mask_A */ +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__SHIFT 0 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__WIDTH 5 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__MASK 0x0000001fU +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field cf_pilot_mask_idx_A */ +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__SHIFT 5 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__WIDTH 7 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__MASK 0x00000fe0U +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fe0U) >> 5) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000fe0U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fe0U) | (((u_int32_t)(src) <<\ + 5) & 0x00000fe0U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000fe0U))) + +/* macros for field cf_pilot_mask_B */ +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__SHIFT 12 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__WIDTH 5 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__MASK 0x0001f000U +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field cf_pilot_mask_idx_B */ +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__SHIFT 17 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__WIDTH 7 +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__MASK 0x00fe0000U +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fe0000U) >> 17) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00fe0000U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x00fe0000U) +#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00fe0000U))) +#define PILOT_SPUR_MASK__TYPE u_int32_t +#define PILOT_SPUR_MASK__READ 0x00ffffffU +#define PILOT_SPUR_MASK__WRITE 0x00ffffffU + +#endif /* __PILOT_SPUR_MASK_MACRO__ */ + + +/* macros for bb_reg_map.bb_mrc_reg_map.BB_pilot_spur_mask */ +#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_PILOT_SPUR_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chan_spur_mask */ +#ifndef __CHAN_SPUR_MASK_MACRO__ +#define __CHAN_SPUR_MASK_MACRO__ + +/* macros for field cf_chan_mask_A */ +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__SHIFT 0 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__WIDTH 5 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__MASK 0x0000001fU +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field cf_chan_mask_idx_A */ +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__SHIFT 5 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__WIDTH 7 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__MASK 0x00000fe0U +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fe0U) >> 5) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000fe0U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fe0U) | (((u_int32_t)(src) <<\ + 5) & 0x00000fe0U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000fe0U))) + +/* macros for field cf_chan_mask_B */ +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__SHIFT 12 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__WIDTH 5 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__MASK 0x0001f000U +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field cf_chan_mask_idx_B */ +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__SHIFT 17 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__WIDTH 7 +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__MASK 0x00fe0000U +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fe0000U) >> 17) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00fe0000U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x00fe0000U) +#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00fe0000U))) +#define CHAN_SPUR_MASK__TYPE u_int32_t +#define CHAN_SPUR_MASK__READ 0x00ffffffU +#define CHAN_SPUR_MASK__WRITE 0x00ffffffU + +#endif /* __CHAN_SPUR_MASK_MACRO__ */ + + +/* macros for bb_reg_map.bb_mrc_reg_map.BB_chan_spur_mask */ +#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_CHAN_SPUR_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::short_gi_delta_slope */ +#ifndef __SHORT_GI_DELTA_SLOPE_MACRO__ +#define __SHORT_GI_DELTA_SLOPE_MACRO__ + +/* macros for field delta_slope_coef_exp_short_gi */ +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__SHIFT 0 +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__WIDTH 4 +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__MASK 0x0000000fU +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field delta_slope_coef_man_short_gi */ +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__SHIFT 4 +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__WIDTH 15 +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__MASK 0x0007fff0U +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__READ(src) \ + (((u_int32_t)(src)\ + & 0x0007fff0U) >> 4) +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x0007fff0U) +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007fff0U) | (((u_int32_t)(src) <<\ + 4) & 0x0007fff0U) +#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x0007fff0U))) +#define SHORT_GI_DELTA_SLOPE__TYPE u_int32_t +#define SHORT_GI_DELTA_SLOPE__READ 0x0007ffffU +#define SHORT_GI_DELTA_SLOPE__WRITE 0x0007ffffU + +#endif /* __SHORT_GI_DELTA_SLOPE_MACRO__ */ + + +/* macros for bb_reg_map.bb_mrc_reg_map.BB_short_gi_delta_slope */ +#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_SHORT_GI_DELTA_SLOPE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ml_cntl1 */ +#ifndef __ML_CNTL1_MACRO__ +#define __ML_CNTL1_MACRO__ + +/* macros for field cf_ml_2s_weight_table */ +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__SHIFT 0 +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__WIDTH 24 +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__MASK 0x00ffffffU +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00ffffffU +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) + +/* macros for field cf_is_flat_ch_thr_ml */ +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__SHIFT 24 +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__WIDTH 2 +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__MASK 0x03000000U +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__READ(src) \ + (((u_int32_t)(src)\ + & 0x03000000U) >> 24) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x03000000U) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field cf_is_flat_ch_thr_zf */ +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__SHIFT 26 +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__WIDTH 2 +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__MASK 0x0c000000U +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__READ(src) \ + (((u_int32_t)(src)\ + & 0x0c000000U) >> 26) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x0c000000U) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) +#define ML_CNTL1__TYPE u_int32_t +#define ML_CNTL1__READ 0x0fffffffU +#define ML_CNTL1__WRITE 0x0fffffffU + +#endif /* __ML_CNTL1_MACRO__ */ + + +/* macros for bb_reg_map.bb_mrc_reg_map.BB_ml_cntl1 */ +#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_ML_CNTL1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ml_cntl2 */ +#ifndef __ML_CNTL2_MACRO__ +#define __ML_CNTL2_MACRO__ + +/* macros for field cf_ml_3s_weight_table */ +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__SHIFT 0 +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__WIDTH 24 +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__MASK 0x00ffffffU +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00ffffffU +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00ffffffU) +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ffffffU) | ((u_int32_t)(src) &\ + 0x00ffffffU) +#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00ffffffU))) +#define ML_CNTL2__TYPE u_int32_t +#define ML_CNTL2__READ 0x00ffffffU +#define ML_CNTL2__WRITE 0x00ffffffU + +#endif /* __ML_CNTL2_MACRO__ */ + + +/* macros for bb_reg_map.bb_mrc_reg_map.BB_ml_cntl2 */ +#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_ML_CNTL2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tstadc */ +#ifndef __TSTADC_MACRO__ +#define __TSTADC_MACRO__ + +/* macros for field tstadc_out_q */ +#define TSTADC__TSTADC_OUT_Q__SHIFT 0 +#define TSTADC__TSTADC_OUT_Q__WIDTH 10 +#define TSTADC__TSTADC_OUT_Q__MASK 0x000003ffU +#define TSTADC__TSTADC_OUT_Q__READ(src) (u_int32_t)(src) & 0x000003ffU + +/* macros for field tstadc_out_i */ +#define TSTADC__TSTADC_OUT_I__SHIFT 10 +#define TSTADC__TSTADC_OUT_I__WIDTH 10 +#define TSTADC__TSTADC_OUT_I__MASK 0x000ffc00U +#define TSTADC__TSTADC_OUT_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define TSTADC__TYPE u_int32_t +#define TSTADC__READ 0x000fffffU + +#endif /* __TSTADC_MACRO__ */ + + +/* macros for bb_reg_map.bb_mrc_reg_map.BB_tstadc */ +#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_TSTADC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_1 */ +#ifndef __BBB_RX_CTRL_1_MACRO__ +#define __BBB_RX_CTRL_1_MACRO__ + +/* macros for field coarse_tim_threshold_2 */ +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__SHIFT 0 +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__WIDTH 3 +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__MASK 0x00000007U +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field coarse_tim_threshold */ +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__SHIFT 3 +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__WIDTH 5 +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__MASK 0x000000f8U +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f8U) >> 3) +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000000f8U) +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000000f8U) +#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000000f8U))) + +/* macros for field coarse_tim_n_sync */ +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__SHIFT 8 +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__WIDTH 3 +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__MASK 0x00000700U +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field max_bal_long */ +#define BBB_RX_CTRL_1__MAX_BAL_LONG__SHIFT 11 +#define BBB_RX_CTRL_1__MAX_BAL_LONG__WIDTH 5 +#define BBB_RX_CTRL_1__MAX_BAL_LONG__MASK 0x0000f800U +#define BBB_RX_CTRL_1__MAX_BAL_LONG__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f800U) >> 11) +#define BBB_RX_CTRL_1__MAX_BAL_LONG__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x0000f800U) +#define BBB_RX_CTRL_1__MAX_BAL_LONG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0000f800U) +#define BBB_RX_CTRL_1__MAX_BAL_LONG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0000f800U))) + +/* macros for field max_bal_short */ +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__SHIFT 16 +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__WIDTH 5 +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__MASK 0x001f0000U +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define BBB_RX_CTRL_1__MAX_BAL_SHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) + +/* macros for field recon_lms_step */ +#define BBB_RX_CTRL_1__RECON_LMS_STEP__SHIFT 21 +#define BBB_RX_CTRL_1__RECON_LMS_STEP__WIDTH 3 +#define BBB_RX_CTRL_1__RECON_LMS_STEP__MASK 0x00e00000U +#define BBB_RX_CTRL_1__RECON_LMS_STEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00e00000U) >> 21) +#define BBB_RX_CTRL_1__RECON_LMS_STEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00e00000U) +#define BBB_RX_CTRL_1__RECON_LMS_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define BBB_RX_CTRL_1__RECON_LMS_STEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field sb_check_win */ +#define BBB_RX_CTRL_1__SB_CHECK_WIN__SHIFT 24 +#define BBB_RX_CTRL_1__SB_CHECK_WIN__WIDTH 7 +#define BBB_RX_CTRL_1__SB_CHECK_WIN__MASK 0x7f000000U +#define BBB_RX_CTRL_1__SB_CHECK_WIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f000000U) >> 24) +#define BBB_RX_CTRL_1__SB_CHECK_WIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define BBB_RX_CTRL_1__SB_CHECK_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define BBB_RX_CTRL_1__SB_CHECK_WIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) + +/* macros for field en_rx_abort_cck */ +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__SHIFT 31 +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__WIDTH 1 +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__MASK 0x80000000U +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define BBB_RX_CTRL_1__TYPE u_int32_t +#define BBB_RX_CTRL_1__READ 0xffffffffU +#define BBB_RX_CTRL_1__WRITE 0xffffffffU + +#endif /* __BBB_RX_CTRL_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_1 */ +#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_2 */ +#ifndef __BBB_RX_CTRL_2_MACRO__ +#define __BBB_RX_CTRL_2_MACRO__ + +/* macros for field freq_est_n_avg_long */ +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__SHIFT 0 +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__WIDTH 6 +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__MASK 0x0000003fU +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field chan_avg_long */ +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__SHIFT 6 +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__WIDTH 6 +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__MASK 0x00000fc0U +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define BBB_RX_CTRL_2__CHAN_AVG_LONG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field coarse_tim_threshold_3 */ +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__SHIFT 12 +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__WIDTH 5 +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__MASK 0x0001f000U +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field freq_track_update_period */ +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__SHIFT 17 +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__WIDTH 5 +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__MASK 0x003e0000U +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field freq_est_scaling_period */ +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__SHIFT 22 +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__WIDTH 4 +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__MASK 0x03c00000U +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x03c00000U) >> 22) +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x03c00000U) +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x03c00000U) +#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x03c00000U))) + +/* macros for field loop_coef_dpsk_c2_data */ +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__SHIFT 26 +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__WIDTH 6 +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__MASK 0xfc000000U +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__READ(src) \ + (((u_int32_t)(src)\ + & 0xfc000000U) >> 26) +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0xfc000000U) +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((u_int32_t)(src) <<\ + 26) & 0xfc000000U) +#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0xfc000000U))) +#define BBB_RX_CTRL_2__TYPE u_int32_t +#define BBB_RX_CTRL_2__READ 0xffffffffU +#define BBB_RX_CTRL_2__WRITE 0xffffffffU + +#endif /* __BBB_RX_CTRL_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_2 */ +#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_3 */ +#ifndef __BBB_RX_CTRL_3_MACRO__ +#define __BBB_RX_CTRL_3_MACRO__ + +/* macros for field tim_adjust_freq_dpsk */ +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__SHIFT 0 +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__WIDTH 8 +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__MASK 0x000000ffU +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tim_adjust_freq_cck */ +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__SHIFT 8 +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__WIDTH 8 +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__MASK 0x0000ff00U +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field timer_n_sfd */ +#define BBB_RX_CTRL_3__TIMER_N_SFD__SHIFT 16 +#define BBB_RX_CTRL_3__TIMER_N_SFD__WIDTH 8 +#define BBB_RX_CTRL_3__TIMER_N_SFD__MASK 0x00ff0000U +#define BBB_RX_CTRL_3__TIMER_N_SFD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define BBB_RX_CTRL_3__TIMER_N_SFD__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define BBB_RX_CTRL_3__TIMER_N_SFD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define BBB_RX_CTRL_3__TIMER_N_SFD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define BBB_RX_CTRL_3__TYPE u_int32_t +#define BBB_RX_CTRL_3__READ 0x00ffffffU +#define BBB_RX_CTRL_3__WRITE 0x00ffffffU + +#endif /* __BBB_RX_CTRL_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_3 */ +#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_4 */ +#ifndef __BBB_RX_CTRL_4_MACRO__ +#define __BBB_RX_CTRL_4_MACRO__ + +/* macros for field timer_n_sync */ +#define BBB_RX_CTRL_4__TIMER_N_SYNC__SHIFT 0 +#define BBB_RX_CTRL_4__TIMER_N_SYNC__WIDTH 4 +#define BBB_RX_CTRL_4__TIMER_N_SYNC__MASK 0x0000000fU +#define BBB_RX_CTRL_4__TIMER_N_SYNC__READ(src) (u_int32_t)(src) & 0x0000000fU +#define BBB_RX_CTRL_4__TIMER_N_SYNC__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define BBB_RX_CTRL_4__TIMER_N_SYNC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define BBB_RX_CTRL_4__TIMER_N_SYNC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field tim_adjust_timer_exp */ +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__SHIFT 4 +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__WIDTH 12 +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__MASK 0x0000fff0U +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fff0U) >> 4) +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x0000fff0U) +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fff0U) | (((u_int32_t)(src) <<\ + 4) & 0x0000fff0U) +#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x0000fff0U))) + +/* macros for field force_unlocked_clocks */ +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__SHIFT 16 +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__WIDTH 1 +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__MASK 0x00010000U +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field dynamic_pream_sel */ +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__SHIFT 17 +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__WIDTH 1 +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__MASK 0x00020000U +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field short_preamble */ +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__SHIFT 18 +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__WIDTH 1 +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__MASK 0x00040000U +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define BBB_RX_CTRL_4__SHORT_PREAMBLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field freq_est_n_avg_short */ +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__SHIFT 19 +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__WIDTH 6 +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__MASK 0x01f80000U +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f80000U) >> 19) +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x01f80000U) +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f80000U) | (((u_int32_t)(src) <<\ + 19) & 0x01f80000U) +#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x01f80000U))) + +/* macros for field chan_avg_short */ +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__SHIFT 25 +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__WIDTH 6 +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__MASK 0x7e000000U +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x7e000000U) >> 25) +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x7e000000U) +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x7e000000U) +#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x7e000000U))) + +/* macros for field use_mrc_weight */ +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__SHIFT 31 +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__WIDTH 1 +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__MASK 0x80000000U +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define BBB_RX_CTRL_4__TYPE u_int32_t +#define BBB_RX_CTRL_4__READ 0xffffffffU +#define BBB_RX_CTRL_4__WRITE 0xffffffffU + +#endif /* __BBB_RX_CTRL_4_MACRO__ */ + + +/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_4 */ +#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_5 */ +#ifndef __BBB_RX_CTRL_5_MACRO__ +#define __BBB_RX_CTRL_5_MACRO__ + +/* macros for field loop_coef_dpsk_c1_data */ +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__SHIFT 0 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__WIDTH 5 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__MASK 0x0000001fU +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field loop_coef_dpsk_c1_head */ +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__SHIFT 5 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__WIDTH 5 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__MASK 0x000003e0U +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field loop_coef_dpsk_c2_head */ +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__SHIFT 10 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__WIDTH 6 +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__MASK 0x0000fc00U +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fc00U) >> 10) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0000fc00U) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0000fc00U) +#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0000fc00U))) + +/* macros for field loop_coef_cck_c1 */ +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__SHIFT 16 +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__WIDTH 5 +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__MASK 0x001f0000U +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) + +/* macros for field loop_coef_cck_c2 */ +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__SHIFT 21 +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__WIDTH 6 +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__MASK 0x07e00000U +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07e00000U) >> 21) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x07e00000U) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x07e00000U) +#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x07e00000U))) +#define BBB_RX_CTRL_5__TYPE u_int32_t +#define BBB_RX_CTRL_5__READ 0x07ffffffU +#define BBB_RX_CTRL_5__WRITE 0x07ffffffU + +#endif /* __BBB_RX_CTRL_5_MACRO__ */ + + +/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_5 */ +#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_6 */ +#ifndef __BBB_RX_CTRL_6_MACRO__ +#define __BBB_RX_CTRL_6_MACRO__ + +/* macros for field sync_start_delay */ +#define BBB_RX_CTRL_6__SYNC_START_DELAY__SHIFT 0 +#define BBB_RX_CTRL_6__SYNC_START_DELAY__WIDTH 10 +#define BBB_RX_CTRL_6__SYNC_START_DELAY__MASK 0x000003ffU +#define BBB_RX_CTRL_6__SYNC_START_DELAY__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define BBB_RX_CTRL_6__SYNC_START_DELAY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define BBB_RX_CTRL_6__SYNC_START_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define BBB_RX_CTRL_6__SYNC_START_DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field map_1s_to_2s */ +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__SHIFT 10 +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__WIDTH 1 +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__MASK 0x00000400U +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define BBB_RX_CTRL_6__MAP_1S_TO_2S__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field start_iir_delay */ +#define BBB_RX_CTRL_6__START_IIR_DELAY__SHIFT 11 +#define BBB_RX_CTRL_6__START_IIR_DELAY__WIDTH 10 +#define BBB_RX_CTRL_6__START_IIR_DELAY__MASK 0x001ff800U +#define BBB_RX_CTRL_6__START_IIR_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x001ff800U) >> 11) +#define BBB_RX_CTRL_6__START_IIR_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x001ff800U) +#define BBB_RX_CTRL_6__START_IIR_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001ff800U) | (((u_int32_t)(src) <<\ + 11) & 0x001ff800U) +#define BBB_RX_CTRL_6__START_IIR_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x001ff800U))) + +/* macros for field use_mcorr_weight */ +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__SHIFT 21 +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__WIDTH 1 +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__MASK 0x00200000U +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field use_bkpwr_for_center_index */ +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__SHIFT 22 +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__WIDTH 1 +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__MASK 0x00400000U +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field cck_sel_chain_by_eo */ +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__SHIFT 23 +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__WIDTH 1 +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__MASK 0x00800000U +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field force_cck_sel_chain */ +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__SHIFT 24 +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__WIDTH 1 +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__MASK 0x01000000U +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field force_center_index */ +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__SHIFT 25 +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__WIDTH 1 +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__MASK 0x02000000U +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) +#define BBB_RX_CTRL_6__TYPE u_int32_t +#define BBB_RX_CTRL_6__READ 0x03ffffffU +#define BBB_RX_CTRL_6__WRITE 0x03ffffffU + +#endif /* __BBB_RX_CTRL_6_MACRO__ */ + + +/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_6 */ +#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::force_clken_cck */ +#ifndef __FORCE_CLKEN_CCK_MACRO__ +#define __FORCE_CLKEN_CCK_MACRO__ + +/* macros for field force_rx_enable0 */ +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__SHIFT 0 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__MASK 0x00000001U +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field force_rx_enable1 */ +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__SHIFT 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__MASK 0x00000002U +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field force_rx_enable2 */ +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__SHIFT 2 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__MASK 0x00000004U +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field force_rx_enable3 */ +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__SHIFT 3 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__MASK 0x00000008U +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field force_rx_always */ +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__SHIFT 4 +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__MASK 0x00000010U +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field force_txsm_clken */ +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__SHIFT 5 +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__WIDTH 1 +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__MASK 0x00000020U +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) +#define FORCE_CLKEN_CCK__TYPE u_int32_t +#define FORCE_CLKEN_CCK__READ 0x0000003fU +#define FORCE_CLKEN_CCK__WRITE 0x0000003fU + +#endif /* __FORCE_CLKEN_CCK_MACRO__ */ + + +/* macros for bb_reg_map.bb_bbb_reg_map.BB_force_clken_cck */ +#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_FORCE_CLKEN_CCK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::settling_time */ +#ifndef __SETTLING_TIME_MACRO__ +#define __SETTLING_TIME_MACRO__ + +/* macros for field agc_settling */ +#define SETTLING_TIME__AGC_SETTLING__SHIFT 0 +#define SETTLING_TIME__AGC_SETTLING__WIDTH 7 +#define SETTLING_TIME__AGC_SETTLING__MASK 0x0000007fU +#define SETTLING_TIME__AGC_SETTLING__READ(src) (u_int32_t)(src) & 0x0000007fU +#define SETTLING_TIME__AGC_SETTLING__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define SETTLING_TIME__AGC_SETTLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define SETTLING_TIME__AGC_SETTLING__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field switch_settling */ +#define SETTLING_TIME__SWITCH_SETTLING__SHIFT 7 +#define SETTLING_TIME__SWITCH_SETTLING__WIDTH 7 +#define SETTLING_TIME__SWITCH_SETTLING__MASK 0x00003f80U +#define SETTLING_TIME__SWITCH_SETTLING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f80U) >> 7) +#define SETTLING_TIME__SWITCH_SETTLING__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00003f80U) +#define SETTLING_TIME__SWITCH_SETTLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00003f80U) +#define SETTLING_TIME__SWITCH_SETTLING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00003f80U))) + +/* macros for field adcsat_thrl */ +#define SETTLING_TIME__ADCSAT_THRL__SHIFT 14 +#define SETTLING_TIME__ADCSAT_THRL__WIDTH 6 +#define SETTLING_TIME__ADCSAT_THRL__MASK 0x000fc000U +#define SETTLING_TIME__ADCSAT_THRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) +#define SETTLING_TIME__ADCSAT_THRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x000fc000U) +#define SETTLING_TIME__ADCSAT_THRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x000fc000U) +#define SETTLING_TIME__ADCSAT_THRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x000fc000U))) + +/* macros for field adcsat_thrh */ +#define SETTLING_TIME__ADCSAT_THRH__SHIFT 20 +#define SETTLING_TIME__ADCSAT_THRH__WIDTH 6 +#define SETTLING_TIME__ADCSAT_THRH__MASK 0x03f00000U +#define SETTLING_TIME__ADCSAT_THRH__READ(src) \ + (((u_int32_t)(src)\ + & 0x03f00000U) >> 20) +#define SETTLING_TIME__ADCSAT_THRH__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x03f00000U) +#define SETTLING_TIME__ADCSAT_THRH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x03f00000U) +#define SETTLING_TIME__ADCSAT_THRH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x03f00000U))) + +/* macros for field lbreset_advance */ +#define SETTLING_TIME__LBRESET_ADVANCE__SHIFT 26 +#define SETTLING_TIME__LBRESET_ADVANCE__WIDTH 4 +#define SETTLING_TIME__LBRESET_ADVANCE__MASK 0x3c000000U +#define SETTLING_TIME__LBRESET_ADVANCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x3c000000U) >> 26) +#define SETTLING_TIME__LBRESET_ADVANCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x3c000000U) +#define SETTLING_TIME__LBRESET_ADVANCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x3c000000U) +#define SETTLING_TIME__LBRESET_ADVANCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x3c000000U))) +#define SETTLING_TIME__TYPE u_int32_t +#define SETTLING_TIME__READ 0x3fffffffU +#define SETTLING_TIME__WRITE 0x3fffffffU + +#endif /* __SETTLING_TIME_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_settling_time */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_SETTLING_TIME__NUM 1 + +/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b0 */ +#ifndef __GAIN_FORCE_MAX_GAINS_B0_MACRO__ +#define __GAIN_FORCE_MAX_GAINS_B0_MACRO__ + +/* macros for field rf_gain_f_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__SHIFT 0 +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__MASK 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field mb_gain_f_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__SHIFT 8 +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__MASK 0x0000ff00U +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field xatten1_sw_f_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__SHIFT 16 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__MASK 0x00010000U +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field xatten2_sw_f_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__SHIFT 17 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__MASK 0x00020000U +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field xatten1_hyst_margin_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__SHIFT 18 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__MASK 0x01fc0000U +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fc0000U) >> 18) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x01fc0000U))) + +/* macros for field xatten2_hyst_margin_0 */ +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__SHIFT 25 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__MASK 0xfe000000U +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0xfe000000U) >> 25) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfe000000U) | (((u_int32_t)(src) <<\ + 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0xfe000000U))) +#define GAIN_FORCE_MAX_GAINS_B0__TYPE u_int32_t +#define GAIN_FORCE_MAX_GAINS_B0__READ 0xffffffffU +#define GAIN_FORCE_MAX_GAINS_B0__WRITE 0xffffffffU + +#endif /* __GAIN_FORCE_MAX_GAINS_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_gain_force_max_gains_b0 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::gains_min_offsets */ +#ifndef __GAINS_MIN_OFFSETS_MACRO__ +#define __GAINS_MIN_OFFSETS_MACRO__ + +/* macros for field offsetC1 */ +#define GAINS_MIN_OFFSETS__OFFSETC1__SHIFT 0 +#define GAINS_MIN_OFFSETS__OFFSETC1__WIDTH 7 +#define GAINS_MIN_OFFSETS__OFFSETC1__MASK 0x0000007fU +#define GAINS_MIN_OFFSETS__OFFSETC1__READ(src) (u_int32_t)(src) & 0x0000007fU +#define GAINS_MIN_OFFSETS__OFFSETC1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define GAINS_MIN_OFFSETS__OFFSETC1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define GAINS_MIN_OFFSETS__OFFSETC1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field offsetC2 */ +#define GAINS_MIN_OFFSETS__OFFSETC2__SHIFT 7 +#define GAINS_MIN_OFFSETS__OFFSETC2__WIDTH 5 +#define GAINS_MIN_OFFSETS__OFFSETC2__MASK 0x00000f80U +#define GAINS_MIN_OFFSETS__OFFSETC2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f80U) >> 7) +#define GAINS_MIN_OFFSETS__OFFSETC2__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000f80U) +#define GAINS_MIN_OFFSETS__OFFSETC2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00000f80U) +#define GAINS_MIN_OFFSETS__OFFSETC2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000f80U))) + +/* macros for field offsetC3 */ +#define GAINS_MIN_OFFSETS__OFFSETC3__SHIFT 12 +#define GAINS_MIN_OFFSETS__OFFSETC3__WIDTH 5 +#define GAINS_MIN_OFFSETS__OFFSETC3__MASK 0x0001f000U +#define GAINS_MIN_OFFSETS__OFFSETC3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define GAINS_MIN_OFFSETS__OFFSETC3__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define GAINS_MIN_OFFSETS__OFFSETC3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define GAINS_MIN_OFFSETS__OFFSETC3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field gain_force */ +#define GAINS_MIN_OFFSETS__GAIN_FORCE__SHIFT 17 +#define GAINS_MIN_OFFSETS__GAIN_FORCE__WIDTH 1 +#define GAINS_MIN_OFFSETS__GAIN_FORCE__MASK 0x00020000U +#define GAINS_MIN_OFFSETS__GAIN_FORCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define GAINS_MIN_OFFSETS__GAIN_FORCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define GAINS_MIN_OFFSETS__GAIN_FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define GAINS_MIN_OFFSETS__GAIN_FORCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define GAINS_MIN_OFFSETS__GAIN_FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define GAINS_MIN_OFFSETS__GAIN_FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field cf_agc_hist_enable */ +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__SHIFT 18 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__WIDTH 1 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__MASK 0x00040000U +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field cf_agc_hist_gc */ +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__SHIFT 19 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__WIDTH 1 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__MASK 0x00080000U +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field cf_agc_hist_voting */ +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__SHIFT 20 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__WIDTH 1 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__MASK 0x00100000U +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field cf_agc_hist_phy_err */ +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__SHIFT 21 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__WIDTH 1 +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__MASK 0x00200000U +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) +#define GAINS_MIN_OFFSETS__TYPE u_int32_t +#define GAINS_MIN_OFFSETS__READ 0x003fffffU +#define GAINS_MIN_OFFSETS__WRITE 0x003fffffU + +#endif /* __GAINS_MIN_OFFSETS_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_gains_min_offsets */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_GAINS_MIN_OFFSETS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::desired_sigsize */ +#ifndef __DESIRED_SIGSIZE_MACRO__ +#define __DESIRED_SIGSIZE_MACRO__ + +/* macros for field adc_desired_size */ +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__SHIFT 0 +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__WIDTH 8 +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__MASK 0x000000ffU +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field total_desired */ +#define DESIRED_SIGSIZE__TOTAL_DESIRED__SHIFT 20 +#define DESIRED_SIGSIZE__TOTAL_DESIRED__WIDTH 8 +#define DESIRED_SIGSIZE__TOTAL_DESIRED__MASK 0x0ff00000U +#define DESIRED_SIGSIZE__TOTAL_DESIRED__READ(src) \ + (((u_int32_t)(src)\ + & 0x0ff00000U) >> 20) +#define DESIRED_SIGSIZE__TOTAL_DESIRED__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x0ff00000U) +#define DESIRED_SIGSIZE__TOTAL_DESIRED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x0ff00000U) +#define DESIRED_SIGSIZE__TOTAL_DESIRED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x0ff00000U))) + +/* macros for field init_gc_count_max */ +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__SHIFT 28 +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__WIDTH 2 +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__MASK 0x30000000U +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x30000000U) >> 28) +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x30000000U) +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) + +/* macros for field reduce_init_gc_count */ +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__SHIFT 30 +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__WIDTH 1 +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__MASK 0x40000000U +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field ena_init_gain */ +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__SHIFT 31 +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__WIDTH 1 +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__MASK 0x80000000U +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define DESIRED_SIGSIZE__ENA_INIT_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define DESIRED_SIGSIZE__TYPE u_int32_t +#define DESIRED_SIGSIZE__READ 0xfff000ffU +#define DESIRED_SIGSIZE__WRITE 0xfff000ffU + +#endif /* __DESIRED_SIGSIZE_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_desired_sigsize */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_DESIRED_SIGSIZE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::find_signal */ +#ifndef __FIND_SIGNAL_MACRO__ +#define __FIND_SIGNAL_MACRO__ + +/* macros for field relstep */ +#define FIND_SIGNAL__RELSTEP__SHIFT 0 +#define FIND_SIGNAL__RELSTEP__WIDTH 6 +#define FIND_SIGNAL__RELSTEP__MASK 0x0000003fU +#define FIND_SIGNAL__RELSTEP__READ(src) (u_int32_t)(src) & 0x0000003fU +#define FIND_SIGNAL__RELSTEP__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define FIND_SIGNAL__RELSTEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define FIND_SIGNAL__RELSTEP__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field relpwr */ +#define FIND_SIGNAL__RELPWR__SHIFT 6 +#define FIND_SIGNAL__RELPWR__WIDTH 6 +#define FIND_SIGNAL__RELPWR__MASK 0x00000fc0U +#define FIND_SIGNAL__RELPWR__READ(src) (((u_int32_t)(src) & 0x00000fc0U) >> 6) +#define FIND_SIGNAL__RELPWR__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000fc0U) +#define FIND_SIGNAL__RELPWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define FIND_SIGNAL__RELPWR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field firstep */ +#define FIND_SIGNAL__FIRSTEP__SHIFT 12 +#define FIND_SIGNAL__FIRSTEP__WIDTH 6 +#define FIND_SIGNAL__FIRSTEP__MASK 0x0003f000U +#define FIND_SIGNAL__FIRSTEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define FIND_SIGNAL__FIRSTEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define FIND_SIGNAL__FIRSTEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define FIND_SIGNAL__FIRSTEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field firpwr */ +#define FIND_SIGNAL__FIRPWR__SHIFT 18 +#define FIND_SIGNAL__FIRPWR__WIDTH 8 +#define FIND_SIGNAL__FIRPWR__MASK 0x03fc0000U +#define FIND_SIGNAL__FIRPWR__READ(src) (((u_int32_t)(src) & 0x03fc0000U) >> 18) +#define FIND_SIGNAL__FIRPWR__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x03fc0000U) +#define FIND_SIGNAL__FIRPWR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x03fc0000U) +#define FIND_SIGNAL__FIRPWR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x03fc0000U))) + +/* macros for field m1count_max */ +#define FIND_SIGNAL__M1COUNT_MAX__SHIFT 26 +#define FIND_SIGNAL__M1COUNT_MAX__WIDTH 6 +#define FIND_SIGNAL__M1COUNT_MAX__MASK 0xfc000000U +#define FIND_SIGNAL__M1COUNT_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0xfc000000U) >> 26) +#define FIND_SIGNAL__M1COUNT_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0xfc000000U) +#define FIND_SIGNAL__M1COUNT_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((u_int32_t)(src) <<\ + 26) & 0xfc000000U) +#define FIND_SIGNAL__M1COUNT_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0xfc000000U))) +#define FIND_SIGNAL__TYPE u_int32_t +#define FIND_SIGNAL__READ 0xffffffffU +#define FIND_SIGNAL__WRITE 0xffffffffU + +#endif /* __FIND_SIGNAL_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_find_signal */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_FIND_SIGNAL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc */ +#ifndef __AGC_MACRO__ +#define __AGC_MACRO__ + +/* macros for field coarsepwr_const */ +#define AGC__COARSEPWR_CONST__SHIFT 0 +#define AGC__COARSEPWR_CONST__WIDTH 7 +#define AGC__COARSEPWR_CONST__MASK 0x0000007fU +#define AGC__COARSEPWR_CONST__READ(src) (u_int32_t)(src) & 0x0000007fU +#define AGC__COARSEPWR_CONST__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) +#define AGC__COARSEPWR_CONST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define AGC__COARSEPWR_CONST__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field coarse_low */ +#define AGC__COARSE_LOW__SHIFT 7 +#define AGC__COARSE_LOW__WIDTH 8 +#define AGC__COARSE_LOW__MASK 0x00007f80U +#define AGC__COARSE_LOW__READ(src) (((u_int32_t)(src) & 0x00007f80U) >> 7) +#define AGC__COARSE_LOW__WRITE(src) (((u_int32_t)(src) << 7) & 0x00007f80U) +#define AGC__COARSE_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00007f80U) +#define AGC__COARSE_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00007f80U))) + +/* macros for field coarse_high */ +#define AGC__COARSE_HIGH__SHIFT 15 +#define AGC__COARSE_HIGH__WIDTH 7 +#define AGC__COARSE_HIGH__MASK 0x003f8000U +#define AGC__COARSE_HIGH__READ(src) (((u_int32_t)(src) & 0x003f8000U) >> 15) +#define AGC__COARSE_HIGH__WRITE(src) (((u_int32_t)(src) << 15) & 0x003f8000U) +#define AGC__COARSE_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x003f8000U) +#define AGC__COARSE_HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x003f8000U))) + +/* macros for field quick_drop */ +#define AGC__QUICK_DROP__SHIFT 22 +#define AGC__QUICK_DROP__WIDTH 8 +#define AGC__QUICK_DROP__MASK 0x3fc00000U +#define AGC__QUICK_DROP__READ(src) (((u_int32_t)(src) & 0x3fc00000U) >> 22) +#define AGC__QUICK_DROP__WRITE(src) (((u_int32_t)(src) << 22) & 0x3fc00000U) +#define AGC__QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x3fc00000U) +#define AGC__QUICK_DROP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x3fc00000U))) + +/* macros for field rssi_out_select */ +#define AGC__RSSI_OUT_SELECT__SHIFT 30 +#define AGC__RSSI_OUT_SELECT__WIDTH 2 +#define AGC__RSSI_OUT_SELECT__MASK 0xc0000000U +#define AGC__RSSI_OUT_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define AGC__RSSI_OUT_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define AGC__RSSI_OUT_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define AGC__RSSI_OUT_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define AGC__TYPE u_int32_t +#define AGC__READ 0xffffffffU +#define AGC__WRITE 0xffffffffU + +#endif /* __AGC_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_agc */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b0 */ +#ifndef __EXT_ATTEN_SWITCH_CTL_B0_MACRO__ +#define __EXT_ATTEN_SWITCH_CTL_B0_MACRO__ + +/* macros for field xatten1_db_0 */ +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__SHIFT 0 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__MASK 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field xatten2_db_0 */ +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__SHIFT 6 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__MASK 0x00000fc0U +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field xatten1_margin_0 */ +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__SHIFT 12 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__MASK 0x0001f000U +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field xatten2_margin_0 */ +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__SHIFT 17 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__MASK 0x003e0000U +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field xlna_gain_db_0 */ +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__SHIFT 22 +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__MASK 0x07c00000U +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) +#define EXT_ATTEN_SWITCH_CTL_B0__TYPE u_int32_t +#define EXT_ATTEN_SWITCH_CTL_B0__READ 0x07ffffffU +#define EXT_ATTEN_SWITCH_CTL_B0__WRITE 0x07ffffffU + +#endif /* __EXT_ATTEN_SWITCH_CTL_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_ext_atten_switch_ctl_b0 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_b0 */ +#ifndef __CCA_B0_MACRO__ +#define __CCA_B0_MACRO__ + +/* macros for field cf_maxCCApwr_0 */ +#define CCA_B0__CF_MAXCCAPWR_0__SHIFT 0 +#define CCA_B0__CF_MAXCCAPWR_0__WIDTH 9 +#define CCA_B0__CF_MAXCCAPWR_0__MASK 0x000001ffU +#define CCA_B0__CF_MAXCCAPWR_0__READ(src) (u_int32_t)(src) & 0x000001ffU +#define CCA_B0__CF_MAXCCAPWR_0__WRITE(src) ((u_int32_t)(src) & 0x000001ffU) +#define CCA_B0__CF_MAXCCAPWR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_B0__CF_MAXCCAPWR_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field cf_cca_count_maxC */ +#define CCA_B0__CF_CCA_COUNT_MAXC__SHIFT 9 +#define CCA_B0__CF_CCA_COUNT_MAXC__WIDTH 3 +#define CCA_B0__CF_CCA_COUNT_MAXC__MASK 0x00000e00U +#define CCA_B0__CF_CCA_COUNT_MAXC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000e00U) >> 9) +#define CCA_B0__CF_CCA_COUNT_MAXC__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define CCA_B0__CF_CCA_COUNT_MAXC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define CCA_B0__CF_CCA_COUNT_MAXC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field cf_thresh62 */ +#define CCA_B0__CF_THRESH62__SHIFT 12 +#define CCA_B0__CF_THRESH62__WIDTH 8 +#define CCA_B0__CF_THRESH62__MASK 0x000ff000U +#define CCA_B0__CF_THRESH62__READ(src) (((u_int32_t)(src) & 0x000ff000U) >> 12) +#define CCA_B0__CF_THRESH62__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x000ff000U) +#define CCA_B0__CF_THRESH62__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x000ff000U) +#define CCA_B0__CF_THRESH62__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x000ff000U))) + +/* macros for field minCCApwr_0 */ +#define CCA_B0__MINCCAPWR_0__SHIFT 20 +#define CCA_B0__MINCCAPWR_0__WIDTH 9 +#define CCA_B0__MINCCAPWR_0__MASK 0x1ff00000U +#define CCA_B0__MINCCAPWR_0__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20) +#define CCA_B0__TYPE u_int32_t +#define CCA_B0__READ 0x1fffffffU +#define CCA_B0__WRITE 0x1fffffffU + +#endif /* __CCA_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_cca_b0 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCA_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b0 */ +#ifndef __CCA_CTRL_2_B0_MACRO__ +#define __CCA_CTRL_2_B0_MACRO__ + +/* macros for field minCCApwr_thr_0 */ +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__SHIFT 0 +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__WIDTH 9 +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__MASK 0x000001ffU +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field enable_minCCApwr_thr */ +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__SHIFT 9 +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__WIDTH 1 +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__MASK 0x00000200U +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field NF_gain_comp_0 */ +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__SHIFT 10 +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__WIDTH 8 +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__MASK 0x0003fc00U +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fc00U) >> 10) +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0003fc00U) +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0003fc00U) +#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0003fc00U))) + +/* macros for field thresh62_mode */ +#define CCA_CTRL_2_B0__THRESH62_MODE__SHIFT 18 +#define CCA_CTRL_2_B0__THRESH62_MODE__WIDTH 1 +#define CCA_CTRL_2_B0__THRESH62_MODE__MASK 0x00040000U +#define CCA_CTRL_2_B0__THRESH62_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define CCA_CTRL_2_B0__THRESH62_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define CCA_CTRL_2_B0__THRESH62_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define CCA_CTRL_2_B0__THRESH62_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define CCA_CTRL_2_B0__THRESH62_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define CCA_CTRL_2_B0__THRESH62_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) +#define CCA_CTRL_2_B0__TYPE u_int32_t +#define CCA_CTRL_2_B0__READ 0x0007ffffU +#define CCA_CTRL_2_B0__WRITE 0x0007ffffU + +#endif /* __CCA_CTRL_2_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_cca_ctrl_2_b0 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCA_CTRL_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::restart */ +#ifndef __RESTART_MACRO__ +#define __RESTART_MACRO__ + +/* macros for field enable_restart */ +#define RESTART__ENABLE_RESTART__SHIFT 0 +#define RESTART__ENABLE_RESTART__WIDTH 1 +#define RESTART__ENABLE_RESTART__MASK 0x00000001U +#define RESTART__ENABLE_RESTART__READ(src) (u_int32_t)(src) & 0x00000001U +#define RESTART__ENABLE_RESTART__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RESTART__ENABLE_RESTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RESTART__ENABLE_RESTART__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RESTART__ENABLE_RESTART__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RESTART__ENABLE_RESTART__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field restart_lgfirpwr_delta */ +#define RESTART__RESTART_LGFIRPWR_DELTA__SHIFT 1 +#define RESTART__RESTART_LGFIRPWR_DELTA__WIDTH 5 +#define RESTART__RESTART_LGFIRPWR_DELTA__MASK 0x0000003eU +#define RESTART__RESTART_LGFIRPWR_DELTA__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) +#define RESTART__RESTART_LGFIRPWR_DELTA__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000003eU) +#define RESTART__RESTART_LGFIRPWR_DELTA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000003eU) +#define RESTART__RESTART_LGFIRPWR_DELTA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000003eU))) + +/* macros for field enable_pwr_drop_err */ +#define RESTART__ENABLE_PWR_DROP_ERR__SHIFT 6 +#define RESTART__ENABLE_PWR_DROP_ERR__WIDTH 1 +#define RESTART__ENABLE_PWR_DROP_ERR__MASK 0x00000040U +#define RESTART__ENABLE_PWR_DROP_ERR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RESTART__ENABLE_PWR_DROP_ERR__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RESTART__ENABLE_PWR_DROP_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RESTART__ENABLE_PWR_DROP_ERR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RESTART__ENABLE_PWR_DROP_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RESTART__ENABLE_PWR_DROP_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field pwrdrop_lgfirpwr_delta */ +#define RESTART__PWRDROP_LGFIRPWR_DELTA__SHIFT 7 +#define RESTART__PWRDROP_LGFIRPWR_DELTA__WIDTH 5 +#define RESTART__PWRDROP_LGFIRPWR_DELTA__MASK 0x00000f80U +#define RESTART__PWRDROP_LGFIRPWR_DELTA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f80U) >> 7) +#define RESTART__PWRDROP_LGFIRPWR_DELTA__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000f80U) +#define RESTART__PWRDROP_LGFIRPWR_DELTA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00000f80U) +#define RESTART__PWRDROP_LGFIRPWR_DELTA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000f80U))) + +/* macros for field ofdm_cck_rssi_bias */ +#define RESTART__OFDM_CCK_RSSI_BIAS__SHIFT 12 +#define RESTART__OFDM_CCK_RSSI_BIAS__WIDTH 6 +#define RESTART__OFDM_CCK_RSSI_BIAS__MASK 0x0003f000U +#define RESTART__OFDM_CCK_RSSI_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define RESTART__OFDM_CCK_RSSI_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define RESTART__OFDM_CCK_RSSI_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define RESTART__OFDM_CCK_RSSI_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field ant_fast_div_gc_limit */ +#define RESTART__ANT_FAST_DIV_GC_LIMIT__SHIFT 18 +#define RESTART__ANT_FAST_DIV_GC_LIMIT__WIDTH 3 +#define RESTART__ANT_FAST_DIV_GC_LIMIT__MASK 0x001c0000U +#define RESTART__ANT_FAST_DIV_GC_LIMIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x001c0000U) >> 18) +#define RESTART__ANT_FAST_DIV_GC_LIMIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x001c0000U) +#define RESTART__ANT_FAST_DIV_GC_LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define RESTART__ANT_FAST_DIV_GC_LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field enable_ant_fast_div_m2flag */ +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__SHIFT 21 +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__WIDTH 1 +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MASK 0x00200000U +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field weak_rssi_vote_thr */ +#define RESTART__WEAK_RSSI_VOTE_THR__SHIFT 22 +#define RESTART__WEAK_RSSI_VOTE_THR__WIDTH 7 +#define RESTART__WEAK_RSSI_VOTE_THR__MASK 0x1fc00000U +#define RESTART__WEAK_RSSI_VOTE_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x1fc00000U) >> 22) +#define RESTART__WEAK_RSSI_VOTE_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x1fc00000U) +#define RESTART__WEAK_RSSI_VOTE_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x1fc00000U) +#define RESTART__WEAK_RSSI_VOTE_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x1fc00000U))) + +/* macros for field enable_pwr_drop_err_cck */ +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__SHIFT 29 +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__WIDTH 1 +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__MASK 0x20000000U +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RESTART__ENABLE_PWR_DROP_ERR_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field disable_dc_restart */ +#define RESTART__DISABLE_DC_RESTART__SHIFT 30 +#define RESTART__DISABLE_DC_RESTART__WIDTH 1 +#define RESTART__DISABLE_DC_RESTART__MASK 0x40000000U +#define RESTART__DISABLE_DC_RESTART__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RESTART__DISABLE_DC_RESTART__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RESTART__DISABLE_DC_RESTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RESTART__DISABLE_DC_RESTART__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RESTART__DISABLE_DC_RESTART__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RESTART__DISABLE_DC_RESTART__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field restart_mode_bw40 */ +#define RESTART__RESTART_MODE_BW40__SHIFT 31 +#define RESTART__RESTART_MODE_BW40__WIDTH 1 +#define RESTART__RESTART_MODE_BW40__MASK 0x80000000U +#define RESTART__RESTART_MODE_BW40__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RESTART__RESTART_MODE_BW40__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RESTART__RESTART_MODE_BW40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RESTART__RESTART_MODE_BW40__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RESTART__RESTART_MODE_BW40__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RESTART__RESTART_MODE_BW40__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RESTART__TYPE u_int32_t +#define RESTART__READ 0xffffffffU +#define RESTART__WRITE 0xffffffffU + +#endif /* __RESTART_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_restart */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RESTART__NUM 1 + +/* macros for BlueprintGlobalNameSpace::multichain_gain_ctrl */ +#ifndef __MULTICHAIN_GAIN_CTRL_MACRO__ +#define __MULTICHAIN_GAIN_CTRL_MACRO__ + +/* macros for field quickdrop_low */ +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__SHIFT 0 +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__WIDTH 8 +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__MASK 0x000000ffU +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field enable_check_strong_ant */ +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__SHIFT 8 +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__MASK 0x00000100U +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field ant_fast_div_bias */ +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__SHIFT 9 +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WIDTH 6 +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK 0x00007e00U +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007e00U) >> 9) +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00007e00U) +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00007e00U) +#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00007e00U))) + +/* macros for field cap_gain_ratio_SNR */ +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__SHIFT 15 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__WIDTH 6 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__MASK 0x001f8000U +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f8000U) >> 15) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x001f8000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x001f8000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x001f8000U))) + +/* macros for field cap_gain_ratio_ena */ +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__SHIFT 21 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__MASK 0x00200000U +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field cap_gain_ratio_mode */ +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__SHIFT 22 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__MASK 0x00400000U +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field enable_ant_sw_rx_prot */ +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SHIFT 23 +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__MASK 0x00800000U +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field enable_ant_div_lnadiv */ +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__SHIFT 24 +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MASK 0x01000000U +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field ant_div_alt_lnaconf */ +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__SHIFT 25 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WIDTH 2 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK 0x06000000U +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(src) \ + (((u_int32_t)(src)\ + & 0x06000000U) >> 25) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x06000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x06000000U) | (((u_int32_t)(src) <<\ + 25) & 0x06000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x06000000U))) + +/* macros for field ant_div_main_lnaconf */ +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__SHIFT 27 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WIDTH 2 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK 0x18000000U +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(src) \ + (((u_int32_t)(src)\ + & 0x18000000U) >> 27) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x18000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x18000000U) | (((u_int32_t)(src) <<\ + 27) & 0x18000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x18000000U))) + +/* macros for field ant_div_alt_gaintb */ +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__SHIFT 29 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK 0x20000000U +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field ant_div_main_gaintb */ +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__SHIFT 30 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK 0x40000000U +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field ant_div_sw_com_lock */ +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__SHIFT 31 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__WIDTH 1 +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__MASK 0x80000000U +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define MULTICHAIN_GAIN_CTRL__TYPE u_int32_t +#define MULTICHAIN_GAIN_CTRL__READ 0xffffffffU +#define MULTICHAIN_GAIN_CTRL__WRITE 0xffffffffU + +#endif /* __MULTICHAIN_GAIN_CTRL_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_multichain_gain_ctrl */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_MULTICHAIN_GAIN_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_1 */ +#ifndef __EXT_CHAN_PWR_THR_1_MACRO__ +#define __EXT_CHAN_PWR_THR_1_MACRO__ + +/* macros for field thresh62_ext */ +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__SHIFT 0 +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__WIDTH 8 +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__MASK 0x000000ffU +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field ant_div_alt_ant_minGainIdx */ +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__SHIFT 8 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__WIDTH 8 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__MASK 0x0000ff00U +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field ant_div_alt_ant_deltaGainIdx */ +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__SHIFT 16 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__WIDTH 5 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__MASK 0x001f0000U +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) + +/* macros for field ant_div_alt_ant_deltaNF */ +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__SHIFT 21 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__WIDTH 6 +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__MASK 0x07e00000U +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__READ(src) \ + (((u_int32_t)(src)\ + & 0x07e00000U) >> 21) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x07e00000U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x07e00000U) +#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x07e00000U))) +#define EXT_CHAN_PWR_THR_1__TYPE u_int32_t +#define EXT_CHAN_PWR_THR_1__READ 0x07ffffffU +#define EXT_CHAN_PWR_THR_1__WRITE 0x07ffffffU + +#endif /* __EXT_CHAN_PWR_THR_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_ext_chan_pwr_thr_1 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_EXT_CHAN_PWR_THR_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_detect_win */ +#ifndef __EXT_CHAN_DETECT_WIN_MACRO__ +#define __EXT_CHAN_DETECT_WIN_MACRO__ + +/* macros for field det_diff_win_weak */ +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__SHIFT 0 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__WIDTH 4 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__MASK 0x0000000fU +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field det_diff_win_weak_low */ +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__SHIFT 4 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__WIDTH 4 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__MASK 0x000000f0U +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field det_diff_win_weak_cck */ +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__SHIFT 8 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__WIDTH 5 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__MASK 0x00001f00U +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) + +/* macros for field det_20h_count */ +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__SHIFT 13 +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__WIDTH 3 +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__MASK 0x0000e000U +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000e000U) >> 13) +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0000e000U) +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0000e000U))) + +/* macros for field det_ext_blk_count */ +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__SHIFT 16 +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__WIDTH 3 +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__MASK 0x00070000U +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field weak_sig_thr_cck_ext */ +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__SHIFT 19 +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__WIDTH 6 +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__MASK 0x01f80000U +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f80000U) >> 19) +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x01f80000U) +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f80000U) | (((u_int32_t)(src) <<\ + 19) & 0x01f80000U) +#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x01f80000U))) + +/* macros for field det_diff_win_thresh */ +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__SHIFT 25 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__WIDTH 4 +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__MASK 0x1e000000U +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x1e000000U) >> 25) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x1e000000U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x1e000000U) +#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x1e000000U))) +#define EXT_CHAN_DETECT_WIN__TYPE u_int32_t +#define EXT_CHAN_DETECT_WIN__READ 0x1fffffffU +#define EXT_CHAN_DETECT_WIN__WRITE 0x1fffffffU + +#endif /* __EXT_CHAN_DETECT_WIN_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_ext_chan_detect_win */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_EXT_CHAN_DETECT_WIN__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pwr_thr_20_40_det */ +#ifndef __PWR_THR_20_40_DET_MACRO__ +#define __PWR_THR_20_40_DET_MACRO__ + +/* macros for field pwrdiff40_thrstr */ +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__SHIFT 0 +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__WIDTH 5 +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__MASK 0x0000001fU +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field blocker40_max */ +#define PWR_THR_20_40_DET__BLOCKER40_MAX__SHIFT 5 +#define PWR_THR_20_40_DET__BLOCKER40_MAX__WIDTH 6 +#define PWR_THR_20_40_DET__BLOCKER40_MAX__MASK 0x000007e0U +#define PWR_THR_20_40_DET__BLOCKER40_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x000007e0U) >> 5) +#define PWR_THR_20_40_DET__BLOCKER40_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000007e0U) +#define PWR_THR_20_40_DET__BLOCKER40_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000007e0U) +#define PWR_THR_20_40_DET__BLOCKER40_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000007e0U))) + +/* macros for field det40_pwrstep_max */ +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__SHIFT 11 +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__WIDTH 5 +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__MASK 0x0000f800U +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f800U) >> 11) +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x0000f800U) +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0000f800U) +#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0000f800U))) + +/* macros for field det40_thr_snr */ +#define PWR_THR_20_40_DET__DET40_THR_SNR__SHIFT 16 +#define PWR_THR_20_40_DET__DET40_THR_SNR__WIDTH 8 +#define PWR_THR_20_40_DET__DET40_THR_SNR__MASK 0x00ff0000U +#define PWR_THR_20_40_DET__DET40_THR_SNR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define PWR_THR_20_40_DET__DET40_THR_SNR__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define PWR_THR_20_40_DET__DET40_THR_SNR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define PWR_THR_20_40_DET__DET40_THR_SNR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field det40_pri_bias */ +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__SHIFT 24 +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__WIDTH 5 +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__MASK 0x1f000000U +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f000000U) >> 24) +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x1f000000U) +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x1f000000U) +#define PWR_THR_20_40_DET__DET40_PRI_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x1f000000U))) + +/* macros for field pwrstep40_ena */ +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__SHIFT 29 +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__WIDTH 1 +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__MASK 0x20000000U +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define PWR_THR_20_40_DET__PWRSTEP40_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field lowsnr40_ena */ +#define PWR_THR_20_40_DET__LOWSNR40_ENA__SHIFT 30 +#define PWR_THR_20_40_DET__LOWSNR40_ENA__WIDTH 1 +#define PWR_THR_20_40_DET__LOWSNR40_ENA__MASK 0x40000000U +#define PWR_THR_20_40_DET__LOWSNR40_ENA__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define PWR_THR_20_40_DET__LOWSNR40_ENA__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define PWR_THR_20_40_DET__LOWSNR40_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define PWR_THR_20_40_DET__LOWSNR40_ENA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define PWR_THR_20_40_DET__LOWSNR40_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define PWR_THR_20_40_DET__LOWSNR40_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define PWR_THR_20_40_DET__TYPE u_int32_t +#define PWR_THR_20_40_DET__READ 0x7fffffffU +#define PWR_THR_20_40_DET__WRITE 0x7fffffffU + +#endif /* __PWR_THR_20_40_DET_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_pwr_thr_20_40_det */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PWR_THR_20_40_DET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rifs_srch */ +#ifndef __RIFS_SRCH_MACRO__ +#define __RIFS_SRCH_MACRO__ + +/* macros for field init_gain_dB_offset */ +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__SHIFT 8 +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__WIDTH 8 +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__MASK 0x0000ff00U +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field rifs_init_delay */ +#define RIFS_SRCH__RIFS_INIT_DELAY__SHIFT 16 +#define RIFS_SRCH__RIFS_INIT_DELAY__WIDTH 10 +#define RIFS_SRCH__RIFS_INIT_DELAY__MASK 0x03ff0000U +#define RIFS_SRCH__RIFS_INIT_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x03ff0000U) >> 16) +#define RIFS_SRCH__RIFS_INIT_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x03ff0000U) +#define RIFS_SRCH__RIFS_INIT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x03ff0000U) +#define RIFS_SRCH__RIFS_INIT_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x03ff0000U))) + +/* macros for field rifs_disable_pwrlow_gc */ +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__SHIFT 26 +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__WIDTH 1 +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__MASK 0x04000000U +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field rifs_disable_cck_det */ +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__SHIFT 27 +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__WIDTH 1 +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__MASK 0x08000000U +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) +#define RIFS_SRCH__TYPE u_int32_t +#define RIFS_SRCH__READ 0x0fffff00U +#define RIFS_SRCH__WRITE 0x0fffff00U + +#endif /* __RIFS_SRCH_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_rifs_srch */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RIFS_SRCH__NUM 1 + +/* macros for BlueprintGlobalNameSpace::peak_det_ctrl_1 */ +#ifndef __PEAK_DET_CTRL_1_MACRO__ +#define __PEAK_DET_CTRL_1_MACRO__ + +/* macros for field use_oc_gain_table */ +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__SHIFT 0 +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__WIDTH 1 +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__MASK 0x00000001U +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field use_peak_det */ +#define PEAK_DET_CTRL_1__USE_PEAK_DET__SHIFT 1 +#define PEAK_DET_CTRL_1__USE_PEAK_DET__WIDTH 1 +#define PEAK_DET_CTRL_1__USE_PEAK_DET__MASK 0x00000002U +#define PEAK_DET_CTRL_1__USE_PEAK_DET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PEAK_DET_CTRL_1__USE_PEAK_DET__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PEAK_DET_CTRL_1__USE_PEAK_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PEAK_DET_CTRL_1__USE_PEAK_DET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PEAK_DET_CTRL_1__USE_PEAK_DET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PEAK_DET_CTRL_1__USE_PEAK_DET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field peak_det_win_len */ +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__SHIFT 2 +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__WIDTH 6 +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__MASK 0x000000fcU +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000fcU) >> 2) +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x000000fcU) +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000fcU) | (((u_int32_t)(src) <<\ + 2) & 0x000000fcU) +#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x000000fcU))) + +/* macros for field peak_det_tally_thr_low_0 */ +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__SHIFT 8 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__WIDTH 5 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MASK 0x00001f00U +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) + +/* macros for field peak_det_tally_thr_med_0 */ +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__SHIFT 13 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__WIDTH 5 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MASK 0x0003e000U +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003e000U) >> 13) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0003e000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0003e000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0003e000U))) + +/* macros for field peak_det_tally_thr_high_0 */ +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__SHIFT 18 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__WIDTH 5 +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MASK 0x007c0000U +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x007c0000U) >> 18) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x007c0000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x007c0000U) +#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x007c0000U))) + +/* macros for field peak_det_settling */ +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__SHIFT 23 +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__WIDTH 7 +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__MASK 0x3f800000U +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f800000U) >> 23) +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x3f800000U) +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x3f800000U) +#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x3f800000U))) + +/* macros for field pwd_pkdet_during_cal */ +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__SHIFT 30 +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__WIDTH 1 +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__MASK 0x40000000U +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field pwd_pkdet_during_rx */ +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__SHIFT 31 +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__WIDTH 1 +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__MASK 0x80000000U +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define PEAK_DET_CTRL_1__TYPE u_int32_t +#define PEAK_DET_CTRL_1__READ 0xffffffffU +#define PEAK_DET_CTRL_1__WRITE 0xffffffffU + +#endif /* __PEAK_DET_CTRL_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_peak_det_ctrl_1 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PEAK_DET_CTRL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::peak_det_ctrl_2 */ +#ifndef __PEAK_DET_CTRL_2_MACRO__ +#define __PEAK_DET_CTRL_2_MACRO__ + +/* macros for field rfsat_2_add_rfgain_del */ +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__SHIFT 0 +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__WIDTH 10 +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__MASK 0x000003ffU +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field rf_gain_drop_db_low_0 */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__SHIFT 10 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MASK 0x00007c00U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field rf_gain_drop_db_med_0 */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__SHIFT 15 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MASK 0x000f8000U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field rf_gain_drop_db_high_0 */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__SHIFT 20 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MASK 0x01f00000U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field rf_gain_drop_db_non_0 */ +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__SHIFT 25 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__WIDTH 5 +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MASK 0x3e000000U +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) + +/* macros for field enable_rfsat_restart */ +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__SHIFT 30 +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__WIDTH 1 +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MASK 0x40000000U +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define PEAK_DET_CTRL_2__TYPE u_int32_t +#define PEAK_DET_CTRL_2__READ 0x7fffffffU +#define PEAK_DET_CTRL_2__WRITE 0x7fffffffU + +#endif /* __PEAK_DET_CTRL_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_peak_det_ctrl_2 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PEAK_DET_CTRL_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_gain_bounds_1 */ +#ifndef __RX_GAIN_BOUNDS_1_MACRO__ +#define __RX_GAIN_BOUNDS_1_MACRO__ + +/* macros for field rx_max_mb_gain */ +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__SHIFT 0 +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__WIDTH 8 +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__MASK 0x000000ffU +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field rx_max_rf_gain_ref */ +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__SHIFT 8 +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__WIDTH 8 +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__MASK 0x0000ff00U +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field rx_max_rf_gain */ +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__SHIFT 16 +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__WIDTH 8 +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__MASK 0x00ff0000U +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field rx_ocgain_sel_2G */ +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__SHIFT 24 +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__WIDTH 1 +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__MASK 0x01000000U +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field rx_ocgain_sel_5G */ +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__SHIFT 25 +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__WIDTH 1 +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__MASK 0x02000000U +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field rf_mb_gain_delta_max_db */ +#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__SHIFT 26 +#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__WIDTH 6 +#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__MASK 0xfc000000U +#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0xfc000000U) >> 26) +#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0xfc000000U) +#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfc000000U) | (((u_int32_t)(src) <<\ + 26) & 0xfc000000U) +#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0xfc000000U))) +#define RX_GAIN_BOUNDS_1__TYPE u_int32_t +#define RX_GAIN_BOUNDS_1__READ 0xffffffffU +#define RX_GAIN_BOUNDS_1__WRITE 0xffffffffU + +#endif /* __RX_GAIN_BOUNDS_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_rx_gain_bounds_1 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RX_GAIN_BOUNDS_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_gain_bounds_2 */ +#ifndef __RX_GAIN_BOUNDS_2_MACRO__ +#define __RX_GAIN_BOUNDS_2_MACRO__ + +/* macros for field gc_rssi_low_db */ +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__SHIFT 0 +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__WIDTH 8 +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__MASK 0x000000ffU +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field rf_gain_ref_base_addr */ +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__SHIFT 8 +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__WIDTH 8 +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__MASK 0x0000ff00U +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field rf_gain_base_addr */ +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__SHIFT 16 +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__WIDTH 8 +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__MASK 0x00ff0000U +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field rf_gain_div_base_addr */ +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__SHIFT 24 +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__WIDTH 8 +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__MASK 0xff000000U +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define RX_GAIN_BOUNDS_2__TYPE u_int32_t +#define RX_GAIN_BOUNDS_2__READ 0xffffffffU +#define RX_GAIN_BOUNDS_2__WRITE 0xffffffffU + +#endif /* __RX_GAIN_BOUNDS_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_rx_gain_bounds_2 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RX_GAIN_BOUNDS_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::peak_det_cal_ctrl */ +#ifndef __PEAK_DET_CAL_CTRL_MACRO__ +#define __PEAK_DET_CAL_CTRL_MACRO__ + +/* macros for field pkdet_cal_win_thr */ +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__SHIFT 0 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__WIDTH 6 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__MASK 0x0000003fU +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field pkdet_cal_bias */ +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__SHIFT 6 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__WIDTH 6 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__MASK 0x00000fc0U +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field pkdet_cal_meas_time_sel */ +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__SHIFT 12 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__WIDTH 2 +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__MASK 0x00003000U +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003000U) >> 12) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00003000U) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((u_int32_t)(src) <<\ + 12) & 0x00003000U) +#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00003000U))) +#define PEAK_DET_CAL_CTRL__TYPE u_int32_t +#define PEAK_DET_CAL_CTRL__READ 0x00003fffU +#define PEAK_DET_CAL_CTRL__WRITE 0x00003fffU + +#endif /* __PEAK_DET_CAL_CTRL_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_peak_det_cal_ctrl */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PEAK_DET_CAL_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_ctrl */ +#ifndef __AGC_DIG_DC_CTRL_MACRO__ +#define __AGC_DIG_DC_CTRL_MACRO__ + +/* macros for field use_dig_dc */ +#define AGC_DIG_DC_CTRL__USE_DIG_DC__SHIFT 0 +#define AGC_DIG_DC_CTRL__USE_DIG_DC__WIDTH 1 +#define AGC_DIG_DC_CTRL__USE_DIG_DC__MASK 0x00000001U +#define AGC_DIG_DC_CTRL__USE_DIG_DC__READ(src) (u_int32_t)(src) & 0x00000001U +#define AGC_DIG_DC_CTRL__USE_DIG_DC__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define AGC_DIG_DC_CTRL__USE_DIG_DC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define AGC_DIG_DC_CTRL__USE_DIG_DC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define AGC_DIG_DC_CTRL__USE_DIG_DC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define AGC_DIG_DC_CTRL__USE_DIG_DC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dig_dc_scale_bias */ +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__SHIFT 1 +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__WIDTH 3 +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__MASK 0x0000000eU +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field dig_dc_correct_cap */ +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__SHIFT 4 +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__WIDTH 6 +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__MASK 0x000003f0U +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field dig_dc_switch_cck */ +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__SHIFT 10 +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__WIDTH 1 +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__MASK 0x00000400U +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field dig_dc_mixer_sel_mask */ +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__SHIFT 16 +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__WIDTH 16 +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__MASK 0xffff0000U +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define AGC_DIG_DC_CTRL__TYPE u_int32_t +#define AGC_DIG_DC_CTRL__READ 0xffff07ffU +#define AGC_DIG_DC_CTRL__WRITE 0xffff07ffU + +#endif /* __AGC_DIG_DC_CTRL_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_agc_dig_dc_ctrl */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC_DIG_DC_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bt_coex_1 */ +#ifndef __BT_COEX_1_MACRO__ +#define __BT_COEX_1_MACRO__ + +/* macros for field peak_det_tally_thr_low_1 */ +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__SHIFT 0 +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__WIDTH 5 +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MASK 0x0000001fU +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field peak_det_tally_thr_med_1 */ +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__SHIFT 5 +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__WIDTH 5 +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MASK 0x000003e0U +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field peak_det_tally_thr_high_1 */ +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__SHIFT 10 +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__WIDTH 5 +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MASK 0x00007c00U +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field rf_gain_drop_db_low_1 */ +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__SHIFT 15 +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__WIDTH 5 +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MASK 0x000f8000U +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field rf_gain_drop_db_med_1 */ +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__SHIFT 20 +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__WIDTH 5 +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MASK 0x01f00000U +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field rf_gain_drop_db_high_1 */ +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__SHIFT 25 +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__WIDTH 5 +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MASK 0x3e000000U +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) + +/* macros for field bt_tx_disable_NF_cal */ +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__SHIFT 30 +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__WIDTH 1 +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MASK 0x40000000U +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field bt_rx_disable_NF_cal */ +#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__SHIFT 31 +#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__WIDTH 1 +#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__MASK 0x80000000U +#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define BT_COEX_1__TYPE u_int32_t +#define BT_COEX_1__READ 0xffffffffU +#define BT_COEX_1__WRITE 0xffffffffU + +#endif /* __BT_COEX_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_1 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bt_coex_2 */ +#ifndef __BT_COEX_2_MACRO__ +#define __BT_COEX_2_MACRO__ + +/* macros for field peak_det_tally_thr_low_2 */ +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__SHIFT 0 +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__WIDTH 5 +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MASK 0x0000001fU +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field peak_det_tally_thr_med_2 */ +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__SHIFT 5 +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__WIDTH 5 +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MASK 0x000003e0U +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field peak_det_tally_thr_high_2 */ +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__SHIFT 10 +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__WIDTH 5 +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MASK 0x00007c00U +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field rf_gain_drop_db_low_2 */ +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__SHIFT 15 +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__WIDTH 5 +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MASK 0x000f8000U +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field rf_gain_drop_db_med_2 */ +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__SHIFT 20 +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__WIDTH 5 +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MASK 0x01f00000U +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field rf_gain_drop_db_high_2 */ +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__SHIFT 25 +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__WIDTH 5 +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MASK 0x3e000000U +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) + +/* macros for field rfsat_rx_rx */ +#define BT_COEX_2__RFSAT_RX_RX__SHIFT 30 +#define BT_COEX_2__RFSAT_RX_RX__WIDTH 2 +#define BT_COEX_2__RFSAT_RX_RX__MASK 0xc0000000U +#define BT_COEX_2__RFSAT_RX_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define BT_COEX_2__RFSAT_RX_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define BT_COEX_2__RFSAT_RX_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define BT_COEX_2__RFSAT_RX_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define BT_COEX_2__TYPE u_int32_t +#define BT_COEX_2__READ 0xffffffffU +#define BT_COEX_2__WRITE 0xffffffffU + +#endif /* __BT_COEX_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_2 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bt_coex_3 */ +#ifndef __BT_COEX_3_MACRO__ +#define __BT_COEX_3_MACRO__ + +/* macros for field rfsat_bt_srch_srch */ +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__SHIFT 0 +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MASK 0x00000003U +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__READ(src) (u_int32_t)(src) & 0x00000003U +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field rfsat_bt_rx_srch */ +#define BT_COEX_3__RFSAT_BT_RX_SRCH__SHIFT 2 +#define BT_COEX_3__RFSAT_BT_RX_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_BT_RX_SRCH__MASK 0x0000000cU +#define BT_COEX_3__RFSAT_BT_RX_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define BT_COEX_3__RFSAT_BT_RX_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define BT_COEX_3__RFSAT_BT_RX_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define BT_COEX_3__RFSAT_BT_RX_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field rfsat_bt_srch_rx */ +#define BT_COEX_3__RFSAT_BT_SRCH_RX__SHIFT 4 +#define BT_COEX_3__RFSAT_BT_SRCH_RX__WIDTH 2 +#define BT_COEX_3__RFSAT_BT_SRCH_RX__MASK 0x00000030U +#define BT_COEX_3__RFSAT_BT_SRCH_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define BT_COEX_3__RFSAT_BT_SRCH_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define BT_COEX_3__RFSAT_BT_SRCH_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define BT_COEX_3__RFSAT_BT_SRCH_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field rfsat_wlan_srch_srch */ +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__SHIFT 6 +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MASK 0x000000c0U +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field rfsat_wlan_rx_srch */ +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__SHIFT 8 +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MASK 0x00000300U +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field rfsat_wlan_srch_rx */ +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__SHIFT 10 +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__WIDTH 2 +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MASK 0x00000c00U +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) + +/* macros for field rfsat_eq_srch_srch */ +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__SHIFT 12 +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MASK 0x00003000U +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003000U) >> 12) +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00003000U) +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((u_int32_t)(src) <<\ + 12) & 0x00003000U) +#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00003000U))) + +/* macros for field rfsat_eq_rx_srch */ +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__SHIFT 14 +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__WIDTH 2 +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__MASK 0x0000c000U +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define BT_COEX_3__RFSAT_EQ_RX_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field rfsat_eq_srch_rx */ +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__SHIFT 16 +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__WIDTH 2 +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__MASK 0x00030000U +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00030000U) >> 16) +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00030000U) +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((u_int32_t)(src) <<\ + 16) & 0x00030000U) +#define BT_COEX_3__RFSAT_EQ_SRCH_RX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00030000U))) + +/* macros for field rf_gain_drop_db_non_1 */ +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__SHIFT 18 +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__WIDTH 5 +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MASK 0x007c0000U +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x007c0000U) >> 18) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x007c0000U) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x007c0000U) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x007c0000U))) + +/* macros for field rf_gain_drop_db_non_2 */ +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__SHIFT 23 +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__WIDTH 5 +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MASK 0x0f800000U +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f800000U) >> 23) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x0f800000U) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x0f800000U) +#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x0f800000U))) + +/* macros for field bt_rx_firpwr_incr */ +#define BT_COEX_3__BT_RX_FIRPWR_INCR__SHIFT 28 +#define BT_COEX_3__BT_RX_FIRPWR_INCR__WIDTH 4 +#define BT_COEX_3__BT_RX_FIRPWR_INCR__MASK 0xf0000000U +#define BT_COEX_3__BT_RX_FIRPWR_INCR__READ(src) \ + (((u_int32_t)(src)\ + & 0xf0000000U) >> 28) +#define BT_COEX_3__BT_RX_FIRPWR_INCR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0xf0000000U) +#define BT_COEX_3__BT_RX_FIRPWR_INCR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((u_int32_t)(src) <<\ + 28) & 0xf0000000U) +#define BT_COEX_3__BT_RX_FIRPWR_INCR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0xf0000000U))) +#define BT_COEX_3__TYPE u_int32_t +#define BT_COEX_3__READ 0xffffffffU +#define BT_COEX_3__WRITE 0xffffffffU + +#endif /* __BT_COEX_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_3 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bt_coex_4 */ +#ifndef __BT_COEX_4_MACRO__ +#define __BT_COEX_4_MACRO__ + +/* macros for field rfgain_eqv_lna_0 */ +#define BT_COEX_4__RFGAIN_EQV_LNA_0__SHIFT 0 +#define BT_COEX_4__RFGAIN_EQV_LNA_0__WIDTH 8 +#define BT_COEX_4__RFGAIN_EQV_LNA_0__MASK 0x000000ffU +#define BT_COEX_4__RFGAIN_EQV_LNA_0__READ(src) (u_int32_t)(src) & 0x000000ffU +#define BT_COEX_4__RFGAIN_EQV_LNA_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define BT_COEX_4__RFGAIN_EQV_LNA_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define BT_COEX_4__RFGAIN_EQV_LNA_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field rfgain_eqv_lna_1 */ +#define BT_COEX_4__RFGAIN_EQV_LNA_1__SHIFT 8 +#define BT_COEX_4__RFGAIN_EQV_LNA_1__WIDTH 8 +#define BT_COEX_4__RFGAIN_EQV_LNA_1__MASK 0x0000ff00U +#define BT_COEX_4__RFGAIN_EQV_LNA_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define BT_COEX_4__RFGAIN_EQV_LNA_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define BT_COEX_4__RFGAIN_EQV_LNA_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define BT_COEX_4__RFGAIN_EQV_LNA_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field rfgain_eqv_lna_2 */ +#define BT_COEX_4__RFGAIN_EQV_LNA_2__SHIFT 16 +#define BT_COEX_4__RFGAIN_EQV_LNA_2__WIDTH 8 +#define BT_COEX_4__RFGAIN_EQV_LNA_2__MASK 0x00ff0000U +#define BT_COEX_4__RFGAIN_EQV_LNA_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define BT_COEX_4__RFGAIN_EQV_LNA_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define BT_COEX_4__RFGAIN_EQV_LNA_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define BT_COEX_4__RFGAIN_EQV_LNA_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field rfgain_eqv_lna_3 */ +#define BT_COEX_4__RFGAIN_EQV_LNA_3__SHIFT 24 +#define BT_COEX_4__RFGAIN_EQV_LNA_3__WIDTH 8 +#define BT_COEX_4__RFGAIN_EQV_LNA_3__MASK 0xff000000U +#define BT_COEX_4__RFGAIN_EQV_LNA_3__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define BT_COEX_4__RFGAIN_EQV_LNA_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define BT_COEX_4__RFGAIN_EQV_LNA_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define BT_COEX_4__RFGAIN_EQV_LNA_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define BT_COEX_4__TYPE u_int32_t +#define BT_COEX_4__READ 0xffffffffU +#define BT_COEX_4__WRITE 0xffffffffU + +#endif /* __BT_COEX_4_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_4 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bt_coex_5 */ +#ifndef __BT_COEX_5_MACRO__ +#define __BT_COEX_5_MACRO__ + +/* macros for field rfgain_eqv_lna_4 */ +#define BT_COEX_5__RFGAIN_EQV_LNA_4__SHIFT 0 +#define BT_COEX_5__RFGAIN_EQV_LNA_4__WIDTH 8 +#define BT_COEX_5__RFGAIN_EQV_LNA_4__MASK 0x000000ffU +#define BT_COEX_5__RFGAIN_EQV_LNA_4__READ(src) (u_int32_t)(src) & 0x000000ffU +#define BT_COEX_5__RFGAIN_EQV_LNA_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define BT_COEX_5__RFGAIN_EQV_LNA_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define BT_COEX_5__RFGAIN_EQV_LNA_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field rfgain_eqv_lna_5 */ +#define BT_COEX_5__RFGAIN_EQV_LNA_5__SHIFT 8 +#define BT_COEX_5__RFGAIN_EQV_LNA_5__WIDTH 8 +#define BT_COEX_5__RFGAIN_EQV_LNA_5__MASK 0x0000ff00U +#define BT_COEX_5__RFGAIN_EQV_LNA_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define BT_COEX_5__RFGAIN_EQV_LNA_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define BT_COEX_5__RFGAIN_EQV_LNA_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define BT_COEX_5__RFGAIN_EQV_LNA_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field rfgain_eqv_lna_6 */ +#define BT_COEX_5__RFGAIN_EQV_LNA_6__SHIFT 16 +#define BT_COEX_5__RFGAIN_EQV_LNA_6__WIDTH 8 +#define BT_COEX_5__RFGAIN_EQV_LNA_6__MASK 0x00ff0000U +#define BT_COEX_5__RFGAIN_EQV_LNA_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define BT_COEX_5__RFGAIN_EQV_LNA_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define BT_COEX_5__RFGAIN_EQV_LNA_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define BT_COEX_5__RFGAIN_EQV_LNA_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field rfgain_eqv_lna_7 */ +#define BT_COEX_5__RFGAIN_EQV_LNA_7__SHIFT 24 +#define BT_COEX_5__RFGAIN_EQV_LNA_7__WIDTH 8 +#define BT_COEX_5__RFGAIN_EQV_LNA_7__MASK 0xff000000U +#define BT_COEX_5__RFGAIN_EQV_LNA_7__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define BT_COEX_5__RFGAIN_EQV_LNA_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define BT_COEX_5__RFGAIN_EQV_LNA_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define BT_COEX_5__RFGAIN_EQV_LNA_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define BT_COEX_5__TYPE u_int32_t +#define BT_COEX_5__READ 0xffffffffU +#define BT_COEX_5__WRITE 0xffffffffU + +#endif /* __BT_COEX_5_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_5 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::redpwr_ctrl_1 */ +#ifndef __REDPWR_CTRL_1_MACRO__ +#define __REDPWR_CTRL_1_MACRO__ + +/* macros for field redpwr_mode */ +#define REDPWR_CTRL_1__REDPWR_MODE__SHIFT 0 +#define REDPWR_CTRL_1__REDPWR_MODE__WIDTH 2 +#define REDPWR_CTRL_1__REDPWR_MODE__MASK 0x00000003U +#define REDPWR_CTRL_1__REDPWR_MODE__READ(src) (u_int32_t)(src) & 0x00000003U +#define REDPWR_CTRL_1__REDPWR_MODE__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define REDPWR_CTRL_1__REDPWR_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define REDPWR_CTRL_1__REDPWR_MODE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field redpwr_mode_clr */ +#define REDPWR_CTRL_1__REDPWR_MODE_CLR__SHIFT 2 +#define REDPWR_CTRL_1__REDPWR_MODE_CLR__WIDTH 1 +#define REDPWR_CTRL_1__REDPWR_MODE_CLR__MASK 0x00000004U +#define REDPWR_CTRL_1__REDPWR_MODE_CLR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define REDPWR_CTRL_1__REDPWR_MODE_CLR__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define REDPWR_CTRL_1__REDPWR_MODE_CLR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define REDPWR_CTRL_1__REDPWR_MODE_CLR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define REDPWR_CTRL_1__REDPWR_MODE_CLR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define REDPWR_CTRL_1__REDPWR_MODE_CLR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field redpwr_mode_set */ +#define REDPWR_CTRL_1__REDPWR_MODE_SET__SHIFT 3 +#define REDPWR_CTRL_1__REDPWR_MODE_SET__WIDTH 1 +#define REDPWR_CTRL_1__REDPWR_MODE_SET__MASK 0x00000008U +#define REDPWR_CTRL_1__REDPWR_MODE_SET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define REDPWR_CTRL_1__REDPWR_MODE_SET__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define REDPWR_CTRL_1__REDPWR_MODE_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define REDPWR_CTRL_1__REDPWR_MODE_SET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define REDPWR_CTRL_1__REDPWR_MODE_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define REDPWR_CTRL_1__REDPWR_MODE_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field gain_corr_db2 */ +#define REDPWR_CTRL_1__GAIN_CORR_DB2__SHIFT 4 +#define REDPWR_CTRL_1__GAIN_CORR_DB2__WIDTH 5 +#define REDPWR_CTRL_1__GAIN_CORR_DB2__MASK 0x000001f0U +#define REDPWR_CTRL_1__GAIN_CORR_DB2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001f0U) >> 4) +#define REDPWR_CTRL_1__GAIN_CORR_DB2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000001f0U) +#define REDPWR_CTRL_1__GAIN_CORR_DB2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000001f0U) +#define REDPWR_CTRL_1__GAIN_CORR_DB2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000001f0U))) + +/* macros for field scfir_adj_gain */ +#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__SHIFT 9 +#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__WIDTH 4 +#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__MASK 0x00001e00U +#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001e00U) >> 9) +#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00001e00U) +#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00001e00U) +#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00001e00U))) + +/* macros for field quickdrop_rf */ +#define REDPWR_CTRL_1__QUICKDROP_RF__SHIFT 13 +#define REDPWR_CTRL_1__QUICKDROP_RF__WIDTH 5 +#define REDPWR_CTRL_1__QUICKDROP_RF__MASK 0x0003e000U +#define REDPWR_CTRL_1__QUICKDROP_RF__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003e000U) >> 13) +#define REDPWR_CTRL_1__QUICKDROP_RF__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0003e000U) +#define REDPWR_CTRL_1__QUICKDROP_RF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0003e000U) +#define REDPWR_CTRL_1__QUICKDROP_RF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0003e000U))) + +/* macros for field bypass_fir_f */ +#define REDPWR_CTRL_1__BYPASS_FIR_F__SHIFT 18 +#define REDPWR_CTRL_1__BYPASS_FIR_F__WIDTH 1 +#define REDPWR_CTRL_1__BYPASS_FIR_F__MASK 0x00040000U +#define REDPWR_CTRL_1__BYPASS_FIR_F__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define REDPWR_CTRL_1__BYPASS_FIR_F__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define REDPWR_CTRL_1__BYPASS_FIR_F__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define REDPWR_CTRL_1__BYPASS_FIR_F__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define REDPWR_CTRL_1__BYPASS_FIR_F__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define REDPWR_CTRL_1__BYPASS_FIR_F__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field adc_half_ref_f */ +#define REDPWR_CTRL_1__ADC_HALF_REF_F__SHIFT 19 +#define REDPWR_CTRL_1__ADC_HALF_REF_F__WIDTH 1 +#define REDPWR_CTRL_1__ADC_HALF_REF_F__MASK 0x00080000U +#define REDPWR_CTRL_1__ADC_HALF_REF_F__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define REDPWR_CTRL_1__ADC_HALF_REF_F__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define REDPWR_CTRL_1__ADC_HALF_REF_F__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define REDPWR_CTRL_1__ADC_HALF_REF_F__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define REDPWR_CTRL_1__ADC_HALF_REF_F__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define REDPWR_CTRL_1__ADC_HALF_REF_F__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) +#define REDPWR_CTRL_1__TYPE u_int32_t +#define REDPWR_CTRL_1__READ 0x000fffffU +#define REDPWR_CTRL_1__WRITE 0x000fffffU + +#endif /* __REDPWR_CTRL_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_redpwr_ctrl_1 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_REDPWR_CTRL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::redpwr_ctrl_2 */ +#ifndef __REDPWR_CTRL_2_MACRO__ +#define __REDPWR_CTRL_2_MACRO__ + +/* macros for field sc01_sw_index */ +#define REDPWR_CTRL_2__SC01_SW_INDEX__SHIFT 0 +#define REDPWR_CTRL_2__SC01_SW_INDEX__WIDTH 7 +#define REDPWR_CTRL_2__SC01_SW_INDEX__MASK 0x0000007fU +#define REDPWR_CTRL_2__SC01_SW_INDEX__READ(src) (u_int32_t)(src) & 0x0000007fU +#define REDPWR_CTRL_2__SC01_SW_INDEX__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define REDPWR_CTRL_2__SC01_SW_INDEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define REDPWR_CTRL_2__SC01_SW_INDEX__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field sc10_sw_index */ +#define REDPWR_CTRL_2__SC10_SW_INDEX__SHIFT 7 +#define REDPWR_CTRL_2__SC10_SW_INDEX__WIDTH 7 +#define REDPWR_CTRL_2__SC10_SW_INDEX__MASK 0x00003f80U +#define REDPWR_CTRL_2__SC10_SW_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f80U) >> 7) +#define REDPWR_CTRL_2__SC10_SW_INDEX__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00003f80U) +#define REDPWR_CTRL_2__SC10_SW_INDEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00003f80U) +#define REDPWR_CTRL_2__SC10_SW_INDEX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00003f80U))) + +/* macros for field last_sc0_index */ +#define REDPWR_CTRL_2__LAST_SC0_INDEX__SHIFT 14 +#define REDPWR_CTRL_2__LAST_SC0_INDEX__WIDTH 7 +#define REDPWR_CTRL_2__LAST_SC0_INDEX__MASK 0x001fc000U +#define REDPWR_CTRL_2__LAST_SC0_INDEX__READ(src) \ + (((u_int32_t)(src)\ + & 0x001fc000U) >> 14) +#define REDPWR_CTRL_2__LAST_SC0_INDEX__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x001fc000U) +#define REDPWR_CTRL_2__LAST_SC0_INDEX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x001fc000U) +#define REDPWR_CTRL_2__LAST_SC0_INDEX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x001fc000U))) +#define REDPWR_CTRL_2__TYPE u_int32_t +#define REDPWR_CTRL_2__READ 0x001fffffU +#define REDPWR_CTRL_2__WRITE 0x001fffffU + +#endif /* __REDPWR_CTRL_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_redpwr_ctrl_2 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_REDPWR_CTRL_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rssi_b0 */ +#ifndef __RSSI_B0_MACRO__ +#define __RSSI_B0_MACRO__ + +/* macros for field rssi_0 */ +#define RSSI_B0__RSSI_0__SHIFT 0 +#define RSSI_B0__RSSI_0__WIDTH 8 +#define RSSI_B0__RSSI_0__MASK 0x000000ffU +#define RSSI_B0__RSSI_0__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field rssi_ext_0 */ +#define RSSI_B0__RSSI_EXT_0__SHIFT 8 +#define RSSI_B0__RSSI_EXT_0__WIDTH 8 +#define RSSI_B0__RSSI_EXT_0__MASK 0x0000ff00U +#define RSSI_B0__RSSI_EXT_0__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define RSSI_B0__TYPE u_int32_t +#define RSSI_B0__READ 0x0000ffffU + +#endif /* __RSSI_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_rssi_b0 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RSSI_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_est_cck_report_b0 */ +#ifndef __SPUR_EST_CCK_REPORT_B0_MACRO__ +#define __SPUR_EST_CCK_REPORT_B0_MACRO__ + +/* macros for field spur_est_sd_i_0_cck */ +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__SHIFT 0 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__MASK 0x000000ffU +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field spur_est_sd_q_0_cck */ +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__SHIFT 8 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__MASK 0x0000ff00U +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field spur_est_i_0_cck */ +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__SHIFT 16 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__MASK 0x00ff0000U +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) + +/* macros for field spur_est_q_0_cck */ +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__SHIFT 24 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__MASK 0xff000000U +#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define SPUR_EST_CCK_REPORT_B0__TYPE u_int32_t +#define SPUR_EST_CCK_REPORT_B0__READ 0xffffffffU + +#endif /* __SPUR_EST_CCK_REPORT_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_spur_est_cck_report_b0 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_SPUR_EST_CCK_REPORT_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b0 */ +#ifndef __AGC_DIG_DC_STATUS_I_B0_MACRO__ +#define __AGC_DIG_DC_STATUS_I_B0_MACRO__ + +/* macros for field dig_dc_C1_res_i_0 */ +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__SHIFT 0 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_i_0 */ +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__SHIFT 9 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_i_0 */ +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__SHIFT 18 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_I_B0__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_I_B0__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_I_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_agc_dig_dc_status_i_b0 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b0 */ +#ifndef __AGC_DIG_DC_STATUS_Q_B0_MACRO__ +#define __AGC_DIG_DC_STATUS_Q_B0_MACRO__ + +/* macros for field dig_dc_C1_res_q_0 */ +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__SHIFT 0 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_q_0 */ +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__SHIFT 9 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_q_0 */ +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__SHIFT 18 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_Q_B0__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_Q_B0__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_Q_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_agc_dig_dc_status_q_b0 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dc_cal_status_b0 */ +#ifndef __DC_CAL_STATUS_B0_MACRO__ +#define __DC_CAL_STATUS_B0_MACRO__ + +/* macros for field offsetC1I_0 */ +#define DC_CAL_STATUS_B0__OFFSETC1I_0__SHIFT 0 +#define DC_CAL_STATUS_B0__OFFSETC1I_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC1I_0__MASK 0x0000001fU +#define DC_CAL_STATUS_B0__OFFSETC1I_0__READ(src) (u_int32_t)(src) & 0x0000001fU + +/* macros for field offsetC1Q_0 */ +#define DC_CAL_STATUS_B0__OFFSETC1Q_0__SHIFT 5 +#define DC_CAL_STATUS_B0__OFFSETC1Q_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC1Q_0__MASK 0x000003e0U +#define DC_CAL_STATUS_B0__OFFSETC1Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) + +/* macros for field offsetC2I_0 */ +#define DC_CAL_STATUS_B0__OFFSETC2I_0__SHIFT 10 +#define DC_CAL_STATUS_B0__OFFSETC2I_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC2I_0__MASK 0x00007c00U +#define DC_CAL_STATUS_B0__OFFSETC2I_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) + +/* macros for field offsetC2Q_0 */ +#define DC_CAL_STATUS_B0__OFFSETC2Q_0__SHIFT 15 +#define DC_CAL_STATUS_B0__OFFSETC2Q_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC2Q_0__MASK 0x000f8000U +#define DC_CAL_STATUS_B0__OFFSETC2Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) + +/* macros for field offsetC3I_0 */ +#define DC_CAL_STATUS_B0__OFFSETC3I_0__SHIFT 20 +#define DC_CAL_STATUS_B0__OFFSETC3I_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC3I_0__MASK 0x01f00000U +#define DC_CAL_STATUS_B0__OFFSETC3I_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) + +/* macros for field offsetC3Q_0 */ +#define DC_CAL_STATUS_B0__OFFSETC3Q_0__SHIFT 25 +#define DC_CAL_STATUS_B0__OFFSETC3Q_0__WIDTH 5 +#define DC_CAL_STATUS_B0__OFFSETC3Q_0__MASK 0x3e000000U +#define DC_CAL_STATUS_B0__OFFSETC3Q_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define DC_CAL_STATUS_B0__TYPE u_int32_t +#define DC_CAL_STATUS_B0__READ 0x3fffffffU + +#endif /* __DC_CAL_STATUS_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_dc_cal_status_b0 */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_DC_CAL_STATUS_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_sig_detect */ +#ifndef __BBB_SIG_DETECT_MACRO__ +#define __BBB_SIG_DETECT_MACRO__ + +/* macros for field weak_sig_thr_cck */ +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__SHIFT 0 +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__WIDTH 6 +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__MASK 0x0000003fU +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field ant_switch_time */ +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__SHIFT 6 +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__WIDTH 7 +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__MASK 0x00001fc0U +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001fc0U) >> 6) +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00001fc0U) +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00001fc0U) +#define BBB_SIG_DETECT__ANT_SWITCH_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00001fc0U))) + +/* macros for field enable_ant_fast_div */ +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SHIFT 13 +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__WIDTH 1 +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MASK 0x00002000U +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field lb_alpha_128_cck */ +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__SHIFT 14 +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__WIDTH 1 +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__MASK 0x00004000U +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field lb_rx_enable_cck */ +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__SHIFT 15 +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__WIDTH 1 +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__MASK 0x00008000U +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field cyc32_coarse_dc_est_cck */ +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__SHIFT 16 +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__WIDTH 1 +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__MASK 0x00010000U +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field cyc64_coarse_dc_est_cck */ +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__SHIFT 17 +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__WIDTH 1 +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__MASK 0x00020000U +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field enable_coarse_dc_cck */ +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__SHIFT 18 +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__WIDTH 1 +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__MASK 0x00040000U +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field cyc256_fine_dc_est_cck */ +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__SHIFT 19 +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__WIDTH 1 +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__MASK 0x00080000U +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field enable_fine_dc_cck */ +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__SHIFT 20 +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__WIDTH 1 +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__MASK 0x00100000U +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field delay_start_sync_cck */ +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__SHIFT 21 +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__WIDTH 1 +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__MASK 0x00200000U +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field use_dc_est_during_srch */ +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__SHIFT 22 +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__WIDTH 1 +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__MASK 0x00400000U +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field bbb_mrc_off_no_swap */ +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__SHIFT 23 +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__WIDTH 1 +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MASK 0x00800000U +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field swap_default_chain_cck */ +#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__SHIFT 24 +#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__WIDTH 1 +#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__MASK 0x01000000U +#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field enable_barker_two_phase */ +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__SHIFT 31 +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__WIDTH 1 +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__MASK 0x80000000U +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define BBB_SIG_DETECT__TYPE u_int32_t +#define BBB_SIG_DETECT__READ 0x81ffffffU +#define BBB_SIG_DETECT__WRITE 0x81ffffffU + +#endif /* __BBB_SIG_DETECT_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_bbb_sig_detect */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BBB_SIG_DETECT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_dagc_ctrl */ +#ifndef __BBB_DAGC_CTRL_MACRO__ +#define __BBB_DAGC_CTRL_MACRO__ + +/* macros for field enable_dagc_cck */ +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__SHIFT 0 +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__WIDTH 1 +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__MASK 0x00000001U +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dagc_target_pwr_cck */ +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__SHIFT 1 +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__WIDTH 8 +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__MASK 0x000001feU +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000001feU) +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((u_int32_t)(src) <<\ + 1) & 0x000001feU) +#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000001feU))) + +/* macros for field enable_barker_rssi_thr */ +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__SHIFT 9 +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__WIDTH 1 +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__MASK 0x00000200U +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field barker_rssi_thr */ +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__SHIFT 10 +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__WIDTH 7 +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__MASK 0x0001fc00U +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fc00U) >> 10) +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0001fc00U) +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0001fc00U) +#define BBB_DAGC_CTRL__BARKER_RSSI_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0001fc00U))) + +/* macros for field enable_firstep_sel */ +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__SHIFT 17 +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__WIDTH 1 +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__MASK 0x00020000U +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field firstep_2 */ +#define BBB_DAGC_CTRL__FIRSTEP_2__SHIFT 18 +#define BBB_DAGC_CTRL__FIRSTEP_2__WIDTH 6 +#define BBB_DAGC_CTRL__FIRSTEP_2__MASK 0x00fc0000U +#define BBB_DAGC_CTRL__FIRSTEP_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define BBB_DAGC_CTRL__FIRSTEP_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define BBB_DAGC_CTRL__FIRSTEP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define BBB_DAGC_CTRL__FIRSTEP_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field firstep_count_lgmax */ +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__SHIFT 24 +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__WIDTH 4 +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__MASK 0x0f000000U +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) + +/* macros for field force_rx_chain_cck_0 */ +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__SHIFT 28 +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__WIDTH 2 +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__MASK 0x30000000U +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x30000000U) >> 28) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x30000000U) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) + +/* macros for field force_rx_chain_cck_1 */ +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__SHIFT 30 +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__WIDTH 2 +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__MASK 0xc0000000U +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define BBB_DAGC_CTRL__TYPE u_int32_t +#define BBB_DAGC_CTRL__READ 0xffffffffU +#define BBB_DAGC_CTRL__WRITE 0xffffffffU + +#endif /* __BBB_DAGC_CTRL_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_bbb_dagc_ctrl */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BBB_DAGC_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iqcorr_ctrl_cck */ +#ifndef __IQCORR_CTRL_CCK_MACRO__ +#define __IQCORR_CTRL_CCK_MACRO__ + +/* macros for field iqcorr_q_q_coff_cck */ +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__SHIFT 0 +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__WIDTH 5 +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__MASK 0x0000001fU +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field iqcorr_q_i_coff_cck */ +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__SHIFT 5 +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__WIDTH 6 +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__MASK 0x000007e0U +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x000007e0U) >> 5) +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000007e0U) +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000007e0U) +#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000007e0U))) + +/* macros for field enable_iqcorr_cck */ +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__SHIFT 11 +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__WIDTH 1 +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__MASK 0x00000800U +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field rxcal_meas_time_sel */ +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__SHIFT 12 +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__WIDTH 2 +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__MASK 0x00003000U +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003000U) >> 12) +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00003000U) +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((u_int32_t)(src) <<\ + 12) & 0x00003000U) +#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00003000U))) + +/* macros for field clcal_meas_time_sel */ +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__SHIFT 14 +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__WIDTH 2 +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__MASK 0x0000c000U +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field cf_clc_init_rfgain */ +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__SHIFT 16 +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__WIDTH 5 +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__MASK 0x001f0000U +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) +#define IQCORR_CTRL_CCK__TYPE u_int32_t +#define IQCORR_CTRL_CCK__READ 0x001fffffU +#define IQCORR_CTRL_CCK__WRITE 0x001fffffU + +#endif /* __IQCORR_CTRL_CCK_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_iqcorr_ctrl_cck */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_IQCORR_CTRL_CCK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cck_spur_mit */ +#ifndef __CCK_SPUR_MIT_MACRO__ +#define __CCK_SPUR_MIT_MACRO__ + +/* macros for field use_cck_spur_mit */ +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__SHIFT 0 +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__WIDTH 1 +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__MASK 0x00000001U +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field spur_rssi_thr */ +#define CCK_SPUR_MIT__SPUR_RSSI_THR__SHIFT 1 +#define CCK_SPUR_MIT__SPUR_RSSI_THR__WIDTH 8 +#define CCK_SPUR_MIT__SPUR_RSSI_THR__MASK 0x000001feU +#define CCK_SPUR_MIT__SPUR_RSSI_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) +#define CCK_SPUR_MIT__SPUR_RSSI_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000001feU) +#define CCK_SPUR_MIT__SPUR_RSSI_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((u_int32_t)(src) <<\ + 1) & 0x000001feU) +#define CCK_SPUR_MIT__SPUR_RSSI_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000001feU))) + +/* macros for field cck_spur_freq */ +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__SHIFT 9 +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__WIDTH 20 +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__MASK 0x1ffffe00U +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x1ffffe00U) >> 9) +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x1ffffe00U) +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1ffffe00U) | (((u_int32_t)(src) <<\ + 9) & 0x1ffffe00U) +#define CCK_SPUR_MIT__CCK_SPUR_FREQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x1ffffe00U))) + +/* macros for field spur_filter_type */ +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__SHIFT 29 +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__WIDTH 2 +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__MASK 0x60000000U +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__READ(src) \ + (((u_int32_t)(src)\ + & 0x60000000U) >> 29) +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x60000000U) +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x60000000U) | (((u_int32_t)(src) <<\ + 29) & 0x60000000U) +#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x60000000U))) +#define CCK_SPUR_MIT__TYPE u_int32_t +#define CCK_SPUR_MIT__READ 0x7fffffffU +#define CCK_SPUR_MIT__WRITE 0x7fffffffU + +#endif /* __CCK_SPUR_MIT_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_cck_spur_mit */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCK_SPUR_MIT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::mrc_cck_ctrl */ +#ifndef __MRC_CCK_CTRL_MACRO__ +#define __MRC_CCK_CTRL_MACRO__ + +/* macros for field bbb_mrc_en */ +#define MRC_CCK_CTRL__BBB_MRC_EN__SHIFT 0 +#define MRC_CCK_CTRL__BBB_MRC_EN__WIDTH 1 +#define MRC_CCK_CTRL__BBB_MRC_EN__MASK 0x00000001U +#define MRC_CCK_CTRL__BBB_MRC_EN__READ(src) (u_int32_t)(src) & 0x00000001U +#define MRC_CCK_CTRL__BBB_MRC_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MRC_CCK_CTRL__BBB_MRC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MRC_CCK_CTRL__BBB_MRC_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MRC_CCK_CTRL__BBB_MRC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MRC_CCK_CTRL__BBB_MRC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field agcdp_cck_mrc_mux_reg */ +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__SHIFT 1 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__WIDTH 1 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__MASK 0x00000002U +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field agcdp_cck_pd_accu_thr_hi */ +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__SHIFT 2 +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__WIDTH 3 +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__MASK 0x0000001cU +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field agcdp_cck_pd_accu_thr_low */ +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__SHIFT 5 +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__WIDTH 3 +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__MASK 0x000000e0U +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field agcdp_cck_barker_rssi_thr */ +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__SHIFT 8 +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__WIDTH 4 +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__MASK 0x00000f00U +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field agcdp_cck_mrc_bk_thr_hi */ +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__SHIFT 12 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__WIDTH 5 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__MASK 0x0001f000U +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field agcdp_cck_mrc_bk_thr_low */ +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__SHIFT 17 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__WIDTH 5 +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__MASK 0x003e0000U +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field agcdp_cck_min_value */ +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__SHIFT 22 +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__WIDTH 6 +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__MASK 0x0fc00000U +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fc00000U) >> 22) +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x0fc00000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x0fc00000U) +#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x0fc00000U))) +#define MRC_CCK_CTRL__TYPE u_int32_t +#define MRC_CCK_CTRL__READ 0x0fffffffU +#define MRC_CCK_CTRL__WRITE 0x0fffffffU + +#endif /* __MRC_CCK_CTRL_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_mrc_cck_ctrl */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_MRC_CCK_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cck_blocker_det */ +#ifndef __CCK_BLOCKER_DET_MACRO__ +#define __CCK_BLOCKER_DET_MACRO__ + +/* macros for field cck_freq_shift_blocker_detection */ +#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__SHIFT 0 +#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__WIDTH 1 +#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__MASK 0x00000001U +#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cck_blocker_det_restart_weak_sig */ +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__SHIFT 1 +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__WIDTH 1 +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__MASK 0x00000002U +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field cck_blocker_det_bksum_num */ +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__SHIFT 2 +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__WIDTH 4 +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__MASK 0x0000003cU +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003cU) >> 2) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000003cU) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000003cU) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000003cU))) + +/* macros for field bk_valid_delay */ +#define CCK_BLOCKER_DET__BK_VALID_DELAY__SHIFT 6 +#define CCK_BLOCKER_DET__BK_VALID_DELAY__WIDTH 3 +#define CCK_BLOCKER_DET__BK_VALID_DELAY__MASK 0x000001c0U +#define CCK_BLOCKER_DET__BK_VALID_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001c0U) >> 6) +#define CCK_BLOCKER_DET__BK_VALID_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000001c0U) +#define CCK_BLOCKER_DET__BK_VALID_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define CCK_BLOCKER_DET__BK_VALID_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field cck_blocker_det_thr */ +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__SHIFT 9 +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__WIDTH 5 +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__MASK 0x00003e00U +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003e00U) >> 9) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00003e00U) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00003e00U) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00003e00U))) + +/* macros for field cck_blocker_det_delay_thr */ +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__SHIFT 14 +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__WIDTH 6 +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__MASK 0x000fc000U +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x000fc000U) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000fc000U) | (((u_int32_t)(src) <<\ + 14) & 0x000fc000U) +#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x000fc000U))) + +/* macros for field cck_blocker_monitor_time */ +#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__SHIFT 20 +#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__WIDTH 6 +#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__MASK 0x03f00000U +#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x03f00000U) >> 20) +#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x03f00000U) +#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x03f00000U) +#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x03f00000U))) + +/* macros for field skip_ramp_enable */ +#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__SHIFT 26 +#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__WIDTH 1 +#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__MASK 0x04000000U +#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field cck_det_ramp_thr */ +#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__SHIFT 27 +#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__WIDTH 5 +#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__MASK 0xf8000000U +#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define CCK_BLOCKER_DET__TYPE u_int32_t +#define CCK_BLOCKER_DET__READ 0xffffffffU +#define CCK_BLOCKER_DET__WRITE 0xffffffffU + +#endif /* __CCK_BLOCKER_DET_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_cck_blocker_det */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCK_BLOCKER_DET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_ocgain */ +#ifndef __RX_OCGAIN_MACRO__ +#define __RX_OCGAIN_MACRO__ + +/* macros for field gain_entry */ +#define RX_OCGAIN__GAIN_ENTRY__SHIFT 0 +#define RX_OCGAIN__GAIN_ENTRY__WIDTH 32 +#define RX_OCGAIN__GAIN_ENTRY__MASK 0xffffffffU +#define RX_OCGAIN__GAIN_ENTRY__READ(src) (u_int32_t)(src) & 0xffffffffU +#define RX_OCGAIN__GAIN_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define RX_OCGAIN__GAIN_ENTRY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define RX_OCGAIN__GAIN_ENTRY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define RX_OCGAIN__TYPE u_int32_t +#define RX_OCGAIN__READ 0xffffffffU +#define RX_OCGAIN__WRITE 0xffffffffU + +#endif /* __RX_OCGAIN_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc_reg_map.BB_rx_ocgain */ +#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RX_OCGAIN__NUM 128 + +/* macros for BlueprintGlobalNameSpace::D2_chip_id */ +#ifndef __D2_CHIP_ID_MACRO__ +#define __D2_CHIP_ID_MACRO__ + +/* macros for field old_id */ +#define D2_CHIP_ID__OLD_ID__SHIFT 0 +#define D2_CHIP_ID__OLD_ID__WIDTH 8 +#define D2_CHIP_ID__OLD_ID__MASK 0x000000ffU +#define D2_CHIP_ID__OLD_ID__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field id */ +#define D2_CHIP_ID__ID__SHIFT 8 +#define D2_CHIP_ID__ID__WIDTH 24 +#define D2_CHIP_ID__ID__MASK 0xffffff00U +#define D2_CHIP_ID__ID__READ(src) (((u_int32_t)(src) & 0xffffff00U) >> 8) +#define D2_CHIP_ID__TYPE u_int32_t +#define D2_CHIP_ID__READ 0xffffffffU + +#endif /* __D2_CHIP_ID_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_D2_chip_id */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_D2_CHIP_ID__NUM 1 + +/* macros for BlueprintGlobalNameSpace::gen_controls */ +#ifndef __GEN_CONTROLS_MACRO__ +#define __GEN_CONTROLS_MACRO__ + +/* macros for field turbo */ +#define GEN_CONTROLS__TURBO__SHIFT 0 +#define GEN_CONTROLS__TURBO__WIDTH 1 +#define GEN_CONTROLS__TURBO__MASK 0x00000001U +#define GEN_CONTROLS__TURBO__READ(src) (u_int32_t)(src) & 0x00000001U +#define GEN_CONTROLS__TURBO__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define GEN_CONTROLS__TURBO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define GEN_CONTROLS__TURBO__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define GEN_CONTROLS__TURBO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define GEN_CONTROLS__TURBO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_short20 */ +#define GEN_CONTROLS__CF_SHORT20__SHIFT 1 +#define GEN_CONTROLS__CF_SHORT20__WIDTH 1 +#define GEN_CONTROLS__CF_SHORT20__MASK 0x00000002U +#define GEN_CONTROLS__CF_SHORT20__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define GEN_CONTROLS__CF_SHORT20__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define GEN_CONTROLS__CF_SHORT20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define GEN_CONTROLS__CF_SHORT20__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define GEN_CONTROLS__CF_SHORT20__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define GEN_CONTROLS__CF_SHORT20__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field dyn_20_40 */ +#define GEN_CONTROLS__DYN_20_40__SHIFT 2 +#define GEN_CONTROLS__DYN_20_40__WIDTH 1 +#define GEN_CONTROLS__DYN_20_40__MASK 0x00000004U +#define GEN_CONTROLS__DYN_20_40__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define GEN_CONTROLS__DYN_20_40__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define GEN_CONTROLS__DYN_20_40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define GEN_CONTROLS__DYN_20_40__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define GEN_CONTROLS__DYN_20_40__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define GEN_CONTROLS__DYN_20_40__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field dyn_20_40_pri_only */ +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__SHIFT 3 +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__WIDTH 1 +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__MASK 0x00000008U +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field dyn_20_40_pri_chn */ +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__SHIFT 4 +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__WIDTH 1 +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__MASK 0x00000010U +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define GEN_CONTROLS__DYN_20_40_PRI_CHN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field dyn_20_40_ext_chn */ +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__SHIFT 5 +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__WIDTH 1 +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__MASK 0x00000020U +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define GEN_CONTROLS__DYN_20_40_EXT_CHN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field ht_enable */ +#define GEN_CONTROLS__HT_ENABLE__SHIFT 6 +#define GEN_CONTROLS__HT_ENABLE__WIDTH 1 +#define GEN_CONTROLS__HT_ENABLE__MASK 0x00000040U +#define GEN_CONTROLS__HT_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define GEN_CONTROLS__HT_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define GEN_CONTROLS__HT_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define GEN_CONTROLS__HT_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define GEN_CONTROLS__HT_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define GEN_CONTROLS__HT_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field allow_short_gi */ +#define GEN_CONTROLS__ALLOW_SHORT_GI__SHIFT 7 +#define GEN_CONTROLS__ALLOW_SHORT_GI__WIDTH 1 +#define GEN_CONTROLS__ALLOW_SHORT_GI__MASK 0x00000080U +#define GEN_CONTROLS__ALLOW_SHORT_GI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define GEN_CONTROLS__ALLOW_SHORT_GI__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define GEN_CONTROLS__ALLOW_SHORT_GI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define GEN_CONTROLS__ALLOW_SHORT_GI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define GEN_CONTROLS__ALLOW_SHORT_GI__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define GEN_CONTROLS__ALLOW_SHORT_GI__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field cf_2_chains_use_walsh */ +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__SHIFT 8 +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__WIDTH 1 +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__MASK 0x00000100U +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field cf_3_chains_use_walsh */ +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__SHIFT 9 +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__WIDTH 1 +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__MASK 0x00000200U +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field gf_enable */ +#define GEN_CONTROLS__GF_ENABLE__SHIFT 10 +#define GEN_CONTROLS__GF_ENABLE__WIDTH 1 +#define GEN_CONTROLS__GF_ENABLE__MASK 0x00000400U +#define GEN_CONTROLS__GF_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define GEN_CONTROLS__GF_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define GEN_CONTROLS__GF_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define GEN_CONTROLS__GF_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define GEN_CONTROLS__GF_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define GEN_CONTROLS__GF_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field enable_dac_async_fifo */ +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__SHIFT 11 +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__WIDTH 1 +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MASK 0x00000800U +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field bond_opt_chain_sel */ +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__SHIFT 14 +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__WIDTH 1 +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__MASK 0x00004000U +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field static20_mode_ht40_packet_handling */ +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__SHIFT 15 +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__WIDTH 1 +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MASK 0x00008000U +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field static20_mode_ht40_packet_error_rpt */ +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__SHIFT 16 +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__WIDTH 1 +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MASK 0x00010000U +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field enable_csd_phase_dithering */ +#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__SHIFT 17 +#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__WIDTH 1 +#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__MASK 0x00020000U +#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field unsupp_ht_rate_threshold */ +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__SHIFT 18 +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__WIDTH 7 +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MASK 0x01fc0000U +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fc0000U) >> 18) +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x01fc0000U) +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x01fc0000U) +#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x01fc0000U))) + +/* macros for field en_err_tx_chain_mask_zero */ +#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__SHIFT 25 +#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__WIDTH 1 +#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__MASK 0x02000000U +#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) +#define GEN_CONTROLS__TYPE u_int32_t +#define GEN_CONTROLS__READ 0x03ffcfffU +#define GEN_CONTROLS__WRITE 0x03ffcfffU + +#endif /* __GEN_CONTROLS_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_gen_controls */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_GEN_CONTROLS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::modes_select */ +#ifndef __MODES_SELECT_MACRO__ +#define __MODES_SELECT_MACRO__ + +/* macros for field cck_mode */ +#define MODES_SELECT__CCK_MODE__SHIFT 0 +#define MODES_SELECT__CCK_MODE__WIDTH 1 +#define MODES_SELECT__CCK_MODE__MASK 0x00000001U +#define MODES_SELECT__CCK_MODE__READ(src) (u_int32_t)(src) & 0x00000001U +#define MODES_SELECT__CCK_MODE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define MODES_SELECT__CCK_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MODES_SELECT__CCK_MODE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MODES_SELECT__CCK_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MODES_SELECT__CCK_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dyn_ofdm_cck_mode */ +#define MODES_SELECT__DYN_OFDM_CCK_MODE__SHIFT 2 +#define MODES_SELECT__DYN_OFDM_CCK_MODE__WIDTH 1 +#define MODES_SELECT__DYN_OFDM_CCK_MODE__MASK 0x00000004U +#define MODES_SELECT__DYN_OFDM_CCK_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MODES_SELECT__DYN_OFDM_CCK_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MODES_SELECT__DYN_OFDM_CCK_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MODES_SELECT__DYN_OFDM_CCK_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MODES_SELECT__DYN_OFDM_CCK_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MODES_SELECT__DYN_OFDM_CCK_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field half_rate_mode */ +#define MODES_SELECT__HALF_RATE_MODE__SHIFT 5 +#define MODES_SELECT__HALF_RATE_MODE__WIDTH 1 +#define MODES_SELECT__HALF_RATE_MODE__MASK 0x00000020U +#define MODES_SELECT__HALF_RATE_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define MODES_SELECT__HALF_RATE_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define MODES_SELECT__HALF_RATE_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define MODES_SELECT__HALF_RATE_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define MODES_SELECT__HALF_RATE_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define MODES_SELECT__HALF_RATE_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field quarter_rate_mode */ +#define MODES_SELECT__QUARTER_RATE_MODE__SHIFT 6 +#define MODES_SELECT__QUARTER_RATE_MODE__WIDTH 1 +#define MODES_SELECT__QUARTER_RATE_MODE__MASK 0x00000040U +#define MODES_SELECT__QUARTER_RATE_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define MODES_SELECT__QUARTER_RATE_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define MODES_SELECT__QUARTER_RATE_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define MODES_SELECT__QUARTER_RATE_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define MODES_SELECT__QUARTER_RATE_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define MODES_SELECT__QUARTER_RATE_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field mac_clk_mode */ +#define MODES_SELECT__MAC_CLK_MODE__SHIFT 7 +#define MODES_SELECT__MAC_CLK_MODE__WIDTH 1 +#define MODES_SELECT__MAC_CLK_MODE__MASK 0x00000080U +#define MODES_SELECT__MAC_CLK_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define MODES_SELECT__MAC_CLK_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define MODES_SELECT__MAC_CLK_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define MODES_SELECT__MAC_CLK_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define MODES_SELECT__MAC_CLK_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define MODES_SELECT__MAC_CLK_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field disable_dyn_cck_det */ +#define MODES_SELECT__DISABLE_DYN_CCK_DET__SHIFT 8 +#define MODES_SELECT__DISABLE_DYN_CCK_DET__WIDTH 1 +#define MODES_SELECT__DISABLE_DYN_CCK_DET__MASK 0x00000100U +#define MODES_SELECT__DISABLE_DYN_CCK_DET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define MODES_SELECT__DISABLE_DYN_CCK_DET__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define MODES_SELECT__DISABLE_DYN_CCK_DET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define MODES_SELECT__DISABLE_DYN_CCK_DET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define MODES_SELECT__DISABLE_DYN_CCK_DET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define MODES_SELECT__DISABLE_DYN_CCK_DET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field svd_half_rate_mode */ +#define MODES_SELECT__SVD_HALF_RATE_MODE__SHIFT 9 +#define MODES_SELECT__SVD_HALF_RATE_MODE__WIDTH 1 +#define MODES_SELECT__SVD_HALF_RATE_MODE__MASK 0x00000200U +#define MODES_SELECT__SVD_HALF_RATE_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define MODES_SELECT__SVD_HALF_RATE_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define MODES_SELECT__SVD_HALF_RATE_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define MODES_SELECT__SVD_HALF_RATE_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define MODES_SELECT__SVD_HALF_RATE_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define MODES_SELECT__SVD_HALF_RATE_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) +#define MODES_SELECT__TYPE u_int32_t +#define MODES_SELECT__READ 0x000003e5U +#define MODES_SELECT__WRITE 0x000003e5U + +#endif /* __MODES_SELECT_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_modes_select */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MODES_SELECT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::active */ +#ifndef __ACTIVE_MACRO__ +#define __ACTIVE_MACRO__ + +/* macros for field cf_active */ +#define ACTIVE__CF_ACTIVE__SHIFT 0 +#define ACTIVE__CF_ACTIVE__WIDTH 1 +#define ACTIVE__CF_ACTIVE__MASK 0x00000001U +#define ACTIVE__CF_ACTIVE__READ(src) (u_int32_t)(src) & 0x00000001U +#define ACTIVE__CF_ACTIVE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define ACTIVE__CF_ACTIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define ACTIVE__CF_ACTIVE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define ACTIVE__CF_ACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define ACTIVE__CF_ACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define ACTIVE__TYPE u_int32_t +#define ACTIVE__READ 0x00000001U +#define ACTIVE__WRITE 0x00000001U + +#endif /* __ACTIVE_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_active */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ACTIVE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::vit_spur_mask_A */ +#ifndef __VIT_SPUR_MASK_A_MACRO__ +#define __VIT_SPUR_MASK_A_MACRO__ + +/* macros for field cf_punc_mask_A */ +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__SHIFT 0 +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__WIDTH 10 +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__MASK 0x000003ffU +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field cf_punc_mask_idx_A */ +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__SHIFT 10 +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__WIDTH 7 +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__MASK 0x0001fc00U +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fc00U) >> 10) +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0001fc00U) +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0001fc00U) +#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0001fc00U))) +#define VIT_SPUR_MASK_A__TYPE u_int32_t +#define VIT_SPUR_MASK_A__READ 0x0001ffffU +#define VIT_SPUR_MASK_A__WRITE 0x0001ffffU + +#endif /* __VIT_SPUR_MASK_A_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_vit_spur_mask_A */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_VIT_SPUR_MASK_A__NUM 1 + +/* macros for BlueprintGlobalNameSpace::vit_spur_mask_B */ +#ifndef __VIT_SPUR_MASK_B_MACRO__ +#define __VIT_SPUR_MASK_B_MACRO__ + +/* macros for field cf_punc_mask_B */ +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__SHIFT 0 +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__WIDTH 10 +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__MASK 0x000003ffU +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field cf_punc_mask_idx_B */ +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__SHIFT 10 +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__WIDTH 7 +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__MASK 0x0001fc00U +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fc00U) >> 10) +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0001fc00U) +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0001fc00U) +#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0001fc00U))) +#define VIT_SPUR_MASK_B__TYPE u_int32_t +#define VIT_SPUR_MASK_B__READ 0x0001ffffU +#define VIT_SPUR_MASK_B__WRITE 0x0001ffffU + +#endif /* __VIT_SPUR_MASK_B_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_vit_spur_mask_B */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_VIT_SPUR_MASK_B__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spectral_scan */ +#ifndef __SPECTRAL_SCAN_MACRO__ +#define __SPECTRAL_SCAN_MACRO__ + +/* macros for field spectral_scan_ena */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__SHIFT 0 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__MASK 0x00000001U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field spectral_scan_active */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__SHIFT 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__MASK 0x00000002U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field disable_radar_tctl_rst */ +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__SHIFT 2 +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__WIDTH 1 +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__MASK 0x00000004U +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field disable_pulse_coarse_low */ +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__SHIFT 3 +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__WIDTH 1 +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__MASK 0x00000008U +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field spectral_scan_fft_period */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__SHIFT 4 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__WIDTH 4 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__MASK 0x000000f0U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field spectral_scan_period */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__SHIFT 8 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__WIDTH 8 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__MASK 0x0000ff00U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field spectral_scan_count */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__SHIFT 16 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__WIDTH 12 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__MASK 0x0fff0000U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fff0000U) >> 16) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x0fff0000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x0fff0000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x0fff0000U))) + +/* macros for field spectral_scan_short_rpt */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__SHIFT 28 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__MASK 0x10000000U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field spectral_scan_priority */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__SHIFT 29 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__MASK 0x20000000U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field spectral_scan_use_err5 */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__SHIFT 30 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__MASK 0x40000000U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field spectral_scan_compressed_rpt */ +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__SHIFT 31 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__WIDTH 1 +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MASK 0x80000000U +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SPECTRAL_SCAN__TYPE u_int32_t +#define SPECTRAL_SCAN__READ 0xffffffffU +#define SPECTRAL_SCAN__WRITE 0xffffffffU + +#endif /* __SPECTRAL_SCAN_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_spectral_scan */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SPECTRAL_SCAN__NUM 1 + +/* macros for BlueprintGlobalNameSpace::radar_bw_filter */ +#ifndef __RADAR_BW_FILTER_MACRO__ +#define __RADAR_BW_FILTER_MACRO__ + +/* macros for field radar_avg_bw_check */ +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__SHIFT 0 +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__WIDTH 1 +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__MASK 0x00000001U +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field radar_dc_src_sel */ +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__SHIFT 1 +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__WIDTH 1 +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__MASK 0x00000002U +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field radar_firpwr_sel */ +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__SHIFT 2 +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__WIDTH 2 +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__MASK 0x0000000cU +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field radar_pulse_width_sel */ +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__SHIFT 4 +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__WIDTH 2 +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__MASK 0x00000030U +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field radar_dc_firpwr_thresh */ +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__SHIFT 8 +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__WIDTH 7 +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__MASK 0x00007f00U +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007f00U) >> 8) +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00007f00U) +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00007f00U) +#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00007f00U))) + +/* macros for field radar_dc_pwr_bias */ +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__SHIFT 15 +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__WIDTH 6 +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__MASK 0x001f8000U +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f8000U) >> 15) +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x001f8000U) +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x001f8000U) +#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x001f8000U))) + +/* macros for field radar_bin_max_bw */ +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__SHIFT 21 +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__WIDTH 6 +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__MASK 0x07e00000U +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__READ(src) \ + (((u_int32_t)(src)\ + & 0x07e00000U) >> 21) +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x07e00000U) +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x07e00000U) +#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x07e00000U))) +#define RADAR_BW_FILTER__TYPE u_int32_t +#define RADAR_BW_FILTER__READ 0x07ffff3fU +#define RADAR_BW_FILTER__WRITE 0x07ffff3fU + +#endif /* __RADAR_BW_FILTER_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_radar_bw_filter */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RADAR_BW_FILTER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::search_start_delay */ +#ifndef __SEARCH_START_DELAY_MACRO__ +#define __SEARCH_START_DELAY_MACRO__ + +/* macros for field search_start_delay */ +#define SEARCH_START_DELAY__SEARCH_START_DELAY__SHIFT 0 +#define SEARCH_START_DELAY__SEARCH_START_DELAY__WIDTH 12 +#define SEARCH_START_DELAY__SEARCH_START_DELAY__MASK 0x00000fffU +#define SEARCH_START_DELAY__SEARCH_START_DELAY__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define SEARCH_START_DELAY__SEARCH_START_DELAY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define SEARCH_START_DELAY__SEARCH_START_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define SEARCH_START_DELAY__SEARCH_START_DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field enable_flt_svd */ +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__SHIFT 12 +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__WIDTH 1 +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__MASK 0x00001000U +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define SEARCH_START_DELAY__ENABLE_FLT_SVD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field enable_send_chan */ +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__SHIFT 13 +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__WIDTH 1 +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__MASK 0x00002000U +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field rx_sounding_enable */ +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__SHIFT 14 +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__WIDTH 1 +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MASK 0x00004000U +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field rm_hcsd4svd */ +#define SEARCH_START_DELAY__RM_HCSD4SVD__SHIFT 15 +#define SEARCH_START_DELAY__RM_HCSD4SVD__WIDTH 1 +#define SEARCH_START_DELAY__RM_HCSD4SVD__MASK 0x00008000U +#define SEARCH_START_DELAY__RM_HCSD4SVD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define SEARCH_START_DELAY__RM_HCSD4SVD__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define SEARCH_START_DELAY__RM_HCSD4SVD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define SEARCH_START_DELAY__RM_HCSD4SVD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define SEARCH_START_DELAY__RM_HCSD4SVD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define SEARCH_START_DELAY__RM_HCSD4SVD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) +#define SEARCH_START_DELAY__TYPE u_int32_t +#define SEARCH_START_DELAY__READ 0x0000ffffU +#define SEARCH_START_DELAY__WRITE 0x0000ffffU + +#endif /* __SEARCH_START_DELAY_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_search_start_delay */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SEARCH_START_DELAY__NUM 1 + +/* macros for BlueprintGlobalNameSpace::max_rx_length */ +#ifndef __MAX_RX_LENGTH_MACRO__ +#define __MAX_RX_LENGTH_MACRO__ + +/* macros for field max_rx_length */ +#define MAX_RX_LENGTH__MAX_RX_LENGTH__SHIFT 0 +#define MAX_RX_LENGTH__MAX_RX_LENGTH__WIDTH 12 +#define MAX_RX_LENGTH__MAX_RX_LENGTH__MASK 0x00000fffU +#define MAX_RX_LENGTH__MAX_RX_LENGTH__READ(src) (u_int32_t)(src) & 0x00000fffU +#define MAX_RX_LENGTH__MAX_RX_LENGTH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define MAX_RX_LENGTH__MAX_RX_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define MAX_RX_LENGTH__MAX_RX_LENGTH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field max_ht_length */ +#define MAX_RX_LENGTH__MAX_HT_LENGTH__SHIFT 12 +#define MAX_RX_LENGTH__MAX_HT_LENGTH__WIDTH 18 +#define MAX_RX_LENGTH__MAX_HT_LENGTH__MASK 0x3ffff000U +#define MAX_RX_LENGTH__MAX_HT_LENGTH__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ffff000U) >> 12) +#define MAX_RX_LENGTH__MAX_HT_LENGTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x3ffff000U) +#define MAX_RX_LENGTH__MAX_HT_LENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ffff000U) | (((u_int32_t)(src) <<\ + 12) & 0x3ffff000U) +#define MAX_RX_LENGTH__MAX_HT_LENGTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x3ffff000U))) +#define MAX_RX_LENGTH__TYPE u_int32_t +#define MAX_RX_LENGTH__READ 0x3fffffffU +#define MAX_RX_LENGTH__WRITE 0x3fffffffU + +#endif /* __MAX_RX_LENGTH_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_max_rx_length */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MAX_RX_LENGTH__NUM 1 + +/* macros for BlueprintGlobalNameSpace::frame_control */ +#ifndef __FRAME_CONTROL_MACRO__ +#define __FRAME_CONTROL_MACRO__ + +/* macros for field cf_overlap_window */ +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__SHIFT 0 +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__WIDTH 2 +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__MASK 0x00000003U +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define FRAME_CONTROL__CF_OVERLAP_WINDOW__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field cf_scale_short */ +#define FRAME_CONTROL__CF_SCALE_SHORT__SHIFT 2 +#define FRAME_CONTROL__CF_SCALE_SHORT__WIDTH 1 +#define FRAME_CONTROL__CF_SCALE_SHORT__MASK 0x00000004U +#define FRAME_CONTROL__CF_SCALE_SHORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define FRAME_CONTROL__CF_SCALE_SHORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define FRAME_CONTROL__CF_SCALE_SHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define FRAME_CONTROL__CF_SCALE_SHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define FRAME_CONTROL__CF_SCALE_SHORT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define FRAME_CONTROL__CF_SCALE_SHORT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field cf_tx_clip */ +#define FRAME_CONTROL__CF_TX_CLIP__SHIFT 3 +#define FRAME_CONTROL__CF_TX_CLIP__WIDTH 3 +#define FRAME_CONTROL__CF_TX_CLIP__MASK 0x00000038U +#define FRAME_CONTROL__CF_TX_CLIP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define FRAME_CONTROL__CF_TX_CLIP__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define FRAME_CONTROL__CF_TX_CLIP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define FRAME_CONTROL__CF_TX_CLIP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field cf_tx_doublesamp_dac */ +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__SHIFT 6 +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__WIDTH 2 +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__MASK 0x000000c0U +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field tx_end_adjust */ +#define FRAME_CONTROL__TX_END_ADJUST__SHIFT 8 +#define FRAME_CONTROL__TX_END_ADJUST__WIDTH 8 +#define FRAME_CONTROL__TX_END_ADJUST__MASK 0x0000ff00U +#define FRAME_CONTROL__TX_END_ADJUST__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define FRAME_CONTROL__TX_END_ADJUST__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define FRAME_CONTROL__TX_END_ADJUST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define FRAME_CONTROL__TX_END_ADJUST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field prepend_chan_info */ +#define FRAME_CONTROL__PREPEND_CHAN_INFO__SHIFT 16 +#define FRAME_CONTROL__PREPEND_CHAN_INFO__WIDTH 1 +#define FRAME_CONTROL__PREPEND_CHAN_INFO__MASK 0x00010000U +#define FRAME_CONTROL__PREPEND_CHAN_INFO__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define FRAME_CONTROL__PREPEND_CHAN_INFO__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define FRAME_CONTROL__PREPEND_CHAN_INFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define FRAME_CONTROL__PREPEND_CHAN_INFO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define FRAME_CONTROL__PREPEND_CHAN_INFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define FRAME_CONTROL__PREPEND_CHAN_INFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field short_high_par_norm */ +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__SHIFT 17 +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__WIDTH 1 +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__MASK 0x00020000U +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field en_err_green_field */ +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__SHIFT 18 +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__MASK 0x00040000U +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field en_err_static20_mode_ht40_packet */ +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__SHIFT 19 +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MASK 0x00080000U +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field en_err_ofdm_xcorr */ +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__SHIFT 20 +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__MASK 0x00100000U +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field en_err_long_sc_thr */ +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__SHIFT 21 +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__MASK 0x00200000U +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field en_err_tim_long1 */ +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__SHIFT 22 +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__MASK 0x00400000U +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define FRAME_CONTROL__EN_ERR_TIM_LONG1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field en_err_tim_early_trig */ +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__SHIFT 23 +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__MASK 0x00800000U +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field en_err_tim_timeout */ +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__SHIFT 24 +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__MASK 0x01000000U +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field en_err_signal_parity */ +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__SHIFT 25 +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__MASK 0x02000000U +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field en_err_rate_illegal */ +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__SHIFT 26 +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__MASK 0x04000000U +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field en_err_length_illegal */ +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__SHIFT 27 +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__MASK 0x08000000U +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field no_6mbps_service_err */ +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__SHIFT 28 +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__WIDTH 1 +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__MASK 0x10000000U +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field en_err_service */ +#define FRAME_CONTROL__EN_ERR_SERVICE__SHIFT 29 +#define FRAME_CONTROL__EN_ERR_SERVICE__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_SERVICE__MASK 0x20000000U +#define FRAME_CONTROL__EN_ERR_SERVICE__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define FRAME_CONTROL__EN_ERR_SERVICE__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define FRAME_CONTROL__EN_ERR_SERVICE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define FRAME_CONTROL__EN_ERR_SERVICE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define FRAME_CONTROL__EN_ERR_SERVICE__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define FRAME_CONTROL__EN_ERR_SERVICE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field en_err_tx_underrun */ +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__SHIFT 30 +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__MASK 0x40000000U +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field en_err_rx_abort */ +#define FRAME_CONTROL__EN_ERR_RX_ABORT__SHIFT 31 +#define FRAME_CONTROL__EN_ERR_RX_ABORT__WIDTH 1 +#define FRAME_CONTROL__EN_ERR_RX_ABORT__MASK 0x80000000U +#define FRAME_CONTROL__EN_ERR_RX_ABORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define FRAME_CONTROL__EN_ERR_RX_ABORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define FRAME_CONTROL__EN_ERR_RX_ABORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define FRAME_CONTROL__EN_ERR_RX_ABORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define FRAME_CONTROL__EN_ERR_RX_ABORT__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define FRAME_CONTROL__EN_ERR_RX_ABORT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define FRAME_CONTROL__TYPE u_int32_t +#define FRAME_CONTROL__READ 0xffffffffU +#define FRAME_CONTROL__WRITE 0xffffffffU + +#endif /* __FRAME_CONTROL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_frame_control */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FRAME_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rfbus_request */ +#ifndef __RFBUS_REQUEST_MACRO__ +#define __RFBUS_REQUEST_MACRO__ + +/* macros for field rfbus_request */ +#define RFBUS_REQUEST__RFBUS_REQUEST__SHIFT 0 +#define RFBUS_REQUEST__RFBUS_REQUEST__WIDTH 1 +#define RFBUS_REQUEST__RFBUS_REQUEST__MASK 0x00000001U +#define RFBUS_REQUEST__RFBUS_REQUEST__READ(src) (u_int32_t)(src) & 0x00000001U +#define RFBUS_REQUEST__RFBUS_REQUEST__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RFBUS_REQUEST__RFBUS_REQUEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RFBUS_REQUEST__RFBUS_REQUEST__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RFBUS_REQUEST__RFBUS_REQUEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RFBUS_REQUEST__RFBUS_REQUEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define RFBUS_REQUEST__TYPE u_int32_t +#define RFBUS_REQUEST__READ 0x00000001U +#define RFBUS_REQUEST__WRITE 0x00000001U + +#endif /* __RFBUS_REQUEST_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_rfbus_request */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RFBUS_REQUEST__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rfbus_grant */ +#ifndef __RFBUS_GRANT_MACRO__ +#define __RFBUS_GRANT_MACRO__ + +/* macros for field rfbus_grant */ +#define RFBUS_GRANT__RFBUS_GRANT__SHIFT 0 +#define RFBUS_GRANT__RFBUS_GRANT__WIDTH 1 +#define RFBUS_GRANT__RFBUS_GRANT__MASK 0x00000001U +#define RFBUS_GRANT__RFBUS_GRANT__READ(src) (u_int32_t)(src) & 0x00000001U +#define RFBUS_GRANT__RFBUS_GRANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RFBUS_GRANT__RFBUS_GRANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field bt_ant */ +#define RFBUS_GRANT__BT_ANT__SHIFT 1 +#define RFBUS_GRANT__BT_ANT__WIDTH 1 +#define RFBUS_GRANT__BT_ANT__MASK 0x00000002U +#define RFBUS_GRANT__BT_ANT__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define RFBUS_GRANT__BT_ANT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RFBUS_GRANT__BT_ANT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define RFBUS_GRANT__TYPE u_int32_t +#define RFBUS_GRANT__READ 0x00000003U + +#endif /* __RFBUS_GRANT_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_rfbus_grant */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RFBUS_GRANT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rifs */ +#ifndef __RIFS_MACRO__ +#define __RIFS_MACRO__ + +/* macros for field disable_fcc_fix */ +#define RIFS__DISABLE_FCC_FIX__SHIFT 25 +#define RIFS__DISABLE_FCC_FIX__WIDTH 1 +#define RIFS__DISABLE_FCC_FIX__MASK 0x02000000U +#define RIFS__DISABLE_FCC_FIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define RIFS__DISABLE_FCC_FIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define RIFS__DISABLE_FCC_FIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RIFS__DISABLE_FCC_FIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RIFS__DISABLE_FCC_FIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RIFS__DISABLE_FCC_FIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field enable_reset_tdomain */ +#define RIFS__ENABLE_RESET_TDOMAIN__SHIFT 26 +#define RIFS__ENABLE_RESET_TDOMAIN__WIDTH 1 +#define RIFS__ENABLE_RESET_TDOMAIN__MASK 0x04000000U +#define RIFS__ENABLE_RESET_TDOMAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define RIFS__ENABLE_RESET_TDOMAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define RIFS__ENABLE_RESET_TDOMAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RIFS__ENABLE_RESET_TDOMAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RIFS__ENABLE_RESET_TDOMAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RIFS__ENABLE_RESET_TDOMAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field disable_fcc_fix2 */ +#define RIFS__DISABLE_FCC_FIX2__SHIFT 27 +#define RIFS__DISABLE_FCC_FIX2__WIDTH 1 +#define RIFS__DISABLE_FCC_FIX2__MASK 0x08000000U +#define RIFS__DISABLE_FCC_FIX2__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RIFS__DISABLE_FCC_FIX2__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RIFS__DISABLE_FCC_FIX2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RIFS__DISABLE_FCC_FIX2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RIFS__DISABLE_FCC_FIX2__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RIFS__DISABLE_FCC_FIX2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field disable_rifs_cck_fix */ +#define RIFS__DISABLE_RIFS_CCK_FIX__SHIFT 28 +#define RIFS__DISABLE_RIFS_CCK_FIX__WIDTH 1 +#define RIFS__DISABLE_RIFS_CCK_FIX__MASK 0x10000000U +#define RIFS__DISABLE_RIFS_CCK_FIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define RIFS__DISABLE_RIFS_CCK_FIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define RIFS__DISABLE_RIFS_CCK_FIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RIFS__DISABLE_RIFS_CCK_FIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RIFS__DISABLE_RIFS_CCK_FIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RIFS__DISABLE_RIFS_CCK_FIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field disable_error_reset_fix */ +#define RIFS__DISABLE_ERROR_RESET_FIX__SHIFT 29 +#define RIFS__DISABLE_ERROR_RESET_FIX__WIDTH 1 +#define RIFS__DISABLE_ERROR_RESET_FIX__MASK 0x20000000U +#define RIFS__DISABLE_ERROR_RESET_FIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RIFS__DISABLE_ERROR_RESET_FIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RIFS__DISABLE_ERROR_RESET_FIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RIFS__DISABLE_ERROR_RESET_FIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RIFS__DISABLE_ERROR_RESET_FIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RIFS__DISABLE_ERROR_RESET_FIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field radar_use_fdomain_reset */ +#define RIFS__RADAR_USE_FDOMAIN_RESET__SHIFT 30 +#define RIFS__RADAR_USE_FDOMAIN_RESET__WIDTH 1 +#define RIFS__RADAR_USE_FDOMAIN_RESET__MASK 0x40000000U +#define RIFS__RADAR_USE_FDOMAIN_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RIFS__RADAR_USE_FDOMAIN_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RIFS__RADAR_USE_FDOMAIN_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RIFS__RADAR_USE_FDOMAIN_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RIFS__RADAR_USE_FDOMAIN_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RIFS__RADAR_USE_FDOMAIN_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define RIFS__TYPE u_int32_t +#define RIFS__READ 0x7e000000U +#define RIFS__WRITE 0x7e000000U + +#endif /* __RIFS_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_rifs */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RIFS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spectral_scan_2 */ +#ifndef __SPECTRAL_SCAN_2_MACRO__ +#define __SPECTRAL_SCAN_2_MACRO__ + +/* macros for field spectral_scan_rpt_mode */ +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__SHIFT 0 +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__WIDTH 1 +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__MASK 0x00000001U +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field spectral_scan_noise_floor_ref */ +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__SHIFT 1 +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__WIDTH 8 +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__MASK 0x000001feU +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000001feU) +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((u_int32_t)(src) <<\ + 1) & 0x000001feU) +#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000001feU))) +#define SPECTRAL_SCAN_2__TYPE u_int32_t +#define SPECTRAL_SCAN_2__READ 0x000001ffU +#define SPECTRAL_SCAN_2__WRITE 0x000001ffU + +#endif /* __SPECTRAL_SCAN_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_spectral_scan_2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SPECTRAL_SCAN_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_clear_delay */ +#ifndef __RX_CLEAR_DELAY_MACRO__ +#define __RX_CLEAR_DELAY_MACRO__ + +/* macros for field ofdm_xr_rx_clear_delay */ +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__SHIFT 0 +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__WIDTH 10 +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__MASK 0x000003ffU +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) +#define RX_CLEAR_DELAY__TYPE u_int32_t +#define RX_CLEAR_DELAY__READ 0x000003ffU +#define RX_CLEAR_DELAY__WRITE 0x000003ffU + +#endif /* __RX_CLEAR_DELAY_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_rx_clear_delay */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RX_CLEAR_DELAY__NUM 1 + +/* macros for BlueprintGlobalNameSpace::analog_power_on_time */ +#ifndef __ANALOG_POWER_ON_TIME_MACRO__ +#define __ANALOG_POWER_ON_TIME_MACRO__ + +/* macros for field active_to_receive */ +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__SHIFT 0 +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__WIDTH 14 +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__MASK 0x00003fffU +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) +#define ANALOG_POWER_ON_TIME__TYPE u_int32_t +#define ANALOG_POWER_ON_TIME__READ 0x00003fffU +#define ANALOG_POWER_ON_TIME__WRITE 0x00003fffU + +#endif /* __ANALOG_POWER_ON_TIME_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_analog_power_on_time */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ANALOG_POWER_ON_TIME__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_timing_1 */ +#ifndef __TX_TIMING_1_MACRO__ +#define __TX_TIMING_1_MACRO__ + +/* macros for field tx_frame_to_adc_off */ +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__SHIFT 0 +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__WIDTH 8 +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__MASK 0x000000ffU +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_frame_to_a2_rx_off */ +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__SHIFT 8 +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__WIDTH 8 +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__MASK 0x0000ff00U +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field tx_frame_to_dac_on */ +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__SHIFT 16 +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__WIDTH 8 +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__MASK 0x00ff0000U +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field tx_frame_to_a2_tx_on */ +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__SHIFT 24 +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__WIDTH 8 +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__MASK 0xff000000U +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TX_TIMING_1__TYPE u_int32_t +#define TX_TIMING_1__READ 0xffffffffU +#define TX_TIMING_1__WRITE 0xffffffffU + +#endif /* __TX_TIMING_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_timing_1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_TIMING_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_timing_2 */ +#ifndef __TX_TIMING_2_MACRO__ +#define __TX_TIMING_2_MACRO__ + +/* macros for field tx_frame_to_tx_d_start */ +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__SHIFT 0 +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__WIDTH 8 +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__MASK 0x000000ffU +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_frame_to_pa_on */ +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__SHIFT 8 +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__WIDTH 8 +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__MASK 0x0000ff00U +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TX_TIMING_2__TX_FRAME_TO_PA_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field tx_end_to_pa_off */ +#define TX_TIMING_2__TX_END_TO_PA_OFF__SHIFT 16 +#define TX_TIMING_2__TX_END_TO_PA_OFF__WIDTH 8 +#define TX_TIMING_2__TX_END_TO_PA_OFF__MASK 0x00ff0000U +#define TX_TIMING_2__TX_END_TO_PA_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TX_TIMING_2__TX_END_TO_PA_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TX_TIMING_2__TX_END_TO_PA_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TX_TIMING_2__TX_END_TO_PA_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field tx_end_to_a2_tx_off */ +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__SHIFT 24 +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__WIDTH 8 +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__MASK 0xff000000U +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TX_TIMING_2__TYPE u_int32_t +#define TX_TIMING_2__READ 0xffffffffU +#define TX_TIMING_2__WRITE 0xffffffffU + +#endif /* __TX_TIMING_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_timing_2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_TIMING_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_timing_3 */ +#ifndef __TX_TIMING_3_MACRO__ +#define __TX_TIMING_3_MACRO__ + +/* macros for field tx_end_to_dac_off */ +#define TX_TIMING_3__TX_END_TO_DAC_OFF__SHIFT 0 +#define TX_TIMING_3__TX_END_TO_DAC_OFF__WIDTH 8 +#define TX_TIMING_3__TX_END_TO_DAC_OFF__MASK 0x000000ffU +#define TX_TIMING_3__TX_END_TO_DAC_OFF__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define TX_TIMING_3__TX_END_TO_DAC_OFF__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TX_TIMING_3__TX_END_TO_DAC_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TX_TIMING_3__TX_END_TO_DAC_OFF__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_frame_to_therm_chain_on */ +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__SHIFT 8 +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__WIDTH 8 +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__MASK 0x0000ff00U +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field tx_end_to_a2_rx_on */ +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__SHIFT 16 +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__WIDTH 8 +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__MASK 0x00ff0000U +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TX_TIMING_3__TX_END_TO_A2_RX_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field tx_end_to_adc_on */ +#define TX_TIMING_3__TX_END_TO_ADC_ON__SHIFT 24 +#define TX_TIMING_3__TX_END_TO_ADC_ON__WIDTH 8 +#define TX_TIMING_3__TX_END_TO_ADC_ON__MASK 0xff000000U +#define TX_TIMING_3__TX_END_TO_ADC_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TX_TIMING_3__TX_END_TO_ADC_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TX_TIMING_3__TX_END_TO_ADC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TX_TIMING_3__TX_END_TO_ADC_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TX_TIMING_3__TYPE u_int32_t +#define TX_TIMING_3__READ 0xffffffffU +#define TX_TIMING_3__WRITE 0xffffffffU + +#endif /* __TX_TIMING_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_timing_3 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_TIMING_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::xpa_timing_control */ +#ifndef __XPA_TIMING_CONTROL_MACRO__ +#define __XPA_TIMING_CONTROL_MACRO__ + +/* macros for field tx_frame_to_xpaa_on */ +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__SHIFT 0 +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__WIDTH 8 +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__MASK 0x000000ffU +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_frame_to_xpab_on */ +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__SHIFT 8 +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__WIDTH 8 +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__MASK 0x0000ff00U +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field tx_end_to_xpaa_off */ +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__SHIFT 16 +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__WIDTH 8 +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__MASK 0x00ff0000U +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field tx_end_to_xpab_off */ +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__SHIFT 24 +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__WIDTH 8 +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__MASK 0xff000000U +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define XPA_TIMING_CONTROL__TYPE u_int32_t +#define XPA_TIMING_CONTROL__READ 0xffffffffU +#define XPA_TIMING_CONTROL__WRITE 0xffffffffU + +#endif /* __XPA_TIMING_CONTROL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_xpa_timing_control */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_XPA_TIMING_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::misc_pa_control */ +#ifndef __MISC_PA_CONTROL_MACRO__ +#define __MISC_PA_CONTROL_MACRO__ + +/* macros for field xpaa_active_high */ +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__SHIFT 0 +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__WIDTH 1 +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__MASK 0x00000001U +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field xpab_active_high */ +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__SHIFT 1 +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__WIDTH 1 +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__MASK 0x00000002U +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field enable_xpaa */ +#define MISC_PA_CONTROL__ENABLE_XPAA__SHIFT 2 +#define MISC_PA_CONTROL__ENABLE_XPAA__WIDTH 1 +#define MISC_PA_CONTROL__ENABLE_XPAA__MASK 0x00000004U +#define MISC_PA_CONTROL__ENABLE_XPAA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define MISC_PA_CONTROL__ENABLE_XPAA__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define MISC_PA_CONTROL__ENABLE_XPAA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define MISC_PA_CONTROL__ENABLE_XPAA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define MISC_PA_CONTROL__ENABLE_XPAA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define MISC_PA_CONTROL__ENABLE_XPAA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field enable_xpab */ +#define MISC_PA_CONTROL__ENABLE_XPAB__SHIFT 3 +#define MISC_PA_CONTROL__ENABLE_XPAB__WIDTH 1 +#define MISC_PA_CONTROL__ENABLE_XPAB__MASK 0x00000008U +#define MISC_PA_CONTROL__ENABLE_XPAB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define MISC_PA_CONTROL__ENABLE_XPAB__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define MISC_PA_CONTROL__ENABLE_XPAB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define MISC_PA_CONTROL__ENABLE_XPAB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define MISC_PA_CONTROL__ENABLE_XPAB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define MISC_PA_CONTROL__ENABLE_XPAB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define MISC_PA_CONTROL__TYPE u_int32_t +#define MISC_PA_CONTROL__READ 0x0000000fU +#define MISC_PA_CONTROL__WRITE 0x0000000fU + +#endif /* __MISC_PA_CONTROL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_misc_pa_control */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MISC_PA_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::switch_table_chn_b0 */ +#ifndef __SWITCH_TABLE_CHN_B0_MACRO__ +#define __SWITCH_TABLE_CHN_B0_MACRO__ + +/* macros for field switch_table_idle_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__SHIFT 0 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__MASK 0x00000003U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field switch_table_t_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__SHIFT 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__MASK 0x0000000cU +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field switch_table_r_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__SHIFT 4 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__MASK 0x00000030U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field switch_table_rx1_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__SHIFT 6 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__MASK 0x000000c0U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field switch_table_rx12_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__SHIFT 8 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__MASK 0x00000300U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field switch_table_b_0 */ +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__SHIFT 10 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__WIDTH 2 +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__MASK 0x00000c00U +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) +#define SWITCH_TABLE_CHN_B0__TYPE u_int32_t +#define SWITCH_TABLE_CHN_B0__READ 0x00000fffU +#define SWITCH_TABLE_CHN_B0__WRITE 0x00000fffU + +#endif /* __SWITCH_TABLE_CHN_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_switch_table_chn_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SWITCH_TABLE_CHN_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::switch_table_com1 */ +#ifndef __SWITCH_TABLE_COM1_MACRO__ +#define __SWITCH_TABLE_COM1_MACRO__ + +/* macros for field switch_table_com_idle */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__SHIFT 0 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__MASK 0x0000000fU +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field switch_table_com_t1 */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__SHIFT 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__MASK 0x000000f0U +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field switch_table_com_t2 */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__SHIFT 8 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__MASK 0x00000f00U +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field switch_table_com_b */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__SHIFT 12 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__MASK 0x0000f000U +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field switch_table_com_idle_alt */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__SHIFT 16 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__MASK 0x000f0000U +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field switch_table_com_tx_1chn */ +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__SHIFT 20 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__WIDTH 4 +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__MASK 0x00f00000U +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) +#define SWITCH_TABLE_COM1__TYPE u_int32_t +#define SWITCH_TABLE_COM1__READ 0x00ffffffU +#define SWITCH_TABLE_COM1__WRITE 0x00ffffffU + +#endif /* __SWITCH_TABLE_COM1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_switch_table_com1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SWITCH_TABLE_COM1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::switch_table_com2 */ +#ifndef __SWITCH_TABLE_COM2_MACRO__ +#define __SWITCH_TABLE_COM2_MACRO__ + +/* macros for field switch_table_com_ra1l1 */ +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__SHIFT 0 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__WIDTH 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__MASK 0x0000000fU +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field switch_table_com_ra2l1 */ +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__SHIFT 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__WIDTH 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__MASK 0x000000f0U +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field switch_table_com_ra1l2 */ +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__SHIFT 8 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__WIDTH 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__MASK 0x00000f00U +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field switch_table_com_ra2l2 */ +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__SHIFT 12 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__WIDTH 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__MASK 0x0000f000U +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field switch_table_com_ra12 */ +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__SHIFT 16 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__WIDTH 4 +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__MASK 0x000f0000U +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) +#define SWITCH_TABLE_COM2__TYPE u_int32_t +#define SWITCH_TABLE_COM2__READ 0x000fffffU +#define SWITCH_TABLE_COM2__WRITE 0x000fffffU + +#endif /* __SWITCH_TABLE_COM2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_switch_table_com2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SWITCH_TABLE_COM2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::multichain_enable */ +#ifndef __MULTICHAIN_ENABLE_MACRO__ +#define __MULTICHAIN_ENABLE_MACRO__ + +/* macros for field rx_chain_mask */ +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__SHIFT 0 +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__WIDTH 3 +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__MASK 0x00000007U +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) +#define MULTICHAIN_ENABLE__TYPE u_int32_t +#define MULTICHAIN_ENABLE__READ 0x00000007U +#define MULTICHAIN_ENABLE__WRITE 0x00000007U + +#endif /* __MULTICHAIN_ENABLE_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_multichain_enable */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MULTICHAIN_ENABLE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_chain_mask */ +#ifndef __CAL_CHAIN_MASK_MACRO__ +#define __CAL_CHAIN_MASK_MACRO__ + +/* macros for field cal_chain_mask */ +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__SHIFT 0 +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__WIDTH 3 +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__MASK 0x00000007U +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) +#define CAL_CHAIN_MASK__TYPE u_int32_t +#define CAL_CHAIN_MASK__READ 0x00000007U +#define CAL_CHAIN_MASK__WRITE 0x00000007U + +#endif /* __CAL_CHAIN_MASK_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_chain_mask */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_CHAIN_MASK__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_control */ +#ifndef __AGC_CONTROL_MACRO__ +#define __AGC_CONTROL_MACRO__ + +/* macros for field do_calibrate */ +#define AGC_CONTROL__DO_CALIBRATE__SHIFT 0 +#define AGC_CONTROL__DO_CALIBRATE__WIDTH 1 +#define AGC_CONTROL__DO_CALIBRATE__MASK 0x00000001U +#define AGC_CONTROL__DO_CALIBRATE__READ(src) (u_int32_t)(src) & 0x00000001U +#define AGC_CONTROL__DO_CALIBRATE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define AGC_CONTROL__DO_CALIBRATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define AGC_CONTROL__DO_CALIBRATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define AGC_CONTROL__DO_CALIBRATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define AGC_CONTROL__DO_CALIBRATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field do_noisefloor */ +#define AGC_CONTROL__DO_NOISEFLOOR__SHIFT 1 +#define AGC_CONTROL__DO_NOISEFLOOR__WIDTH 1 +#define AGC_CONTROL__DO_NOISEFLOOR__MASK 0x00000002U +#define AGC_CONTROL__DO_NOISEFLOOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define AGC_CONTROL__DO_NOISEFLOOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define AGC_CONTROL__DO_NOISEFLOOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define AGC_CONTROL__DO_NOISEFLOOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define AGC_CONTROL__DO_NOISEFLOOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define AGC_CONTROL__DO_NOISEFLOOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field min_num_gain_change */ +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__SHIFT 3 +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__WIDTH 3 +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__MASK 0x00000038U +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field ycok_max */ +#define AGC_CONTROL__YCOK_MAX__SHIFT 6 +#define AGC_CONTROL__YCOK_MAX__WIDTH 4 +#define AGC_CONTROL__YCOK_MAX__MASK 0x000003c0U +#define AGC_CONTROL__YCOK_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003c0U) >> 6) +#define AGC_CONTROL__YCOK_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000003c0U) +#define AGC_CONTROL__YCOK_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000003c0U) +#define AGC_CONTROL__YCOK_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000003c0U))) + +/* macros for field leaky_bucket_enable */ +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__SHIFT 10 +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__WIDTH 1 +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__MASK 0x00000400U +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field CAL_enable */ +#define AGC_CONTROL__CAL_ENABLE__SHIFT 11 +#define AGC_CONTROL__CAL_ENABLE__WIDTH 1 +#define AGC_CONTROL__CAL_ENABLE__MASK 0x00000800U +#define AGC_CONTROL__CAL_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define AGC_CONTROL__CAL_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define AGC_CONTROL__CAL_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define AGC_CONTROL__CAL_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define AGC_CONTROL__CAL_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define AGC_CONTROL__CAL_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field use_table_seed */ +#define AGC_CONTROL__USE_TABLE_SEED__SHIFT 12 +#define AGC_CONTROL__USE_TABLE_SEED__WIDTH 1 +#define AGC_CONTROL__USE_TABLE_SEED__MASK 0x00001000U +#define AGC_CONTROL__USE_TABLE_SEED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define AGC_CONTROL__USE_TABLE_SEED__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define AGC_CONTROL__USE_TABLE_SEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define AGC_CONTROL__USE_TABLE_SEED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define AGC_CONTROL__USE_TABLE_SEED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define AGC_CONTROL__USE_TABLE_SEED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field agc_update_table_seed */ +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__SHIFT 13 +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__WIDTH 1 +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__MASK 0x00002000U +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field enable_noisefloor */ +#define AGC_CONTROL__ENABLE_NOISEFLOOR__SHIFT 15 +#define AGC_CONTROL__ENABLE_NOISEFLOOR__WIDTH 1 +#define AGC_CONTROL__ENABLE_NOISEFLOOR__MASK 0x00008000U +#define AGC_CONTROL__ENABLE_NOISEFLOOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define AGC_CONTROL__ENABLE_NOISEFLOOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define AGC_CONTROL__ENABLE_NOISEFLOOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define AGC_CONTROL__ENABLE_NOISEFLOOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define AGC_CONTROL__ENABLE_NOISEFLOOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define AGC_CONTROL__ENABLE_NOISEFLOOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field enable_fltr_cal */ +#define AGC_CONTROL__ENABLE_FLTR_CAL__SHIFT 16 +#define AGC_CONTROL__ENABLE_FLTR_CAL__WIDTH 1 +#define AGC_CONTROL__ENABLE_FLTR_CAL__MASK 0x00010000U +#define AGC_CONTROL__ENABLE_FLTR_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define AGC_CONTROL__ENABLE_FLTR_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define AGC_CONTROL__ENABLE_FLTR_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define AGC_CONTROL__ENABLE_FLTR_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define AGC_CONTROL__ENABLE_FLTR_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define AGC_CONTROL__ENABLE_FLTR_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field no_update_noisefloor */ +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__SHIFT 17 +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__WIDTH 1 +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__MASK 0x00020000U +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field extend_NF_pwr_meas */ +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__SHIFT 18 +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__WIDTH 1 +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__MASK 0x00040000U +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field clc_success */ +#define AGC_CONTROL__CLC_SUCCESS__SHIFT 19 +#define AGC_CONTROL__CLC_SUCCESS__WIDTH 1 +#define AGC_CONTROL__CLC_SUCCESS__MASK 0x00080000U +#define AGC_CONTROL__CLC_SUCCESS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define AGC_CONTROL__CLC_SUCCESS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define AGC_CONTROL__CLC_SUCCESS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field enable_pkdet_cal */ +#define AGC_CONTROL__ENABLE_PKDET_CAL__SHIFT 20 +#define AGC_CONTROL__ENABLE_PKDET_CAL__WIDTH 1 +#define AGC_CONTROL__ENABLE_PKDET_CAL__MASK 0x00100000U +#define AGC_CONTROL__ENABLE_PKDET_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define AGC_CONTROL__ENABLE_PKDET_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define AGC_CONTROL__ENABLE_PKDET_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define AGC_CONTROL__ENABLE_PKDET_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define AGC_CONTROL__ENABLE_PKDET_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define AGC_CONTROL__ENABLE_PKDET_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) +#define AGC_CONTROL__TYPE u_int32_t +#define AGC_CONTROL__READ 0x001fbffbU +#define AGC_CONTROL__WRITE 0x001fbffbU + +#endif /* __AGC_CONTROL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_agc_control */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_AGC_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_cal_mode */ +#ifndef __IQ_ADC_CAL_MODE_MACRO__ +#define __IQ_ADC_CAL_MODE_MACRO__ + +/* macros for field gain_dc_iq_cal_mode */ +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__SHIFT 0 +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__WIDTH 2 +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__MASK 0x00000003U +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field test_caladcoff */ +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__SHIFT 2 +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__WIDTH 1 +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__MASK 0x00000004U +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define IQ_ADC_CAL_MODE__TYPE u_int32_t +#define IQ_ADC_CAL_MODE__READ 0x00000007U +#define IQ_ADC_CAL_MODE__WRITE 0x00000007U + +#endif /* __IQ_ADC_CAL_MODE_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_iq_adc_cal_mode */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_IQ_ADC_CAL_MODE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::fcal_1 */ +#ifndef __FCAL_1_MACRO__ +#define __FCAL_1_MACRO__ + +/* macros for field flc_pb_fstep */ +#define FCAL_1__FLC_PB_FSTEP__SHIFT 0 +#define FCAL_1__FLC_PB_FSTEP__WIDTH 10 +#define FCAL_1__FLC_PB_FSTEP__MASK 0x000003ffU +#define FCAL_1__FLC_PB_FSTEP__READ(src) (u_int32_t)(src) & 0x000003ffU +#define FCAL_1__FLC_PB_FSTEP__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define FCAL_1__FLC_PB_FSTEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define FCAL_1__FLC_PB_FSTEP__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field flc_sb_fstep */ +#define FCAL_1__FLC_SB_FSTEP__SHIFT 10 +#define FCAL_1__FLC_SB_FSTEP__WIDTH 10 +#define FCAL_1__FLC_SB_FSTEP__MASK 0x000ffc00U +#define FCAL_1__FLC_SB_FSTEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define FCAL_1__FLC_SB_FSTEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define FCAL_1__FLC_SB_FSTEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define FCAL_1__FLC_SB_FSTEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field flc_pb_atten */ +#define FCAL_1__FLC_PB_ATTEN__SHIFT 20 +#define FCAL_1__FLC_PB_ATTEN__WIDTH 5 +#define FCAL_1__FLC_PB_ATTEN__MASK 0x01f00000U +#define FCAL_1__FLC_PB_ATTEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define FCAL_1__FLC_PB_ATTEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define FCAL_1__FLC_PB_ATTEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define FCAL_1__FLC_PB_ATTEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field flc_sb_atten */ +#define FCAL_1__FLC_SB_ATTEN__SHIFT 25 +#define FCAL_1__FLC_SB_ATTEN__WIDTH 5 +#define FCAL_1__FLC_SB_ATTEN__MASK 0x3e000000U +#define FCAL_1__FLC_SB_ATTEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define FCAL_1__FLC_SB_ATTEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define FCAL_1__FLC_SB_ATTEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define FCAL_1__FLC_SB_ATTEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define FCAL_1__TYPE u_int32_t +#define FCAL_1__READ 0x3fffffffU +#define FCAL_1__WRITE 0x3fffffffU + +#endif /* __FCAL_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_fcal_1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FCAL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::fcal_2_b0 */ +#ifndef __FCAL_2_B0_MACRO__ +#define __FCAL_2_B0_MACRO__ + +/* macros for field flc_pwr_thresh */ +#define FCAL_2_B0__FLC_PWR_THRESH__SHIFT 0 +#define FCAL_2_B0__FLC_PWR_THRESH__WIDTH 3 +#define FCAL_2_B0__FLC_PWR_THRESH__MASK 0x00000007U +#define FCAL_2_B0__FLC_PWR_THRESH__READ(src) (u_int32_t)(src) & 0x00000007U +#define FCAL_2_B0__FLC_PWR_THRESH__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define FCAL_2_B0__FLC_PWR_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define FCAL_2_B0__FLC_PWR_THRESH__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field flc_sw_cap_val_0 */ +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__SHIFT 3 +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__WIDTH 5 +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__MASK 0x000000f8U +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f8U) >> 3) +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000000f8U) +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000000f8U) +#define FCAL_2_B0__FLC_SW_CAP_VAL_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000000f8U))) + +/* macros for field flc_bbmiscgain */ +#define FCAL_2_B0__FLC_BBMISCGAIN__SHIFT 8 +#define FCAL_2_B0__FLC_BBMISCGAIN__WIDTH 2 +#define FCAL_2_B0__FLC_BBMISCGAIN__MASK 0x00000300U +#define FCAL_2_B0__FLC_BBMISCGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define FCAL_2_B0__FLC_BBMISCGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define FCAL_2_B0__FLC_BBMISCGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define FCAL_2_B0__FLC_BBMISCGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field flc_bb1dbgain */ +#define FCAL_2_B0__FLC_BB1DBGAIN__SHIFT 10 +#define FCAL_2_B0__FLC_BB1DBGAIN__WIDTH 3 +#define FCAL_2_B0__FLC_BB1DBGAIN__MASK 0x00001c00U +#define FCAL_2_B0__FLC_BB1DBGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001c00U) >> 10) +#define FCAL_2_B0__FLC_BB1DBGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00001c00U) +#define FCAL_2_B0__FLC_BB1DBGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00001c00U) +#define FCAL_2_B0__FLC_BB1DBGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00001c00U))) + +/* macros for field flc_bb6dbgain */ +#define FCAL_2_B0__FLC_BB6DBGAIN__SHIFT 13 +#define FCAL_2_B0__FLC_BB6DBGAIN__WIDTH 2 +#define FCAL_2_B0__FLC_BB6DBGAIN__MASK 0x00006000U +#define FCAL_2_B0__FLC_BB6DBGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00006000U) >> 13) +#define FCAL_2_B0__FLC_BB6DBGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00006000U) +#define FCAL_2_B0__FLC_BB6DBGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00006000U) | (((u_int32_t)(src) <<\ + 13) & 0x00006000U) +#define FCAL_2_B0__FLC_BB6DBGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00006000U))) + +/* macros for field flc_sw_cap_set */ +#define FCAL_2_B0__FLC_SW_CAP_SET__SHIFT 15 +#define FCAL_2_B0__FLC_SW_CAP_SET__WIDTH 1 +#define FCAL_2_B0__FLC_SW_CAP_SET__MASK 0x00008000U +#define FCAL_2_B0__FLC_SW_CAP_SET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define FCAL_2_B0__FLC_SW_CAP_SET__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define FCAL_2_B0__FLC_SW_CAP_SET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define FCAL_2_B0__FLC_SW_CAP_SET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define FCAL_2_B0__FLC_SW_CAP_SET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define FCAL_2_B0__FLC_SW_CAP_SET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field flc_meas_win */ +#define FCAL_2_B0__FLC_MEAS_WIN__SHIFT 16 +#define FCAL_2_B0__FLC_MEAS_WIN__WIDTH 3 +#define FCAL_2_B0__FLC_MEAS_WIN__MASK 0x00070000U +#define FCAL_2_B0__FLC_MEAS_WIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define FCAL_2_B0__FLC_MEAS_WIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define FCAL_2_B0__FLC_MEAS_WIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define FCAL_2_B0__FLC_MEAS_WIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field flc_cap_val_status_0 */ +#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__SHIFT 20 +#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__WIDTH 5 +#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__MASK 0x01f00000U +#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define FCAL_2_B0__TYPE u_int32_t +#define FCAL_2_B0__READ 0x01f7ffffU +#define FCAL_2_B0__WRITE 0x01f7ffffU + +#endif /* __FCAL_2_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_fcal_2_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FCAL_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b0 */ +#ifndef __DFT_TONE_CTRL_B0_MACRO__ +#define __DFT_TONE_CTRL_B0_MACRO__ + +/* macros for field dft_tone_en_0 */ +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__SHIFT 0 +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__WIDTH 1 +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__MASK 0x00000001U +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dft_tone_amp_sel_0 */ +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__SHIFT 2 +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__WIDTH 2 +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__MASK 0x0000000cU +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field dft_tone_freq_ang_0 */ +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__SHIFT 4 +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__WIDTH 9 +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__MASK 0x00001ff0U +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001ff0U) >> 4) +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001ff0U) | (((u_int32_t)(src) <<\ + 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00001ff0U))) +#define DFT_TONE_CTRL_B0__TYPE u_int32_t +#define DFT_TONE_CTRL_B0__READ 0x00001ffdU +#define DFT_TONE_CTRL_B0__WRITE 0x00001ffdU + +#endif /* __DFT_TONE_CTRL_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_dft_tone_ctrl_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_DFT_TONE_CTRL_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_cal_ctrl */ +#ifndef __CL_CAL_CTRL_MACRO__ +#define __CL_CAL_CTRL_MACRO__ + +/* macros for field enable_parallel_cal */ +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__SHIFT 0 +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__WIDTH 1 +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__MASK 0x00000001U +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field enable_cl_calibrate */ +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__SHIFT 1 +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__WIDTH 1 +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__MASK 0x00000002U +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field cf_clc_test_point */ +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__SHIFT 2 +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__WIDTH 2 +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__MASK 0x0000000cU +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define CL_CAL_CTRL__CF_CLC_TEST_POINT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field cf_clc_forced_pagain */ +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__SHIFT 4 +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__WIDTH 4 +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__MASK 0x000000f0U +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field carr_leak_max_offset */ +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__SHIFT 8 +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__WIDTH 8 +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__MASK 0x0000ff00U +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field cf_clc_init_bbgain */ +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__SHIFT 16 +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__WIDTH 6 +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__MASK 0x003f0000U +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field cf_adc_bound */ +#define CL_CAL_CTRL__CF_ADC_BOUND__SHIFT 22 +#define CL_CAL_CTRL__CF_ADC_BOUND__WIDTH 8 +#define CL_CAL_CTRL__CF_ADC_BOUND__MASK 0x3fc00000U +#define CL_CAL_CTRL__CF_ADC_BOUND__READ(src) \ + (((u_int32_t)(src)\ + & 0x3fc00000U) >> 22) +#define CL_CAL_CTRL__CF_ADC_BOUND__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x3fc00000U) +#define CL_CAL_CTRL__CF_ADC_BOUND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x3fc00000U) +#define CL_CAL_CTRL__CF_ADC_BOUND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x3fc00000U))) + +/* macros for field use_dac_cl_correction */ +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__SHIFT 30 +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__WIDTH 1 +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__MASK 0x40000000U +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field cl_map_hw_gen */ +#define CL_CAL_CTRL__CL_MAP_HW_GEN__SHIFT 31 +#define CL_CAL_CTRL__CL_MAP_HW_GEN__WIDTH 1 +#define CL_CAL_CTRL__CL_MAP_HW_GEN__MASK 0x80000000U +#define CL_CAL_CTRL__CL_MAP_HW_GEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define CL_CAL_CTRL__CL_MAP_HW_GEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define CL_CAL_CTRL__CL_MAP_HW_GEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define CL_CAL_CTRL__CL_MAP_HW_GEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define CL_CAL_CTRL__CL_MAP_HW_GEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define CL_CAL_CTRL__CL_MAP_HW_GEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define CL_CAL_CTRL__TYPE u_int32_t +#define CL_CAL_CTRL__READ 0xffffffffU +#define CL_CAL_CTRL__WRITE 0xffffffffU + +#endif /* __CL_CAL_CTRL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_cal_ctrl */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_CAL_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_0 */ +#ifndef __CL_MAP_0_MACRO__ +#define __CL_MAP_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_0__TYPE u_int32_t +#define CL_MAP_0__READ 0xffffffffU +#define CL_MAP_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_0_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_0_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_1 */ +#ifndef __CL_MAP_1_MACRO__ +#define __CL_MAP_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_1__TYPE u_int32_t +#define CL_MAP_1__READ 0xffffffffU +#define CL_MAP_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_1_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_1_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_2 */ +#ifndef __CL_MAP_2_MACRO__ +#define __CL_MAP_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_2__TYPE u_int32_t +#define CL_MAP_2__READ 0xffffffffU +#define CL_MAP_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_2_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_3 */ +#ifndef __CL_MAP_3_MACRO__ +#define __CL_MAP_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_3__TYPE u_int32_t +#define CL_MAP_3__READ 0xffffffffU +#define CL_MAP_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_3_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_3_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */ +#ifndef __CL_MAP_PAL_0_MACRO__ +#define __CL_MAP_PAL_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_PAL_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_PAL_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_PAL_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_0__TYPE u_int32_t +#define CL_MAP_PAL_0__READ 0xffffffffU +#define CL_MAP_PAL_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_0_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_0_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */ +#ifndef __CL_MAP_PAL_1_MACRO__ +#define __CL_MAP_PAL_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_PAL_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_PAL_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_PAL_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_1__TYPE u_int32_t +#define CL_MAP_PAL_1__READ 0xffffffffU +#define CL_MAP_PAL_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_1_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_1_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */ +#ifndef __CL_MAP_PAL_2_MACRO__ +#define __CL_MAP_PAL_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_PAL_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_PAL_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_PAL_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_2__TYPE u_int32_t +#define CL_MAP_PAL_2__READ 0xffffffffU +#define CL_MAP_PAL_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_2_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_2_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */ +#ifndef __CL_MAP_PAL_3_MACRO__ +#define __CL_MAP_PAL_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_PAL_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_PAL_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_PAL_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_3__TYPE u_int32_t +#define CL_MAP_PAL_3__READ 0xffffffffU +#define CL_MAP_PAL_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_3_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_3_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_tab */ +#ifndef __CL_TAB_MACRO__ +#define __CL_TAB_MACRO__ + +/* macros for field cl_gain_mod */ +#define CL_TAB__CL_GAIN_MOD__SHIFT 0 +#define CL_TAB__CL_GAIN_MOD__WIDTH 5 +#define CL_TAB__CL_GAIN_MOD__MASK 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field carr_lk_dc_add_Q */ +#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT 5 +#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_Q__MASK 0x0000ffe0U +#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ffe0U) >> 5) +#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffe0U) | (((u_int32_t)(src) <<\ + 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x0000ffe0U))) + +/* macros for field carr_lk_dc_add_I */ +#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT 16 +#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_I__MASK 0x07ff0000U +#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) + +/* macros for field bb_gain */ +#define CL_TAB__BB_GAIN__SHIFT 27 +#define CL_TAB__BB_GAIN__WIDTH 4 +#define CL_TAB__BB_GAIN__MASK 0x78000000U +#define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) +#define CL_TAB__TYPE u_int32_t +#define CL_TAB__READ 0x7fffffffU +#define CL_TAB__WRITE 0x7fffffffU + +#endif /* __CL_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_tab_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_TAB_B0__NUM 16 + +/* macros for BlueprintGlobalNameSpace::synth_control */ +#ifndef __SYNTH_CONTROL_MACRO__ +#define __SYNTH_CONTROL_MACRO__ + +/* macros for field rfchanFrac */ +#define SYNTH_CONTROL__RFCHANFRAC__SHIFT 0 +#define SYNTH_CONTROL__RFCHANFRAC__WIDTH 17 +#define SYNTH_CONTROL__RFCHANFRAC__MASK 0x0001ffffU +#define SYNTH_CONTROL__RFCHANFRAC__READ(src) (u_int32_t)(src) & 0x0001ffffU +#define SYNTH_CONTROL__RFCHANFRAC__WRITE(src) ((u_int32_t)(src) & 0x0001ffffU) +#define SYNTH_CONTROL__RFCHANFRAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ffffU) | ((u_int32_t)(src) &\ + 0x0001ffffU) +#define SYNTH_CONTROL__RFCHANFRAC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0001ffffU))) + +/* macros for field rfchannel */ +#define SYNTH_CONTROL__RFCHANNEL__SHIFT 17 +#define SYNTH_CONTROL__RFCHANNEL__WIDTH 9 +#define SYNTH_CONTROL__RFCHANNEL__MASK 0x03fe0000U +#define SYNTH_CONTROL__RFCHANNEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x03fe0000U) >> 17) +#define SYNTH_CONTROL__RFCHANNEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x03fe0000U) +#define SYNTH_CONTROL__RFCHANNEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x03fe0000U) +#define SYNTH_CONTROL__RFCHANNEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x03fe0000U))) + +/* macros for field rfAmodeRefSel */ +#define SYNTH_CONTROL__RFAMODEREFSEL__SHIFT 26 +#define SYNTH_CONTROL__RFAMODEREFSEL__WIDTH 2 +#define SYNTH_CONTROL__RFAMODEREFSEL__MASK 0x0c000000U +#define SYNTH_CONTROL__RFAMODEREFSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0c000000U) >> 26) +#define SYNTH_CONTROL__RFAMODEREFSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x0c000000U) +#define SYNTH_CONTROL__RFAMODEREFSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define SYNTH_CONTROL__RFAMODEREFSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) + +/* macros for field rfFracmode */ +#define SYNTH_CONTROL__RFFRACMODE__SHIFT 28 +#define SYNTH_CONTROL__RFFRACMODE__WIDTH 1 +#define SYNTH_CONTROL__RFFRACMODE__MASK 0x10000000U +#define SYNTH_CONTROL__RFFRACMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define SYNTH_CONTROL__RFFRACMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define SYNTH_CONTROL__RFFRACMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define SYNTH_CONTROL__RFFRACMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define SYNTH_CONTROL__RFFRACMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define SYNTH_CONTROL__RFFRACMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field rfbmode */ +#define SYNTH_CONTROL__RFBMODE__SHIFT 29 +#define SYNTH_CONTROL__RFBMODE__WIDTH 1 +#define SYNTH_CONTROL__RFBMODE__MASK 0x20000000U +#define SYNTH_CONTROL__RFBMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define SYNTH_CONTROL__RFBMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define SYNTH_CONTROL__RFBMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define SYNTH_CONTROL__RFBMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define SYNTH_CONTROL__RFBMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define SYNTH_CONTROL__RFBMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field rfsynth_ctrl_sshift */ +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__SHIFT 30 +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__WIDTH 1 +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__MASK 0x40000000U +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) +#define SYNTH_CONTROL__TYPE u_int32_t +#define SYNTH_CONTROL__READ 0x7fffffffU +#define SYNTH_CONTROL__WRITE 0x7fffffffU + +#endif /* __SYNTH_CONTROL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_synth_control */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SYNTH_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::addac_clk_select */ +#ifndef __ADDAC_CLK_SELECT_MACRO__ +#define __ADDAC_CLK_SELECT_MACRO__ + +/* macros for field bb_dac_clk_select */ +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__SHIFT 1 +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__WIDTH 3 +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__MASK 0x0000000eU +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field bb_adc_clk_select */ +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__SHIFT 4 +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__WIDTH 4 +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__MASK 0x000000f0U +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) +#define ADDAC_CLK_SELECT__TYPE u_int32_t +#define ADDAC_CLK_SELECT__READ 0x000000feU +#define ADDAC_CLK_SELECT__WRITE 0x000000feU + +#endif /* __ADDAC_CLK_SELECT_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_addac_clk_select */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ADDAC_CLK_SELECT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pll_cntl */ +#ifndef __PLL_CNTL_MACRO__ +#define __PLL_CNTL_MACRO__ + +/* macros for field bb_pll_div */ +#define PLL_CNTL__BB_PLL_DIV__SHIFT 0 +#define PLL_CNTL__BB_PLL_DIV__WIDTH 10 +#define PLL_CNTL__BB_PLL_DIV__MASK 0x000003ffU +#define PLL_CNTL__BB_PLL_DIV__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PLL_CNTL__BB_PLL_DIV__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PLL_CNTL__BB_PLL_DIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PLL_CNTL__BB_PLL_DIV__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field bb_pll_refdiv */ +#define PLL_CNTL__BB_PLL_REFDIV__SHIFT 10 +#define PLL_CNTL__BB_PLL_REFDIV__WIDTH 4 +#define PLL_CNTL__BB_PLL_REFDIV__MASK 0x00003c00U +#define PLL_CNTL__BB_PLL_REFDIV__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003c00U) >> 10) +#define PLL_CNTL__BB_PLL_REFDIV__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00003c00U) +#define PLL_CNTL__BB_PLL_REFDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00003c00U) +#define PLL_CNTL__BB_PLL_REFDIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00003c00U))) + +/* macros for field bb_pll_clk_sel */ +#define PLL_CNTL__BB_PLL_CLK_SEL__SHIFT 14 +#define PLL_CNTL__BB_PLL_CLK_SEL__WIDTH 2 +#define PLL_CNTL__BB_PLL_CLK_SEL__MASK 0x0000c000U +#define PLL_CNTL__BB_PLL_CLK_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000c000U) >> 14) +#define PLL_CNTL__BB_PLL_CLK_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0000c000U) +#define PLL_CNTL__BB_PLL_CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define PLL_CNTL__BB_PLL_CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field bb_pllbypass */ +#define PLL_CNTL__BB_PLLBYPASS__SHIFT 16 +#define PLL_CNTL__BB_PLLBYPASS__WIDTH 1 +#define PLL_CNTL__BB_PLLBYPASS__MASK 0x00010000U +#define PLL_CNTL__BB_PLLBYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define PLL_CNTL__BB_PLLBYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define PLL_CNTL__BB_PLLBYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define PLL_CNTL__BB_PLLBYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define PLL_CNTL__BB_PLLBYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define PLL_CNTL__BB_PLLBYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field bb_pll_settle_time */ +#define PLL_CNTL__BB_PLL_SETTLE_TIME__SHIFT 17 +#define PLL_CNTL__BB_PLL_SETTLE_TIME__WIDTH 11 +#define PLL_CNTL__BB_PLL_SETTLE_TIME__MASK 0x0ffe0000U +#define PLL_CNTL__BB_PLL_SETTLE_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x0ffe0000U) >> 17) +#define PLL_CNTL__BB_PLL_SETTLE_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x0ffe0000U) +#define PLL_CNTL__BB_PLL_SETTLE_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ffe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x0ffe0000U) +#define PLL_CNTL__BB_PLL_SETTLE_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x0ffe0000U))) +#define PLL_CNTL__TYPE u_int32_t +#define PLL_CNTL__READ 0x0fffffffU +#define PLL_CNTL__WRITE 0x0fffffffU + +#endif /* __PLL_CNTL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_pll_cntl */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PLL_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::analog_swap */ +#ifndef __ANALOG_SWAP_MACRO__ +#define __ANALOG_SWAP_MACRO__ + +/* macros for field analog_rx_swap_cntl */ +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__SHIFT 0 +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__WIDTH 3 +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__MASK 0x00000007U +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field analog_tx_swap_cntl */ +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__SHIFT 3 +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__WIDTH 3 +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__MASK 0x00000038U +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000038U) >> 3) +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field swap_alt_chn */ +#define ANALOG_SWAP__SWAP_ALT_CHN__SHIFT 6 +#define ANALOG_SWAP__SWAP_ALT_CHN__WIDTH 1 +#define ANALOG_SWAP__SWAP_ALT_CHN__MASK 0x00000040U +#define ANALOG_SWAP__SWAP_ALT_CHN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define ANALOG_SWAP__SWAP_ALT_CHN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define ANALOG_SWAP__SWAP_ALT_CHN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define ANALOG_SWAP__SWAP_ALT_CHN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define ANALOG_SWAP__SWAP_ALT_CHN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define ANALOG_SWAP__SWAP_ALT_CHN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field analog_dc_dac_polarity */ +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__SHIFT 7 +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__WIDTH 1 +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__MASK 0x00000080U +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field analog_pkdet_dac_polarity */ +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__SHIFT 8 +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__WIDTH 1 +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__MASK 0x00000100U +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) +#define ANALOG_SWAP__TYPE u_int32_t +#define ANALOG_SWAP__READ 0x000001ffU +#define ANALOG_SWAP__WRITE 0x000001ffU + +#endif /* __ANALOG_SWAP_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_analog_swap */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ANALOG_SWAP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::addac_parallel_control */ +#ifndef __ADDAC_PARALLEL_CONTROL_MACRO__ +#define __ADDAC_PARALLEL_CONTROL_MACRO__ + +/* macros for field off_daclpmode */ +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__SHIFT 12 +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__MASK 0x00001000U +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field off_pwdDac */ +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__SHIFT 13 +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__MASK 0x00002000U +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field off_pwdAdc */ +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__SHIFT 15 +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__MASK 0x00008000U +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field on_daclpmode */ +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__SHIFT 28 +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__MASK 0x10000000U +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field on_pwdDac */ +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__SHIFT 29 +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__MASK 0x20000000U +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field on_pwdAdc */ +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__SHIFT 31 +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__WIDTH 1 +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__MASK 0x80000000U +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define ADDAC_PARALLEL_CONTROL__TYPE u_int32_t +#define ADDAC_PARALLEL_CONTROL__READ 0xb000b000U +#define ADDAC_PARALLEL_CONTROL__WRITE 0xb000b000U + +#endif /* __ADDAC_PARALLEL_CONTROL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_addac_parallel_control */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ADDAC_PARALLEL_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::force_analog */ +#ifndef __FORCE_ANALOG_MACRO__ +#define __FORCE_ANALOG_MACRO__ + +/* macros for field force_xpaon */ +#define FORCE_ANALOG__FORCE_XPAON__SHIFT 0 +#define FORCE_ANALOG__FORCE_XPAON__WIDTH 1 +#define FORCE_ANALOG__FORCE_XPAON__MASK 0x00000001U +#define FORCE_ANALOG__FORCE_XPAON__READ(src) (u_int32_t)(src) & 0x00000001U +#define FORCE_ANALOG__FORCE_XPAON__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define FORCE_ANALOG__FORCE_XPAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define FORCE_ANALOG__FORCE_XPAON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define FORCE_ANALOG__FORCE_XPAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define FORCE_ANALOG__FORCE_XPAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field forced_xpaon */ +#define FORCE_ANALOG__FORCED_XPAON__SHIFT 1 +#define FORCE_ANALOG__FORCED_XPAON__WIDTH 3 +#define FORCE_ANALOG__FORCED_XPAON__MASK 0x0000000eU +#define FORCE_ANALOG__FORCED_XPAON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define FORCE_ANALOG__FORCED_XPAON__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define FORCE_ANALOG__FORCED_XPAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define FORCE_ANALOG__FORCED_XPAON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field force_pdadc_pwd */ +#define FORCE_ANALOG__FORCE_PDADC_PWD__SHIFT 4 +#define FORCE_ANALOG__FORCE_PDADC_PWD__WIDTH 1 +#define FORCE_ANALOG__FORCE_PDADC_PWD__MASK 0x00000010U +#define FORCE_ANALOG__FORCE_PDADC_PWD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define FORCE_ANALOG__FORCE_PDADC_PWD__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define FORCE_ANALOG__FORCE_PDADC_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define FORCE_ANALOG__FORCE_PDADC_PWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define FORCE_ANALOG__FORCE_PDADC_PWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define FORCE_ANALOG__FORCE_PDADC_PWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field forced_pdadc_pwd */ +#define FORCE_ANALOG__FORCED_PDADC_PWD__SHIFT 5 +#define FORCE_ANALOG__FORCED_PDADC_PWD__WIDTH 3 +#define FORCE_ANALOG__FORCED_PDADC_PWD__MASK 0x000000e0U +#define FORCE_ANALOG__FORCED_PDADC_PWD__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define FORCE_ANALOG__FORCED_PDADC_PWD__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define FORCE_ANALOG__FORCED_PDADC_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define FORCE_ANALOG__FORCED_PDADC_PWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) +#define FORCE_ANALOG__TYPE u_int32_t +#define FORCE_ANALOG__READ 0x000000ffU +#define FORCE_ANALOG__WRITE 0x000000ffU + +#endif /* __FORCE_ANALOG_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_force_analog */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FORCE_ANALOG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::test_controls */ +#ifndef __TEST_CONTROLS_MACRO__ +#define __TEST_CONTROLS_MACRO__ + +/* macros for field cf_tsttrig_sel */ +#define TEST_CONTROLS__CF_TSTTRIG_SEL__SHIFT 0 +#define TEST_CONTROLS__CF_TSTTRIG_SEL__WIDTH 4 +#define TEST_CONTROLS__CF_TSTTRIG_SEL__MASK 0x0000000fU +#define TEST_CONTROLS__CF_TSTTRIG_SEL__READ(src) (u_int32_t)(src) & 0x0000000fU +#define TEST_CONTROLS__CF_TSTTRIG_SEL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define TEST_CONTROLS__CF_TSTTRIG_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define TEST_CONTROLS__CF_TSTTRIG_SEL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field cf_tsttrig */ +#define TEST_CONTROLS__CF_TSTTRIG__SHIFT 4 +#define TEST_CONTROLS__CF_TSTTRIG__WIDTH 1 +#define TEST_CONTROLS__CF_TSTTRIG__MASK 0x00000010U +#define TEST_CONTROLS__CF_TSTTRIG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define TEST_CONTROLS__CF_TSTTRIG__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define TEST_CONTROLS__CF_TSTTRIG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define TEST_CONTROLS__CF_TSTTRIG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define TEST_CONTROLS__CF_TSTTRIG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define TEST_CONTROLS__CF_TSTTRIG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field cf_rfshift_sel */ +#define TEST_CONTROLS__CF_RFSHIFT_SEL__SHIFT 5 +#define TEST_CONTROLS__CF_RFSHIFT_SEL__WIDTH 2 +#define TEST_CONTROLS__CF_RFSHIFT_SEL__MASK 0x00000060U +#define TEST_CONTROLS__CF_RFSHIFT_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000060U) >> 5) +#define TEST_CONTROLS__CF_RFSHIFT_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000060U) +#define TEST_CONTROLS__CF_RFSHIFT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((u_int32_t)(src) <<\ + 5) & 0x00000060U) +#define TEST_CONTROLS__CF_RFSHIFT_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000060U))) + +/* macros for field cardbus_mode */ +#define TEST_CONTROLS__CARDBUS_MODE__SHIFT 8 +#define TEST_CONTROLS__CARDBUS_MODE__WIDTH 2 +#define TEST_CONTROLS__CARDBUS_MODE__MASK 0x00000300U +#define TEST_CONTROLS__CARDBUS_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define TEST_CONTROLS__CARDBUS_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define TEST_CONTROLS__CARDBUS_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define TEST_CONTROLS__CARDBUS_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field clkout_is_clk32 */ +#define TEST_CONTROLS__CLKOUT_IS_CLK32__SHIFT 10 +#define TEST_CONTROLS__CLKOUT_IS_CLK32__WIDTH 1 +#define TEST_CONTROLS__CLKOUT_IS_CLK32__MASK 0x00000400U +#define TEST_CONTROLS__CLKOUT_IS_CLK32__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define TEST_CONTROLS__CLKOUT_IS_CLK32__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define TEST_CONTROLS__CLKOUT_IS_CLK32__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TEST_CONTROLS__CLKOUT_IS_CLK32__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TEST_CONTROLS__CLKOUT_IS_CLK32__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TEST_CONTROLS__CLKOUT_IS_CLK32__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field enable_rfsilent_bb */ +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__SHIFT 13 +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__WIDTH 1 +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__MASK 0x00002000U +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TEST_CONTROLS__ENABLE_RFSILENT_BB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field enable_mini_obs */ +#define TEST_CONTROLS__ENABLE_MINI_OBS__SHIFT 15 +#define TEST_CONTROLS__ENABLE_MINI_OBS__WIDTH 1 +#define TEST_CONTROLS__ENABLE_MINI_OBS__MASK 0x00008000U +#define TEST_CONTROLS__ENABLE_MINI_OBS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TEST_CONTROLS__ENABLE_MINI_OBS__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TEST_CONTROLS__ENABLE_MINI_OBS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TEST_CONTROLS__ENABLE_MINI_OBS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TEST_CONTROLS__ENABLE_MINI_OBS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TEST_CONTROLS__ENABLE_MINI_OBS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field slow_clk160 */ +#define TEST_CONTROLS__SLOW_CLK160__SHIFT 17 +#define TEST_CONTROLS__SLOW_CLK160__WIDTH 1 +#define TEST_CONTROLS__SLOW_CLK160__MASK 0x00020000U +#define TEST_CONTROLS__SLOW_CLK160__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define TEST_CONTROLS__SLOW_CLK160__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define TEST_CONTROLS__SLOW_CLK160__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define TEST_CONTROLS__SLOW_CLK160__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define TEST_CONTROLS__SLOW_CLK160__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define TEST_CONTROLS__SLOW_CLK160__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field agc_obs_sel_3 */ +#define TEST_CONTROLS__AGC_OBS_SEL_3__SHIFT 18 +#define TEST_CONTROLS__AGC_OBS_SEL_3__WIDTH 1 +#define TEST_CONTROLS__AGC_OBS_SEL_3__MASK 0x00040000U +#define TEST_CONTROLS__AGC_OBS_SEL_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define TEST_CONTROLS__AGC_OBS_SEL_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define TEST_CONTROLS__AGC_OBS_SEL_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define TEST_CONTROLS__AGC_OBS_SEL_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define TEST_CONTROLS__AGC_OBS_SEL_3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define TEST_CONTROLS__AGC_OBS_SEL_3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field cf_bbb_obs_sel */ +#define TEST_CONTROLS__CF_BBB_OBS_SEL__SHIFT 19 +#define TEST_CONTROLS__CF_BBB_OBS_SEL__WIDTH 4 +#define TEST_CONTROLS__CF_BBB_OBS_SEL__MASK 0x00780000U +#define TEST_CONTROLS__CF_BBB_OBS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00780000U) >> 19) +#define TEST_CONTROLS__CF_BBB_OBS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00780000U) +#define TEST_CONTROLS__CF_BBB_OBS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00780000U) | (((u_int32_t)(src) <<\ + 19) & 0x00780000U) +#define TEST_CONTROLS__CF_BBB_OBS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00780000U))) + +/* macros for field rx_obs_sel_5th_bit */ +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__SHIFT 23 +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__WIDTH 1 +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__MASK 0x00800000U +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field agc_obs_sel_4 */ +#define TEST_CONTROLS__AGC_OBS_SEL_4__SHIFT 24 +#define TEST_CONTROLS__AGC_OBS_SEL_4__WIDTH 1 +#define TEST_CONTROLS__AGC_OBS_SEL_4__MASK 0x01000000U +#define TEST_CONTROLS__AGC_OBS_SEL_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TEST_CONTROLS__AGC_OBS_SEL_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TEST_CONTROLS__AGC_OBS_SEL_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TEST_CONTROLS__AGC_OBS_SEL_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TEST_CONTROLS__AGC_OBS_SEL_4__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TEST_CONTROLS__AGC_OBS_SEL_4__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field force_agc_clear */ +#define TEST_CONTROLS__FORCE_AGC_CLEAR__SHIFT 28 +#define TEST_CONTROLS__FORCE_AGC_CLEAR__WIDTH 1 +#define TEST_CONTROLS__FORCE_AGC_CLEAR__MASK 0x10000000U +#define TEST_CONTROLS__FORCE_AGC_CLEAR__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define TEST_CONTROLS__FORCE_AGC_CLEAR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TEST_CONTROLS__FORCE_AGC_CLEAR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TEST_CONTROLS__FORCE_AGC_CLEAR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TEST_CONTROLS__FORCE_AGC_CLEAR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TEST_CONTROLS__FORCE_AGC_CLEAR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field tstdac_out_sel */ +#define TEST_CONTROLS__TSTDAC_OUT_SEL__SHIFT 30 +#define TEST_CONTROLS__TSTDAC_OUT_SEL__WIDTH 2 +#define TEST_CONTROLS__TSTDAC_OUT_SEL__MASK 0xc0000000U +#define TEST_CONTROLS__TSTDAC_OUT_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define TEST_CONTROLS__TSTDAC_OUT_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define TEST_CONTROLS__TSTDAC_OUT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define TEST_CONTROLS__TSTDAC_OUT_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define TEST_CONTROLS__TYPE u_int32_t +#define TEST_CONTROLS__READ 0xd1fea77fU +#define TEST_CONTROLS__WRITE 0xd1fea77fU + +#endif /* __TEST_CONTROLS_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_test_controls */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TEST_CONTROLS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::test_controls_status */ +#ifndef __TEST_CONTROLS_STATUS_MACRO__ +#define __TEST_CONTROLS_STATUS_MACRO__ + +/* macros for field cf_tstdac_en */ +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__SHIFT 0 +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__MASK 0x00000001U +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_tx_src_is_tstdac */ +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__SHIFT 1 +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__MASK 0x00000002U +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field cf_tx_obs_sel */ +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__SHIFT 2 +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__WIDTH 3 +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__MASK 0x0000001cU +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field cf_tx_obs_mux_sel */ +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__SHIFT 5 +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__WIDTH 2 +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__MASK 0x00000060U +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000060U) >> 5) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000060U) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((u_int32_t)(src) <<\ + 5) & 0x00000060U) +#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000060U))) + +/* macros for field cf_tx_src_alternate */ +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__SHIFT 7 +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__MASK 0x00000080U +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field cf_tstadc_en */ +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__SHIFT 8 +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__MASK 0x00000100U +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field cf_rx_src_is_tstadc */ +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__SHIFT 9 +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__MASK 0x00000200U +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field rx_obs_sel */ +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__SHIFT 10 +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__WIDTH 4 +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__MASK 0x00003c00U +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003c00U) >> 10) +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00003c00U) +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00003c00U) +#define TEST_CONTROLS_STATUS__RX_OBS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00003c00U))) + +/* macros for field disable_a2_warm_reset */ +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__SHIFT 14 +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__WIDTH 1 +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__MASK 0x00004000U +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field reset_a2 */ +#define TEST_CONTROLS_STATUS__RESET_A2__SHIFT 15 +#define TEST_CONTROLS_STATUS__RESET_A2__WIDTH 1 +#define TEST_CONTROLS_STATUS__RESET_A2__MASK 0x00008000U +#define TEST_CONTROLS_STATUS__RESET_A2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TEST_CONTROLS_STATUS__RESET_A2__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TEST_CONTROLS_STATUS__RESET_A2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TEST_CONTROLS_STATUS__RESET_A2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TEST_CONTROLS_STATUS__RESET_A2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TEST_CONTROLS_STATUS__RESET_A2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field agc_obs_sel */ +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__SHIFT 16 +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__WIDTH 3 +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__MASK 0x00070000U +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field cf_enable_fft_dump */ +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__SHIFT 19 +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__MASK 0x00080000U +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field cf_debugport_in */ +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__SHIFT 23 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__MASK 0x00800000U +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field disable_agc_to_a2 */ +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__SHIFT 27 +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__WIDTH 1 +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__MASK 0x08000000U +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field cf_debugport_en */ +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__SHIFT 28 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__WIDTH 1 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__MASK 0x10000000U +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field cf_debugport_sel */ +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__SHIFT 29 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__WIDTH 3 +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__MASK 0xe0000000U +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define TEST_CONTROLS_STATUS__TYPE u_int32_t +#define TEST_CONTROLS_STATUS__READ 0xf88fffffU +#define TEST_CONTROLS_STATUS__WRITE 0xf88fffffU + +#endif /* __TEST_CONTROLS_STATUS_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_test_controls_status */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TEST_CONTROLS_STATUS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tstdac */ +#ifndef __TSTDAC_MACRO__ +#define __TSTDAC_MACRO__ + +/* macros for field tstdac_out_q */ +#define TSTDAC__TSTDAC_OUT_Q__SHIFT 0 +#define TSTDAC__TSTDAC_OUT_Q__WIDTH 10 +#define TSTDAC__TSTDAC_OUT_Q__MASK 0x000003ffU +#define TSTDAC__TSTDAC_OUT_Q__READ(src) (u_int32_t)(src) & 0x000003ffU + +/* macros for field tstdac_out_i */ +#define TSTDAC__TSTDAC_OUT_I__SHIFT 10 +#define TSTDAC__TSTDAC_OUT_I__WIDTH 10 +#define TSTDAC__TSTDAC_OUT_I__MASK 0x000ffc00U +#define TSTDAC__TSTDAC_OUT_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define TSTDAC__TYPE u_int32_t +#define TSTDAC__READ 0x000fffffU + +#endif /* __TSTDAC_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tstdac */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TSTDAC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::channel_status */ +#ifndef __CHANNEL_STATUS_MACRO__ +#define __CHANNEL_STATUS_MACRO__ + +/* macros for field bt_active */ +#define CHANNEL_STATUS__BT_ACTIVE__SHIFT 0 +#define CHANNEL_STATUS__BT_ACTIVE__WIDTH 1 +#define CHANNEL_STATUS__BT_ACTIVE__MASK 0x00000001U +#define CHANNEL_STATUS__BT_ACTIVE__READ(src) (u_int32_t)(src) & 0x00000001U +#define CHANNEL_STATUS__BT_ACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define CHANNEL_STATUS__BT_ACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field rx_clear_raw */ +#define CHANNEL_STATUS__RX_CLEAR_RAW__SHIFT 1 +#define CHANNEL_STATUS__RX_CLEAR_RAW__WIDTH 1 +#define CHANNEL_STATUS__RX_CLEAR_RAW__MASK 0x00000002U +#define CHANNEL_STATUS__RX_CLEAR_RAW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define CHANNEL_STATUS__RX_CLEAR_RAW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define CHANNEL_STATUS__RX_CLEAR_RAW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field rx_clear_mac */ +#define CHANNEL_STATUS__RX_CLEAR_MAC__SHIFT 2 +#define CHANNEL_STATUS__RX_CLEAR_MAC__WIDTH 1 +#define CHANNEL_STATUS__RX_CLEAR_MAC__MASK 0x00000004U +#define CHANNEL_STATUS__RX_CLEAR_MAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define CHANNEL_STATUS__RX_CLEAR_MAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define CHANNEL_STATUS__RX_CLEAR_MAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field rx_clear_pad */ +#define CHANNEL_STATUS__RX_CLEAR_PAD__SHIFT 3 +#define CHANNEL_STATUS__RX_CLEAR_PAD__WIDTH 1 +#define CHANNEL_STATUS__RX_CLEAR_PAD__MASK 0x00000008U +#define CHANNEL_STATUS__RX_CLEAR_PAD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define CHANNEL_STATUS__RX_CLEAR_PAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define CHANNEL_STATUS__RX_CLEAR_PAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field bb_sw_out_0 */ +#define CHANNEL_STATUS__BB_SW_OUT_0__SHIFT 4 +#define CHANNEL_STATUS__BB_SW_OUT_0__WIDTH 2 +#define CHANNEL_STATUS__BB_SW_OUT_0__MASK 0x00000030U +#define CHANNEL_STATUS__BB_SW_OUT_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) + +/* macros for field bb_sw_out_1 */ +#define CHANNEL_STATUS__BB_SW_OUT_1__SHIFT 6 +#define CHANNEL_STATUS__BB_SW_OUT_1__WIDTH 2 +#define CHANNEL_STATUS__BB_SW_OUT_1__MASK 0x000000c0U +#define CHANNEL_STATUS__BB_SW_OUT_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) + +/* macros for field bb_sw_out_2 */ +#define CHANNEL_STATUS__BB_SW_OUT_2__SHIFT 8 +#define CHANNEL_STATUS__BB_SW_OUT_2__WIDTH 2 +#define CHANNEL_STATUS__BB_SW_OUT_2__MASK 0x00000300U +#define CHANNEL_STATUS__BB_SW_OUT_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) + +/* macros for field bb_sw_com_out */ +#define CHANNEL_STATUS__BB_SW_COM_OUT__SHIFT 10 +#define CHANNEL_STATUS__BB_SW_COM_OUT__WIDTH 4 +#define CHANNEL_STATUS__BB_SW_COM_OUT__MASK 0x00003c00U +#define CHANNEL_STATUS__BB_SW_COM_OUT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003c00U) >> 10) + +/* macros for field ant_div_cfg_used */ +#define CHANNEL_STATUS__ANT_DIV_CFG_USED__SHIFT 14 +#define CHANNEL_STATUS__ANT_DIV_CFG_USED__WIDTH 3 +#define CHANNEL_STATUS__ANT_DIV_CFG_USED__MASK 0x0001c000U +#define CHANNEL_STATUS__ANT_DIV_CFG_USED__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define CHANNEL_STATUS__TYPE u_int32_t +#define CHANNEL_STATUS__READ 0x0001ffffU + +#endif /* __CHANNEL_STATUS_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_channel_status */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHANNEL_STATUS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chaninfo_ctrl */ +#ifndef __CHANINFO_CTRL_MACRO__ +#define __CHANINFO_CTRL_MACRO__ + +/* macros for field capture_chan_info */ +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__SHIFT 0 +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__WIDTH 1 +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__MASK 0x00000001U +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field disable_chaninfomem */ +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__SHIFT 1 +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__WIDTH 1 +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__MASK 0x00000002U +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field capture_sounding_packet */ +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__SHIFT 2 +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__WIDTH 1 +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__MASK 0x00000004U +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field chaninfomem_s2_read */ +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__SHIFT 3 +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__WIDTH 1 +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__MASK 0x00000008U +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) +#define CHANINFO_CTRL__TYPE u_int32_t +#define CHANINFO_CTRL__READ 0x0000000fU +#define CHANINFO_CTRL__WRITE 0x0000000fU + +#endif /* __CHANINFO_CTRL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_chaninfo_ctrl */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHANINFO_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chan_info_noise_pwr */ +#ifndef __CHAN_INFO_NOISE_PWR_MACRO__ +#define __CHAN_INFO_NOISE_PWR_MACRO__ + +/* macros for field noise_power */ +#define CHAN_INFO_NOISE_PWR__NOISE_POWER__SHIFT 0 +#define CHAN_INFO_NOISE_PWR__NOISE_POWER__WIDTH 12 +#define CHAN_INFO_NOISE_PWR__NOISE_POWER__MASK 0x00000fffU +#define CHAN_INFO_NOISE_PWR__NOISE_POWER__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define CHAN_INFO_NOISE_PWR__TYPE u_int32_t +#define CHAN_INFO_NOISE_PWR__READ 0x00000fffU + +#endif /* __CHAN_INFO_NOISE_PWR_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_noise_pwr */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_NOISE_PWR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chan_info_gain_diff */ +#ifndef __CHAN_INFO_GAIN_DIFF_MACRO__ +#define __CHAN_INFO_GAIN_DIFF_MACRO__ + +/* macros for field fine_ppm */ +#define CHAN_INFO_GAIN_DIFF__FINE_PPM__SHIFT 0 +#define CHAN_INFO_GAIN_DIFF__FINE_PPM__WIDTH 12 +#define CHAN_INFO_GAIN_DIFF__FINE_PPM__MASK 0x00000fffU +#define CHAN_INFO_GAIN_DIFF__FINE_PPM__READ(src) (u_int32_t)(src) & 0x00000fffU + +/* macros for field analog_gain_diff_01 */ +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__SHIFT 12 +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__WIDTH 7 +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__MASK 0x0007f000U +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__READ(src) \ + (((u_int32_t)(src)\ + & 0x0007f000U) >> 12) + +/* macros for field analog_gain_diff_02 */ +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__SHIFT 19 +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__WIDTH 7 +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__MASK 0x03f80000U +#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__READ(src) \ + (((u_int32_t)(src)\ + & 0x03f80000U) >> 19) +#define CHAN_INFO_GAIN_DIFF__TYPE u_int32_t +#define CHAN_INFO_GAIN_DIFF__READ 0x03ffffffU + +#endif /* __CHAN_INFO_GAIN_DIFF_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_gain_diff */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_GAIN_DIFF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chan_info_fine_timing */ +#ifndef __CHAN_INFO_FINE_TIMING_MACRO__ +#define __CHAN_INFO_FINE_TIMING_MACRO__ + +/* macros for field coarse_ppm */ +#define CHAN_INFO_FINE_TIMING__COARSE_PPM__SHIFT 0 +#define CHAN_INFO_FINE_TIMING__COARSE_PPM__WIDTH 12 +#define CHAN_INFO_FINE_TIMING__COARSE_PPM__MASK 0x00000fffU +#define CHAN_INFO_FINE_TIMING__COARSE_PPM__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU + +/* macros for field fine_timing */ +#define CHAN_INFO_FINE_TIMING__FINE_TIMING__SHIFT 12 +#define CHAN_INFO_FINE_TIMING__FINE_TIMING__WIDTH 10 +#define CHAN_INFO_FINE_TIMING__FINE_TIMING__MASK 0x003ff000U +#define CHAN_INFO_FINE_TIMING__FINE_TIMING__READ(src) \ + (((u_int32_t)(src)\ + & 0x003ff000U) >> 12) +#define CHAN_INFO_FINE_TIMING__TYPE u_int32_t +#define CHAN_INFO_FINE_TIMING__READ 0x003fffffU + +#endif /* __CHAN_INFO_FINE_TIMING_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_fine_timing */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_FINE_TIMING__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chan_info_gain_b0 */ +#ifndef __CHAN_INFO_GAIN_B0_MACRO__ +#define __CHAN_INFO_GAIN_B0_MACRO__ + +/* macros for field chan_info_rssi_0 */ +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__SHIFT 0 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__WIDTH 8 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__MASK 0x000000ffU +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field chan_info_rf_gain_0 */ +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__SHIFT 8 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__WIDTH 8 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__MASK 0x0000ff00U +#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field chan_info_mb_gain_0 */ +#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__SHIFT 16 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__WIDTH 7 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__MASK 0x007f0000U +#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) + +/* macros for field chan_info_xatten1_sw_0 */ +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__SHIFT 23 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__WIDTH 1 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__MASK 0x00800000U +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field chan_info_xatten2_sw_0 */ +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__SHIFT 24 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__WIDTH 1 +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__MASK 0x01000000U +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define CHAN_INFO_GAIN_B0__TYPE u_int32_t +#define CHAN_INFO_GAIN_B0__READ 0x01ffffffU + +#endif /* __CHAN_INFO_GAIN_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_gain_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_GAIN_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::scrambler_seed */ +#ifndef __SCRAMBLER_SEED_MACRO__ +#define __SCRAMBLER_SEED_MACRO__ + +/* macros for field fixed_scrambler_seed */ +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__SHIFT 0 +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__WIDTH 7 +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__MASK 0x0000007fU +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) +#define SCRAMBLER_SEED__TYPE u_int32_t +#define SCRAMBLER_SEED__READ 0x0000007fU +#define SCRAMBLER_SEED__WRITE 0x0000007fU + +#endif /* __SCRAMBLER_SEED_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_scrambler_seed */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SCRAMBLER_SEED__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_tx_ctrl */ +#ifndef __BBB_TX_CTRL_MACRO__ +#define __BBB_TX_CTRL_MACRO__ + +/* macros for field disable_scrambler */ +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__SHIFT 0 +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__WIDTH 1 +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__MASK 0x00000001U +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BBB_TX_CTRL__DISABLE_SCRAMBLER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field use_scrambler_seed */ +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__SHIFT 1 +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__WIDTH 1 +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__MASK 0x00000002U +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field tx_dac_scale_cck */ +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__SHIFT 2 +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__WIDTH 2 +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__MASK 0x0000000cU +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field txfir_japan_cck */ +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__SHIFT 4 +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__WIDTH 1 +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__MASK 0x00000010U +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field allow_1mbps_short */ +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__SHIFT 5 +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__WIDTH 1 +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__MASK 0x00000020U +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field tx_cck_delay_1 */ +#define BBB_TX_CTRL__TX_CCK_DELAY_1__SHIFT 6 +#define BBB_TX_CTRL__TX_CCK_DELAY_1__WIDTH 3 +#define BBB_TX_CTRL__TX_CCK_DELAY_1__MASK 0x000001c0U +#define BBB_TX_CTRL__TX_CCK_DELAY_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001c0U) >> 6) +#define BBB_TX_CTRL__TX_CCK_DELAY_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000001c0U) +#define BBB_TX_CTRL__TX_CCK_DELAY_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define BBB_TX_CTRL__TX_CCK_DELAY_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field tx_cck_delay_2 */ +#define BBB_TX_CTRL__TX_CCK_DELAY_2__SHIFT 9 +#define BBB_TX_CTRL__TX_CCK_DELAY_2__WIDTH 3 +#define BBB_TX_CTRL__TX_CCK_DELAY_2__MASK 0x00000e00U +#define BBB_TX_CTRL__TX_CCK_DELAY_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000e00U) >> 9) +#define BBB_TX_CTRL__TX_CCK_DELAY_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define BBB_TX_CTRL__TX_CCK_DELAY_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define BBB_TX_CTRL__TX_CCK_DELAY_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) +#define BBB_TX_CTRL__TYPE u_int32_t +#define BBB_TX_CTRL__READ 0x00000fffU +#define BBB_TX_CTRL__WRITE 0x00000fffU + +#endif /* __BBB_TX_CTRL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_tx_ctrl */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TX_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_txfir_0 */ +#ifndef __BBB_TXFIR_0_MACRO__ +#define __BBB_TXFIR_0_MACRO__ + +/* macros for field txfir_coeff_h0 */ +#define BBB_TXFIR_0__TXFIR_COEFF_H0__SHIFT 0 +#define BBB_TXFIR_0__TXFIR_COEFF_H0__WIDTH 4 +#define BBB_TXFIR_0__TXFIR_COEFF_H0__MASK 0x0000000fU +#define BBB_TXFIR_0__TXFIR_COEFF_H0__READ(src) (u_int32_t)(src) & 0x0000000fU +#define BBB_TXFIR_0__TXFIR_COEFF_H0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define BBB_TXFIR_0__TXFIR_COEFF_H0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define BBB_TXFIR_0__TXFIR_COEFF_H0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field txfir_coeff_h1 */ +#define BBB_TXFIR_0__TXFIR_COEFF_H1__SHIFT 8 +#define BBB_TXFIR_0__TXFIR_COEFF_H1__WIDTH 4 +#define BBB_TXFIR_0__TXFIR_COEFF_H1__MASK 0x00000f00U +#define BBB_TXFIR_0__TXFIR_COEFF_H1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define BBB_TXFIR_0__TXFIR_COEFF_H1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define BBB_TXFIR_0__TXFIR_COEFF_H1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define BBB_TXFIR_0__TXFIR_COEFF_H1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field txfir_coeff_h2 */ +#define BBB_TXFIR_0__TXFIR_COEFF_H2__SHIFT 16 +#define BBB_TXFIR_0__TXFIR_COEFF_H2__WIDTH 5 +#define BBB_TXFIR_0__TXFIR_COEFF_H2__MASK 0x001f0000U +#define BBB_TXFIR_0__TXFIR_COEFF_H2__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define BBB_TXFIR_0__TXFIR_COEFF_H2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define BBB_TXFIR_0__TXFIR_COEFF_H2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define BBB_TXFIR_0__TXFIR_COEFF_H2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) + +/* macros for field txfir_coeff_h3 */ +#define BBB_TXFIR_0__TXFIR_COEFF_H3__SHIFT 24 +#define BBB_TXFIR_0__TXFIR_COEFF_H3__WIDTH 5 +#define BBB_TXFIR_0__TXFIR_COEFF_H3__MASK 0x1f000000U +#define BBB_TXFIR_0__TXFIR_COEFF_H3__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f000000U) >> 24) +#define BBB_TXFIR_0__TXFIR_COEFF_H3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x1f000000U) +#define BBB_TXFIR_0__TXFIR_COEFF_H3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x1f000000U) +#define BBB_TXFIR_0__TXFIR_COEFF_H3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x1f000000U))) +#define BBB_TXFIR_0__TYPE u_int32_t +#define BBB_TXFIR_0__READ 0x1f1f0f0fU +#define BBB_TXFIR_0__WRITE 0x1f1f0f0fU + +#endif /* __BBB_TXFIR_0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_txfir_0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TXFIR_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_txfir_1 */ +#ifndef __BBB_TXFIR_1_MACRO__ +#define __BBB_TXFIR_1_MACRO__ + +/* macros for field txfir_coeff_h4 */ +#define BBB_TXFIR_1__TXFIR_COEFF_H4__SHIFT 0 +#define BBB_TXFIR_1__TXFIR_COEFF_H4__WIDTH 6 +#define BBB_TXFIR_1__TXFIR_COEFF_H4__MASK 0x0000003fU +#define BBB_TXFIR_1__TXFIR_COEFF_H4__READ(src) (u_int32_t)(src) & 0x0000003fU +#define BBB_TXFIR_1__TXFIR_COEFF_H4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define BBB_TXFIR_1__TXFIR_COEFF_H4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define BBB_TXFIR_1__TXFIR_COEFF_H4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field txfir_coeff_h5 */ +#define BBB_TXFIR_1__TXFIR_COEFF_H5__SHIFT 8 +#define BBB_TXFIR_1__TXFIR_COEFF_H5__WIDTH 6 +#define BBB_TXFIR_1__TXFIR_COEFF_H5__MASK 0x00003f00U +#define BBB_TXFIR_1__TXFIR_COEFF_H5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define BBB_TXFIR_1__TXFIR_COEFF_H5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define BBB_TXFIR_1__TXFIR_COEFF_H5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define BBB_TXFIR_1__TXFIR_COEFF_H5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field txfir_coeff_h6 */ +#define BBB_TXFIR_1__TXFIR_COEFF_H6__SHIFT 16 +#define BBB_TXFIR_1__TXFIR_COEFF_H6__WIDTH 7 +#define BBB_TXFIR_1__TXFIR_COEFF_H6__MASK 0x007f0000U +#define BBB_TXFIR_1__TXFIR_COEFF_H6__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) +#define BBB_TXFIR_1__TXFIR_COEFF_H6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x007f0000U) +#define BBB_TXFIR_1__TXFIR_COEFF_H6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x007f0000U) +#define BBB_TXFIR_1__TXFIR_COEFF_H6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x007f0000U))) + +/* macros for field txfir_coeff_h7 */ +#define BBB_TXFIR_1__TXFIR_COEFF_H7__SHIFT 24 +#define BBB_TXFIR_1__TXFIR_COEFF_H7__WIDTH 7 +#define BBB_TXFIR_1__TXFIR_COEFF_H7__MASK 0x7f000000U +#define BBB_TXFIR_1__TXFIR_COEFF_H7__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f000000U) >> 24) +#define BBB_TXFIR_1__TXFIR_COEFF_H7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define BBB_TXFIR_1__TXFIR_COEFF_H7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define BBB_TXFIR_1__TXFIR_COEFF_H7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) +#define BBB_TXFIR_1__TYPE u_int32_t +#define BBB_TXFIR_1__READ 0x7f7f3f3fU +#define BBB_TXFIR_1__WRITE 0x7f7f3f3fU + +#endif /* __BBB_TXFIR_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_txfir_1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TXFIR_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bbb_txfir_2 */ +#ifndef __BBB_TXFIR_2_MACRO__ +#define __BBB_TXFIR_2_MACRO__ + +/* macros for field txfir_coeff_h8 */ +#define BBB_TXFIR_2__TXFIR_COEFF_H8__SHIFT 0 +#define BBB_TXFIR_2__TXFIR_COEFF_H8__WIDTH 8 +#define BBB_TXFIR_2__TXFIR_COEFF_H8__MASK 0x000000ffU +#define BBB_TXFIR_2__TXFIR_COEFF_H8__READ(src) (u_int32_t)(src) & 0x000000ffU +#define BBB_TXFIR_2__TXFIR_COEFF_H8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define BBB_TXFIR_2__TXFIR_COEFF_H8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define BBB_TXFIR_2__TXFIR_COEFF_H8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txfir_coeff_h9 */ +#define BBB_TXFIR_2__TXFIR_COEFF_H9__SHIFT 8 +#define BBB_TXFIR_2__TXFIR_COEFF_H9__WIDTH 8 +#define BBB_TXFIR_2__TXFIR_COEFF_H9__MASK 0x0000ff00U +#define BBB_TXFIR_2__TXFIR_COEFF_H9__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define BBB_TXFIR_2__TXFIR_COEFF_H9__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define BBB_TXFIR_2__TXFIR_COEFF_H9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define BBB_TXFIR_2__TXFIR_COEFF_H9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txfir_coeff_h10 */ +#define BBB_TXFIR_2__TXFIR_COEFF_H10__SHIFT 16 +#define BBB_TXFIR_2__TXFIR_COEFF_H10__WIDTH 8 +#define BBB_TXFIR_2__TXFIR_COEFF_H10__MASK 0x00ff0000U +#define BBB_TXFIR_2__TXFIR_COEFF_H10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define BBB_TXFIR_2__TXFIR_COEFF_H10__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define BBB_TXFIR_2__TXFIR_COEFF_H10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define BBB_TXFIR_2__TXFIR_COEFF_H10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txfir_coeff_h11 */ +#define BBB_TXFIR_2__TXFIR_COEFF_H11__SHIFT 24 +#define BBB_TXFIR_2__TXFIR_COEFF_H11__WIDTH 8 +#define BBB_TXFIR_2__TXFIR_COEFF_H11__MASK 0xff000000U +#define BBB_TXFIR_2__TXFIR_COEFF_H11__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define BBB_TXFIR_2__TXFIR_COEFF_H11__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define BBB_TXFIR_2__TXFIR_COEFF_H11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define BBB_TXFIR_2__TXFIR_COEFF_H11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define BBB_TXFIR_2__TYPE u_int32_t +#define BBB_TXFIR_2__READ 0xffffffffU +#define BBB_TXFIR_2__WRITE 0xffffffffU + +#endif /* __BBB_TXFIR_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_txfir_2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TXFIR_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::heavy_clip_ctrl */ +#ifndef __HEAVY_CLIP_CTRL_MACRO__ +#define __HEAVY_CLIP_CTRL_MACRO__ + +/* macros for field cf_heavy_clip_enable */ +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__SHIFT 0 +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__WIDTH 9 +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__MASK 0x000001ffU +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field pre_emp_ht40_enable */ +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__SHIFT 9 +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__WIDTH 1 +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__MASK 0x00000200U +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field heavy_clip_factor_xr */ +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__SHIFT 10 +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__WIDTH 8 +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__MASK 0x0003fc00U +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fc00U) >> 10) +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0003fc00U) +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0003fc00U) +#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0003fc00U))) +#define HEAVY_CLIP_CTRL__TYPE u_int32_t +#define HEAVY_CLIP_CTRL__READ 0x0003ffffU +#define HEAVY_CLIP_CTRL__WRITE 0x0003ffffU + +#endif /* __HEAVY_CLIP_CTRL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_heavy_clip_ctrl */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_HEAVY_CLIP_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::heavy_clip_20 */ +#ifndef __HEAVY_CLIP_20_MACRO__ +#define __HEAVY_CLIP_20_MACRO__ + +/* macros for field heavy_clip_factor_0 */ +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__SHIFT 0 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__WIDTH 8 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__MASK 0x000000ffU +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field heavy_clip_factor_1 */ +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__SHIFT 8 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__WIDTH 8 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__MASK 0x0000ff00U +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field heavy_clip_factor_2 */ +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__SHIFT 16 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__WIDTH 8 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__MASK 0x00ff0000U +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field heavy_clip_factor_3 */ +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__SHIFT 24 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__WIDTH 8 +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__MASK 0xff000000U +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define HEAVY_CLIP_20__TYPE u_int32_t +#define HEAVY_CLIP_20__READ 0xffffffffU +#define HEAVY_CLIP_20__WRITE 0xffffffffU + +#endif /* __HEAVY_CLIP_20_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_heavy_clip_20 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_HEAVY_CLIP_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::heavy_clip_40 */ +#ifndef __HEAVY_CLIP_40_MACRO__ +#define __HEAVY_CLIP_40_MACRO__ + +/* macros for field heavy_clip_factor_4 */ +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__SHIFT 0 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__WIDTH 8 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__MASK 0x000000ffU +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field heavy_clip_factor_5 */ +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__SHIFT 8 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__WIDTH 8 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__MASK 0x0000ff00U +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field heavy_clip_factor_6 */ +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__SHIFT 16 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__WIDTH 8 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__MASK 0x00ff0000U +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field heavy_clip_factor_7 */ +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__SHIFT 24 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__WIDTH 8 +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__MASK 0xff000000U +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define HEAVY_CLIP_40__TYPE u_int32_t +#define HEAVY_CLIP_40__READ 0xffffffffU +#define HEAVY_CLIP_40__WRITE 0xffffffffU + +#endif /* __HEAVY_CLIP_40_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_heavy_clip_40 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_HEAVY_CLIP_40__NUM 1 + +/* macros for BlueprintGlobalNameSpace::illegal_tx_rate */ +#ifndef __ILLEGAL_TX_RATE_MACRO__ +#define __ILLEGAL_TX_RATE_MACRO__ + +/* macros for field illegal_tx_rate */ +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__SHIFT 0 +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__WIDTH 1 +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__MASK 0x00000001U +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define ILLEGAL_TX_RATE__TYPE u_int32_t +#define ILLEGAL_TX_RATE__READ 0x00000001U + +#endif /* __ILLEGAL_TX_RATE_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_illegal_tx_rate */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ILLEGAL_TX_RATE__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate1 */ +#ifndef __POWERTX_RATE1_MACRO__ +#define __POWERTX_RATE1_MACRO__ + +/* macros for field powertx_0 */ +#define POWERTX_RATE1__POWERTX_0__SHIFT 0 +#define POWERTX_RATE1__POWERTX_0__WIDTH 6 +#define POWERTX_RATE1__POWERTX_0__MASK 0x0000003fU +#define POWERTX_RATE1__POWERTX_0__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE1__POWERTX_0__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define POWERTX_RATE1__POWERTX_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE1__POWERTX_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_1 */ +#define POWERTX_RATE1__POWERTX_1__SHIFT 8 +#define POWERTX_RATE1__POWERTX_1__WIDTH 6 +#define POWERTX_RATE1__POWERTX_1__MASK 0x00003f00U +#define POWERTX_RATE1__POWERTX_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE1__POWERTX_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE1__POWERTX_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE1__POWERTX_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertx_2 */ +#define POWERTX_RATE1__POWERTX_2__SHIFT 16 +#define POWERTX_RATE1__POWERTX_2__WIDTH 6 +#define POWERTX_RATE1__POWERTX_2__MASK 0x003f0000U +#define POWERTX_RATE1__POWERTX_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE1__POWERTX_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE1__POWERTX_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE1__POWERTX_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertx_3 */ +#define POWERTX_RATE1__POWERTX_3__SHIFT 24 +#define POWERTX_RATE1__POWERTX_3__WIDTH 6 +#define POWERTX_RATE1__POWERTX_3__MASK 0x3f000000U +#define POWERTX_RATE1__POWERTX_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE1__POWERTX_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE1__POWERTX_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE1__POWERTX_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE1__TYPE u_int32_t +#define POWERTX_RATE1__READ 0x3f3f3f3fU +#define POWERTX_RATE1__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate2 */ +#ifndef __POWERTX_RATE2_MACRO__ +#define __POWERTX_RATE2_MACRO__ + +/* macros for field powertx_4 */ +#define POWERTX_RATE2__POWERTX_4__SHIFT 0 +#define POWERTX_RATE2__POWERTX_4__WIDTH 6 +#define POWERTX_RATE2__POWERTX_4__MASK 0x0000003fU +#define POWERTX_RATE2__POWERTX_4__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE2__POWERTX_4__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define POWERTX_RATE2__POWERTX_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE2__POWERTX_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_5 */ +#define POWERTX_RATE2__POWERTX_5__SHIFT 8 +#define POWERTX_RATE2__POWERTX_5__WIDTH 6 +#define POWERTX_RATE2__POWERTX_5__MASK 0x00003f00U +#define POWERTX_RATE2__POWERTX_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE2__POWERTX_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE2__POWERTX_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE2__POWERTX_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertx_6 */ +#define POWERTX_RATE2__POWERTX_6__SHIFT 16 +#define POWERTX_RATE2__POWERTX_6__WIDTH 6 +#define POWERTX_RATE2__POWERTX_6__MASK 0x003f0000U +#define POWERTX_RATE2__POWERTX_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE2__POWERTX_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE2__POWERTX_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE2__POWERTX_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertx_7 */ +#define POWERTX_RATE2__POWERTX_7__SHIFT 24 +#define POWERTX_RATE2__POWERTX_7__WIDTH 6 +#define POWERTX_RATE2__POWERTX_7__MASK 0x3f000000U +#define POWERTX_RATE2__POWERTX_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE2__POWERTX_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE2__POWERTX_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE2__POWERTX_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE2__TYPE u_int32_t +#define POWERTX_RATE2__READ 0x3f3f3f3fU +#define POWERTX_RATE2__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate3 */ +#ifndef __POWERTX_RATE3_MACRO__ +#define __POWERTX_RATE3_MACRO__ + +/* macros for field powertx_1l */ +#define POWERTX_RATE3__POWERTX_1L__SHIFT 0 +#define POWERTX_RATE3__POWERTX_1L__WIDTH 6 +#define POWERTX_RATE3__POWERTX_1L__MASK 0x0000003fU +#define POWERTX_RATE3__POWERTX_1L__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE3__POWERTX_1L__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define POWERTX_RATE3__POWERTX_1L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE3__POWERTX_1L__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_2l */ +#define POWERTX_RATE3__POWERTX_2L__SHIFT 16 +#define POWERTX_RATE3__POWERTX_2L__WIDTH 6 +#define POWERTX_RATE3__POWERTX_2L__MASK 0x003f0000U +#define POWERTX_RATE3__POWERTX_2L__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE3__POWERTX_2L__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE3__POWERTX_2L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE3__POWERTX_2L__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertx_2s */ +#define POWERTX_RATE3__POWERTX_2S__SHIFT 24 +#define POWERTX_RATE3__POWERTX_2S__WIDTH 6 +#define POWERTX_RATE3__POWERTX_2S__MASK 0x3f000000U +#define POWERTX_RATE3__POWERTX_2S__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE3__POWERTX_2S__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE3__POWERTX_2S__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE3__POWERTX_2S__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE3__TYPE u_int32_t +#define POWERTX_RATE3__READ 0x3f3f003fU +#define POWERTX_RATE3__WRITE 0x3f3f003fU + +#endif /* __POWERTX_RATE3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate3 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate4 */ +#ifndef __POWERTX_RATE4_MACRO__ +#define __POWERTX_RATE4_MACRO__ + +/* macros for field powertx_55l */ +#define POWERTX_RATE4__POWERTX_55L__SHIFT 0 +#define POWERTX_RATE4__POWERTX_55L__WIDTH 6 +#define POWERTX_RATE4__POWERTX_55L__MASK 0x0000003fU +#define POWERTX_RATE4__POWERTX_55L__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE4__POWERTX_55L__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define POWERTX_RATE4__POWERTX_55L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE4__POWERTX_55L__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_55s */ +#define POWERTX_RATE4__POWERTX_55S__SHIFT 8 +#define POWERTX_RATE4__POWERTX_55S__WIDTH 6 +#define POWERTX_RATE4__POWERTX_55S__MASK 0x00003f00U +#define POWERTX_RATE4__POWERTX_55S__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE4__POWERTX_55S__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE4__POWERTX_55S__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE4__POWERTX_55S__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertx_11l */ +#define POWERTX_RATE4__POWERTX_11L__SHIFT 16 +#define POWERTX_RATE4__POWERTX_11L__WIDTH 6 +#define POWERTX_RATE4__POWERTX_11L__MASK 0x003f0000U +#define POWERTX_RATE4__POWERTX_11L__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE4__POWERTX_11L__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE4__POWERTX_11L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE4__POWERTX_11L__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertx_11s */ +#define POWERTX_RATE4__POWERTX_11S__SHIFT 24 +#define POWERTX_RATE4__POWERTX_11S__WIDTH 6 +#define POWERTX_RATE4__POWERTX_11S__MASK 0x3f000000U +#define POWERTX_RATE4__POWERTX_11S__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE4__POWERTX_11S__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE4__POWERTX_11S__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE4__POWERTX_11S__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE4__TYPE u_int32_t +#define POWERTX_RATE4__READ 0x3f3f3f3fU +#define POWERTX_RATE4__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE4_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate4 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate5 */ +#ifndef __POWERTX_RATE5_MACRO__ +#define __POWERTX_RATE5_MACRO__ + +/* macros for field powertxht20_0 */ +#define POWERTX_RATE5__POWERTXHT20_0__SHIFT 0 +#define POWERTX_RATE5__POWERTXHT20_0__WIDTH 6 +#define POWERTX_RATE5__POWERTXHT20_0__MASK 0x0000003fU +#define POWERTX_RATE5__POWERTXHT20_0__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE5__POWERTXHT20_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE5__POWERTXHT20_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE5__POWERTXHT20_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht20_1 */ +#define POWERTX_RATE5__POWERTXHT20_1__SHIFT 8 +#define POWERTX_RATE5__POWERTXHT20_1__WIDTH 6 +#define POWERTX_RATE5__POWERTXHT20_1__MASK 0x00003f00U +#define POWERTX_RATE5__POWERTXHT20_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE5__POWERTXHT20_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE5__POWERTXHT20_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE5__POWERTXHT20_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht20_2 */ +#define POWERTX_RATE5__POWERTXHT20_2__SHIFT 16 +#define POWERTX_RATE5__POWERTXHT20_2__WIDTH 6 +#define POWERTX_RATE5__POWERTXHT20_2__MASK 0x003f0000U +#define POWERTX_RATE5__POWERTXHT20_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE5__POWERTXHT20_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE5__POWERTXHT20_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE5__POWERTXHT20_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht20_3 */ +#define POWERTX_RATE5__POWERTXHT20_3__SHIFT 24 +#define POWERTX_RATE5__POWERTXHT20_3__WIDTH 6 +#define POWERTX_RATE5__POWERTXHT20_3__MASK 0x3f000000U +#define POWERTX_RATE5__POWERTXHT20_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE5__POWERTXHT20_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE5__POWERTXHT20_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE5__POWERTXHT20_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE5__TYPE u_int32_t +#define POWERTX_RATE5__READ 0x3f3f3f3fU +#define POWERTX_RATE5__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE5_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate5 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate6 */ +#ifndef __POWERTX_RATE6_MACRO__ +#define __POWERTX_RATE6_MACRO__ + +/* macros for field powertxht20_4 */ +#define POWERTX_RATE6__POWERTXHT20_4__SHIFT 0 +#define POWERTX_RATE6__POWERTXHT20_4__WIDTH 6 +#define POWERTX_RATE6__POWERTXHT20_4__MASK 0x0000003fU +#define POWERTX_RATE6__POWERTXHT20_4__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE6__POWERTXHT20_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE6__POWERTXHT20_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE6__POWERTXHT20_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht20_5 */ +#define POWERTX_RATE6__POWERTXHT20_5__SHIFT 8 +#define POWERTX_RATE6__POWERTXHT20_5__WIDTH 6 +#define POWERTX_RATE6__POWERTXHT20_5__MASK 0x00003f00U +#define POWERTX_RATE6__POWERTXHT20_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE6__POWERTXHT20_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE6__POWERTXHT20_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE6__POWERTXHT20_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht20_6 */ +#define POWERTX_RATE6__POWERTXHT20_6__SHIFT 16 +#define POWERTX_RATE6__POWERTXHT20_6__WIDTH 6 +#define POWERTX_RATE6__POWERTXHT20_6__MASK 0x003f0000U +#define POWERTX_RATE6__POWERTXHT20_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE6__POWERTXHT20_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE6__POWERTXHT20_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE6__POWERTXHT20_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht20_7 */ +#define POWERTX_RATE6__POWERTXHT20_7__SHIFT 24 +#define POWERTX_RATE6__POWERTXHT20_7__WIDTH 6 +#define POWERTX_RATE6__POWERTXHT20_7__MASK 0x3f000000U +#define POWERTX_RATE6__POWERTXHT20_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE6__POWERTXHT20_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE6__POWERTXHT20_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE6__POWERTXHT20_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE6__TYPE u_int32_t +#define POWERTX_RATE6__READ 0x3f3f3f3fU +#define POWERTX_RATE6__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE6_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate6 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate7 */ +#ifndef __POWERTX_RATE7_MACRO__ +#define __POWERTX_RATE7_MACRO__ + +/* macros for field powertxht40_0 */ +#define POWERTX_RATE7__POWERTXHT40_0__SHIFT 0 +#define POWERTX_RATE7__POWERTXHT40_0__WIDTH 6 +#define POWERTX_RATE7__POWERTXHT40_0__MASK 0x0000003fU +#define POWERTX_RATE7__POWERTXHT40_0__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE7__POWERTXHT40_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE7__POWERTXHT40_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE7__POWERTXHT40_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht40_1 */ +#define POWERTX_RATE7__POWERTXHT40_1__SHIFT 8 +#define POWERTX_RATE7__POWERTXHT40_1__WIDTH 6 +#define POWERTX_RATE7__POWERTXHT40_1__MASK 0x00003f00U +#define POWERTX_RATE7__POWERTXHT40_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE7__POWERTXHT40_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE7__POWERTXHT40_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE7__POWERTXHT40_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht40_2 */ +#define POWERTX_RATE7__POWERTXHT40_2__SHIFT 16 +#define POWERTX_RATE7__POWERTXHT40_2__WIDTH 6 +#define POWERTX_RATE7__POWERTXHT40_2__MASK 0x003f0000U +#define POWERTX_RATE7__POWERTXHT40_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE7__POWERTXHT40_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE7__POWERTXHT40_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE7__POWERTXHT40_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht40_3 */ +#define POWERTX_RATE7__POWERTXHT40_3__SHIFT 24 +#define POWERTX_RATE7__POWERTXHT40_3__WIDTH 6 +#define POWERTX_RATE7__POWERTXHT40_3__MASK 0x3f000000U +#define POWERTX_RATE7__POWERTXHT40_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE7__POWERTXHT40_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE7__POWERTXHT40_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE7__POWERTXHT40_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE7__TYPE u_int32_t +#define POWERTX_RATE7__READ 0x3f3f3f3fU +#define POWERTX_RATE7__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE7_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate7 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate8 */ +#ifndef __POWERTX_RATE8_MACRO__ +#define __POWERTX_RATE8_MACRO__ + +/* macros for field powertxht40_4 */ +#define POWERTX_RATE8__POWERTXHT40_4__SHIFT 0 +#define POWERTX_RATE8__POWERTXHT40_4__WIDTH 6 +#define POWERTX_RATE8__POWERTXHT40_4__MASK 0x0000003fU +#define POWERTX_RATE8__POWERTXHT40_4__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE8__POWERTXHT40_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE8__POWERTXHT40_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE8__POWERTXHT40_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht40_5 */ +#define POWERTX_RATE8__POWERTXHT40_5__SHIFT 8 +#define POWERTX_RATE8__POWERTXHT40_5__WIDTH 6 +#define POWERTX_RATE8__POWERTXHT40_5__MASK 0x00003f00U +#define POWERTX_RATE8__POWERTXHT40_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE8__POWERTXHT40_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE8__POWERTXHT40_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE8__POWERTXHT40_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht40_6 */ +#define POWERTX_RATE8__POWERTXHT40_6__SHIFT 16 +#define POWERTX_RATE8__POWERTXHT40_6__WIDTH 6 +#define POWERTX_RATE8__POWERTXHT40_6__MASK 0x003f0000U +#define POWERTX_RATE8__POWERTXHT40_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE8__POWERTXHT40_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE8__POWERTXHT40_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE8__POWERTXHT40_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht40_7 */ +#define POWERTX_RATE8__POWERTXHT40_7__SHIFT 24 +#define POWERTX_RATE8__POWERTXHT40_7__WIDTH 6 +#define POWERTX_RATE8__POWERTXHT40_7__MASK 0x3f000000U +#define POWERTX_RATE8__POWERTXHT40_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE8__POWERTXHT40_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE8__POWERTXHT40_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE8__POWERTXHT40_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE8__TYPE u_int32_t +#define POWERTX_RATE8__READ 0x3f3f3f3fU +#define POWERTX_RATE8__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE8_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate8 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate9 */ +#ifndef __POWERTX_RATE9_MACRO__ +#define __POWERTX_RATE9_MACRO__ + +/* macros for field powertx_dup40_cck */ +#define POWERTX_RATE9__POWERTX_DUP40_CCK__SHIFT 0 +#define POWERTX_RATE9__POWERTX_DUP40_CCK__WIDTH 6 +#define POWERTX_RATE9__POWERTX_DUP40_CCK__MASK 0x0000003fU +#define POWERTX_RATE9__POWERTX_DUP40_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define POWERTX_RATE9__POWERTX_DUP40_CCK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE9__POWERTX_DUP40_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE9__POWERTX_DUP40_CCK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_dup40_ofdm */ +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__SHIFT 8 +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__WIDTH 6 +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__MASK 0x00003f00U +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE9__POWERTX_DUP40_OFDM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertx_ext20_cck */ +#define POWERTX_RATE9__POWERTX_EXT20_CCK__SHIFT 16 +#define POWERTX_RATE9__POWERTX_EXT20_CCK__WIDTH 6 +#define POWERTX_RATE9__POWERTX_EXT20_CCK__MASK 0x003f0000U +#define POWERTX_RATE9__POWERTX_EXT20_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE9__POWERTX_EXT20_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE9__POWERTX_EXT20_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE9__POWERTX_EXT20_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertx_ext20_ofdm */ +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__SHIFT 24 +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__WIDTH 6 +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__MASK 0x3f000000U +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE9__POWERTX_EXT20_OFDM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE9__TYPE u_int32_t +#define POWERTX_RATE9__READ 0x3f3f3f3fU +#define POWERTX_RATE9__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE9_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate9 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate10 */ +#ifndef __POWERTX_RATE10_MACRO__ +#define __POWERTX_RATE10_MACRO__ + +/* macros for field powertxht20_8 */ +#define POWERTX_RATE10__POWERTXHT20_8__SHIFT 0 +#define POWERTX_RATE10__POWERTXHT20_8__WIDTH 6 +#define POWERTX_RATE10__POWERTXHT20_8__MASK 0x0000003fU +#define POWERTX_RATE10__POWERTXHT20_8__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE10__POWERTXHT20_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE10__POWERTXHT20_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE10__POWERTXHT20_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht20_9 */ +#define POWERTX_RATE10__POWERTXHT20_9__SHIFT 8 +#define POWERTX_RATE10__POWERTXHT20_9__WIDTH 6 +#define POWERTX_RATE10__POWERTXHT20_9__MASK 0x00003f00U +#define POWERTX_RATE10__POWERTXHT20_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE10__POWERTXHT20_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE10__POWERTXHT20_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE10__POWERTXHT20_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht20_10 */ +#define POWERTX_RATE10__POWERTXHT20_10__SHIFT 16 +#define POWERTX_RATE10__POWERTXHT20_10__WIDTH 6 +#define POWERTX_RATE10__POWERTXHT20_10__MASK 0x003f0000U +#define POWERTX_RATE10__POWERTXHT20_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE10__POWERTXHT20_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE10__POWERTXHT20_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE10__POWERTXHT20_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht20_11 */ +#define POWERTX_RATE10__POWERTXHT20_11__SHIFT 24 +#define POWERTX_RATE10__POWERTXHT20_11__WIDTH 6 +#define POWERTX_RATE10__POWERTXHT20_11__MASK 0x3f000000U +#define POWERTX_RATE10__POWERTXHT20_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE10__POWERTXHT20_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE10__POWERTXHT20_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE10__POWERTXHT20_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE10__TYPE u_int32_t +#define POWERTX_RATE10__READ 0x3f3f3f3fU +#define POWERTX_RATE10__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE10_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate10 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate11 */ +#ifndef __POWERTX_RATE11_MACRO__ +#define __POWERTX_RATE11_MACRO__ + +/* macros for field powertxht20_12 */ +#define POWERTX_RATE11__POWERTXHT20_12__SHIFT 0 +#define POWERTX_RATE11__POWERTXHT20_12__WIDTH 6 +#define POWERTX_RATE11__POWERTXHT20_12__MASK 0x0000003fU +#define POWERTX_RATE11__POWERTXHT20_12__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define POWERTX_RATE11__POWERTXHT20_12__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE11__POWERTXHT20_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE11__POWERTXHT20_12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht20_13 */ +#define POWERTX_RATE11__POWERTXHT20_13__SHIFT 8 +#define POWERTX_RATE11__POWERTXHT20_13__WIDTH 6 +#define POWERTX_RATE11__POWERTXHT20_13__MASK 0x00003f00U +#define POWERTX_RATE11__POWERTXHT20_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE11__POWERTXHT20_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE11__POWERTXHT20_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE11__POWERTXHT20_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht40_12 */ +#define POWERTX_RATE11__POWERTXHT40_12__SHIFT 16 +#define POWERTX_RATE11__POWERTXHT40_12__WIDTH 6 +#define POWERTX_RATE11__POWERTXHT40_12__MASK 0x003f0000U +#define POWERTX_RATE11__POWERTXHT40_12__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE11__POWERTXHT40_12__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE11__POWERTXHT40_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE11__POWERTXHT40_12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht40_13 */ +#define POWERTX_RATE11__POWERTXHT40_13__SHIFT 24 +#define POWERTX_RATE11__POWERTXHT40_13__WIDTH 6 +#define POWERTX_RATE11__POWERTXHT40_13__MASK 0x3f000000U +#define POWERTX_RATE11__POWERTXHT40_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE11__POWERTXHT40_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE11__POWERTXHT40_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE11__POWERTXHT40_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE11__TYPE u_int32_t +#define POWERTX_RATE11__READ 0x3f3f3f3fU +#define POWERTX_RATE11__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE11_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate11 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_rate12 */ +#ifndef __POWERTX_RATE12_MACRO__ +#define __POWERTX_RATE12_MACRO__ + +/* macros for field powertxht40_8 */ +#define POWERTX_RATE12__POWERTXHT40_8__SHIFT 0 +#define POWERTX_RATE12__POWERTXHT40_8__WIDTH 6 +#define POWERTX_RATE12__POWERTXHT40_8__MASK 0x0000003fU +#define POWERTX_RATE12__POWERTXHT40_8__READ(src) (u_int32_t)(src) & 0x0000003fU +#define POWERTX_RATE12__POWERTXHT40_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_RATE12__POWERTXHT40_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_RATE12__POWERTXHT40_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertxht40_9 */ +#define POWERTX_RATE12__POWERTXHT40_9__SHIFT 8 +#define POWERTX_RATE12__POWERTXHT40_9__WIDTH 6 +#define POWERTX_RATE12__POWERTXHT40_9__MASK 0x00003f00U +#define POWERTX_RATE12__POWERTXHT40_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define POWERTX_RATE12__POWERTXHT40_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define POWERTX_RATE12__POWERTXHT40_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define POWERTX_RATE12__POWERTXHT40_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field powertxht40_10 */ +#define POWERTX_RATE12__POWERTXHT40_10__SHIFT 16 +#define POWERTX_RATE12__POWERTXHT40_10__WIDTH 6 +#define POWERTX_RATE12__POWERTXHT40_10__MASK 0x003f0000U +#define POWERTX_RATE12__POWERTXHT40_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define POWERTX_RATE12__POWERTXHT40_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define POWERTX_RATE12__POWERTXHT40_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define POWERTX_RATE12__POWERTXHT40_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field powertxht40_11 */ +#define POWERTX_RATE12__POWERTXHT40_11__SHIFT 24 +#define POWERTX_RATE12__POWERTXHT40_11__WIDTH 6 +#define POWERTX_RATE12__POWERTXHT40_11__MASK 0x3f000000U +#define POWERTX_RATE12__POWERTXHT40_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define POWERTX_RATE12__POWERTXHT40_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define POWERTX_RATE12__POWERTXHT40_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define POWERTX_RATE12__POWERTXHT40_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define POWERTX_RATE12__TYPE u_int32_t +#define POWERTX_RATE12__READ 0x3f3f3f3fU +#define POWERTX_RATE12__WRITE 0x3f3f3f3fU + +#endif /* __POWERTX_RATE12_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate12 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_max */ +#ifndef __POWERTX_MAX_MACRO__ +#define __POWERTX_MAX_MACRO__ + +/* macros for field use_per_packet_powertx_max */ +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__SHIFT 6 +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__WIDTH 1 +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__MASK 0x00000040U +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field use_per_packet_olpc_gain_delta_adj */ +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__SHIFT 7 +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__WIDTH 1 +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MASK 0x00000080U +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) +#define POWERTX_MAX__TYPE u_int32_t +#define POWERTX_MAX__READ 0x000000c0U +#define POWERTX_MAX__WRITE 0x000000c0U + +#endif /* __POWERTX_MAX_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_max */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_MAX__NUM 1 + +/* macros for BlueprintGlobalNameSpace::powertx_sub */ +#ifndef __POWERTX_SUB_MACRO__ +#define __POWERTX_SUB_MACRO__ + +/* macros for field powertx_sub_for_2chain */ +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__SHIFT 0 +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__WIDTH 6 +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__MASK 0x0000003fU +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field powertx_sub_for_3chain */ +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__SHIFT 6 +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__WIDTH 6 +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__MASK 0x00000fc0U +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) +#define POWERTX_SUB__TYPE u_int32_t +#define POWERTX_SUB__READ 0x00000fffU +#define POWERTX_SUB__WRITE 0x00000fffU + +#endif /* __POWERTX_SUB_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_sub */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_SUB__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_1 */ +#ifndef __TPC_1_MACRO__ +#define __TPC_1_MACRO__ + +/* macros for field force_dac_gain */ +#define TPC_1__FORCE_DAC_GAIN__SHIFT 0 +#define TPC_1__FORCE_DAC_GAIN__WIDTH 1 +#define TPC_1__FORCE_DAC_GAIN__MASK 0x00000001U +#define TPC_1__FORCE_DAC_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_1__FORCE_DAC_GAIN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TPC_1__FORCE_DAC_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TPC_1__FORCE_DAC_GAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TPC_1__FORCE_DAC_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_1__FORCE_DAC_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field forced_dac_gain */ +#define TPC_1__FORCED_DAC_GAIN__SHIFT 1 +#define TPC_1__FORCED_DAC_GAIN__WIDTH 5 +#define TPC_1__FORCED_DAC_GAIN__MASK 0x0000003eU +#define TPC_1__FORCED_DAC_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) +#define TPC_1__FORCED_DAC_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000003eU) +#define TPC_1__FORCED_DAC_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000003eU) +#define TPC_1__FORCED_DAC_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000003eU))) + +/* macros for field pd_dc_offset_target */ +#define TPC_1__PD_DC_OFFSET_TARGET__SHIFT 6 +#define TPC_1__PD_DC_OFFSET_TARGET__WIDTH 8 +#define TPC_1__PD_DC_OFFSET_TARGET__MASK 0x00003fc0U +#define TPC_1__PD_DC_OFFSET_TARGET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003fc0U) >> 6) +#define TPC_1__PD_DC_OFFSET_TARGET__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00003fc0U) +#define TPC_1__PD_DC_OFFSET_TARGET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00003fc0U) +#define TPC_1__PD_DC_OFFSET_TARGET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00003fc0U))) + +/* macros for field num_pd_gain */ +#define TPC_1__NUM_PD_GAIN__SHIFT 14 +#define TPC_1__NUM_PD_GAIN__WIDTH 2 +#define TPC_1__NUM_PD_GAIN__MASK 0x0000c000U +#define TPC_1__NUM_PD_GAIN__READ(src) (((u_int32_t)(src) & 0x0000c000U) >> 14) +#define TPC_1__NUM_PD_GAIN__WRITE(src) (((u_int32_t)(src) << 14) & 0x0000c000U) +#define TPC_1__NUM_PD_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0000c000U) +#define TPC_1__NUM_PD_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0000c000U))) + +/* macros for field pd_gain_setting1 */ +#define TPC_1__PD_GAIN_SETTING1__SHIFT 16 +#define TPC_1__PD_GAIN_SETTING1__WIDTH 2 +#define TPC_1__PD_GAIN_SETTING1__MASK 0x00030000U +#define TPC_1__PD_GAIN_SETTING1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00030000U) >> 16) +#define TPC_1__PD_GAIN_SETTING1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00030000U) +#define TPC_1__PD_GAIN_SETTING1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((u_int32_t)(src) <<\ + 16) & 0x00030000U) +#define TPC_1__PD_GAIN_SETTING1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00030000U))) + +/* macros for field pd_gain_setting2 */ +#define TPC_1__PD_GAIN_SETTING2__SHIFT 18 +#define TPC_1__PD_GAIN_SETTING2__WIDTH 2 +#define TPC_1__PD_GAIN_SETTING2__MASK 0x000c0000U +#define TPC_1__PD_GAIN_SETTING2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000c0000U) >> 18) +#define TPC_1__PD_GAIN_SETTING2__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define TPC_1__PD_GAIN_SETTING2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define TPC_1__PD_GAIN_SETTING2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field pd_gain_setting3 */ +#define TPC_1__PD_GAIN_SETTING3__SHIFT 20 +#define TPC_1__PD_GAIN_SETTING3__WIDTH 2 +#define TPC_1__PD_GAIN_SETTING3__MASK 0x00300000U +#define TPC_1__PD_GAIN_SETTING3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00300000U) >> 20) +#define TPC_1__PD_GAIN_SETTING3__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00300000U) +#define TPC_1__PD_GAIN_SETTING3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((u_int32_t)(src) <<\ + 20) & 0x00300000U) +#define TPC_1__PD_GAIN_SETTING3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00300000U))) + +/* macros for field enable_pd_calibrate */ +#define TPC_1__ENABLE_PD_CALIBRATE__SHIFT 22 +#define TPC_1__ENABLE_PD_CALIBRATE__WIDTH 1 +#define TPC_1__ENABLE_PD_CALIBRATE__MASK 0x00400000U +#define TPC_1__ENABLE_PD_CALIBRATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define TPC_1__ENABLE_PD_CALIBRATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define TPC_1__ENABLE_PD_CALIBRATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TPC_1__ENABLE_PD_CALIBRATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TPC_1__ENABLE_PD_CALIBRATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TPC_1__ENABLE_PD_CALIBRATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field pd_calibrate_wait */ +#define TPC_1__PD_CALIBRATE_WAIT__SHIFT 23 +#define TPC_1__PD_CALIBRATE_WAIT__WIDTH 6 +#define TPC_1__PD_CALIBRATE_WAIT__MASK 0x1f800000U +#define TPC_1__PD_CALIBRATE_WAIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f800000U) >> 23) +#define TPC_1__PD_CALIBRATE_WAIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x1f800000U) +#define TPC_1__PD_CALIBRATE_WAIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x1f800000U) +#define TPC_1__PD_CALIBRATE_WAIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x1f800000U))) + +/* macros for field force_pdadc_gain */ +#define TPC_1__FORCE_PDADC_GAIN__SHIFT 29 +#define TPC_1__FORCE_PDADC_GAIN__WIDTH 1 +#define TPC_1__FORCE_PDADC_GAIN__MASK 0x20000000U +#define TPC_1__FORCE_PDADC_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define TPC_1__FORCE_PDADC_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define TPC_1__FORCE_PDADC_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define TPC_1__FORCE_PDADC_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define TPC_1__FORCE_PDADC_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define TPC_1__FORCE_PDADC_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field forced_pdadc_gain */ +#define TPC_1__FORCED_PDADC_GAIN__SHIFT 30 +#define TPC_1__FORCED_PDADC_GAIN__WIDTH 2 +#define TPC_1__FORCED_PDADC_GAIN__MASK 0xc0000000U +#define TPC_1__FORCED_PDADC_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define TPC_1__FORCED_PDADC_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define TPC_1__FORCED_PDADC_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define TPC_1__FORCED_PDADC_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define TPC_1__TYPE u_int32_t +#define TPC_1__READ 0xffffffffU +#define TPC_1__WRITE 0xffffffffU + +#endif /* __TPC_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_2 */ +#ifndef __TPC_2_MACRO__ +#define __TPC_2_MACRO__ + +/* macros for field tx_frame_to_pdadc_on */ +#define TPC_2__TX_FRAME_TO_PDADC_ON__SHIFT 0 +#define TPC_2__TX_FRAME_TO_PDADC_ON__WIDTH 8 +#define TPC_2__TX_FRAME_TO_PDADC_ON__MASK 0x000000ffU +#define TPC_2__TX_FRAME_TO_PDADC_ON__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TPC_2__TX_FRAME_TO_PDADC_ON__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define TPC_2__TX_FRAME_TO_PDADC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TPC_2__TX_FRAME_TO_PDADC_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_frame_to_pd_acc_ofdm */ +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__SHIFT 8 +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__WIDTH 8 +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__MASK 0x0000ff00U +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field tx_frame_to_pd_acc_cck */ +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__SHIFT 16 +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__WIDTH 8 +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__MASK 0x00ff0000U +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) +#define TPC_2__TYPE u_int32_t +#define TPC_2__READ 0x00ffffffU +#define TPC_2__WRITE 0x00ffffffU + +#endif /* __TPC_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_3 */ +#ifndef __TPC_3_MACRO__ +#define __TPC_3_MACRO__ + +/* macros for field tx_end_to_pdadc_on */ +#define TPC_3__TX_END_TO_PDADC_ON__SHIFT 0 +#define TPC_3__TX_END_TO_PDADC_ON__WIDTH 8 +#define TPC_3__TX_END_TO_PDADC_ON__MASK 0x000000ffU +#define TPC_3__TX_END_TO_PDADC_ON__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TPC_3__TX_END_TO_PDADC_ON__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define TPC_3__TX_END_TO_PDADC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TPC_3__TX_END_TO_PDADC_ON__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field tx_end_to_pd_acc_on */ +#define TPC_3__TX_END_TO_PD_ACC_ON__SHIFT 8 +#define TPC_3__TX_END_TO_PD_ACC_ON__WIDTH 8 +#define TPC_3__TX_END_TO_PD_ACC_ON__MASK 0x0000ff00U +#define TPC_3__TX_END_TO_PD_ACC_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TPC_3__TX_END_TO_PD_ACC_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TPC_3__TX_END_TO_PD_ACC_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TPC_3__TX_END_TO_PD_ACC_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field pd_acc_window_dc_off */ +#define TPC_3__PD_ACC_WINDOW_DC_OFF__SHIFT 16 +#define TPC_3__PD_ACC_WINDOW_DC_OFF__WIDTH 3 +#define TPC_3__PD_ACC_WINDOW_DC_OFF__MASK 0x00070000U +#define TPC_3__PD_ACC_WINDOW_DC_OFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define TPC_3__PD_ACC_WINDOW_DC_OFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define TPC_3__PD_ACC_WINDOW_DC_OFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define TPC_3__PD_ACC_WINDOW_DC_OFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field pd_acc_window_cal */ +#define TPC_3__PD_ACC_WINDOW_CAL__SHIFT 19 +#define TPC_3__PD_ACC_WINDOW_CAL__WIDTH 3 +#define TPC_3__PD_ACC_WINDOW_CAL__MASK 0x00380000U +#define TPC_3__PD_ACC_WINDOW_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00380000U) >> 19) +#define TPC_3__PD_ACC_WINDOW_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define TPC_3__PD_ACC_WINDOW_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define TPC_3__PD_ACC_WINDOW_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field pd_acc_window_ofdm */ +#define TPC_3__PD_ACC_WINDOW_OFDM__SHIFT 22 +#define TPC_3__PD_ACC_WINDOW_OFDM__WIDTH 3 +#define TPC_3__PD_ACC_WINDOW_OFDM__MASK 0x01c00000U +#define TPC_3__PD_ACC_WINDOW_OFDM__READ(src) \ + (((u_int32_t)(src)\ + & 0x01c00000U) >> 22) +#define TPC_3__PD_ACC_WINDOW_OFDM__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x01c00000U) +#define TPC_3__PD_ACC_WINDOW_OFDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x01c00000U) +#define TPC_3__PD_ACC_WINDOW_OFDM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x01c00000U))) + +/* macros for field pd_acc_window_cck */ +#define TPC_3__PD_ACC_WINDOW_CCK__SHIFT 25 +#define TPC_3__PD_ACC_WINDOW_CCK__WIDTH 3 +#define TPC_3__PD_ACC_WINDOW_CCK__MASK 0x0e000000U +#define TPC_3__PD_ACC_WINDOW_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0e000000U) >> 25) +#define TPC_3__PD_ACC_WINDOW_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x0e000000U) +#define TPC_3__PD_ACC_WINDOW_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x0e000000U) +#define TPC_3__PD_ACC_WINDOW_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x0e000000U))) + +/* macros for field tpc_clk_gate_enable */ +#define TPC_3__TPC_CLK_GATE_ENABLE__SHIFT 31 +#define TPC_3__TPC_CLK_GATE_ENABLE__WIDTH 1 +#define TPC_3__TPC_CLK_GATE_ENABLE__MASK 0x80000000U +#define TPC_3__TPC_CLK_GATE_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TPC_3__TPC_CLK_GATE_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TPC_3__TPC_CLK_GATE_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TPC_3__TPC_CLK_GATE_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TPC_3__TPC_CLK_GATE_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TPC_3__TPC_CLK_GATE_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TPC_3__TYPE u_int32_t +#define TPC_3__READ 0x8fffffffU +#define TPC_3__WRITE 0x8fffffffU + +#endif /* __TPC_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_3 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_4_b0 */ +#ifndef __TPC_4_B0_MACRO__ +#define __TPC_4_B0_MACRO__ + +/* macros for field pd_avg_valid_0 */ +#define TPC_4_B0__PD_AVG_VALID_0__SHIFT 0 +#define TPC_4_B0__PD_AVG_VALID_0__WIDTH 1 +#define TPC_4_B0__PD_AVG_VALID_0__MASK 0x00000001U +#define TPC_4_B0__PD_AVG_VALID_0__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_4_B0__PD_AVG_VALID_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_4_B0__PD_AVG_VALID_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field pd_avg_out_0 */ +#define TPC_4_B0__PD_AVG_OUT_0__SHIFT 1 +#define TPC_4_B0__PD_AVG_OUT_0__WIDTH 8 +#define TPC_4_B0__PD_AVG_OUT_0__MASK 0x000001feU +#define TPC_4_B0__PD_AVG_OUT_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) + +/* macros for field dac_gain_0 */ +#define TPC_4_B0__DAC_GAIN_0__SHIFT 9 +#define TPC_4_B0__DAC_GAIN_0__WIDTH 5 +#define TPC_4_B0__DAC_GAIN_0__MASK 0x00003e00U +#define TPC_4_B0__DAC_GAIN_0__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9) + +/* macros for field tx_gain_setting_0 */ +#define TPC_4_B0__TX_GAIN_SETTING_0__SHIFT 14 +#define TPC_4_B0__TX_GAIN_SETTING_0__WIDTH 6 +#define TPC_4_B0__TX_GAIN_SETTING_0__MASK 0x000fc000U +#define TPC_4_B0__TX_GAIN_SETTING_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) + +/* macros for field rate_sent_0 */ +#define TPC_4_B0__RATE_SENT_0__SHIFT 20 +#define TPC_4_B0__RATE_SENT_0__WIDTH 5 +#define TPC_4_B0__RATE_SENT_0__MASK 0x01f00000U +#define TPC_4_B0__RATE_SENT_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) + +/* macros for field error_est_update_power_thresh */ +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__SHIFT 25 +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__WIDTH 6 +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__MASK 0x7e000000U +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__READ(src) \ + (((u_int32_t)(src)\ + & 0x7e000000U) >> 25) +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x7e000000U) +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x7e000000U) +#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x7e000000U))) +#define TPC_4_B0__TYPE u_int32_t +#define TPC_4_B0__READ 0x7fffffffU +#define TPC_4_B0__WRITE 0x7fffffffU + +#endif /* __TPC_4_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_4_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_4_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_5_b0 */ +#ifndef __TPC_5_B0_MACRO__ +#define __TPC_5_B0_MACRO__ + +/* macros for field pd_gain_overlap */ +#define TPC_5_B0__PD_GAIN_OVERLAP__SHIFT 0 +#define TPC_5_B0__PD_GAIN_OVERLAP__WIDTH 4 +#define TPC_5_B0__PD_GAIN_OVERLAP__MASK 0x0000000fU +#define TPC_5_B0__PD_GAIN_OVERLAP__READ(src) (u_int32_t)(src) & 0x0000000fU +#define TPC_5_B0__PD_GAIN_OVERLAP__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define TPC_5_B0__PD_GAIN_OVERLAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define TPC_5_B0__PD_GAIN_OVERLAP__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field pd_gain_boundary_1_0 */ +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__SHIFT 4 +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__WIDTH 6 +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__MASK 0x000003f0U +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field pd_gain_boundary_2_0 */ +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__SHIFT 10 +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__WIDTH 6 +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__MASK 0x0000fc00U +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fc00U) >> 10) +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0000fc00U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0000fc00U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0000fc00U))) + +/* macros for field pd_gain_boundary_3_0 */ +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__SHIFT 16 +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__WIDTH 6 +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__MASK 0x003f0000U +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field pd_gain_boundary_4_0 */ +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__SHIFT 22 +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__WIDTH 6 +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__MASK 0x0fc00000U +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fc00000U) >> 22) +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x0fc00000U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x0fc00000U) +#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x0fc00000U))) +#define TPC_5_B0__TYPE u_int32_t +#define TPC_5_B0__READ 0x0fffffffU +#define TPC_5_B0__WRITE 0x0fffffffU + +#endif /* __TPC_5_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_5_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_5_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_6_b0 */ +#ifndef __TPC_6_B0_MACRO__ +#define __TPC_6_B0_MACRO__ + +/* macros for field pd_dac_setting_1_0 */ +#define TPC_6_B0__PD_DAC_SETTING_1_0__SHIFT 0 +#define TPC_6_B0__PD_DAC_SETTING_1_0__WIDTH 6 +#define TPC_6_B0__PD_DAC_SETTING_1_0__MASK 0x0000003fU +#define TPC_6_B0__PD_DAC_SETTING_1_0__READ(src) (u_int32_t)(src) & 0x0000003fU +#define TPC_6_B0__PD_DAC_SETTING_1_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define TPC_6_B0__PD_DAC_SETTING_1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TPC_6_B0__PD_DAC_SETTING_1_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field pd_dac_setting_2_0 */ +#define TPC_6_B0__PD_DAC_SETTING_2_0__SHIFT 6 +#define TPC_6_B0__PD_DAC_SETTING_2_0__WIDTH 6 +#define TPC_6_B0__PD_DAC_SETTING_2_0__MASK 0x00000fc0U +#define TPC_6_B0__PD_DAC_SETTING_2_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TPC_6_B0__PD_DAC_SETTING_2_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TPC_6_B0__PD_DAC_SETTING_2_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TPC_6_B0__PD_DAC_SETTING_2_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field pd_dac_setting_3_0 */ +#define TPC_6_B0__PD_DAC_SETTING_3_0__SHIFT 12 +#define TPC_6_B0__PD_DAC_SETTING_3_0__WIDTH 6 +#define TPC_6_B0__PD_DAC_SETTING_3_0__MASK 0x0003f000U +#define TPC_6_B0__PD_DAC_SETTING_3_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define TPC_6_B0__PD_DAC_SETTING_3_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define TPC_6_B0__PD_DAC_SETTING_3_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define TPC_6_B0__PD_DAC_SETTING_3_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field pd_dac_setting_4_0 */ +#define TPC_6_B0__PD_DAC_SETTING_4_0__SHIFT 18 +#define TPC_6_B0__PD_DAC_SETTING_4_0__WIDTH 6 +#define TPC_6_B0__PD_DAC_SETTING_4_0__MASK 0x00fc0000U +#define TPC_6_B0__PD_DAC_SETTING_4_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TPC_6_B0__PD_DAC_SETTING_4_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define TPC_6_B0__PD_DAC_SETTING_4_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define TPC_6_B0__PD_DAC_SETTING_4_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field error_est_mode */ +#define TPC_6_B0__ERROR_EST_MODE__SHIFT 24 +#define TPC_6_B0__ERROR_EST_MODE__WIDTH 2 +#define TPC_6_B0__ERROR_EST_MODE__MASK 0x03000000U +#define TPC_6_B0__ERROR_EST_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x03000000U) >> 24) +#define TPC_6_B0__ERROR_EST_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x03000000U) +#define TPC_6_B0__ERROR_EST_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define TPC_6_B0__ERROR_EST_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field error_est_filter_coeff */ +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__SHIFT 26 +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__WIDTH 3 +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__MASK 0x1c000000U +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TPC_6_B0__ERROR_EST_FILTER_COEFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) +#define TPC_6_B0__TYPE u_int32_t +#define TPC_6_B0__READ 0x1fffffffU +#define TPC_6_B0__WRITE 0x1fffffffU + +#endif /* __TPC_6_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_6_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_6_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_7 */ +#ifndef __TPC_7_MACRO__ +#define __TPC_7_MACRO__ + +/* macros for field tx_gain_table_max */ +#define TPC_7__TX_GAIN_TABLE_MAX__SHIFT 0 +#define TPC_7__TX_GAIN_TABLE_MAX__WIDTH 6 +#define TPC_7__TX_GAIN_TABLE_MAX__MASK 0x0000003fU +#define TPC_7__TX_GAIN_TABLE_MAX__READ(src) (u_int32_t)(src) & 0x0000003fU +#define TPC_7__TX_GAIN_TABLE_MAX__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define TPC_7__TX_GAIN_TABLE_MAX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TPC_7__TX_GAIN_TABLE_MAX__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field init_tx_gain_setting */ +#define TPC_7__INIT_TX_GAIN_SETTING__SHIFT 6 +#define TPC_7__INIT_TX_GAIN_SETTING__WIDTH 6 +#define TPC_7__INIT_TX_GAIN_SETTING__MASK 0x00000fc0U +#define TPC_7__INIT_TX_GAIN_SETTING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TPC_7__INIT_TX_GAIN_SETTING__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TPC_7__INIT_TX_GAIN_SETTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TPC_7__INIT_TX_GAIN_SETTING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field en_cl_gain_mod */ +#define TPC_7__EN_CL_GAIN_MOD__SHIFT 12 +#define TPC_7__EN_CL_GAIN_MOD__WIDTH 1 +#define TPC_7__EN_CL_GAIN_MOD__MASK 0x00001000U +#define TPC_7__EN_CL_GAIN_MOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define TPC_7__EN_CL_GAIN_MOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define TPC_7__EN_CL_GAIN_MOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define TPC_7__EN_CL_GAIN_MOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define TPC_7__EN_CL_GAIN_MOD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define TPC_7__EN_CL_GAIN_MOD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field use_tx_pd_in_xpa */ +#define TPC_7__USE_TX_PD_IN_XPA__SHIFT 13 +#define TPC_7__USE_TX_PD_IN_XPA__WIDTH 1 +#define TPC_7__USE_TX_PD_IN_XPA__MASK 0x00002000U +#define TPC_7__USE_TX_PD_IN_XPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define TPC_7__USE_TX_PD_IN_XPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define TPC_7__USE_TX_PD_IN_XPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TPC_7__USE_TX_PD_IN_XPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TPC_7__USE_TX_PD_IN_XPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TPC_7__USE_TX_PD_IN_XPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field extend_tx_frame_for_tpc */ +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__SHIFT 14 +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__WIDTH 1 +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__MASK 0x00004000U +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field use_init_tx_gain_setting_after_warm_reset */ +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__SHIFT 15 +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__WIDTH 1 +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__MASK 0x00008000U +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) +#define TPC_7__TYPE u_int32_t +#define TPC_7__READ 0x0000ffffU +#define TPC_7__WRITE 0x0000ffffU + +#endif /* __TPC_7_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_7 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_8 */ +#ifndef __TPC_8_MACRO__ +#define __TPC_8_MACRO__ + +/* macros for field desired_scale_0 */ +#define TPC_8__DESIRED_SCALE_0__SHIFT 0 +#define TPC_8__DESIRED_SCALE_0__WIDTH 5 +#define TPC_8__DESIRED_SCALE_0__MASK 0x0000001fU +#define TPC_8__DESIRED_SCALE_0__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_8__DESIRED_SCALE_0__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define TPC_8__DESIRED_SCALE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_8__DESIRED_SCALE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_1 */ +#define TPC_8__DESIRED_SCALE_1__SHIFT 5 +#define TPC_8__DESIRED_SCALE_1__WIDTH 5 +#define TPC_8__DESIRED_SCALE_1__MASK 0x000003e0U +#define TPC_8__DESIRED_SCALE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_8__DESIRED_SCALE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_8__DESIRED_SCALE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_8__DESIRED_SCALE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_2 */ +#define TPC_8__DESIRED_SCALE_2__SHIFT 10 +#define TPC_8__DESIRED_SCALE_2__WIDTH 5 +#define TPC_8__DESIRED_SCALE_2__MASK 0x00007c00U +#define TPC_8__DESIRED_SCALE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_8__DESIRED_SCALE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_8__DESIRED_SCALE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_8__DESIRED_SCALE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field desired_scale_3 */ +#define TPC_8__DESIRED_SCALE_3__SHIFT 15 +#define TPC_8__DESIRED_SCALE_3__WIDTH 5 +#define TPC_8__DESIRED_SCALE_3__MASK 0x000f8000U +#define TPC_8__DESIRED_SCALE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define TPC_8__DESIRED_SCALE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define TPC_8__DESIRED_SCALE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define TPC_8__DESIRED_SCALE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field desired_scale_4 */ +#define TPC_8__DESIRED_SCALE_4__SHIFT 20 +#define TPC_8__DESIRED_SCALE_4__WIDTH 5 +#define TPC_8__DESIRED_SCALE_4__MASK 0x01f00000U +#define TPC_8__DESIRED_SCALE_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_8__DESIRED_SCALE_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define TPC_8__DESIRED_SCALE_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define TPC_8__DESIRED_SCALE_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field desired_scale_5 */ +#define TPC_8__DESIRED_SCALE_5__SHIFT 25 +#define TPC_8__DESIRED_SCALE_5__WIDTH 5 +#define TPC_8__DESIRED_SCALE_5__MASK 0x3e000000U +#define TPC_8__DESIRED_SCALE_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define TPC_8__DESIRED_SCALE_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define TPC_8__DESIRED_SCALE_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define TPC_8__DESIRED_SCALE_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define TPC_8__TYPE u_int32_t +#define TPC_8__READ 0x3fffffffU +#define TPC_8__WRITE 0x3fffffffU + +#endif /* __TPC_8_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_8 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_9 */ +#ifndef __TPC_9_MACRO__ +#define __TPC_9_MACRO__ + +/* macros for field desired_scale_6 */ +#define TPC_9__DESIRED_SCALE_6__SHIFT 0 +#define TPC_9__DESIRED_SCALE_6__WIDTH 5 +#define TPC_9__DESIRED_SCALE_6__MASK 0x0000001fU +#define TPC_9__DESIRED_SCALE_6__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_9__DESIRED_SCALE_6__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define TPC_9__DESIRED_SCALE_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_9__DESIRED_SCALE_6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_7 */ +#define TPC_9__DESIRED_SCALE_7__SHIFT 5 +#define TPC_9__DESIRED_SCALE_7__WIDTH 5 +#define TPC_9__DESIRED_SCALE_7__MASK 0x000003e0U +#define TPC_9__DESIRED_SCALE_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_9__DESIRED_SCALE_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_9__DESIRED_SCALE_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_9__DESIRED_SCALE_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_cck */ +#define TPC_9__DESIRED_SCALE_CCK__SHIFT 10 +#define TPC_9__DESIRED_SCALE_CCK__WIDTH 5 +#define TPC_9__DESIRED_SCALE_CCK__MASK 0x00007c00U +#define TPC_9__DESIRED_SCALE_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_9__DESIRED_SCALE_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_9__DESIRED_SCALE_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_9__DESIRED_SCALE_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field en_pd_dc_offset_thr */ +#define TPC_9__EN_PD_DC_OFFSET_THR__SHIFT 20 +#define TPC_9__EN_PD_DC_OFFSET_THR__WIDTH 1 +#define TPC_9__EN_PD_DC_OFFSET_THR__MASK 0x00100000U +#define TPC_9__EN_PD_DC_OFFSET_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define TPC_9__EN_PD_DC_OFFSET_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define TPC_9__EN_PD_DC_OFFSET_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TPC_9__EN_PD_DC_OFFSET_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TPC_9__EN_PD_DC_OFFSET_THR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TPC_9__EN_PD_DC_OFFSET_THR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field pd_dc_offset_thr */ +#define TPC_9__PD_DC_OFFSET_THR__SHIFT 21 +#define TPC_9__PD_DC_OFFSET_THR__WIDTH 6 +#define TPC_9__PD_DC_OFFSET_THR__MASK 0x07e00000U +#define TPC_9__PD_DC_OFFSET_THR__READ(src) \ + (((u_int32_t)(src)\ + & 0x07e00000U) >> 21) +#define TPC_9__PD_DC_OFFSET_THR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x07e00000U) +#define TPC_9__PD_DC_OFFSET_THR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x07e00000U) +#define TPC_9__PD_DC_OFFSET_THR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x07e00000U))) + +/* macros for field wait_caltx_settle */ +#define TPC_9__WAIT_CALTX_SETTLE__SHIFT 27 +#define TPC_9__WAIT_CALTX_SETTLE__WIDTH 4 +#define TPC_9__WAIT_CALTX_SETTLE__MASK 0x78000000U +#define TPC_9__WAIT_CALTX_SETTLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x78000000U) >> 27) +#define TPC_9__WAIT_CALTX_SETTLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x78000000U) +#define TPC_9__WAIT_CALTX_SETTLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define TPC_9__WAIT_CALTX_SETTLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) + +/* macros for field disable_pdadc_residual_dc_removal */ +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__SHIFT 31 +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__WIDTH 1 +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__MASK 0x80000000U +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TPC_9__TYPE u_int32_t +#define TPC_9__READ 0xfff07fffU +#define TPC_9__WRITE 0xfff07fffU + +#endif /* __TPC_9_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_9 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_10 */ +#ifndef __TPC_10_MACRO__ +#define __TPC_10_MACRO__ + +/* macros for field desired_scale_ht20_0 */ +#define TPC_10__DESIRED_SCALE_HT20_0__SHIFT 0 +#define TPC_10__DESIRED_SCALE_HT20_0__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_0__MASK 0x0000001fU +#define TPC_10__DESIRED_SCALE_HT20_0__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_10__DESIRED_SCALE_HT20_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_10__DESIRED_SCALE_HT20_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_10__DESIRED_SCALE_HT20_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht20_1 */ +#define TPC_10__DESIRED_SCALE_HT20_1__SHIFT 5 +#define TPC_10__DESIRED_SCALE_HT20_1__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_1__MASK 0x000003e0U +#define TPC_10__DESIRED_SCALE_HT20_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_10__DESIRED_SCALE_HT20_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_10__DESIRED_SCALE_HT20_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_10__DESIRED_SCALE_HT20_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_ht20_2 */ +#define TPC_10__DESIRED_SCALE_HT20_2__SHIFT 10 +#define TPC_10__DESIRED_SCALE_HT20_2__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_2__MASK 0x00007c00U +#define TPC_10__DESIRED_SCALE_HT20_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_10__DESIRED_SCALE_HT20_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_10__DESIRED_SCALE_HT20_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_10__DESIRED_SCALE_HT20_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field desired_scale_ht20_3 */ +#define TPC_10__DESIRED_SCALE_HT20_3__SHIFT 15 +#define TPC_10__DESIRED_SCALE_HT20_3__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_3__MASK 0x000f8000U +#define TPC_10__DESIRED_SCALE_HT20_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define TPC_10__DESIRED_SCALE_HT20_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define TPC_10__DESIRED_SCALE_HT20_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define TPC_10__DESIRED_SCALE_HT20_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field desired_scale_ht20_4 */ +#define TPC_10__DESIRED_SCALE_HT20_4__SHIFT 20 +#define TPC_10__DESIRED_SCALE_HT20_4__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_4__MASK 0x01f00000U +#define TPC_10__DESIRED_SCALE_HT20_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_10__DESIRED_SCALE_HT20_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define TPC_10__DESIRED_SCALE_HT20_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define TPC_10__DESIRED_SCALE_HT20_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field desired_scale_ht20_5 */ +#define TPC_10__DESIRED_SCALE_HT20_5__SHIFT 25 +#define TPC_10__DESIRED_SCALE_HT20_5__WIDTH 5 +#define TPC_10__DESIRED_SCALE_HT20_5__MASK 0x3e000000U +#define TPC_10__DESIRED_SCALE_HT20_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define TPC_10__DESIRED_SCALE_HT20_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define TPC_10__DESIRED_SCALE_HT20_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define TPC_10__DESIRED_SCALE_HT20_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define TPC_10__TYPE u_int32_t +#define TPC_10__READ 0x3fffffffU +#define TPC_10__WRITE 0x3fffffffU + +#endif /* __TPC_10_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_10 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_11_b0 */ +#ifndef __TPC_11_B0_MACRO__ +#define __TPC_11_B0_MACRO__ + +/* macros for field desired_scale_ht20_6 */ +#define TPC_11_B0__DESIRED_SCALE_HT20_6__SHIFT 0 +#define TPC_11_B0__DESIRED_SCALE_HT20_6__WIDTH 5 +#define TPC_11_B0__DESIRED_SCALE_HT20_6__MASK 0x0000001fU +#define TPC_11_B0__DESIRED_SCALE_HT20_6__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define TPC_11_B0__DESIRED_SCALE_HT20_6__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_11_B0__DESIRED_SCALE_HT20_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_11_B0__DESIRED_SCALE_HT20_6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht20_7 */ +#define TPC_11_B0__DESIRED_SCALE_HT20_7__SHIFT 5 +#define TPC_11_B0__DESIRED_SCALE_HT20_7__WIDTH 5 +#define TPC_11_B0__DESIRED_SCALE_HT20_7__MASK 0x000003e0U +#define TPC_11_B0__DESIRED_SCALE_HT20_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_11_B0__DESIRED_SCALE_HT20_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_11_B0__DESIRED_SCALE_HT20_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_11_B0__DESIRED_SCALE_HT20_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field olpc_gain_delta_0 */ +#define TPC_11_B0__OLPC_GAIN_DELTA_0__SHIFT 16 +#define TPC_11_B0__OLPC_GAIN_DELTA_0__WIDTH 8 +#define TPC_11_B0__OLPC_GAIN_DELTA_0__MASK 0x00ff0000U +#define TPC_11_B0__OLPC_GAIN_DELTA_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TPC_11_B0__OLPC_GAIN_DELTA_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TPC_11_B0__OLPC_GAIN_DELTA_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TPC_11_B0__OLPC_GAIN_DELTA_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field olpc_gain_delta_0_pal_on */ +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__SHIFT 24 +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__WIDTH 8 +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__MASK 0xff000000U +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TPC_11_B0__TYPE u_int32_t +#define TPC_11_B0__READ 0xffff03ffU +#define TPC_11_B0__WRITE 0xffff03ffU + +#endif /* __TPC_11_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_11_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_11_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_12 */ +#ifndef __TPC_12_MACRO__ +#define __TPC_12_MACRO__ + +/* macros for field desired_scale_ht40_0 */ +#define TPC_12__DESIRED_SCALE_HT40_0__SHIFT 0 +#define TPC_12__DESIRED_SCALE_HT40_0__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_0__MASK 0x0000001fU +#define TPC_12__DESIRED_SCALE_HT40_0__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_12__DESIRED_SCALE_HT40_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_12__DESIRED_SCALE_HT40_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_12__DESIRED_SCALE_HT40_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht40_1 */ +#define TPC_12__DESIRED_SCALE_HT40_1__SHIFT 5 +#define TPC_12__DESIRED_SCALE_HT40_1__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_1__MASK 0x000003e0U +#define TPC_12__DESIRED_SCALE_HT40_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_12__DESIRED_SCALE_HT40_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_12__DESIRED_SCALE_HT40_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_12__DESIRED_SCALE_HT40_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_ht40_2 */ +#define TPC_12__DESIRED_SCALE_HT40_2__SHIFT 10 +#define TPC_12__DESIRED_SCALE_HT40_2__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_2__MASK 0x00007c00U +#define TPC_12__DESIRED_SCALE_HT40_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_12__DESIRED_SCALE_HT40_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_12__DESIRED_SCALE_HT40_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_12__DESIRED_SCALE_HT40_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field desired_scale_ht40_3 */ +#define TPC_12__DESIRED_SCALE_HT40_3__SHIFT 15 +#define TPC_12__DESIRED_SCALE_HT40_3__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_3__MASK 0x000f8000U +#define TPC_12__DESIRED_SCALE_HT40_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define TPC_12__DESIRED_SCALE_HT40_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define TPC_12__DESIRED_SCALE_HT40_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define TPC_12__DESIRED_SCALE_HT40_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field desired_scale_ht40_4 */ +#define TPC_12__DESIRED_SCALE_HT40_4__SHIFT 20 +#define TPC_12__DESIRED_SCALE_HT40_4__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_4__MASK 0x01f00000U +#define TPC_12__DESIRED_SCALE_HT40_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_12__DESIRED_SCALE_HT40_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define TPC_12__DESIRED_SCALE_HT40_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define TPC_12__DESIRED_SCALE_HT40_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field desired_scale_ht40_5 */ +#define TPC_12__DESIRED_SCALE_HT40_5__SHIFT 25 +#define TPC_12__DESIRED_SCALE_HT40_5__WIDTH 5 +#define TPC_12__DESIRED_SCALE_HT40_5__MASK 0x3e000000U +#define TPC_12__DESIRED_SCALE_HT40_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define TPC_12__DESIRED_SCALE_HT40_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define TPC_12__DESIRED_SCALE_HT40_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define TPC_12__DESIRED_SCALE_HT40_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define TPC_12__TYPE u_int32_t +#define TPC_12__READ 0x3fffffffU +#define TPC_12__WRITE 0x3fffffffU + +#endif /* __TPC_12_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_12 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_13 */ +#ifndef __TPC_13_MACRO__ +#define __TPC_13_MACRO__ + +/* macros for field desired_scale_ht40_6 */ +#define TPC_13__DESIRED_SCALE_HT40_6__SHIFT 0 +#define TPC_13__DESIRED_SCALE_HT40_6__WIDTH 5 +#define TPC_13__DESIRED_SCALE_HT40_6__MASK 0x0000001fU +#define TPC_13__DESIRED_SCALE_HT40_6__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_13__DESIRED_SCALE_HT40_6__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_13__DESIRED_SCALE_HT40_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_13__DESIRED_SCALE_HT40_6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht40_7 */ +#define TPC_13__DESIRED_SCALE_HT40_7__SHIFT 5 +#define TPC_13__DESIRED_SCALE_HT40_7__WIDTH 5 +#define TPC_13__DESIRED_SCALE_HT40_7__MASK 0x000003e0U +#define TPC_13__DESIRED_SCALE_HT40_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_13__DESIRED_SCALE_HT40_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_13__DESIRED_SCALE_HT40_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_13__DESIRED_SCALE_HT40_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) +#define TPC_13__TYPE u_int32_t +#define TPC_13__READ 0x000003ffU +#define TPC_13__WRITE 0x000003ffU + +#endif /* __TPC_13_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_13 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_13__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_14 */ +#ifndef __TPC_14_MACRO__ +#define __TPC_14_MACRO__ + +/* macros for field desired_scale_ht20_8 */ +#define TPC_14__DESIRED_SCALE_HT20_8__SHIFT 0 +#define TPC_14__DESIRED_SCALE_HT20_8__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_8__MASK 0x0000001fU +#define TPC_14__DESIRED_SCALE_HT20_8__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_14__DESIRED_SCALE_HT20_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_14__DESIRED_SCALE_HT20_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_14__DESIRED_SCALE_HT20_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht20_9 */ +#define TPC_14__DESIRED_SCALE_HT20_9__SHIFT 5 +#define TPC_14__DESIRED_SCALE_HT20_9__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_9__MASK 0x000003e0U +#define TPC_14__DESIRED_SCALE_HT20_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_14__DESIRED_SCALE_HT20_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_14__DESIRED_SCALE_HT20_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_14__DESIRED_SCALE_HT20_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_ht20_10 */ +#define TPC_14__DESIRED_SCALE_HT20_10__SHIFT 10 +#define TPC_14__DESIRED_SCALE_HT20_10__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_10__MASK 0x00007c00U +#define TPC_14__DESIRED_SCALE_HT20_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_14__DESIRED_SCALE_HT20_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_14__DESIRED_SCALE_HT20_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_14__DESIRED_SCALE_HT20_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field desired_scale_ht20_11 */ +#define TPC_14__DESIRED_SCALE_HT20_11__SHIFT 15 +#define TPC_14__DESIRED_SCALE_HT20_11__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_11__MASK 0x000f8000U +#define TPC_14__DESIRED_SCALE_HT20_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define TPC_14__DESIRED_SCALE_HT20_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define TPC_14__DESIRED_SCALE_HT20_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define TPC_14__DESIRED_SCALE_HT20_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field desired_scale_ht20_12 */ +#define TPC_14__DESIRED_SCALE_HT20_12__SHIFT 20 +#define TPC_14__DESIRED_SCALE_HT20_12__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_12__MASK 0x01f00000U +#define TPC_14__DESIRED_SCALE_HT20_12__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_14__DESIRED_SCALE_HT20_12__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define TPC_14__DESIRED_SCALE_HT20_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define TPC_14__DESIRED_SCALE_HT20_12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field desired_scale_ht20_13 */ +#define TPC_14__DESIRED_SCALE_HT20_13__SHIFT 25 +#define TPC_14__DESIRED_SCALE_HT20_13__WIDTH 5 +#define TPC_14__DESIRED_SCALE_HT20_13__MASK 0x3e000000U +#define TPC_14__DESIRED_SCALE_HT20_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define TPC_14__DESIRED_SCALE_HT20_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define TPC_14__DESIRED_SCALE_HT20_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define TPC_14__DESIRED_SCALE_HT20_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define TPC_14__TYPE u_int32_t +#define TPC_14__READ 0x3fffffffU +#define TPC_14__WRITE 0x3fffffffU + +#endif /* __TPC_14_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_14 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_14__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_15 */ +#ifndef __TPC_15_MACRO__ +#define __TPC_15_MACRO__ + +/* macros for field desired_scale_ht40_8 */ +#define TPC_15__DESIRED_SCALE_HT40_8__SHIFT 0 +#define TPC_15__DESIRED_SCALE_HT40_8__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_8__MASK 0x0000001fU +#define TPC_15__DESIRED_SCALE_HT40_8__READ(src) (u_int32_t)(src) & 0x0000001fU +#define TPC_15__DESIRED_SCALE_HT40_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define TPC_15__DESIRED_SCALE_HT40_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define TPC_15__DESIRED_SCALE_HT40_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field desired_scale_ht40_9 */ +#define TPC_15__DESIRED_SCALE_HT40_9__SHIFT 5 +#define TPC_15__DESIRED_SCALE_HT40_9__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_9__MASK 0x000003e0U +#define TPC_15__DESIRED_SCALE_HT40_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) +#define TPC_15__DESIRED_SCALE_HT40_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000003e0U) +#define TPC_15__DESIRED_SCALE_HT40_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000003e0U) +#define TPC_15__DESIRED_SCALE_HT40_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000003e0U))) + +/* macros for field desired_scale_ht40_10 */ +#define TPC_15__DESIRED_SCALE_HT40_10__SHIFT 10 +#define TPC_15__DESIRED_SCALE_HT40_10__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_10__MASK 0x00007c00U +#define TPC_15__DESIRED_SCALE_HT40_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) +#define TPC_15__DESIRED_SCALE_HT40_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00007c00U) +#define TPC_15__DESIRED_SCALE_HT40_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define TPC_15__DESIRED_SCALE_HT40_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field desired_scale_ht40_11 */ +#define TPC_15__DESIRED_SCALE_HT40_11__SHIFT 15 +#define TPC_15__DESIRED_SCALE_HT40_11__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_11__MASK 0x000f8000U +#define TPC_15__DESIRED_SCALE_HT40_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) +#define TPC_15__DESIRED_SCALE_HT40_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x000f8000U) +#define TPC_15__DESIRED_SCALE_HT40_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x000f8000U) +#define TPC_15__DESIRED_SCALE_HT40_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x000f8000U))) + +/* macros for field desired_scale_ht40_12 */ +#define TPC_15__DESIRED_SCALE_HT40_12__SHIFT 20 +#define TPC_15__DESIRED_SCALE_HT40_12__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_12__MASK 0x01f00000U +#define TPC_15__DESIRED_SCALE_HT40_12__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_15__DESIRED_SCALE_HT40_12__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define TPC_15__DESIRED_SCALE_HT40_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define TPC_15__DESIRED_SCALE_HT40_12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) + +/* macros for field desired_scale_ht40_13 */ +#define TPC_15__DESIRED_SCALE_HT40_13__SHIFT 25 +#define TPC_15__DESIRED_SCALE_HT40_13__WIDTH 5 +#define TPC_15__DESIRED_SCALE_HT40_13__MASK 0x3e000000U +#define TPC_15__DESIRED_SCALE_HT40_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define TPC_15__DESIRED_SCALE_HT40_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x3e000000U) +#define TPC_15__DESIRED_SCALE_HT40_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x3e000000U) +#define TPC_15__DESIRED_SCALE_HT40_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x3e000000U))) +#define TPC_15__TYPE u_int32_t +#define TPC_15__READ 0x3fffffffU +#define TPC_15__WRITE 0x3fffffffU + +#endif /* __TPC_15_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_15 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_15__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_16 */ +#ifndef __TPC_16_MACRO__ +#define __TPC_16_MACRO__ + +/* macros for field pdadc_par_corr_cck */ +#define TPC_16__PDADC_PAR_CORR_CCK__SHIFT 8 +#define TPC_16__PDADC_PAR_CORR_CCK__WIDTH 6 +#define TPC_16__PDADC_PAR_CORR_CCK__MASK 0x00003f00U +#define TPC_16__PDADC_PAR_CORR_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define TPC_16__PDADC_PAR_CORR_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define TPC_16__PDADC_PAR_CORR_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define TPC_16__PDADC_PAR_CORR_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field pdadc_par_corr_ofdm */ +#define TPC_16__PDADC_PAR_CORR_OFDM__SHIFT 16 +#define TPC_16__PDADC_PAR_CORR_OFDM__WIDTH 6 +#define TPC_16__PDADC_PAR_CORR_OFDM__MASK 0x003f0000U +#define TPC_16__PDADC_PAR_CORR_OFDM__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define TPC_16__PDADC_PAR_CORR_OFDM__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define TPC_16__PDADC_PAR_CORR_OFDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define TPC_16__PDADC_PAR_CORR_OFDM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field pdadc_par_corr_ht40 */ +#define TPC_16__PDADC_PAR_CORR_HT40__SHIFT 24 +#define TPC_16__PDADC_PAR_CORR_HT40__WIDTH 6 +#define TPC_16__PDADC_PAR_CORR_HT40__MASK 0x3f000000U +#define TPC_16__PDADC_PAR_CORR_HT40__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define TPC_16__PDADC_PAR_CORR_HT40__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define TPC_16__PDADC_PAR_CORR_HT40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define TPC_16__PDADC_PAR_CORR_HT40__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define TPC_16__TYPE u_int32_t +#define TPC_16__READ 0x3f3f3f00U +#define TPC_16__WRITE 0x3f3f3f00U + +#endif /* __TPC_16_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_16 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_17 */ +#ifndef __TPC_17_MACRO__ +#define __TPC_17_MACRO__ + +/* macros for field enable_pal */ +#define TPC_17__ENABLE_PAL__SHIFT 0 +#define TPC_17__ENABLE_PAL__WIDTH 1 +#define TPC_17__ENABLE_PAL__MASK 0x00000001U +#define TPC_17__ENABLE_PAL__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_17__ENABLE_PAL__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TPC_17__ENABLE_PAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TPC_17__ENABLE_PAL__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TPC_17__ENABLE_PAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_17__ENABLE_PAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field enable_pal_cck */ +#define TPC_17__ENABLE_PAL_CCK__SHIFT 1 +#define TPC_17__ENABLE_PAL_CCK__WIDTH 1 +#define TPC_17__ENABLE_PAL_CCK__MASK 0x00000002U +#define TPC_17__ENABLE_PAL_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define TPC_17__ENABLE_PAL_CCK__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define TPC_17__ENABLE_PAL_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define TPC_17__ENABLE_PAL_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define TPC_17__ENABLE_PAL_CCK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TPC_17__ENABLE_PAL_CCK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field enable_pal_ofdm_20 */ +#define TPC_17__ENABLE_PAL_OFDM_20__SHIFT 2 +#define TPC_17__ENABLE_PAL_OFDM_20__WIDTH 1 +#define TPC_17__ENABLE_PAL_OFDM_20__MASK 0x00000004U +#define TPC_17__ENABLE_PAL_OFDM_20__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define TPC_17__ENABLE_PAL_OFDM_20__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define TPC_17__ENABLE_PAL_OFDM_20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define TPC_17__ENABLE_PAL_OFDM_20__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define TPC_17__ENABLE_PAL_OFDM_20__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TPC_17__ENABLE_PAL_OFDM_20__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field enable_pal_ofdm_40 */ +#define TPC_17__ENABLE_PAL_OFDM_40__SHIFT 3 +#define TPC_17__ENABLE_PAL_OFDM_40__WIDTH 1 +#define TPC_17__ENABLE_PAL_OFDM_40__MASK 0x00000008U +#define TPC_17__ENABLE_PAL_OFDM_40__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define TPC_17__ENABLE_PAL_OFDM_40__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define TPC_17__ENABLE_PAL_OFDM_40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TPC_17__ENABLE_PAL_OFDM_40__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define TPC_17__ENABLE_PAL_OFDM_40__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TPC_17__ENABLE_PAL_OFDM_40__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field pal_power_threshold */ +#define TPC_17__PAL_POWER_THRESHOLD__SHIFT 4 +#define TPC_17__PAL_POWER_THRESHOLD__WIDTH 6 +#define TPC_17__PAL_POWER_THRESHOLD__MASK 0x000003f0U +#define TPC_17__PAL_POWER_THRESHOLD__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define TPC_17__PAL_POWER_THRESHOLD__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define TPC_17__PAL_POWER_THRESHOLD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define TPC_17__PAL_POWER_THRESHOLD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field force_pal_locked */ +#define TPC_17__FORCE_PAL_LOCKED__SHIFT 10 +#define TPC_17__FORCE_PAL_LOCKED__WIDTH 1 +#define TPC_17__FORCE_PAL_LOCKED__MASK 0x00000400U +#define TPC_17__FORCE_PAL_LOCKED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define TPC_17__FORCE_PAL_LOCKED__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define TPC_17__FORCE_PAL_LOCKED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TPC_17__FORCE_PAL_LOCKED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TPC_17__FORCE_PAL_LOCKED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TPC_17__FORCE_PAL_LOCKED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field init_tx_gain_setting_pal_on */ +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__SHIFT 11 +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__WIDTH 6 +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__MASK 0x0001f800U +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f800U) >> 11) +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x0001f800U) +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0001f800U) +#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0001f800U))) +#define TPC_17__TYPE u_int32_t +#define TPC_17__READ 0x0001ffffU +#define TPC_17__WRITE 0x0001ffffU + +#endif /* __TPC_17_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_17 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_17__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_18 */ +#ifndef __TPC_18_MACRO__ +#define __TPC_18_MACRO__ + +/* macros for field therm_cal_value */ +#define TPC_18__THERM_CAL_VALUE__SHIFT 0 +#define TPC_18__THERM_CAL_VALUE__WIDTH 8 +#define TPC_18__THERM_CAL_VALUE__MASK 0x000000ffU +#define TPC_18__THERM_CAL_VALUE__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TPC_18__THERM_CAL_VALUE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define TPC_18__THERM_CAL_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TPC_18__THERM_CAL_VALUE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field volt_cal_value */ +#define TPC_18__VOLT_CAL_VALUE__SHIFT 8 +#define TPC_18__VOLT_CAL_VALUE__WIDTH 8 +#define TPC_18__VOLT_CAL_VALUE__MASK 0x0000ff00U +#define TPC_18__VOLT_CAL_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TPC_18__VOLT_CAL_VALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TPC_18__VOLT_CAL_VALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TPC_18__VOLT_CAL_VALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field use_legacy_tpc */ +#define TPC_18__USE_LEGACY_TPC__SHIFT 16 +#define TPC_18__USE_LEGACY_TPC__WIDTH 1 +#define TPC_18__USE_LEGACY_TPC__MASK 0x00010000U +#define TPC_18__USE_LEGACY_TPC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define TPC_18__USE_LEGACY_TPC__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define TPC_18__USE_LEGACY_TPC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define TPC_18__USE_LEGACY_TPC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define TPC_18__USE_LEGACY_TPC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define TPC_18__USE_LEGACY_TPC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field min_power_therm_volt_gain_corr */ +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__SHIFT 17 +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__WIDTH 6 +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__MASK 0x007e0000U +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__READ(src) \ + (((u_int32_t)(src)\ + & 0x007e0000U) >> 17) +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x007e0000U) +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x007e0000U) +#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x007e0000U))) +#define TPC_18__TYPE u_int32_t +#define TPC_18__READ 0x007fffffU +#define TPC_18__WRITE 0x007fffffU + +#endif /* __TPC_18_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_18 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_18__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_19_b0 */ +#ifndef __TPC_19_B0_MACRO__ +#define __TPC_19_B0_MACRO__ + +/* macros for field alpha_therm_0 */ +#define TPC_19_B0__ALPHA_THERM_0__SHIFT 0 +#define TPC_19_B0__ALPHA_THERM_0__WIDTH 8 +#define TPC_19_B0__ALPHA_THERM_0__MASK 0x000000ffU +#define TPC_19_B0__ALPHA_THERM_0__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TPC_19_B0__ALPHA_THERM_0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define TPC_19_B0__ALPHA_THERM_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TPC_19_B0__ALPHA_THERM_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field alpha_therm_pal_on_0 */ +#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__SHIFT 8 +#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__WIDTH 8 +#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__MASK 0x0000ff00U +#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field alpha_volt_0 */ +#define TPC_19_B0__ALPHA_VOLT_0__SHIFT 16 +#define TPC_19_B0__ALPHA_VOLT_0__WIDTH 7 +#define TPC_19_B0__ALPHA_VOLT_0__MASK 0x007f0000U +#define TPC_19_B0__ALPHA_VOLT_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) +#define TPC_19_B0__ALPHA_VOLT_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x007f0000U) +#define TPC_19_B0__ALPHA_VOLT_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x007f0000U) +#define TPC_19_B0__ALPHA_VOLT_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x007f0000U))) + +/* macros for field alpha_volt_pal_on_0 */ +#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__SHIFT 23 +#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__WIDTH 7 +#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__MASK 0x3f800000U +#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f800000U) >> 23) +#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x3f800000U) +#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x3f800000U) +#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x3f800000U))) +#define TPC_19_B0__TYPE u_int32_t +#define TPC_19_B0__READ 0x3fffffffU +#define TPC_19_B0__WRITE 0x3fffffffU + +#endif /* __TPC_19_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_19_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_19_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_20 */ +#ifndef __TPC_20_MACRO__ +#define __TPC_20_MACRO__ + +/* macros for field enable_pal_mcs_0 */ +#define TPC_20__ENABLE_PAL_MCS_0__SHIFT 0 +#define TPC_20__ENABLE_PAL_MCS_0__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_0__MASK 0x00000001U +#define TPC_20__ENABLE_PAL_MCS_0__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_20__ENABLE_PAL_MCS_0__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TPC_20__ENABLE_PAL_MCS_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TPC_20__ENABLE_PAL_MCS_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TPC_20__ENABLE_PAL_MCS_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_20__ENABLE_PAL_MCS_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field enable_pal_mcs_1 */ +#define TPC_20__ENABLE_PAL_MCS_1__SHIFT 1 +#define TPC_20__ENABLE_PAL_MCS_1__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_1__MASK 0x00000002U +#define TPC_20__ENABLE_PAL_MCS_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define TPC_20__ENABLE_PAL_MCS_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define TPC_20__ENABLE_PAL_MCS_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define TPC_20__ENABLE_PAL_MCS_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define TPC_20__ENABLE_PAL_MCS_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TPC_20__ENABLE_PAL_MCS_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field enable_pal_mcs_2 */ +#define TPC_20__ENABLE_PAL_MCS_2__SHIFT 2 +#define TPC_20__ENABLE_PAL_MCS_2__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_2__MASK 0x00000004U +#define TPC_20__ENABLE_PAL_MCS_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define TPC_20__ENABLE_PAL_MCS_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define TPC_20__ENABLE_PAL_MCS_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define TPC_20__ENABLE_PAL_MCS_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define TPC_20__ENABLE_PAL_MCS_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TPC_20__ENABLE_PAL_MCS_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field enable_pal_mcs_3 */ +#define TPC_20__ENABLE_PAL_MCS_3__SHIFT 3 +#define TPC_20__ENABLE_PAL_MCS_3__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_3__MASK 0x00000008U +#define TPC_20__ENABLE_PAL_MCS_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define TPC_20__ENABLE_PAL_MCS_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define TPC_20__ENABLE_PAL_MCS_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TPC_20__ENABLE_PAL_MCS_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define TPC_20__ENABLE_PAL_MCS_3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TPC_20__ENABLE_PAL_MCS_3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field enable_pal_mcs_4 */ +#define TPC_20__ENABLE_PAL_MCS_4__SHIFT 4 +#define TPC_20__ENABLE_PAL_MCS_4__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_4__MASK 0x00000010U +#define TPC_20__ENABLE_PAL_MCS_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define TPC_20__ENABLE_PAL_MCS_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define TPC_20__ENABLE_PAL_MCS_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define TPC_20__ENABLE_PAL_MCS_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define TPC_20__ENABLE_PAL_MCS_4__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define TPC_20__ENABLE_PAL_MCS_4__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field enable_pal_mcs_5 */ +#define TPC_20__ENABLE_PAL_MCS_5__SHIFT 5 +#define TPC_20__ENABLE_PAL_MCS_5__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_5__MASK 0x00000020U +#define TPC_20__ENABLE_PAL_MCS_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define TPC_20__ENABLE_PAL_MCS_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define TPC_20__ENABLE_PAL_MCS_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define TPC_20__ENABLE_PAL_MCS_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define TPC_20__ENABLE_PAL_MCS_5__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define TPC_20__ENABLE_PAL_MCS_5__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field enable_pal_mcs_6 */ +#define TPC_20__ENABLE_PAL_MCS_6__SHIFT 6 +#define TPC_20__ENABLE_PAL_MCS_6__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_6__MASK 0x00000040U +#define TPC_20__ENABLE_PAL_MCS_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define TPC_20__ENABLE_PAL_MCS_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define TPC_20__ENABLE_PAL_MCS_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define TPC_20__ENABLE_PAL_MCS_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define TPC_20__ENABLE_PAL_MCS_6__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define TPC_20__ENABLE_PAL_MCS_6__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field enable_pal_mcs_7 */ +#define TPC_20__ENABLE_PAL_MCS_7__SHIFT 7 +#define TPC_20__ENABLE_PAL_MCS_7__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_7__MASK 0x00000080U +#define TPC_20__ENABLE_PAL_MCS_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define TPC_20__ENABLE_PAL_MCS_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define TPC_20__ENABLE_PAL_MCS_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define TPC_20__ENABLE_PAL_MCS_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define TPC_20__ENABLE_PAL_MCS_7__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define TPC_20__ENABLE_PAL_MCS_7__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field enable_pal_mcs_8 */ +#define TPC_20__ENABLE_PAL_MCS_8__SHIFT 8 +#define TPC_20__ENABLE_PAL_MCS_8__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_8__MASK 0x00000100U +#define TPC_20__ENABLE_PAL_MCS_8__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define TPC_20__ENABLE_PAL_MCS_8__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define TPC_20__ENABLE_PAL_MCS_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define TPC_20__ENABLE_PAL_MCS_8__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define TPC_20__ENABLE_PAL_MCS_8__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define TPC_20__ENABLE_PAL_MCS_8__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field enable_pal_mcs_9 */ +#define TPC_20__ENABLE_PAL_MCS_9__SHIFT 9 +#define TPC_20__ENABLE_PAL_MCS_9__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_9__MASK 0x00000200U +#define TPC_20__ENABLE_PAL_MCS_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define TPC_20__ENABLE_PAL_MCS_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define TPC_20__ENABLE_PAL_MCS_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define TPC_20__ENABLE_PAL_MCS_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define TPC_20__ENABLE_PAL_MCS_9__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define TPC_20__ENABLE_PAL_MCS_9__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field enable_pal_mcs_10 */ +#define TPC_20__ENABLE_PAL_MCS_10__SHIFT 10 +#define TPC_20__ENABLE_PAL_MCS_10__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_10__MASK 0x00000400U +#define TPC_20__ENABLE_PAL_MCS_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define TPC_20__ENABLE_PAL_MCS_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define TPC_20__ENABLE_PAL_MCS_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TPC_20__ENABLE_PAL_MCS_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TPC_20__ENABLE_PAL_MCS_10__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TPC_20__ENABLE_PAL_MCS_10__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field enable_pal_mcs_11 */ +#define TPC_20__ENABLE_PAL_MCS_11__SHIFT 11 +#define TPC_20__ENABLE_PAL_MCS_11__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_11__MASK 0x00000800U +#define TPC_20__ENABLE_PAL_MCS_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define TPC_20__ENABLE_PAL_MCS_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define TPC_20__ENABLE_PAL_MCS_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define TPC_20__ENABLE_PAL_MCS_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define TPC_20__ENABLE_PAL_MCS_11__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define TPC_20__ENABLE_PAL_MCS_11__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field enable_pal_mcs_12 */ +#define TPC_20__ENABLE_PAL_MCS_12__SHIFT 12 +#define TPC_20__ENABLE_PAL_MCS_12__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_12__MASK 0x00001000U +#define TPC_20__ENABLE_PAL_MCS_12__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define TPC_20__ENABLE_PAL_MCS_12__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define TPC_20__ENABLE_PAL_MCS_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define TPC_20__ENABLE_PAL_MCS_12__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define TPC_20__ENABLE_PAL_MCS_12__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define TPC_20__ENABLE_PAL_MCS_12__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field enable_pal_mcs_13 */ +#define TPC_20__ENABLE_PAL_MCS_13__SHIFT 13 +#define TPC_20__ENABLE_PAL_MCS_13__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_13__MASK 0x00002000U +#define TPC_20__ENABLE_PAL_MCS_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define TPC_20__ENABLE_PAL_MCS_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define TPC_20__ENABLE_PAL_MCS_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TPC_20__ENABLE_PAL_MCS_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TPC_20__ENABLE_PAL_MCS_13__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TPC_20__ENABLE_PAL_MCS_13__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field enable_pal_mcs_14 */ +#define TPC_20__ENABLE_PAL_MCS_14__SHIFT 14 +#define TPC_20__ENABLE_PAL_MCS_14__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_14__MASK 0x00004000U +#define TPC_20__ENABLE_PAL_MCS_14__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define TPC_20__ENABLE_PAL_MCS_14__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define TPC_20__ENABLE_PAL_MCS_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define TPC_20__ENABLE_PAL_MCS_14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define TPC_20__ENABLE_PAL_MCS_14__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define TPC_20__ENABLE_PAL_MCS_14__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field enable_pal_mcs_15 */ +#define TPC_20__ENABLE_PAL_MCS_15__SHIFT 15 +#define TPC_20__ENABLE_PAL_MCS_15__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_15__MASK 0x00008000U +#define TPC_20__ENABLE_PAL_MCS_15__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TPC_20__ENABLE_PAL_MCS_15__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TPC_20__ENABLE_PAL_MCS_15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TPC_20__ENABLE_PAL_MCS_15__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TPC_20__ENABLE_PAL_MCS_15__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TPC_20__ENABLE_PAL_MCS_15__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field enable_pal_mcs_16 */ +#define TPC_20__ENABLE_PAL_MCS_16__SHIFT 16 +#define TPC_20__ENABLE_PAL_MCS_16__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_16__MASK 0x00010000U +#define TPC_20__ENABLE_PAL_MCS_16__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define TPC_20__ENABLE_PAL_MCS_16__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define TPC_20__ENABLE_PAL_MCS_16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define TPC_20__ENABLE_PAL_MCS_16__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define TPC_20__ENABLE_PAL_MCS_16__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define TPC_20__ENABLE_PAL_MCS_16__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field enable_pal_mcs_17 */ +#define TPC_20__ENABLE_PAL_MCS_17__SHIFT 17 +#define TPC_20__ENABLE_PAL_MCS_17__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_17__MASK 0x00020000U +#define TPC_20__ENABLE_PAL_MCS_17__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define TPC_20__ENABLE_PAL_MCS_17__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define TPC_20__ENABLE_PAL_MCS_17__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define TPC_20__ENABLE_PAL_MCS_17__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define TPC_20__ENABLE_PAL_MCS_17__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define TPC_20__ENABLE_PAL_MCS_17__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field enable_pal_mcs_18 */ +#define TPC_20__ENABLE_PAL_MCS_18__SHIFT 18 +#define TPC_20__ENABLE_PAL_MCS_18__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_18__MASK 0x00040000U +#define TPC_20__ENABLE_PAL_MCS_18__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define TPC_20__ENABLE_PAL_MCS_18__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define TPC_20__ENABLE_PAL_MCS_18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define TPC_20__ENABLE_PAL_MCS_18__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define TPC_20__ENABLE_PAL_MCS_18__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define TPC_20__ENABLE_PAL_MCS_18__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field enable_pal_mcs_19 */ +#define TPC_20__ENABLE_PAL_MCS_19__SHIFT 19 +#define TPC_20__ENABLE_PAL_MCS_19__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_19__MASK 0x00080000U +#define TPC_20__ENABLE_PAL_MCS_19__READ(src) \ + (((u_int32_t)(src)\ + & 0x00080000U) >> 19) +#define TPC_20__ENABLE_PAL_MCS_19__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define TPC_20__ENABLE_PAL_MCS_19__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TPC_20__ENABLE_PAL_MCS_19__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TPC_20__ENABLE_PAL_MCS_19__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TPC_20__ENABLE_PAL_MCS_19__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field enable_pal_mcs_20 */ +#define TPC_20__ENABLE_PAL_MCS_20__SHIFT 20 +#define TPC_20__ENABLE_PAL_MCS_20__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_20__MASK 0x00100000U +#define TPC_20__ENABLE_PAL_MCS_20__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define TPC_20__ENABLE_PAL_MCS_20__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define TPC_20__ENABLE_PAL_MCS_20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TPC_20__ENABLE_PAL_MCS_20__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TPC_20__ENABLE_PAL_MCS_20__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TPC_20__ENABLE_PAL_MCS_20__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field enable_pal_mcs_21 */ +#define TPC_20__ENABLE_PAL_MCS_21__SHIFT 21 +#define TPC_20__ENABLE_PAL_MCS_21__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_21__MASK 0x00200000U +#define TPC_20__ENABLE_PAL_MCS_21__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define TPC_20__ENABLE_PAL_MCS_21__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define TPC_20__ENABLE_PAL_MCS_21__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define TPC_20__ENABLE_PAL_MCS_21__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define TPC_20__ENABLE_PAL_MCS_21__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define TPC_20__ENABLE_PAL_MCS_21__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field enable_pal_mcs_22 */ +#define TPC_20__ENABLE_PAL_MCS_22__SHIFT 22 +#define TPC_20__ENABLE_PAL_MCS_22__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_22__MASK 0x00400000U +#define TPC_20__ENABLE_PAL_MCS_22__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define TPC_20__ENABLE_PAL_MCS_22__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define TPC_20__ENABLE_PAL_MCS_22__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TPC_20__ENABLE_PAL_MCS_22__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TPC_20__ENABLE_PAL_MCS_22__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TPC_20__ENABLE_PAL_MCS_22__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field enable_pal_mcs_23 */ +#define TPC_20__ENABLE_PAL_MCS_23__SHIFT 23 +#define TPC_20__ENABLE_PAL_MCS_23__WIDTH 1 +#define TPC_20__ENABLE_PAL_MCS_23__MASK 0x00800000U +#define TPC_20__ENABLE_PAL_MCS_23__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TPC_20__ENABLE_PAL_MCS_23__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TPC_20__ENABLE_PAL_MCS_23__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TPC_20__ENABLE_PAL_MCS_23__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TPC_20__ENABLE_PAL_MCS_23__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TPC_20__ENABLE_PAL_MCS_23__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) +#define TPC_20__TYPE u_int32_t +#define TPC_20__READ 0x00ffffffU +#define TPC_20__WRITE 0x00ffffffU + +#endif /* __TPC_20_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_20 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::therm_adc_1 */ +#ifndef __THERM_ADC_1_MACRO__ +#define __THERM_ADC_1_MACRO__ + +/* macros for field init_therm_setting */ +#define THERM_ADC_1__INIT_THERM_SETTING__SHIFT 0 +#define THERM_ADC_1__INIT_THERM_SETTING__WIDTH 8 +#define THERM_ADC_1__INIT_THERM_SETTING__MASK 0x000000ffU +#define THERM_ADC_1__INIT_THERM_SETTING__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define THERM_ADC_1__INIT_THERM_SETTING__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define THERM_ADC_1__INIT_THERM_SETTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define THERM_ADC_1__INIT_THERM_SETTING__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field init_volt_setting */ +#define THERM_ADC_1__INIT_VOLT_SETTING__SHIFT 8 +#define THERM_ADC_1__INIT_VOLT_SETTING__WIDTH 8 +#define THERM_ADC_1__INIT_VOLT_SETTING__MASK 0x0000ff00U +#define THERM_ADC_1__INIT_VOLT_SETTING__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define THERM_ADC_1__INIT_VOLT_SETTING__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define THERM_ADC_1__INIT_VOLT_SETTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define THERM_ADC_1__INIT_VOLT_SETTING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field init_atb_setting */ +#define THERM_ADC_1__INIT_ATB_SETTING__SHIFT 16 +#define THERM_ADC_1__INIT_ATB_SETTING__WIDTH 8 +#define THERM_ADC_1__INIT_ATB_SETTING__MASK 0x00ff0000U +#define THERM_ADC_1__INIT_ATB_SETTING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define THERM_ADC_1__INIT_ATB_SETTING__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define THERM_ADC_1__INIT_ATB_SETTING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define THERM_ADC_1__INIT_ATB_SETTING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field samples_cnt_coding */ +#define THERM_ADC_1__SAMPLES_CNT_CODING__SHIFT 24 +#define THERM_ADC_1__SAMPLES_CNT_CODING__WIDTH 2 +#define THERM_ADC_1__SAMPLES_CNT_CODING__MASK 0x03000000U +#define THERM_ADC_1__SAMPLES_CNT_CODING__READ(src) \ + (((u_int32_t)(src)\ + & 0x03000000U) >> 24) +#define THERM_ADC_1__SAMPLES_CNT_CODING__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x03000000U) +#define THERM_ADC_1__SAMPLES_CNT_CODING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define THERM_ADC_1__SAMPLES_CNT_CODING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field use_init_therm_volt_atb_after_warm_reset */ +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__SHIFT 26 +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__WIDTH 1 +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__MASK 0x04000000U +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field force_therm_volt_atb_to_init_settings */ +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__SHIFT 27 +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__WIDTH 1 +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__MASK 0x08000000U +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field check_done_for_1st_adc_meas_of_each_frame */ +#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__SHIFT 28 +#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__WIDTH 1 +#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__MASK \ + 0x10000000U +#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field therm_measure_reset */ +#define THERM_ADC_1__THERM_MEASURE_RESET__SHIFT 29 +#define THERM_ADC_1__THERM_MEASURE_RESET__WIDTH 1 +#define THERM_ADC_1__THERM_MEASURE_RESET__MASK 0x20000000U +#define THERM_ADC_1__THERM_MEASURE_RESET__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define THERM_ADC_1__THERM_MEASURE_RESET__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define THERM_ADC_1__THERM_MEASURE_RESET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define THERM_ADC_1__THERM_MEASURE_RESET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define THERM_ADC_1__THERM_MEASURE_RESET__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define THERM_ADC_1__THERM_MEASURE_RESET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define THERM_ADC_1__TYPE u_int32_t +#define THERM_ADC_1__READ 0x3fffffffU +#define THERM_ADC_1__WRITE 0x3fffffffU + +#endif /* __THERM_ADC_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::therm_adc_2 */ +#ifndef __THERM_ADC_2_MACRO__ +#define __THERM_ADC_2_MACRO__ + +/* macros for field measure_therm_freq */ +#define THERM_ADC_2__MEASURE_THERM_FREQ__SHIFT 0 +#define THERM_ADC_2__MEASURE_THERM_FREQ__WIDTH 12 +#define THERM_ADC_2__MEASURE_THERM_FREQ__MASK 0x00000fffU +#define THERM_ADC_2__MEASURE_THERM_FREQ__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define THERM_ADC_2__MEASURE_THERM_FREQ__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define THERM_ADC_2__MEASURE_THERM_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define THERM_ADC_2__MEASURE_THERM_FREQ__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field measure_volt_freq */ +#define THERM_ADC_2__MEASURE_VOLT_FREQ__SHIFT 12 +#define THERM_ADC_2__MEASURE_VOLT_FREQ__WIDTH 10 +#define THERM_ADC_2__MEASURE_VOLT_FREQ__MASK 0x003ff000U +#define THERM_ADC_2__MEASURE_VOLT_FREQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x003ff000U) >> 12) +#define THERM_ADC_2__MEASURE_VOLT_FREQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x003ff000U) +#define THERM_ADC_2__MEASURE_VOLT_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x003ff000U) +#define THERM_ADC_2__MEASURE_VOLT_FREQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x003ff000U))) + +/* macros for field measure_atb_freq */ +#define THERM_ADC_2__MEASURE_ATB_FREQ__SHIFT 22 +#define THERM_ADC_2__MEASURE_ATB_FREQ__WIDTH 10 +#define THERM_ADC_2__MEASURE_ATB_FREQ__MASK 0xffc00000U +#define THERM_ADC_2__MEASURE_ATB_FREQ__READ(src) \ + (((u_int32_t)(src)\ + & 0xffc00000U) >> 22) +#define THERM_ADC_2__MEASURE_ATB_FREQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0xffc00000U) +#define THERM_ADC_2__MEASURE_ATB_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffc00000U) | (((u_int32_t)(src) <<\ + 22) & 0xffc00000U) +#define THERM_ADC_2__MEASURE_ATB_FREQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0xffc00000U))) +#define THERM_ADC_2__TYPE u_int32_t +#define THERM_ADC_2__READ 0xffffffffU +#define THERM_ADC_2__WRITE 0xffffffffU + +#endif /* __THERM_ADC_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::therm_adc_3 */ +#ifndef __THERM_ADC_3_MACRO__ +#define __THERM_ADC_3_MACRO__ + +/* macros for field therm_adc_offset */ +#define THERM_ADC_3__THERM_ADC_OFFSET__SHIFT 0 +#define THERM_ADC_3__THERM_ADC_OFFSET__WIDTH 8 +#define THERM_ADC_3__THERM_ADC_OFFSET__MASK 0x000000ffU +#define THERM_ADC_3__THERM_ADC_OFFSET__READ(src) (u_int32_t)(src) & 0x000000ffU +#define THERM_ADC_3__THERM_ADC_OFFSET__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define THERM_ADC_3__THERM_ADC_OFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define THERM_ADC_3__THERM_ADC_OFFSET__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field therm_adc_scaled_gain */ +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__SHIFT 8 +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__WIDTH 9 +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__MASK 0x0001ff00U +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001ff00U) >> 8) +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0001ff00U) +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0001ff00U) +#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0001ff00U))) + +/* macros for field adc_interval */ +#define THERM_ADC_3__ADC_INTERVAL__SHIFT 17 +#define THERM_ADC_3__ADC_INTERVAL__WIDTH 13 +#define THERM_ADC_3__ADC_INTERVAL__MASK 0x3ffe0000U +#define THERM_ADC_3__ADC_INTERVAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ffe0000U) >> 17) +#define THERM_ADC_3__ADC_INTERVAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x3ffe0000U) +#define THERM_ADC_3__ADC_INTERVAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ffe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x3ffe0000U) +#define THERM_ADC_3__ADC_INTERVAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x3ffe0000U))) +#define THERM_ADC_3__TYPE u_int32_t +#define THERM_ADC_3__READ 0x3fffffffU +#define THERM_ADC_3__WRITE 0x3fffffffU + +#endif /* __THERM_ADC_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_3 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::therm_adc_4 */ +#ifndef __THERM_ADC_4_MACRO__ +#define __THERM_ADC_4_MACRO__ + +/* macros for field latest_therm_value */ +#define THERM_ADC_4__LATEST_THERM_VALUE__SHIFT 0 +#define THERM_ADC_4__LATEST_THERM_VALUE__WIDTH 8 +#define THERM_ADC_4__LATEST_THERM_VALUE__MASK 0x000000ffU +#define THERM_ADC_4__LATEST_THERM_VALUE__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field latest_volt_value */ +#define THERM_ADC_4__LATEST_VOLT_VALUE__SHIFT 8 +#define THERM_ADC_4__LATEST_VOLT_VALUE__WIDTH 8 +#define THERM_ADC_4__LATEST_VOLT_VALUE__MASK 0x0000ff00U +#define THERM_ADC_4__LATEST_VOLT_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field latest_atb_value */ +#define THERM_ADC_4__LATEST_ATB_VALUE__SHIFT 16 +#define THERM_ADC_4__LATEST_ATB_VALUE__WIDTH 8 +#define THERM_ADC_4__LATEST_ATB_VALUE__MASK 0x00ff0000U +#define THERM_ADC_4__LATEST_ATB_VALUE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) + +/* macros for field force_therm_chain */ +#define THERM_ADC_4__FORCE_THERM_CHAIN__SHIFT 24 +#define THERM_ADC_4__FORCE_THERM_CHAIN__WIDTH 1 +#define THERM_ADC_4__FORCE_THERM_CHAIN__MASK 0x01000000U +#define THERM_ADC_4__FORCE_THERM_CHAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define THERM_ADC_4__FORCE_THERM_CHAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define THERM_ADC_4__FORCE_THERM_CHAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define THERM_ADC_4__FORCE_THERM_CHAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define THERM_ADC_4__FORCE_THERM_CHAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define THERM_ADC_4__FORCE_THERM_CHAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field preferred_therm_chain */ +#define THERM_ADC_4__PREFERRED_THERM_CHAIN__SHIFT 25 +#define THERM_ADC_4__PREFERRED_THERM_CHAIN__WIDTH 3 +#define THERM_ADC_4__PREFERRED_THERM_CHAIN__MASK 0x0e000000U +#define THERM_ADC_4__PREFERRED_THERM_CHAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0e000000U) >> 25) +#define THERM_ADC_4__PREFERRED_THERM_CHAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x0e000000U) +#define THERM_ADC_4__PREFERRED_THERM_CHAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x0e000000U) +#define THERM_ADC_4__PREFERRED_THERM_CHAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x0e000000U))) +#define THERM_ADC_4__TYPE u_int32_t +#define THERM_ADC_4__READ 0x0fffffffU +#define THERM_ADC_4__WRITE 0x0fffffffU + +#endif /* __THERM_ADC_4_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_4 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_forced_gain */ +#ifndef __TX_FORCED_GAIN_MACRO__ +#define __TX_FORCED_GAIN_MACRO__ + +/* macros for field force_tx_gain */ +#define TX_FORCED_GAIN__FORCE_TX_GAIN__SHIFT 0 +#define TX_FORCED_GAIN__FORCE_TX_GAIN__WIDTH 1 +#define TX_FORCED_GAIN__FORCE_TX_GAIN__MASK 0x00000001U +#define TX_FORCED_GAIN__FORCE_TX_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U +#define TX_FORCED_GAIN__FORCE_TX_GAIN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TX_FORCED_GAIN__FORCE_TX_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TX_FORCED_GAIN__FORCE_TX_GAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TX_FORCED_GAIN__FORCE_TX_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TX_FORCED_GAIN__FORCE_TX_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field forced_txbb1dbgain */ +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__SHIFT 1 +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__WIDTH 3 +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__MASK 0x0000000eU +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field forced_txbb6dbgain */ +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__SHIFT 4 +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__WIDTH 2 +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__MASK 0x00000030U +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field forced_txmxrgain */ +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__SHIFT 6 +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__WIDTH 4 +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__MASK 0x000003c0U +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003c0U) >> 6) +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000003c0U) +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000003c0U) +#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000003c0U))) + +/* macros for field forced_padrvgnA */ +#define TX_FORCED_GAIN__FORCED_PADRVGNA__SHIFT 10 +#define TX_FORCED_GAIN__FORCED_PADRVGNA__WIDTH 4 +#define TX_FORCED_GAIN__FORCED_PADRVGNA__MASK 0x00003c00U +#define TX_FORCED_GAIN__FORCED_PADRVGNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003c00U) >> 10) +#define TX_FORCED_GAIN__FORCED_PADRVGNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00003c00U) +#define TX_FORCED_GAIN__FORCED_PADRVGNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00003c00U) +#define TX_FORCED_GAIN__FORCED_PADRVGNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00003c00U))) + +/* macros for field forced_padrvgnB */ +#define TX_FORCED_GAIN__FORCED_PADRVGNB__SHIFT 14 +#define TX_FORCED_GAIN__FORCED_PADRVGNB__WIDTH 4 +#define TX_FORCED_GAIN__FORCED_PADRVGNB__MASK 0x0003c000U +#define TX_FORCED_GAIN__FORCED_PADRVGNB__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003c000U) >> 14) +#define TX_FORCED_GAIN__FORCED_PADRVGNB__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0003c000U) +#define TX_FORCED_GAIN__FORCED_PADRVGNB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0003c000U) +#define TX_FORCED_GAIN__FORCED_PADRVGNB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0003c000U))) + +/* macros for field forced_padrvgnC */ +#define TX_FORCED_GAIN__FORCED_PADRVGNC__SHIFT 18 +#define TX_FORCED_GAIN__FORCED_PADRVGNC__WIDTH 4 +#define TX_FORCED_GAIN__FORCED_PADRVGNC__MASK 0x003c0000U +#define TX_FORCED_GAIN__FORCED_PADRVGNC__READ(src) \ + (((u_int32_t)(src)\ + & 0x003c0000U) >> 18) +#define TX_FORCED_GAIN__FORCED_PADRVGNC__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x003c0000U) +#define TX_FORCED_GAIN__FORCED_PADRVGNC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x003c0000U) +#define TX_FORCED_GAIN__FORCED_PADRVGNC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x003c0000U))) + +/* macros for field forced_padrvgnD */ +#define TX_FORCED_GAIN__FORCED_PADRVGND__SHIFT 22 +#define TX_FORCED_GAIN__FORCED_PADRVGND__WIDTH 2 +#define TX_FORCED_GAIN__FORCED_PADRVGND__MASK 0x00c00000U +#define TX_FORCED_GAIN__FORCED_PADRVGND__READ(src) \ + (((u_int32_t)(src)\ + & 0x00c00000U) >> 22) +#define TX_FORCED_GAIN__FORCED_PADRVGND__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00c00000U) +#define TX_FORCED_GAIN__FORCED_PADRVGND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x00c00000U) +#define TX_FORCED_GAIN__FORCED_PADRVGND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00c00000U))) + +/* macros for field forced_enable_PAL */ +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__SHIFT 24 +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__WIDTH 1 +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__MASK 0x01000000U +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field forced_ob */ +#define TX_FORCED_GAIN__FORCED_OB__SHIFT 25 +#define TX_FORCED_GAIN__FORCED_OB__WIDTH 3 +#define TX_FORCED_GAIN__FORCED_OB__MASK 0x0e000000U +#define TX_FORCED_GAIN__FORCED_OB__READ(src) \ + (((u_int32_t)(src)\ + & 0x0e000000U) >> 25) +#define TX_FORCED_GAIN__FORCED_OB__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x0e000000U) +#define TX_FORCED_GAIN__FORCED_OB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x0e000000U) +#define TX_FORCED_GAIN__FORCED_OB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x0e000000U))) + +/* macros for field forced_db */ +#define TX_FORCED_GAIN__FORCED_DB__SHIFT 28 +#define TX_FORCED_GAIN__FORCED_DB__WIDTH 3 +#define TX_FORCED_GAIN__FORCED_DB__MASK 0x70000000U +#define TX_FORCED_GAIN__FORCED_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x70000000U) >> 28) +#define TX_FORCED_GAIN__FORCED_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x70000000U) +#define TX_FORCED_GAIN__FORCED_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x70000000U) | (((u_int32_t)(src) <<\ + 28) & 0x70000000U) +#define TX_FORCED_GAIN__FORCED_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x70000000U))) + +/* macros for field forced_green_paprd_enable */ +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__SHIFT 31 +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__WIDTH 1 +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MASK 0x80000000U +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TX_FORCED_GAIN__TYPE u_int32_t +#define TX_FORCED_GAIN__READ 0xffffffffU +#define TX_FORCED_GAIN__WRITE 0xffffffffU + +#endif /* __TX_FORCED_GAIN_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_forced_gain */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_FORCED_GAIN__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pdadc_tab */ +#ifndef __PDADC_TAB_MACRO__ +#define __PDADC_TAB_MACRO__ + +/* macros for field tab_entry */ +#define PDADC_TAB__TAB_ENTRY__SHIFT 0 +#define PDADC_TAB__TAB_ENTRY__WIDTH 32 +#define PDADC_TAB__TAB_ENTRY__MASK 0xffffffffU +#define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define PDADC_TAB__TYPE u_int32_t +#define PDADC_TAB__WRITE 0x00000000U + +#endif /* __PDADC_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_pdadc_tab_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PDADC_TAB_B0__NUM 32 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_1 */ +#ifndef __TX_GAIN_TAB_1_MACRO__ +#define __TX_GAIN_TAB_1_MACRO__ + +/* macros for field tg_table1 */ +#define TX_GAIN_TAB_1__TG_TABLE1__SHIFT 0 +#define TX_GAIN_TAB_1__TG_TABLE1__WIDTH 32 +#define TX_GAIN_TAB_1__TG_TABLE1__MASK 0xffffffffU +#define TX_GAIN_TAB_1__TG_TABLE1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_1__TG_TABLE1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_1__TG_TABLE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_1__TG_TABLE1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_1__TYPE u_int32_t +#define TX_GAIN_TAB_1__READ 0xffffffffU +#define TX_GAIN_TAB_1__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_2 */ +#ifndef __TX_GAIN_TAB_2_MACRO__ +#define __TX_GAIN_TAB_2_MACRO__ + +/* macros for field tg_table2 */ +#define TX_GAIN_TAB_2__TG_TABLE2__SHIFT 0 +#define TX_GAIN_TAB_2__TG_TABLE2__WIDTH 32 +#define TX_GAIN_TAB_2__TG_TABLE2__MASK 0xffffffffU +#define TX_GAIN_TAB_2__TG_TABLE2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_2__TG_TABLE2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_2__TG_TABLE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_2__TG_TABLE2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_2__TYPE u_int32_t +#define TX_GAIN_TAB_2__READ 0xffffffffU +#define TX_GAIN_TAB_2__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_3 */ +#ifndef __TX_GAIN_TAB_3_MACRO__ +#define __TX_GAIN_TAB_3_MACRO__ + +/* macros for field tg_table3 */ +#define TX_GAIN_TAB_3__TG_TABLE3__SHIFT 0 +#define TX_GAIN_TAB_3__TG_TABLE3__WIDTH 32 +#define TX_GAIN_TAB_3__TG_TABLE3__MASK 0xffffffffU +#define TX_GAIN_TAB_3__TG_TABLE3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_3__TG_TABLE3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_3__TG_TABLE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_3__TG_TABLE3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_3__TYPE u_int32_t +#define TX_GAIN_TAB_3__READ 0xffffffffU +#define TX_GAIN_TAB_3__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_3 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_4 */ +#ifndef __TX_GAIN_TAB_4_MACRO__ +#define __TX_GAIN_TAB_4_MACRO__ + +/* macros for field tg_table4 */ +#define TX_GAIN_TAB_4__TG_TABLE4__SHIFT 0 +#define TX_GAIN_TAB_4__TG_TABLE4__WIDTH 32 +#define TX_GAIN_TAB_4__TG_TABLE4__MASK 0xffffffffU +#define TX_GAIN_TAB_4__TG_TABLE4__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_4__TG_TABLE4__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_4__TG_TABLE4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_4__TG_TABLE4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_4__TYPE u_int32_t +#define TX_GAIN_TAB_4__READ 0xffffffffU +#define TX_GAIN_TAB_4__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_4_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_4 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_5 */ +#ifndef __TX_GAIN_TAB_5_MACRO__ +#define __TX_GAIN_TAB_5_MACRO__ + +/* macros for field tg_table5 */ +#define TX_GAIN_TAB_5__TG_TABLE5__SHIFT 0 +#define TX_GAIN_TAB_5__TG_TABLE5__WIDTH 32 +#define TX_GAIN_TAB_5__TG_TABLE5__MASK 0xffffffffU +#define TX_GAIN_TAB_5__TG_TABLE5__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_5__TG_TABLE5__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_5__TG_TABLE5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_5__TG_TABLE5__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_5__TYPE u_int32_t +#define TX_GAIN_TAB_5__READ 0xffffffffU +#define TX_GAIN_TAB_5__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_5_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_5 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_6 */ +#ifndef __TX_GAIN_TAB_6_MACRO__ +#define __TX_GAIN_TAB_6_MACRO__ + +/* macros for field tg_table6 */ +#define TX_GAIN_TAB_6__TG_TABLE6__SHIFT 0 +#define TX_GAIN_TAB_6__TG_TABLE6__WIDTH 32 +#define TX_GAIN_TAB_6__TG_TABLE6__MASK 0xffffffffU +#define TX_GAIN_TAB_6__TG_TABLE6__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_6__TG_TABLE6__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_6__TG_TABLE6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_6__TG_TABLE6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_6__TYPE u_int32_t +#define TX_GAIN_TAB_6__READ 0xffffffffU +#define TX_GAIN_TAB_6__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_6_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_6 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_7 */ +#ifndef __TX_GAIN_TAB_7_MACRO__ +#define __TX_GAIN_TAB_7_MACRO__ + +/* macros for field tg_table7 */ +#define TX_GAIN_TAB_7__TG_TABLE7__SHIFT 0 +#define TX_GAIN_TAB_7__TG_TABLE7__WIDTH 32 +#define TX_GAIN_TAB_7__TG_TABLE7__MASK 0xffffffffU +#define TX_GAIN_TAB_7__TG_TABLE7__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_7__TG_TABLE7__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_7__TG_TABLE7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_7__TG_TABLE7__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_7__TYPE u_int32_t +#define TX_GAIN_TAB_7__READ 0xffffffffU +#define TX_GAIN_TAB_7__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_7_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_7 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_8 */ +#ifndef __TX_GAIN_TAB_8_MACRO__ +#define __TX_GAIN_TAB_8_MACRO__ + +/* macros for field tg_table8 */ +#define TX_GAIN_TAB_8__TG_TABLE8__SHIFT 0 +#define TX_GAIN_TAB_8__TG_TABLE8__WIDTH 32 +#define TX_GAIN_TAB_8__TG_TABLE8__MASK 0xffffffffU +#define TX_GAIN_TAB_8__TG_TABLE8__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_8__TG_TABLE8__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_8__TG_TABLE8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_8__TG_TABLE8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_8__TYPE u_int32_t +#define TX_GAIN_TAB_8__READ 0xffffffffU +#define TX_GAIN_TAB_8__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_8_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_8 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_9 */ +#ifndef __TX_GAIN_TAB_9_MACRO__ +#define __TX_GAIN_TAB_9_MACRO__ + +/* macros for field tg_table9 */ +#define TX_GAIN_TAB_9__TG_TABLE9__SHIFT 0 +#define TX_GAIN_TAB_9__TG_TABLE9__WIDTH 32 +#define TX_GAIN_TAB_9__TG_TABLE9__MASK 0xffffffffU +#define TX_GAIN_TAB_9__TG_TABLE9__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_9__TG_TABLE9__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_9__TG_TABLE9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_9__TG_TABLE9__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_9__TYPE u_int32_t +#define TX_GAIN_TAB_9__READ 0xffffffffU +#define TX_GAIN_TAB_9__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_9_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_9 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_10 */ +#ifndef __TX_GAIN_TAB_10_MACRO__ +#define __TX_GAIN_TAB_10_MACRO__ + +/* macros for field tg_table10 */ +#define TX_GAIN_TAB_10__TG_TABLE10__SHIFT 0 +#define TX_GAIN_TAB_10__TG_TABLE10__WIDTH 32 +#define TX_GAIN_TAB_10__TG_TABLE10__MASK 0xffffffffU +#define TX_GAIN_TAB_10__TG_TABLE10__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_10__TG_TABLE10__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_10__TG_TABLE10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_10__TG_TABLE10__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_10__TYPE u_int32_t +#define TX_GAIN_TAB_10__READ 0xffffffffU +#define TX_GAIN_TAB_10__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_10_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_10 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_11 */ +#ifndef __TX_GAIN_TAB_11_MACRO__ +#define __TX_GAIN_TAB_11_MACRO__ + +/* macros for field tg_table11 */ +#define TX_GAIN_TAB_11__TG_TABLE11__SHIFT 0 +#define TX_GAIN_TAB_11__TG_TABLE11__WIDTH 32 +#define TX_GAIN_TAB_11__TG_TABLE11__MASK 0xffffffffU +#define TX_GAIN_TAB_11__TG_TABLE11__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_11__TG_TABLE11__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_11__TG_TABLE11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_11__TG_TABLE11__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_11__TYPE u_int32_t +#define TX_GAIN_TAB_11__READ 0xffffffffU +#define TX_GAIN_TAB_11__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_11_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_11 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_12 */ +#ifndef __TX_GAIN_TAB_12_MACRO__ +#define __TX_GAIN_TAB_12_MACRO__ + +/* macros for field tg_table12 */ +#define TX_GAIN_TAB_12__TG_TABLE12__SHIFT 0 +#define TX_GAIN_TAB_12__TG_TABLE12__WIDTH 32 +#define TX_GAIN_TAB_12__TG_TABLE12__MASK 0xffffffffU +#define TX_GAIN_TAB_12__TG_TABLE12__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_12__TG_TABLE12__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_12__TG_TABLE12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_12__TG_TABLE12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_12__TYPE u_int32_t +#define TX_GAIN_TAB_12__READ 0xffffffffU +#define TX_GAIN_TAB_12__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_12_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_12 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_13 */ +#ifndef __TX_GAIN_TAB_13_MACRO__ +#define __TX_GAIN_TAB_13_MACRO__ + +/* macros for field tg_table13 */ +#define TX_GAIN_TAB_13__TG_TABLE13__SHIFT 0 +#define TX_GAIN_TAB_13__TG_TABLE13__WIDTH 32 +#define TX_GAIN_TAB_13__TG_TABLE13__MASK 0xffffffffU +#define TX_GAIN_TAB_13__TG_TABLE13__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_13__TG_TABLE13__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_13__TG_TABLE13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_13__TG_TABLE13__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_13__TYPE u_int32_t +#define TX_GAIN_TAB_13__READ 0xffffffffU +#define TX_GAIN_TAB_13__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_13_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_13 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_13__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_14 */ +#ifndef __TX_GAIN_TAB_14_MACRO__ +#define __TX_GAIN_TAB_14_MACRO__ + +/* macros for field tg_table14 */ +#define TX_GAIN_TAB_14__TG_TABLE14__SHIFT 0 +#define TX_GAIN_TAB_14__TG_TABLE14__WIDTH 32 +#define TX_GAIN_TAB_14__TG_TABLE14__MASK 0xffffffffU +#define TX_GAIN_TAB_14__TG_TABLE14__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_14__TG_TABLE14__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_14__TG_TABLE14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_14__TG_TABLE14__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_14__TYPE u_int32_t +#define TX_GAIN_TAB_14__READ 0xffffffffU +#define TX_GAIN_TAB_14__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_14_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_14 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_14__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_15 */ +#ifndef __TX_GAIN_TAB_15_MACRO__ +#define __TX_GAIN_TAB_15_MACRO__ + +/* macros for field tg_table15 */ +#define TX_GAIN_TAB_15__TG_TABLE15__SHIFT 0 +#define TX_GAIN_TAB_15__TG_TABLE15__WIDTH 32 +#define TX_GAIN_TAB_15__TG_TABLE15__MASK 0xffffffffU +#define TX_GAIN_TAB_15__TG_TABLE15__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_15__TG_TABLE15__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_15__TG_TABLE15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_15__TG_TABLE15__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_15__TYPE u_int32_t +#define TX_GAIN_TAB_15__READ 0xffffffffU +#define TX_GAIN_TAB_15__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_15_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_15 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_15__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_16 */ +#ifndef __TX_GAIN_TAB_16_MACRO__ +#define __TX_GAIN_TAB_16_MACRO__ + +/* macros for field tg_table16 */ +#define TX_GAIN_TAB_16__TG_TABLE16__SHIFT 0 +#define TX_GAIN_TAB_16__TG_TABLE16__WIDTH 32 +#define TX_GAIN_TAB_16__TG_TABLE16__MASK 0xffffffffU +#define TX_GAIN_TAB_16__TG_TABLE16__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_16__TG_TABLE16__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_16__TG_TABLE16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_16__TG_TABLE16__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_16__TYPE u_int32_t +#define TX_GAIN_TAB_16__READ 0xffffffffU +#define TX_GAIN_TAB_16__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_16_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_16 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_17 */ +#ifndef __TX_GAIN_TAB_17_MACRO__ +#define __TX_GAIN_TAB_17_MACRO__ + +/* macros for field tg_table17 */ +#define TX_GAIN_TAB_17__TG_TABLE17__SHIFT 0 +#define TX_GAIN_TAB_17__TG_TABLE17__WIDTH 32 +#define TX_GAIN_TAB_17__TG_TABLE17__MASK 0xffffffffU +#define TX_GAIN_TAB_17__TG_TABLE17__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_17__TG_TABLE17__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_17__TG_TABLE17__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_17__TG_TABLE17__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_17__TYPE u_int32_t +#define TX_GAIN_TAB_17__READ 0xffffffffU +#define TX_GAIN_TAB_17__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_17_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_17 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_17__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_18 */ +#ifndef __TX_GAIN_TAB_18_MACRO__ +#define __TX_GAIN_TAB_18_MACRO__ + +/* macros for field tg_table18 */ +#define TX_GAIN_TAB_18__TG_TABLE18__SHIFT 0 +#define TX_GAIN_TAB_18__TG_TABLE18__WIDTH 32 +#define TX_GAIN_TAB_18__TG_TABLE18__MASK 0xffffffffU +#define TX_GAIN_TAB_18__TG_TABLE18__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_18__TG_TABLE18__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_18__TG_TABLE18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_18__TG_TABLE18__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_18__TYPE u_int32_t +#define TX_GAIN_TAB_18__READ 0xffffffffU +#define TX_GAIN_TAB_18__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_18_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_18 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_18__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_19 */ +#ifndef __TX_GAIN_TAB_19_MACRO__ +#define __TX_GAIN_TAB_19_MACRO__ + +/* macros for field tg_table19 */ +#define TX_GAIN_TAB_19__TG_TABLE19__SHIFT 0 +#define TX_GAIN_TAB_19__TG_TABLE19__WIDTH 32 +#define TX_GAIN_TAB_19__TG_TABLE19__MASK 0xffffffffU +#define TX_GAIN_TAB_19__TG_TABLE19__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_19__TG_TABLE19__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_19__TG_TABLE19__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_19__TG_TABLE19__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_19__TYPE u_int32_t +#define TX_GAIN_TAB_19__READ 0xffffffffU +#define TX_GAIN_TAB_19__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_19_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_19 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_19__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_20 */ +#ifndef __TX_GAIN_TAB_20_MACRO__ +#define __TX_GAIN_TAB_20_MACRO__ + +/* macros for field tg_table20 */ +#define TX_GAIN_TAB_20__TG_TABLE20__SHIFT 0 +#define TX_GAIN_TAB_20__TG_TABLE20__WIDTH 32 +#define TX_GAIN_TAB_20__TG_TABLE20__MASK 0xffffffffU +#define TX_GAIN_TAB_20__TG_TABLE20__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_20__TG_TABLE20__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_20__TG_TABLE20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_20__TG_TABLE20__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_20__TYPE u_int32_t +#define TX_GAIN_TAB_20__READ 0xffffffffU +#define TX_GAIN_TAB_20__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_20_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_20 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_21 */ +#ifndef __TX_GAIN_TAB_21_MACRO__ +#define __TX_GAIN_TAB_21_MACRO__ + +/* macros for field tg_table21 */ +#define TX_GAIN_TAB_21__TG_TABLE21__SHIFT 0 +#define TX_GAIN_TAB_21__TG_TABLE21__WIDTH 32 +#define TX_GAIN_TAB_21__TG_TABLE21__MASK 0xffffffffU +#define TX_GAIN_TAB_21__TG_TABLE21__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_21__TG_TABLE21__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_21__TG_TABLE21__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_21__TG_TABLE21__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_21__TYPE u_int32_t +#define TX_GAIN_TAB_21__READ 0xffffffffU +#define TX_GAIN_TAB_21__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_21_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_21 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_21__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_22 */ +#ifndef __TX_GAIN_TAB_22_MACRO__ +#define __TX_GAIN_TAB_22_MACRO__ + +/* macros for field tg_table22 */ +#define TX_GAIN_TAB_22__TG_TABLE22__SHIFT 0 +#define TX_GAIN_TAB_22__TG_TABLE22__WIDTH 32 +#define TX_GAIN_TAB_22__TG_TABLE22__MASK 0xffffffffU +#define TX_GAIN_TAB_22__TG_TABLE22__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_22__TG_TABLE22__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_22__TG_TABLE22__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_22__TG_TABLE22__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_22__TYPE u_int32_t +#define TX_GAIN_TAB_22__READ 0xffffffffU +#define TX_GAIN_TAB_22__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_22_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_22 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_22__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_23 */ +#ifndef __TX_GAIN_TAB_23_MACRO__ +#define __TX_GAIN_TAB_23_MACRO__ + +/* macros for field tg_table23 */ +#define TX_GAIN_TAB_23__TG_TABLE23__SHIFT 0 +#define TX_GAIN_TAB_23__TG_TABLE23__WIDTH 32 +#define TX_GAIN_TAB_23__TG_TABLE23__MASK 0xffffffffU +#define TX_GAIN_TAB_23__TG_TABLE23__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_23__TG_TABLE23__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_23__TG_TABLE23__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_23__TG_TABLE23__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_23__TYPE u_int32_t +#define TX_GAIN_TAB_23__READ 0xffffffffU +#define TX_GAIN_TAB_23__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_23_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_23 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_23__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_24 */ +#ifndef __TX_GAIN_TAB_24_MACRO__ +#define __TX_GAIN_TAB_24_MACRO__ + +/* macros for field tg_table24 */ +#define TX_GAIN_TAB_24__TG_TABLE24__SHIFT 0 +#define TX_GAIN_TAB_24__TG_TABLE24__WIDTH 32 +#define TX_GAIN_TAB_24__TG_TABLE24__MASK 0xffffffffU +#define TX_GAIN_TAB_24__TG_TABLE24__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_24__TG_TABLE24__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_24__TG_TABLE24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_24__TG_TABLE24__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_24__TYPE u_int32_t +#define TX_GAIN_TAB_24__READ 0xffffffffU +#define TX_GAIN_TAB_24__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_24_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_24 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_24__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_25 */ +#ifndef __TX_GAIN_TAB_25_MACRO__ +#define __TX_GAIN_TAB_25_MACRO__ + +/* macros for field tg_table25 */ +#define TX_GAIN_TAB_25__TG_TABLE25__SHIFT 0 +#define TX_GAIN_TAB_25__TG_TABLE25__WIDTH 32 +#define TX_GAIN_TAB_25__TG_TABLE25__MASK 0xffffffffU +#define TX_GAIN_TAB_25__TG_TABLE25__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_25__TG_TABLE25__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_25__TG_TABLE25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_25__TG_TABLE25__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_25__TYPE u_int32_t +#define TX_GAIN_TAB_25__READ 0xffffffffU +#define TX_GAIN_TAB_25__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_25_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_25 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_25__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_26 */ +#ifndef __TX_GAIN_TAB_26_MACRO__ +#define __TX_GAIN_TAB_26_MACRO__ + +/* macros for field tg_table26 */ +#define TX_GAIN_TAB_26__TG_TABLE26__SHIFT 0 +#define TX_GAIN_TAB_26__TG_TABLE26__WIDTH 32 +#define TX_GAIN_TAB_26__TG_TABLE26__MASK 0xffffffffU +#define TX_GAIN_TAB_26__TG_TABLE26__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_26__TG_TABLE26__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_26__TG_TABLE26__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_26__TG_TABLE26__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_26__TYPE u_int32_t +#define TX_GAIN_TAB_26__READ 0xffffffffU +#define TX_GAIN_TAB_26__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_26_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_26 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_26__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_27 */ +#ifndef __TX_GAIN_TAB_27_MACRO__ +#define __TX_GAIN_TAB_27_MACRO__ + +/* macros for field tg_table27 */ +#define TX_GAIN_TAB_27__TG_TABLE27__SHIFT 0 +#define TX_GAIN_TAB_27__TG_TABLE27__WIDTH 32 +#define TX_GAIN_TAB_27__TG_TABLE27__MASK 0xffffffffU +#define TX_GAIN_TAB_27__TG_TABLE27__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_27__TG_TABLE27__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_27__TG_TABLE27__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_27__TG_TABLE27__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_27__TYPE u_int32_t +#define TX_GAIN_TAB_27__READ 0xffffffffU +#define TX_GAIN_TAB_27__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_27_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_27 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_27__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_28 */ +#ifndef __TX_GAIN_TAB_28_MACRO__ +#define __TX_GAIN_TAB_28_MACRO__ + +/* macros for field tg_table28 */ +#define TX_GAIN_TAB_28__TG_TABLE28__SHIFT 0 +#define TX_GAIN_TAB_28__TG_TABLE28__WIDTH 32 +#define TX_GAIN_TAB_28__TG_TABLE28__MASK 0xffffffffU +#define TX_GAIN_TAB_28__TG_TABLE28__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_28__TG_TABLE28__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_28__TG_TABLE28__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_28__TG_TABLE28__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_28__TYPE u_int32_t +#define TX_GAIN_TAB_28__READ 0xffffffffU +#define TX_GAIN_TAB_28__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_28_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_28 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_28__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_29 */ +#ifndef __TX_GAIN_TAB_29_MACRO__ +#define __TX_GAIN_TAB_29_MACRO__ + +/* macros for field tg_table29 */ +#define TX_GAIN_TAB_29__TG_TABLE29__SHIFT 0 +#define TX_GAIN_TAB_29__TG_TABLE29__WIDTH 32 +#define TX_GAIN_TAB_29__TG_TABLE29__MASK 0xffffffffU +#define TX_GAIN_TAB_29__TG_TABLE29__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_29__TG_TABLE29__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_29__TG_TABLE29__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_29__TG_TABLE29__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_29__TYPE u_int32_t +#define TX_GAIN_TAB_29__READ 0xffffffffU +#define TX_GAIN_TAB_29__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_29_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_29 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_29__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_30 */ +#ifndef __TX_GAIN_TAB_30_MACRO__ +#define __TX_GAIN_TAB_30_MACRO__ + +/* macros for field tg_table30 */ +#define TX_GAIN_TAB_30__TG_TABLE30__SHIFT 0 +#define TX_GAIN_TAB_30__TG_TABLE30__WIDTH 32 +#define TX_GAIN_TAB_30__TG_TABLE30__MASK 0xffffffffU +#define TX_GAIN_TAB_30__TG_TABLE30__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_30__TG_TABLE30__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_30__TG_TABLE30__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_30__TG_TABLE30__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_30__TYPE u_int32_t +#define TX_GAIN_TAB_30__READ 0xffffffffU +#define TX_GAIN_TAB_30__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_30_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_30 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_30__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_31 */ +#ifndef __TX_GAIN_TAB_31_MACRO__ +#define __TX_GAIN_TAB_31_MACRO__ + +/* macros for field tg_table31 */ +#define TX_GAIN_TAB_31__TG_TABLE31__SHIFT 0 +#define TX_GAIN_TAB_31__TG_TABLE31__WIDTH 32 +#define TX_GAIN_TAB_31__TG_TABLE31__MASK 0xffffffffU +#define TX_GAIN_TAB_31__TG_TABLE31__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_31__TG_TABLE31__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_31__TG_TABLE31__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_31__TG_TABLE31__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_31__TYPE u_int32_t +#define TX_GAIN_TAB_31__READ 0xffffffffU +#define TX_GAIN_TAB_31__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_31_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_31 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_31__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_gain_tab_32 */ +#ifndef __TX_GAIN_TAB_32_MACRO__ +#define __TX_GAIN_TAB_32_MACRO__ + +/* macros for field tg_table32 */ +#define TX_GAIN_TAB_32__TG_TABLE32__SHIFT 0 +#define TX_GAIN_TAB_32__TG_TABLE32__WIDTH 32 +#define TX_GAIN_TAB_32__TG_TABLE32__MASK 0xffffffffU +#define TX_GAIN_TAB_32__TG_TABLE32__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TX_GAIN_TAB_32__TG_TABLE32__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define TX_GAIN_TAB_32__TG_TABLE32__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TX_GAIN_TAB_32__TG_TABLE32__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TX_GAIN_TAB_32__TYPE u_int32_t +#define TX_GAIN_TAB_32__READ 0xffffffffU +#define TX_GAIN_TAB_32__WRITE 0xffffffffU + +#endif /* __TX_GAIN_TAB_32_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_32 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_32__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rtt_ctrl */ +#ifndef __RTT_CTRL_MACRO__ +#define __RTT_CTRL_MACRO__ + +/* macros for field ena_radio_retention */ +#define RTT_CTRL__ENA_RADIO_RETENTION__SHIFT 0 +#define RTT_CTRL__ENA_RADIO_RETENTION__WIDTH 1 +#define RTT_CTRL__ENA_RADIO_RETENTION__MASK 0x00000001U +#define RTT_CTRL__ENA_RADIO_RETENTION__READ(src) (u_int32_t)(src) & 0x00000001U +#define RTT_CTRL__ENA_RADIO_RETENTION__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RTT_CTRL__ENA_RADIO_RETENTION__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTT_CTRL__ENA_RADIO_RETENTION__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTT_CTRL__ENA_RADIO_RETENTION__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTT_CTRL__ENA_RADIO_RETENTION__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field restore_mask */ +#define RTT_CTRL__RESTORE_MASK__SHIFT 1 +#define RTT_CTRL__RESTORE_MASK__WIDTH 6 +#define RTT_CTRL__RESTORE_MASK__MASK 0x0000007eU +#define RTT_CTRL__RESTORE_MASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000007eU) >> 1) +#define RTT_CTRL__RESTORE_MASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000007eU) +#define RTT_CTRL__RESTORE_MASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000007eU) +#define RTT_CTRL__RESTORE_MASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000007eU))) + +/* macros for field force_radio_restore */ +#define RTT_CTRL__FORCE_RADIO_RESTORE__SHIFT 7 +#define RTT_CTRL__FORCE_RADIO_RESTORE__WIDTH 1 +#define RTT_CTRL__FORCE_RADIO_RESTORE__MASK 0x00000080U +#define RTT_CTRL__FORCE_RADIO_RESTORE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RTT_CTRL__FORCE_RADIO_RESTORE__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RTT_CTRL__FORCE_RADIO_RESTORE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RTT_CTRL__FORCE_RADIO_RESTORE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RTT_CTRL__FORCE_RADIO_RESTORE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RTT_CTRL__FORCE_RADIO_RESTORE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) +#define RTT_CTRL__TYPE u_int32_t +#define RTT_CTRL__READ 0x000000ffU +#define RTT_CTRL__WRITE 0x000000ffU + +#endif /* __RTT_CTRL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_rtt_ctrl */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RTT_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_b0 */ +#ifndef __RTT_TABLE_SW_INTF_B0_MACRO__ +#define __RTT_TABLE_SW_INTF_B0_MACRO__ + +/* macros for field sw_rtt_table_access_0 */ +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__SHIFT 0 +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__WIDTH 1 +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__MASK 0x00000001U +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field sw_rtt_table_write_0 */ +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__SHIFT 1 +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__WIDTH 1 +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__MASK 0x00000002U +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field sw_rtt_table_addr_0 */ +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__SHIFT 2 +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__WIDTH 3 +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__MASK 0x0000001cU +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) +#define RTT_TABLE_SW_INTF_B0__TYPE u_int32_t +#define RTT_TABLE_SW_INTF_B0__READ 0x0000001fU +#define RTT_TABLE_SW_INTF_B0__WRITE 0x0000001fU + +#endif /* __RTT_TABLE_SW_INTF_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_rtt_table_sw_intf_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RTT_TABLE_SW_INTF_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_1_b0 */ +#ifndef __RTT_TABLE_SW_INTF_1_B0_MACRO__ +#define __RTT_TABLE_SW_INTF_1_B0_MACRO__ + +/* macros for field sw_rtt_table_data_0 */ +#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__SHIFT 4 +#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__WIDTH 28 +#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__MASK 0xfffffff0U +#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__READ(src) \ + (((u_int32_t)(src)\ + & 0xfffffff0U) >> 4) +#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0xfffffff0U) +#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffffff0U) | (((u_int32_t)(src) <<\ + 4) & 0xfffffff0U) +#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0xfffffff0U))) +#define RTT_TABLE_SW_INTF_1_B0__TYPE u_int32_t +#define RTT_TABLE_SW_INTF_1_B0__READ 0xfffffff0U +#define RTT_TABLE_SW_INTF_1_B0__WRITE 0xfffffff0U + +#endif /* __RTT_TABLE_SW_INTF_1_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_rtt_table_sw_intf_1_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RTT_TABLE_SW_INTF_1_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_0 */ +#ifndef __CALTX_GAIN_SET_0_MACRO__ +#define __CALTX_GAIN_SET_0_MACRO__ + +/* macros for field caltx_gain_set_0 */ +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__SHIFT 0 +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__WIDTH 14 +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__MASK 0x00003fffU +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_1 */ +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__SHIFT 14 +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__WIDTH 14 +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__MASK 0x0fffc000U +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_0__TYPE u_int32_t +#define CALTX_GAIN_SET_0__READ 0x0fffffffU +#define CALTX_GAIN_SET_0__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_2 */ +#ifndef __CALTX_GAIN_SET_2_MACRO__ +#define __CALTX_GAIN_SET_2_MACRO__ + +/* macros for field caltx_gain_set_2 */ +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__SHIFT 0 +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__WIDTH 14 +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__MASK 0x00003fffU +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_3 */ +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__SHIFT 14 +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__WIDTH 14 +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__MASK 0x0fffc000U +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_2__TYPE u_int32_t +#define CALTX_GAIN_SET_2__READ 0x0fffffffU +#define CALTX_GAIN_SET_2__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_4 */ +#ifndef __CALTX_GAIN_SET_4_MACRO__ +#define __CALTX_GAIN_SET_4_MACRO__ + +/* macros for field caltx_gain_set_4 */ +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__SHIFT 0 +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__WIDTH 14 +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__MASK 0x00003fffU +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_5 */ +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__SHIFT 14 +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__WIDTH 14 +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__MASK 0x0fffc000U +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_4__TYPE u_int32_t +#define CALTX_GAIN_SET_4__READ 0x0fffffffU +#define CALTX_GAIN_SET_4__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_4_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_4 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_6 */ +#ifndef __CALTX_GAIN_SET_6_MACRO__ +#define __CALTX_GAIN_SET_6_MACRO__ + +/* macros for field caltx_gain_set_6 */ +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__SHIFT 0 +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__WIDTH 14 +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__MASK 0x00003fffU +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_7 */ +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__SHIFT 14 +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__WIDTH 14 +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__MASK 0x0fffc000U +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_6__TYPE u_int32_t +#define CALTX_GAIN_SET_6__READ 0x0fffffffU +#define CALTX_GAIN_SET_6__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_6_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_6 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_8 */ +#ifndef __CALTX_GAIN_SET_8_MACRO__ +#define __CALTX_GAIN_SET_8_MACRO__ + +/* macros for field caltx_gain_set_8 */ +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__SHIFT 0 +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__WIDTH 14 +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__MASK 0x00003fffU +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_9 */ +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__SHIFT 14 +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__WIDTH 14 +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__MASK 0x0fffc000U +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_8__TYPE u_int32_t +#define CALTX_GAIN_SET_8__READ 0x0fffffffU +#define CALTX_GAIN_SET_8__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_8_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_8 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_10 */ +#ifndef __CALTX_GAIN_SET_10_MACRO__ +#define __CALTX_GAIN_SET_10_MACRO__ + +/* macros for field caltx_gain_set_10 */ +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__SHIFT 0 +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__WIDTH 14 +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__MASK 0x00003fffU +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_11 */ +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__SHIFT 14 +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__WIDTH 14 +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__MASK 0x0fffc000U +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_10__TYPE u_int32_t +#define CALTX_GAIN_SET_10__READ 0x0fffffffU +#define CALTX_GAIN_SET_10__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_10_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_10 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_12 */ +#ifndef __CALTX_GAIN_SET_12_MACRO__ +#define __CALTX_GAIN_SET_12_MACRO__ + +/* macros for field caltx_gain_set_12 */ +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__SHIFT 0 +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__WIDTH 14 +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__MASK 0x00003fffU +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_13 */ +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__SHIFT 14 +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__WIDTH 14 +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__MASK 0x0fffc000U +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_12__TYPE u_int32_t +#define CALTX_GAIN_SET_12__READ 0x0fffffffU +#define CALTX_GAIN_SET_12__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_12_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_12 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_14 */ +#ifndef __CALTX_GAIN_SET_14_MACRO__ +#define __CALTX_GAIN_SET_14_MACRO__ + +/* macros for field caltx_gain_set_14 */ +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__SHIFT 0 +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__WIDTH 14 +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__MASK 0x00003fffU +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_15 */ +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__SHIFT 14 +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__WIDTH 14 +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__MASK 0x0fffc000U +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_14__TYPE u_int32_t +#define CALTX_GAIN_SET_14__READ 0x0fffffffU +#define CALTX_GAIN_SET_14__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_14_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_14 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_14__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_16 */ +#ifndef __CALTX_GAIN_SET_16_MACRO__ +#define __CALTX_GAIN_SET_16_MACRO__ + +/* macros for field caltx_gain_set_16 */ +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__SHIFT 0 +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__WIDTH 14 +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__MASK 0x00003fffU +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_17 */ +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__SHIFT 14 +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__WIDTH 14 +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__MASK 0x0fffc000U +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_16__TYPE u_int32_t +#define CALTX_GAIN_SET_16__READ 0x0fffffffU +#define CALTX_GAIN_SET_16__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_16_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_16 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_18 */ +#ifndef __CALTX_GAIN_SET_18_MACRO__ +#define __CALTX_GAIN_SET_18_MACRO__ + +/* macros for field caltx_gain_set_18 */ +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__SHIFT 0 +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__WIDTH 14 +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__MASK 0x00003fffU +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_19 */ +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__SHIFT 14 +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__WIDTH 14 +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__MASK 0x0fffc000U +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_18__TYPE u_int32_t +#define CALTX_GAIN_SET_18__READ 0x0fffffffU +#define CALTX_GAIN_SET_18__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_18_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_18 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_18__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_20 */ +#ifndef __CALTX_GAIN_SET_20_MACRO__ +#define __CALTX_GAIN_SET_20_MACRO__ + +/* macros for field caltx_gain_set_20 */ +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__SHIFT 0 +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__WIDTH 14 +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__MASK 0x00003fffU +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_21 */ +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__SHIFT 14 +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__WIDTH 14 +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__MASK 0x0fffc000U +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_20__TYPE u_int32_t +#define CALTX_GAIN_SET_20__READ 0x0fffffffU +#define CALTX_GAIN_SET_20__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_20_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_20 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_22 */ +#ifndef __CALTX_GAIN_SET_22_MACRO__ +#define __CALTX_GAIN_SET_22_MACRO__ + +/* macros for field caltx_gain_set_22 */ +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__SHIFT 0 +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__WIDTH 14 +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__MASK 0x00003fffU +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_23 */ +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__SHIFT 14 +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__WIDTH 14 +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__MASK 0x0fffc000U +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_22__TYPE u_int32_t +#define CALTX_GAIN_SET_22__READ 0x0fffffffU +#define CALTX_GAIN_SET_22__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_22_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_22 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_22__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_24 */ +#ifndef __CALTX_GAIN_SET_24_MACRO__ +#define __CALTX_GAIN_SET_24_MACRO__ + +/* macros for field caltx_gain_set_24 */ +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__SHIFT 0 +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__WIDTH 14 +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__MASK 0x00003fffU +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_25 */ +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__SHIFT 14 +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__WIDTH 14 +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__MASK 0x0fffc000U +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_24__TYPE u_int32_t +#define CALTX_GAIN_SET_24__READ 0x0fffffffU +#define CALTX_GAIN_SET_24__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_24_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_24 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_24__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_26 */ +#ifndef __CALTX_GAIN_SET_26_MACRO__ +#define __CALTX_GAIN_SET_26_MACRO__ + +/* macros for field caltx_gain_set_26 */ +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__SHIFT 0 +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__WIDTH 14 +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__MASK 0x00003fffU +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_27 */ +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__SHIFT 14 +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__WIDTH 14 +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__MASK 0x0fffc000U +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_26__TYPE u_int32_t +#define CALTX_GAIN_SET_26__READ 0x0fffffffU +#define CALTX_GAIN_SET_26__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_26_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_26 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_26__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_28 */ +#ifndef __CALTX_GAIN_SET_28_MACRO__ +#define __CALTX_GAIN_SET_28_MACRO__ + +/* macros for field caltx_gain_set_28 */ +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__SHIFT 0 +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__WIDTH 14 +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__MASK 0x00003fffU +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_29 */ +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__SHIFT 14 +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__WIDTH 14 +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__MASK 0x0fffc000U +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_28__TYPE u_int32_t +#define CALTX_GAIN_SET_28__READ 0x0fffffffU +#define CALTX_GAIN_SET_28__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_28_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_28 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_28__NUM 1 + +/* macros for BlueprintGlobalNameSpace::caltx_gain_set_30 */ +#ifndef __CALTX_GAIN_SET_30_MACRO__ +#define __CALTX_GAIN_SET_30_MACRO__ + +/* macros for field caltx_gain_set_30 */ +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__SHIFT 0 +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__WIDTH 14 +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__MASK 0x00003fffU +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field caltx_gain_set_31 */ +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__SHIFT 14 +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__WIDTH 14 +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__MASK 0x0fffc000U +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define CALTX_GAIN_SET_30__TYPE u_int32_t +#define CALTX_GAIN_SET_30__READ 0x0fffffffU +#define CALTX_GAIN_SET_30__WRITE 0x0fffffffU + +#endif /* __CALTX_GAIN_SET_30_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_30 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_30__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_control_0 */ +#ifndef __TXIQCAL_CONTROL_0_MACRO__ +#define __TXIQCAL_CONTROL_0_MACRO__ + +/* macros for field iqc_tx_table_sel */ +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__SHIFT 0 +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__WIDTH 1 +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__MASK 0x00000001U +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field base_tx_tone_db */ +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__SHIFT 1 +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__WIDTH 6 +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__MASK 0x0000007eU +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000007eU) >> 1) +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000007eU) +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000007eU) +#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000007eU))) + +/* macros for field max_tx_tone_gain */ +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__SHIFT 7 +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__WIDTH 6 +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__MASK 0x00001f80U +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f80U) >> 7) +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00001f80U) +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00001f80U) +#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00001f80U))) + +/* macros for field min_tx_tone_gain */ +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__SHIFT 13 +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__WIDTH 6 +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__MASK 0x0007e000U +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0007e000U) >> 13) +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0007e000U) +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0007e000U) +#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0007e000U))) + +/* macros for field caltxshift_delay */ +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__SHIFT 19 +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__WIDTH 4 +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__MASK 0x00780000U +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x00780000U) >> 19) +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00780000U) +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00780000U) | (((u_int32_t)(src) <<\ + 19) & 0x00780000U) +#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00780000U))) + +/* macros for field loopback_delay */ +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__SHIFT 23 +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__WIDTH 7 +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__MASK 0x3f800000U +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f800000U) >> 23) +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x3f800000U) +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x3f800000U) +#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x3f800000U))) + +/* macros for field enable_combined_carr_iq_cal */ +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__SHIFT 30 +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__WIDTH 1 +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__MASK 0x40000000U +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field enable_txiq_calibrate */ +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SHIFT 31 +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WIDTH 1 +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MASK 0x80000000U +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TXIQCAL_CONTROL_0__TYPE u_int32_t +#define TXIQCAL_CONTROL_0__READ 0xffffffffU +#define TXIQCAL_CONTROL_0__WRITE 0xffffffffU + +#endif /* __TXIQCAL_CONTROL_0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_control_0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_control_1 */ +#ifndef __TXIQCAL_CONTROL_1_MACRO__ +#define __TXIQCAL_CONTROL_1_MACRO__ + +/* macros for field rx_init_gain_db */ +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__SHIFT 0 +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__WIDTH 6 +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__MASK 0x0000003fU +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field max_rx_gain_db */ +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__SHIFT 6 +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__WIDTH 6 +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__MASK 0x00000fc0U +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field min_rx_gain_db */ +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__SHIFT 12 +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__WIDTH 6 +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__MASK 0x0003f000U +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field iqcorr_i_q_coff_delpt */ +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__SHIFT 18 +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__WIDTH 7 +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__MASK 0x01fc0000U +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fc0000U) >> 18) +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x01fc0000U) +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x01fc0000U) +#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x01fc0000U))) +#define TXIQCAL_CONTROL_1__TYPE u_int32_t +#define TXIQCAL_CONTROL_1__READ 0x01ffffffU +#define TXIQCAL_CONTROL_1__WRITE 0x01ffffffU + +#endif /* __TXIQCAL_CONTROL_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_control_1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_control_2 */ +#ifndef __TXIQCAL_CONTROL_2_MACRO__ +#define __TXIQCAL_CONTROL_2_MACRO__ + +/* macros for field iqc_forced_pagain */ +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__SHIFT 0 +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__WIDTH 4 +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__MASK 0x0000000fU +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field iqcal_min_tx_gain */ +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__SHIFT 4 +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__WIDTH 5 +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__MASK 0x000001f0U +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001f0U) >> 4) +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000001f0U) +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000001f0U) +#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000001f0U))) + +/* macros for field iqcal_max_tx_gain */ +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__SHIFT 9 +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__WIDTH 5 +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__MASK 0x00003e00U +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003e00U) >> 9) +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00003e00U) +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00003e00U) +#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00003e00U))) +#define TXIQCAL_CONTROL_2__TYPE u_int32_t +#define TXIQCAL_CONTROL_2__READ 0x00003fffU +#define TXIQCAL_CONTROL_2__WRITE 0x00003fffU + +#endif /* __TXIQCAL_CONTROL_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_control_2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b0 */ +#ifndef __TXIQ_CORR_COEFF_01_B0_MACRO__ +#define __TXIQ_CORR_COEFF_01_B0_MACRO__ + +/* macros for field iqc_coeff_table_0_0 */ +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__SHIFT 0 +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_1_0 */ +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__SHIFT 14 +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_01_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_01_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_01_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_01_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_01_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_01_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b0 */ +#ifndef __TXIQ_CORR_COEFF_23_B0_MACRO__ +#define __TXIQ_CORR_COEFF_23_B0_MACRO__ + +/* macros for field iqc_coeff_table_2_0 */ +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__SHIFT 0 +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_3_0 */ +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__SHIFT 14 +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_23_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_23_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_23_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_23_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_23_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_23_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b0 */ +#ifndef __TXIQ_CORR_COEFF_45_B0_MACRO__ +#define __TXIQ_CORR_COEFF_45_B0_MACRO__ + +/* macros for field iqc_coeff_table_4_0 */ +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__SHIFT 0 +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_5_0 */ +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__SHIFT 14 +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_45_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_45_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_45_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_45_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_45_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_45_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b0 */ +#ifndef __TXIQ_CORR_COEFF_67_B0_MACRO__ +#define __TXIQ_CORR_COEFF_67_B0_MACRO__ + +/* macros for field iqc_coeff_table_6_0 */ +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__SHIFT 0 +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_7_0 */ +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__SHIFT 14 +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_67_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_67_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_67_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_67_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_67_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_67_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b0 */ +#ifndef __TXIQ_CORR_COEFF_89_B0_MACRO__ +#define __TXIQ_CORR_COEFF_89_B0_MACRO__ + +/* macros for field iqc_coeff_table_8_0 */ +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__SHIFT 0 +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_9_0 */ +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__SHIFT 14 +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_89_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_89_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_89_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_89_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_89_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_89_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b0 */ +#ifndef __TXIQ_CORR_COEFF_AB_B0_MACRO__ +#define __TXIQ_CORR_COEFF_AB_B0_MACRO__ + +/* macros for field iqc_coeff_table_a_0 */ +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__SHIFT 0 +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_b_0 */ +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__SHIFT 14 +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_AB_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_AB_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_AB_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_AB_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_ab_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b0 */ +#ifndef __TXIQ_CORR_COEFF_CD_B0_MACRO__ +#define __TXIQ_CORR_COEFF_CD_B0_MACRO__ + +/* macros for field iqc_coeff_table_c_0 */ +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__SHIFT 0 +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_d_0 */ +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__SHIFT 14 +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_CD_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_CD_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_CD_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_CD_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_cd_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b0 */ +#ifndef __TXIQ_CORR_COEFF_EF_B0_MACRO__ +#define __TXIQ_CORR_COEFF_EF_B0_MACRO__ + +/* macros for field iqc_coeff_table_e_0 */ +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__SHIFT 0 +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_f_0 */ +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__SHIFT 14 +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_EF_B0__TYPE u_int32_t +#define TXIQ_CORR_COEFF_EF_B0__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_EF_B0__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_EF_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_ef_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_0 */ +#ifndef __CAL_RXBB_GAIN_TBL_0_MACRO__ +#define __CAL_RXBB_GAIN_TBL_0_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_0 */ +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_1 */ +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_2 */ +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_3 */ +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_0__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_0__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_0__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_4 */ +#ifndef __CAL_RXBB_GAIN_TBL_4_MACRO__ +#define __CAL_RXBB_GAIN_TBL_4_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_4 */ +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_5 */ +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_6 */ +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_7 */ +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_4__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_4__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_4__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_4_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_4 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_8 */ +#ifndef __CAL_RXBB_GAIN_TBL_8_MACRO__ +#define __CAL_RXBB_GAIN_TBL_8_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_8 */ +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_9 */ +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_10 */ +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_11 */ +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_8__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_8__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_8__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_8_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_8 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_12 */ +#ifndef __CAL_RXBB_GAIN_TBL_12_MACRO__ +#define __CAL_RXBB_GAIN_TBL_12_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_12 */ +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_13 */ +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_14 */ +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_15 */ +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_12__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_12__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_12__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_12_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_12 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_16 */ +#ifndef __CAL_RXBB_GAIN_TBL_16_MACRO__ +#define __CAL_RXBB_GAIN_TBL_16_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_16 */ +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_17 */ +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_18 */ +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_19 */ +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_16__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_16__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_16__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_16_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_16 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_16__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_20 */ +#ifndef __CAL_RXBB_GAIN_TBL_20_MACRO__ +#define __CAL_RXBB_GAIN_TBL_20_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_20 */ +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field txcal_rx_bb_gain_table_21 */ +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__SHIFT 8 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__MASK 0x0000ff00U +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field txcal_rx_bb_gain_table_22 */ +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__SHIFT 16 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__MASK 0x00ff0000U +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field txcal_rx_bb_gain_table_23 */ +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__SHIFT 24 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__MASK 0xff000000U +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define CAL_RXBB_GAIN_TBL_20__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_20__READ 0xffffffffU +#define CAL_RXBB_GAIN_TBL_20__WRITE 0xffffffffU + +#endif /* __CAL_RXBB_GAIN_TBL_20_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_20 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_20__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_24 */ +#ifndef __CAL_RXBB_GAIN_TBL_24_MACRO__ +#define __CAL_RXBB_GAIN_TBL_24_MACRO__ + +/* macros for field txcal_rx_bb_gain_table_24 */ +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__SHIFT 0 +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__WIDTH 8 +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__MASK 0x000000ffU +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) +#define CAL_RXBB_GAIN_TBL_24__TYPE u_int32_t +#define CAL_RXBB_GAIN_TBL_24__READ 0x000000ffU +#define CAL_RXBB_GAIN_TBL_24__WRITE 0x000000ffU + +#endif /* __CAL_RXBB_GAIN_TBL_24_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_24 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_24__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_status_b0 */ +#ifndef __TXIQCAL_STATUS_B0_MACRO__ +#define __TXIQCAL_STATUS_B0_MACRO__ + +/* macros for field txiqcal_failed_0 */ +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__SHIFT 0 +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__WIDTH 1 +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__MASK 0x00000001U +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field calibrated_gains_0 */ +#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__SHIFT 1 +#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__WIDTH 5 +#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__MASK 0x0000003eU +#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) + +/* macros for field tone_gain_used_0 */ +#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__SHIFT 6 +#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__WIDTH 6 +#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__MASK 0x00000fc0U +#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) + +/* macros for field rx_gain_used_0 */ +#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__SHIFT 12 +#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__WIDTH 6 +#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__MASK 0x0003f000U +#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) + +/* macros for field last_meas_addr_0 */ +#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__SHIFT 18 +#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__WIDTH 6 +#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__MASK 0x00fc0000U +#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TXIQCAL_STATUS_B0__TYPE u_int32_t +#define TXIQCAL_STATUS_B0__READ 0x00ffffffU + +#endif /* __TXIQCAL_STATUS_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_status_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_STATUS_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl1 */ +#ifndef __PAPRD_TRAINER_CNTL1_MACRO__ +#define __PAPRD_TRAINER_CNTL1_MACRO__ + +/* macros for field cf_paprd_train_enable */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__SHIFT 0 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__WIDTH 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__MASK 0x00000001U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_paprd_agc2_settling */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__SHIFT 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__WIDTH 7 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__MASK 0x000000feU +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000feU) >> 1) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000000feU) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((u_int32_t)(src) <<\ + 1) & 0x000000feU) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000000feU))) + +/* macros for field cf_paprd_iqcorr_enable */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__SHIFT 8 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__WIDTH 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__MASK 0x00000100U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field cf_paprd_rx_bb_gain_force */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__SHIFT 9 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__WIDTH 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__MASK 0x00000200U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field cf_paprd_tx_gain_force */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__SHIFT 10 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__WIDTH 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__MASK 0x00000400U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field cf_paprd_lb_enable */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__SHIFT 11 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__WIDTH 1 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__MASK 0x00000800U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field cf_paprd_lb_skip */ +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__SHIFT 12 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__WIDTH 7 +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__MASK 0x0007f000U +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__READ(src) \ + (((u_int32_t)(src)\ + & 0x0007f000U) >> 12) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0007f000U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0007f000U) +#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0007f000U))) +#define PAPRD_TRAINER_CNTL1__TYPE u_int32_t +#define PAPRD_TRAINER_CNTL1__READ 0x0007ffffU +#define PAPRD_TRAINER_CNTL1__WRITE 0x0007ffffU + +#endif /* __PAPRD_TRAINER_CNTL1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl2 */ +#ifndef __PAPRD_TRAINER_CNTL2_MACRO__ +#define __PAPRD_TRAINER_CNTL2_MACRO__ + +/* macros for field cf_paprd_init_rx_bb_gain */ +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__SHIFT 0 +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__WIDTH 32 +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__MASK 0xffffffffU +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define PAPRD_TRAINER_CNTL2__TYPE u_int32_t +#define PAPRD_TRAINER_CNTL2__READ 0xffffffffU +#define PAPRD_TRAINER_CNTL2__WRITE 0xffffffffU + +#endif /* __PAPRD_TRAINER_CNTL2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl3 */ +#ifndef __PAPRD_TRAINER_CNTL3_MACRO__ +#define __PAPRD_TRAINER_CNTL3_MACRO__ + +/* macros for field cf_paprd_adc_desired_size */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__SHIFT 0 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__WIDTH 6 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__MASK 0x0000003fU +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field cf_paprd_quick_drop */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__SHIFT 6 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__WIDTH 6 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__MASK 0x00000fc0U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field cf_paprd_min_loopback_del */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__SHIFT 12 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__WIDTH 5 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__MASK 0x0001f000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field cf_paprd_num_corr_stages */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__SHIFT 17 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__WIDTH 3 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__MASK 0x000e0000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field cf_paprd_coarse_corr_len */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__SHIFT 20 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__WIDTH 4 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__MASK 0x00f00000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) + +/* macros for field cf_paprd_fine_corr_len */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__SHIFT 24 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__WIDTH 4 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__MASK 0x0f000000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) + +/* macros for field cf_paprd_reuse_corr */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__SHIFT 28 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__WIDTH 1 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__MASK 0x10000000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field cf_paprd_bbtxmix_disable */ +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__SHIFT 29 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__WIDTH 1 +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__MASK 0x20000000U +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) +#define PAPRD_TRAINER_CNTL3__TYPE u_int32_t +#define PAPRD_TRAINER_CNTL3__READ 0x3fffffffU +#define PAPRD_TRAINER_CNTL3__WRITE 0x3fffffffU + +#endif /* __PAPRD_TRAINER_CNTL3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl3 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl4 */ +#ifndef __PAPRD_TRAINER_CNTL4_MACRO__ +#define __PAPRD_TRAINER_CNTL4_MACRO__ + +/* macros for field cf_paprd_min_corr */ +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__SHIFT 0 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__WIDTH 12 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__MASK 0x00000fffU +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__READ(src) \ + (u_int32_t)(src)\ + & 0x00000fffU +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000fffU) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fffU) | ((u_int32_t)(src) &\ + 0x00000fffU) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000fffU))) + +/* macros for field cf_paprd_safety_delta */ +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__SHIFT 12 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__WIDTH 4 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__MASK 0x0000f000U +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field cf_paprd_num_train_samples */ +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__SHIFT 16 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__WIDTH 10 +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__MASK 0x03ff0000U +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__READ(src) \ + (((u_int32_t)(src)\ + & 0x03ff0000U) >> 16) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x03ff0000U) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x03ff0000U) +#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define PAPRD_TRAINER_CNTL4__TYPE u_int32_t +#define PAPRD_TRAINER_CNTL4__READ 0x03ffffffU +#define PAPRD_TRAINER_CNTL4__WRITE 0x03ffffffU + +#endif /* __PAPRD_TRAINER_CNTL4_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl4 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat1 */ +#ifndef __PAPRD_TRAINER_STAT1_MACRO__ +#define __PAPRD_TRAINER_STAT1_MACRO__ + +/* macros for field paprd_train_done */ +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__SHIFT 0 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__WIDTH 1 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__MASK 0x00000001U +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_train_incomplete */ +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__SHIFT 1 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__WIDTH 1 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__MASK 0x00000002U +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_corr_err */ +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__SHIFT 2 +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__WIDTH 1 +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__MASK 0x00000004U +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field paprd_train_active */ +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__SHIFT 3 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__WIDTH 1 +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__MASK 0x00000008U +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field paprd_rx_gain_idx */ +#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__SHIFT 4 +#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__WIDTH 5 +#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__MASK 0x000001f0U +#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001f0U) >> 4) + +/* macros for field paprd_agc2_pwr */ +#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__SHIFT 9 +#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__WIDTH 8 +#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__MASK 0x0001fe00U +#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fe00U) >> 9) +#define PAPRD_TRAINER_STAT1__TYPE u_int32_t +#define PAPRD_TRAINER_STAT1__READ 0x0001ffffU +#define PAPRD_TRAINER_STAT1__WRITE 0x0001ffffU + +#endif /* __PAPRD_TRAINER_STAT1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_stat1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat2 */ +#ifndef __PAPRD_TRAINER_STAT2_MACRO__ +#define __PAPRD_TRAINER_STAT2_MACRO__ + +/* macros for field paprd_fine_val */ +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__SHIFT 0 +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__WIDTH 16 +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__MASK 0x0000ffffU +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__READ(src) \ + (u_int32_t)(src)\ + & 0x0000ffffU + +/* macros for field paprd_coarse_idx */ +#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__SHIFT 16 +#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__WIDTH 5 +#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__MASK 0x001f0000U +#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) + +/* macros for field paprd_fine_idx */ +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__SHIFT 21 +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__WIDTH 2 +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__MASK 0x00600000U +#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00600000U) >> 21) +#define PAPRD_TRAINER_STAT2__TYPE u_int32_t +#define PAPRD_TRAINER_STAT2__READ 0x007fffffU + +#endif /* __PAPRD_TRAINER_STAT2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_stat2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat3 */ +#ifndef __PAPRD_TRAINER_STAT3_MACRO__ +#define __PAPRD_TRAINER_STAT3_MACRO__ + +/* macros for field paprd_train_samples_cnt */ +#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__SHIFT 0 +#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__WIDTH 20 +#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__MASK 0x000fffffU +#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__READ(src) \ + (u_int32_t)(src)\ + & 0x000fffffU +#define PAPRD_TRAINER_STAT3__TYPE u_int32_t +#define PAPRD_TRAINER_STAT3__READ 0x000fffffU + +#endif /* __PAPRD_TRAINER_STAT3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_stat3 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::watchdog_status */ +#ifndef __WATCHDOG_STATUS_MACRO__ +#define __WATCHDOG_STATUS_MACRO__ + +/* macros for field watchdog_status_1 */ +#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__SHIFT 0 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__WIDTH 3 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__MASK 0x00000007U +#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000007U +#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000007U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field watchdog_timeout */ +#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__SHIFT 3 +#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__WIDTH 1 +#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__MASK 0x00000008U +#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field watchdog_status_2 */ +#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__SHIFT 4 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__WIDTH 4 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__MASK 0x000000f0U +#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field watchdog_status_3 */ +#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__SHIFT 8 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__WIDTH 4 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__MASK 0x00000f00U +#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field watchdog_status_4 */ +#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__SHIFT 12 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__WIDTH 4 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__MASK 0x0000f000U +#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field watchdog_status_5 */ +#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__SHIFT 16 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__WIDTH 4 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__MASK 0x000f0000U +#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field watchdog_status_6 */ +#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__SHIFT 20 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__WIDTH 4 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__MASK 0x00f00000U +#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) + +/* macros for field watchdog_status_7 */ +#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__SHIFT 24 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__WIDTH 4 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__MASK 0x0f000000U +#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__READ(src) \ + (((u_int32_t)(src)\ + & 0x0f000000U) >> 24) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x0f000000U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x0f000000U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x0f000000U))) + +/* macros for field watchdog_status_8 */ +#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__SHIFT 28 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__WIDTH 4 +#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__MASK 0xf0000000U +#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__READ(src) \ + (((u_int32_t)(src)\ + & 0xf0000000U) >> 28) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0xf0000000U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf0000000U) | (((u_int32_t)(src) <<\ + 28) & 0xf0000000U) +#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0xf0000000U))) +#define WATCHDOG_STATUS__TYPE u_int32_t +#define WATCHDOG_STATUS__READ 0xffffffffU +#define WATCHDOG_STATUS__WRITE 0xffffffffU + +#endif /* __WATCHDOG_STATUS_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_watchdog_status */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_WATCHDOG_STATUS__NUM 1 + +/* macros for BlueprintGlobalNameSpace::watchdog_ctrl_1 */ +#ifndef __WATCHDOG_CTRL_1_MACRO__ +#define __WATCHDOG_CTRL_1_MACRO__ + +/* macros for field enable_watchdog_timeout_reset_non_idle */ +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__SHIFT 0 +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__WIDTH 1 +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__MASK \ + 0x00000001U +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field enable_watchdog_timeout_reset_idle */ +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__SHIFT 1 +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__WIDTH 1 +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__MASK 0x00000002U +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field watchdog_timeout_reset_non_idle_limit */ +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__SHIFT 2 +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__WIDTH 14 +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__MASK \ + 0x0000fffcU +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fffcU) >> 2) +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000fffcU) +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0000fffcU) +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000fffcU))) + +/* macros for field watchdog_timeout_reset_idle_limit */ +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__SHIFT 16 +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__WIDTH 16 +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__MASK 0xffff0000U +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0xffff0000U) +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffff0000U) | (((u_int32_t)(src) <<\ + 16) & 0xffff0000U) +#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0xffff0000U))) +#define WATCHDOG_CTRL_1__TYPE u_int32_t +#define WATCHDOG_CTRL_1__READ 0xffffffffU +#define WATCHDOG_CTRL_1__WRITE 0xffffffffU + +#endif /* __WATCHDOG_CTRL_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_watchdog_ctrl_1 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_WATCHDOG_CTRL_1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::watchdog_ctrl_2 */ +#ifndef __WATCHDOG_CTRL_2_MACRO__ +#define __WATCHDOG_CTRL_2_MACRO__ + +/* macros for field force_fast_adc_clk */ +#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__SHIFT 0 +#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__WIDTH 1 +#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__MASK 0x00000001U +#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field watchdog_timeout_reset_ena */ +#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__SHIFT 1 +#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__WIDTH 1 +#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__MASK 0x00000002U +#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field watchdog_irq_ena */ +#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__SHIFT 2 +#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__WIDTH 1 +#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__MASK 0x00000004U +#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) +#define WATCHDOG_CTRL_2__TYPE u_int32_t +#define WATCHDOG_CTRL_2__READ 0x00000007U +#define WATCHDOG_CTRL_2__WRITE 0x00000007U + +#endif /* __WATCHDOG_CTRL_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_watchdog_ctrl_2 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_WATCHDOG_CTRL_2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::bluetooth_cntl */ +#ifndef __BLUETOOTH_CNTL_MACRO__ +#define __BLUETOOTH_CNTL_MACRO__ + +/* macros for field bt_break_cck_en */ +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__SHIFT 0 +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__WIDTH 1 +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__MASK 0x00000001U +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field bt_ant_halt_wlan */ +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__SHIFT 1 +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__WIDTH 1 +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__MASK 0x00000002U +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) +#define BLUETOOTH_CNTL__TYPE u_int32_t +#define BLUETOOTH_CNTL__READ 0x00000003U +#define BLUETOOTH_CNTL__WRITE 0x00000003U + +#endif /* __BLUETOOTH_CNTL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_bluetooth_cntl */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BLUETOOTH_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::phyonly_warm_reset */ +#ifndef __PHYONLY_WARM_RESET_MACRO__ +#define __PHYONLY_WARM_RESET_MACRO__ + +/* macros for field phyonly_rst_warm_l */ +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__SHIFT 0 +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__WIDTH 1 +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__MASK 0x00000001U +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) +#define PHYONLY_WARM_RESET__TYPE u_int32_t +#define PHYONLY_WARM_RESET__READ 0x00000001U +#define PHYONLY_WARM_RESET__WRITE 0x00000001U + +#endif /* __PHYONLY_WARM_RESET_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_phyonly_warm_reset */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PHYONLY_WARM_RESET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::phyonly_control */ +#ifndef __PHYONLY_CONTROL_MACRO__ +#define __PHYONLY_CONTROL_MACRO__ + +/* macros for field rx_drain_rate */ +#define PHYONLY_CONTROL__RX_DRAIN_RATE__SHIFT 0 +#define PHYONLY_CONTROL__RX_DRAIN_RATE__WIDTH 1 +#define PHYONLY_CONTROL__RX_DRAIN_RATE__MASK 0x00000001U +#define PHYONLY_CONTROL__RX_DRAIN_RATE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PHYONLY_CONTROL__RX_DRAIN_RATE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PHYONLY_CONTROL__RX_DRAIN_RATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PHYONLY_CONTROL__RX_DRAIN_RATE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PHYONLY_CONTROL__RX_DRAIN_RATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PHYONLY_CONTROL__RX_DRAIN_RATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field late_tx_signal_symbol */ +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__SHIFT 1 +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__WIDTH 1 +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__MASK 0x00000002U +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field generate_scrambler */ +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__SHIFT 2 +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__WIDTH 1 +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__MASK 0x00000004U +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field tx_antenna_select */ +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__SHIFT 3 +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__WIDTH 1 +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__MASK 0x00000008U +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field static_tx_antenna */ +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__SHIFT 4 +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__WIDTH 1 +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__MASK 0x00000010U +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field rx_antenna_select */ +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__SHIFT 5 +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__WIDTH 1 +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__MASK 0x00000020U +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field static_rx_antenna */ +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__SHIFT 6 +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__WIDTH 1 +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__MASK 0x00000040U +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field en_low_freq_sleep */ +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__SHIFT 7 +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__WIDTH 1 +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__MASK 0x00000080U +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) +#define PHYONLY_CONTROL__TYPE u_int32_t +#define PHYONLY_CONTROL__READ 0x000000ffU +#define PHYONLY_CONTROL__WRITE 0x000000ffU + +#endif /* __PHYONLY_CONTROL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_phyonly_control */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PHYONLY_CONTROL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::eco_ctrl */ +#ifndef __ECO_CTRL_MACRO__ +#define __ECO_CTRL_MACRO__ + +/* macros for field eco_ctrl */ +#define ECO_CTRL__ECO_CTRL__SHIFT 0 +#define ECO_CTRL__ECO_CTRL__WIDTH 8 +#define ECO_CTRL__ECO_CTRL__MASK 0x000000ffU +#define ECO_CTRL__ECO_CTRL__READ(src) (u_int32_t)(src) & 0x000000ffU +#define ECO_CTRL__ECO_CTRL__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define ECO_CTRL__ECO_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define ECO_CTRL__ECO_CTRL__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) +#define ECO_CTRL__TYPE u_int32_t +#define ECO_CTRL__READ 0x000000ffU +#define ECO_CTRL__WRITE 0x000000ffU + +#endif /* __ECO_CTRL_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_eco_ctrl */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ECO_CTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tables_intf_addr_b0 */ +#ifndef __TABLES_INTF_ADDR_B0_MACRO__ +#define __TABLES_INTF_ADDR_B0_MACRO__ + +/* macros for field tables_addr_0 */ +#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__SHIFT 2 +#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__WIDTH 16 +#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__MASK 0x0003fffcU +#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fffcU) >> 2) +#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0003fffcU) +#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0003fffcU) +#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0003fffcU))) + +/* macros for field addr_auto_incr_0 */ +#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__SHIFT 31 +#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__WIDTH 1 +#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__MASK 0x80000000U +#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TABLES_INTF_ADDR_B0__TYPE u_int32_t +#define TABLES_INTF_ADDR_B0__READ 0x8003fffcU +#define TABLES_INTF_ADDR_B0__WRITE 0x8003fffcU + +#endif /* __TABLES_INTF_ADDR_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tables_intf_addr_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TABLES_INTF_ADDR_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tables_intf_data_b0 */ +#ifndef __TABLES_INTF_DATA_B0_MACRO__ +#define __TABLES_INTF_DATA_B0_MACRO__ + +/* macros for field tables_data_0 */ +#define TABLES_INTF_DATA_B0__TABLES_DATA_0__SHIFT 0 +#define TABLES_INTF_DATA_B0__TABLES_DATA_0__WIDTH 32 +#define TABLES_INTF_DATA_B0__TABLES_DATA_0__MASK 0xffffffffU +#define TABLES_INTF_DATA_B0__TABLES_DATA_0__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TABLES_INTF_DATA_B0__TABLES_DATA_0__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TABLES_INTF_DATA_B0__TABLES_DATA_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TABLES_INTF_DATA_B0__TABLES_DATA_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TABLES_INTF_DATA_B0__TYPE u_int32_t +#define TABLES_INTF_DATA_B0__READ 0xffffffffU +#define TABLES_INTF_DATA_B0__WRITE 0xffffffffU + +#endif /* __TABLES_INTF_DATA_B0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm_reg_map.BB_tables_intf_data_b0 */ +#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TABLES_INTF_DATA_B0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b1 */ +#ifndef __EXT_CHAN_PWR_THR_2_B1_MACRO__ +#define __EXT_CHAN_PWR_THR_2_B1_MACRO__ + +/* macros for field cf_maxCCApwr_ext_1 */ +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__SHIFT 0 +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__MASK 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field minCCApwr_ext_1 */ +#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__SHIFT 16 +#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__MASK 0x01ff0000U +#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01ff0000U) >> 16) +#define EXT_CHAN_PWR_THR_2_B1__TYPE u_int32_t +#define EXT_CHAN_PWR_THR_2_B1__READ 0x01ff01ffU +#define EXT_CHAN_PWR_THR_2_B1__WRITE 0x01ff01ffU + +#endif /* __EXT_CHAN_PWR_THR_2_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_ext_chan_pwr_thr_2_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_report_b1 */ +#ifndef __SPUR_REPORT_B1_MACRO__ +#define __SPUR_REPORT_B1_MACRO__ + +/* macros for field spur_est_i_1 */ +#define SPUR_REPORT_B1__SPUR_EST_I_1__SHIFT 0 +#define SPUR_REPORT_B1__SPUR_EST_I_1__WIDTH 8 +#define SPUR_REPORT_B1__SPUR_EST_I_1__MASK 0x000000ffU +#define SPUR_REPORT_B1__SPUR_EST_I_1__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field spur_est_q_1 */ +#define SPUR_REPORT_B1__SPUR_EST_Q_1__SHIFT 8 +#define SPUR_REPORT_B1__SPUR_EST_Q_1__WIDTH 8 +#define SPUR_REPORT_B1__SPUR_EST_Q_1__MASK 0x0000ff00U +#define SPUR_REPORT_B1__SPUR_EST_Q_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field power_with_spur_removed_1 */ +#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__SHIFT 16 +#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__WIDTH 16 +#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__MASK 0xffff0000U +#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define SPUR_REPORT_B1__TYPE u_int32_t +#define SPUR_REPORT_B1__READ 0xffffffffU + +#endif /* __SPUR_REPORT_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_spur_report_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_SPUR_REPORT_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b1 */ +#ifndef __IQ_ADC_MEAS_0_B1_MACRO__ +#define __IQ_ADC_MEAS_0_B1_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_0_1 */ +#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__SHIFT 0 +#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__WIDTH 32 +#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__MASK 0xffffffffU +#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_0_B1__TYPE u_int32_t +#define IQ_ADC_MEAS_0_B1__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_0_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_0_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_0_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b1 */ +#ifndef __IQ_ADC_MEAS_1_B1_MACRO__ +#define __IQ_ADC_MEAS_1_B1_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_1_1 */ +#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__SHIFT 0 +#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__WIDTH 32 +#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__MASK 0xffffffffU +#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_1_B1__TYPE u_int32_t +#define IQ_ADC_MEAS_1_B1__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_1_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_1_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_1_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b1 */ +#ifndef __IQ_ADC_MEAS_2_B1_MACRO__ +#define __IQ_ADC_MEAS_2_B1_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_2_1 */ +#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__SHIFT 0 +#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__WIDTH 32 +#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__MASK 0xffffffffU +#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_2_B1__TYPE u_int32_t +#define IQ_ADC_MEAS_2_B1__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_2_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_2_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b1 */ +#ifndef __IQ_ADC_MEAS_3_B1_MACRO__ +#define __IQ_ADC_MEAS_3_B1_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_3_1 */ +#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__SHIFT 0 +#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__WIDTH 32 +#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__MASK 0xffffffffU +#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_3_B1__TYPE u_int32_t +#define IQ_ADC_MEAS_3_B1__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_3_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_3_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_3_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b1 */ +#ifndef __TX_PHASE_RAMP_B1_MACRO__ +#define __TX_PHASE_RAMP_B1_MACRO__ + +/* macros for field cf_phase_ramp_enable_1 */ +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__SHIFT 0 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__WIDTH 1 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__MASK 0x00000001U +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_phase_ramp_bias_1 */ +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__SHIFT 1 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__WIDTH 6 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__MASK 0x0000007eU +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000007eU) >> 1) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000007eU))) + +/* macros for field cf_phase_ramp_init_1 */ +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__SHIFT 7 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__WIDTH 10 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__MASK 0x0001ff80U +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001ff80U) >> 7) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ff80U) | (((u_int32_t)(src) <<\ + 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x0001ff80U))) + +/* macros for field cf_phase_ramp_alpha_1 */ +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__SHIFT 17 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__WIDTH 8 +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__MASK 0x01fe0000U +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fe0000U) >> 17) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x01fe0000U))) +#define TX_PHASE_RAMP_B1__TYPE u_int32_t +#define TX_PHASE_RAMP_B1__READ 0x01ffffffU +#define TX_PHASE_RAMP_B1__WRITE 0x01ffffffU + +#endif /* __TX_PHASE_RAMP_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_tx_phase_ramp_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_TX_PHASE_RAMP_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b1 */ +#ifndef __ADC_GAIN_DC_CORR_B1_MACRO__ +#define __ADC_GAIN_DC_CORR_B1_MACRO__ + +/* macros for field adc_gain_corr_q_coeff_1 */ +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__SHIFT 0 +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__WIDTH 6 +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__MASK 0x0000003fU +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field adc_gain_corr_i_coeff_1 */ +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__SHIFT 6 +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__WIDTH 6 +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__MASK 0x00000fc0U +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field adc_dc_corr_q_coeff_1 */ +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__SHIFT 12 +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__WIDTH 9 +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__MASK 0x001ff000U +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x001ff000U) >> 12) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x001ff000U))) + +/* macros for field adc_dc_corr_i_coeff_1 */ +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__SHIFT 21 +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__WIDTH 9 +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__MASK 0x3fe00000U +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x3fe00000U) >> 21) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x3fe00000U))) +#define ADC_GAIN_DC_CORR_B1__TYPE u_int32_t +#define ADC_GAIN_DC_CORR_B1__READ 0x3fffffffU +#define ADC_GAIN_DC_CORR_B1__WRITE 0x3fffffffU + +#endif /* __ADC_GAIN_DC_CORR_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_adc_gain_dc_corr_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_ADC_GAIN_DC_CORR_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b1 */ +#ifndef __RX_IQ_CORR_B1_MACRO__ +#define __RX_IQ_CORR_B1_MACRO__ + +/* macros for field rx_iqcorr_q_q_coff_1 */ +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__SHIFT 0 +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__WIDTH 7 +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__MASK 0x0000007fU +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field rx_iqcorr_q_i_coff_1 */ +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__SHIFT 7 +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__WIDTH 7 +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__MASK 0x00003f80U +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f80U) >> 7) +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00003f80U) +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00003f80U) +#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00003f80U))) + +/* macros for field loopback_iqcorr_q_q_coff_1 */ +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__SHIFT 15 +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__WIDTH 7 +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__MASK 0x003f8000U +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f8000U) >> 15) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x003f8000U) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x003f8000U) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x003f8000U))) + +/* macros for field loopback_iqcorr_q_i_coff_1 */ +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__SHIFT 22 +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__WIDTH 7 +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__MASK 0x1fc00000U +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x1fc00000U) >> 22) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x1fc00000U) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x1fc00000U) +#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x1fc00000U))) +#define RX_IQ_CORR_B1__TYPE u_int32_t +#define RX_IQ_CORR_B1__READ 0x1fffbfffU +#define RX_IQ_CORR_B1__WRITE 0x1fffbfffU + +#endif /* __RX_IQ_CORR_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_rx_iq_corr_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_RX_IQ_CORR_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b1 */ +#ifndef __PAPRD_CTRL0_B1_MACRO__ +#define __PAPRD_CTRL0_B1_MACRO__ + +/* macros for field paprd_enable_1 */ +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__SHIFT 0 +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__WIDTH 1 +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__MASK 0x00000001U +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_use_single_table_1 */ +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__SHIFT 1 +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__WIDTH 1 +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__MASK 0x00000002U +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_valid_gain_1 */ +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__SHIFT 2 +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__WIDTH 25 +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__MASK 0x07fffffcU +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fffffcU) >> 2) +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fffffcU) | (((u_int32_t)(src) <<\ + 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x07fffffcU))) + +/* macros for field paprd_mag_thrsh_1 */ +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__SHIFT 27 +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__WIDTH 5 +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__MASK 0xf8000000U +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define PAPRD_CTRL0_B1__TYPE u_int32_t +#define PAPRD_CTRL0_B1__READ 0xffffffffU +#define PAPRD_CTRL0_B1__WRITE 0xffffffffU + +#endif /* __PAPRD_CTRL0_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_ctrl0_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_CTRL0_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b1 */ +#ifndef __PAPRD_CTRL1_B1_MACRO__ +#define __PAPRD_CTRL1_B1_MACRO__ + +/* macros for field paprd_adaptive_scaling_enable_1 */ +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__SHIFT 0 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__WIDTH 1 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__MASK 0x00000001U +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_am2am_enable_1 */ +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__SHIFT 1 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__WIDTH 1 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__MASK 0x00000002U +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_adaptive_am2pm_enable_1 */ +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__SHIFT 2 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__WIDTH 1 +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__MASK 0x00000004U +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field paprd_power_at_am2am_cal_1 */ +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__SHIFT 3 +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__WIDTH 6 +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__MASK 0x000001f8U +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001f8U) >> 3) +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000001f8U) +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000001f8U) +#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000001f8U))) + +/* macros for field pa_gain_scale_factor_1 */ +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__SHIFT 9 +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__WIDTH 8 +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__MASK 0x0001fe00U +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fe00U) >> 9) +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((u_int32_t)(src) <<\ + 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x0001fe00U))) + +/* macros for field paprd_mag_scale_factor_1 */ +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__SHIFT 17 +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__WIDTH 10 +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__MASK 0x07fe0000U +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fe0000U) >> 17) +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x07fe0000U))) + +/* macros for field paprd_trainer_iandq_sel_1 */ +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__SHIFT 27 +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__WIDTH 1 +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__MASK 0x08000000U +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) +#define PAPRD_CTRL1_B1__TYPE u_int32_t +#define PAPRD_CTRL1_B1__READ 0x0fffffffU +#define PAPRD_CTRL1_B1__WRITE 0x0fffffffU + +#endif /* __PAPRD_CTRL1_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_ctrl1_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_CTRL1_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain123_b1 */ +#ifndef __PA_GAIN123_B1_MACRO__ +#define __PA_GAIN123_B1_MACRO__ + +/* macros for field pa_gain1_1 */ +#define PA_GAIN123_B1__PA_GAIN1_1__SHIFT 0 +#define PA_GAIN123_B1__PA_GAIN1_1__WIDTH 10 +#define PA_GAIN123_B1__PA_GAIN1_1__MASK 0x000003ffU +#define PA_GAIN123_B1__PA_GAIN1_1__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN123_B1__PA_GAIN1_1__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN123_B1__PA_GAIN1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN123_B1__PA_GAIN1_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain2_1 */ +#define PA_GAIN123_B1__PA_GAIN2_1__SHIFT 10 +#define PA_GAIN123_B1__PA_GAIN2_1__WIDTH 10 +#define PA_GAIN123_B1__PA_GAIN2_1__MASK 0x000ffc00U +#define PA_GAIN123_B1__PA_GAIN2_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN123_B1__PA_GAIN2_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN123_B1__PA_GAIN2_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN123_B1__PA_GAIN2_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field pa_gain3_1 */ +#define PA_GAIN123_B1__PA_GAIN3_1__SHIFT 20 +#define PA_GAIN123_B1__PA_GAIN3_1__WIDTH 10 +#define PA_GAIN123_B1__PA_GAIN3_1__MASK 0x3ff00000U +#define PA_GAIN123_B1__PA_GAIN3_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ff00000U) >> 20) +#define PA_GAIN123_B1__PA_GAIN3_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x3ff00000U) +#define PA_GAIN123_B1__PA_GAIN3_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x3ff00000U) +#define PA_GAIN123_B1__PA_GAIN3_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define PA_GAIN123_B1__TYPE u_int32_t +#define PA_GAIN123_B1__READ 0x3fffffffU +#define PA_GAIN123_B1__WRITE 0x3fffffffU + +#endif /* __PA_GAIN123_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_pa_gain123_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PA_GAIN123_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain45_b1 */ +#ifndef __PA_GAIN45_B1_MACRO__ +#define __PA_GAIN45_B1_MACRO__ + +/* macros for field pa_gain4_1 */ +#define PA_GAIN45_B1__PA_GAIN4_1__SHIFT 0 +#define PA_GAIN45_B1__PA_GAIN4_1__WIDTH 10 +#define PA_GAIN45_B1__PA_GAIN4_1__MASK 0x000003ffU +#define PA_GAIN45_B1__PA_GAIN4_1__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN45_B1__PA_GAIN4_1__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN45_B1__PA_GAIN4_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN45_B1__PA_GAIN4_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain5_1 */ +#define PA_GAIN45_B1__PA_GAIN5_1__SHIFT 10 +#define PA_GAIN45_B1__PA_GAIN5_1__WIDTH 10 +#define PA_GAIN45_B1__PA_GAIN5_1__MASK 0x000ffc00U +#define PA_GAIN45_B1__PA_GAIN5_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN45_B1__PA_GAIN5_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN45_B1__PA_GAIN5_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN45_B1__PA_GAIN5_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field paprd_adaptive_table_valid_1 */ +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__SHIFT 20 +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__WIDTH 5 +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__MASK 0x01f00000U +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) +#define PA_GAIN45_B1__TYPE u_int32_t +#define PA_GAIN45_B1__READ 0x01ffffffU +#define PA_GAIN45_B1__WRITE 0x01ffffffU + +#endif /* __PA_GAIN45_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_pa_gain45_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PA_GAIN45_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_0_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_0_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_0_1 */ +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_0_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_0_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_0_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_0_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_1_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_1_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_1_1 */ +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_1_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_1_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_1_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_1_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_2_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_2_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_2_1 */ +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_2_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_2_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_2_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_2_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_3_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_3_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_3_1 */ +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_3_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_3_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_3_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_3_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_4_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_4_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_4_1 */ +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_4_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_4_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_4_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_4_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_5_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_5_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_5_1 */ +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_5_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_5_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_5_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_5_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_6_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_6_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_6_1 */ +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_6_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_6_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_6_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_6_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b1 */ +#ifndef __PAPRD_PRE_POST_SCALE_7_B1_MACRO__ +#define __PAPRD_PRE_POST_SCALE_7_B1_MACRO__ + +/* macros for field paprd_pre_post_scaling_7_1 */ +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_7_B1__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_7_B1__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B1__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_7_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_7_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */ +#ifndef __PAPRD_MEM_TAB_MACRO__ +#define __PAPRD_MEM_TAB_MACRO__ + +/* macros for field paprd_mem */ +#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT 0 +#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH 22 +#define PAPRD_MEM_TAB__PAPRD_MEM__MASK 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((u_int32_t)(src) &\ + 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x003fffffU))) +#define PAPRD_MEM_TAB__TYPE u_int32_t +#define PAPRD_MEM_TAB__READ 0x003fffffU +#define PAPRD_MEM_TAB__WRITE 0x003fffffU + +#endif /* __PAPRD_MEM_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_mem_tab_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_MEM_TAB_B1__NUM 120 + +/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */ +#ifndef __CHAN_INFO_CHAN_TAB_MACRO__ +#define __CHAN_INFO_CHAN_TAB_MACRO__ + +/* macros for field chaninfo_word */ +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT 0 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH 32 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK 0xffffffffU +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define CHAN_INFO_CHAN_TAB__TYPE u_int32_t +#define CHAN_INFO_CHAN_TAB__READ 0xffffffffU + +#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_chan_info_chan_tab_b1 */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B1__NUM 60 + +/* macros for BlueprintGlobalNameSpace::chn1_tables_intf_addr */ +#ifndef __CHN1_TABLES_INTF_ADDR_MACRO__ +#define __CHN1_TABLES_INTF_ADDR_MACRO__ + +/* macros for field chn1_tables_addr */ +#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__SHIFT 2 +#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__WIDTH 16 +#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__MASK 0x0003fffcU +#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fffcU) >> 2) +#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0003fffcU) +#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0003fffcU) +#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0003fffcU))) + +/* macros for field chn1_addr_auto_incr */ +#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__SHIFT 31 +#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__WIDTH 1 +#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__MASK 0x80000000U +#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define CHN1_TABLES_INTF_ADDR__TYPE u_int32_t +#define CHN1_TABLES_INTF_ADDR__READ 0x8003fffcU +#define CHN1_TABLES_INTF_ADDR__WRITE 0x8003fffcU + +#endif /* __CHN1_TABLES_INTF_ADDR_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_chn1_tables_intf_addr */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_CHN1_TABLES_INTF_ADDR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chn1_tables_intf_data */ +#ifndef __CHN1_TABLES_INTF_DATA_MACRO__ +#define __CHN1_TABLES_INTF_DATA_MACRO__ + +/* macros for field chn1_tables_data */ +#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__SHIFT 0 +#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__WIDTH 32 +#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__MASK 0xffffffffU +#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CHN1_TABLES_INTF_DATA__TYPE u_int32_t +#define CHN1_TABLES_INTF_DATA__READ 0xffffffffU +#define CHN1_TABLES_INTF_DATA__WRITE 0xffffffffU + +#endif /* __CHN1_TABLES_INTF_DATA_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn1_reg_map.BB_chn1_tables_intf_data */ +#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_CHN1_TABLES_INTF_DATA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b1 */ +#ifndef __GAIN_FORCE_MAX_GAINS_B1_MACRO__ +#define __GAIN_FORCE_MAX_GAINS_B1_MACRO__ + +/* macros for field rf_gain_f_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__SHIFT 0 +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__MASK 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field mb_gain_f_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__SHIFT 8 +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__MASK 0x0000ff00U +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field xatten1_sw_f_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__SHIFT 16 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__MASK 0x00010000U +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field xatten2_sw_f_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__SHIFT 17 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__MASK 0x00020000U +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field xatten1_hyst_margin_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__SHIFT 18 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__MASK 0x01fc0000U +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fc0000U) >> 18) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x01fc0000U))) + +/* macros for field xatten2_hyst_margin_1 */ +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__SHIFT 25 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__MASK 0xfe000000U +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0xfe000000U) >> 25) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfe000000U) | (((u_int32_t)(src) <<\ + 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0xfe000000U))) +#define GAIN_FORCE_MAX_GAINS_B1__TYPE u_int32_t +#define GAIN_FORCE_MAX_GAINS_B1__READ 0xffffffffU +#define GAIN_FORCE_MAX_GAINS_B1__WRITE 0xffffffffU + +#endif /* __GAIN_FORCE_MAX_GAINS_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc1_reg_map.BB_gain_force_max_gains_b1 */ +#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b1 */ +#ifndef __EXT_ATTEN_SWITCH_CTL_B1_MACRO__ +#define __EXT_ATTEN_SWITCH_CTL_B1_MACRO__ + +/* macros for field xatten1_db_1 */ +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__SHIFT 0 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__MASK 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field xatten2_db_1 */ +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__SHIFT 6 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__MASK 0x00000fc0U +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field xatten1_margin_1 */ +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__SHIFT 12 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__MASK 0x0001f000U +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field xatten2_margin_1 */ +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__SHIFT 17 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__MASK 0x003e0000U +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field xlna_gain_db_1 */ +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__SHIFT 22 +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__MASK 0x07c00000U +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) +#define EXT_ATTEN_SWITCH_CTL_B1__TYPE u_int32_t +#define EXT_ATTEN_SWITCH_CTL_B1__READ 0x07ffffffU +#define EXT_ATTEN_SWITCH_CTL_B1__WRITE 0x07ffffffU + +#endif /* __EXT_ATTEN_SWITCH_CTL_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc1_reg_map.BB_ext_atten_switch_ctl_b1 */ +#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_b1 */ +#ifndef __CCA_B1_MACRO__ +#define __CCA_B1_MACRO__ + +/* macros for field cf_maxCCApwr_1 */ +#define CCA_B1__CF_MAXCCAPWR_1__SHIFT 0 +#define CCA_B1__CF_MAXCCAPWR_1__WIDTH 9 +#define CCA_B1__CF_MAXCCAPWR_1__MASK 0x000001ffU +#define CCA_B1__CF_MAXCCAPWR_1__READ(src) (u_int32_t)(src) & 0x000001ffU +#define CCA_B1__CF_MAXCCAPWR_1__WRITE(src) ((u_int32_t)(src) & 0x000001ffU) +#define CCA_B1__CF_MAXCCAPWR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_B1__CF_MAXCCAPWR_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field minCCApwr_1 */ +#define CCA_B1__MINCCAPWR_1__SHIFT 20 +#define CCA_B1__MINCCAPWR_1__WIDTH 9 +#define CCA_B1__MINCCAPWR_1__MASK 0x1ff00000U +#define CCA_B1__MINCCAPWR_1__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20) +#define CCA_B1__TYPE u_int32_t +#define CCA_B1__READ 0x1ff001ffU +#define CCA_B1__WRITE 0x1ff001ffU + +#endif /* __CCA_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc1_reg_map.BB_cca_b1 */ +#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_CCA_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b1 */ +#ifndef __CCA_CTRL_2_B1_MACRO__ +#define __CCA_CTRL_2_B1_MACRO__ + +/* macros for field minCCApwr_thr_1 */ +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__SHIFT 0 +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__WIDTH 9 +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__MASK 0x000001ffU +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field NF_gain_comp_1 */ +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__SHIFT 10 +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__WIDTH 8 +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__MASK 0x0003fc00U +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fc00U) >> 10) +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0003fc00U) +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0003fc00U) +#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0003fc00U))) +#define CCA_CTRL_2_B1__TYPE u_int32_t +#define CCA_CTRL_2_B1__READ 0x0003fdffU +#define CCA_CTRL_2_B1__WRITE 0x0003fdffU + +#endif /* __CCA_CTRL_2_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc1_reg_map.BB_cca_ctrl_2_b1 */ +#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_CCA_CTRL_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rssi_b1 */ +#ifndef __RSSI_B1_MACRO__ +#define __RSSI_B1_MACRO__ + +/* macros for field rssi_1 */ +#define RSSI_B1__RSSI_1__SHIFT 0 +#define RSSI_B1__RSSI_1__WIDTH 8 +#define RSSI_B1__RSSI_1__MASK 0x000000ffU +#define RSSI_B1__RSSI_1__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field rssi_ext_1 */ +#define RSSI_B1__RSSI_EXT_1__SHIFT 8 +#define RSSI_B1__RSSI_EXT_1__WIDTH 8 +#define RSSI_B1__RSSI_EXT_1__MASK 0x0000ff00U +#define RSSI_B1__RSSI_EXT_1__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define RSSI_B1__TYPE u_int32_t +#define RSSI_B1__READ 0x0000ffffU + +#endif /* __RSSI_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc1_reg_map.BB_rssi_b1 */ +#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_RSSI_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_est_cck_report_b1 */ +#ifndef __SPUR_EST_CCK_REPORT_B1_MACRO__ +#define __SPUR_EST_CCK_REPORT_B1_MACRO__ + +/* macros for field spur_est_sd_i_1_cck */ +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__SHIFT 0 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__MASK 0x000000ffU +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field spur_est_sd_q_1_cck */ +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__SHIFT 8 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__MASK 0x0000ff00U +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field spur_est_i_1_cck */ +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__SHIFT 16 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__MASK 0x00ff0000U +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) + +/* macros for field spur_est_q_1_cck */ +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__SHIFT 24 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__WIDTH 8 +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__MASK 0xff000000U +#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define SPUR_EST_CCK_REPORT_B1__TYPE u_int32_t +#define SPUR_EST_CCK_REPORT_B1__READ 0xffffffffU + +#endif /* __SPUR_EST_CCK_REPORT_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc1_reg_map.BB_spur_est_cck_report_b1 */ +#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_SPUR_EST_CCK_REPORT_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b1 */ +#ifndef __AGC_DIG_DC_STATUS_I_B1_MACRO__ +#define __AGC_DIG_DC_STATUS_I_B1_MACRO__ + +/* macros for field dig_dc_C1_res_i_1 */ +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__SHIFT 0 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_i_1 */ +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__SHIFT 9 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_i_1 */ +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__SHIFT 18 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_I_B1__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_I_B1__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_I_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc1_reg_map.BB_agc_dig_dc_status_i_b1 */ +#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b1 */ +#ifndef __AGC_DIG_DC_STATUS_Q_B1_MACRO__ +#define __AGC_DIG_DC_STATUS_Q_B1_MACRO__ + +/* macros for field dig_dc_C1_res_q_1 */ +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__SHIFT 0 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_q_1 */ +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__SHIFT 9 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_q_1 */ +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__SHIFT 18 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_Q_B1__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_Q_B1__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_Q_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc1_reg_map.BB_agc_dig_dc_status_q_b1 */ +#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dc_cal_status_b1 */ +#ifndef __DC_CAL_STATUS_B1_MACRO__ +#define __DC_CAL_STATUS_B1_MACRO__ + +/* macros for field offsetC1I_1 */ +#define DC_CAL_STATUS_B1__OFFSETC1I_1__SHIFT 0 +#define DC_CAL_STATUS_B1__OFFSETC1I_1__WIDTH 5 +#define DC_CAL_STATUS_B1__OFFSETC1I_1__MASK 0x0000001fU +#define DC_CAL_STATUS_B1__OFFSETC1I_1__READ(src) (u_int32_t)(src) & 0x0000001fU + +/* macros for field offsetC1Q_1 */ +#define DC_CAL_STATUS_B1__OFFSETC1Q_1__SHIFT 5 +#define DC_CAL_STATUS_B1__OFFSETC1Q_1__WIDTH 5 +#define DC_CAL_STATUS_B1__OFFSETC1Q_1__MASK 0x000003e0U +#define DC_CAL_STATUS_B1__OFFSETC1Q_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) + +/* macros for field offsetC2I_1 */ +#define DC_CAL_STATUS_B1__OFFSETC2I_1__SHIFT 10 +#define DC_CAL_STATUS_B1__OFFSETC2I_1__WIDTH 5 +#define DC_CAL_STATUS_B1__OFFSETC2I_1__MASK 0x00007c00U +#define DC_CAL_STATUS_B1__OFFSETC2I_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) + +/* macros for field offsetC2Q_1 */ +#define DC_CAL_STATUS_B1__OFFSETC2Q_1__SHIFT 15 +#define DC_CAL_STATUS_B1__OFFSETC2Q_1__WIDTH 5 +#define DC_CAL_STATUS_B1__OFFSETC2Q_1__MASK 0x000f8000U +#define DC_CAL_STATUS_B1__OFFSETC2Q_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) + +/* macros for field offsetC3I_1 */ +#define DC_CAL_STATUS_B1__OFFSETC3I_1__SHIFT 20 +#define DC_CAL_STATUS_B1__OFFSETC3I_1__WIDTH 5 +#define DC_CAL_STATUS_B1__OFFSETC3I_1__MASK 0x01f00000U +#define DC_CAL_STATUS_B1__OFFSETC3I_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) + +/* macros for field offsetC3Q_1 */ +#define DC_CAL_STATUS_B1__OFFSETC3Q_1__SHIFT 25 +#define DC_CAL_STATUS_B1__OFFSETC3Q_1__WIDTH 5 +#define DC_CAL_STATUS_B1__OFFSETC3Q_1__MASK 0x3e000000U +#define DC_CAL_STATUS_B1__OFFSETC3Q_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define DC_CAL_STATUS_B1__TYPE u_int32_t +#define DC_CAL_STATUS_B1__READ 0x3fffffffU + +#endif /* __DC_CAL_STATUS_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc1_reg_map.BB_dc_cal_status_b1 */ +#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_DC_CAL_STATUS_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_ocgain2 */ +#ifndef __RX_OCGAIN2_MACRO__ +#define __RX_OCGAIN2_MACRO__ + +/* macros for field gain_entry2 */ +#define RX_OCGAIN2__GAIN_ENTRY2__SHIFT 0 +#define RX_OCGAIN2__GAIN_ENTRY2__WIDTH 32 +#define RX_OCGAIN2__GAIN_ENTRY2__MASK 0xffffffffU +#define RX_OCGAIN2__GAIN_ENTRY2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define RX_OCGAIN2__GAIN_ENTRY2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define RX_OCGAIN2__GAIN_ENTRY2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define RX_OCGAIN2__GAIN_ENTRY2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define RX_OCGAIN2__TYPE u_int32_t +#define RX_OCGAIN2__READ 0xffffffffU +#define RX_OCGAIN2__WRITE 0xffffffffU + +#endif /* __RX_OCGAIN2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc1_reg_map.BB_rx_ocgain2 */ +#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_RX_OCGAIN2__NUM 128 + +/* macros for BlueprintGlobalNameSpace::switch_table_chn_b1 */ +#ifndef __SWITCH_TABLE_CHN_B1_MACRO__ +#define __SWITCH_TABLE_CHN_B1_MACRO__ + +/* macros for field switch_table_idle_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__SHIFT 0 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__MASK 0x00000003U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field switch_table_t_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__SHIFT 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__MASK 0x0000000cU +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field switch_table_r_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__SHIFT 4 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__MASK 0x00000030U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field switch_table_rx1_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__SHIFT 6 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__MASK 0x000000c0U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field switch_table_rx12_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__SHIFT 8 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__MASK 0x00000300U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field switch_table_b_1 */ +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__SHIFT 10 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__WIDTH 2 +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__MASK 0x00000c00U +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) +#define SWITCH_TABLE_CHN_B1__TYPE u_int32_t +#define SWITCH_TABLE_CHN_B1__READ 0x00000fffU +#define SWITCH_TABLE_CHN_B1__WRITE 0x00000fffU + +#endif /* __SWITCH_TABLE_CHN_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_switch_table_chn_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_SWITCH_TABLE_CHN_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::fcal_2_b1 */ +#ifndef __FCAL_2_B1_MACRO__ +#define __FCAL_2_B1_MACRO__ + +/* macros for field flc_sw_cap_val_1 */ +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__SHIFT 3 +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__WIDTH 5 +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__MASK 0x000000f8U +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f8U) >> 3) +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000000f8U) +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000000f8U) +#define FCAL_2_B1__FLC_SW_CAP_VAL_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000000f8U))) + +/* macros for field flc_cap_val_status_1 */ +#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__SHIFT 20 +#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__WIDTH 5 +#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__MASK 0x01f00000U +#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define FCAL_2_B1__TYPE u_int32_t +#define FCAL_2_B1__READ 0x01f000f8U +#define FCAL_2_B1__WRITE 0x01f000f8U + +#endif /* __FCAL_2_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_fcal_2_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_FCAL_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b1 */ +#ifndef __DFT_TONE_CTRL_B1_MACRO__ +#define __DFT_TONE_CTRL_B1_MACRO__ + +/* macros for field dft_tone_en_1 */ +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__SHIFT 0 +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__WIDTH 1 +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__MASK 0x00000001U +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dft_tone_amp_sel_1 */ +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__SHIFT 2 +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__WIDTH 2 +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__MASK 0x0000000cU +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field dft_tone_freq_ang_1 */ +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__SHIFT 4 +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__WIDTH 9 +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__MASK 0x00001ff0U +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001ff0U) >> 4) +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001ff0U) | (((u_int32_t)(src) <<\ + 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00001ff0U))) +#define DFT_TONE_CTRL_B1__TYPE u_int32_t +#define DFT_TONE_CTRL_B1__READ 0x00001ffdU +#define DFT_TONE_CTRL_B1__WRITE 0x00001ffdU + +#endif /* __DFT_TONE_CTRL_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_dft_tone_ctrl_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_DFT_TONE_CTRL_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_0 */ +#ifndef __CL_MAP_0_MACRO__ +#define __CL_MAP_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_0__TYPE u_int32_t +#define CL_MAP_0__READ 0xffffffffU +#define CL_MAP_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_0_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_0_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_1 */ +#ifndef __CL_MAP_1_MACRO__ +#define __CL_MAP_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_1__TYPE u_int32_t +#define CL_MAP_1__READ 0xffffffffU +#define CL_MAP_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_1_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_1_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_2 */ +#ifndef __CL_MAP_2_MACRO__ +#define __CL_MAP_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_2__TYPE u_int32_t +#define CL_MAP_2__READ 0xffffffffU +#define CL_MAP_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_2_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_3 */ +#ifndef __CL_MAP_3_MACRO__ +#define __CL_MAP_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_3__TYPE u_int32_t +#define CL_MAP_3__READ 0xffffffffU +#define CL_MAP_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_3_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_3_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */ +#ifndef __CL_MAP_PAL_0_MACRO__ +#define __CL_MAP_PAL_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_PAL_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_PAL_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_PAL_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_0__TYPE u_int32_t +#define CL_MAP_PAL_0__READ 0xffffffffU +#define CL_MAP_PAL_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_0_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_0_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */ +#ifndef __CL_MAP_PAL_1_MACRO__ +#define __CL_MAP_PAL_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_PAL_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_PAL_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_PAL_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_1__TYPE u_int32_t +#define CL_MAP_PAL_1__READ 0xffffffffU +#define CL_MAP_PAL_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_1_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_1_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */ +#ifndef __CL_MAP_PAL_2_MACRO__ +#define __CL_MAP_PAL_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_PAL_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_PAL_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_PAL_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_2__TYPE u_int32_t +#define CL_MAP_PAL_2__READ 0xffffffffU +#define CL_MAP_PAL_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_2_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_2_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */ +#ifndef __CL_MAP_PAL_3_MACRO__ +#define __CL_MAP_PAL_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_PAL_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_PAL_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_PAL_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_3__TYPE u_int32_t +#define CL_MAP_PAL_3__READ 0xffffffffU +#define CL_MAP_PAL_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_3_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_3_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_tab */ +#ifndef __CL_TAB_MACRO__ +#define __CL_TAB_MACRO__ + +/* macros for field cl_gain_mod */ +#define CL_TAB__CL_GAIN_MOD__SHIFT 0 +#define CL_TAB__CL_GAIN_MOD__WIDTH 5 +#define CL_TAB__CL_GAIN_MOD__MASK 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field carr_lk_dc_add_Q */ +#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT 5 +#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_Q__MASK 0x0000ffe0U +#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ffe0U) >> 5) +#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffe0U) | (((u_int32_t)(src) <<\ + 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x0000ffe0U))) + +/* macros for field carr_lk_dc_add_I */ +#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT 16 +#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_I__MASK 0x07ff0000U +#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) + +/* macros for field bb_gain */ +#define CL_TAB__BB_GAIN__SHIFT 27 +#define CL_TAB__BB_GAIN__WIDTH 4 +#define CL_TAB__BB_GAIN__MASK 0x78000000U +#define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) +#define CL_TAB__TYPE u_int32_t +#define CL_TAB__READ 0x7fffffffU +#define CL_TAB__WRITE 0x7fffffffU + +#endif /* __CL_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_tab_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_TAB_B1__NUM 16 + +/* macros for BlueprintGlobalNameSpace::chan_info_gain_b1 */ +#ifndef __CHAN_INFO_GAIN_B1_MACRO__ +#define __CHAN_INFO_GAIN_B1_MACRO__ + +/* macros for field chan_info_rssi_1 */ +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__SHIFT 0 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__WIDTH 8 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__MASK 0x000000ffU +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field chan_info_rf_gain_1 */ +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__SHIFT 8 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__WIDTH 8 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__MASK 0x0000ff00U +#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field chan_info_mb_gain_1 */ +#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__SHIFT 16 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__WIDTH 7 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__MASK 0x007f0000U +#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) + +/* macros for field chan_info_xatten1_sw_1 */ +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__SHIFT 23 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__WIDTH 1 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__MASK 0x00800000U +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field chan_info_xatten2_sw_1 */ +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__SHIFT 24 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__WIDTH 1 +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__MASK 0x01000000U +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define CHAN_INFO_GAIN_B1__TYPE u_int32_t +#define CHAN_INFO_GAIN_B1__READ 0x01ffffffU + +#endif /* __CHAN_INFO_GAIN_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_chan_info_gain_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CHAN_INFO_GAIN_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_4_b1 */ +#ifndef __TPC_4_B1_MACRO__ +#define __TPC_4_B1_MACRO__ + +/* macros for field pd_avg_valid_1 */ +#define TPC_4_B1__PD_AVG_VALID_1__SHIFT 0 +#define TPC_4_B1__PD_AVG_VALID_1__WIDTH 1 +#define TPC_4_B1__PD_AVG_VALID_1__MASK 0x00000001U +#define TPC_4_B1__PD_AVG_VALID_1__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_4_B1__PD_AVG_VALID_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_4_B1__PD_AVG_VALID_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field pd_avg_out_1 */ +#define TPC_4_B1__PD_AVG_OUT_1__SHIFT 1 +#define TPC_4_B1__PD_AVG_OUT_1__WIDTH 8 +#define TPC_4_B1__PD_AVG_OUT_1__MASK 0x000001feU +#define TPC_4_B1__PD_AVG_OUT_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) + +/* macros for field dac_gain_1 */ +#define TPC_4_B1__DAC_GAIN_1__SHIFT 9 +#define TPC_4_B1__DAC_GAIN_1__WIDTH 5 +#define TPC_4_B1__DAC_GAIN_1__MASK 0x00003e00U +#define TPC_4_B1__DAC_GAIN_1__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9) + +/* macros for field tx_gain_setting_1 */ +#define TPC_4_B1__TX_GAIN_SETTING_1__SHIFT 14 +#define TPC_4_B1__TX_GAIN_SETTING_1__WIDTH 6 +#define TPC_4_B1__TX_GAIN_SETTING_1__MASK 0x000fc000U +#define TPC_4_B1__TX_GAIN_SETTING_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) + +/* macros for field rate_sent_1 */ +#define TPC_4_B1__RATE_SENT_1__SHIFT 20 +#define TPC_4_B1__RATE_SENT_1__WIDTH 5 +#define TPC_4_B1__RATE_SENT_1__MASK 0x01f00000U +#define TPC_4_B1__RATE_SENT_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_4_B1__TYPE u_int32_t +#define TPC_4_B1__READ 0x01ffffffU + +#endif /* __TPC_4_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_4_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_4_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_5_b1 */ +#ifndef __TPC_5_B1_MACRO__ +#define __TPC_5_B1_MACRO__ + +/* macros for field pd_gain_boundary_1_1 */ +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__SHIFT 4 +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__WIDTH 6 +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__MASK 0x000003f0U +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field pd_gain_boundary_2_1 */ +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__SHIFT 10 +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__WIDTH 6 +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__MASK 0x0000fc00U +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fc00U) >> 10) +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0000fc00U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0000fc00U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0000fc00U))) + +/* macros for field pd_gain_boundary_3_1 */ +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__SHIFT 16 +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__WIDTH 6 +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__MASK 0x003f0000U +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field pd_gain_boundary_4_1 */ +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__SHIFT 22 +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__WIDTH 6 +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__MASK 0x0fc00000U +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fc00000U) >> 22) +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x0fc00000U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x0fc00000U) +#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x0fc00000U))) +#define TPC_5_B1__TYPE u_int32_t +#define TPC_5_B1__READ 0x0ffffff0U +#define TPC_5_B1__WRITE 0x0ffffff0U + +#endif /* __TPC_5_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_5_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_5_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_6_b1 */ +#ifndef __TPC_6_B1_MACRO__ +#define __TPC_6_B1_MACRO__ + +/* macros for field pd_dac_setting_1_1 */ +#define TPC_6_B1__PD_DAC_SETTING_1_1__SHIFT 0 +#define TPC_6_B1__PD_DAC_SETTING_1_1__WIDTH 6 +#define TPC_6_B1__PD_DAC_SETTING_1_1__MASK 0x0000003fU +#define TPC_6_B1__PD_DAC_SETTING_1_1__READ(src) (u_int32_t)(src) & 0x0000003fU +#define TPC_6_B1__PD_DAC_SETTING_1_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define TPC_6_B1__PD_DAC_SETTING_1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TPC_6_B1__PD_DAC_SETTING_1_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field pd_dac_setting_2_1 */ +#define TPC_6_B1__PD_DAC_SETTING_2_1__SHIFT 6 +#define TPC_6_B1__PD_DAC_SETTING_2_1__WIDTH 6 +#define TPC_6_B1__PD_DAC_SETTING_2_1__MASK 0x00000fc0U +#define TPC_6_B1__PD_DAC_SETTING_2_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TPC_6_B1__PD_DAC_SETTING_2_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TPC_6_B1__PD_DAC_SETTING_2_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TPC_6_B1__PD_DAC_SETTING_2_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field pd_dac_setting_3_1 */ +#define TPC_6_B1__PD_DAC_SETTING_3_1__SHIFT 12 +#define TPC_6_B1__PD_DAC_SETTING_3_1__WIDTH 6 +#define TPC_6_B1__PD_DAC_SETTING_3_1__MASK 0x0003f000U +#define TPC_6_B1__PD_DAC_SETTING_3_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define TPC_6_B1__PD_DAC_SETTING_3_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define TPC_6_B1__PD_DAC_SETTING_3_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define TPC_6_B1__PD_DAC_SETTING_3_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field pd_dac_setting_4_1 */ +#define TPC_6_B1__PD_DAC_SETTING_4_1__SHIFT 18 +#define TPC_6_B1__PD_DAC_SETTING_4_1__WIDTH 6 +#define TPC_6_B1__PD_DAC_SETTING_4_1__MASK 0x00fc0000U +#define TPC_6_B1__PD_DAC_SETTING_4_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TPC_6_B1__PD_DAC_SETTING_4_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define TPC_6_B1__PD_DAC_SETTING_4_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define TPC_6_B1__PD_DAC_SETTING_4_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field error_est_mode */ +#define TPC_6_B1__ERROR_EST_MODE__SHIFT 24 +#define TPC_6_B1__ERROR_EST_MODE__WIDTH 2 +#define TPC_6_B1__ERROR_EST_MODE__MASK 0x03000000U +#define TPC_6_B1__ERROR_EST_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x03000000U) >> 24) +#define TPC_6_B1__ERROR_EST_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x03000000U) +#define TPC_6_B1__ERROR_EST_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define TPC_6_B1__ERROR_EST_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field error_est_filter_coeff */ +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__SHIFT 26 +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__WIDTH 3 +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__MASK 0x1c000000U +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TPC_6_B1__ERROR_EST_FILTER_COEFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) +#define TPC_6_B1__TYPE u_int32_t +#define TPC_6_B1__READ 0x1fffffffU +#define TPC_6_B1__WRITE 0x1fffffffU + +#endif /* __TPC_6_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_6_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_6_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_11_b1 */ +#ifndef __TPC_11_B1_MACRO__ +#define __TPC_11_B1_MACRO__ + +/* macros for field olpc_gain_delta_1 */ +#define TPC_11_B1__OLPC_GAIN_DELTA_1__SHIFT 16 +#define TPC_11_B1__OLPC_GAIN_DELTA_1__WIDTH 8 +#define TPC_11_B1__OLPC_GAIN_DELTA_1__MASK 0x00ff0000U +#define TPC_11_B1__OLPC_GAIN_DELTA_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TPC_11_B1__OLPC_GAIN_DELTA_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TPC_11_B1__OLPC_GAIN_DELTA_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TPC_11_B1__OLPC_GAIN_DELTA_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field olpc_gain_delta_1_pal_on */ +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__SHIFT 24 +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__WIDTH 8 +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__MASK 0xff000000U +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TPC_11_B1__TYPE u_int32_t +#define TPC_11_B1__READ 0xffff0000U +#define TPC_11_B1__WRITE 0xffff0000U + +#endif /* __TPC_11_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_11_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_11_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_19_b1 */ +#ifndef __TPC_19_B1_MACRO__ +#define __TPC_19_B1_MACRO__ + +/* macros for field alpha_therm_1 */ +#define TPC_19_B1__ALPHA_THERM_1__SHIFT 0 +#define TPC_19_B1__ALPHA_THERM_1__WIDTH 8 +#define TPC_19_B1__ALPHA_THERM_1__MASK 0x000000ffU +#define TPC_19_B1__ALPHA_THERM_1__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TPC_19_B1__ALPHA_THERM_1__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define TPC_19_B1__ALPHA_THERM_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TPC_19_B1__ALPHA_THERM_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field alpha_therm_pal_on_1 */ +#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__SHIFT 8 +#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__WIDTH 8 +#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__MASK 0x0000ff00U +#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field alpha_volt_1 */ +#define TPC_19_B1__ALPHA_VOLT_1__SHIFT 16 +#define TPC_19_B1__ALPHA_VOLT_1__WIDTH 7 +#define TPC_19_B1__ALPHA_VOLT_1__MASK 0x007f0000U +#define TPC_19_B1__ALPHA_VOLT_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) +#define TPC_19_B1__ALPHA_VOLT_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x007f0000U) +#define TPC_19_B1__ALPHA_VOLT_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x007f0000U) +#define TPC_19_B1__ALPHA_VOLT_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x007f0000U))) + +/* macros for field alpha_volt_pal_on_1 */ +#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__SHIFT 23 +#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__WIDTH 7 +#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__MASK 0x3f800000U +#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f800000U) >> 23) +#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x3f800000U) +#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x3f800000U) +#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x3f800000U))) +#define TPC_19_B1__TYPE u_int32_t +#define TPC_19_B1__READ 0x3fffffffU +#define TPC_19_B1__WRITE 0x3fffffffU + +#endif /* __TPC_19_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_19_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_19_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pdadc_tab */ +#ifndef __PDADC_TAB_MACRO__ +#define __PDADC_TAB_MACRO__ + +/* macros for field tab_entry */ +#define PDADC_TAB__TAB_ENTRY__SHIFT 0 +#define PDADC_TAB__TAB_ENTRY__WIDTH 32 +#define PDADC_TAB__TAB_ENTRY__MASK 0xffffffffU +#define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define PDADC_TAB__TYPE u_int32_t +#define PDADC_TAB__WRITE 0x00000000U + +#endif /* __PDADC_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_pdadc_tab_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_PDADC_TAB_B1__NUM 32 + +/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_b1 */ +#ifndef __RTT_TABLE_SW_INTF_B1_MACRO__ +#define __RTT_TABLE_SW_INTF_B1_MACRO__ + +/* macros for field sw_rtt_table_access_1 */ +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__SHIFT 0 +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__WIDTH 1 +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__MASK 0x00000001U +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field sw_rtt_table_write_1 */ +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__SHIFT 1 +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__WIDTH 1 +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__MASK 0x00000002U +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field sw_rtt_table_addr_1 */ +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__SHIFT 2 +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__WIDTH 3 +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__MASK 0x0000001cU +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) +#define RTT_TABLE_SW_INTF_B1__TYPE u_int32_t +#define RTT_TABLE_SW_INTF_B1__READ 0x0000001fU +#define RTT_TABLE_SW_INTF_B1__WRITE 0x0000001fU + +#endif /* __RTT_TABLE_SW_INTF_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_rtt_table_sw_intf_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_RTT_TABLE_SW_INTF_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_1_b1 */ +#ifndef __RTT_TABLE_SW_INTF_1_B1_MACRO__ +#define __RTT_TABLE_SW_INTF_1_B1_MACRO__ + +/* macros for field sw_rtt_table_data_1 */ +#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__SHIFT 4 +#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__WIDTH 28 +#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__MASK 0xfffffff0U +#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__READ(src) \ + (((u_int32_t)(src)\ + & 0xfffffff0U) >> 4) +#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0xfffffff0U) +#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffffff0U) | (((u_int32_t)(src) <<\ + 4) & 0xfffffff0U) +#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0xfffffff0U))) +#define RTT_TABLE_SW_INTF_1_B1__TYPE u_int32_t +#define RTT_TABLE_SW_INTF_1_B1__READ 0xfffffff0U +#define RTT_TABLE_SW_INTF_1_B1__WRITE 0xfffffff0U + +#endif /* __RTT_TABLE_SW_INTF_1_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_rtt_table_sw_intf_1_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_RTT_TABLE_SW_INTF_1_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b1 */ +#ifndef __TXIQ_CORR_COEFF_01_B1_MACRO__ +#define __TXIQ_CORR_COEFF_01_B1_MACRO__ + +/* macros for field iqc_coeff_table_0_1 */ +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__SHIFT 0 +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_1_1 */ +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__SHIFT 14 +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_01_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_01_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_01_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_01_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_01_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_01_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b1 */ +#ifndef __TXIQ_CORR_COEFF_23_B1_MACRO__ +#define __TXIQ_CORR_COEFF_23_B1_MACRO__ + +/* macros for field iqc_coeff_table_2_1 */ +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__SHIFT 0 +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_3_1 */ +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__SHIFT 14 +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_23_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_23_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_23_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_23_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_23_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_23_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b1 */ +#ifndef __TXIQ_CORR_COEFF_45_B1_MACRO__ +#define __TXIQ_CORR_COEFF_45_B1_MACRO__ + +/* macros for field iqc_coeff_table_4_1 */ +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__SHIFT 0 +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_5_1 */ +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__SHIFT 14 +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_45_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_45_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_45_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_45_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_45_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_45_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b1 */ +#ifndef __TXIQ_CORR_COEFF_67_B1_MACRO__ +#define __TXIQ_CORR_COEFF_67_B1_MACRO__ + +/* macros for field iqc_coeff_table_6_1 */ +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__SHIFT 0 +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_7_1 */ +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__SHIFT 14 +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_67_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_67_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_67_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_67_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_67_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_67_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b1 */ +#ifndef __TXIQ_CORR_COEFF_89_B1_MACRO__ +#define __TXIQ_CORR_COEFF_89_B1_MACRO__ + +/* macros for field iqc_coeff_table_8_1 */ +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__SHIFT 0 +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_9_1 */ +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__SHIFT 14 +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_89_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_89_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_89_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_89_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_89_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_89_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b1 */ +#ifndef __TXIQ_CORR_COEFF_AB_B1_MACRO__ +#define __TXIQ_CORR_COEFF_AB_B1_MACRO__ + +/* macros for field iqc_coeff_table_a_1 */ +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__SHIFT 0 +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_b_1 */ +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__SHIFT 14 +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_AB_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_AB_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_AB_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_AB_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_ab_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b1 */ +#ifndef __TXIQ_CORR_COEFF_CD_B1_MACRO__ +#define __TXIQ_CORR_COEFF_CD_B1_MACRO__ + +/* macros for field iqc_coeff_table_c_1 */ +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__SHIFT 0 +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_d_1 */ +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__SHIFT 14 +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_CD_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_CD_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_CD_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_CD_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_cd_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b1 */ +#ifndef __TXIQ_CORR_COEFF_EF_B1_MACRO__ +#define __TXIQ_CORR_COEFF_EF_B1_MACRO__ + +/* macros for field iqc_coeff_table_e_1 */ +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__SHIFT 0 +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_f_1 */ +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__SHIFT 14 +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_EF_B1__TYPE u_int32_t +#define TXIQ_CORR_COEFF_EF_B1__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_EF_B1__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_EF_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_ef_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_status_b1 */ +#ifndef __TXIQCAL_STATUS_B1_MACRO__ +#define __TXIQCAL_STATUS_B1_MACRO__ + +/* macros for field txiqcal_failed_1 */ +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__SHIFT 0 +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__WIDTH 1 +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__MASK 0x00000001U +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field calibrated_gains_1 */ +#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__SHIFT 1 +#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__WIDTH 5 +#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__MASK 0x0000003eU +#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) + +/* macros for field tone_gain_used_1 */ +#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__SHIFT 6 +#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__WIDTH 6 +#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__MASK 0x00000fc0U +#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) + +/* macros for field rx_gain_used_1 */ +#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__SHIFT 12 +#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__WIDTH 6 +#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__MASK 0x0003f000U +#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) + +/* macros for field last_meas_addr_1 */ +#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__SHIFT 18 +#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__WIDTH 6 +#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__MASK 0x00fc0000U +#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TXIQCAL_STATUS_B1__TYPE u_int32_t +#define TXIQCAL_STATUS_B1__READ 0x00ffffffU + +#endif /* __TXIQCAL_STATUS_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiqcal_status_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQCAL_STATUS_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tables_intf_addr_b1 */ +#ifndef __TABLES_INTF_ADDR_B1_MACRO__ +#define __TABLES_INTF_ADDR_B1_MACRO__ + +/* macros for field tables_addr_1 */ +#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__SHIFT 2 +#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__WIDTH 16 +#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__MASK 0x0003fffcU +#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fffcU) >> 2) +#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0003fffcU) +#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0003fffcU) +#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0003fffcU))) + +/* macros for field addr_auto_incr_1 */ +#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__SHIFT 31 +#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__WIDTH 1 +#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__MASK 0x80000000U +#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TABLES_INTF_ADDR_B1__TYPE u_int32_t +#define TABLES_INTF_ADDR_B1__READ 0x8003fffcU +#define TABLES_INTF_ADDR_B1__WRITE 0x8003fffcU + +#endif /* __TABLES_INTF_ADDR_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_tables_intf_addr_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TABLES_INTF_ADDR_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tables_intf_data_b1 */ +#ifndef __TABLES_INTF_DATA_B1_MACRO__ +#define __TABLES_INTF_DATA_B1_MACRO__ + +/* macros for field tables_data_1 */ +#define TABLES_INTF_DATA_B1__TABLES_DATA_1__SHIFT 0 +#define TABLES_INTF_DATA_B1__TABLES_DATA_1__WIDTH 32 +#define TABLES_INTF_DATA_B1__TABLES_DATA_1__MASK 0xffffffffU +#define TABLES_INTF_DATA_B1__TABLES_DATA_1__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TABLES_INTF_DATA_B1__TABLES_DATA_1__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TABLES_INTF_DATA_B1__TABLES_DATA_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TABLES_INTF_DATA_B1__TABLES_DATA_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TABLES_INTF_DATA_B1__TYPE u_int32_t +#define TABLES_INTF_DATA_B1__READ 0xffffffffU +#define TABLES_INTF_DATA_B1__WRITE 0xffffffffU + +#endif /* __TABLES_INTF_DATA_B1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm1_reg_map.BB_tables_intf_data_b1 */ +#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TABLES_INTF_DATA_B1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b2 */ +#ifndef __EXT_CHAN_PWR_THR_2_B2_MACRO__ +#define __EXT_CHAN_PWR_THR_2_B2_MACRO__ + +/* macros for field cf_maxCCApwr_ext_2 */ +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__SHIFT 0 +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__MASK 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field minCCApwr_ext_2 */ +#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__SHIFT 16 +#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__WIDTH 9 +#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__MASK 0x01ff0000U +#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01ff0000U) >> 16) +#define EXT_CHAN_PWR_THR_2_B2__TYPE u_int32_t +#define EXT_CHAN_PWR_THR_2_B2__READ 0x01ff01ffU +#define EXT_CHAN_PWR_THR_2_B2__WRITE 0x01ff01ffU + +#endif /* __EXT_CHAN_PWR_THR_2_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_ext_chan_pwr_thr_2_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::spur_report_b2 */ +#ifndef __SPUR_REPORT_B2_MACRO__ +#define __SPUR_REPORT_B2_MACRO__ + +/* macros for field spur_est_i_2 */ +#define SPUR_REPORT_B2__SPUR_EST_I_2__SHIFT 0 +#define SPUR_REPORT_B2__SPUR_EST_I_2__WIDTH 8 +#define SPUR_REPORT_B2__SPUR_EST_I_2__MASK 0x000000ffU +#define SPUR_REPORT_B2__SPUR_EST_I_2__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field spur_est_q_2 */ +#define SPUR_REPORT_B2__SPUR_EST_Q_2__SHIFT 8 +#define SPUR_REPORT_B2__SPUR_EST_Q_2__WIDTH 8 +#define SPUR_REPORT_B2__SPUR_EST_Q_2__MASK 0x0000ff00U +#define SPUR_REPORT_B2__SPUR_EST_Q_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field power_with_spur_removed_2 */ +#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__SHIFT 16 +#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__WIDTH 16 +#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__MASK 0xffff0000U +#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__READ(src) \ + (((u_int32_t)(src)\ + & 0xffff0000U) >> 16) +#define SPUR_REPORT_B2__TYPE u_int32_t +#define SPUR_REPORT_B2__READ 0xffffffffU + +#endif /* __SPUR_REPORT_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_spur_report_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_SPUR_REPORT_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b2 */ +#ifndef __IQ_ADC_MEAS_0_B2_MACRO__ +#define __IQ_ADC_MEAS_0_B2_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_0_2 */ +#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__SHIFT 0 +#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__WIDTH 32 +#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__MASK 0xffffffffU +#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_0_B2__TYPE u_int32_t +#define IQ_ADC_MEAS_0_B2__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_0_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_0_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_0_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b2 */ +#ifndef __IQ_ADC_MEAS_1_B2_MACRO__ +#define __IQ_ADC_MEAS_1_B2_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_1_2 */ +#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__SHIFT 0 +#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__WIDTH 32 +#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__MASK 0xffffffffU +#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_1_B2__TYPE u_int32_t +#define IQ_ADC_MEAS_1_B2__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_1_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_1_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_1_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b2 */ +#ifndef __IQ_ADC_MEAS_2_B2_MACRO__ +#define __IQ_ADC_MEAS_2_B2_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_2_2 */ +#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__SHIFT 0 +#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__WIDTH 32 +#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__MASK 0xffffffffU +#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_2_B2__TYPE u_int32_t +#define IQ_ADC_MEAS_2_B2__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_2_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_2_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b2 */ +#ifndef __IQ_ADC_MEAS_3_B2_MACRO__ +#define __IQ_ADC_MEAS_3_B2_MACRO__ + +/* macros for field gain_dc_iq_cal_meas_3_2 */ +#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__SHIFT 0 +#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__WIDTH 32 +#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__MASK 0xffffffffU +#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define IQ_ADC_MEAS_3_B2__TYPE u_int32_t +#define IQ_ADC_MEAS_3_B2__READ 0xffffffffU + +#endif /* __IQ_ADC_MEAS_3_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_3_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_3_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b2 */ +#ifndef __TX_PHASE_RAMP_B2_MACRO__ +#define __TX_PHASE_RAMP_B2_MACRO__ + +/* macros for field cf_phase_ramp_enable_2 */ +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__SHIFT 0 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__WIDTH 1 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__MASK 0x00000001U +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field cf_phase_ramp_bias_2 */ +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__SHIFT 1 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__WIDTH 6 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__MASK 0x0000007eU +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000007eU) >> 1) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000007eU) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000007eU))) + +/* macros for field cf_phase_ramp_init_2 */ +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__SHIFT 7 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__WIDTH 10 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__MASK 0x0001ff80U +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001ff80U) >> 7) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001ff80U) | (((u_int32_t)(src) <<\ + 7) & 0x0001ff80U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x0001ff80U))) + +/* macros for field cf_phase_ramp_alpha_2 */ +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__SHIFT 17 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__WIDTH 8 +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__MASK 0x01fe0000U +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fe0000U) >> 17) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x01fe0000U) +#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x01fe0000U))) +#define TX_PHASE_RAMP_B2__TYPE u_int32_t +#define TX_PHASE_RAMP_B2__READ 0x01ffffffU +#define TX_PHASE_RAMP_B2__WRITE 0x01ffffffU + +#endif /* __TX_PHASE_RAMP_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_tx_phase_ramp_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_TX_PHASE_RAMP_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b2 */ +#ifndef __ADC_GAIN_DC_CORR_B2_MACRO__ +#define __ADC_GAIN_DC_CORR_B2_MACRO__ + +/* macros for field adc_gain_corr_q_coeff_2 */ +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__SHIFT 0 +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__WIDTH 6 +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__MASK 0x0000003fU +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field adc_gain_corr_i_coeff_2 */ +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__SHIFT 6 +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__WIDTH 6 +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__MASK 0x00000fc0U +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field adc_dc_corr_q_coeff_2 */ +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__SHIFT 12 +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__WIDTH 9 +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__MASK 0x001ff000U +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x001ff000U) >> 12) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x001ff000U) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x001ff000U))) + +/* macros for field adc_dc_corr_i_coeff_2 */ +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__SHIFT 21 +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__WIDTH 9 +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__MASK 0x3fe00000U +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x3fe00000U) >> 21) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3fe00000U) | (((u_int32_t)(src) <<\ + 21) & 0x3fe00000U) +#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x3fe00000U))) +#define ADC_GAIN_DC_CORR_B2__TYPE u_int32_t +#define ADC_GAIN_DC_CORR_B2__READ 0x3fffffffU +#define ADC_GAIN_DC_CORR_B2__WRITE 0x3fffffffU + +#endif /* __ADC_GAIN_DC_CORR_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_adc_gain_dc_corr_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_ADC_GAIN_DC_CORR_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b2 */ +#ifndef __RX_IQ_CORR_B2_MACRO__ +#define __RX_IQ_CORR_B2_MACRO__ + +/* macros for field rx_iqcorr_q_q_coff_2 */ +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__SHIFT 0 +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__WIDTH 7 +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__MASK 0x0000007fU +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field rx_iqcorr_q_i_coff_2 */ +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__SHIFT 7 +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__WIDTH 7 +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__MASK 0x00003f80U +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f80U) >> 7) +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00003f80U) +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00003f80U) +#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00003f80U))) + +/* macros for field loopback_iqcorr_q_q_coff_2 */ +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__SHIFT 15 +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__WIDTH 7 +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__MASK 0x003f8000U +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f8000U) >> 15) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x003f8000U) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f8000U) | (((u_int32_t)(src) <<\ + 15) & 0x003f8000U) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x003f8000U))) + +/* macros for field loopback_iqcorr_q_i_coff_2 */ +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__SHIFT 22 +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__WIDTH 7 +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__MASK 0x1fc00000U +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x1fc00000U) >> 22) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x1fc00000U) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x1fc00000U) +#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x1fc00000U))) +#define RX_IQ_CORR_B2__TYPE u_int32_t +#define RX_IQ_CORR_B2__READ 0x1fffbfffU +#define RX_IQ_CORR_B2__WRITE 0x1fffbfffU + +#endif /* __RX_IQ_CORR_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_rx_iq_corr_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_RX_IQ_CORR_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b2 */ +#ifndef __PAPRD_CTRL0_B2_MACRO__ +#define __PAPRD_CTRL0_B2_MACRO__ + +/* macros for field paprd_enable_2 */ +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__SHIFT 0 +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__WIDTH 1 +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__MASK 0x00000001U +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_use_single_table_2 */ +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__SHIFT 1 +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__WIDTH 1 +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__MASK 0x00000002U +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_valid_gain_2 */ +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__SHIFT 2 +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__WIDTH 25 +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__MASK 0x07fffffcU +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fffffcU) >> 2) +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fffffcU) | (((u_int32_t)(src) <<\ + 2) & 0x07fffffcU) +#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x07fffffcU))) + +/* macros for field paprd_mag_thrsh_2 */ +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__SHIFT 27 +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__WIDTH 5 +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__MASK 0xf8000000U +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define PAPRD_CTRL0_B2__TYPE u_int32_t +#define PAPRD_CTRL0_B2__READ 0xffffffffU +#define PAPRD_CTRL0_B2__WRITE 0xffffffffU + +#endif /* __PAPRD_CTRL0_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_ctrl0_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_CTRL0_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b2 */ +#ifndef __PAPRD_CTRL1_B2_MACRO__ +#define __PAPRD_CTRL1_B2_MACRO__ + +/* macros for field paprd_adaptive_scaling_enable_2 */ +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__SHIFT 0 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__WIDTH 1 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__MASK 0x00000001U +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field paprd_adaptive_am2am_enable_2 */ +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__SHIFT 1 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__WIDTH 1 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__MASK 0x00000002U +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field paprd_adaptive_am2pm_enable_2 */ +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__SHIFT 2 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__WIDTH 1 +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__MASK 0x00000004U +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field paprd_power_at_am2am_cal_2 */ +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__SHIFT 3 +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__WIDTH 6 +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__MASK 0x000001f8U +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001f8U) >> 3) +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000001f8U) +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000001f8U) +#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000001f8U))) + +/* macros for field pa_gain_scale_factor_2 */ +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__SHIFT 9 +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__WIDTH 8 +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__MASK 0x0001fe00U +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001fe00U) >> 9) +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001fe00U) | (((u_int32_t)(src) <<\ + 9) & 0x0001fe00U) +#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x0001fe00U))) + +/* macros for field paprd_mag_scale_factor_2 */ +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__SHIFT 17 +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__WIDTH 10 +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__MASK 0x07fe0000U +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fe0000U) >> 17) +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x07fe0000U) +#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x07fe0000U))) + +/* macros for field paprd_trainer_iandq_sel_2 */ +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__SHIFT 27 +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__WIDTH 1 +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__MASK 0x08000000U +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) +#define PAPRD_CTRL1_B2__TYPE u_int32_t +#define PAPRD_CTRL1_B2__READ 0x0fffffffU +#define PAPRD_CTRL1_B2__WRITE 0x0fffffffU + +#endif /* __PAPRD_CTRL1_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_ctrl1_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_CTRL1_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain123_b2 */ +#ifndef __PA_GAIN123_B2_MACRO__ +#define __PA_GAIN123_B2_MACRO__ + +/* macros for field pa_gain1_2 */ +#define PA_GAIN123_B2__PA_GAIN1_2__SHIFT 0 +#define PA_GAIN123_B2__PA_GAIN1_2__WIDTH 10 +#define PA_GAIN123_B2__PA_GAIN1_2__MASK 0x000003ffU +#define PA_GAIN123_B2__PA_GAIN1_2__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN123_B2__PA_GAIN1_2__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN123_B2__PA_GAIN1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN123_B2__PA_GAIN1_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain2_2 */ +#define PA_GAIN123_B2__PA_GAIN2_2__SHIFT 10 +#define PA_GAIN123_B2__PA_GAIN2_2__WIDTH 10 +#define PA_GAIN123_B2__PA_GAIN2_2__MASK 0x000ffc00U +#define PA_GAIN123_B2__PA_GAIN2_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN123_B2__PA_GAIN2_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN123_B2__PA_GAIN2_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN123_B2__PA_GAIN2_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field pa_gain3_2 */ +#define PA_GAIN123_B2__PA_GAIN3_2__SHIFT 20 +#define PA_GAIN123_B2__PA_GAIN3_2__WIDTH 10 +#define PA_GAIN123_B2__PA_GAIN3_2__MASK 0x3ff00000U +#define PA_GAIN123_B2__PA_GAIN3_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x3ff00000U) >> 20) +#define PA_GAIN123_B2__PA_GAIN3_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x3ff00000U) +#define PA_GAIN123_B2__PA_GAIN3_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3ff00000U) | (((u_int32_t)(src) <<\ + 20) & 0x3ff00000U) +#define PA_GAIN123_B2__PA_GAIN3_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x3ff00000U))) +#define PA_GAIN123_B2__TYPE u_int32_t +#define PA_GAIN123_B2__READ 0x3fffffffU +#define PA_GAIN123_B2__WRITE 0x3fffffffU + +#endif /* __PA_GAIN123_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_pa_gain123_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PA_GAIN123_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pa_gain45_b2 */ +#ifndef __PA_GAIN45_B2_MACRO__ +#define __PA_GAIN45_B2_MACRO__ + +/* macros for field pa_gain4_2 */ +#define PA_GAIN45_B2__PA_GAIN4_2__SHIFT 0 +#define PA_GAIN45_B2__PA_GAIN4_2__WIDTH 10 +#define PA_GAIN45_B2__PA_GAIN4_2__MASK 0x000003ffU +#define PA_GAIN45_B2__PA_GAIN4_2__READ(src) (u_int32_t)(src) & 0x000003ffU +#define PA_GAIN45_B2__PA_GAIN4_2__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define PA_GAIN45_B2__PA_GAIN4_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define PA_GAIN45_B2__PA_GAIN4_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field pa_gain5_2 */ +#define PA_GAIN45_B2__PA_GAIN5_2__SHIFT 10 +#define PA_GAIN45_B2__PA_GAIN5_2__WIDTH 10 +#define PA_GAIN45_B2__PA_GAIN5_2__MASK 0x000ffc00U +#define PA_GAIN45_B2__PA_GAIN5_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000ffc00U) >> 10) +#define PA_GAIN45_B2__PA_GAIN5_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x000ffc00U) +#define PA_GAIN45_B2__PA_GAIN5_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000ffc00U) | (((u_int32_t)(src) <<\ + 10) & 0x000ffc00U) +#define PA_GAIN45_B2__PA_GAIN5_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x000ffc00U))) + +/* macros for field paprd_adaptive_table_valid_2 */ +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__SHIFT 20 +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__WIDTH 5 +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__MASK 0x01f00000U +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x01f00000U) +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x01f00000U) +#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x01f00000U))) +#define PA_GAIN45_B2__TYPE u_int32_t +#define PA_GAIN45_B2__READ 0x01ffffffU +#define PA_GAIN45_B2__WRITE 0x01ffffffU + +#endif /* __PA_GAIN45_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_pa_gain45_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PA_GAIN45_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_0_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_0_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_0_2 */ +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_0_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_0_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_0_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_0_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_0_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_1_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_1_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_1_2 */ +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_1_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_1_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_1_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_1_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_1_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_2_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_2_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_2_2 */ +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_2_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_2_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_2_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_2_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_2_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_3_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_3_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_3_2 */ +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_3_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_3_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_3_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_3_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_3_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_4_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_4_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_4_2 */ +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_4_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_4_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_4_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_4_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_4_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_5_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_5_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_5_2 */ +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_5_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_5_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_5_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_5_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_5_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_6_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_6_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_6_2 */ +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_6_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_6_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_6_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_6_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_6_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b2 */ +#ifndef __PAPRD_PRE_POST_SCALE_7_B2_MACRO__ +#define __PAPRD_PRE_POST_SCALE_7_B2_MACRO__ + +/* macros for field paprd_pre_post_scaling_7_2 */ +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__SHIFT 0 +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__WIDTH 18 +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__MASK 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0003ffffU))) +#define PAPRD_PRE_POST_SCALE_7_B2__TYPE u_int32_t +#define PAPRD_PRE_POST_SCALE_7_B2__READ 0x0003ffffU +#define PAPRD_PRE_POST_SCALE_7_B2__WRITE 0x0003ffffU + +#endif /* __PAPRD_PRE_POST_SCALE_7_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_7_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */ +#ifndef __PAPRD_MEM_TAB_MACRO__ +#define __PAPRD_MEM_TAB_MACRO__ + +/* macros for field paprd_mem */ +#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT 0 +#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH 22 +#define PAPRD_MEM_TAB__PAPRD_MEM__MASK 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU +#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003fffffU) | ((u_int32_t)(src) &\ + 0x003fffffU) +#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x003fffffU))) +#define PAPRD_MEM_TAB__TYPE u_int32_t +#define PAPRD_MEM_TAB__READ 0x003fffffU +#define PAPRD_MEM_TAB__WRITE 0x003fffffU + +#endif /* __PAPRD_MEM_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_mem_tab_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_MEM_TAB_B2__NUM 120 + +/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */ +#ifndef __CHAN_INFO_CHAN_TAB_MACRO__ +#define __CHAN_INFO_CHAN_TAB_MACRO__ + +/* macros for field chaninfo_word */ +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT 0 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH 32 +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK 0xffffffffU +#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define CHAN_INFO_CHAN_TAB__TYPE u_int32_t +#define CHAN_INFO_CHAN_TAB__READ 0xffffffffU + +#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_chan_info_chan_tab_b2 */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B2__NUM 60 + +/* macros for BlueprintGlobalNameSpace::chn2_tables_intf_addr */ +#ifndef __CHN2_TABLES_INTF_ADDR_MACRO__ +#define __CHN2_TABLES_INTF_ADDR_MACRO__ + +/* macros for field chn2_tables_addr */ +#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__SHIFT 2 +#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__WIDTH 16 +#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__MASK 0x0003fffcU +#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fffcU) >> 2) +#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0003fffcU) +#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0003fffcU) +#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0003fffcU))) + +/* macros for field chn2_addr_auto_incr */ +#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__SHIFT 31 +#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__WIDTH 1 +#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__MASK 0x80000000U +#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define CHN2_TABLES_INTF_ADDR__TYPE u_int32_t +#define CHN2_TABLES_INTF_ADDR__READ 0x8003fffcU +#define CHN2_TABLES_INTF_ADDR__WRITE 0x8003fffcU + +#endif /* __CHN2_TABLES_INTF_ADDR_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_chn2_tables_intf_addr */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_CHN2_TABLES_INTF_ADDR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::chn2_tables_intf_data */ +#ifndef __CHN2_TABLES_INTF_DATA_MACRO__ +#define __CHN2_TABLES_INTF_DATA_MACRO__ + +/* macros for field chn2_tables_data */ +#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__SHIFT 0 +#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__WIDTH 32 +#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__MASK 0xffffffffU +#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CHN2_TABLES_INTF_DATA__TYPE u_int32_t +#define CHN2_TABLES_INTF_DATA__READ 0xffffffffU +#define CHN2_TABLES_INTF_DATA__WRITE 0xffffffffU + +#endif /* __CHN2_TABLES_INTF_DATA_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn2_reg_map.BB_chn2_tables_intf_data */ +#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_CHN2_TABLES_INTF_DATA__NUM 1 + +/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b2 */ +#ifndef __GAIN_FORCE_MAX_GAINS_B2_MACRO__ +#define __GAIN_FORCE_MAX_GAINS_B2_MACRO__ + +/* macros for field rf_gain_f_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__SHIFT 0 +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__MASK 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field mb_gain_f_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__SHIFT 8 +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__WIDTH 8 +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__MASK 0x0000ff00U +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field xatten1_sw_f_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__SHIFT 16 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__MASK 0x00010000U +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field xatten2_sw_f_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__SHIFT 17 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__WIDTH 1 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__MASK 0x00020000U +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field xatten1_hyst_margin_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__SHIFT 18 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__MASK 0x01fc0000U +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01fc0000U) >> 18) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x01fc0000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x01fc0000U))) + +/* macros for field xatten2_hyst_margin_2 */ +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__SHIFT 25 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__WIDTH 7 +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__MASK 0xfe000000U +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0xfe000000U) >> 25) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfe000000U) | (((u_int32_t)(src) <<\ + 25) & 0xfe000000U) +#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0xfe000000U))) +#define GAIN_FORCE_MAX_GAINS_B2__TYPE u_int32_t +#define GAIN_FORCE_MAX_GAINS_B2__READ 0xffffffffU +#define GAIN_FORCE_MAX_GAINS_B2__WRITE 0xffffffffU + +#endif /* __GAIN_FORCE_MAX_GAINS_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc2_reg_map.BB_gain_force_max_gains_b2 */ +#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b2 */ +#ifndef __EXT_ATTEN_SWITCH_CTL_B2_MACRO__ +#define __EXT_ATTEN_SWITCH_CTL_B2_MACRO__ + +/* macros for field xatten1_db_2 */ +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__SHIFT 0 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__MASK 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__READ(src) \ + (u_int32_t)(src)\ + & 0x0000003fU +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field xatten2_db_2 */ +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__SHIFT 6 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__WIDTH 6 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__MASK 0x00000fc0U +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field xatten1_margin_2 */ +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__SHIFT 12 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__MASK 0x0001f000U +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field xatten2_margin_2 */ +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__SHIFT 17 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__MASK 0x003e0000U +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field xlna_gain_db_2 */ +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__SHIFT 22 +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__WIDTH 5 +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__MASK 0x07c00000U +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) +#define EXT_ATTEN_SWITCH_CTL_B2__TYPE u_int32_t +#define EXT_ATTEN_SWITCH_CTL_B2__READ 0x07ffffffU +#define EXT_ATTEN_SWITCH_CTL_B2__WRITE 0x07ffffffU + +#endif /* __EXT_ATTEN_SWITCH_CTL_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc2_reg_map.BB_ext_atten_switch_ctl_b2 */ +#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_b2 */ +#ifndef __CCA_B2_MACRO__ +#define __CCA_B2_MACRO__ + +/* macros for field cf_maxCCApwr_2 */ +#define CCA_B2__CF_MAXCCAPWR_2__SHIFT 0 +#define CCA_B2__CF_MAXCCAPWR_2__WIDTH 9 +#define CCA_B2__CF_MAXCCAPWR_2__MASK 0x000001ffU +#define CCA_B2__CF_MAXCCAPWR_2__READ(src) (u_int32_t)(src) & 0x000001ffU +#define CCA_B2__CF_MAXCCAPWR_2__WRITE(src) ((u_int32_t)(src) & 0x000001ffU) +#define CCA_B2__CF_MAXCCAPWR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_B2__CF_MAXCCAPWR_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field minCCApwr_2 */ +#define CCA_B2__MINCCAPWR_2__SHIFT 20 +#define CCA_B2__MINCCAPWR_2__WIDTH 9 +#define CCA_B2__MINCCAPWR_2__MASK 0x1ff00000U +#define CCA_B2__MINCCAPWR_2__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20) +#define CCA_B2__TYPE u_int32_t +#define CCA_B2__READ 0x1ff001ffU +#define CCA_B2__WRITE 0x1ff001ffU + +#endif /* __CCA_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc2_reg_map.BB_cca_b2 */ +#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_CCA_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b2 */ +#ifndef __CCA_CTRL_2_B2_MACRO__ +#define __CCA_CTRL_2_B2_MACRO__ + +/* macros for field minCCApwr_thr_2 */ +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__SHIFT 0 +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__WIDTH 9 +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__MASK 0x000001ffU +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000001ffU) +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001ffU) | ((u_int32_t)(src) &\ + 0x000001ffU) +#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000001ffU))) + +/* macros for field NF_gain_comp_2 */ +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__SHIFT 10 +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__WIDTH 8 +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__MASK 0x0003fc00U +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fc00U) >> 10) +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0003fc00U) +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0003fc00U) +#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0003fc00U))) +#define CCA_CTRL_2_B2__TYPE u_int32_t +#define CCA_CTRL_2_B2__READ 0x0003fdffU +#define CCA_CTRL_2_B2__WRITE 0x0003fdffU + +#endif /* __CCA_CTRL_2_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc2_reg_map.BB_cca_ctrl_2_b2 */ +#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_CCA_CTRL_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rssi_b2 */ +#ifndef __RSSI_B2_MACRO__ +#define __RSSI_B2_MACRO__ + +/* macros for field rssi_2 */ +#define RSSI_B2__RSSI_2__SHIFT 0 +#define RSSI_B2__RSSI_2__WIDTH 8 +#define RSSI_B2__RSSI_2__MASK 0x000000ffU +#define RSSI_B2__RSSI_2__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field rssi_ext_2 */ +#define RSSI_B2__RSSI_EXT_2__SHIFT 8 +#define RSSI_B2__RSSI_EXT_2__WIDTH 8 +#define RSSI_B2__RSSI_EXT_2__MASK 0x0000ff00U +#define RSSI_B2__RSSI_EXT_2__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define RSSI_B2__TYPE u_int32_t +#define RSSI_B2__READ 0x0000ffffU + +#endif /* __RSSI_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc2_reg_map.BB_rssi_b2 */ +#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_RSSI_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b2 */ +#ifndef __AGC_DIG_DC_STATUS_I_B2_MACRO__ +#define __AGC_DIG_DC_STATUS_I_B2_MACRO__ + +/* macros for field dig_dc_C1_res_i_2 */ +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__SHIFT 0 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_i_2 */ +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__SHIFT 9 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_i_2 */ +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__SHIFT 18 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_I_B2__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_I_B2__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_I_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc2_reg_map.BB_agc_dig_dc_status_i_b2 */ +#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b2 */ +#ifndef __AGC_DIG_DC_STATUS_Q_B2_MACRO__ +#define __AGC_DIG_DC_STATUS_Q_B2_MACRO__ + +/* macros for field dig_dc_C1_res_q_2 */ +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__SHIFT 0 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__MASK 0x000001ffU +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000001ffU + +/* macros for field dig_dc_C2_res_q_2 */ +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__SHIFT 9 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__MASK 0x0003fe00U +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fe00U) >> 9) + +/* macros for field dig_dc_C3_res_q_2 */ +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__SHIFT 18 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__WIDTH 9 +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__MASK 0x07fc0000U +#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x07fc0000U) >> 18) +#define AGC_DIG_DC_STATUS_Q_B2__TYPE u_int32_t +#define AGC_DIG_DC_STATUS_Q_B2__READ 0x07ffffffU + +#endif /* __AGC_DIG_DC_STATUS_Q_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc2_reg_map.BB_agc_dig_dc_status_q_b2 */ +#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dc_cal_status_b2 */ +#ifndef __DC_CAL_STATUS_B2_MACRO__ +#define __DC_CAL_STATUS_B2_MACRO__ + +/* macros for field offsetC1I_2 */ +#define DC_CAL_STATUS_B2__OFFSETC1I_2__SHIFT 0 +#define DC_CAL_STATUS_B2__OFFSETC1I_2__WIDTH 5 +#define DC_CAL_STATUS_B2__OFFSETC1I_2__MASK 0x0000001fU +#define DC_CAL_STATUS_B2__OFFSETC1I_2__READ(src) (u_int32_t)(src) & 0x0000001fU + +/* macros for field offsetC1Q_2 */ +#define DC_CAL_STATUS_B2__OFFSETC1Q_2__SHIFT 5 +#define DC_CAL_STATUS_B2__OFFSETC1Q_2__WIDTH 5 +#define DC_CAL_STATUS_B2__OFFSETC1Q_2__MASK 0x000003e0U +#define DC_CAL_STATUS_B2__OFFSETC1Q_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003e0U) >> 5) + +/* macros for field offsetC2I_2 */ +#define DC_CAL_STATUS_B2__OFFSETC2I_2__SHIFT 10 +#define DC_CAL_STATUS_B2__OFFSETC2I_2__WIDTH 5 +#define DC_CAL_STATUS_B2__OFFSETC2I_2__MASK 0x00007c00U +#define DC_CAL_STATUS_B2__OFFSETC2I_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007c00U) >> 10) + +/* macros for field offsetC2Q_2 */ +#define DC_CAL_STATUS_B2__OFFSETC2Q_2__SHIFT 15 +#define DC_CAL_STATUS_B2__OFFSETC2Q_2__WIDTH 5 +#define DC_CAL_STATUS_B2__OFFSETC2Q_2__MASK 0x000f8000U +#define DC_CAL_STATUS_B2__OFFSETC2Q_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f8000U) >> 15) + +/* macros for field offsetC3I_2 */ +#define DC_CAL_STATUS_B2__OFFSETC3I_2__SHIFT 20 +#define DC_CAL_STATUS_B2__OFFSETC3I_2__WIDTH 5 +#define DC_CAL_STATUS_B2__OFFSETC3I_2__MASK 0x01f00000U +#define DC_CAL_STATUS_B2__OFFSETC3I_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) + +/* macros for field offsetC3Q_2 */ +#define DC_CAL_STATUS_B2__OFFSETC3Q_2__SHIFT 25 +#define DC_CAL_STATUS_B2__OFFSETC3Q_2__WIDTH 5 +#define DC_CAL_STATUS_B2__OFFSETC3Q_2__MASK 0x3e000000U +#define DC_CAL_STATUS_B2__OFFSETC3Q_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x3e000000U) >> 25) +#define DC_CAL_STATUS_B2__TYPE u_int32_t +#define DC_CAL_STATUS_B2__READ 0x3fffffffU + +#endif /* __DC_CAL_STATUS_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc2_reg_map.BB_dc_cal_status_b2 */ +#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_DC_CAL_STATUS_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::switch_table_chn_b2 */ +#ifndef __SWITCH_TABLE_CHN_B2_MACRO__ +#define __SWITCH_TABLE_CHN_B2_MACRO__ + +/* macros for field switch_table_idle_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__SHIFT 0 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__MASK 0x00000003U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field switch_table_t_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__SHIFT 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__MASK 0x0000000cU +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field switch_table_r_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__SHIFT 4 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__MASK 0x00000030U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field switch_table_rx1_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__SHIFT 6 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__MASK 0x000000c0U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field switch_table_rx12_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__SHIFT 8 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__MASK 0x00000300U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field switch_table_b_2 */ +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__SHIFT 10 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__WIDTH 2 +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__MASK 0x00000c00U +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000c00U) >> 10) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00000c00U) +#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000c00U))) +#define SWITCH_TABLE_CHN_B2__TYPE u_int32_t +#define SWITCH_TABLE_CHN_B2__READ 0x00000fffU +#define SWITCH_TABLE_CHN_B2__WRITE 0x00000fffU + +#endif /* __SWITCH_TABLE_CHN_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_switch_table_chn_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_SWITCH_TABLE_CHN_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::fcal_2_b2 */ +#ifndef __FCAL_2_B2_MACRO__ +#define __FCAL_2_B2_MACRO__ + +/* macros for field flc_sw_cap_val_2 */ +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__SHIFT 3 +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__WIDTH 5 +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__MASK 0x000000f8U +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f8U) >> 3) +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x000000f8U) +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f8U) | (((u_int32_t)(src) <<\ + 3) & 0x000000f8U) +#define FCAL_2_B2__FLC_SW_CAP_VAL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x000000f8U))) + +/* macros for field flc_cap_val_status_2 */ +#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__SHIFT 20 +#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__WIDTH 5 +#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__MASK 0x01f00000U +#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define FCAL_2_B2__TYPE u_int32_t +#define FCAL_2_B2__READ 0x01f000f8U +#define FCAL_2_B2__WRITE 0x01f000f8U + +#endif /* __FCAL_2_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_fcal_2_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_FCAL_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b2 */ +#ifndef __DFT_TONE_CTRL_B2_MACRO__ +#define __DFT_TONE_CTRL_B2_MACRO__ + +/* macros for field dft_tone_en_2 */ +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__SHIFT 0 +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__WIDTH 1 +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__MASK 0x00000001U +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field dft_tone_amp_sel_2 */ +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__SHIFT 2 +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__WIDTH 2 +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__MASK 0x0000000cU +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field dft_tone_freq_ang_2 */ +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__SHIFT 4 +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__WIDTH 9 +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__MASK 0x00001ff0U +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001ff0U) >> 4) +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001ff0U) | (((u_int32_t)(src) <<\ + 4) & 0x00001ff0U) +#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00001ff0U))) +#define DFT_TONE_CTRL_B2__TYPE u_int32_t +#define DFT_TONE_CTRL_B2__READ 0x00001ffdU +#define DFT_TONE_CTRL_B2__WRITE 0x00001ffdU + +#endif /* __DFT_TONE_CTRL_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_dft_tone_ctrl_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_DFT_TONE_CTRL_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_0 */ +#ifndef __CL_MAP_0_MACRO__ +#define __CL_MAP_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_0__TYPE u_int32_t +#define CL_MAP_0__READ 0xffffffffU +#define CL_MAP_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_0_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_0_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_1 */ +#ifndef __CL_MAP_1_MACRO__ +#define __CL_MAP_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_1__TYPE u_int32_t +#define CL_MAP_1__READ 0xffffffffU +#define CL_MAP_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_1_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_1_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_2 */ +#ifndef __CL_MAP_2_MACRO__ +#define __CL_MAP_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_2__TYPE u_int32_t +#define CL_MAP_2__READ 0xffffffffU +#define CL_MAP_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_2_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_3 */ +#ifndef __CL_MAP_3_MACRO__ +#define __CL_MAP_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CL_MAP_3__TYPE u_int32_t +#define CL_MAP_3__READ 0xffffffffU +#define CL_MAP_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_3_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_3_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */ +#ifndef __CL_MAP_PAL_0_MACRO__ +#define __CL_MAP_PAL_0_MACRO__ + +/* macros for field cl_map_0 */ +#define CL_MAP_PAL_0__CL_MAP_0__SHIFT 0 +#define CL_MAP_PAL_0__CL_MAP_0__WIDTH 32 +#define CL_MAP_PAL_0__CL_MAP_0__MASK 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_0__TYPE u_int32_t +#define CL_MAP_PAL_0__READ 0xffffffffU +#define CL_MAP_PAL_0__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_0_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_0_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_0_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */ +#ifndef __CL_MAP_PAL_1_MACRO__ +#define __CL_MAP_PAL_1_MACRO__ + +/* macros for field cl_map_1 */ +#define CL_MAP_PAL_1__CL_MAP_1__SHIFT 0 +#define CL_MAP_PAL_1__CL_MAP_1__WIDTH 32 +#define CL_MAP_PAL_1__CL_MAP_1__MASK 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_1__TYPE u_int32_t +#define CL_MAP_PAL_1__READ 0xffffffffU +#define CL_MAP_PAL_1__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_1_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_1_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_1_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */ +#ifndef __CL_MAP_PAL_2_MACRO__ +#define __CL_MAP_PAL_2_MACRO__ + +/* macros for field cl_map_2 */ +#define CL_MAP_PAL_2__CL_MAP_2__SHIFT 0 +#define CL_MAP_PAL_2__CL_MAP_2__WIDTH 32 +#define CL_MAP_PAL_2__CL_MAP_2__MASK 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_2__TYPE u_int32_t +#define CL_MAP_PAL_2__READ 0xffffffffU +#define CL_MAP_PAL_2__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_2_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_2_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */ +#ifndef __CL_MAP_PAL_3_MACRO__ +#define __CL_MAP_PAL_3_MACRO__ + +/* macros for field cl_map_3 */ +#define CL_MAP_PAL_3__CL_MAP_3__SHIFT 0 +#define CL_MAP_PAL_3__CL_MAP_3__WIDTH 32 +#define CL_MAP_PAL_3__CL_MAP_3__MASK 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CL_MAP_PAL_3__TYPE u_int32_t +#define CL_MAP_PAL_3__READ 0xffffffffU +#define CL_MAP_PAL_3__WRITE 0xffffffffU + +#endif /* __CL_MAP_PAL_3_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_3_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_3_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cl_tab */ +#ifndef __CL_TAB_MACRO__ +#define __CL_TAB_MACRO__ + +/* macros for field cl_gain_mod */ +#define CL_TAB__CL_GAIN_MOD__SHIFT 0 +#define CL_TAB__CL_GAIN_MOD__WIDTH 5 +#define CL_TAB__CL_GAIN_MOD__MASK 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU +#define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field carr_lk_dc_add_Q */ +#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT 5 +#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_Q__MASK 0x0000ffe0U +#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ffe0U) >> 5) +#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffe0U) | (((u_int32_t)(src) <<\ + 5) & 0x0000ffe0U) +#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x0000ffe0U))) + +/* macros for field carr_lk_dc_add_I */ +#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT 16 +#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH 11 +#define CL_TAB__CARR_LK_DC_ADD_I__MASK 0x07ff0000U +#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) + +/* macros for field bb_gain */ +#define CL_TAB__BB_GAIN__SHIFT 27 +#define CL_TAB__BB_GAIN__WIDTH 4 +#define CL_TAB__BB_GAIN__MASK 0x78000000U +#define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define CL_TAB__BB_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) +#define CL_TAB__TYPE u_int32_t +#define CL_TAB__READ 0x7fffffffU +#define CL_TAB__WRITE 0x7fffffffU + +#endif /* __CL_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_tab_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_TAB_B2__NUM 16 + +/* macros for BlueprintGlobalNameSpace::chan_info_gain_b2 */ +#ifndef __CHAN_INFO_GAIN_B2_MACRO__ +#define __CHAN_INFO_GAIN_B2_MACRO__ + +/* macros for field chan_info_rssi_2 */ +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__SHIFT 0 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__WIDTH 8 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__MASK 0x000000ffU +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__READ(src) \ + (u_int32_t)(src)\ + & 0x000000ffU + +/* macros for field chan_info_rf_gain_2 */ +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__SHIFT 8 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__WIDTH 8 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__MASK 0x0000ff00U +#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) + +/* macros for field chan_info_mb_gain_2 */ +#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__SHIFT 16 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__WIDTH 7 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__MASK 0x007f0000U +#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) + +/* macros for field chan_info_xatten1_sw_2 */ +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__SHIFT 23 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__WIDTH 1 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__MASK 0x00800000U +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field chan_info_xatten2_sw_2 */ +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__SHIFT 24 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__WIDTH 1 +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__MASK 0x01000000U +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define CHAN_INFO_GAIN_B2__TYPE u_int32_t +#define CHAN_INFO_GAIN_B2__READ 0x01ffffffU + +#endif /* __CHAN_INFO_GAIN_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_chan_info_gain_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CHAN_INFO_GAIN_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_4_b2 */ +#ifndef __TPC_4_B2_MACRO__ +#define __TPC_4_B2_MACRO__ + +/* macros for field pd_avg_valid_2 */ +#define TPC_4_B2__PD_AVG_VALID_2__SHIFT 0 +#define TPC_4_B2__PD_AVG_VALID_2__WIDTH 1 +#define TPC_4_B2__PD_AVG_VALID_2__MASK 0x00000001U +#define TPC_4_B2__PD_AVG_VALID_2__READ(src) (u_int32_t)(src) & 0x00000001U +#define TPC_4_B2__PD_AVG_VALID_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TPC_4_B2__PD_AVG_VALID_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field pd_avg_out_2 */ +#define TPC_4_B2__PD_AVG_OUT_2__SHIFT 1 +#define TPC_4_B2__PD_AVG_OUT_2__WIDTH 8 +#define TPC_4_B2__PD_AVG_OUT_2__MASK 0x000001feU +#define TPC_4_B2__PD_AVG_OUT_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) + +/* macros for field dac_gain_2 */ +#define TPC_4_B2__DAC_GAIN_2__SHIFT 9 +#define TPC_4_B2__DAC_GAIN_2__WIDTH 5 +#define TPC_4_B2__DAC_GAIN_2__MASK 0x00003e00U +#define TPC_4_B2__DAC_GAIN_2__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9) + +/* macros for field tx_gain_setting_2 */ +#define TPC_4_B2__TX_GAIN_SETTING_2__SHIFT 14 +#define TPC_4_B2__TX_GAIN_SETTING_2__WIDTH 6 +#define TPC_4_B2__TX_GAIN_SETTING_2__MASK 0x000fc000U +#define TPC_4_B2__TX_GAIN_SETTING_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000fc000U) >> 14) + +/* macros for field rate_sent_2 */ +#define TPC_4_B2__RATE_SENT_2__SHIFT 20 +#define TPC_4_B2__RATE_SENT_2__WIDTH 5 +#define TPC_4_B2__RATE_SENT_2__MASK 0x01f00000U +#define TPC_4_B2__RATE_SENT_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f00000U) >> 20) +#define TPC_4_B2__TYPE u_int32_t +#define TPC_4_B2__READ 0x01ffffffU + +#endif /* __TPC_4_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_4_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_4_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_5_b2 */ +#ifndef __TPC_5_B2_MACRO__ +#define __TPC_5_B2_MACRO__ + +/* macros for field pd_gain_boundary_1_2 */ +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__SHIFT 4 +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__WIDTH 6 +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__MASK 0x000003f0U +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000003f0U) >> 4) +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000003f0U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000003f0U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000003f0U))) + +/* macros for field pd_gain_boundary_2_2 */ +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__SHIFT 10 +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__WIDTH 6 +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__MASK 0x0000fc00U +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000fc00U) >> 10) +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x0000fc00U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000fc00U) | (((u_int32_t)(src) <<\ + 10) & 0x0000fc00U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x0000fc00U))) + +/* macros for field pd_gain_boundary_3_2 */ +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__SHIFT 16 +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__WIDTH 6 +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__MASK 0x003f0000U +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x003f0000U) >> 16) +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x003f0000U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x003f0000U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x003f0000U))) + +/* macros for field pd_gain_boundary_4_2 */ +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__SHIFT 22 +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__WIDTH 6 +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__MASK 0x0fc00000U +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fc00000U) >> 22) +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x0fc00000U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x0fc00000U) +#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x0fc00000U))) +#define TPC_5_B2__TYPE u_int32_t +#define TPC_5_B2__READ 0x0ffffff0U +#define TPC_5_B2__WRITE 0x0ffffff0U + +#endif /* __TPC_5_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_5_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_5_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_6_b2 */ +#ifndef __TPC_6_B2_MACRO__ +#define __TPC_6_B2_MACRO__ + +/* macros for field pd_dac_setting_1_2 */ +#define TPC_6_B2__PD_DAC_SETTING_1_2__SHIFT 0 +#define TPC_6_B2__PD_DAC_SETTING_1_2__WIDTH 6 +#define TPC_6_B2__PD_DAC_SETTING_1_2__MASK 0x0000003fU +#define TPC_6_B2__PD_DAC_SETTING_1_2__READ(src) (u_int32_t)(src) & 0x0000003fU +#define TPC_6_B2__PD_DAC_SETTING_1_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000003fU) +#define TPC_6_B2__PD_DAC_SETTING_1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define TPC_6_B2__PD_DAC_SETTING_1_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field pd_dac_setting_2_2 */ +#define TPC_6_B2__PD_DAC_SETTING_2_2__SHIFT 6 +#define TPC_6_B2__PD_DAC_SETTING_2_2__WIDTH 6 +#define TPC_6_B2__PD_DAC_SETTING_2_2__MASK 0x00000fc0U +#define TPC_6_B2__PD_DAC_SETTING_2_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) +#define TPC_6_B2__PD_DAC_SETTING_2_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define TPC_6_B2__PD_DAC_SETTING_2_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define TPC_6_B2__PD_DAC_SETTING_2_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field pd_dac_setting_3_2 */ +#define TPC_6_B2__PD_DAC_SETTING_3_2__SHIFT 12 +#define TPC_6_B2__PD_DAC_SETTING_3_2__WIDTH 6 +#define TPC_6_B2__PD_DAC_SETTING_3_2__MASK 0x0003f000U +#define TPC_6_B2__PD_DAC_SETTING_3_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define TPC_6_B2__PD_DAC_SETTING_3_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define TPC_6_B2__PD_DAC_SETTING_3_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define TPC_6_B2__PD_DAC_SETTING_3_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field pd_dac_setting_4_2 */ +#define TPC_6_B2__PD_DAC_SETTING_4_2__SHIFT 18 +#define TPC_6_B2__PD_DAC_SETTING_4_2__WIDTH 6 +#define TPC_6_B2__PD_DAC_SETTING_4_2__MASK 0x00fc0000U +#define TPC_6_B2__PD_DAC_SETTING_4_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TPC_6_B2__PD_DAC_SETTING_4_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00fc0000U) +#define TPC_6_B2__PD_DAC_SETTING_4_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define TPC_6_B2__PD_DAC_SETTING_4_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field error_est_mode */ +#define TPC_6_B2__ERROR_EST_MODE__SHIFT 24 +#define TPC_6_B2__ERROR_EST_MODE__WIDTH 2 +#define TPC_6_B2__ERROR_EST_MODE__MASK 0x03000000U +#define TPC_6_B2__ERROR_EST_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x03000000U) >> 24) +#define TPC_6_B2__ERROR_EST_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x03000000U) +#define TPC_6_B2__ERROR_EST_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define TPC_6_B2__ERROR_EST_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field error_est_filter_coeff */ +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__SHIFT 26 +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__WIDTH 3 +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__MASK 0x1c000000U +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TPC_6_B2__ERROR_EST_FILTER_COEFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) +#define TPC_6_B2__TYPE u_int32_t +#define TPC_6_B2__READ 0x1fffffffU +#define TPC_6_B2__WRITE 0x1fffffffU + +#endif /* __TPC_6_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_6_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_6_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_11_b2 */ +#ifndef __TPC_11_B2_MACRO__ +#define __TPC_11_B2_MACRO__ + +/* macros for field olpc_gain_delta_2 */ +#define TPC_11_B2__OLPC_GAIN_DELTA_2__SHIFT 16 +#define TPC_11_B2__OLPC_GAIN_DELTA_2__WIDTH 8 +#define TPC_11_B2__OLPC_GAIN_DELTA_2__MASK 0x00ff0000U +#define TPC_11_B2__OLPC_GAIN_DELTA_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TPC_11_B2__OLPC_GAIN_DELTA_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TPC_11_B2__OLPC_GAIN_DELTA_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TPC_11_B2__OLPC_GAIN_DELTA_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field olpc_gain_delta_2_pal_on */ +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__SHIFT 24 +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__WIDTH 8 +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__MASK 0xff000000U +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0xff000000U) >> 24) +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0xff000000U) +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define TPC_11_B2__TYPE u_int32_t +#define TPC_11_B2__READ 0xffff0000U +#define TPC_11_B2__WRITE 0xffff0000U + +#endif /* __TPC_11_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_11_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_11_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tpc_19_b2 */ +#ifndef __TPC_19_B2_MACRO__ +#define __TPC_19_B2_MACRO__ + +/* macros for field alpha_therm_2 */ +#define TPC_19_B2__ALPHA_THERM_2__SHIFT 0 +#define TPC_19_B2__ALPHA_THERM_2__WIDTH 8 +#define TPC_19_B2__ALPHA_THERM_2__MASK 0x000000ffU +#define TPC_19_B2__ALPHA_THERM_2__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TPC_19_B2__ALPHA_THERM_2__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define TPC_19_B2__ALPHA_THERM_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TPC_19_B2__ALPHA_THERM_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000000ffU))) + +/* macros for field alpha_therm_pal_on_2 */ +#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__SHIFT 8 +#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__WIDTH 8 +#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__MASK 0x0000ff00U +#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000ff00U) >> 8) +#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) + +/* macros for field alpha_volt_2 */ +#define TPC_19_B2__ALPHA_VOLT_2__SHIFT 16 +#define TPC_19_B2__ALPHA_VOLT_2__WIDTH 7 +#define TPC_19_B2__ALPHA_VOLT_2__MASK 0x007f0000U +#define TPC_19_B2__ALPHA_VOLT_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x007f0000U) >> 16) +#define TPC_19_B2__ALPHA_VOLT_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x007f0000U) +#define TPC_19_B2__ALPHA_VOLT_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x007f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x007f0000U) +#define TPC_19_B2__ALPHA_VOLT_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x007f0000U))) + +/* macros for field alpha_volt_pal_on_2 */ +#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__SHIFT 23 +#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__WIDTH 7 +#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__MASK 0x3f800000U +#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f800000U) >> 23) +#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x3f800000U) +#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x3f800000U) +#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x3f800000U))) +#define TPC_19_B2__TYPE u_int32_t +#define TPC_19_B2__READ 0x3fffffffU +#define TPC_19_B2__WRITE 0x3fffffffU + +#endif /* __TPC_19_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_19_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_19_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::pdadc_tab */ +#ifndef __PDADC_TAB_MACRO__ +#define __PDADC_TAB_MACRO__ + +/* macros for field tab_entry */ +#define PDADC_TAB__TAB_ENTRY__SHIFT 0 +#define PDADC_TAB__TAB_ENTRY__WIDTH 32 +#define PDADC_TAB__TAB_ENTRY__MASK 0xffffffffU +#define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define PDADC_TAB__TYPE u_int32_t +#define PDADC_TAB__WRITE 0x00000000U + +#endif /* __PDADC_TAB_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_pdadc_tab_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_PDADC_TAB_B2__NUM 32 + +/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_b2 */ +#ifndef __RTT_TABLE_SW_INTF_B2_MACRO__ +#define __RTT_TABLE_SW_INTF_B2_MACRO__ + +/* macros for field sw_rtt_table_access_2 */ +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__SHIFT 0 +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__WIDTH 1 +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__MASK 0x00000001U +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field sw_rtt_table_write_2 */ +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__SHIFT 1 +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__WIDTH 1 +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__MASK 0x00000002U +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field sw_rtt_table_addr_2 */ +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__SHIFT 2 +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__WIDTH 3 +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__MASK 0x0000001cU +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) +#define RTT_TABLE_SW_INTF_B2__TYPE u_int32_t +#define RTT_TABLE_SW_INTF_B2__READ 0x0000001fU +#define RTT_TABLE_SW_INTF_B2__WRITE 0x0000001fU + +#endif /* __RTT_TABLE_SW_INTF_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_rtt_table_sw_intf_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_RTT_TABLE_SW_INTF_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_1_b2 */ +#ifndef __RTT_TABLE_SW_INTF_1_B2_MACRO__ +#define __RTT_TABLE_SW_INTF_1_B2_MACRO__ + +/* macros for field sw_rtt_table_data_2 */ +#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__SHIFT 4 +#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__WIDTH 28 +#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__MASK 0xfffffff0U +#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__READ(src) \ + (((u_int32_t)(src)\ + & 0xfffffff0U) >> 4) +#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0xfffffff0U) +#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xfffffff0U) | (((u_int32_t)(src) <<\ + 4) & 0xfffffff0U) +#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0xfffffff0U))) +#define RTT_TABLE_SW_INTF_1_B2__TYPE u_int32_t +#define RTT_TABLE_SW_INTF_1_B2__READ 0xfffffff0U +#define RTT_TABLE_SW_INTF_1_B2__WRITE 0xfffffff0U + +#endif /* __RTT_TABLE_SW_INTF_1_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_rtt_table_sw_intf_1_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_RTT_TABLE_SW_INTF_1_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b2 */ +#ifndef __TXIQ_CORR_COEFF_01_B2_MACRO__ +#define __TXIQ_CORR_COEFF_01_B2_MACRO__ + +/* macros for field iqc_coeff_table_0_2 */ +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__SHIFT 0 +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_1_2 */ +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__SHIFT 14 +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__WIDTH 14 +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_01_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_01_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_01_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_01_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_01_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_01_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b2 */ +#ifndef __TXIQ_CORR_COEFF_23_B2_MACRO__ +#define __TXIQ_CORR_COEFF_23_B2_MACRO__ + +/* macros for field iqc_coeff_table_2_2 */ +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__SHIFT 0 +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_3_2 */ +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__SHIFT 14 +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__WIDTH 14 +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_23_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_23_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_23_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_23_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_23_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_23_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b2 */ +#ifndef __TXIQ_CORR_COEFF_45_B2_MACRO__ +#define __TXIQ_CORR_COEFF_45_B2_MACRO__ + +/* macros for field iqc_coeff_table_4_2 */ +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__SHIFT 0 +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_5_2 */ +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__SHIFT 14 +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__WIDTH 14 +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_45_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_45_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_45_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_45_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_45_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_45_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b2 */ +#ifndef __TXIQ_CORR_COEFF_67_B2_MACRO__ +#define __TXIQ_CORR_COEFF_67_B2_MACRO__ + +/* macros for field iqc_coeff_table_6_2 */ +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__SHIFT 0 +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_7_2 */ +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__SHIFT 14 +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__WIDTH 14 +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_67_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_67_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_67_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_67_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_67_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_67_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b2 */ +#ifndef __TXIQ_CORR_COEFF_89_B2_MACRO__ +#define __TXIQ_CORR_COEFF_89_B2_MACRO__ + +/* macros for field iqc_coeff_table_8_2 */ +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__SHIFT 0 +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_9_2 */ +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__SHIFT 14 +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__WIDTH 14 +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_89_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_89_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_89_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_89_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_89_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_89_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b2 */ +#ifndef __TXIQ_CORR_COEFF_AB_B2_MACRO__ +#define __TXIQ_CORR_COEFF_AB_B2_MACRO__ + +/* macros for field iqc_coeff_table_a_2 */ +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__SHIFT 0 +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_b_2 */ +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__SHIFT 14 +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__WIDTH 14 +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_AB_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_AB_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_AB_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_AB_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_ab_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b2 */ +#ifndef __TXIQ_CORR_COEFF_CD_B2_MACRO__ +#define __TXIQ_CORR_COEFF_CD_B2_MACRO__ + +/* macros for field iqc_coeff_table_c_2 */ +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__SHIFT 0 +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_d_2 */ +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__SHIFT 14 +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__WIDTH 14 +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_CD_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_CD_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_CD_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_CD_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_cd_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b2 */ +#ifndef __TXIQ_CORR_COEFF_EF_B2_MACRO__ +#define __TXIQ_CORR_COEFF_EF_B2_MACRO__ + +/* macros for field iqc_coeff_table_e_2 */ +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__SHIFT 0 +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__MASK 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00003fffU +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00003fffU))) + +/* macros for field iqc_coeff_table_f_2 */ +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__SHIFT 14 +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__WIDTH 14 +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__MASK 0x0fffc000U +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0fffc000U) >> 14) +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fffc000U) | (((u_int32_t)(src) <<\ + 14) & 0x0fffc000U) +#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0fffc000U))) +#define TXIQ_CORR_COEFF_EF_B2__TYPE u_int32_t +#define TXIQ_CORR_COEFF_EF_B2__READ 0x0fffffffU +#define TXIQ_CORR_COEFF_EF_B2__WRITE 0x0fffffffU + +#endif /* __TXIQ_CORR_COEFF_EF_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_ef_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::txiqcal_status_b2 */ +#ifndef __TXIQCAL_STATUS_B2_MACRO__ +#define __TXIQCAL_STATUS_B2_MACRO__ + +/* macros for field txiqcal_failed_2 */ +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__SHIFT 0 +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__WIDTH 1 +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__MASK 0x00000001U +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field calibrated_gains_2 */ +#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__SHIFT 1 +#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__WIDTH 5 +#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__MASK 0x0000003eU +#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000003eU) >> 1) + +/* macros for field tone_gain_used_2 */ +#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__SHIFT 6 +#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__WIDTH 6 +#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__MASK 0x00000fc0U +#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000fc0U) >> 6) + +/* macros for field rx_gain_used_2 */ +#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__SHIFT 12 +#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__WIDTH 6 +#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__MASK 0x0003f000U +#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) + +/* macros for field last_meas_addr_2 */ +#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__SHIFT 18 +#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__WIDTH 6 +#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__MASK 0x00fc0000U +#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fc0000U) >> 18) +#define TXIQCAL_STATUS_B2__TYPE u_int32_t +#define TXIQCAL_STATUS_B2__READ 0x00ffffffU + +#endif /* __TXIQCAL_STATUS_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiqcal_status_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQCAL_STATUS_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tables_intf_addr_b2 */ +#ifndef __TABLES_INTF_ADDR_B2_MACRO__ +#define __TABLES_INTF_ADDR_B2_MACRO__ + +/* macros for field tables_addr_2 */ +#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__SHIFT 2 +#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__WIDTH 16 +#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__MASK 0x0003fffcU +#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fffcU) >> 2) +#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0003fffcU) +#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0003fffcU) +#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0003fffcU))) + +/* macros for field addr_auto_incr_2 */ +#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__SHIFT 31 +#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__WIDTH 1 +#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__MASK 0x80000000U +#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TABLES_INTF_ADDR_B2__TYPE u_int32_t +#define TABLES_INTF_ADDR_B2__READ 0x8003fffcU +#define TABLES_INTF_ADDR_B2__WRITE 0x8003fffcU + +#endif /* __TABLES_INTF_ADDR_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_tables_intf_addr_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TABLES_INTF_ADDR_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tables_intf_data_b2 */ +#ifndef __TABLES_INTF_DATA_B2_MACRO__ +#define __TABLES_INTF_DATA_B2_MACRO__ + +/* macros for field tables_data_2 */ +#define TABLES_INTF_DATA_B2__TABLES_DATA_2__SHIFT 0 +#define TABLES_INTF_DATA_B2__TABLES_DATA_2__WIDTH 32 +#define TABLES_INTF_DATA_B2__TABLES_DATA_2__MASK 0xffffffffU +#define TABLES_INTF_DATA_B2__TABLES_DATA_2__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define TABLES_INTF_DATA_B2__TABLES_DATA_2__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define TABLES_INTF_DATA_B2__TABLES_DATA_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define TABLES_INTF_DATA_B2__TABLES_DATA_2__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define TABLES_INTF_DATA_B2__TYPE u_int32_t +#define TABLES_INTF_DATA_B2__READ 0xffffffffU +#define TABLES_INTF_DATA_B2__WRITE 0xffffffffU + +#endif /* __TABLES_INTF_DATA_B2_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm2_reg_map.BB_tables_intf_data_b2 */ +#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TABLES_INTF_DATA_B2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_map.bb_chn3_reg_map.BB_dummy1 */ +#define INST_BB_REG_MAP__BB_CHN3_REG_MAP__BB_DUMMY1__NUM 256 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc3_reg_map.BB_dummy */ +#define INST_BB_REG_MAP__BB_AGC3_REG_MAP__BB_DUMMY__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rssi_b3 */ +#ifndef __RSSI_B3_MACRO__ +#define __RSSI_B3_MACRO__ + +/* macros for field rssi_3 */ +#define RSSI_B3__RSSI_3__SHIFT 0 +#define RSSI_B3__RSSI_3__WIDTH 8 +#define RSSI_B3__RSSI_3__MASK 0x000000ffU +#define RSSI_B3__RSSI_3__READ(src) (u_int32_t)(src) & 0x000000ffU + +/* macros for field rssi_ext_3 */ +#define RSSI_B3__RSSI_EXT_3__SHIFT 8 +#define RSSI_B3__RSSI_EXT_3__WIDTH 8 +#define RSSI_B3__RSSI_EXT_3__MASK 0x0000ff00U +#define RSSI_B3__RSSI_EXT_3__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define RSSI_B3__TYPE u_int32_t +#define RSSI_B3__READ 0x0000ffffU + +#endif /* __RSSI_B3_MACRO__ */ + + +/* macros for bb_reg_map.bb_agc3_reg_map.BB_rssi_b3 */ +#define INST_BB_REG_MAP__BB_AGC3_REG_MAP__BB_RSSI_B3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::dummy */ +#ifndef __DUMMY_MACRO__ +#define __DUMMY_MACRO__ + +/* macros for field dummy */ +#define DUMMY__DUMMY__SHIFT 0 +#define DUMMY__DUMMY__WIDTH 1 +#define DUMMY__DUMMY__MASK 0x00000001U +#define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U +#define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) +#define DUMMY__TYPE u_int32_t +#define DUMMY__READ 0x00000001U + +#endif /* __DUMMY_MACRO__ */ + + +/* macros for bb_reg_map.bb_sm3_reg_map.BB_dummy2 */ +#define INST_BB_REG_MAP__BB_SM3_REG_MAP__BB_DUMMY2__NUM 384 +#define RFILE_INST_BB_REG_MAP__BB_CHN_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_MRC_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_BBB_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_AGC_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_SM_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_CHN1_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_AGC1_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_SM1_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_CHN2_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_AGC2_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_SM2_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_CHN3_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_AGC3_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__BB_SM3_REG_MAP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::MAC_PCU_BUF */ +#ifndef __MAC_PCU_BUF_MACRO__ +#define __MAC_PCU_BUF_MACRO__ + +/* macros for field DATA */ +#define MAC_PCU_BUF__DATA__SHIFT 0 +#define MAC_PCU_BUF__DATA__WIDTH 32 +#define MAC_PCU_BUF__DATA__MASK 0xffffffffU +#define MAC_PCU_BUF__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define MAC_PCU_BUF__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define MAC_PCU_BUF__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define MAC_PCU_BUF__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define MAC_PCU_BUF__TYPE u_int32_t +#define MAC_PCU_BUF__READ 0xffffffffU +#define MAC_PCU_BUF__WRITE 0xffffffffU + +#endif /* __MAC_PCU_BUF_MACRO__ */ + + +/* macros for mac_pcu_buf_reg_map.MAC_PCU_BUF */ +#define INST_MAC_PCU_BUF_REG_MAP__MAC_PCU_BUF__NUM 2048 + +/* macros for BlueprintGlobalNameSpace::TXBF_DBG */ +#ifndef __TXBF_DBG_MACRO__ +#define __TXBF_DBG_MACRO__ + +/* macros for field MODE */ +#define TXBF_DBG__MODE__SHIFT 0 +#define TXBF_DBG__MODE__WIDTH 2 +#define TXBF_DBG__MODE__MASK 0x00000003U +#define TXBF_DBG__MODE__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXBF_DBG__MODE__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXBF_DBG__MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXBF_DBG__MODE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field CLIENT_TABLE */ +#define TXBF_DBG__CLIENT_TABLE__SHIFT 2 +#define TXBF_DBG__CLIENT_TABLE__WIDTH 16 +#define TXBF_DBG__CLIENT_TABLE__MASK 0x0003fffcU +#define TXBF_DBG__CLIENT_TABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003fffcU) >> 2) +#define TXBF_DBG__CLIENT_TABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0003fffcU) +#define TXBF_DBG__CLIENT_TABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0003fffcU) +#define TXBF_DBG__CLIENT_TABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0003fffcU))) + +/* macros for field SW_WR_V_DONE */ +#define TXBF_DBG__SW_WR_V_DONE__SHIFT 18 +#define TXBF_DBG__SW_WR_V_DONE__WIDTH 1 +#define TXBF_DBG__SW_WR_V_DONE__MASK 0x00040000U +#define TXBF_DBG__SW_WR_V_DONE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define TXBF_DBG__SW_WR_V_DONE__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define TXBF_DBG__SW_WR_V_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define TXBF_DBG__SW_WR_V_DONE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define TXBF_DBG__SW_WR_V_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define TXBF_DBG__SW_WR_V_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field DBG_IM */ +#define TXBF_DBG__DBG_IM__SHIFT 19 +#define TXBF_DBG__DBG_IM__WIDTH 1 +#define TXBF_DBG__DBG_IM__MASK 0x00080000U +#define TXBF_DBG__DBG_IM__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) +#define TXBF_DBG__DBG_IM__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) +#define TXBF_DBG__DBG_IM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TXBF_DBG__DBG_IM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TXBF_DBG__DBG_IM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TXBF_DBG__DBG_IM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field DBG_BW */ +#define TXBF_DBG__DBG_BW__SHIFT 20 +#define TXBF_DBG__DBG_BW__WIDTH 1 +#define TXBF_DBG__DBG_BW__MASK 0x00100000U +#define TXBF_DBG__DBG_BW__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define TXBF_DBG__DBG_BW__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) +#define TXBF_DBG__DBG_BW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TXBF_DBG__DBG_BW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TXBF_DBG__DBG_BW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TXBF_DBG__DBG_BW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field CLK_CNTL */ +#define TXBF_DBG__CLK_CNTL__SHIFT 21 +#define TXBF_DBG__CLK_CNTL__WIDTH 1 +#define TXBF_DBG__CLK_CNTL__MASK 0x00200000U +#define TXBF_DBG__CLK_CNTL__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U) +#define TXBF_DBG__CLK_CNTL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define TXBF_DBG__CLK_CNTL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define TXBF_DBG__CLK_CNTL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define TXBF_DBG__CLK_CNTL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field REGULAR_SOUNDING */ +#define TXBF_DBG__REGULAR_SOUNDING__SHIFT 22 +#define TXBF_DBG__REGULAR_SOUNDING__WIDTH 1 +#define TXBF_DBG__REGULAR_SOUNDING__MASK 0x00400000U +#define TXBF_DBG__REGULAR_SOUNDING__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define TXBF_DBG__REGULAR_SOUNDING__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define TXBF_DBG__REGULAR_SOUNDING__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TXBF_DBG__REGULAR_SOUNDING__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TXBF_DBG__REGULAR_SOUNDING__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TXBF_DBG__REGULAR_SOUNDING__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field DBG_NO_WALSH */ +#define TXBF_DBG__DBG_NO_WALSH__SHIFT 23 +#define TXBF_DBG__DBG_NO_WALSH__WIDTH 1 +#define TXBF_DBG__DBG_NO_WALSH__MASK 0x00800000U +#define TXBF_DBG__DBG_NO_WALSH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TXBF_DBG__DBG_NO_WALSH__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TXBF_DBG__DBG_NO_WALSH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TXBF_DBG__DBG_NO_WALSH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TXBF_DBG__DBG_NO_WALSH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TXBF_DBG__DBG_NO_WALSH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field DBG_NO_CSD */ +#define TXBF_DBG__DBG_NO_CSD__SHIFT 24 +#define TXBF_DBG__DBG_NO_CSD__WIDTH 1 +#define TXBF_DBG__DBG_NO_CSD__MASK 0x01000000U +#define TXBF_DBG__DBG_NO_CSD__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TXBF_DBG__DBG_NO_CSD__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TXBF_DBG__DBG_NO_CSD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TXBF_DBG__DBG_NO_CSD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TXBF_DBG__DBG_NO_CSD__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TXBF_DBG__DBG_NO_CSD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) +#define TXBF_DBG__TYPE u_int32_t +#define TXBF_DBG__READ 0x01dfffffU +#define TXBF_DBG__WRITE 0x01dfffffU + +#endif /* __TXBF_DBG_MACRO__ */ + + +/* macros for svd_reg_map.TXBF_DBG */ +#define INST_SVD_REG_MAP__TXBF_DBG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF */ +#ifndef __TXBF_MACRO__ +#define __TXBF_MACRO__ + +/* macros for field CB_TX */ +#define TXBF__CB_TX__SHIFT 0 +#define TXBF__CB_TX__WIDTH 2 +#define TXBF__CB_TX__MASK 0x00000003U +#define TXBF__CB_TX__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXBF__CB_TX__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXBF__CB_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXBF__CB_TX__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field NB_TX */ +#define TXBF__NB_TX__SHIFT 2 +#define TXBF__NB_TX__WIDTH 2 +#define TXBF__NB_TX__MASK 0x0000000cU +#define TXBF__NB_TX__READ(src) (((u_int32_t)(src) & 0x0000000cU) >> 2) +#define TXBF__NB_TX__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000000cU) +#define TXBF__NB_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define TXBF__NB_TX__VERIFY(src) (!((((u_int32_t)(src) << 2) & ~0x0000000cU))) + +/* macros for field NG_RPT_TX */ +#define TXBF__NG_RPT_TX__SHIFT 4 +#define TXBF__NG_RPT_TX__WIDTH 2 +#define TXBF__NG_RPT_TX__MASK 0x00000030U +#define TXBF__NG_RPT_TX__READ(src) (((u_int32_t)(src) & 0x00000030U) >> 4) +#define TXBF__NG_RPT_TX__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000030U) +#define TXBF__NG_RPT_TX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define TXBF__NG_RPT_TX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field NG_CVCACHE */ +#define TXBF__NG_CVCACHE__SHIFT 6 +#define TXBF__NG_CVCACHE__WIDTH 2 +#define TXBF__NG_CVCACHE__MASK 0x000000c0U +#define TXBF__NG_CVCACHE__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6) +#define TXBF__NG_CVCACHE__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U) +#define TXBF__NG_CVCACHE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define TXBF__NG_CVCACHE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field TXCV_BFWEIGHT_METHOD */ +#define TXBF__TXCV_BFWEIGHT_METHOD__SHIFT 9 +#define TXBF__TXCV_BFWEIGHT_METHOD__WIDTH 2 +#define TXBF__TXCV_BFWEIGHT_METHOD__MASK 0x00000600U +#define TXBF__TXCV_BFWEIGHT_METHOD__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000600U) >> 9) +#define TXBF__TXCV_BFWEIGHT_METHOD__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000600U) +#define TXBF__TXCV_BFWEIGHT_METHOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000600U) | (((u_int32_t)(src) <<\ + 9) & 0x00000600U) +#define TXBF__TXCV_BFWEIGHT_METHOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000600U))) + +/* macros for field RLR_EN */ +#define TXBF__RLR_EN__SHIFT 11 +#define TXBF__RLR_EN__WIDTH 1 +#define TXBF__RLR_EN__MASK 0x00000800U +#define TXBF__RLR_EN__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define TXBF__RLR_EN__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define TXBF__RLR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define TXBF__RLR_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define TXBF__RLR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define TXBF__RLR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field RC_20_U_DONE */ +#define TXBF__RC_20_U_DONE__SHIFT 12 +#define TXBF__RC_20_U_DONE__WIDTH 1 +#define TXBF__RC_20_U_DONE__MASK 0x00001000U +#define TXBF__RC_20_U_DONE__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) +#define TXBF__RC_20_U_DONE__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) +#define TXBF__RC_20_U_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define TXBF__RC_20_U_DONE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define TXBF__RC_20_U_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define TXBF__RC_20_U_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field RC_20_L_DONE */ +#define TXBF__RC_20_L_DONE__SHIFT 13 +#define TXBF__RC_20_L_DONE__WIDTH 1 +#define TXBF__RC_20_L_DONE__MASK 0x00002000U +#define TXBF__RC_20_L_DONE__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) +#define TXBF__RC_20_L_DONE__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U) +#define TXBF__RC_20_L_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TXBF__RC_20_L_DONE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TXBF__RC_20_L_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TXBF__RC_20_L_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field RC_40_DONE */ +#define TXBF__RC_40_DONE__SHIFT 14 +#define TXBF__RC_40_DONE__WIDTH 1 +#define TXBF__RC_40_DONE__MASK 0x00004000U +#define TXBF__RC_40_DONE__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) +#define TXBF__RC_40_DONE__WRITE(src) (((u_int32_t)(src) << 14) & 0x00004000U) +#define TXBF__RC_40_DONE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define TXBF__RC_40_DONE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define TXBF__RC_40_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define TXBF__RC_40_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) +#define TXBF__TYPE u_int32_t +#define TXBF__READ 0x00007effU +#define TXBF__WRITE 0x00007effU + +#endif /* __TXBF_MACRO__ */ + + +/* macros for svd_reg_map.TXBF */ +#define INST_SVD_REG_MAP__TXBF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF_TIMER */ +#ifndef __TXBF_TIMER_MACRO__ +#define __TXBF_TIMER_MACRO__ + +/* macros for field TIMEOUT */ +#define TXBF_TIMER__TIMEOUT__SHIFT 0 +#define TXBF_TIMER__TIMEOUT__WIDTH 8 +#define TXBF_TIMER__TIMEOUT__MASK 0x000000ffU +#define TXBF_TIMER__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000000ffU +#define TXBF_TIMER__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define TXBF_TIMER__TIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define TXBF_TIMER__TIMEOUT__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field ATIMEOUT */ +#define TXBF_TIMER__ATIMEOUT__SHIFT 8 +#define TXBF_TIMER__ATIMEOUT__WIDTH 8 +#define TXBF_TIMER__ATIMEOUT__MASK 0x0000ff00U +#define TXBF_TIMER__ATIMEOUT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) +#define TXBF_TIMER__ATIMEOUT__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x0000ff00U) +#define TXBF_TIMER__ATIMEOUT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ff00U) | (((u_int32_t)(src) <<\ + 8) & 0x0000ff00U) +#define TXBF_TIMER__ATIMEOUT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x0000ff00U))) +#define TXBF_TIMER__TYPE u_int32_t +#define TXBF_TIMER__READ 0x0000ffffU +#define TXBF_TIMER__WRITE 0x0000ffffU + +#endif /* __TXBF_TIMER_MACRO__ */ + + +/* macros for svd_reg_map.TXBF_TIMER */ +#define INST_SVD_REG_MAP__TXBF_TIMER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF_SW */ +#ifndef __TXBF_SW_MACRO__ +#define __TXBF_SW_MACRO__ + +/* macros for field LRU_ACK */ +#define TXBF_SW__LRU_ACK__SHIFT 0 +#define TXBF_SW__LRU_ACK__WIDTH 1 +#define TXBF_SW__LRU_ACK__MASK 0x00000001U +#define TXBF_SW__LRU_ACK__READ(src) (u_int32_t)(src) & 0x00000001U +#define TXBF_SW__LRU_ACK__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TXBF_SW__LRU_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TXBF_SW__LRU_ACK__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TXBF_SW__LRU_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXBF_SW__LRU_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LRU_ADDR */ +#define TXBF_SW__LRU_ADDR__SHIFT 1 +#define TXBF_SW__LRU_ADDR__WIDTH 9 +#define TXBF_SW__LRU_ADDR__MASK 0x000003feU +#define TXBF_SW__LRU_ADDR__READ(src) (((u_int32_t)(src) & 0x000003feU) >> 1) + +/* macros for field LRU_EN */ +#define TXBF_SW__LRU_EN__SHIFT 11 +#define TXBF_SW__LRU_EN__WIDTH 1 +#define TXBF_SW__LRU_EN__MASK 0x00000800U +#define TXBF_SW__LRU_EN__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define TXBF_SW__LRU_EN__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define TXBF_SW__LRU_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define TXBF_SW__LRU_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define TXBF_SW__LRU_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define TXBF_SW__LRU_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field DEST_IDX */ +#define TXBF_SW__DEST_IDX__SHIFT 12 +#define TXBF_SW__DEST_IDX__WIDTH 7 +#define TXBF_SW__DEST_IDX__MASK 0x0007f000U +#define TXBF_SW__DEST_IDX__READ(src) (((u_int32_t)(src) & 0x0007f000U) >> 12) +#define TXBF_SW__DEST_IDX__WRITE(src) (((u_int32_t)(src) << 12) & 0x0007f000U) +#define TXBF_SW__DEST_IDX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0007f000U) +#define TXBF_SW__DEST_IDX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0007f000U))) + +/* macros for field LRU_WR_ACK */ +#define TXBF_SW__LRU_WR_ACK__SHIFT 19 +#define TXBF_SW__LRU_WR_ACK__WIDTH 1 +#define TXBF_SW__LRU_WR_ACK__MASK 0x00080000U +#define TXBF_SW__LRU_WR_ACK__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) +#define TXBF_SW__LRU_WR_ACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00080000U) +#define TXBF_SW__LRU_WR_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TXBF_SW__LRU_WR_ACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TXBF_SW__LRU_WR_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TXBF_SW__LRU_WR_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field LRU_RD_ACK */ +#define TXBF_SW__LRU_RD_ACK__SHIFT 20 +#define TXBF_SW__LRU_RD_ACK__WIDTH 1 +#define TXBF_SW__LRU_RD_ACK__MASK 0x00100000U +#define TXBF_SW__LRU_RD_ACK__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define TXBF_SW__LRU_RD_ACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define TXBF_SW__LRU_RD_ACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TXBF_SW__LRU_RD_ACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TXBF_SW__LRU_RD_ACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TXBF_SW__LRU_RD_ACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field WALSH_CSD_MODE */ +#define TXBF_SW__WALSH_CSD_MODE__SHIFT 21 +#define TXBF_SW__WALSH_CSD_MODE__WIDTH 1 +#define TXBF_SW__WALSH_CSD_MODE__MASK 0x00200000U +#define TXBF_SW__WALSH_CSD_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define TXBF_SW__WALSH_CSD_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define TXBF_SW__WALSH_CSD_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define TXBF_SW__WALSH_CSD_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define TXBF_SW__WALSH_CSD_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define TXBF_SW__WALSH_CSD_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field CONDITION_NUMBER */ +#define TXBF_SW__CONDITION_NUMBER__SHIFT 22 +#define TXBF_SW__CONDITION_NUMBER__WIDTH 5 +#define TXBF_SW__CONDITION_NUMBER__MASK 0x07c00000U +#define TXBF_SW__CONDITION_NUMBER__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define TXBF_SW__CONDITION_NUMBER__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define TXBF_SW__CONDITION_NUMBER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define TXBF_SW__CONDITION_NUMBER__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) +#define TXBF_SW__TYPE u_int32_t +#define TXBF_SW__READ 0x07fffbffU +#define TXBF_SW__WRITE 0x07fffbffU + +#endif /* __TXBF_SW_MACRO__ */ + + +/* macros for svd_reg_map.TXBF_SW */ +#define INST_SVD_REG_MAP__TXBF_SW__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF_SM */ +#ifndef __TXBF_SM_MACRO__ +#define __TXBF_SM_MACRO__ + +/* macros for field OBS */ +#define TXBF_SM__OBS__SHIFT 0 +#define TXBF_SM__OBS__WIDTH 32 +#define TXBF_SM__OBS__MASK 0xffffffffU +#define TXBF_SM__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF_SM__TYPE u_int32_t +#define TXBF_SM__READ 0xffffffffU + +#endif /* __TXBF_SM_MACRO__ */ + + +/* macros for svd_reg_map.TXBF_SM */ +#define INST_SVD_REG_MAP__TXBF_SM__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF1_CNTL */ +#ifndef __TXBF1_CNTL_MACRO__ +#define __TXBF1_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF1_CNTL__OBS__SHIFT 0 +#define TXBF1_CNTL__OBS__WIDTH 32 +#define TXBF1_CNTL__OBS__MASK 0xffffffffU +#define TXBF1_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF1_CNTL__TYPE u_int32_t +#define TXBF1_CNTL__READ 0xffffffffU + +#endif /* __TXBF1_CNTL_MACRO__ */ + + +/* macros for svd_reg_map.TXBF1_CNTL */ +#define INST_SVD_REG_MAP__TXBF1_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF2_CNTL */ +#ifndef __TXBF2_CNTL_MACRO__ +#define __TXBF2_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF2_CNTL__OBS__SHIFT 0 +#define TXBF2_CNTL__OBS__WIDTH 32 +#define TXBF2_CNTL__OBS__MASK 0xffffffffU +#define TXBF2_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF2_CNTL__TYPE u_int32_t +#define TXBF2_CNTL__READ 0xffffffffU + +#endif /* __TXBF2_CNTL_MACRO__ */ + + +/* macros for svd_reg_map.TXBF2_CNTL */ +#define INST_SVD_REG_MAP__TXBF2_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF3_CNTL */ +#ifndef __TXBF3_CNTL_MACRO__ +#define __TXBF3_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF3_CNTL__OBS__SHIFT 0 +#define TXBF3_CNTL__OBS__WIDTH 32 +#define TXBF3_CNTL__OBS__MASK 0xffffffffU +#define TXBF3_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF3_CNTL__TYPE u_int32_t +#define TXBF3_CNTL__READ 0xffffffffU + +#endif /* __TXBF3_CNTL_MACRO__ */ + + +/* macros for svd_reg_map.TXBF3_CNTL */ +#define INST_SVD_REG_MAP__TXBF3_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF4_CNTL */ +#ifndef __TXBF4_CNTL_MACRO__ +#define __TXBF4_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF4_CNTL__OBS__SHIFT 0 +#define TXBF4_CNTL__OBS__WIDTH 32 +#define TXBF4_CNTL__OBS__MASK 0xffffffffU +#define TXBF4_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF4_CNTL__TYPE u_int32_t +#define TXBF4_CNTL__READ 0xffffffffU + +#endif /* __TXBF4_CNTL_MACRO__ */ + + +/* macros for svd_reg_map.TXBF4_CNTL */ +#define INST_SVD_REG_MAP__TXBF4_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF5_CNTL */ +#ifndef __TXBF5_CNTL_MACRO__ +#define __TXBF5_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF5_CNTL__OBS__SHIFT 0 +#define TXBF5_CNTL__OBS__WIDTH 32 +#define TXBF5_CNTL__OBS__MASK 0xffffffffU +#define TXBF5_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF5_CNTL__TYPE u_int32_t +#define TXBF5_CNTL__READ 0xffffffffU + +#endif /* __TXBF5_CNTL_MACRO__ */ + + +/* macros for svd_reg_map.TXBF5_CNTL */ +#define INST_SVD_REG_MAP__TXBF5_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF6_CNTL */ +#ifndef __TXBF6_CNTL_MACRO__ +#define __TXBF6_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF6_CNTL__OBS__SHIFT 0 +#define TXBF6_CNTL__OBS__WIDTH 32 +#define TXBF6_CNTL__OBS__MASK 0xffffffffU +#define TXBF6_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF6_CNTL__TYPE u_int32_t +#define TXBF6_CNTL__READ 0xffffffffU + +#endif /* __TXBF6_CNTL_MACRO__ */ + + +/* macros for svd_reg_map.TXBF6_CNTL */ +#define INST_SVD_REG_MAP__TXBF6_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF7_CNTL */ +#ifndef __TXBF7_CNTL_MACRO__ +#define __TXBF7_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF7_CNTL__OBS__SHIFT 0 +#define TXBF7_CNTL__OBS__WIDTH 32 +#define TXBF7_CNTL__OBS__MASK 0xffffffffU +#define TXBF7_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF7_CNTL__TYPE u_int32_t +#define TXBF7_CNTL__READ 0xffffffffU + +#endif /* __TXBF7_CNTL_MACRO__ */ + + +/* macros for svd_reg_map.TXBF7_CNTL */ +#define INST_SVD_REG_MAP__TXBF7_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXBF8_CNTL */ +#ifndef __TXBF8_CNTL_MACRO__ +#define __TXBF8_CNTL_MACRO__ + +/* macros for field OBS */ +#define TXBF8_CNTL__OBS__SHIFT 0 +#define TXBF8_CNTL__OBS__WIDTH 32 +#define TXBF8_CNTL__OBS__MASK 0xffffffffU +#define TXBF8_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU +#define TXBF8_CNTL__TYPE u_int32_t +#define TXBF8_CNTL__READ 0xffffffffU + +#endif /* __TXBF8_CNTL_MACRO__ */ + + +/* macros for svd_reg_map.TXBF8_CNTL */ +#define INST_SVD_REG_MAP__TXBF8_CNTL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RC0 */ +#ifndef __RC0_MACRO__ +#define __RC0_MACRO__ + +/* macros for field DATA */ +#define RC0__DATA__SHIFT 0 +#define RC0__DATA__WIDTH 32 +#define RC0__DATA__MASK 0xffffffffU +#define RC0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define RC0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define RC0__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define RC0__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define RC0__TYPE u_int32_t +#define RC0__READ 0xffffffffU +#define RC0__WRITE 0xffffffffU + +#endif /* __RC0_MACRO__ */ + + +/* macros for svd_reg_map.RC0 */ +#define INST_SVD_REG_MAP__RC0__NUM 118 + +/* macros for BlueprintGlobalNameSpace::RC1 */ +#ifndef __RC1_MACRO__ +#define __RC1_MACRO__ + +/* macros for field DATA */ +#define RC1__DATA__SHIFT 0 +#define RC1__DATA__WIDTH 32 +#define RC1__DATA__MASK 0xffffffffU +#define RC1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define RC1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define RC1__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define RC1__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define RC1__TYPE u_int32_t +#define RC1__READ 0xffffffffU +#define RC1__WRITE 0xffffffffU + +#endif /* __RC1_MACRO__ */ + + +/* macros for svd_reg_map.RC1 */ +#define INST_SVD_REG_MAP__RC1__NUM 118 + +/* macros for BlueprintGlobalNameSpace::SVD_MEM0 */ +#ifndef __SVD_MEM0_MACRO__ +#define __SVD_MEM0_MACRO__ + +/* macros for field DATA */ +#define SVD_MEM0__DATA__SHIFT 0 +#define SVD_MEM0__DATA__WIDTH 32 +#define SVD_MEM0__DATA__MASK 0xffffffffU +#define SVD_MEM0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define SVD_MEM0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define SVD_MEM0__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define SVD_MEM0__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define SVD_MEM0__TYPE u_int32_t +#define SVD_MEM0__READ 0xffffffffU +#define SVD_MEM0__WRITE 0xffffffffU + +#endif /* __SVD_MEM0_MACRO__ */ + + +/* macros for svd_reg_map.SVD_MEM0 */ +#define INST_SVD_REG_MAP__SVD_MEM0__NUM 114 + +/* macros for BlueprintGlobalNameSpace::SVD_MEM1 */ +#ifndef __SVD_MEM1_MACRO__ +#define __SVD_MEM1_MACRO__ + +/* macros for field DATA */ +#define SVD_MEM1__DATA__SHIFT 0 +#define SVD_MEM1__DATA__WIDTH 32 +#define SVD_MEM1__DATA__MASK 0xffffffffU +#define SVD_MEM1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define SVD_MEM1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define SVD_MEM1__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define SVD_MEM1__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define SVD_MEM1__TYPE u_int32_t +#define SVD_MEM1__READ 0xffffffffU +#define SVD_MEM1__WRITE 0xffffffffU + +#endif /* __SVD_MEM1_MACRO__ */ + + +/* macros for svd_reg_map.SVD_MEM1 */ +#define INST_SVD_REG_MAP__SVD_MEM1__NUM 114 + +/* macros for BlueprintGlobalNameSpace::SVD_MEM2 */ +#ifndef __SVD_MEM2_MACRO__ +#define __SVD_MEM2_MACRO__ + +/* macros for field DATA */ +#define SVD_MEM2__DATA__SHIFT 0 +#define SVD_MEM2__DATA__WIDTH 32 +#define SVD_MEM2__DATA__MASK 0xffffffffU +#define SVD_MEM2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define SVD_MEM2__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define SVD_MEM2__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define SVD_MEM2__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define SVD_MEM2__TYPE u_int32_t +#define SVD_MEM2__READ 0xffffffffU +#define SVD_MEM2__WRITE 0xffffffffU + +#endif /* __SVD_MEM2_MACRO__ */ + + +/* macros for svd_reg_map.SVD_MEM2 */ +#define INST_SVD_REG_MAP__SVD_MEM2__NUM 114 + +/* macros for BlueprintGlobalNameSpace::SVD_MEM3 */ +#ifndef __SVD_MEM3_MACRO__ +#define __SVD_MEM3_MACRO__ + +/* macros for field DATA */ +#define SVD_MEM3__DATA__SHIFT 0 +#define SVD_MEM3__DATA__WIDTH 32 +#define SVD_MEM3__DATA__MASK 0xffffffffU +#define SVD_MEM3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define SVD_MEM3__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define SVD_MEM3__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define SVD_MEM3__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define SVD_MEM3__TYPE u_int32_t +#define SVD_MEM3__READ 0xffffffffU +#define SVD_MEM3__WRITE 0xffffffffU + +#endif /* __SVD_MEM3_MACRO__ */ + + +/* macros for svd_reg_map.SVD_MEM3 */ +#define INST_SVD_REG_MAP__SVD_MEM3__NUM 114 + +/* macros for BlueprintGlobalNameSpace::SVD_MEM4 */ +#ifndef __SVD_MEM4_MACRO__ +#define __SVD_MEM4_MACRO__ + +/* macros for field DATA */ +#define SVD_MEM4__DATA__SHIFT 0 +#define SVD_MEM4__DATA__WIDTH 32 +#define SVD_MEM4__DATA__MASK 0xffffffffU +#define SVD_MEM4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define SVD_MEM4__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define SVD_MEM4__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define SVD_MEM4__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define SVD_MEM4__TYPE u_int32_t +#define SVD_MEM4__READ 0xffffffffU +#define SVD_MEM4__WRITE 0xffffffffU + +#endif /* __SVD_MEM4_MACRO__ */ + + +/* macros for svd_reg_map.SVD_MEM4 */ +#define INST_SVD_REG_MAP__SVD_MEM4__NUM 114 + +/* macros for BlueprintGlobalNameSpace::CVCACHE */ +#ifndef __CVCACHE_MACRO__ +#define __CVCACHE_MACRO__ + +/* macros for field DATA */ +#define CVCACHE__DATA__SHIFT 0 +#define CVCACHE__DATA__WIDTH 32 +#define CVCACHE__DATA__MASK 0xffffffffU +#define CVCACHE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU +#define CVCACHE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) +#define CVCACHE__DATA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CVCACHE__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) +#define CVCACHE__TYPE u_int32_t +#define CVCACHE__READ 0xffffffffU +#define CVCACHE__WRITE 0xffffffffU + +#endif /* __CVCACHE_MACRO__ */ + + +/* macros for svd_reg_map.CVCACHE */ +#define INST_SVD_REG_MAP__CVCACHE__NUM 512 + +/* macros for BlueprintGlobalNameSpace::RXRF_BIAS1 */ +#ifndef __RXRF_BIAS1_MACRO__ +#define __RXRF_BIAS1_MACRO__ + +/* macros for field SPARE */ +#define RXRF_BIAS1__SPARE__SHIFT 0 +#define RXRF_BIAS1__SPARE__WIDTH 1 +#define RXRF_BIAS1__SPARE__MASK 0x00000001U +#define RXRF_BIAS1__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXRF_BIAS1__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXRF_BIAS1__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXRF_BIAS1__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define RXRF_BIAS1__SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXRF_BIAS1__SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PWD_IR25SPARE */ +#define RXRF_BIAS1__PWD_IR25SPARE__SHIFT 1 +#define RXRF_BIAS1__PWD_IR25SPARE__WIDTH 3 +#define RXRF_BIAS1__PWD_IR25SPARE__MASK 0x0000000eU +#define RXRF_BIAS1__PWD_IR25SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define RXRF_BIAS1__PWD_IR25SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define RXRF_BIAS1__PWD_IR25SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define RXRF_BIAS1__PWD_IR25SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field PWD_IR25LO18 */ +#define RXRF_BIAS1__PWD_IR25LO18__SHIFT 4 +#define RXRF_BIAS1__PWD_IR25LO18__WIDTH 3 +#define RXRF_BIAS1__PWD_IR25LO18__MASK 0x00000070U +#define RXRF_BIAS1__PWD_IR25LO18__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000070U) >> 4) +#define RXRF_BIAS1__PWD_IR25LO18__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define RXRF_BIAS1__PWD_IR25LO18__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define RXRF_BIAS1__PWD_IR25LO18__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field PWD_IC25LO36 */ +#define RXRF_BIAS1__PWD_IC25LO36__SHIFT 7 +#define RXRF_BIAS1__PWD_IC25LO36__WIDTH 3 +#define RXRF_BIAS1__PWD_IC25LO36__MASK 0x00000380U +#define RXRF_BIAS1__PWD_IC25LO36__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000380U) >> 7) +#define RXRF_BIAS1__PWD_IC25LO36__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000380U) +#define RXRF_BIAS1__PWD_IC25LO36__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((u_int32_t)(src) <<\ + 7) & 0x00000380U) +#define RXRF_BIAS1__PWD_IC25LO36__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000380U))) + +/* macros for field PWD_IC25MXR2_5GH */ +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__SHIFT 10 +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__WIDTH 3 +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__MASK 0x00001c00U +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001c00U) >> 10) +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00001c00U) +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00001c00U) +#define RXRF_BIAS1__PWD_IC25MXR2_5GH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00001c00U))) + +/* macros for field PWD_IC25MXR5GH */ +#define RXRF_BIAS1__PWD_IC25MXR5GH__SHIFT 13 +#define RXRF_BIAS1__PWD_IC25MXR5GH__WIDTH 3 +#define RXRF_BIAS1__PWD_IC25MXR5GH__MASK 0x0000e000U +#define RXRF_BIAS1__PWD_IC25MXR5GH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000e000U) >> 13) +#define RXRF_BIAS1__PWD_IC25MXR5GH__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x0000e000U) +#define RXRF_BIAS1__PWD_IC25MXR5GH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define RXRF_BIAS1__PWD_IC25MXR5GH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0000e000U))) + +/* macros for field PWD_IC25VGA5G */ +#define RXRF_BIAS1__PWD_IC25VGA5G__SHIFT 16 +#define RXRF_BIAS1__PWD_IC25VGA5G__WIDTH 3 +#define RXRF_BIAS1__PWD_IC25VGA5G__MASK 0x00070000U +#define RXRF_BIAS1__PWD_IC25VGA5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00070000U) >> 16) +#define RXRF_BIAS1__PWD_IC25VGA5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00070000U) +#define RXRF_BIAS1__PWD_IC25VGA5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00070000U) | (((u_int32_t)(src) <<\ + 16) & 0x00070000U) +#define RXRF_BIAS1__PWD_IC25VGA5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00070000U))) + +/* macros for field PWD_IC75LNA5G */ +#define RXRF_BIAS1__PWD_IC75LNA5G__SHIFT 19 +#define RXRF_BIAS1__PWD_IC75LNA5G__WIDTH 3 +#define RXRF_BIAS1__PWD_IC75LNA5G__MASK 0x00380000U +#define RXRF_BIAS1__PWD_IC75LNA5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00380000U) >> 19) +#define RXRF_BIAS1__PWD_IC75LNA5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define RXRF_BIAS1__PWD_IC75LNA5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define RXRF_BIAS1__PWD_IC75LNA5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field PWD_IR25LO24 */ +#define RXRF_BIAS1__PWD_IR25LO24__SHIFT 22 +#define RXRF_BIAS1__PWD_IR25LO24__WIDTH 3 +#define RXRF_BIAS1__PWD_IR25LO24__MASK 0x01c00000U +#define RXRF_BIAS1__PWD_IR25LO24__READ(src) \ + (((u_int32_t)(src)\ + & 0x01c00000U) >> 22) +#define RXRF_BIAS1__PWD_IR25LO24__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x01c00000U) +#define RXRF_BIAS1__PWD_IR25LO24__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x01c00000U) +#define RXRF_BIAS1__PWD_IR25LO24__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x01c00000U))) + +/* macros for field PWD_IC25MXR2GH */ +#define RXRF_BIAS1__PWD_IC25MXR2GH__SHIFT 25 +#define RXRF_BIAS1__PWD_IC25MXR2GH__WIDTH 3 +#define RXRF_BIAS1__PWD_IC25MXR2GH__MASK 0x0e000000U +#define RXRF_BIAS1__PWD_IC25MXR2GH__READ(src) \ + (((u_int32_t)(src)\ + & 0x0e000000U) >> 25) +#define RXRF_BIAS1__PWD_IC25MXR2GH__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x0e000000U) +#define RXRF_BIAS1__PWD_IC25MXR2GH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x0e000000U) +#define RXRF_BIAS1__PWD_IC25MXR2GH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x0e000000U))) + +/* macros for field PWD_IC75LNA2G */ +#define RXRF_BIAS1__PWD_IC75LNA2G__SHIFT 28 +#define RXRF_BIAS1__PWD_IC75LNA2G__WIDTH 3 +#define RXRF_BIAS1__PWD_IC75LNA2G__MASK 0x70000000U +#define RXRF_BIAS1__PWD_IC75LNA2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x70000000U) >> 28) +#define RXRF_BIAS1__PWD_IC75LNA2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x70000000U) +#define RXRF_BIAS1__PWD_IC75LNA2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x70000000U) | (((u_int32_t)(src) <<\ + 28) & 0x70000000U) +#define RXRF_BIAS1__PWD_IC75LNA2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x70000000U))) + +/* macros for field PWD_BIAS */ +#define RXRF_BIAS1__PWD_BIAS__SHIFT 31 +#define RXRF_BIAS1__PWD_BIAS__WIDTH 1 +#define RXRF_BIAS1__PWD_BIAS__MASK 0x80000000U +#define RXRF_BIAS1__PWD_BIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RXRF_BIAS1__PWD_BIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RXRF_BIAS1__PWD_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RXRF_BIAS1__PWD_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RXRF_BIAS1__PWD_BIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RXRF_BIAS1__PWD_BIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RXRF_BIAS1__TYPE u_int32_t +#define RXRF_BIAS1__READ 0xffffffffU +#define RXRF_BIAS1__WRITE 0xffffffffU + +#endif /* __RXRF_BIAS1_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_RXRF_BIAS1 */ +#define INST_RADIO65_REG_MAP__CH0_RXRF_BIAS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXRF_BIAS2 */ +#ifndef __RXRF_BIAS2_MACRO__ +#define __RXRF_BIAS2_MACRO__ + +/* macros for field SPARE */ +#define RXRF_BIAS2__SPARE__SHIFT 0 +#define RXRF_BIAS2__SPARE__WIDTH 1 +#define RXRF_BIAS2__SPARE__MASK 0x00000001U +#define RXRF_BIAS2__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXRF_BIAS2__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXRF_BIAS2__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXRF_BIAS2__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define RXRF_BIAS2__SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXRF_BIAS2__SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PKEN */ +#define RXRF_BIAS2__PKEN__SHIFT 1 +#define RXRF_BIAS2__PKEN__WIDTH 3 +#define RXRF_BIAS2__PKEN__MASK 0x0000000eU +#define RXRF_BIAS2__PKEN__READ(src) (((u_int32_t)(src) & 0x0000000eU) >> 1) +#define RXRF_BIAS2__PKEN__WRITE(src) (((u_int32_t)(src) << 1) & 0x0000000eU) +#define RXRF_BIAS2__PKEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define RXRF_BIAS2__PKEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field VCMVALUE */ +#define RXRF_BIAS2__VCMVALUE__SHIFT 4 +#define RXRF_BIAS2__VCMVALUE__WIDTH 3 +#define RXRF_BIAS2__VCMVALUE__MASK 0x00000070U +#define RXRF_BIAS2__VCMVALUE__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4) +#define RXRF_BIAS2__VCMVALUE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000070U) +#define RXRF_BIAS2__VCMVALUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000070U) | (((u_int32_t)(src) <<\ + 4) & 0x00000070U) +#define RXRF_BIAS2__VCMVALUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000070U))) + +/* macros for field PWD_VCMBUF */ +#define RXRF_BIAS2__PWD_VCMBUF__SHIFT 7 +#define RXRF_BIAS2__PWD_VCMBUF__WIDTH 1 +#define RXRF_BIAS2__PWD_VCMBUF__MASK 0x00000080U +#define RXRF_BIAS2__PWD_VCMBUF__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RXRF_BIAS2__PWD_VCMBUF__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RXRF_BIAS2__PWD_VCMBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RXRF_BIAS2__PWD_VCMBUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RXRF_BIAS2__PWD_VCMBUF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RXRF_BIAS2__PWD_VCMBUF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field PWD_IR25SPAREH */ +#define RXRF_BIAS2__PWD_IR25SPAREH__SHIFT 8 +#define RXRF_BIAS2__PWD_IR25SPAREH__WIDTH 3 +#define RXRF_BIAS2__PWD_IR25SPAREH__MASK 0x00000700U +#define RXRF_BIAS2__PWD_IR25SPAREH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define RXRF_BIAS2__PWD_IR25SPAREH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define RXRF_BIAS2__PWD_IR25SPAREH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define RXRF_BIAS2__PWD_IR25SPAREH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field PWD_IR25SPARE */ +#define RXRF_BIAS2__PWD_IR25SPARE__SHIFT 11 +#define RXRF_BIAS2__PWD_IR25SPARE__WIDTH 3 +#define RXRF_BIAS2__PWD_IR25SPARE__MASK 0x00003800U +#define RXRF_BIAS2__PWD_IR25SPARE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define RXRF_BIAS2__PWD_IR25SPARE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define RXRF_BIAS2__PWD_IR25SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define RXRF_BIAS2__PWD_IR25SPARE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field PWD_IC25LNABUF */ +#define RXRF_BIAS2__PWD_IC25LNABUF__SHIFT 14 +#define RXRF_BIAS2__PWD_IC25LNABUF__WIDTH 3 +#define RXRF_BIAS2__PWD_IC25LNABUF__MASK 0x0001c000U +#define RXRF_BIAS2__PWD_IC25LNABUF__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define RXRF_BIAS2__PWD_IC25LNABUF__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define RXRF_BIAS2__PWD_IC25LNABUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define RXRF_BIAS2__PWD_IC25LNABUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field PWD_IR25AGCH */ +#define RXRF_BIAS2__PWD_IR25AGCH__SHIFT 17 +#define RXRF_BIAS2__PWD_IR25AGCH__WIDTH 3 +#define RXRF_BIAS2__PWD_IR25AGCH__MASK 0x000e0000U +#define RXRF_BIAS2__PWD_IR25AGCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define RXRF_BIAS2__PWD_IR25AGCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define RXRF_BIAS2__PWD_IR25AGCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define RXRF_BIAS2__PWD_IR25AGCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field PWD_IR25AGC */ +#define RXRF_BIAS2__PWD_IR25AGC__SHIFT 20 +#define RXRF_BIAS2__PWD_IR25AGC__WIDTH 3 +#define RXRF_BIAS2__PWD_IR25AGC__MASK 0x00700000U +#define RXRF_BIAS2__PWD_IR25AGC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RXRF_BIAS2__PWD_IR25AGC__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RXRF_BIAS2__PWD_IR25AGC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RXRF_BIAS2__PWD_IR25AGC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field PWD_IC25AGC */ +#define RXRF_BIAS2__PWD_IC25AGC__SHIFT 23 +#define RXRF_BIAS2__PWD_IC25AGC__WIDTH 3 +#define RXRF_BIAS2__PWD_IC25AGC__MASK 0x03800000U +#define RXRF_BIAS2__PWD_IC25AGC__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RXRF_BIAS2__PWD_IC25AGC__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RXRF_BIAS2__PWD_IC25AGC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RXRF_BIAS2__PWD_IC25AGC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field PWD_IC25VCMBUF */ +#define RXRF_BIAS2__PWD_IC25VCMBUF__SHIFT 26 +#define RXRF_BIAS2__PWD_IC25VCMBUF__WIDTH 3 +#define RXRF_BIAS2__PWD_IC25VCMBUF__MASK 0x1c000000U +#define RXRF_BIAS2__PWD_IC25VCMBUF__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define RXRF_BIAS2__PWD_IC25VCMBUF__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define RXRF_BIAS2__PWD_IC25VCMBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RXRF_BIAS2__PWD_IC25VCMBUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field PWD_IR25VCM */ +#define RXRF_BIAS2__PWD_IR25VCM__SHIFT 29 +#define RXRF_BIAS2__PWD_IR25VCM__WIDTH 3 +#define RXRF_BIAS2__PWD_IR25VCM__MASK 0xe0000000U +#define RXRF_BIAS2__PWD_IR25VCM__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define RXRF_BIAS2__PWD_IR25VCM__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define RXRF_BIAS2__PWD_IR25VCM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RXRF_BIAS2__PWD_IR25VCM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RXRF_BIAS2__TYPE u_int32_t +#define RXRF_BIAS2__READ 0xffffffffU +#define RXRF_BIAS2__WRITE 0xffffffffU + +#endif /* __RXRF_BIAS2_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_RXRF_BIAS2 */ +#define INST_RADIO65_REG_MAP__CH0_RXRF_BIAS2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXRF_GAINSTAGES */ +#ifndef __RXRF_GAINSTAGES_MACRO__ +#define __RXRF_GAINSTAGES_MACRO__ + +/* macros for field SPARE */ +#define RXRF_GAINSTAGES__SPARE__SHIFT 0 +#define RXRF_GAINSTAGES__SPARE__WIDTH 1 +#define RXRF_GAINSTAGES__SPARE__MASK 0x00000001U +#define RXRF_GAINSTAGES__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXRF_GAINSTAGES__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXRF_GAINSTAGES__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXRF_GAINSTAGES__SPARE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RXRF_GAINSTAGES__SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXRF_GAINSTAGES__SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LNAON_CALDC */ +#define RXRF_GAINSTAGES__LNAON_CALDC__SHIFT 1 +#define RXRF_GAINSTAGES__LNAON_CALDC__WIDTH 1 +#define RXRF_GAINSTAGES__LNAON_CALDC__MASK 0x00000002U +#define RXRF_GAINSTAGES__LNAON_CALDC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RXRF_GAINSTAGES__LNAON_CALDC__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RXRF_GAINSTAGES__LNAON_CALDC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RXRF_GAINSTAGES__LNAON_CALDC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RXRF_GAINSTAGES__LNAON_CALDC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RXRF_GAINSTAGES__LNAON_CALDC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field VGA5G_CAP */ +#define RXRF_GAINSTAGES__VGA5G_CAP__SHIFT 2 +#define RXRF_GAINSTAGES__VGA5G_CAP__WIDTH 2 +#define RXRF_GAINSTAGES__VGA5G_CAP__MASK 0x0000000cU +#define RXRF_GAINSTAGES__VGA5G_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define RXRF_GAINSTAGES__VGA5G_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define RXRF_GAINSTAGES__VGA5G_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define RXRF_GAINSTAGES__VGA5G_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field LNA5G_CAP */ +#define RXRF_GAINSTAGES__LNA5G_CAP__SHIFT 4 +#define RXRF_GAINSTAGES__LNA5G_CAP__WIDTH 2 +#define RXRF_GAINSTAGES__LNA5G_CAP__MASK 0x00000030U +#define RXRF_GAINSTAGES__LNA5G_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define RXRF_GAINSTAGES__LNA5G_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define RXRF_GAINSTAGES__LNA5G_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define RXRF_GAINSTAGES__LNA5G_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field LNA5G_SHORTINP */ +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__SHIFT 6 +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__WIDTH 1 +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__MASK 0x00000040U +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RXRF_GAINSTAGES__LNA5G_SHORTINP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field PWD_LO5G */ +#define RXRF_GAINSTAGES__PWD_LO5G__SHIFT 7 +#define RXRF_GAINSTAGES__PWD_LO5G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_LO5G__MASK 0x00000080U +#define RXRF_GAINSTAGES__PWD_LO5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RXRF_GAINSTAGES__PWD_LO5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RXRF_GAINSTAGES__PWD_LO5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RXRF_GAINSTAGES__PWD_LO5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RXRF_GAINSTAGES__PWD_LO5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RXRF_GAINSTAGES__PWD_LO5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field PWD_VGA5G */ +#define RXRF_GAINSTAGES__PWD_VGA5G__SHIFT 8 +#define RXRF_GAINSTAGES__PWD_VGA5G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_VGA5G__MASK 0x00000100U +#define RXRF_GAINSTAGES__PWD_VGA5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define RXRF_GAINSTAGES__PWD_VGA5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define RXRF_GAINSTAGES__PWD_VGA5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RXRF_GAINSTAGES__PWD_VGA5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RXRF_GAINSTAGES__PWD_VGA5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RXRF_GAINSTAGES__PWD_VGA5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field PWD_MXR5G */ +#define RXRF_GAINSTAGES__PWD_MXR5G__SHIFT 9 +#define RXRF_GAINSTAGES__PWD_MXR5G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_MXR5G__MASK 0x00000200U +#define RXRF_GAINSTAGES__PWD_MXR5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define RXRF_GAINSTAGES__PWD_MXR5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define RXRF_GAINSTAGES__PWD_MXR5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define RXRF_GAINSTAGES__PWD_MXR5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define RXRF_GAINSTAGES__PWD_MXR5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define RXRF_GAINSTAGES__PWD_MXR5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field PWD_LNA5G */ +#define RXRF_GAINSTAGES__PWD_LNA5G__SHIFT 10 +#define RXRF_GAINSTAGES__PWD_LNA5G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_LNA5G__MASK 0x00000400U +#define RXRF_GAINSTAGES__PWD_LNA5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define RXRF_GAINSTAGES__PWD_LNA5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define RXRF_GAINSTAGES__PWD_LNA5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RXRF_GAINSTAGES__PWD_LNA5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RXRF_GAINSTAGES__PWD_LNA5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RXRF_GAINSTAGES__PWD_LNA5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field LNA2G_CAP */ +#define RXRF_GAINSTAGES__LNA2G_CAP__SHIFT 11 +#define RXRF_GAINSTAGES__LNA2G_CAP__WIDTH 2 +#define RXRF_GAINSTAGES__LNA2G_CAP__MASK 0x00001800U +#define RXRF_GAINSTAGES__LNA2G_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001800U) >> 11) +#define RXRF_GAINSTAGES__LNA2G_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00001800U) +#define RXRF_GAINSTAGES__LNA2G_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define RXRF_GAINSTAGES__LNA2G_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field LNA2G_SHORTINP */ +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__SHIFT 13 +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__WIDTH 1 +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__MASK 0x00002000U +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RXRF_GAINSTAGES__LNA2G_SHORTINP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field LNA2G_LP */ +#define RXRF_GAINSTAGES__LNA2G_LP__SHIFT 14 +#define RXRF_GAINSTAGES__LNA2G_LP__WIDTH 1 +#define RXRF_GAINSTAGES__LNA2G_LP__MASK 0x00004000U +#define RXRF_GAINSTAGES__LNA2G_LP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RXRF_GAINSTAGES__LNA2G_LP__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RXRF_GAINSTAGES__LNA2G_LP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RXRF_GAINSTAGES__LNA2G_LP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RXRF_GAINSTAGES__LNA2G_LP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RXRF_GAINSTAGES__LNA2G_LP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field PWD_LO2G */ +#define RXRF_GAINSTAGES__PWD_LO2G__SHIFT 15 +#define RXRF_GAINSTAGES__PWD_LO2G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_LO2G__MASK 0x00008000U +#define RXRF_GAINSTAGES__PWD_LO2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define RXRF_GAINSTAGES__PWD_LO2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define RXRF_GAINSTAGES__PWD_LO2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define RXRF_GAINSTAGES__PWD_LO2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define RXRF_GAINSTAGES__PWD_LO2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define RXRF_GAINSTAGES__PWD_LO2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field PWD_MXR2G */ +#define RXRF_GAINSTAGES__PWD_MXR2G__SHIFT 16 +#define RXRF_GAINSTAGES__PWD_MXR2G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_MXR2G__MASK 0x00010000U +#define RXRF_GAINSTAGES__PWD_MXR2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define RXRF_GAINSTAGES__PWD_MXR2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define RXRF_GAINSTAGES__PWD_MXR2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define RXRF_GAINSTAGES__PWD_MXR2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define RXRF_GAINSTAGES__PWD_MXR2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define RXRF_GAINSTAGES__PWD_MXR2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field PWD_LNA2G */ +#define RXRF_GAINSTAGES__PWD_LNA2G__SHIFT 17 +#define RXRF_GAINSTAGES__PWD_LNA2G__WIDTH 1 +#define RXRF_GAINSTAGES__PWD_LNA2G__MASK 0x00020000U +#define RXRF_GAINSTAGES__PWD_LNA2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define RXRF_GAINSTAGES__PWD_LNA2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define RXRF_GAINSTAGES__PWD_LNA2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RXRF_GAINSTAGES__PWD_LNA2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RXRF_GAINSTAGES__PWD_LNA2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RXRF_GAINSTAGES__PWD_LNA2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field MXR5G_GAIN_OVR */ +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__SHIFT 18 +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__WIDTH 2 +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__MASK 0x000c0000U +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x000c0000U) >> 18) +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field VGA5G_GAIN_OVR */ +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__SHIFT 20 +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__WIDTH 3 +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__MASK 0x00700000U +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field LNA5G_GAIN_OVR */ +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__SHIFT 23 +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__WIDTH 3 +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__MASK 0x03800000U +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field MXR2G_GAIN_OVR */ +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__SHIFT 26 +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__WIDTH 2 +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__MASK 0x0c000000U +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0c000000U) >> 26) +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x0c000000U) +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) + +/* macros for field LNA2G_GAIN_OVR */ +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__SHIFT 28 +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__WIDTH 3 +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__MASK 0x70000000U +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x70000000U) >> 28) +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x70000000U) +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x70000000U) | (((u_int32_t)(src) <<\ + 28) & 0x70000000U) +#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x70000000U))) + +/* macros for field RX_OVERRIDE */ +#define RXRF_GAINSTAGES__RX_OVERRIDE__SHIFT 31 +#define RXRF_GAINSTAGES__RX_OVERRIDE__WIDTH 1 +#define RXRF_GAINSTAGES__RX_OVERRIDE__MASK 0x80000000U +#define RXRF_GAINSTAGES__RX_OVERRIDE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RXRF_GAINSTAGES__RX_OVERRIDE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RXRF_GAINSTAGES__RX_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RXRF_GAINSTAGES__RX_OVERRIDE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RXRF_GAINSTAGES__RX_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RXRF_GAINSTAGES__RX_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RXRF_GAINSTAGES__TYPE u_int32_t +#define RXRF_GAINSTAGES__READ 0xffffffffU +#define RXRF_GAINSTAGES__WRITE 0xffffffffU + +#endif /* __RXRF_GAINSTAGES_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_RXRF_GAINSTAGES */ +#define INST_RADIO65_REG_MAP__CH0_RXRF_GAINSTAGES__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXRF_AGC */ +#ifndef __RXRF_AGC_MACRO__ +#define __RXRF_AGC_MACRO__ + +/* macros for field RF5G_ON_DURING_CALPA */ +#define RXRF_AGC__RF5G_ON_DURING_CALPA__SHIFT 0 +#define RXRF_AGC__RF5G_ON_DURING_CALPA__WIDTH 1 +#define RXRF_AGC__RF5G_ON_DURING_CALPA__MASK 0x00000001U +#define RXRF_AGC__RF5G_ON_DURING_CALPA__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RXRF_AGC__RF5G_ON_DURING_CALPA__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RXRF_AGC__RF5G_ON_DURING_CALPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXRF_AGC__RF5G_ON_DURING_CALPA__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RXRF_AGC__RF5G_ON_DURING_CALPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXRF_AGC__RF5G_ON_DURING_CALPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field RF2G_ON_DURING_CALPA */ +#define RXRF_AGC__RF2G_ON_DURING_CALPA__SHIFT 1 +#define RXRF_AGC__RF2G_ON_DURING_CALPA__WIDTH 1 +#define RXRF_AGC__RF2G_ON_DURING_CALPA__MASK 0x00000002U +#define RXRF_AGC__RF2G_ON_DURING_CALPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RXRF_AGC__RF2G_ON_DURING_CALPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RXRF_AGC__RF2G_ON_DURING_CALPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RXRF_AGC__RF2G_ON_DURING_CALPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RXRF_AGC__RF2G_ON_DURING_CALPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RXRF_AGC__RF2G_ON_DURING_CALPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field AGC_OUT */ +#define RXRF_AGC__AGC_OUT__SHIFT 2 +#define RXRF_AGC__AGC_OUT__WIDTH 1 +#define RXRF_AGC__AGC_OUT__MASK 0x00000004U +#define RXRF_AGC__AGC_OUT__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define RXRF_AGC__AGC_OUT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RXRF_AGC__AGC_OUT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field LNABUFGAIN2X */ +#define RXRF_AGC__LNABUFGAIN2X__SHIFT 3 +#define RXRF_AGC__LNABUFGAIN2X__WIDTH 1 +#define RXRF_AGC__LNABUFGAIN2X__MASK 0x00000008U +#define RXRF_AGC__LNABUFGAIN2X__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RXRF_AGC__LNABUFGAIN2X__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RXRF_AGC__LNABUFGAIN2X__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RXRF_AGC__LNABUFGAIN2X__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RXRF_AGC__LNABUFGAIN2X__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RXRF_AGC__LNABUFGAIN2X__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field LNABUF_PWD_OVR */ +#define RXRF_AGC__LNABUF_PWD_OVR__SHIFT 4 +#define RXRF_AGC__LNABUF_PWD_OVR__WIDTH 1 +#define RXRF_AGC__LNABUF_PWD_OVR__MASK 0x00000010U +#define RXRF_AGC__LNABUF_PWD_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RXRF_AGC__LNABUF_PWD_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RXRF_AGC__LNABUF_PWD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RXRF_AGC__LNABUF_PWD_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RXRF_AGC__LNABUF_PWD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RXRF_AGC__LNABUF_PWD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PWD_LNABUF */ +#define RXRF_AGC__PWD_LNABUF__SHIFT 5 +#define RXRF_AGC__PWD_LNABUF__WIDTH 1 +#define RXRF_AGC__PWD_LNABUF__MASK 0x00000020U +#define RXRF_AGC__PWD_LNABUF__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define RXRF_AGC__PWD_LNABUF__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RXRF_AGC__PWD_LNABUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RXRF_AGC__PWD_LNABUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RXRF_AGC__PWD_LNABUF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RXRF_AGC__PWD_LNABUF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field AGC_FALL_CTRL */ +#define RXRF_AGC__AGC_FALL_CTRL__SHIFT 6 +#define RXRF_AGC__AGC_FALL_CTRL__WIDTH 3 +#define RXRF_AGC__AGC_FALL_CTRL__MASK 0x000001c0U +#define RXRF_AGC__AGC_FALL_CTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001c0U) >> 6) +#define RXRF_AGC__AGC_FALL_CTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000001c0U) +#define RXRF_AGC__AGC_FALL_CTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define RXRF_AGC__AGC_FALL_CTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field AGC5G_CALDAC_OVR */ +#define RXRF_AGC__AGC5G_CALDAC_OVR__SHIFT 9 +#define RXRF_AGC__AGC5G_CALDAC_OVR__WIDTH 6 +#define RXRF_AGC__AGC5G_CALDAC_OVR__MASK 0x00007e00U +#define RXRF_AGC__AGC5G_CALDAC_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007e00U) >> 9) +#define RXRF_AGC__AGC5G_CALDAC_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00007e00U) +#define RXRF_AGC__AGC5G_CALDAC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00007e00U) +#define RXRF_AGC__AGC5G_CALDAC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00007e00U))) + +/* macros for field AGC5G_DBDAC_OVR */ +#define RXRF_AGC__AGC5G_DBDAC_OVR__SHIFT 15 +#define RXRF_AGC__AGC5G_DBDAC_OVR__WIDTH 4 +#define RXRF_AGC__AGC5G_DBDAC_OVR__MASK 0x00078000U +#define RXRF_AGC__AGC5G_DBDAC_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00078000U) >> 15) +#define RXRF_AGC__AGC5G_DBDAC_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00078000U) +#define RXRF_AGC__AGC5G_DBDAC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00078000U) | (((u_int32_t)(src) <<\ + 15) & 0x00078000U) +#define RXRF_AGC__AGC5G_DBDAC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00078000U))) + +/* macros for field AGC2G_CALDAC_OVR */ +#define RXRF_AGC__AGC2G_CALDAC_OVR__SHIFT 19 +#define RXRF_AGC__AGC2G_CALDAC_OVR__WIDTH 6 +#define RXRF_AGC__AGC2G_CALDAC_OVR__MASK 0x01f80000U +#define RXRF_AGC__AGC2G_CALDAC_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x01f80000U) >> 19) +#define RXRF_AGC__AGC2G_CALDAC_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x01f80000U) +#define RXRF_AGC__AGC2G_CALDAC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01f80000U) | (((u_int32_t)(src) <<\ + 19) & 0x01f80000U) +#define RXRF_AGC__AGC2G_CALDAC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x01f80000U))) + +/* macros for field AGC2G_DBDAC_OVR */ +#define RXRF_AGC__AGC2G_DBDAC_OVR__SHIFT 25 +#define RXRF_AGC__AGC2G_DBDAC_OVR__WIDTH 4 +#define RXRF_AGC__AGC2G_DBDAC_OVR__MASK 0x1e000000U +#define RXRF_AGC__AGC2G_DBDAC_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x1e000000U) >> 25) +#define RXRF_AGC__AGC2G_DBDAC_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x1e000000U) +#define RXRF_AGC__AGC2G_DBDAC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x1e000000U) +#define RXRF_AGC__AGC2G_DBDAC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x1e000000U))) + +/* macros for field AGC_CAL_OVR */ +#define RXRF_AGC__AGC_CAL_OVR__SHIFT 29 +#define RXRF_AGC__AGC_CAL_OVR__WIDTH 1 +#define RXRF_AGC__AGC_CAL_OVR__MASK 0x20000000U +#define RXRF_AGC__AGC_CAL_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define RXRF_AGC__AGC_CAL_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define RXRF_AGC__AGC_CAL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RXRF_AGC__AGC_CAL_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RXRF_AGC__AGC_CAL_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RXRF_AGC__AGC_CAL_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field AGC_ON_OVR */ +#define RXRF_AGC__AGC_ON_OVR__SHIFT 30 +#define RXRF_AGC__AGC_ON_OVR__WIDTH 1 +#define RXRF_AGC__AGC_ON_OVR__MASK 0x40000000U +#define RXRF_AGC__AGC_ON_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define RXRF_AGC__AGC_ON_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define RXRF_AGC__AGC_ON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RXRF_AGC__AGC_ON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RXRF_AGC__AGC_ON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RXRF_AGC__AGC_ON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field AGC_OVERRIDE */ +#define RXRF_AGC__AGC_OVERRIDE__SHIFT 31 +#define RXRF_AGC__AGC_OVERRIDE__WIDTH 1 +#define RXRF_AGC__AGC_OVERRIDE__MASK 0x80000000U +#define RXRF_AGC__AGC_OVERRIDE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define RXRF_AGC__AGC_OVERRIDE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RXRF_AGC__AGC_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RXRF_AGC__AGC_OVERRIDE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RXRF_AGC__AGC_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RXRF_AGC__AGC_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RXRF_AGC__TYPE u_int32_t +#define RXRF_AGC__READ 0xffffffffU +#define RXRF_AGC__WRITE 0xffffffffU + +#endif /* __RXRF_AGC_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_RXRF_AGC */ +#define INST_RADIO65_REG_MAP__CH0_RXRF_AGC__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF1 */ +#ifndef __TXRF1_MACRO__ +#define __TXRF1_MACRO__ + +/* macros for field pdlobuf5G */ +#define TXRF1__PDLOBUF5G__SHIFT 0 +#define TXRF1__PDLOBUF5G__WIDTH 1 +#define TXRF1__PDLOBUF5G__MASK 0x00000001U +#define TXRF1__PDLOBUF5G__READ(src) (u_int32_t)(src) & 0x00000001U +#define TXRF1__PDLOBUF5G__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TXRF1__PDLOBUF5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TXRF1__PDLOBUF5G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TXRF1__PDLOBUF5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXRF1__PDLOBUF5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field pdlodiv5G */ +#define TXRF1__PDLODIV5G__SHIFT 1 +#define TXRF1__PDLODIV5G__WIDTH 1 +#define TXRF1__PDLODIV5G__MASK 0x00000002U +#define TXRF1__PDLODIV5G__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define TXRF1__PDLODIV5G__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define TXRF1__PDLODIV5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define TXRF1__PDLODIV5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define TXRF1__PDLODIV5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TXRF1__PDLODIV5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field LObuf5Gforced */ +#define TXRF1__LOBUF5GFORCED__SHIFT 2 +#define TXRF1__LOBUF5GFORCED__WIDTH 1 +#define TXRF1__LOBUF5GFORCED__MASK 0x00000004U +#define TXRF1__LOBUF5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define TXRF1__LOBUF5GFORCED__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define TXRF1__LOBUF5GFORCED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define TXRF1__LOBUF5GFORCED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define TXRF1__LOBUF5GFORCED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TXRF1__LOBUF5GFORCED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field LOdiv5Gforced */ +#define TXRF1__LODIV5GFORCED__SHIFT 3 +#define TXRF1__LODIV5GFORCED__WIDTH 1 +#define TXRF1__LODIV5GFORCED__MASK 0x00000008U +#define TXRF1__LODIV5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define TXRF1__LODIV5GFORCED__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define TXRF1__LODIV5GFORCED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TXRF1__LODIV5GFORCED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define TXRF1__LODIV5GFORCED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TXRF1__LODIV5GFORCED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field padrv2gn5G */ +#define TXRF1__PADRV2GN5G__SHIFT 4 +#define TXRF1__PADRV2GN5G__WIDTH 4 +#define TXRF1__PADRV2GN5G__MASK 0x000000f0U +#define TXRF1__PADRV2GN5G__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) +#define TXRF1__PADRV2GN5G__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) +#define TXRF1__PADRV2GN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define TXRF1__PADRV2GN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field padrv3gn5G */ +#define TXRF1__PADRV3GN5G__SHIFT 8 +#define TXRF1__PADRV3GN5G__WIDTH 4 +#define TXRF1__PADRV3GN5G__MASK 0x00000f00U +#define TXRF1__PADRV3GN5G__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) +#define TXRF1__PADRV3GN5G__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) +#define TXRF1__PADRV3GN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define TXRF1__PADRV3GN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field padrv4gn5G */ +#define TXRF1__PADRV4GN5G__SHIFT 12 +#define TXRF1__PADRV4GN5G__WIDTH 4 +#define TXRF1__PADRV4GN5G__MASK 0x0000f000U +#define TXRF1__PADRV4GN5G__READ(src) (((u_int32_t)(src) & 0x0000f000U) >> 12) +#define TXRF1__PADRV4GN5G__WRITE(src) (((u_int32_t)(src) << 12) & 0x0000f000U) +#define TXRF1__PADRV4GN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define TXRF1__PADRV4GN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field localtxgain5G */ +#define TXRF1__LOCALTXGAIN5G__SHIFT 16 +#define TXRF1__LOCALTXGAIN5G__WIDTH 1 +#define TXRF1__LOCALTXGAIN5G__MASK 0x00010000U +#define TXRF1__LOCALTXGAIN5G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define TXRF1__LOCALTXGAIN5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define TXRF1__LOCALTXGAIN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define TXRF1__LOCALTXGAIN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define TXRF1__LOCALTXGAIN5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define TXRF1__LOCALTXGAIN5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field pdout2G */ +#define TXRF1__PDOUT2G__SHIFT 17 +#define TXRF1__PDOUT2G__WIDTH 1 +#define TXRF1__PDOUT2G__MASK 0x00020000U +#define TXRF1__PDOUT2G__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17) +#define TXRF1__PDOUT2G__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U) +#define TXRF1__PDOUT2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define TXRF1__PDOUT2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define TXRF1__PDOUT2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define TXRF1__PDOUT2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field pdDR2G */ +#define TXRF1__PDDR2G__SHIFT 18 +#define TXRF1__PDDR2G__WIDTH 1 +#define TXRF1__PDDR2G__MASK 0x00040000U +#define TXRF1__PDDR2G__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define TXRF1__PDDR2G__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define TXRF1__PDDR2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define TXRF1__PDDR2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define TXRF1__PDDR2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define TXRF1__PDDR2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field pdmxr2G */ +#define TXRF1__PDMXR2G__SHIFT 19 +#define TXRF1__PDMXR2G__WIDTH 1 +#define TXRF1__PDMXR2G__MASK 0x00080000U +#define TXRF1__PDMXR2G__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) +#define TXRF1__PDMXR2G__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) +#define TXRF1__PDMXR2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TXRF1__PDMXR2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TXRF1__PDMXR2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TXRF1__PDMXR2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field pdlobuf2G */ +#define TXRF1__PDLOBUF2G__SHIFT 20 +#define TXRF1__PDLOBUF2G__WIDTH 1 +#define TXRF1__PDLOBUF2G__MASK 0x00100000U +#define TXRF1__PDLOBUF2G__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define TXRF1__PDLOBUF2G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) +#define TXRF1__PDLOBUF2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TXRF1__PDLOBUF2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TXRF1__PDLOBUF2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TXRF1__PDLOBUF2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field pdlodiv2G */ +#define TXRF1__PDLODIV2G__SHIFT 21 +#define TXRF1__PDLODIV2G__WIDTH 1 +#define TXRF1__PDLODIV2G__MASK 0x00200000U +#define TXRF1__PDLODIV2G__READ(src) (((u_int32_t)(src) & 0x00200000U) >> 21) +#define TXRF1__PDLODIV2G__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U) +#define TXRF1__PDLODIV2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define TXRF1__PDLODIV2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define TXRF1__PDLODIV2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define TXRF1__PDLODIV2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field LObuf2Gforced */ +#define TXRF1__LOBUF2GFORCED__SHIFT 22 +#define TXRF1__LOBUF2GFORCED__WIDTH 1 +#define TXRF1__LOBUF2GFORCED__MASK 0x00400000U +#define TXRF1__LOBUF2GFORCED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define TXRF1__LOBUF2GFORCED__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define TXRF1__LOBUF2GFORCED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TXRF1__LOBUF2GFORCED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TXRF1__LOBUF2GFORCED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TXRF1__LOBUF2GFORCED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field LOdiv2Gforced */ +#define TXRF1__LODIV2GFORCED__SHIFT 23 +#define TXRF1__LODIV2GFORCED__WIDTH 1 +#define TXRF1__LODIV2GFORCED__MASK 0x00800000U +#define TXRF1__LODIV2GFORCED__READ(src) \ + (((u_int32_t)(src)\ + & 0x00800000U) >> 23) +#define TXRF1__LODIV2GFORCED__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x00800000U) +#define TXRF1__LODIV2GFORCED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TXRF1__LODIV2GFORCED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TXRF1__LODIV2GFORCED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TXRF1__LODIV2GFORCED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field padrvgn2G */ +#define TXRF1__PADRVGN2G__SHIFT 24 +#define TXRF1__PADRVGN2G__WIDTH 7 +#define TXRF1__PADRVGN2G__MASK 0x7f000000U +#define TXRF1__PADRVGN2G__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24) +#define TXRF1__PADRVGN2G__WRITE(src) (((u_int32_t)(src) << 24) & 0x7f000000U) +#define TXRF1__PADRVGN2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define TXRF1__PADRVGN2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) + +/* macros for field localtxgain2G */ +#define TXRF1__LOCALTXGAIN2G__SHIFT 31 +#define TXRF1__LOCALTXGAIN2G__WIDTH 1 +#define TXRF1__LOCALTXGAIN2G__MASK 0x80000000U +#define TXRF1__LOCALTXGAIN2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define TXRF1__LOCALTXGAIN2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TXRF1__LOCALTXGAIN2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TXRF1__LOCALTXGAIN2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TXRF1__LOCALTXGAIN2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TXRF1__LOCALTXGAIN2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TXRF1__TYPE u_int32_t +#define TXRF1__READ 0xffffffffU +#define TXRF1__WRITE 0xffffffffU + +#endif /* __TXRF1_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_TXRF1 */ +#define INST_RADIO65_REG_MAP__CH0_TXRF1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF2 */ +#ifndef __TXRF2_MACRO__ +#define __TXRF2_MACRO__ + +/* macros for field d3b5G */ +#define TXRF2__D3B5G__SHIFT 0 +#define TXRF2__D3B5G__WIDTH 3 +#define TXRF2__D3B5G__MASK 0x00000007U +#define TXRF2__D3B5G__READ(src) (u_int32_t)(src) & 0x00000007U +#define TXRF2__D3B5G__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define TXRF2__D3B5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define TXRF2__D3B5G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) + +/* macros for field d4b5G */ +#define TXRF2__D4B5G__SHIFT 3 +#define TXRF2__D4B5G__WIDTH 3 +#define TXRF2__D4B5G__MASK 0x00000038U +#define TXRF2__D4B5G__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3) +#define TXRF2__D4B5G__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000038U) +#define TXRF2__D4B5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define TXRF2__D4B5G__VERIFY(src) (!((((u_int32_t)(src) << 3) & ~0x00000038U))) + +/* macros for field ocas2G */ +#define TXRF2__OCAS2G__SHIFT 6 +#define TXRF2__OCAS2G__WIDTH 3 +#define TXRF2__OCAS2G__MASK 0x000001c0U +#define TXRF2__OCAS2G__READ(src) (((u_int32_t)(src) & 0x000001c0U) >> 6) +#define TXRF2__OCAS2G__WRITE(src) (((u_int32_t)(src) << 6) & 0x000001c0U) +#define TXRF2__OCAS2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define TXRF2__OCAS2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field dcas2G */ +#define TXRF2__DCAS2G__SHIFT 9 +#define TXRF2__DCAS2G__WIDTH 3 +#define TXRF2__DCAS2G__MASK 0x00000e00U +#define TXRF2__DCAS2G__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) +#define TXRF2__DCAS2G__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U) +#define TXRF2__DCAS2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define TXRF2__DCAS2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field ob2G_paloff */ +#define TXRF2__OB2G_PALOFF__SHIFT 12 +#define TXRF2__OB2G_PALOFF__WIDTH 3 +#define TXRF2__OB2G_PALOFF__MASK 0x00007000U +#define TXRF2__OB2G_PALOFF__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12) +#define TXRF2__OB2G_PALOFF__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U) +#define TXRF2__OB2G_PALOFF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define TXRF2__OB2G_PALOFF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field ob2G_qam */ +#define TXRF2__OB2G_QAM__SHIFT 15 +#define TXRF2__OB2G_QAM__WIDTH 3 +#define TXRF2__OB2G_QAM__MASK 0x00038000U +#define TXRF2__OB2G_QAM__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) +#define TXRF2__OB2G_QAM__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) +#define TXRF2__OB2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define TXRF2__OB2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field ob2G_psk */ +#define TXRF2__OB2G_PSK__SHIFT 18 +#define TXRF2__OB2G_PSK__WIDTH 3 +#define TXRF2__OB2G_PSK__MASK 0x001c0000U +#define TXRF2__OB2G_PSK__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18) +#define TXRF2__OB2G_PSK__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U) +#define TXRF2__OB2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define TXRF2__OB2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field ob2G_cck */ +#define TXRF2__OB2G_CCK__SHIFT 21 +#define TXRF2__OB2G_CCK__WIDTH 3 +#define TXRF2__OB2G_CCK__MASK 0x00e00000U +#define TXRF2__OB2G_CCK__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21) +#define TXRF2__OB2G_CCK__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U) +#define TXRF2__OB2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define TXRF2__OB2G_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field db2G */ +#define TXRF2__DB2G__SHIFT 24 +#define TXRF2__DB2G__WIDTH 3 +#define TXRF2__DB2G__MASK 0x07000000U +#define TXRF2__DB2G__READ(src) (((u_int32_t)(src) & 0x07000000U) >> 24) +#define TXRF2__DB2G__WRITE(src) (((u_int32_t)(src) << 24) & 0x07000000U) +#define TXRF2__DB2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define TXRF2__DB2G__VERIFY(src) (!((((u_int32_t)(src) << 24) & ~0x07000000U))) + +/* macros for field pdout5G */ +#define TXRF2__PDOUT5G__SHIFT 27 +#define TXRF2__PDOUT5G__WIDTH 4 +#define TXRF2__PDOUT5G__MASK 0x78000000U +#define TXRF2__PDOUT5G__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define TXRF2__PDOUT5G__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define TXRF2__PDOUT5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define TXRF2__PDOUT5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) + +/* macros for field pdmxr5G */ +#define TXRF2__PDMXR5G__SHIFT 31 +#define TXRF2__PDMXR5G__WIDTH 1 +#define TXRF2__PDMXR5G__MASK 0x80000000U +#define TXRF2__PDMXR5G__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define TXRF2__PDMXR5G__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) +#define TXRF2__PDMXR5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TXRF2__PDMXR5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TXRF2__PDMXR5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TXRF2__PDMXR5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TXRF2__TYPE u_int32_t +#define TXRF2__READ 0xffffffffU +#define TXRF2__WRITE 0xffffffffU + +#endif /* __TXRF2_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_TXRF2 */ +#define INST_RADIO65_REG_MAP__CH0_TXRF2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF3 */ +#ifndef __TXRF3_MACRO__ +#define __TXRF3_MACRO__ + +/* macros for field filtR2G */ +#define TXRF3__FILTR2G__SHIFT 0 +#define TXRF3__FILTR2G__WIDTH 2 +#define TXRF3__FILTR2G__MASK 0x00000003U +#define TXRF3__FILTR2G__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXRF3__FILTR2G__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXRF3__FILTR2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXRF3__FILTR2G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field pwdFB2_2G */ +#define TXRF3__PWDFB2_2G__SHIFT 2 +#define TXRF3__PWDFB2_2G__WIDTH 1 +#define TXRF3__PWDFB2_2G__MASK 0x00000004U +#define TXRF3__PWDFB2_2G__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define TXRF3__PWDFB2_2G__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define TXRF3__PWDFB2_2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define TXRF3__PWDFB2_2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define TXRF3__PWDFB2_2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TXRF3__PWDFB2_2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field pwdFB1_2G */ +#define TXRF3__PWDFB1_2G__SHIFT 3 +#define TXRF3__PWDFB1_2G__WIDTH 1 +#define TXRF3__PWDFB1_2G__MASK 0x00000008U +#define TXRF3__PWDFB1_2G__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define TXRF3__PWDFB1_2G__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define TXRF3__PWDFB1_2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TXRF3__PWDFB1_2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define TXRF3__PWDFB1_2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TXRF3__PWDFB1_2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field pdFB2G */ +#define TXRF3__PDFB2G__SHIFT 4 +#define TXRF3__PDFB2G__WIDTH 1 +#define TXRF3__PDFB2G__MASK 0x00000010U +#define TXRF3__PDFB2G__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) +#define TXRF3__PDFB2G__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) +#define TXRF3__PDFB2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define TXRF3__PDFB2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define TXRF3__PDFB2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define TXRF3__PDFB2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field rdiv5G */ +#define TXRF3__RDIV5G__SHIFT 5 +#define TXRF3__RDIV5G__WIDTH 2 +#define TXRF3__RDIV5G__MASK 0x00000060U +#define TXRF3__RDIV5G__READ(src) (((u_int32_t)(src) & 0x00000060U) >> 5) +#define TXRF3__RDIV5G__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000060U) +#define TXRF3__RDIV5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000060U) | (((u_int32_t)(src) <<\ + 5) & 0x00000060U) +#define TXRF3__RDIV5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000060U))) + +/* macros for field capdiv5G */ +#define TXRF3__CAPDIV5G__SHIFT 7 +#define TXRF3__CAPDIV5G__WIDTH 3 +#define TXRF3__CAPDIV5G__MASK 0x00000380U +#define TXRF3__CAPDIV5G__READ(src) (((u_int32_t)(src) & 0x00000380U) >> 7) +#define TXRF3__CAPDIV5G__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000380U) +#define TXRF3__CAPDIV5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000380U) | (((u_int32_t)(src) <<\ + 7) & 0x00000380U) +#define TXRF3__CAPDIV5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000380U))) + +/* macros for field pdpredist5G */ +#define TXRF3__PDPREDIST5G__SHIFT 10 +#define TXRF3__PDPREDIST5G__WIDTH 1 +#define TXRF3__PDPREDIST5G__MASK 0x00000400U +#define TXRF3__PDPREDIST5G__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define TXRF3__PDPREDIST5G__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) +#define TXRF3__PDPREDIST5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TXRF3__PDPREDIST5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TXRF3__PDPREDIST5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TXRF3__PDPREDIST5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field rdiv2G */ +#define TXRF3__RDIV2G__SHIFT 11 +#define TXRF3__RDIV2G__WIDTH 2 +#define TXRF3__RDIV2G__MASK 0x00001800U +#define TXRF3__RDIV2G__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11) +#define TXRF3__RDIV2G__WRITE(src) (((u_int32_t)(src) << 11) & 0x00001800U) +#define TXRF3__RDIV2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define TXRF3__RDIV2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field pdpredist2G */ +#define TXRF3__PDPREDIST2G__SHIFT 13 +#define TXRF3__PDPREDIST2G__WIDTH 1 +#define TXRF3__PDPREDIST2G__MASK 0x00002000U +#define TXRF3__PDPREDIST2G__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) +#define TXRF3__PDPREDIST2G__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U) +#define TXRF3__PDPREDIST2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TXRF3__PDPREDIST2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TXRF3__PDPREDIST2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TXRF3__PDPREDIST2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field ocas5G */ +#define TXRF3__OCAS5G__SHIFT 14 +#define TXRF3__OCAS5G__WIDTH 3 +#define TXRF3__OCAS5G__MASK 0x0001c000U +#define TXRF3__OCAS5G__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) +#define TXRF3__OCAS5G__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U) +#define TXRF3__OCAS5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define TXRF3__OCAS5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field d2cas5G */ +#define TXRF3__D2CAS5G__SHIFT 17 +#define TXRF3__D2CAS5G__WIDTH 3 +#define TXRF3__D2CAS5G__MASK 0x000e0000U +#define TXRF3__D2CAS5G__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) +#define TXRF3__D2CAS5G__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) +#define TXRF3__D2CAS5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define TXRF3__D2CAS5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field d3cas5G */ +#define TXRF3__D3CAS5G__SHIFT 20 +#define TXRF3__D3CAS5G__WIDTH 3 +#define TXRF3__D3CAS5G__MASK 0x00700000U +#define TXRF3__D3CAS5G__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) +#define TXRF3__D3CAS5G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) +#define TXRF3__D3CAS5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define TXRF3__D3CAS5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field d4cas5G */ +#define TXRF3__D4CAS5G__SHIFT 23 +#define TXRF3__D4CAS5G__WIDTH 3 +#define TXRF3__D4CAS5G__MASK 0x03800000U +#define TXRF3__D4CAS5G__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) +#define TXRF3__D4CAS5G__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) +#define TXRF3__D4CAS5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define TXRF3__D4CAS5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field ob5G */ +#define TXRF3__OB5G__SHIFT 26 +#define TXRF3__OB5G__WIDTH 3 +#define TXRF3__OB5G__MASK 0x1c000000U +#define TXRF3__OB5G__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define TXRF3__OB5G__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define TXRF3__OB5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TXRF3__OB5G__VERIFY(src) (!((((u_int32_t)(src) << 26) & ~0x1c000000U))) + +/* macros for field d2b5G */ +#define TXRF3__D2B5G__SHIFT 29 +#define TXRF3__D2B5G__WIDTH 3 +#define TXRF3__D2B5G__MASK 0xe0000000U +#define TXRF3__D2B5G__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define TXRF3__D2B5G__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define TXRF3__D2B5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define TXRF3__D2B5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define TXRF3__TYPE u_int32_t +#define TXRF3__READ 0xffffffffU +#define TXRF3__WRITE 0xffffffffU + +#endif /* __TXRF3_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_TXRF3 */ +#define INST_RADIO65_REG_MAP__CH0_TXRF3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF4 */ +#ifndef __TXRF4_MACRO__ +#define __TXRF4_MACRO__ + +/* macros for field pk1b2G_cck */ +#define TXRF4__PK1B2G_CCK__SHIFT 0 +#define TXRF4__PK1B2G_CCK__WIDTH 2 +#define TXRF4__PK1B2G_CCK__MASK 0x00000003U +#define TXRF4__PK1B2G_CCK__READ(src) (u_int32_t)(src) & 0x00000003U +#define TXRF4__PK1B2G_CCK__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define TXRF4__PK1B2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define TXRF4__PK1B2G_CCK__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field miob2G_qam */ +#define TXRF4__MIOB2G_QAM__SHIFT 2 +#define TXRF4__MIOB2G_QAM__WIDTH 3 +#define TXRF4__MIOB2G_QAM__MASK 0x0000001cU +#define TXRF4__MIOB2G_QAM__READ(src) (((u_int32_t)(src) & 0x0000001cU) >> 2) +#define TXRF4__MIOB2G_QAM__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000001cU) +#define TXRF4__MIOB2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define TXRF4__MIOB2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field miob2G_psk */ +#define TXRF4__MIOB2G_PSK__SHIFT 5 +#define TXRF4__MIOB2G_PSK__WIDTH 3 +#define TXRF4__MIOB2G_PSK__MASK 0x000000e0U +#define TXRF4__MIOB2G_PSK__READ(src) (((u_int32_t)(src) & 0x000000e0U) >> 5) +#define TXRF4__MIOB2G_PSK__WRITE(src) (((u_int32_t)(src) << 5) & 0x000000e0U) +#define TXRF4__MIOB2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define TXRF4__MIOB2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field miob2G_cck */ +#define TXRF4__MIOB2G_CCK__SHIFT 8 +#define TXRF4__MIOB2G_CCK__WIDTH 3 +#define TXRF4__MIOB2G_CCK__MASK 0x00000700U +#define TXRF4__MIOB2G_CCK__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) +#define TXRF4__MIOB2G_CCK__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U) +#define TXRF4__MIOB2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define TXRF4__MIOB2G_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field comp2G_qam */ +#define TXRF4__COMP2G_QAM__SHIFT 11 +#define TXRF4__COMP2G_QAM__WIDTH 3 +#define TXRF4__COMP2G_QAM__MASK 0x00003800U +#define TXRF4__COMP2G_QAM__READ(src) (((u_int32_t)(src) & 0x00003800U) >> 11) +#define TXRF4__COMP2G_QAM__WRITE(src) (((u_int32_t)(src) << 11) & 0x00003800U) +#define TXRF4__COMP2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define TXRF4__COMP2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field comp2G_psk */ +#define TXRF4__COMP2G_PSK__SHIFT 14 +#define TXRF4__COMP2G_PSK__WIDTH 3 +#define TXRF4__COMP2G_PSK__MASK 0x0001c000U +#define TXRF4__COMP2G_PSK__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) +#define TXRF4__COMP2G_PSK__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U) +#define TXRF4__COMP2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define TXRF4__COMP2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field comp2G_cck */ +#define TXRF4__COMP2G_CCK__SHIFT 17 +#define TXRF4__COMP2G_CCK__WIDTH 3 +#define TXRF4__COMP2G_CCK__MASK 0x000e0000U +#define TXRF4__COMP2G_CCK__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) +#define TXRF4__COMP2G_CCK__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) +#define TXRF4__COMP2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define TXRF4__COMP2G_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field amp2b2G_qam */ +#define TXRF4__AMP2B2G_QAM__SHIFT 20 +#define TXRF4__AMP2B2G_QAM__WIDTH 3 +#define TXRF4__AMP2B2G_QAM__MASK 0x00700000U +#define TXRF4__AMP2B2G_QAM__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) +#define TXRF4__AMP2B2G_QAM__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) +#define TXRF4__AMP2B2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define TXRF4__AMP2B2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field amp2b2G_psk */ +#define TXRF4__AMP2B2G_PSK__SHIFT 23 +#define TXRF4__AMP2B2G_PSK__WIDTH 3 +#define TXRF4__AMP2B2G_PSK__MASK 0x03800000U +#define TXRF4__AMP2B2G_PSK__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) +#define TXRF4__AMP2B2G_PSK__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) +#define TXRF4__AMP2B2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define TXRF4__AMP2B2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field amp2b2G_cck */ +#define TXRF4__AMP2B2G_CCK__SHIFT 26 +#define TXRF4__AMP2B2G_CCK__WIDTH 3 +#define TXRF4__AMP2B2G_CCK__MASK 0x1c000000U +#define TXRF4__AMP2B2G_CCK__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define TXRF4__AMP2B2G_CCK__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define TXRF4__AMP2B2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define TXRF4__AMP2B2G_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field amp2cas2G */ +#define TXRF4__AMP2CAS2G__SHIFT 29 +#define TXRF4__AMP2CAS2G__WIDTH 3 +#define TXRF4__AMP2CAS2G__MASK 0xe0000000U +#define TXRF4__AMP2CAS2G__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define TXRF4__AMP2CAS2G__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define TXRF4__AMP2CAS2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define TXRF4__AMP2CAS2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define TXRF4__TYPE u_int32_t +#define TXRF4__READ 0xffffffffU +#define TXRF4__WRITE 0xffffffffU + +#endif /* __TXRF4_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_TXRF4 */ +#define INST_RADIO65_REG_MAP__CH0_TXRF4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF5 */ +#ifndef __TXRF5_MACRO__ +#define __TXRF5_MACRO__ + +/* macros for field txmodPALonly */ +#define TXRF5__TXMODPALONLY__SHIFT 0 +#define TXRF5__TXMODPALONLY__WIDTH 1 +#define TXRF5__TXMODPALONLY__MASK 0x00000001U +#define TXRF5__TXMODPALONLY__READ(src) (u_int32_t)(src) & 0x00000001U +#define TXRF5__TXMODPALONLY__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TXRF5__TXMODPALONLY__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TXRF5__TXMODPALONLY__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TXRF5__TXMODPALONLY__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXRF5__TXMODPALONLY__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field PAL_locked */ +#define TXRF5__PAL_LOCKED__SHIFT 1 +#define TXRF5__PAL_LOCKED__WIDTH 1 +#define TXRF5__PAL_LOCKED__MASK 0x00000002U +#define TXRF5__PAL_LOCKED__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define TXRF5__PAL_LOCKED__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TXRF5__PAL_LOCKED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field fbHi2G */ +#define TXRF5__FBHI2G__SHIFT 2 +#define TXRF5__FBHI2G__WIDTH 1 +#define TXRF5__FBHI2G__MASK 0x00000004U +#define TXRF5__FBHI2G__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define TXRF5__FBHI2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TXRF5__FBHI2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field fbLo2G */ +#define TXRF5__FBLO2G__SHIFT 3 +#define TXRF5__FBLO2G__WIDTH 1 +#define TXRF5__FBLO2G__MASK 0x00000008U +#define TXRF5__FBLO2G__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define TXRF5__FBLO2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TXRF5__FBLO2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field nopalgain2G */ +#define TXRF5__NOPALGAIN2G__SHIFT 4 +#define TXRF5__NOPALGAIN2G__WIDTH 1 +#define TXRF5__NOPALGAIN2G__MASK 0x00000010U +#define TXRF5__NOPALGAIN2G__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) +#define TXRF5__NOPALGAIN2G__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) +#define TXRF5__NOPALGAIN2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define TXRF5__NOPALGAIN2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define TXRF5__NOPALGAIN2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define TXRF5__NOPALGAIN2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field enPAcal2G */ +#define TXRF5__ENPACAL2G__SHIFT 5 +#define TXRF5__ENPACAL2G__WIDTH 1 +#define TXRF5__ENPACAL2G__MASK 0x00000020U +#define TXRF5__ENPACAL2G__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define TXRF5__ENPACAL2G__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) +#define TXRF5__ENPACAL2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define TXRF5__ENPACAL2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define TXRF5__ENPACAL2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define TXRF5__ENPACAL2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field offset2G */ +#define TXRF5__OFFSET2G__SHIFT 6 +#define TXRF5__OFFSET2G__WIDTH 7 +#define TXRF5__OFFSET2G__MASK 0x00001fc0U +#define TXRF5__OFFSET2G__READ(src) (((u_int32_t)(src) & 0x00001fc0U) >> 6) +#define TXRF5__OFFSET2G__WRITE(src) (((u_int32_t)(src) << 6) & 0x00001fc0U) +#define TXRF5__OFFSET2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00001fc0U) +#define TXRF5__OFFSET2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00001fc0U))) + +/* macros for field enoffsetcal2G */ +#define TXRF5__ENOFFSETCAL2G__SHIFT 13 +#define TXRF5__ENOFFSETCAL2G__WIDTH 1 +#define TXRF5__ENOFFSETCAL2G__MASK 0x00002000U +#define TXRF5__ENOFFSETCAL2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define TXRF5__ENOFFSETCAL2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define TXRF5__ENOFFSETCAL2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define TXRF5__ENOFFSETCAL2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define TXRF5__ENOFFSETCAL2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define TXRF5__ENOFFSETCAL2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field refHi2G */ +#define TXRF5__REFHI2G__SHIFT 14 +#define TXRF5__REFHI2G__WIDTH 3 +#define TXRF5__REFHI2G__MASK 0x0001c000U +#define TXRF5__REFHI2G__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) +#define TXRF5__REFHI2G__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U) +#define TXRF5__REFHI2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define TXRF5__REFHI2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field refLo2G */ +#define TXRF5__REFLO2G__SHIFT 17 +#define TXRF5__REFLO2G__WIDTH 3 +#define TXRF5__REFLO2G__MASK 0x000e0000U +#define TXRF5__REFLO2G__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) +#define TXRF5__REFLO2G__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) +#define TXRF5__REFLO2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define TXRF5__REFLO2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field palclamp2G */ +#define TXRF5__PALCLAMP2G__SHIFT 20 +#define TXRF5__PALCLAMP2G__WIDTH 2 +#define TXRF5__PALCLAMP2G__MASK 0x00300000U +#define TXRF5__PALCLAMP2G__READ(src) (((u_int32_t)(src) & 0x00300000U) >> 20) +#define TXRF5__PALCLAMP2G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00300000U) +#define TXRF5__PALCLAMP2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00300000U) | (((u_int32_t)(src) <<\ + 20) & 0x00300000U) +#define TXRF5__PALCLAMP2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00300000U))) + +/* macros for field pk2b2G_qam */ +#define TXRF5__PK2B2G_QAM__SHIFT 22 +#define TXRF5__PK2B2G_QAM__WIDTH 2 +#define TXRF5__PK2B2G_QAM__MASK 0x00c00000U +#define TXRF5__PK2B2G_QAM__READ(src) (((u_int32_t)(src) & 0x00c00000U) >> 22) +#define TXRF5__PK2B2G_QAM__WRITE(src) (((u_int32_t)(src) << 22) & 0x00c00000U) +#define TXRF5__PK2B2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x00c00000U) +#define TXRF5__PK2B2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00c00000U))) + +/* macros for field pk2b2G_psk */ +#define TXRF5__PK2B2G_PSK__SHIFT 24 +#define TXRF5__PK2B2G_PSK__WIDTH 2 +#define TXRF5__PK2B2G_PSK__MASK 0x03000000U +#define TXRF5__PK2B2G_PSK__READ(src) (((u_int32_t)(src) & 0x03000000U) >> 24) +#define TXRF5__PK2B2G_PSK__WRITE(src) (((u_int32_t)(src) << 24) & 0x03000000U) +#define TXRF5__PK2B2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define TXRF5__PK2B2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field pk2b2G_cck */ +#define TXRF5__PK2B2G_CCK__SHIFT 26 +#define TXRF5__PK2B2G_CCK__WIDTH 2 +#define TXRF5__PK2B2G_CCK__MASK 0x0c000000U +#define TXRF5__PK2B2G_CCK__READ(src) (((u_int32_t)(src) & 0x0c000000U) >> 26) +#define TXRF5__PK2B2G_CCK__WRITE(src) (((u_int32_t)(src) << 26) & 0x0c000000U) +#define TXRF5__PK2B2G_CCK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define TXRF5__PK2B2G_CCK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) + +/* macros for field pk1b2G_qam */ +#define TXRF5__PK1B2G_QAM__SHIFT 28 +#define TXRF5__PK1B2G_QAM__WIDTH 2 +#define TXRF5__PK1B2G_QAM__MASK 0x30000000U +#define TXRF5__PK1B2G_QAM__READ(src) (((u_int32_t)(src) & 0x30000000U) >> 28) +#define TXRF5__PK1B2G_QAM__WRITE(src) (((u_int32_t)(src) << 28) & 0x30000000U) +#define TXRF5__PK1B2G_QAM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define TXRF5__PK1B2G_QAM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) + +/* macros for field pk1b2G_psk */ +#define TXRF5__PK1B2G_PSK__SHIFT 30 +#define TXRF5__PK1B2G_PSK__WIDTH 2 +#define TXRF5__PK1B2G_PSK__MASK 0xc0000000U +#define TXRF5__PK1B2G_PSK__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) +#define TXRF5__PK1B2G_PSK__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U) +#define TXRF5__PK1B2G_PSK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define TXRF5__PK1B2G_PSK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define TXRF5__TYPE u_int32_t +#define TXRF5__READ 0xffffffffU +#define TXRF5__WRITE 0xffffffffU + +#endif /* __TXRF5_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_TXRF5 */ +#define INST_RADIO65_REG_MAP__CH0_TXRF5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TXRF6 */ +#ifndef __TXRF6_MACRO__ +#define __TXRF6_MACRO__ + +/* macros for field palclkgate2G */ +#define TXRF6__PALCLKGATE2G__SHIFT 0 +#define TXRF6__PALCLKGATE2G__WIDTH 1 +#define TXRF6__PALCLKGATE2G__MASK 0x00000001U +#define TXRF6__PALCLKGATE2G__READ(src) (u_int32_t)(src) & 0x00000001U +#define TXRF6__PALCLKGATE2G__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TXRF6__PALCLKGATE2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TXRF6__PALCLKGATE2G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TXRF6__PALCLKGATE2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TXRF6__PALCLKGATE2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field palfluctcount2G */ +#define TXRF6__PALFLUCTCOUNT2G__SHIFT 1 +#define TXRF6__PALFLUCTCOUNT2G__WIDTH 8 +#define TXRF6__PALFLUCTCOUNT2G__MASK 0x000001feU +#define TXRF6__PALFLUCTCOUNT2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001feU) >> 1) +#define TXRF6__PALFLUCTCOUNT2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x000001feU) +#define TXRF6__PALFLUCTCOUNT2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001feU) | (((u_int32_t)(src) <<\ + 1) & 0x000001feU) +#define TXRF6__PALFLUCTCOUNT2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000001feU))) + +/* macros for field palfluctgain2G */ +#define TXRF6__PALFLUCTGAIN2G__SHIFT 9 +#define TXRF6__PALFLUCTGAIN2G__WIDTH 2 +#define TXRF6__PALFLUCTGAIN2G__MASK 0x00000600U +#define TXRF6__PALFLUCTGAIN2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000600U) >> 9) +#define TXRF6__PALFLUCTGAIN2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000600U) +#define TXRF6__PALFLUCTGAIN2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000600U) | (((u_int32_t)(src) <<\ + 9) & 0x00000600U) +#define TXRF6__PALFLUCTGAIN2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000600U))) + +/* macros for field palnofluct2G */ +#define TXRF6__PALNOFLUCT2G__SHIFT 11 +#define TXRF6__PALNOFLUCT2G__WIDTH 1 +#define TXRF6__PALNOFLUCT2G__MASK 0x00000800U +#define TXRF6__PALNOFLUCT2G__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define TXRF6__PALNOFLUCT2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define TXRF6__PALNOFLUCT2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define TXRF6__PALNOFLUCT2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define TXRF6__PALNOFLUCT2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define TXRF6__PALNOFLUCT2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field gainstep2G */ +#define TXRF6__GAINSTEP2G__SHIFT 12 +#define TXRF6__GAINSTEP2G__WIDTH 3 +#define TXRF6__GAINSTEP2G__MASK 0x00007000U +#define TXRF6__GAINSTEP2G__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12) +#define TXRF6__GAINSTEP2G__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U) +#define TXRF6__GAINSTEP2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define TXRF6__GAINSTEP2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field use_gain_delta2G */ +#define TXRF6__USE_GAIN_DELTA2G__SHIFT 15 +#define TXRF6__USE_GAIN_DELTA2G__WIDTH 1 +#define TXRF6__USE_GAIN_DELTA2G__MASK 0x00008000U +#define TXRF6__USE_GAIN_DELTA2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define TXRF6__USE_GAIN_DELTA2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define TXRF6__USE_GAIN_DELTA2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define TXRF6__USE_GAIN_DELTA2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define TXRF6__USE_GAIN_DELTA2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define TXRF6__USE_GAIN_DELTA2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field capdiv_I2G */ +#define TXRF6__CAPDIV_I2G__SHIFT 16 +#define TXRF6__CAPDIV_I2G__WIDTH 4 +#define TXRF6__CAPDIV_I2G__MASK 0x000f0000U +#define TXRF6__CAPDIV_I2G__READ(src) (((u_int32_t)(src) & 0x000f0000U) >> 16) +#define TXRF6__CAPDIV_I2G__WRITE(src) (((u_int32_t)(src) << 16) & 0x000f0000U) +#define TXRF6__CAPDIV_I2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define TXRF6__CAPDIV_I2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) + +/* macros for field padrvgn_index_I2G */ +#define TXRF6__PADRVGN_INDEX_I2G__SHIFT 20 +#define TXRF6__PADRVGN_INDEX_I2G__WIDTH 4 +#define TXRF6__PADRVGN_INDEX_I2G__MASK 0x00f00000U +#define TXRF6__PADRVGN_INDEX_I2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00f00000U) >> 20) +#define TXRF6__PADRVGN_INDEX_I2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00f00000U) +#define TXRF6__PADRVGN_INDEX_I2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f00000U) | (((u_int32_t)(src) <<\ + 20) & 0x00f00000U) +#define TXRF6__PADRVGN_INDEX_I2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00f00000U))) + +/* macros for field vcmondelay2G */ +#define TXRF6__VCMONDELAY2G__SHIFT 24 +#define TXRF6__VCMONDELAY2G__WIDTH 3 +#define TXRF6__VCMONDELAY2G__MASK 0x07000000U +#define TXRF6__VCMONDELAY2G__READ(src) (((u_int32_t)(src) & 0x07000000U) >> 24) +#define TXRF6__VCMONDELAY2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x07000000U) +#define TXRF6__VCMONDELAY2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define TXRF6__VCMONDELAY2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x07000000U))) + +/* macros for field capdiv2G */ +#define TXRF6__CAPDIV2G__SHIFT 27 +#define TXRF6__CAPDIV2G__WIDTH 4 +#define TXRF6__CAPDIV2G__MASK 0x78000000U +#define TXRF6__CAPDIV2G__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define TXRF6__CAPDIV2G__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define TXRF6__CAPDIV2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define TXRF6__CAPDIV2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) + +/* macros for field capdiv2Govr */ +#define TXRF6__CAPDIV2GOVR__SHIFT 31 +#define TXRF6__CAPDIV2GOVR__WIDTH 1 +#define TXRF6__CAPDIV2GOVR__MASK 0x80000000U +#define TXRF6__CAPDIV2GOVR__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define TXRF6__CAPDIV2GOVR__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) +#define TXRF6__CAPDIV2GOVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TXRF6__CAPDIV2GOVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TXRF6__CAPDIV2GOVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TXRF6__CAPDIV2GOVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TXRF6__TYPE u_int32_t +#define TXRF6__READ 0xffffffffU +#define TXRF6__WRITE 0xffffffffU + +#endif /* __TXRF6_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_TXRF6 */ +#define INST_RADIO65_REG_MAP__CH0_TXRF6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH1 */ +#ifndef __SYNTH1_MACRO__ +#define __SYNTH1_MACRO__ + +/* macros for field SEL_VCMONABUS */ +#define SYNTH1__SEL_VCMONABUS__SHIFT 0 +#define SYNTH1__SEL_VCMONABUS__WIDTH 3 +#define SYNTH1__SEL_VCMONABUS__MASK 0x00000007U +#define SYNTH1__SEL_VCMONABUS__READ(src) (u_int32_t)(src) & 0x00000007U +#define SYNTH1__SEL_VCMONABUS__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define SYNTH1__SEL_VCMONABUS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define SYNTH1__SEL_VCMONABUS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000007U))) + +/* macros for field SEL_VCOABUS */ +#define SYNTH1__SEL_VCOABUS__SHIFT 3 +#define SYNTH1__SEL_VCOABUS__WIDTH 3 +#define SYNTH1__SEL_VCOABUS__MASK 0x00000038U +#define SYNTH1__SEL_VCOABUS__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3) +#define SYNTH1__SEL_VCOABUS__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000038U) +#define SYNTH1__SEL_VCOABUS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define SYNTH1__SEL_VCOABUS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field MONITOR_SYNTHLOCKVCOK */ +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__SHIFT 6 +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__WIDTH 1 +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__MASK 0x00000040U +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define SYNTH1__MONITOR_SYNTHLOCKVCOK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field MONITOR_VC2LOW */ +#define SYNTH1__MONITOR_VC2LOW__SHIFT 7 +#define SYNTH1__MONITOR_VC2LOW__WIDTH 1 +#define SYNTH1__MONITOR_VC2LOW__MASK 0x00000080U +#define SYNTH1__MONITOR_VC2LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define SYNTH1__MONITOR_VC2LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define SYNTH1__MONITOR_VC2LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define SYNTH1__MONITOR_VC2LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define SYNTH1__MONITOR_VC2LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define SYNTH1__MONITOR_VC2LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field MONITOR_VC2HIGH */ +#define SYNTH1__MONITOR_VC2HIGH__SHIFT 8 +#define SYNTH1__MONITOR_VC2HIGH__WIDTH 1 +#define SYNTH1__MONITOR_VC2HIGH__MASK 0x00000100U +#define SYNTH1__MONITOR_VC2HIGH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define SYNTH1__MONITOR_VC2HIGH__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define SYNTH1__MONITOR_VC2HIGH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define SYNTH1__MONITOR_VC2HIGH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define SYNTH1__MONITOR_VC2HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define SYNTH1__MONITOR_VC2HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field MONITOR_FB_DIV2 */ +#define SYNTH1__MONITOR_FB_DIV2__SHIFT 9 +#define SYNTH1__MONITOR_FB_DIV2__WIDTH 1 +#define SYNTH1__MONITOR_FB_DIV2__MASK 0x00000200U +#define SYNTH1__MONITOR_FB_DIV2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define SYNTH1__MONITOR_FB_DIV2__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define SYNTH1__MONITOR_FB_DIV2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define SYNTH1__MONITOR_FB_DIV2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define SYNTH1__MONITOR_FB_DIV2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define SYNTH1__MONITOR_FB_DIV2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field MONITOR_REF */ +#define SYNTH1__MONITOR_REF__SHIFT 10 +#define SYNTH1__MONITOR_REF__WIDTH 1 +#define SYNTH1__MONITOR_REF__MASK 0x00000400U +#define SYNTH1__MONITOR_REF__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define SYNTH1__MONITOR_REF__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define SYNTH1__MONITOR_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define SYNTH1__MONITOR_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define SYNTH1__MONITOR_REF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define SYNTH1__MONITOR_REF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field MONITOR_FB */ +#define SYNTH1__MONITOR_FB__SHIFT 11 +#define SYNTH1__MONITOR_FB__WIDTH 1 +#define SYNTH1__MONITOR_FB__MASK 0x00000800U +#define SYNTH1__MONITOR_FB__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define SYNTH1__MONITOR_FB__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define SYNTH1__MONITOR_FB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define SYNTH1__MONITOR_FB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define SYNTH1__MONITOR_FB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define SYNTH1__MONITOR_FB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field SEVENBITVCOCAP */ +#define SYNTH1__SEVENBITVCOCAP__SHIFT 12 +#define SYNTH1__SEVENBITVCOCAP__WIDTH 1 +#define SYNTH1__SEVENBITVCOCAP__MASK 0x00001000U +#define SYNTH1__SEVENBITVCOCAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define SYNTH1__SEVENBITVCOCAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define SYNTH1__SEVENBITVCOCAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define SYNTH1__SEVENBITVCOCAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define SYNTH1__SEVENBITVCOCAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define SYNTH1__SEVENBITVCOCAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field PWUP_PD */ +#define SYNTH1__PWUP_PD__SHIFT 13 +#define SYNTH1__PWUP_PD__WIDTH 3 +#define SYNTH1__PWUP_PD__MASK 0x0000e000U +#define SYNTH1__PWUP_PD__READ(src) (((u_int32_t)(src) & 0x0000e000U) >> 13) +#define SYNTH1__PWUP_PD__WRITE(src) (((u_int32_t)(src) << 13) & 0x0000e000U) +#define SYNTH1__PWUP_PD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define SYNTH1__PWUP_PD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0000e000U))) + +/* macros for field PWD_VCOBUF */ +#define SYNTH1__PWD_VCOBUF__SHIFT 16 +#define SYNTH1__PWD_VCOBUF__WIDTH 1 +#define SYNTH1__PWD_VCOBUF__MASK 0x00010000U +#define SYNTH1__PWD_VCOBUF__READ(src) (((u_int32_t)(src) & 0x00010000U) >> 16) +#define SYNTH1__PWD_VCOBUF__WRITE(src) (((u_int32_t)(src) << 16) & 0x00010000U) +#define SYNTH1__PWD_VCOBUF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define SYNTH1__PWD_VCOBUF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define SYNTH1__PWD_VCOBUF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define SYNTH1__PWD_VCOBUF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field VCOBUFGAIN */ +#define SYNTH1__VCOBUFGAIN__SHIFT 17 +#define SYNTH1__VCOBUFGAIN__WIDTH 2 +#define SYNTH1__VCOBUFGAIN__MASK 0x00060000U +#define SYNTH1__VCOBUFGAIN__READ(src) (((u_int32_t)(src) & 0x00060000U) >> 17) +#define SYNTH1__VCOBUFGAIN__WRITE(src) (((u_int32_t)(src) << 17) & 0x00060000U) +#define SYNTH1__VCOBUFGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00060000U) | (((u_int32_t)(src) <<\ + 17) & 0x00060000U) +#define SYNTH1__VCOBUFGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00060000U))) + +/* macros for field VCOREGLEVEL */ +#define SYNTH1__VCOREGLEVEL__SHIFT 19 +#define SYNTH1__VCOREGLEVEL__WIDTH 2 +#define SYNTH1__VCOREGLEVEL__MASK 0x00180000U +#define SYNTH1__VCOREGLEVEL__READ(src) (((u_int32_t)(src) & 0x00180000U) >> 19) +#define SYNTH1__VCOREGLEVEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00180000U) +#define SYNTH1__VCOREGLEVEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00180000U) | (((u_int32_t)(src) <<\ + 19) & 0x00180000U) +#define SYNTH1__VCOREGLEVEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00180000U))) + +/* macros for field VCOREGBYPASS */ +#define SYNTH1__VCOREGBYPASS__SHIFT 21 +#define SYNTH1__VCOREGBYPASS__WIDTH 1 +#define SYNTH1__VCOREGBYPASS__MASK 0x00200000U +#define SYNTH1__VCOREGBYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define SYNTH1__VCOREGBYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define SYNTH1__VCOREGBYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define SYNTH1__VCOREGBYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define SYNTH1__VCOREGBYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define SYNTH1__VCOREGBYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field PWUP_LOREF */ +#define SYNTH1__PWUP_LOREF__SHIFT 22 +#define SYNTH1__PWUP_LOREF__WIDTH 1 +#define SYNTH1__PWUP_LOREF__MASK 0x00400000U +#define SYNTH1__PWUP_LOREF__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22) +#define SYNTH1__PWUP_LOREF__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U) +#define SYNTH1__PWUP_LOREF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define SYNTH1__PWUP_LOREF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define SYNTH1__PWUP_LOREF__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define SYNTH1__PWUP_LOREF__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field PWD_LOMIX */ +#define SYNTH1__PWD_LOMIX__SHIFT 23 +#define SYNTH1__PWD_LOMIX__WIDTH 1 +#define SYNTH1__PWD_LOMIX__MASK 0x00800000U +#define SYNTH1__PWD_LOMIX__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) +#define SYNTH1__PWD_LOMIX__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) +#define SYNTH1__PWD_LOMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define SYNTH1__PWD_LOMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define SYNTH1__PWD_LOMIX__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define SYNTH1__PWD_LOMIX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field PWD_LODIV */ +#define SYNTH1__PWD_LODIV__SHIFT 24 +#define SYNTH1__PWD_LODIV__WIDTH 1 +#define SYNTH1__PWD_LODIV__MASK 0x01000000U +#define SYNTH1__PWD_LODIV__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define SYNTH1__PWD_LODIV__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U) +#define SYNTH1__PWD_LODIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define SYNTH1__PWD_LODIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define SYNTH1__PWD_LODIV__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define SYNTH1__PWD_LODIV__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field PWD_LOBUF5G */ +#define SYNTH1__PWD_LOBUF5G__SHIFT 25 +#define SYNTH1__PWD_LOBUF5G__WIDTH 1 +#define SYNTH1__PWD_LOBUF5G__MASK 0x02000000U +#define SYNTH1__PWD_LOBUF5G__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) +#define SYNTH1__PWD_LOBUF5G__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define SYNTH1__PWD_LOBUF5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define SYNTH1__PWD_LOBUF5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define SYNTH1__PWD_LOBUF5G__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define SYNTH1__PWD_LOBUF5G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field PWD_LOBUF2G */ +#define SYNTH1__PWD_LOBUF2G__SHIFT 26 +#define SYNTH1__PWD_LOBUF2G__WIDTH 1 +#define SYNTH1__PWD_LOBUF2G__MASK 0x04000000U +#define SYNTH1__PWD_LOBUF2G__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) +#define SYNTH1__PWD_LOBUF2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define SYNTH1__PWD_LOBUF2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define SYNTH1__PWD_LOBUF2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define SYNTH1__PWD_LOBUF2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define SYNTH1__PWD_LOBUF2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field PWD_PRESC */ +#define SYNTH1__PWD_PRESC__SHIFT 27 +#define SYNTH1__PWD_PRESC__WIDTH 1 +#define SYNTH1__PWD_PRESC__MASK 0x08000000U +#define SYNTH1__PWD_PRESC__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) +#define SYNTH1__PWD_PRESC__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U) +#define SYNTH1__PWD_PRESC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define SYNTH1__PWD_PRESC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define SYNTH1__PWD_PRESC__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define SYNTH1__PWD_PRESC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field PWD_VCO */ +#define SYNTH1__PWD_VCO__SHIFT 28 +#define SYNTH1__PWD_VCO__WIDTH 1 +#define SYNTH1__PWD_VCO__MASK 0x10000000U +#define SYNTH1__PWD_VCO__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define SYNTH1__PWD_VCO__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define SYNTH1__PWD_VCO__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define SYNTH1__PWD_VCO__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define SYNTH1__PWD_VCO__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define SYNTH1__PWD_VCO__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field PWD_VCMON */ +#define SYNTH1__PWD_VCMON__SHIFT 29 +#define SYNTH1__PWD_VCMON__WIDTH 1 +#define SYNTH1__PWD_VCMON__MASK 0x20000000U +#define SYNTH1__PWD_VCMON__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define SYNTH1__PWD_VCMON__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define SYNTH1__PWD_VCMON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define SYNTH1__PWD_VCMON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define SYNTH1__PWD_VCMON__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define SYNTH1__PWD_VCMON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field PWD_CP */ +#define SYNTH1__PWD_CP__SHIFT 30 +#define SYNTH1__PWD_CP__WIDTH 1 +#define SYNTH1__PWD_CP__MASK 0x40000000U +#define SYNTH1__PWD_CP__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define SYNTH1__PWD_CP__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define SYNTH1__PWD_CP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SYNTH1__PWD_CP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SYNTH1__PWD_CP__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SYNTH1__PWD_CP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PWD_BIAS */ +#define SYNTH1__PWD_BIAS__SHIFT 31 +#define SYNTH1__PWD_BIAS__WIDTH 1 +#define SYNTH1__PWD_BIAS__MASK 0x80000000U +#define SYNTH1__PWD_BIAS__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define SYNTH1__PWD_BIAS__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) +#define SYNTH1__PWD_BIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SYNTH1__PWD_BIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SYNTH1__PWD_BIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH1__PWD_BIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH1__TYPE u_int32_t +#define SYNTH1__READ 0xffffffffU +#define SYNTH1__WRITE 0xffffffffU + +#endif /* __SYNTH1_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH1 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH2 */ +#ifndef __SYNTH2_MACRO__ +#define __SYNTH2_MACRO__ + +/* macros for field CAPRANGE3 */ +#define SYNTH2__CAPRANGE3__SHIFT 0 +#define SYNTH2__CAPRANGE3__WIDTH 4 +#define SYNTH2__CAPRANGE3__MASK 0x0000000fU +#define SYNTH2__CAPRANGE3__READ(src) (u_int32_t)(src) & 0x0000000fU +#define SYNTH2__CAPRANGE3__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define SYNTH2__CAPRANGE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define SYNTH2__CAPRANGE3__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) + +/* macros for field CAPRANGE2 */ +#define SYNTH2__CAPRANGE2__SHIFT 4 +#define SYNTH2__CAPRANGE2__WIDTH 4 +#define SYNTH2__CAPRANGE2__MASK 0x000000f0U +#define SYNTH2__CAPRANGE2__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) +#define SYNTH2__CAPRANGE2__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) +#define SYNTH2__CAPRANGE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SYNTH2__CAPRANGE2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field CAPRANGE1 */ +#define SYNTH2__CAPRANGE1__SHIFT 8 +#define SYNTH2__CAPRANGE1__WIDTH 4 +#define SYNTH2__CAPRANGE1__MASK 0x00000f00U +#define SYNTH2__CAPRANGE1__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) +#define SYNTH2__CAPRANGE1__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) +#define SYNTH2__CAPRANGE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SYNTH2__CAPRANGE1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field LOOPLEAKCUR_INTN */ +#define SYNTH2__LOOPLEAKCUR_INTN__SHIFT 12 +#define SYNTH2__LOOPLEAKCUR_INTN__WIDTH 4 +#define SYNTH2__LOOPLEAKCUR_INTN__MASK 0x0000f000U +#define SYNTH2__LOOPLEAKCUR_INTN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f000U) >> 12) +#define SYNTH2__LOOPLEAKCUR_INTN__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0000f000U) +#define SYNTH2__LOOPLEAKCUR_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0000f000U) +#define SYNTH2__LOOPLEAKCUR_INTN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0000f000U))) + +/* macros for field CPLOWLK_INTN */ +#define SYNTH2__CPLOWLK_INTN__SHIFT 16 +#define SYNTH2__CPLOWLK_INTN__WIDTH 1 +#define SYNTH2__CPLOWLK_INTN__MASK 0x00010000U +#define SYNTH2__CPLOWLK_INTN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define SYNTH2__CPLOWLK_INTN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define SYNTH2__CPLOWLK_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define SYNTH2__CPLOWLK_INTN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define SYNTH2__CPLOWLK_INTN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define SYNTH2__CPLOWLK_INTN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field CPSTEERING_EN_INTN */ +#define SYNTH2__CPSTEERING_EN_INTN__SHIFT 17 +#define SYNTH2__CPSTEERING_EN_INTN__WIDTH 1 +#define SYNTH2__CPSTEERING_EN_INTN__MASK 0x00020000U +#define SYNTH2__CPSTEERING_EN_INTN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define SYNTH2__CPSTEERING_EN_INTN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define SYNTH2__CPSTEERING_EN_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define SYNTH2__CPSTEERING_EN_INTN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define SYNTH2__CPSTEERING_EN_INTN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define SYNTH2__CPSTEERING_EN_INTN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field CPBIAS_INTN */ +#define SYNTH2__CPBIAS_INTN__SHIFT 18 +#define SYNTH2__CPBIAS_INTN__WIDTH 2 +#define SYNTH2__CPBIAS_INTN__MASK 0x000c0000U +#define SYNTH2__CPBIAS_INTN__READ(src) (((u_int32_t)(src) & 0x000c0000U) >> 18) +#define SYNTH2__CPBIAS_INTN__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x000c0000U) +#define SYNTH2__CPBIAS_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x000c0000U) +#define SYNTH2__CPBIAS_INTN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x000c0000U))) + +/* macros for field VC_LOW_REF */ +#define SYNTH2__VC_LOW_REF__SHIFT 20 +#define SYNTH2__VC_LOW_REF__WIDTH 3 +#define SYNTH2__VC_LOW_REF__MASK 0x00700000U +#define SYNTH2__VC_LOW_REF__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) +#define SYNTH2__VC_LOW_REF__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) +#define SYNTH2__VC_LOW_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define SYNTH2__VC_LOW_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field VC_MID_REF */ +#define SYNTH2__VC_MID_REF__SHIFT 23 +#define SYNTH2__VC_MID_REF__WIDTH 3 +#define SYNTH2__VC_MID_REF__MASK 0x03800000U +#define SYNTH2__VC_MID_REF__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) +#define SYNTH2__VC_MID_REF__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) +#define SYNTH2__VC_MID_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define SYNTH2__VC_MID_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field VC_HI_REF */ +#define SYNTH2__VC_HI_REF__SHIFT 26 +#define SYNTH2__VC_HI_REF__WIDTH 3 +#define SYNTH2__VC_HI_REF__MASK 0x1c000000U +#define SYNTH2__VC_HI_REF__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define SYNTH2__VC_HI_REF__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define SYNTH2__VC_HI_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define SYNTH2__VC_HI_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field VC_CAL_REF */ +#define SYNTH2__VC_CAL_REF__SHIFT 29 +#define SYNTH2__VC_CAL_REF__WIDTH 3 +#define SYNTH2__VC_CAL_REF__MASK 0xe0000000U +#define SYNTH2__VC_CAL_REF__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define SYNTH2__VC_CAL_REF__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define SYNTH2__VC_CAL_REF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define SYNTH2__VC_CAL_REF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define SYNTH2__TYPE u_int32_t +#define SYNTH2__READ 0xffffffffU +#define SYNTH2__WRITE 0xffffffffU + +#endif /* __SYNTH2_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH2 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH3 */ +#ifndef __SYNTH3_MACRO__ +#define __SYNTH3_MACRO__ + +/* macros for field WAIT_VC_CHECK */ +#define SYNTH3__WAIT_VC_CHECK__SHIFT 0 +#define SYNTH3__WAIT_VC_CHECK__WIDTH 6 +#define SYNTH3__WAIT_VC_CHECK__MASK 0x0000003fU +#define SYNTH3__WAIT_VC_CHECK__READ(src) (u_int32_t)(src) & 0x0000003fU +#define SYNTH3__WAIT_VC_CHECK__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define SYNTH3__WAIT_VC_CHECK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define SYNTH3__WAIT_VC_CHECK__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000003fU))) + +/* macros for field WAIT_CAL_LIN */ +#define SYNTH3__WAIT_CAL_LIN__SHIFT 6 +#define SYNTH3__WAIT_CAL_LIN__WIDTH 6 +#define SYNTH3__WAIT_CAL_LIN__MASK 0x00000fc0U +#define SYNTH3__WAIT_CAL_LIN__READ(src) (((u_int32_t)(src) & 0x00000fc0U) >> 6) +#define SYNTH3__WAIT_CAL_LIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000fc0U) +#define SYNTH3__WAIT_CAL_LIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000fc0U) | (((u_int32_t)(src) <<\ + 6) & 0x00000fc0U) +#define SYNTH3__WAIT_CAL_LIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000fc0U))) + +/* macros for field WAIT_CAL_BIN */ +#define SYNTH3__WAIT_CAL_BIN__SHIFT 12 +#define SYNTH3__WAIT_CAL_BIN__WIDTH 6 +#define SYNTH3__WAIT_CAL_BIN__MASK 0x0003f000U +#define SYNTH3__WAIT_CAL_BIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0003f000U) >> 12) +#define SYNTH3__WAIT_CAL_BIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0003f000U) +#define SYNTH3__WAIT_CAL_BIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0003f000U) +#define SYNTH3__WAIT_CAL_BIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0003f000U))) + +/* macros for field WAIT_PWRUP */ +#define SYNTH3__WAIT_PWRUP__SHIFT 18 +#define SYNTH3__WAIT_PWRUP__WIDTH 6 +#define SYNTH3__WAIT_PWRUP__MASK 0x00fc0000U +#define SYNTH3__WAIT_PWRUP__READ(src) (((u_int32_t)(src) & 0x00fc0000U) >> 18) +#define SYNTH3__WAIT_PWRUP__WRITE(src) (((u_int32_t)(src) << 18) & 0x00fc0000U) +#define SYNTH3__WAIT_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x00fc0000U) +#define SYNTH3__WAIT_PWRUP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00fc0000U))) + +/* macros for field WAIT_SHORTR_PWRUP */ +#define SYNTH3__WAIT_SHORTR_PWRUP__SHIFT 24 +#define SYNTH3__WAIT_SHORTR_PWRUP__WIDTH 6 +#define SYNTH3__WAIT_SHORTR_PWRUP__MASK 0x3f000000U +#define SYNTH3__WAIT_SHORTR_PWRUP__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define SYNTH3__WAIT_SHORTR_PWRUP__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define SYNTH3__WAIT_SHORTR_PWRUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define SYNTH3__WAIT_SHORTR_PWRUP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) + +/* macros for field SEL_CLK_DIV2 */ +#define SYNTH3__SEL_CLK_DIV2__SHIFT 30 +#define SYNTH3__SEL_CLK_DIV2__WIDTH 1 +#define SYNTH3__SEL_CLK_DIV2__MASK 0x40000000U +#define SYNTH3__SEL_CLK_DIV2__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define SYNTH3__SEL_CLK_DIV2__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define SYNTH3__SEL_CLK_DIV2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SYNTH3__SEL_CLK_DIV2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SYNTH3__SEL_CLK_DIV2__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SYNTH3__SEL_CLK_DIV2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field DIS_CLK_XTAL */ +#define SYNTH3__DIS_CLK_XTAL__SHIFT 31 +#define SYNTH3__DIS_CLK_XTAL__WIDTH 1 +#define SYNTH3__DIS_CLK_XTAL__MASK 0x80000000U +#define SYNTH3__DIS_CLK_XTAL__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define SYNTH3__DIS_CLK_XTAL__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define SYNTH3__DIS_CLK_XTAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SYNTH3__DIS_CLK_XTAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SYNTH3__DIS_CLK_XTAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH3__DIS_CLK_XTAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH3__TYPE u_int32_t +#define SYNTH3__READ 0xffffffffU +#define SYNTH3__WRITE 0xffffffffU + +#endif /* __SYNTH3_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH3 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH4 */ +#ifndef __SYNTH4_MACRO__ +#define __SYNTH4_MACRO__ + +/* macros for field PS_SINGLE_PULSE */ +#define SYNTH4__PS_SINGLE_PULSE__SHIFT 0 +#define SYNTH4__PS_SINGLE_PULSE__WIDTH 1 +#define SYNTH4__PS_SINGLE_PULSE__MASK 0x00000001U +#define SYNTH4__PS_SINGLE_PULSE__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYNTH4__PS_SINGLE_PULSE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define SYNTH4__PS_SINGLE_PULSE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYNTH4__PS_SINGLE_PULSE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SYNTH4__PS_SINGLE_PULSE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYNTH4__PS_SINGLE_PULSE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LONGSHIFTSEL */ +#define SYNTH4__LONGSHIFTSEL__SHIFT 1 +#define SYNTH4__LONGSHIFTSEL__WIDTH 1 +#define SYNTH4__LONGSHIFTSEL__MASK 0x00000002U +#define SYNTH4__LONGSHIFTSEL__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define SYNTH4__LONGSHIFTSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define SYNTH4__LONGSHIFTSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define SYNTH4__LONGSHIFTSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define SYNTH4__LONGSHIFTSEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define SYNTH4__LONGSHIFTSEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field LOBUF5GTUNE_OVR */ +#define SYNTH4__LOBUF5GTUNE_OVR__SHIFT 2 +#define SYNTH4__LOBUF5GTUNE_OVR__WIDTH 2 +#define SYNTH4__LOBUF5GTUNE_OVR__MASK 0x0000000cU +#define SYNTH4__LOBUF5GTUNE_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define SYNTH4__LOBUF5GTUNE_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define SYNTH4__LOBUF5GTUNE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define SYNTH4__LOBUF5GTUNE_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field FORCE_LOBUF5GTUNE */ +#define SYNTH4__FORCE_LOBUF5GTUNE__SHIFT 4 +#define SYNTH4__FORCE_LOBUF5GTUNE__WIDTH 1 +#define SYNTH4__FORCE_LOBUF5GTUNE__MASK 0x00000010U +#define SYNTH4__FORCE_LOBUF5GTUNE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define SYNTH4__FORCE_LOBUF5GTUNE__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define SYNTH4__FORCE_LOBUF5GTUNE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define SYNTH4__FORCE_LOBUF5GTUNE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define SYNTH4__FORCE_LOBUF5GTUNE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define SYNTH4__FORCE_LOBUF5GTUNE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field PSCOUNT_FBSEL */ +#define SYNTH4__PSCOUNT_FBSEL__SHIFT 5 +#define SYNTH4__PSCOUNT_FBSEL__WIDTH 1 +#define SYNTH4__PSCOUNT_FBSEL__MASK 0x00000020U +#define SYNTH4__PSCOUNT_FBSEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define SYNTH4__PSCOUNT_FBSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define SYNTH4__PSCOUNT_FBSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define SYNTH4__PSCOUNT_FBSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define SYNTH4__PSCOUNT_FBSEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define SYNTH4__PSCOUNT_FBSEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field SDM_DITHER1 */ +#define SYNTH4__SDM_DITHER1__SHIFT 6 +#define SYNTH4__SDM_DITHER1__WIDTH 2 +#define SYNTH4__SDM_DITHER1__MASK 0x000000c0U +#define SYNTH4__SDM_DITHER1__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6) +#define SYNTH4__SDM_DITHER1__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U) +#define SYNTH4__SDM_DITHER1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SYNTH4__SDM_DITHER1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field SDM_MODE */ +#define SYNTH4__SDM_MODE__SHIFT 8 +#define SYNTH4__SDM_MODE__WIDTH 1 +#define SYNTH4__SDM_MODE__MASK 0x00000100U +#define SYNTH4__SDM_MODE__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define SYNTH4__SDM_MODE__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) +#define SYNTH4__SDM_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define SYNTH4__SDM_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define SYNTH4__SDM_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define SYNTH4__SDM_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field SDM_DISABLE */ +#define SYNTH4__SDM_DISABLE__SHIFT 9 +#define SYNTH4__SDM_DISABLE__WIDTH 1 +#define SYNTH4__SDM_DISABLE__MASK 0x00000200U +#define SYNTH4__SDM_DISABLE__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define SYNTH4__SDM_DISABLE__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) +#define SYNTH4__SDM_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define SYNTH4__SDM_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define SYNTH4__SDM_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define SYNTH4__SDM_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field RESET_PRESC */ +#define SYNTH4__RESET_PRESC__SHIFT 10 +#define SYNTH4__RESET_PRESC__WIDTH 1 +#define SYNTH4__RESET_PRESC__MASK 0x00000400U +#define SYNTH4__RESET_PRESC__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define SYNTH4__RESET_PRESC__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define SYNTH4__RESET_PRESC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define SYNTH4__RESET_PRESC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define SYNTH4__RESET_PRESC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define SYNTH4__RESET_PRESC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field PRESCSEL */ +#define SYNTH4__PRESCSEL__SHIFT 11 +#define SYNTH4__PRESCSEL__WIDTH 2 +#define SYNTH4__PRESCSEL__MASK 0x00001800U +#define SYNTH4__PRESCSEL__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11) +#define SYNTH4__PRESCSEL__WRITE(src) (((u_int32_t)(src) << 11) & 0x00001800U) +#define SYNTH4__PRESCSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001800U) | (((u_int32_t)(src) <<\ + 11) & 0x00001800U) +#define SYNTH4__PRESCSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00001800U))) + +/* macros for field PFD_DISABLE */ +#define SYNTH4__PFD_DISABLE__SHIFT 13 +#define SYNTH4__PFD_DISABLE__WIDTH 1 +#define SYNTH4__PFD_DISABLE__MASK 0x00002000U +#define SYNTH4__PFD_DISABLE__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) +#define SYNTH4__PFD_DISABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define SYNTH4__PFD_DISABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define SYNTH4__PFD_DISABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define SYNTH4__PFD_DISABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define SYNTH4__PFD_DISABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field PFDDELAY_FRACN */ +#define SYNTH4__PFDDELAY_FRACN__SHIFT 14 +#define SYNTH4__PFDDELAY_FRACN__WIDTH 1 +#define SYNTH4__PFDDELAY_FRACN__MASK 0x00004000U +#define SYNTH4__PFDDELAY_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define SYNTH4__PFDDELAY_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define SYNTH4__PFDDELAY_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define SYNTH4__PFDDELAY_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define SYNTH4__PFDDELAY_FRACN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define SYNTH4__PFDDELAY_FRACN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field FORCE_LO_ON */ +#define SYNTH4__FORCE_LO_ON__SHIFT 15 +#define SYNTH4__FORCE_LO_ON__WIDTH 1 +#define SYNTH4__FORCE_LO_ON__MASK 0x00008000U +#define SYNTH4__FORCE_LO_ON__READ(src) (((u_int32_t)(src) & 0x00008000U) >> 15) +#define SYNTH4__FORCE_LO_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define SYNTH4__FORCE_LO_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define SYNTH4__FORCE_LO_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define SYNTH4__FORCE_LO_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define SYNTH4__FORCE_LO_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field CLKXTAL_EDGE_SEL */ +#define SYNTH4__CLKXTAL_EDGE_SEL__SHIFT 16 +#define SYNTH4__CLKXTAL_EDGE_SEL__WIDTH 1 +#define SYNTH4__CLKXTAL_EDGE_SEL__MASK 0x00010000U +#define SYNTH4__CLKXTAL_EDGE_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define SYNTH4__CLKXTAL_EDGE_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define SYNTH4__CLKXTAL_EDGE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define SYNTH4__CLKXTAL_EDGE_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define SYNTH4__CLKXTAL_EDGE_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define SYNTH4__CLKXTAL_EDGE_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field VCOCAPPULLUP */ +#define SYNTH4__VCOCAPPULLUP__SHIFT 17 +#define SYNTH4__VCOCAPPULLUP__WIDTH 1 +#define SYNTH4__VCOCAPPULLUP__MASK 0x00020000U +#define SYNTH4__VCOCAPPULLUP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define SYNTH4__VCOCAPPULLUP__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define SYNTH4__VCOCAPPULLUP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define SYNTH4__VCOCAPPULLUP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define SYNTH4__VCOCAPPULLUP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define SYNTH4__VCOCAPPULLUP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field VCOCAP_OVR */ +#define SYNTH4__VCOCAP_OVR__SHIFT 18 +#define SYNTH4__VCOCAP_OVR__WIDTH 8 +#define SYNTH4__VCOCAP_OVR__MASK 0x03fc0000U +#define SYNTH4__VCOCAP_OVR__READ(src) (((u_int32_t)(src) & 0x03fc0000U) >> 18) +#define SYNTH4__VCOCAP_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x03fc0000U) +#define SYNTH4__VCOCAP_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x03fc0000U) +#define SYNTH4__VCOCAP_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x03fc0000U))) + +/* macros for field FORCE_VCOCAP */ +#define SYNTH4__FORCE_VCOCAP__SHIFT 26 +#define SYNTH4__FORCE_VCOCAP__WIDTH 1 +#define SYNTH4__FORCE_VCOCAP__MASK 0x04000000U +#define SYNTH4__FORCE_VCOCAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define SYNTH4__FORCE_VCOCAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define SYNTH4__FORCE_VCOCAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define SYNTH4__FORCE_VCOCAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define SYNTH4__FORCE_VCOCAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define SYNTH4__FORCE_VCOCAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field FORCE_PINVC */ +#define SYNTH4__FORCE_PINVC__SHIFT 27 +#define SYNTH4__FORCE_PINVC__WIDTH 1 +#define SYNTH4__FORCE_PINVC__MASK 0x08000000U +#define SYNTH4__FORCE_PINVC__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) +#define SYNTH4__FORCE_PINVC__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define SYNTH4__FORCE_PINVC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define SYNTH4__FORCE_PINVC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define SYNTH4__FORCE_PINVC__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define SYNTH4__FORCE_PINVC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field SHORTR_UNTIL_LOCKED */ +#define SYNTH4__SHORTR_UNTIL_LOCKED__SHIFT 28 +#define SYNTH4__SHORTR_UNTIL_LOCKED__WIDTH 1 +#define SYNTH4__SHORTR_UNTIL_LOCKED__MASK 0x10000000U +#define SYNTH4__SHORTR_UNTIL_LOCKED__READ(src) \ + (((u_int32_t)(src)\ + & 0x10000000U) >> 28) +#define SYNTH4__SHORTR_UNTIL_LOCKED__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define SYNTH4__SHORTR_UNTIL_LOCKED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define SYNTH4__SHORTR_UNTIL_LOCKED__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define SYNTH4__SHORTR_UNTIL_LOCKED__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define SYNTH4__SHORTR_UNTIL_LOCKED__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field ALWAYS_SHORTR */ +#define SYNTH4__ALWAYS_SHORTR__SHIFT 29 +#define SYNTH4__ALWAYS_SHORTR__WIDTH 1 +#define SYNTH4__ALWAYS_SHORTR__MASK 0x20000000U +#define SYNTH4__ALWAYS_SHORTR__READ(src) \ + (((u_int32_t)(src)\ + & 0x20000000U) >> 29) +#define SYNTH4__ALWAYS_SHORTR__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define SYNTH4__ALWAYS_SHORTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define SYNTH4__ALWAYS_SHORTR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define SYNTH4__ALWAYS_SHORTR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define SYNTH4__ALWAYS_SHORTR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field DIS_LOSTVC */ +#define SYNTH4__DIS_LOSTVC__SHIFT 30 +#define SYNTH4__DIS_LOSTVC__WIDTH 1 +#define SYNTH4__DIS_LOSTVC__MASK 0x40000000U +#define SYNTH4__DIS_LOSTVC__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define SYNTH4__DIS_LOSTVC__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define SYNTH4__DIS_LOSTVC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SYNTH4__DIS_LOSTVC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SYNTH4__DIS_LOSTVC__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SYNTH4__DIS_LOSTVC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field DIS_LIN_CAPSEARCH */ +#define SYNTH4__DIS_LIN_CAPSEARCH__SHIFT 31 +#define SYNTH4__DIS_LIN_CAPSEARCH__WIDTH 1 +#define SYNTH4__DIS_LIN_CAPSEARCH__MASK 0x80000000U +#define SYNTH4__DIS_LIN_CAPSEARCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define SYNTH4__DIS_LIN_CAPSEARCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define SYNTH4__DIS_LIN_CAPSEARCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SYNTH4__DIS_LIN_CAPSEARCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SYNTH4__DIS_LIN_CAPSEARCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH4__DIS_LIN_CAPSEARCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH4__TYPE u_int32_t +#define SYNTH4__READ 0xffffffffU +#define SYNTH4__WRITE 0xffffffffU + +#endif /* __SYNTH4_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH4 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH5 */ +#ifndef __SYNTH5_MACRO__ +#define __SYNTH5_MACRO__ + +/* macros for field VCOBIAS */ +#define SYNTH5__VCOBIAS__SHIFT 0 +#define SYNTH5__VCOBIAS__WIDTH 2 +#define SYNTH5__VCOBIAS__MASK 0x00000003U +#define SYNTH5__VCOBIAS__READ(src) (u_int32_t)(src) & 0x00000003U +#define SYNTH5__VCOBIAS__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define SYNTH5__VCOBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SYNTH5__VCOBIAS__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field PWDB_ICLOBUF5G50 */ +#define SYNTH5__PWDB_ICLOBUF5G50__SHIFT 2 +#define SYNTH5__PWDB_ICLOBUF5G50__WIDTH 3 +#define SYNTH5__PWDB_ICLOBUF5G50__MASK 0x0000001cU +#define SYNTH5__PWDB_ICLOBUF5G50__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define SYNTH5__PWDB_ICLOBUF5G50__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define SYNTH5__PWDB_ICLOBUF5G50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define SYNTH5__PWDB_ICLOBUF5G50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field PWDB_ICLOBUF2G50 */ +#define SYNTH5__PWDB_ICLOBUF2G50__SHIFT 5 +#define SYNTH5__PWDB_ICLOBUF2G50__WIDTH 3 +#define SYNTH5__PWDB_ICLOBUF2G50__MASK 0x000000e0U +#define SYNTH5__PWDB_ICLOBUF2G50__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define SYNTH5__PWDB_ICLOBUF2G50__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define SYNTH5__PWDB_ICLOBUF2G50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define SYNTH5__PWDB_ICLOBUF2G50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field PWDB_ICVCO25 */ +#define SYNTH5__PWDB_ICVCO25__SHIFT 8 +#define SYNTH5__PWDB_ICVCO25__WIDTH 3 +#define SYNTH5__PWDB_ICVCO25__MASK 0x00000700U +#define SYNTH5__PWDB_ICVCO25__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) +#define SYNTH5__PWDB_ICVCO25__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define SYNTH5__PWDB_ICVCO25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define SYNTH5__PWDB_ICVCO25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field PWDB_ICVCOREG25 */ +#define SYNTH5__PWDB_ICVCOREG25__SHIFT 11 +#define SYNTH5__PWDB_ICVCOREG25__WIDTH 3 +#define SYNTH5__PWDB_ICVCOREG25__MASK 0x00003800U +#define SYNTH5__PWDB_ICVCOREG25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define SYNTH5__PWDB_ICVCOREG25__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define SYNTH5__PWDB_ICVCOREG25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define SYNTH5__PWDB_ICVCOREG25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field PWDB_IRVCOREG50 */ +#define SYNTH5__PWDB_IRVCOREG50__SHIFT 14 +#define SYNTH5__PWDB_IRVCOREG50__WIDTH 1 +#define SYNTH5__PWDB_IRVCOREG50__MASK 0x00004000U +#define SYNTH5__PWDB_IRVCOREG50__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define SYNTH5__PWDB_IRVCOREG50__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define SYNTH5__PWDB_IRVCOREG50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define SYNTH5__PWDB_IRVCOREG50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define SYNTH5__PWDB_IRVCOREG50__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define SYNTH5__PWDB_IRVCOREG50__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field PWDB_ICLOMIX */ +#define SYNTH5__PWDB_ICLOMIX__SHIFT 15 +#define SYNTH5__PWDB_ICLOMIX__WIDTH 3 +#define SYNTH5__PWDB_ICLOMIX__MASK 0x00038000U +#define SYNTH5__PWDB_ICLOMIX__READ(src) \ + (((u_int32_t)(src)\ + & 0x00038000U) >> 15) +#define SYNTH5__PWDB_ICLOMIX__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00038000U) +#define SYNTH5__PWDB_ICLOMIX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define SYNTH5__PWDB_ICLOMIX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field PWDB_ICLODIV50 */ +#define SYNTH5__PWDB_ICLODIV50__SHIFT 18 +#define SYNTH5__PWDB_ICLODIV50__WIDTH 3 +#define SYNTH5__PWDB_ICLODIV50__MASK 0x001c0000U +#define SYNTH5__PWDB_ICLODIV50__READ(src) \ + (((u_int32_t)(src)\ + & 0x001c0000U) >> 18) +#define SYNTH5__PWDB_ICLODIV50__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x001c0000U) +#define SYNTH5__PWDB_ICLODIV50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define SYNTH5__PWDB_ICLODIV50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field PWDB_ICPRESC50 */ +#define SYNTH5__PWDB_ICPRESC50__SHIFT 21 +#define SYNTH5__PWDB_ICPRESC50__WIDTH 3 +#define SYNTH5__PWDB_ICPRESC50__MASK 0x00e00000U +#define SYNTH5__PWDB_ICPRESC50__READ(src) \ + (((u_int32_t)(src)\ + & 0x00e00000U) >> 21) +#define SYNTH5__PWDB_ICPRESC50__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00e00000U) +#define SYNTH5__PWDB_ICPRESC50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define SYNTH5__PWDB_ICPRESC50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field PWDB_IRVCMON25 */ +#define SYNTH5__PWDB_IRVCMON25__SHIFT 24 +#define SYNTH5__PWDB_IRVCMON25__WIDTH 3 +#define SYNTH5__PWDB_IRVCMON25__MASK 0x07000000U +#define SYNTH5__PWDB_IRVCMON25__READ(src) \ + (((u_int32_t)(src)\ + & 0x07000000U) >> 24) +#define SYNTH5__PWDB_IRVCMON25__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x07000000U) +#define SYNTH5__PWDB_IRVCMON25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07000000U) | (((u_int32_t)(src) <<\ + 24) & 0x07000000U) +#define SYNTH5__PWDB_IRVCMON25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x07000000U))) + +/* macros for field PWDB_IRPFDCP */ +#define SYNTH5__PWDB_IRPFDCP__SHIFT 27 +#define SYNTH5__PWDB_IRPFDCP__WIDTH 3 +#define SYNTH5__PWDB_IRPFDCP__MASK 0x38000000U +#define SYNTH5__PWDB_IRPFDCP__READ(src) \ + (((u_int32_t)(src)\ + & 0x38000000U) >> 27) +#define SYNTH5__PWDB_IRPFDCP__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x38000000U) +#define SYNTH5__PWDB_IRPFDCP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x38000000U) | (((u_int32_t)(src) <<\ + 27) & 0x38000000U) +#define SYNTH5__PWDB_IRPFDCP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x38000000U))) + +/* macros for field SDM_DITHER2 */ +#define SYNTH5__SDM_DITHER2__SHIFT 30 +#define SYNTH5__SDM_DITHER2__WIDTH 2 +#define SYNTH5__SDM_DITHER2__MASK 0xc0000000U +#define SYNTH5__SDM_DITHER2__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) +#define SYNTH5__SDM_DITHER2__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define SYNTH5__SDM_DITHER2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define SYNTH5__SDM_DITHER2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define SYNTH5__TYPE u_int32_t +#define SYNTH5__READ 0xffffffffU +#define SYNTH5__WRITE 0xffffffffU + +#endif /* __SYNTH5_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH5 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH5__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH6 */ +#ifndef __SYNTH6_MACRO__ +#define __SYNTH6_MACRO__ + +/* macros for field LOBUF5GTUNE */ +#define SYNTH6__LOBUF5GTUNE__SHIFT 0 +#define SYNTH6__LOBUF5GTUNE__WIDTH 2 +#define SYNTH6__LOBUF5GTUNE__MASK 0x00000003U +#define SYNTH6__LOBUF5GTUNE__READ(src) (u_int32_t)(src) & 0x00000003U + +/* macros for field LOOP_IP */ +#define SYNTH6__LOOP_IP__SHIFT 2 +#define SYNTH6__LOOP_IP__WIDTH 7 +#define SYNTH6__LOOP_IP__MASK 0x000001fcU +#define SYNTH6__LOOP_IP__READ(src) (((u_int32_t)(src) & 0x000001fcU) >> 2) + +/* macros for field VC2LOW */ +#define SYNTH6__VC2LOW__SHIFT 9 +#define SYNTH6__VC2LOW__WIDTH 1 +#define SYNTH6__VC2LOW__MASK 0x00000200U +#define SYNTH6__VC2LOW__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define SYNTH6__VC2LOW__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define SYNTH6__VC2LOW__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field VC2HIGH */ +#define SYNTH6__VC2HIGH__SHIFT 10 +#define SYNTH6__VC2HIGH__WIDTH 1 +#define SYNTH6__VC2HIGH__MASK 0x00000400U +#define SYNTH6__VC2HIGH__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define SYNTH6__VC2HIGH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define SYNTH6__VC2HIGH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field RESET_SDM_B */ +#define SYNTH6__RESET_SDM_B__SHIFT 11 +#define SYNTH6__RESET_SDM_B__WIDTH 1 +#define SYNTH6__RESET_SDM_B__MASK 0x00000800U +#define SYNTH6__RESET_SDM_B__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define SYNTH6__RESET_SDM_B__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define SYNTH6__RESET_SDM_B__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field RESET_PSCOUNTERS */ +#define SYNTH6__RESET_PSCOUNTERS__SHIFT 12 +#define SYNTH6__RESET_PSCOUNTERS__WIDTH 1 +#define SYNTH6__RESET_PSCOUNTERS__MASK 0x00001000U +#define SYNTH6__RESET_PSCOUNTERS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define SYNTH6__RESET_PSCOUNTERS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define SYNTH6__RESET_PSCOUNTERS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field RESET_PFD */ +#define SYNTH6__RESET_PFD__SHIFT 13 +#define SYNTH6__RESET_PFD__WIDTH 1 +#define SYNTH6__RESET_PFD__MASK 0x00002000U +#define SYNTH6__RESET_PFD__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) +#define SYNTH6__RESET_PFD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define SYNTH6__RESET_PFD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field RESET_RFD */ +#define SYNTH6__RESET_RFD__SHIFT 14 +#define SYNTH6__RESET_RFD__WIDTH 1 +#define SYNTH6__RESET_RFD__MASK 0x00004000U +#define SYNTH6__RESET_RFD__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) +#define SYNTH6__RESET_RFD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define SYNTH6__RESET_RFD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field SHORT_R */ +#define SYNTH6__SHORT_R__SHIFT 15 +#define SYNTH6__SHORT_R__WIDTH 1 +#define SYNTH6__SHORT_R__MASK 0x00008000U +#define SYNTH6__SHORT_R__READ(src) (((u_int32_t)(src) & 0x00008000U) >> 15) +#define SYNTH6__SHORT_R__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define SYNTH6__SHORT_R__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field VCO_CAP_ST */ +#define SYNTH6__VCO_CAP_ST__SHIFT 16 +#define SYNTH6__VCO_CAP_ST__WIDTH 8 +#define SYNTH6__VCO_CAP_ST__MASK 0x00ff0000U +#define SYNTH6__VCO_CAP_ST__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) + +/* macros for field PIN_VC */ +#define SYNTH6__PIN_VC__SHIFT 24 +#define SYNTH6__PIN_VC__WIDTH 1 +#define SYNTH6__PIN_VC__MASK 0x01000000U +#define SYNTH6__PIN_VC__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define SYNTH6__PIN_VC__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define SYNTH6__PIN_VC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field SYNTH_LOCK_VC_OK */ +#define SYNTH6__SYNTH_LOCK_VC_OK__SHIFT 25 +#define SYNTH6__SYNTH_LOCK_VC_OK__WIDTH 1 +#define SYNTH6__SYNTH_LOCK_VC_OK__MASK 0x02000000U +#define SYNTH6__SYNTH_LOCK_VC_OK__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define SYNTH6__SYNTH_LOCK_VC_OK__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define SYNTH6__SYNTH_LOCK_VC_OK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field CAP_SEARCH */ +#define SYNTH6__CAP_SEARCH__SHIFT 26 +#define SYNTH6__CAP_SEARCH__WIDTH 1 +#define SYNTH6__CAP_SEARCH__MASK 0x04000000U +#define SYNTH6__CAP_SEARCH__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) +#define SYNTH6__CAP_SEARCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define SYNTH6__CAP_SEARCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field SYNTH_SM_STATE */ +#define SYNTH6__SYNTH_SM_STATE__SHIFT 27 +#define SYNTH6__SYNTH_SM_STATE__WIDTH 4 +#define SYNTH6__SYNTH_SM_STATE__MASK 0x78000000U +#define SYNTH6__SYNTH_SM_STATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x78000000U) >> 27) + +/* macros for field SYNTH_ON */ +#define SYNTH6__SYNTH_ON__SHIFT 31 +#define SYNTH6__SYNTH_ON__WIDTH 1 +#define SYNTH6__SYNTH_ON__MASK 0x80000000U +#define SYNTH6__SYNTH_ON__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define SYNTH6__SYNTH_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH6__SYNTH_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH6__TYPE u_int32_t +#define SYNTH6__READ 0xffffffffU + +#endif /* __SYNTH6_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH6 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH6__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH7 */ +#ifndef __SYNTH7_MACRO__ +#define __SYNTH7_MACRO__ + +/* macros for field OVRCHANDECODER */ +#define SYNTH7__OVRCHANDECODER__SHIFT 0 +#define SYNTH7__OVRCHANDECODER__WIDTH 1 +#define SYNTH7__OVRCHANDECODER__MASK 0x00000001U +#define SYNTH7__OVRCHANDECODER__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYNTH7__OVRCHANDECODER__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define SYNTH7__OVRCHANDECODER__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYNTH7__OVRCHANDECODER__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SYNTH7__OVRCHANDECODER__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYNTH7__OVRCHANDECODER__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field FORCE_FRACLSB */ +#define SYNTH7__FORCE_FRACLSB__SHIFT 1 +#define SYNTH7__FORCE_FRACLSB__WIDTH 1 +#define SYNTH7__FORCE_FRACLSB__MASK 0x00000002U +#define SYNTH7__FORCE_FRACLSB__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define SYNTH7__FORCE_FRACLSB__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define SYNTH7__FORCE_FRACLSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define SYNTH7__FORCE_FRACLSB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define SYNTH7__FORCE_FRACLSB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define SYNTH7__FORCE_FRACLSB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field CHANFRAC */ +#define SYNTH7__CHANFRAC__SHIFT 2 +#define SYNTH7__CHANFRAC__WIDTH 17 +#define SYNTH7__CHANFRAC__MASK 0x0007fffcU +#define SYNTH7__CHANFRAC__READ(src) (((u_int32_t)(src) & 0x0007fffcU) >> 2) +#define SYNTH7__CHANFRAC__WRITE(src) (((u_int32_t)(src) << 2) & 0x0007fffcU) +#define SYNTH7__CHANFRAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0007fffcU) | (((u_int32_t)(src) <<\ + 2) & 0x0007fffcU) +#define SYNTH7__CHANFRAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0007fffcU))) + +/* macros for field CHANSEL */ +#define SYNTH7__CHANSEL__SHIFT 19 +#define SYNTH7__CHANSEL__WIDTH 9 +#define SYNTH7__CHANSEL__MASK 0x0ff80000U +#define SYNTH7__CHANSEL__READ(src) (((u_int32_t)(src) & 0x0ff80000U) >> 19) +#define SYNTH7__CHANSEL__WRITE(src) (((u_int32_t)(src) << 19) & 0x0ff80000U) +#define SYNTH7__CHANSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0ff80000U) | (((u_int32_t)(src) <<\ + 19) & 0x0ff80000U) +#define SYNTH7__CHANSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x0ff80000U))) + +/* macros for field AMODEREFSEL */ +#define SYNTH7__AMODEREFSEL__SHIFT 28 +#define SYNTH7__AMODEREFSEL__WIDTH 2 +#define SYNTH7__AMODEREFSEL__MASK 0x30000000U +#define SYNTH7__AMODEREFSEL__READ(src) (((u_int32_t)(src) & 0x30000000U) >> 28) +#define SYNTH7__AMODEREFSEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x30000000U) +#define SYNTH7__AMODEREFSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x30000000U) | (((u_int32_t)(src) <<\ + 28) & 0x30000000U) +#define SYNTH7__AMODEREFSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x30000000U))) + +/* macros for field FRACMODE */ +#define SYNTH7__FRACMODE__SHIFT 30 +#define SYNTH7__FRACMODE__WIDTH 1 +#define SYNTH7__FRACMODE__MASK 0x40000000U +#define SYNTH7__FRACMODE__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define SYNTH7__FRACMODE__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define SYNTH7__FRACMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define SYNTH7__FRACMODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define SYNTH7__FRACMODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define SYNTH7__FRACMODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field LOADSYNTHCHANNEL */ +#define SYNTH7__LOADSYNTHCHANNEL__SHIFT 31 +#define SYNTH7__LOADSYNTHCHANNEL__WIDTH 1 +#define SYNTH7__LOADSYNTHCHANNEL__MASK 0x80000000U +#define SYNTH7__LOADSYNTHCHANNEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define SYNTH7__LOADSYNTHCHANNEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define SYNTH7__LOADSYNTHCHANNEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SYNTH7__LOADSYNTHCHANNEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SYNTH7__LOADSYNTHCHANNEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH7__LOADSYNTHCHANNEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH7__TYPE u_int32_t +#define SYNTH7__READ 0xffffffffU +#define SYNTH7__WRITE 0xffffffffU + +#endif /* __SYNTH7_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH7 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH7__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH8 */ +#ifndef __SYNTH8_MACRO__ +#define __SYNTH8_MACRO__ + +/* macros for field CPSTEERING_EN_FRACN */ +#define SYNTH8__CPSTEERING_EN_FRACN__SHIFT 0 +#define SYNTH8__CPSTEERING_EN_FRACN__WIDTH 1 +#define SYNTH8__CPSTEERING_EN_FRACN__MASK 0x00000001U +#define SYNTH8__CPSTEERING_EN_FRACN__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYNTH8__CPSTEERING_EN_FRACN__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define SYNTH8__CPSTEERING_EN_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYNTH8__CPSTEERING_EN_FRACN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SYNTH8__CPSTEERING_EN_FRACN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYNTH8__CPSTEERING_EN_FRACN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field LOOP_ICPB */ +#define SYNTH8__LOOP_ICPB__SHIFT 1 +#define SYNTH8__LOOP_ICPB__WIDTH 7 +#define SYNTH8__LOOP_ICPB__MASK 0x000000feU +#define SYNTH8__LOOP_ICPB__READ(src) (((u_int32_t)(src) & 0x000000feU) >> 1) +#define SYNTH8__LOOP_ICPB__WRITE(src) (((u_int32_t)(src) << 1) & 0x000000feU) +#define SYNTH8__LOOP_ICPB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000feU) | (((u_int32_t)(src) <<\ + 1) & 0x000000feU) +#define SYNTH8__LOOP_ICPB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x000000feU))) + +/* macros for field LOOP_CSB */ +#define SYNTH8__LOOP_CSB__SHIFT 8 +#define SYNTH8__LOOP_CSB__WIDTH 4 +#define SYNTH8__LOOP_CSB__MASK 0x00000f00U +#define SYNTH8__LOOP_CSB__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) +#define SYNTH8__LOOP_CSB__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) +#define SYNTH8__LOOP_CSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SYNTH8__LOOP_CSB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field LOOP_RSB */ +#define SYNTH8__LOOP_RSB__SHIFT 12 +#define SYNTH8__LOOP_RSB__WIDTH 5 +#define SYNTH8__LOOP_RSB__MASK 0x0001f000U +#define SYNTH8__LOOP_RSB__READ(src) (((u_int32_t)(src) & 0x0001f000U) >> 12) +#define SYNTH8__LOOP_RSB__WRITE(src) (((u_int32_t)(src) << 12) & 0x0001f000U) +#define SYNTH8__LOOP_RSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define SYNTH8__LOOP_RSB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field LOOP_CPB */ +#define SYNTH8__LOOP_CPB__SHIFT 17 +#define SYNTH8__LOOP_CPB__WIDTH 5 +#define SYNTH8__LOOP_CPB__MASK 0x003e0000U +#define SYNTH8__LOOP_CPB__READ(src) (((u_int32_t)(src) & 0x003e0000U) >> 17) +#define SYNTH8__LOOP_CPB__WRITE(src) (((u_int32_t)(src) << 17) & 0x003e0000U) +#define SYNTH8__LOOP_CPB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define SYNTH8__LOOP_CPB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field LOOP_3RD_ORDER_RB */ +#define SYNTH8__LOOP_3RD_ORDER_RB__SHIFT 22 +#define SYNTH8__LOOP_3RD_ORDER_RB__WIDTH 5 +#define SYNTH8__LOOP_3RD_ORDER_RB__MASK 0x07c00000U +#define SYNTH8__LOOP_3RD_ORDER_RB__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define SYNTH8__LOOP_3RD_ORDER_RB__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define SYNTH8__LOOP_3RD_ORDER_RB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define SYNTH8__LOOP_3RD_ORDER_RB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field REFDIVB */ +#define SYNTH8__REFDIVB__SHIFT 27 +#define SYNTH8__REFDIVB__WIDTH 5 +#define SYNTH8__REFDIVB__MASK 0xf8000000U +#define SYNTH8__REFDIVB__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) +#define SYNTH8__REFDIVB__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) +#define SYNTH8__REFDIVB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define SYNTH8__REFDIVB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define SYNTH8__TYPE u_int32_t +#define SYNTH8__READ 0xffffffffU +#define SYNTH8__WRITE 0xffffffffU + +#endif /* __SYNTH8_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH8 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH8__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH9 */ +#ifndef __SYNTH9_MACRO__ +#define __SYNTH9_MACRO__ + +/* macros for field PFDDELAY_INTN */ +#define SYNTH9__PFDDELAY_INTN__SHIFT 0 +#define SYNTH9__PFDDELAY_INTN__WIDTH 1 +#define SYNTH9__PFDDELAY_INTN__MASK 0x00000001U +#define SYNTH9__PFDDELAY_INTN__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYNTH9__PFDDELAY_INTN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define SYNTH9__PFDDELAY_INTN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYNTH9__PFDDELAY_INTN__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define SYNTH9__PFDDELAY_INTN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYNTH9__PFDDELAY_INTN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field SLOPE_ICPA0 */ +#define SYNTH9__SLOPE_ICPA0__SHIFT 1 +#define SYNTH9__SLOPE_ICPA0__WIDTH 3 +#define SYNTH9__SLOPE_ICPA0__MASK 0x0000000eU +#define SYNTH9__SLOPE_ICPA0__READ(src) (((u_int32_t)(src) & 0x0000000eU) >> 1) +#define SYNTH9__SLOPE_ICPA0__WRITE(src) (((u_int32_t)(src) << 1) & 0x0000000eU) +#define SYNTH9__SLOPE_ICPA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define SYNTH9__SLOPE_ICPA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field LOOP_ICPA0 */ +#define SYNTH9__LOOP_ICPA0__SHIFT 4 +#define SYNTH9__LOOP_ICPA0__WIDTH 4 +#define SYNTH9__LOOP_ICPA0__MASK 0x000000f0U +#define SYNTH9__LOOP_ICPA0__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) +#define SYNTH9__LOOP_ICPA0__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) +#define SYNTH9__LOOP_ICPA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SYNTH9__LOOP_ICPA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field LOOP_CSA0 */ +#define SYNTH9__LOOP_CSA0__SHIFT 8 +#define SYNTH9__LOOP_CSA0__WIDTH 4 +#define SYNTH9__LOOP_CSA0__MASK 0x00000f00U +#define SYNTH9__LOOP_CSA0__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) +#define SYNTH9__LOOP_CSA0__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) +#define SYNTH9__LOOP_CSA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SYNTH9__LOOP_CSA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field LOOP_RSA0 */ +#define SYNTH9__LOOP_RSA0__SHIFT 12 +#define SYNTH9__LOOP_RSA0__WIDTH 5 +#define SYNTH9__LOOP_RSA0__MASK 0x0001f000U +#define SYNTH9__LOOP_RSA0__READ(src) (((u_int32_t)(src) & 0x0001f000U) >> 12) +#define SYNTH9__LOOP_RSA0__WRITE(src) (((u_int32_t)(src) << 12) & 0x0001f000U) +#define SYNTH9__LOOP_RSA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define SYNTH9__LOOP_RSA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field LOOP_CPA0 */ +#define SYNTH9__LOOP_CPA0__SHIFT 17 +#define SYNTH9__LOOP_CPA0__WIDTH 5 +#define SYNTH9__LOOP_CPA0__MASK 0x003e0000U +#define SYNTH9__LOOP_CPA0__READ(src) (((u_int32_t)(src) & 0x003e0000U) >> 17) +#define SYNTH9__LOOP_CPA0__WRITE(src) (((u_int32_t)(src) << 17) & 0x003e0000U) +#define SYNTH9__LOOP_CPA0__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define SYNTH9__LOOP_CPA0__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field LOOP_3RD_ORDER_RA */ +#define SYNTH9__LOOP_3RD_ORDER_RA__SHIFT 22 +#define SYNTH9__LOOP_3RD_ORDER_RA__WIDTH 5 +#define SYNTH9__LOOP_3RD_ORDER_RA__MASK 0x07c00000U +#define SYNTH9__LOOP_3RD_ORDER_RA__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define SYNTH9__LOOP_3RD_ORDER_RA__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define SYNTH9__LOOP_3RD_ORDER_RA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define SYNTH9__LOOP_3RD_ORDER_RA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field REFDIVA */ +#define SYNTH9__REFDIVA__SHIFT 27 +#define SYNTH9__REFDIVA__WIDTH 5 +#define SYNTH9__REFDIVA__MASK 0xf8000000U +#define SYNTH9__REFDIVA__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) +#define SYNTH9__REFDIVA__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) +#define SYNTH9__REFDIVA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define SYNTH9__REFDIVA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define SYNTH9__TYPE u_int32_t +#define SYNTH9__READ 0xffffffffU +#define SYNTH9__WRITE 0xffffffffU + +#endif /* __SYNTH9_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH9 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH9__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH10 */ +#ifndef __SYNTH10_MACRO__ +#define __SYNTH10_MACRO__ + +/* macros for field SPARE10A */ +#define SYNTH10__SPARE10A__SHIFT 0 +#define SYNTH10__SPARE10A__WIDTH 2 +#define SYNTH10__SPARE10A__MASK 0x00000003U +#define SYNTH10__SPARE10A__READ(src) (u_int32_t)(src) & 0x00000003U +#define SYNTH10__SPARE10A__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define SYNTH10__SPARE10A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SYNTH10__SPARE10A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field PWDB_ICLOBIAS50 */ +#define SYNTH10__PWDB_ICLOBIAS50__SHIFT 2 +#define SYNTH10__PWDB_ICLOBIAS50__WIDTH 3 +#define SYNTH10__PWDB_ICLOBIAS50__MASK 0x0000001cU +#define SYNTH10__PWDB_ICLOBIAS50__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define SYNTH10__PWDB_ICLOBIAS50__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define SYNTH10__PWDB_ICLOBIAS50__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define SYNTH10__PWDB_ICLOBIAS50__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field PWDB_IRSPARE25 */ +#define SYNTH10__PWDB_IRSPARE25__SHIFT 5 +#define SYNTH10__PWDB_IRSPARE25__WIDTH 3 +#define SYNTH10__PWDB_IRSPARE25__MASK 0x000000e0U +#define SYNTH10__PWDB_IRSPARE25__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define SYNTH10__PWDB_IRSPARE25__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define SYNTH10__PWDB_IRSPARE25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define SYNTH10__PWDB_IRSPARE25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field PWDB_ICSPARE25 */ +#define SYNTH10__PWDB_ICSPARE25__SHIFT 8 +#define SYNTH10__PWDB_ICSPARE25__WIDTH 3 +#define SYNTH10__PWDB_ICSPARE25__MASK 0x00000700U +#define SYNTH10__PWDB_ICSPARE25__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000700U) >> 8) +#define SYNTH10__PWDB_ICSPARE25__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000700U) +#define SYNTH10__PWDB_ICSPARE25__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define SYNTH10__PWDB_ICSPARE25__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field SLOPE_ICPA1 */ +#define SYNTH10__SLOPE_ICPA1__SHIFT 11 +#define SYNTH10__SLOPE_ICPA1__WIDTH 3 +#define SYNTH10__SLOPE_ICPA1__MASK 0x00003800U +#define SYNTH10__SLOPE_ICPA1__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define SYNTH10__SLOPE_ICPA1__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define SYNTH10__SLOPE_ICPA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define SYNTH10__SLOPE_ICPA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field LOOP_ICPA1 */ +#define SYNTH10__LOOP_ICPA1__SHIFT 14 +#define SYNTH10__LOOP_ICPA1__WIDTH 4 +#define SYNTH10__LOOP_ICPA1__MASK 0x0003c000U +#define SYNTH10__LOOP_ICPA1__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14) +#define SYNTH10__LOOP_ICPA1__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0003c000U) +#define SYNTH10__LOOP_ICPA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0003c000U) +#define SYNTH10__LOOP_ICPA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0003c000U))) + +/* macros for field LOOP_CSA1 */ +#define SYNTH10__LOOP_CSA1__SHIFT 18 +#define SYNTH10__LOOP_CSA1__WIDTH 4 +#define SYNTH10__LOOP_CSA1__MASK 0x003c0000U +#define SYNTH10__LOOP_CSA1__READ(src) (((u_int32_t)(src) & 0x003c0000U) >> 18) +#define SYNTH10__LOOP_CSA1__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U) +#define SYNTH10__LOOP_CSA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x003c0000U) +#define SYNTH10__LOOP_CSA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x003c0000U))) + +/* macros for field LOOP_RSA1 */ +#define SYNTH10__LOOP_RSA1__SHIFT 22 +#define SYNTH10__LOOP_RSA1__WIDTH 5 +#define SYNTH10__LOOP_RSA1__MASK 0x07c00000U +#define SYNTH10__LOOP_RSA1__READ(src) (((u_int32_t)(src) & 0x07c00000U) >> 22) +#define SYNTH10__LOOP_RSA1__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U) +#define SYNTH10__LOOP_RSA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define SYNTH10__LOOP_RSA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field LOOP_CPA1 */ +#define SYNTH10__LOOP_CPA1__SHIFT 27 +#define SYNTH10__LOOP_CPA1__WIDTH 5 +#define SYNTH10__LOOP_CPA1__MASK 0xf8000000U +#define SYNTH10__LOOP_CPA1__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) +#define SYNTH10__LOOP_CPA1__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) +#define SYNTH10__LOOP_CPA1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define SYNTH10__LOOP_CPA1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define SYNTH10__TYPE u_int32_t +#define SYNTH10__READ 0xffffffffU +#define SYNTH10__WRITE 0xffffffffU + +#endif /* __SYNTH10_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH10 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH10__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH11 */ +#ifndef __SYNTH11_MACRO__ +#define __SYNTH11_MACRO__ + +/* macros for field SPARE11A */ +#define SYNTH11__SPARE11A__SHIFT 0 +#define SYNTH11__SPARE11A__WIDTH 5 +#define SYNTH11__SPARE11A__MASK 0x0000001fU +#define SYNTH11__SPARE11A__READ(src) (u_int32_t)(src) & 0x0000001fU +#define SYNTH11__SPARE11A__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define SYNTH11__SPARE11A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define SYNTH11__SPARE11A__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field FORCE_LOBUF5G_ON */ +#define SYNTH11__FORCE_LOBUF5G_ON__SHIFT 5 +#define SYNTH11__FORCE_LOBUF5G_ON__WIDTH 1 +#define SYNTH11__FORCE_LOBUF5G_ON__MASK 0x00000020U +#define SYNTH11__FORCE_LOBUF5G_ON__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define SYNTH11__FORCE_LOBUF5G_ON__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define SYNTH11__FORCE_LOBUF5G_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define SYNTH11__FORCE_LOBUF5G_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define SYNTH11__FORCE_LOBUF5G_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define SYNTH11__FORCE_LOBUF5G_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field LOREFSEL */ +#define SYNTH11__LOREFSEL__SHIFT 6 +#define SYNTH11__LOREFSEL__WIDTH 2 +#define SYNTH11__LOREFSEL__MASK 0x000000c0U +#define SYNTH11__LOREFSEL__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6) +#define SYNTH11__LOREFSEL__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U) +#define SYNTH11__LOREFSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SYNTH11__LOREFSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field LOBUF2GTUNE */ +#define SYNTH11__LOBUF2GTUNE__SHIFT 8 +#define SYNTH11__LOBUF2GTUNE__WIDTH 2 +#define SYNTH11__LOBUF2GTUNE__MASK 0x00000300U +#define SYNTH11__LOBUF2GTUNE__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8) +#define SYNTH11__LOBUF2GTUNE__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define SYNTH11__LOBUF2GTUNE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define SYNTH11__LOBUF2GTUNE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field CPSTEERING_MODE */ +#define SYNTH11__CPSTEERING_MODE__SHIFT 10 +#define SYNTH11__CPSTEERING_MODE__WIDTH 1 +#define SYNTH11__CPSTEERING_MODE__MASK 0x00000400U +#define SYNTH11__CPSTEERING_MODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define SYNTH11__CPSTEERING_MODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define SYNTH11__CPSTEERING_MODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define SYNTH11__CPSTEERING_MODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define SYNTH11__CPSTEERING_MODE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define SYNTH11__CPSTEERING_MODE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field SLOPE_ICPA2 */ +#define SYNTH11__SLOPE_ICPA2__SHIFT 11 +#define SYNTH11__SLOPE_ICPA2__WIDTH 3 +#define SYNTH11__SLOPE_ICPA2__MASK 0x00003800U +#define SYNTH11__SLOPE_ICPA2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define SYNTH11__SLOPE_ICPA2__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define SYNTH11__SLOPE_ICPA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define SYNTH11__SLOPE_ICPA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field LOOP_ICPA2 */ +#define SYNTH11__LOOP_ICPA2__SHIFT 14 +#define SYNTH11__LOOP_ICPA2__WIDTH 4 +#define SYNTH11__LOOP_ICPA2__MASK 0x0003c000U +#define SYNTH11__LOOP_ICPA2__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14) +#define SYNTH11__LOOP_ICPA2__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0003c000U) +#define SYNTH11__LOOP_ICPA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0003c000U) +#define SYNTH11__LOOP_ICPA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0003c000U))) + +/* macros for field LOOP_CSA2 */ +#define SYNTH11__LOOP_CSA2__SHIFT 18 +#define SYNTH11__LOOP_CSA2__WIDTH 4 +#define SYNTH11__LOOP_CSA2__MASK 0x003c0000U +#define SYNTH11__LOOP_CSA2__READ(src) (((u_int32_t)(src) & 0x003c0000U) >> 18) +#define SYNTH11__LOOP_CSA2__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U) +#define SYNTH11__LOOP_CSA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x003c0000U) +#define SYNTH11__LOOP_CSA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x003c0000U))) + +/* macros for field LOOP_RSA2 */ +#define SYNTH11__LOOP_RSA2__SHIFT 22 +#define SYNTH11__LOOP_RSA2__WIDTH 5 +#define SYNTH11__LOOP_RSA2__MASK 0x07c00000U +#define SYNTH11__LOOP_RSA2__READ(src) (((u_int32_t)(src) & 0x07c00000U) >> 22) +#define SYNTH11__LOOP_RSA2__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U) +#define SYNTH11__LOOP_RSA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define SYNTH11__LOOP_RSA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field LOOP_CPA2 */ +#define SYNTH11__LOOP_CPA2__SHIFT 27 +#define SYNTH11__LOOP_CPA2__WIDTH 5 +#define SYNTH11__LOOP_CPA2__MASK 0xf8000000U +#define SYNTH11__LOOP_CPA2__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) +#define SYNTH11__LOOP_CPA2__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) +#define SYNTH11__LOOP_CPA2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define SYNTH11__LOOP_CPA2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define SYNTH11__TYPE u_int32_t +#define SYNTH11__READ 0xffffffffU +#define SYNTH11__WRITE 0xffffffffU + +#endif /* __SYNTH11_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH11 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH11__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH12 */ +#ifndef __SYNTH12_MACRO__ +#define __SYNTH12_MACRO__ + +/* macros for field SPARE12A */ +#define SYNTH12__SPARE12A__SHIFT 0 +#define SYNTH12__SPARE12A__WIDTH 10 +#define SYNTH12__SPARE12A__MASK 0x000003ffU +#define SYNTH12__SPARE12A__READ(src) (u_int32_t)(src) & 0x000003ffU +#define SYNTH12__SPARE12A__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) +#define SYNTH12__SPARE12A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define SYNTH12__SPARE12A__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU))) + +/* macros for field LOOPLEAKCUR_FRACN */ +#define SYNTH12__LOOPLEAKCUR_FRACN__SHIFT 10 +#define SYNTH12__LOOPLEAKCUR_FRACN__WIDTH 4 +#define SYNTH12__LOOPLEAKCUR_FRACN__MASK 0x00003c00U +#define SYNTH12__LOOPLEAKCUR_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003c00U) >> 10) +#define SYNTH12__LOOPLEAKCUR_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00003c00U) +#define SYNTH12__LOOPLEAKCUR_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00003c00U) +#define SYNTH12__LOOPLEAKCUR_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00003c00U))) + +/* macros for field CPLOWLK_FRACN */ +#define SYNTH12__CPLOWLK_FRACN__SHIFT 14 +#define SYNTH12__CPLOWLK_FRACN__WIDTH 1 +#define SYNTH12__CPLOWLK_FRACN__MASK 0x00004000U +#define SYNTH12__CPLOWLK_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define SYNTH12__CPLOWLK_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define SYNTH12__CPLOWLK_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define SYNTH12__CPLOWLK_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define SYNTH12__CPLOWLK_FRACN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define SYNTH12__CPLOWLK_FRACN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field CPBIAS_FRACN */ +#define SYNTH12__CPBIAS_FRACN__SHIFT 15 +#define SYNTH12__CPBIAS_FRACN__WIDTH 2 +#define SYNTH12__CPBIAS_FRACN__MASK 0x00018000U +#define SYNTH12__CPBIAS_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00018000U) >> 15) +#define SYNTH12__CPBIAS_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00018000U) +#define SYNTH12__CPBIAS_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00018000U) | (((u_int32_t)(src) <<\ + 15) & 0x00018000U) +#define SYNTH12__CPBIAS_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00018000U))) + +/* macros for field SYNTHDIGOUTEN */ +#define SYNTH12__SYNTHDIGOUTEN__SHIFT 17 +#define SYNTH12__SYNTHDIGOUTEN__WIDTH 1 +#define SYNTH12__SYNTHDIGOUTEN__MASK 0x00020000U +#define SYNTH12__SYNTHDIGOUTEN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00020000U) >> 17) +#define SYNTH12__SYNTHDIGOUTEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00020000U) +#define SYNTH12__SYNTHDIGOUTEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define SYNTH12__SYNTHDIGOUTEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define SYNTH12__SYNTHDIGOUTEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define SYNTH12__SYNTHDIGOUTEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field STRCONT */ +#define SYNTH12__STRCONT__SHIFT 18 +#define SYNTH12__STRCONT__WIDTH 1 +#define SYNTH12__STRCONT__MASK 0x00040000U +#define SYNTH12__STRCONT__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define SYNTH12__STRCONT__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define SYNTH12__STRCONT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define SYNTH12__STRCONT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define SYNTH12__STRCONT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define SYNTH12__STRCONT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field VREFMUL3 */ +#define SYNTH12__VREFMUL3__SHIFT 19 +#define SYNTH12__VREFMUL3__WIDTH 4 +#define SYNTH12__VREFMUL3__MASK 0x00780000U +#define SYNTH12__VREFMUL3__READ(src) (((u_int32_t)(src) & 0x00780000U) >> 19) +#define SYNTH12__VREFMUL3__WRITE(src) (((u_int32_t)(src) << 19) & 0x00780000U) +#define SYNTH12__VREFMUL3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00780000U) | (((u_int32_t)(src) <<\ + 19) & 0x00780000U) +#define SYNTH12__VREFMUL3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00780000U))) + +/* macros for field VREFMUL2 */ +#define SYNTH12__VREFMUL2__SHIFT 23 +#define SYNTH12__VREFMUL2__WIDTH 4 +#define SYNTH12__VREFMUL2__MASK 0x07800000U +#define SYNTH12__VREFMUL2__READ(src) (((u_int32_t)(src) & 0x07800000U) >> 23) +#define SYNTH12__VREFMUL2__WRITE(src) (((u_int32_t)(src) << 23) & 0x07800000U) +#define SYNTH12__VREFMUL2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07800000U) | (((u_int32_t)(src) <<\ + 23) & 0x07800000U) +#define SYNTH12__VREFMUL2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x07800000U))) + +/* macros for field VREFMUL1 */ +#define SYNTH12__VREFMUL1__SHIFT 27 +#define SYNTH12__VREFMUL1__WIDTH 4 +#define SYNTH12__VREFMUL1__MASK 0x78000000U +#define SYNTH12__VREFMUL1__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define SYNTH12__VREFMUL1__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define SYNTH12__VREFMUL1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define SYNTH12__VREFMUL1__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) + +/* macros for field CLK_DOUBLER_EN */ +#define SYNTH12__CLK_DOUBLER_EN__SHIFT 31 +#define SYNTH12__CLK_DOUBLER_EN__WIDTH 1 +#define SYNTH12__CLK_DOUBLER_EN__MASK 0x80000000U +#define SYNTH12__CLK_DOUBLER_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define SYNTH12__CLK_DOUBLER_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define SYNTH12__CLK_DOUBLER_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define SYNTH12__CLK_DOUBLER_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define SYNTH12__CLK_DOUBLER_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define SYNTH12__CLK_DOUBLER_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define SYNTH12__TYPE u_int32_t +#define SYNTH12__READ 0xffffffffU +#define SYNTH12__WRITE 0xffffffffU + +#endif /* __SYNTH12_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH12 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH12__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH13 */ +#ifndef __SYNTH13_MACRO__ +#define __SYNTH13_MACRO__ + +/* macros for field SPARE13A */ +#define SYNTH13__SPARE13A__SHIFT 0 +#define SYNTH13__SPARE13A__WIDTH 1 +#define SYNTH13__SPARE13A__MASK 0x00000001U +#define SYNTH13__SPARE13A__READ(src) (u_int32_t)(src) & 0x00000001U +#define SYNTH13__SPARE13A__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define SYNTH13__SPARE13A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define SYNTH13__SPARE13A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define SYNTH13__SPARE13A__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define SYNTH13__SPARE13A__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field SLOPE_ICPA_FRACN */ +#define SYNTH13__SLOPE_ICPA_FRACN__SHIFT 1 +#define SYNTH13__SLOPE_ICPA_FRACN__WIDTH 3 +#define SYNTH13__SLOPE_ICPA_FRACN__MASK 0x0000000eU +#define SYNTH13__SLOPE_ICPA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000eU) >> 1) +#define SYNTH13__SLOPE_ICPA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x0000000eU) +#define SYNTH13__SLOPE_ICPA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000eU) | (((u_int32_t)(src) <<\ + 1) & 0x0000000eU) +#define SYNTH13__SLOPE_ICPA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x0000000eU))) + +/* macros for field LOOP_ICPA_FRACN */ +#define SYNTH13__LOOP_ICPA_FRACN__SHIFT 4 +#define SYNTH13__LOOP_ICPA_FRACN__WIDTH 4 +#define SYNTH13__LOOP_ICPA_FRACN__MASK 0x000000f0U +#define SYNTH13__LOOP_ICPA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define SYNTH13__LOOP_ICPA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define SYNTH13__LOOP_ICPA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define SYNTH13__LOOP_ICPA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field LOOP_CSA_FRACN */ +#define SYNTH13__LOOP_CSA_FRACN__SHIFT 8 +#define SYNTH13__LOOP_CSA_FRACN__WIDTH 4 +#define SYNTH13__LOOP_CSA_FRACN__MASK 0x00000f00U +#define SYNTH13__LOOP_CSA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define SYNTH13__LOOP_CSA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define SYNTH13__LOOP_CSA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define SYNTH13__LOOP_CSA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field LOOP_RSA_FRACN */ +#define SYNTH13__LOOP_RSA_FRACN__SHIFT 12 +#define SYNTH13__LOOP_RSA_FRACN__WIDTH 5 +#define SYNTH13__LOOP_RSA_FRACN__MASK 0x0001f000U +#define SYNTH13__LOOP_RSA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001f000U) >> 12) +#define SYNTH13__LOOP_RSA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x0001f000U) +#define SYNTH13__LOOP_RSA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f000U) | (((u_int32_t)(src) <<\ + 12) & 0x0001f000U) +#define SYNTH13__LOOP_RSA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x0001f000U))) + +/* macros for field LOOP_CPA_FRACN */ +#define SYNTH13__LOOP_CPA_FRACN__SHIFT 17 +#define SYNTH13__LOOP_CPA_FRACN__WIDTH 5 +#define SYNTH13__LOOP_CPA_FRACN__MASK 0x003e0000U +#define SYNTH13__LOOP_CPA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x003e0000U) >> 17) +#define SYNTH13__LOOP_CPA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x003e0000U) +#define SYNTH13__LOOP_CPA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x003e0000U) +#define SYNTH13__LOOP_CPA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x003e0000U))) + +/* macros for field LOOP_3RD_ORDER_RA_FRACN */ +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__SHIFT 22 +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__WIDTH 5 +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__MASK 0x07c00000U +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0x07c00000U) >> 22) +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x07c00000U) +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x07c00000U) +#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x07c00000U))) + +/* macros for field REFDIVA_FRACN */ +#define SYNTH13__REFDIVA_FRACN__SHIFT 27 +#define SYNTH13__REFDIVA_FRACN__WIDTH 5 +#define SYNTH13__REFDIVA_FRACN__MASK 0xf8000000U +#define SYNTH13__REFDIVA_FRACN__READ(src) \ + (((u_int32_t)(src)\ + & 0xf8000000U) >> 27) +#define SYNTH13__REFDIVA_FRACN__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0xf8000000U) +#define SYNTH13__REFDIVA_FRACN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define SYNTH13__REFDIVA_FRACN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define SYNTH13__TYPE u_int32_t +#define SYNTH13__READ 0xffffffffU +#define SYNTH13__WRITE 0xffffffffU + +#endif /* __SYNTH13_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH13 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH13__NUM 1 + +/* macros for BlueprintGlobalNameSpace::SYNTH14 */ +#ifndef __SYNTH14_MACRO__ +#define __SYNTH14_MACRO__ + +/* macros for field SPARE14A */ +#define SYNTH14__SPARE14A__SHIFT 0 +#define SYNTH14__SPARE14A__WIDTH 2 +#define SYNTH14__SPARE14A__MASK 0x00000003U +#define SYNTH14__SPARE14A__READ(src) (u_int32_t)(src) & 0x00000003U +#define SYNTH14__SPARE14A__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define SYNTH14__SPARE14A__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define SYNTH14__SPARE14A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field LOBUF5GTUNE_3 */ +#define SYNTH14__LOBUF5GTUNE_3__SHIFT 2 +#define SYNTH14__LOBUF5GTUNE_3__WIDTH 2 +#define SYNTH14__LOBUF5GTUNE_3__MASK 0x0000000cU +#define SYNTH14__LOBUF5GTUNE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000000cU) >> 2) +#define SYNTH14__LOBUF5GTUNE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000000cU) +#define SYNTH14__LOBUF5GTUNE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000000cU) +#define SYNTH14__LOBUF5GTUNE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000000cU))) + +/* macros for field LOBUF2GTUNE_3 */ +#define SYNTH14__LOBUF2GTUNE_3__SHIFT 4 +#define SYNTH14__LOBUF2GTUNE_3__WIDTH 2 +#define SYNTH14__LOBUF2GTUNE_3__MASK 0x00000030U +#define SYNTH14__LOBUF2GTUNE_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000030U) >> 4) +#define SYNTH14__LOBUF2GTUNE_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000030U) +#define SYNTH14__LOBUF2GTUNE_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define SYNTH14__LOBUF2GTUNE_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000030U))) + +/* macros for field LOBUF5GTUNE_2 */ +#define SYNTH14__LOBUF5GTUNE_2__SHIFT 6 +#define SYNTH14__LOBUF5GTUNE_2__WIDTH 2 +#define SYNTH14__LOBUF5GTUNE_2__MASK 0x000000c0U +#define SYNTH14__LOBUF5GTUNE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000c0U) >> 6) +#define SYNTH14__LOBUF5GTUNE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000000c0U) +#define SYNTH14__LOBUF5GTUNE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000000c0U) +#define SYNTH14__LOBUF5GTUNE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000000c0U))) + +/* macros for field LOBUF2GTUNE_2 */ +#define SYNTH14__LOBUF2GTUNE_2__SHIFT 8 +#define SYNTH14__LOBUF2GTUNE_2__WIDTH 2 +#define SYNTH14__LOBUF2GTUNE_2__MASK 0x00000300U +#define SYNTH14__LOBUF2GTUNE_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000300U) >> 8) +#define SYNTH14__LOBUF2GTUNE_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define SYNTH14__LOBUF2GTUNE_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define SYNTH14__LOBUF2GTUNE_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field PWD_LOBUF5G_3 */ +#define SYNTH14__PWD_LOBUF5G_3__SHIFT 10 +#define SYNTH14__PWD_LOBUF5G_3__WIDTH 1 +#define SYNTH14__PWD_LOBUF5G_3__MASK 0x00000400U +#define SYNTH14__PWD_LOBUF5G_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define SYNTH14__PWD_LOBUF5G_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define SYNTH14__PWD_LOBUF5G_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define SYNTH14__PWD_LOBUF5G_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define SYNTH14__PWD_LOBUF5G_3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define SYNTH14__PWD_LOBUF5G_3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field PWD_LOBUF2G_3 */ +#define SYNTH14__PWD_LOBUF2G_3__SHIFT 11 +#define SYNTH14__PWD_LOBUF2G_3__WIDTH 1 +#define SYNTH14__PWD_LOBUF2G_3__MASK 0x00000800U +#define SYNTH14__PWD_LOBUF2G_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define SYNTH14__PWD_LOBUF2G_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define SYNTH14__PWD_LOBUF2G_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define SYNTH14__PWD_LOBUF2G_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define SYNTH14__PWD_LOBUF2G_3__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define SYNTH14__PWD_LOBUF2G_3__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field PWD_LOBUF5G_2 */ +#define SYNTH14__PWD_LOBUF5G_2__SHIFT 12 +#define SYNTH14__PWD_LOBUF5G_2__WIDTH 1 +#define SYNTH14__PWD_LOBUF5G_2__MASK 0x00001000U +#define SYNTH14__PWD_LOBUF5G_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define SYNTH14__PWD_LOBUF5G_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define SYNTH14__PWD_LOBUF5G_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define SYNTH14__PWD_LOBUF5G_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define SYNTH14__PWD_LOBUF5G_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define SYNTH14__PWD_LOBUF5G_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field PWD_LOBUF2G_2 */ +#define SYNTH14__PWD_LOBUF2G_2__SHIFT 13 +#define SYNTH14__PWD_LOBUF2G_2__WIDTH 1 +#define SYNTH14__PWD_LOBUF2G_2__MASK 0x00002000U +#define SYNTH14__PWD_LOBUF2G_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define SYNTH14__PWD_LOBUF2G_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define SYNTH14__PWD_LOBUF2G_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define SYNTH14__PWD_LOBUF2G_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define SYNTH14__PWD_LOBUF2G_2__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define SYNTH14__PWD_LOBUF2G_2__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field PWUPLO23_PD */ +#define SYNTH14__PWUPLO23_PD__SHIFT 14 +#define SYNTH14__PWUPLO23_PD__WIDTH 3 +#define SYNTH14__PWUPLO23_PD__MASK 0x0001c000U +#define SYNTH14__PWUPLO23_PD__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define SYNTH14__PWUPLO23_PD__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define SYNTH14__PWUPLO23_PD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define SYNTH14__PWUPLO23_PD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field PWDB_ICLOBUF5G50_3 */ +#define SYNTH14__PWDB_ICLOBUF5G50_3__SHIFT 17 +#define SYNTH14__PWDB_ICLOBUF5G50_3__WIDTH 3 +#define SYNTH14__PWDB_ICLOBUF5G50_3__MASK 0x000e0000U +#define SYNTH14__PWDB_ICLOBUF5G50_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define SYNTH14__PWDB_ICLOBUF5G50_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define SYNTH14__PWDB_ICLOBUF5G50_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define SYNTH14__PWDB_ICLOBUF5G50_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field PWDB_ICLOBUF2G50_3 */ +#define SYNTH14__PWDB_ICLOBUF2G50_3__SHIFT 20 +#define SYNTH14__PWDB_ICLOBUF2G50_3__WIDTH 3 +#define SYNTH14__PWDB_ICLOBUF2G50_3__MASK 0x00700000U +#define SYNTH14__PWDB_ICLOBUF2G50_3__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define SYNTH14__PWDB_ICLOBUF2G50_3__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define SYNTH14__PWDB_ICLOBUF2G50_3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define SYNTH14__PWDB_ICLOBUF2G50_3__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field PWDB_ICLOBUF5G50_2 */ +#define SYNTH14__PWDB_ICLOBUF5G50_2__SHIFT 23 +#define SYNTH14__PWDB_ICLOBUF5G50_2__WIDTH 3 +#define SYNTH14__PWDB_ICLOBUF5G50_2__MASK 0x03800000U +#define SYNTH14__PWDB_ICLOBUF5G50_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define SYNTH14__PWDB_ICLOBUF5G50_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define SYNTH14__PWDB_ICLOBUF5G50_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define SYNTH14__PWDB_ICLOBUF5G50_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field PWDB_ICLOBUF2G50_2 */ +#define SYNTH14__PWDB_ICLOBUF2G50_2__SHIFT 26 +#define SYNTH14__PWDB_ICLOBUF2G50_2__WIDTH 3 +#define SYNTH14__PWDB_ICLOBUF2G50_2__MASK 0x1c000000U +#define SYNTH14__PWDB_ICLOBUF2G50_2__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define SYNTH14__PWDB_ICLOBUF2G50_2__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define SYNTH14__PWDB_ICLOBUF2G50_2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define SYNTH14__PWDB_ICLOBUF2G50_2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field PWDB_ICLVLSHFT */ +#define SYNTH14__PWDB_ICLVLSHFT__SHIFT 29 +#define SYNTH14__PWDB_ICLVLSHFT__WIDTH 3 +#define SYNTH14__PWDB_ICLVLSHFT__MASK 0xe0000000U +#define SYNTH14__PWDB_ICLVLSHFT__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define SYNTH14__PWDB_ICLVLSHFT__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define SYNTH14__PWDB_ICLVLSHFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define SYNTH14__PWDB_ICLVLSHFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define SYNTH14__TYPE u_int32_t +#define SYNTH14__READ 0xffffffffU +#define SYNTH14__WRITE 0xffffffffU + +#endif /* __SYNTH14_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_SYNTH14 */ +#define INST_RADIO65_REG_MAP__CH0_SYNTH14__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BIAS1 */ +#ifndef __BIAS1_MACRO__ +#define __BIAS1_MACRO__ + +/* macros for field SPARE1 */ +#define BIAS1__SPARE1__SHIFT 0 +#define BIAS1__SPARE1__WIDTH 3 +#define BIAS1__SPARE1__MASK 0x00000007U +#define BIAS1__SPARE1__READ(src) (u_int32_t)(src) & 0x00000007U +#define BIAS1__SPARE1__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define BIAS1__SPARE1__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define BIAS1__SPARE1__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) + +/* macros for field pwd_ic100pcie */ +#define BIAS1__PWD_IC100PCIE__SHIFT 3 +#define BIAS1__PWD_IC100PCIE__WIDTH 3 +#define BIAS1__PWD_IC100PCIE__MASK 0x00000038U +#define BIAS1__PWD_IC100PCIE__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3) +#define BIAS1__PWD_IC100PCIE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000038U) +#define BIAS1__PWD_IC100PCIE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000038U) | (((u_int32_t)(src) <<\ + 3) & 0x00000038U) +#define BIAS1__PWD_IC100PCIE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000038U))) + +/* macros for field pwd_ic25v2iQ */ +#define BIAS1__PWD_IC25V2IQ__SHIFT 6 +#define BIAS1__PWD_IC25V2IQ__WIDTH 3 +#define BIAS1__PWD_IC25V2IQ__MASK 0x000001c0U +#define BIAS1__PWD_IC25V2IQ__READ(src) (((u_int32_t)(src) & 0x000001c0U) >> 6) +#define BIAS1__PWD_IC25V2IQ__WRITE(src) (((u_int32_t)(src) << 6) & 0x000001c0U) +#define BIAS1__PWD_IC25V2IQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define BIAS1__PWD_IC25V2IQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field pwd_ic25v2iI */ +#define BIAS1__PWD_IC25V2II__SHIFT 9 +#define BIAS1__PWD_IC25V2II__WIDTH 3 +#define BIAS1__PWD_IC25V2II__MASK 0x00000e00U +#define BIAS1__PWD_IC25V2II__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) +#define BIAS1__PWD_IC25V2II__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U) +#define BIAS1__PWD_IC25V2II__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define BIAS1__PWD_IC25V2II__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field pwd_ic25bb */ +#define BIAS1__PWD_IC25BB__SHIFT 12 +#define BIAS1__PWD_IC25BB__WIDTH 3 +#define BIAS1__PWD_IC25BB__MASK 0x00007000U +#define BIAS1__PWD_IC25BB__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12) +#define BIAS1__PWD_IC25BB__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U) +#define BIAS1__PWD_IC25BB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define BIAS1__PWD_IC25BB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field pwd_ic25dac */ +#define BIAS1__PWD_IC25DAC__SHIFT 15 +#define BIAS1__PWD_IC25DAC__WIDTH 3 +#define BIAS1__PWD_IC25DAC__MASK 0x00038000U +#define BIAS1__PWD_IC25DAC__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) +#define BIAS1__PWD_IC25DAC__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) +#define BIAS1__PWD_IC25DAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define BIAS1__PWD_IC25DAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field pwd_ic25fir */ +#define BIAS1__PWD_IC25FIR__SHIFT 18 +#define BIAS1__PWD_IC25FIR__WIDTH 3 +#define BIAS1__PWD_IC25FIR__MASK 0x001c0000U +#define BIAS1__PWD_IC25FIR__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18) +#define BIAS1__PWD_IC25FIR__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U) +#define BIAS1__PWD_IC25FIR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define BIAS1__PWD_IC25FIR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field pwd_ic25adc */ +#define BIAS1__PWD_IC25ADC__SHIFT 21 +#define BIAS1__PWD_IC25ADC__WIDTH 3 +#define BIAS1__PWD_IC25ADC__MASK 0x00e00000U +#define BIAS1__PWD_IC25ADC__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21) +#define BIAS1__PWD_IC25ADC__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U) +#define BIAS1__PWD_IC25ADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define BIAS1__PWD_IC25ADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field bias_sel */ +#define BIAS1__BIAS_SEL__SHIFT 24 +#define BIAS1__BIAS_SEL__WIDTH 8 +#define BIAS1__BIAS_SEL__MASK 0xff000000U +#define BIAS1__BIAS_SEL__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) +#define BIAS1__BIAS_SEL__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) +#define BIAS1__BIAS_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xff000000U) | (((u_int32_t)(src) <<\ + 24) & 0xff000000U) +#define BIAS1__BIAS_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0xff000000U))) +#define BIAS1__TYPE u_int32_t +#define BIAS1__READ 0xffffffffU +#define BIAS1__WRITE 0xffffffffU + +#endif /* __BIAS1_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_BIAS1 */ +#define INST_RADIO65_REG_MAP__CH0_BIAS1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BIAS2 */ +#ifndef __BIAS2_MACRO__ +#define __BIAS2_MACRO__ + +/* macros for field SPARE2 */ +#define BIAS2__SPARE2__SHIFT 0 +#define BIAS2__SPARE2__WIDTH 5 +#define BIAS2__SPARE2__MASK 0x0000001fU +#define BIAS2__SPARE2__READ(src) (u_int32_t)(src) & 0x0000001fU +#define BIAS2__SPARE2__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) +#define BIAS2__SPARE2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define BIAS2__SPARE2__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) + +/* macros for field pwd_ic25xtalreg */ +#define BIAS2__PWD_IC25XTALREG__SHIFT 5 +#define BIAS2__PWD_IC25XTALREG__WIDTH 3 +#define BIAS2__PWD_IC25XTALREG__MASK 0x000000e0U +#define BIAS2__PWD_IC25XTALREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000e0U) >> 5) +#define BIAS2__PWD_IC25XTALREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x000000e0U) +#define BIAS2__PWD_IC25XTALREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define BIAS2__PWD_IC25XTALREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field pwd_ic25xtal */ +#define BIAS2__PWD_IC25XTAL__SHIFT 8 +#define BIAS2__PWD_IC25XTAL__WIDTH 3 +#define BIAS2__PWD_IC25XTAL__MASK 0x00000700U +#define BIAS2__PWD_IC25XTAL__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) +#define BIAS2__PWD_IC25XTAL__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U) +#define BIAS2__PWD_IC25XTAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define BIAS2__PWD_IC25XTAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field pwd_ic25txrf */ +#define BIAS2__PWD_IC25TXRF__SHIFT 11 +#define BIAS2__PWD_IC25TXRF__WIDTH 3 +#define BIAS2__PWD_IC25TXRF__MASK 0x00003800U +#define BIAS2__PWD_IC25TXRF__READ(src) (((u_int32_t)(src) & 0x00003800U) >> 11) +#define BIAS2__PWD_IC25TXRF__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define BIAS2__PWD_IC25TXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define BIAS2__PWD_IC25TXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field pwd_ic25rxrf */ +#define BIAS2__PWD_IC25RXRF__SHIFT 14 +#define BIAS2__PWD_IC25RXRF__WIDTH 3 +#define BIAS2__PWD_IC25RXRF__MASK 0x0001c000U +#define BIAS2__PWD_IC25RXRF__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) +#define BIAS2__PWD_IC25RXRF__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define BIAS2__PWD_IC25RXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define BIAS2__PWD_IC25RXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field pwd_ic25synth */ +#define BIAS2__PWD_IC25SYNTH__SHIFT 17 +#define BIAS2__PWD_IC25SYNTH__WIDTH 3 +#define BIAS2__PWD_IC25SYNTH__MASK 0x000e0000U +#define BIAS2__PWD_IC25SYNTH__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define BIAS2__PWD_IC25SYNTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define BIAS2__PWD_IC25SYNTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define BIAS2__PWD_IC25SYNTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field pwd_ic25pllreg */ +#define BIAS2__PWD_IC25PLLREG__SHIFT 20 +#define BIAS2__PWD_IC25PLLREG__WIDTH 3 +#define BIAS2__PWD_IC25PLLREG__MASK 0x00700000U +#define BIAS2__PWD_IC25PLLREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define BIAS2__PWD_IC25PLLREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define BIAS2__PWD_IC25PLLREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define BIAS2__PWD_IC25PLLREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field pwd_ic25pllcp2 */ +#define BIAS2__PWD_IC25PLLCP2__SHIFT 23 +#define BIAS2__PWD_IC25PLLCP2__WIDTH 3 +#define BIAS2__PWD_IC25PLLCP2__MASK 0x03800000U +#define BIAS2__PWD_IC25PLLCP2__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define BIAS2__PWD_IC25PLLCP2__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define BIAS2__PWD_IC25PLLCP2__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define BIAS2__PWD_IC25PLLCP2__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field pwd_ic25pllcp */ +#define BIAS2__PWD_IC25PLLCP__SHIFT 26 +#define BIAS2__PWD_IC25PLLCP__WIDTH 3 +#define BIAS2__PWD_IC25PLLCP__MASK 0x1c000000U +#define BIAS2__PWD_IC25PLLCP__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define BIAS2__PWD_IC25PLLCP__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define BIAS2__PWD_IC25PLLCP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define BIAS2__PWD_IC25PLLCP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field pwd_ic25pllgm */ +#define BIAS2__PWD_IC25PLLGM__SHIFT 29 +#define BIAS2__PWD_IC25PLLGM__WIDTH 3 +#define BIAS2__PWD_IC25PLLGM__MASK 0xe0000000U +#define BIAS2__PWD_IC25PLLGM__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define BIAS2__PWD_IC25PLLGM__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define BIAS2__PWD_IC25PLLGM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define BIAS2__PWD_IC25PLLGM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define BIAS2__TYPE u_int32_t +#define BIAS2__READ 0xffffffffU +#define BIAS2__WRITE 0xffffffffU + +#endif /* __BIAS2_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_BIAS2 */ +#define INST_RADIO65_REG_MAP__CH0_BIAS2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BIAS3 */ +#ifndef __BIAS3_MACRO__ +#define __BIAS3_MACRO__ + +/* macros for field SPARE3 */ +#define BIAS3__SPARE3__SHIFT 0 +#define BIAS3__SPARE3__WIDTH 2 +#define BIAS3__SPARE3__MASK 0x00000003U +#define BIAS3__SPARE3__READ(src) (u_int32_t)(src) & 0x00000003U +#define BIAS3__SPARE3__WRITE(src) ((u_int32_t)(src) & 0x00000003U) +#define BIAS3__SPARE3__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define BIAS3__SPARE3__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) + +/* macros for field pwd_ir25xtalreg */ +#define BIAS3__PWD_IR25XTALREG__SHIFT 2 +#define BIAS3__PWD_IR25XTALREG__WIDTH 3 +#define BIAS3__PWD_IR25XTALREG__MASK 0x0000001cU +#define BIAS3__PWD_IR25XTALREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000001cU) >> 2) +#define BIAS3__PWD_IR25XTALREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x0000001cU) +#define BIAS3__PWD_IR25XTALREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000001cU) +#define BIAS3__PWD_IR25XTALREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000001cU))) + +/* macros for field pwd_ir25txrf */ +#define BIAS3__PWD_IR25TXRF__SHIFT 5 +#define BIAS3__PWD_IR25TXRF__WIDTH 3 +#define BIAS3__PWD_IR25TXRF__MASK 0x000000e0U +#define BIAS3__PWD_IR25TXRF__READ(src) (((u_int32_t)(src) & 0x000000e0U) >> 5) +#define BIAS3__PWD_IR25TXRF__WRITE(src) (((u_int32_t)(src) << 5) & 0x000000e0U) +#define BIAS3__PWD_IR25TXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000e0U) | (((u_int32_t)(src) <<\ + 5) & 0x000000e0U) +#define BIAS3__PWD_IR25TXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x000000e0U))) + +/* macros for field pwd_ir25rxrf */ +#define BIAS3__PWD_IR25RXRF__SHIFT 8 +#define BIAS3__PWD_IR25RXRF__WIDTH 3 +#define BIAS3__PWD_IR25RXRF__MASK 0x00000700U +#define BIAS3__PWD_IR25RXRF__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) +#define BIAS3__PWD_IR25RXRF__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U) +#define BIAS3__PWD_IR25RXRF__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000700U) | (((u_int32_t)(src) <<\ + 8) & 0x00000700U) +#define BIAS3__PWD_IR25RXRF__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000700U))) + +/* macros for field pwd_ir25synth */ +#define BIAS3__PWD_IR25SYNTH__SHIFT 11 +#define BIAS3__PWD_IR25SYNTH__WIDTH 3 +#define BIAS3__PWD_IR25SYNTH__MASK 0x00003800U +#define BIAS3__PWD_IR25SYNTH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003800U) >> 11) +#define BIAS3__PWD_IR25SYNTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00003800U) +#define BIAS3__PWD_IR25SYNTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003800U) | (((u_int32_t)(src) <<\ + 11) & 0x00003800U) +#define BIAS3__PWD_IR25SYNTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00003800U))) + +/* macros for field pwd_ir25pllreg */ +#define BIAS3__PWD_IR25PLLREG__SHIFT 14 +#define BIAS3__PWD_IR25PLLREG__WIDTH 3 +#define BIAS3__PWD_IR25PLLREG__MASK 0x0001c000U +#define BIAS3__PWD_IR25PLLREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define BIAS3__PWD_IR25PLLREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define BIAS3__PWD_IR25PLLREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define BIAS3__PWD_IR25PLLREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field pwd_ir25bb */ +#define BIAS3__PWD_IR25BB__SHIFT 17 +#define BIAS3__PWD_IR25BB__WIDTH 3 +#define BIAS3__PWD_IR25BB__MASK 0x000e0000U +#define BIAS3__PWD_IR25BB__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) +#define BIAS3__PWD_IR25BB__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) +#define BIAS3__PWD_IR25BB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define BIAS3__PWD_IR25BB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field pwd_ir50dac */ +#define BIAS3__PWD_IR50DAC__SHIFT 20 +#define BIAS3__PWD_IR50DAC__WIDTH 3 +#define BIAS3__PWD_IR50DAC__MASK 0x00700000U +#define BIAS3__PWD_IR50DAC__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) +#define BIAS3__PWD_IR50DAC__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) +#define BIAS3__PWD_IR50DAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define BIAS3__PWD_IR50DAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field pwd_ir25dac */ +#define BIAS3__PWD_IR25DAC__SHIFT 23 +#define BIAS3__PWD_IR25DAC__WIDTH 3 +#define BIAS3__PWD_IR25DAC__MASK 0x03800000U +#define BIAS3__PWD_IR25DAC__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) +#define BIAS3__PWD_IR25DAC__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) +#define BIAS3__PWD_IR25DAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define BIAS3__PWD_IR25DAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field pwd_ir25fir */ +#define BIAS3__PWD_IR25FIR__SHIFT 26 +#define BIAS3__PWD_IR25FIR__WIDTH 3 +#define BIAS3__PWD_IR25FIR__MASK 0x1c000000U +#define BIAS3__PWD_IR25FIR__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define BIAS3__PWD_IR25FIR__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define BIAS3__PWD_IR25FIR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define BIAS3__PWD_IR25FIR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field pwd_ir50adc */ +#define BIAS3__PWD_IR50ADC__SHIFT 29 +#define BIAS3__PWD_IR50ADC__WIDTH 3 +#define BIAS3__PWD_IR50ADC__MASK 0xe0000000U +#define BIAS3__PWD_IR50ADC__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define BIAS3__PWD_IR50ADC__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define BIAS3__PWD_IR50ADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define BIAS3__PWD_IR50ADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define BIAS3__TYPE u_int32_t +#define BIAS3__READ 0xffffffffU +#define BIAS3__WRITE 0xffffffffU + +#endif /* __BIAS3_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_BIAS3 */ +#define INST_RADIO65_REG_MAP__CH0_BIAS3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BIAS4 */ +#ifndef __BIAS4_MACRO__ +#define __BIAS4_MACRO__ + +/* macros for field SPARE4 */ +#define BIAS4__SPARE4__SHIFT 0 +#define BIAS4__SPARE4__WIDTH 14 +#define BIAS4__SPARE4__MASK 0x00003fffU +#define BIAS4__SPARE4__READ(src) (u_int32_t)(src) & 0x00003fffU +#define BIAS4__SPARE4__WRITE(src) ((u_int32_t)(src) & 0x00003fffU) +#define BIAS4__SPARE4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003fffU) | ((u_int32_t)(src) &\ + 0x00003fffU) +#define BIAS4__SPARE4__VERIFY(src) (!(((u_int32_t)(src) & ~0x00003fffU))) + +/* macros for field pwd_ir25xpabias */ +#define BIAS4__PWD_IR25XPABIAS__SHIFT 14 +#define BIAS4__PWD_IR25XPABIAS__WIDTH 3 +#define BIAS4__PWD_IR25XPABIAS__MASK 0x0001c000U +#define BIAS4__PWD_IR25XPABIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x0001c000U) >> 14) +#define BIAS4__PWD_IR25XPABIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x0001c000U) +#define BIAS4__PWD_IR25XPABIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001c000U) | (((u_int32_t)(src) <<\ + 14) & 0x0001c000U) +#define BIAS4__PWD_IR25XPABIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x0001c000U))) + +/* macros for field pwd_ir25thermadc */ +#define BIAS4__PWD_IR25THERMADC__SHIFT 17 +#define BIAS4__PWD_IR25THERMADC__WIDTH 3 +#define BIAS4__PWD_IR25THERMADC__MASK 0x000e0000U +#define BIAS4__PWD_IR25THERMADC__READ(src) \ + (((u_int32_t)(src)\ + & 0x000e0000U) >> 17) +#define BIAS4__PWD_IR25THERMADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x000e0000U) +#define BIAS4__PWD_IR25THERMADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000e0000U) | (((u_int32_t)(src) <<\ + 17) & 0x000e0000U) +#define BIAS4__PWD_IR25THERMADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x000e0000U))) + +/* macros for field pwd_ir25otpreg */ +#define BIAS4__PWD_IR25OTPREG__SHIFT 20 +#define BIAS4__PWD_IR25OTPREG__WIDTH 3 +#define BIAS4__PWD_IR25OTPREG__MASK 0x00700000U +#define BIAS4__PWD_IR25OTPREG__READ(src) \ + (((u_int32_t)(src)\ + & 0x00700000U) >> 20) +#define BIAS4__PWD_IR25OTPREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00700000U) +#define BIAS4__PWD_IR25OTPREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00700000U) | (((u_int32_t)(src) <<\ + 20) & 0x00700000U) +#define BIAS4__PWD_IR25OTPREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00700000U))) + +/* macros for field pwd_ic25xpabias */ +#define BIAS4__PWD_IC25XPABIAS__SHIFT 23 +#define BIAS4__PWD_IC25XPABIAS__WIDTH 3 +#define BIAS4__PWD_IC25XPABIAS__MASK 0x03800000U +#define BIAS4__PWD_IC25XPABIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x03800000U) >> 23) +#define BIAS4__PWD_IC25XPABIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 23) & 0x03800000U) +#define BIAS4__PWD_IC25XPABIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03800000U) | (((u_int32_t)(src) <<\ + 23) & 0x03800000U) +#define BIAS4__PWD_IC25XPABIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x03800000U))) + +/* macros for field pwd_ic25spareB */ +#define BIAS4__PWD_IC25SPAREB__SHIFT 26 +#define BIAS4__PWD_IC25SPAREB__WIDTH 3 +#define BIAS4__PWD_IC25SPAREB__MASK 0x1c000000U +#define BIAS4__PWD_IC25SPAREB__READ(src) \ + (((u_int32_t)(src)\ + & 0x1c000000U) >> 26) +#define BIAS4__PWD_IC25SPAREB__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x1c000000U) +#define BIAS4__PWD_IC25SPAREB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define BIAS4__PWD_IC25SPAREB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field pwd_ic25spareA */ +#define BIAS4__PWD_IC25SPAREA__SHIFT 29 +#define BIAS4__PWD_IC25SPAREA__WIDTH 3 +#define BIAS4__PWD_IC25SPAREA__MASK 0xe0000000U +#define BIAS4__PWD_IC25SPAREA__READ(src) \ + (((u_int32_t)(src)\ + & 0xe0000000U) >> 29) +#define BIAS4__PWD_IC25SPAREA__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0xe0000000U) +#define BIAS4__PWD_IC25SPAREA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define BIAS4__PWD_IC25SPAREA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define BIAS4__TYPE u_int32_t +#define BIAS4__READ 0xffffffffU +#define BIAS4__WRITE 0xffffffffU + +#endif /* __BIAS4_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_BIAS4 */ +#define INST_RADIO65_REG_MAP__CH0_BIAS4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXTX1 */ +#ifndef __RXTX1_MACRO__ +#define __RXTX1_MACRO__ + +/* macros for field scfir_gain */ +#define RXTX1__SCFIR_GAIN__SHIFT 0 +#define RXTX1__SCFIR_GAIN__WIDTH 1 +#define RXTX1__SCFIR_GAIN__MASK 0x00000001U +#define RXTX1__SCFIR_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXTX1__SCFIR_GAIN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXTX1__SCFIR_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXTX1__SCFIR_GAIN__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define RXTX1__SCFIR_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXTX1__SCFIR_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field manrxgain */ +#define RXTX1__MANRXGAIN__SHIFT 1 +#define RXTX1__MANRXGAIN__WIDTH 1 +#define RXTX1__MANRXGAIN__MASK 0x00000002U +#define RXTX1__MANRXGAIN__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define RXTX1__MANRXGAIN__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define RXTX1__MANRXGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RXTX1__MANRXGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RXTX1__MANRXGAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RXTX1__MANRXGAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field agc_dbdac */ +#define RXTX1__AGC_DBDAC__SHIFT 2 +#define RXTX1__AGC_DBDAC__WIDTH 4 +#define RXTX1__AGC_DBDAC__MASK 0x0000003cU +#define RXTX1__AGC_DBDAC__READ(src) (((u_int32_t)(src) & 0x0000003cU) >> 2) +#define RXTX1__AGC_DBDAC__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000003cU) +#define RXTX1__AGC_DBDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003cU) | (((u_int32_t)(src) <<\ + 2) & 0x0000003cU) +#define RXTX1__AGC_DBDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x0000003cU))) + +/* macros for field ovr_agc_dbdac */ +#define RXTX1__OVR_AGC_DBDAC__SHIFT 6 +#define RXTX1__OVR_AGC_DBDAC__WIDTH 1 +#define RXTX1__OVR_AGC_DBDAC__MASK 0x00000040U +#define RXTX1__OVR_AGC_DBDAC__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define RXTX1__OVR_AGC_DBDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RXTX1__OVR_AGC_DBDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RXTX1__OVR_AGC_DBDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RXTX1__OVR_AGC_DBDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RXTX1__OVR_AGC_DBDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field enable_PAL */ +#define RXTX1__ENABLE_PAL__SHIFT 7 +#define RXTX1__ENABLE_PAL__WIDTH 1 +#define RXTX1__ENABLE_PAL__MASK 0x00000080U +#define RXTX1__ENABLE_PAL__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define RXTX1__ENABLE_PAL__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) +#define RXTX1__ENABLE_PAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RXTX1__ENABLE_PAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RXTX1__ENABLE_PAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RXTX1__ENABLE_PAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field enable_PAL_ovr */ +#define RXTX1__ENABLE_PAL_OVR__SHIFT 8 +#define RXTX1__ENABLE_PAL_OVR__WIDTH 1 +#define RXTX1__ENABLE_PAL_OVR__MASK 0x00000100U +#define RXTX1__ENABLE_PAL_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define RXTX1__ENABLE_PAL_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define RXTX1__ENABLE_PAL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RXTX1__ENABLE_PAL_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RXTX1__ENABLE_PAL_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RXTX1__ENABLE_PAL_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field tx1db_biquad */ +#define RXTX1__TX1DB_BIQUAD__SHIFT 9 +#define RXTX1__TX1DB_BIQUAD__WIDTH 3 +#define RXTX1__TX1DB_BIQUAD__MASK 0x00000e00U +#define RXTX1__TX1DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) +#define RXTX1__TX1DB_BIQUAD__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U) +#define RXTX1__TX1DB_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define RXTX1__TX1DB_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field tx6db_biquad */ +#define RXTX1__TX6DB_BIQUAD__SHIFT 12 +#define RXTX1__TX6DB_BIQUAD__WIDTH 2 +#define RXTX1__TX6DB_BIQUAD__MASK 0x00003000U +#define RXTX1__TX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00003000U) >> 12) +#define RXTX1__TX6DB_BIQUAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00003000U) +#define RXTX1__TX6DB_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003000U) | (((u_int32_t)(src) <<\ + 12) & 0x00003000U) +#define RXTX1__TX6DB_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00003000U))) + +/* macros for field padrvhalfgn2g */ +#define RXTX1__PADRVHALFGN2G__SHIFT 14 +#define RXTX1__PADRVHALFGN2G__WIDTH 1 +#define RXTX1__PADRVHALFGN2G__MASK 0x00004000U +#define RXTX1__PADRVHALFGN2G__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RXTX1__PADRVHALFGN2G__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RXTX1__PADRVHALFGN2G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RXTX1__PADRVHALFGN2G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RXTX1__PADRVHALFGN2G__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RXTX1__PADRVHALFGN2G__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field padrv2gn */ +#define RXTX1__PADRV2GN__SHIFT 15 +#define RXTX1__PADRV2GN__WIDTH 4 +#define RXTX1__PADRV2GN__MASK 0x00078000U +#define RXTX1__PADRV2GN__READ(src) (((u_int32_t)(src) & 0x00078000U) >> 15) +#define RXTX1__PADRV2GN__WRITE(src) (((u_int32_t)(src) << 15) & 0x00078000U) +#define RXTX1__PADRV2GN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00078000U) | (((u_int32_t)(src) <<\ + 15) & 0x00078000U) +#define RXTX1__PADRV2GN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00078000U))) + +/* macros for field padrv3gn5g */ +#define RXTX1__PADRV3GN5G__SHIFT 19 +#define RXTX1__PADRV3GN5G__WIDTH 4 +#define RXTX1__PADRV3GN5G__MASK 0x00780000U +#define RXTX1__PADRV3GN5G__READ(src) (((u_int32_t)(src) & 0x00780000U) >> 19) +#define RXTX1__PADRV3GN5G__WRITE(src) (((u_int32_t)(src) << 19) & 0x00780000U) +#define RXTX1__PADRV3GN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00780000U) | (((u_int32_t)(src) <<\ + 19) & 0x00780000U) +#define RXTX1__PADRV3GN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00780000U))) + +/* macros for field padrv4gn5g */ +#define RXTX1__PADRV4GN5G__SHIFT 23 +#define RXTX1__PADRV4GN5G__WIDTH 4 +#define RXTX1__PADRV4GN5G__MASK 0x07800000U +#define RXTX1__PADRV4GN5G__READ(src) (((u_int32_t)(src) & 0x07800000U) >> 23) +#define RXTX1__PADRV4GN5G__WRITE(src) (((u_int32_t)(src) << 23) & 0x07800000U) +#define RXTX1__PADRV4GN5G__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07800000U) | (((u_int32_t)(src) <<\ + 23) & 0x07800000U) +#define RXTX1__PADRV4GN5G__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x07800000U))) + +/* macros for field txbb_gc */ +#define RXTX1__TXBB_GC__SHIFT 27 +#define RXTX1__TXBB_GC__WIDTH 4 +#define RXTX1__TXBB_GC__MASK 0x78000000U +#define RXTX1__TXBB_GC__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) +#define RXTX1__TXBB_GC__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) +#define RXTX1__TXBB_GC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x78000000U) | (((u_int32_t)(src) <<\ + 27) & 0x78000000U) +#define RXTX1__TXBB_GC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x78000000U))) + +/* macros for field mantxgain */ +#define RXTX1__MANTXGAIN__SHIFT 31 +#define RXTX1__MANTXGAIN__WIDTH 1 +#define RXTX1__MANTXGAIN__MASK 0x80000000U +#define RXTX1__MANTXGAIN__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define RXTX1__MANTXGAIN__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) +#define RXTX1__MANTXGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RXTX1__MANTXGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RXTX1__MANTXGAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RXTX1__MANTXGAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RXTX1__TYPE u_int32_t +#define RXTX1__READ 0xffffffffU +#define RXTX1__WRITE 0xffffffffU + +#endif /* __RXTX1_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_RXTX1 */ +#define INST_RADIO65_REG_MAP__CH0_RXTX1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXTX2 */ +#ifndef __RXTX2_MACRO__ +#define __RXTX2_MACRO__ + +/* macros for field bmode */ +#define RXTX2__BMODE__SHIFT 0 +#define RXTX2__BMODE__WIDTH 1 +#define RXTX2__BMODE__MASK 0x00000001U +#define RXTX2__BMODE__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXTX2__BMODE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXTX2__BMODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXTX2__BMODE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define RXTX2__BMODE__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define RXTX2__BMODE__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) + +/* macros for field bmode_ovr */ +#define RXTX2__BMODE_OVR__SHIFT 1 +#define RXTX2__BMODE_OVR__WIDTH 1 +#define RXTX2__BMODE_OVR__MASK 0x00000002U +#define RXTX2__BMODE_OVR__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define RXTX2__BMODE_OVR__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define RXTX2__BMODE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RXTX2__BMODE_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RXTX2__BMODE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RXTX2__BMODE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field synthon */ +#define RXTX2__SYNTHON__SHIFT 2 +#define RXTX2__SYNTHON__WIDTH 1 +#define RXTX2__SYNTHON__MASK 0x00000004U +#define RXTX2__SYNTHON__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define RXTX2__SYNTHON__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define RXTX2__SYNTHON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RXTX2__SYNTHON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RXTX2__SYNTHON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RXTX2__SYNTHON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field synthon_ovr */ +#define RXTX2__SYNTHON_OVR__SHIFT 3 +#define RXTX2__SYNTHON_OVR__WIDTH 1 +#define RXTX2__SYNTHON_OVR__MASK 0x00000008U +#define RXTX2__SYNTHON_OVR__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define RXTX2__SYNTHON_OVR__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define RXTX2__SYNTHON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RXTX2__SYNTHON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RXTX2__SYNTHON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RXTX2__SYNTHON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field BW_ST */ +#define RXTX2__BW_ST__SHIFT 4 +#define RXTX2__BW_ST__WIDTH 2 +#define RXTX2__BW_ST__MASK 0x00000030U +#define RXTX2__BW_ST__READ(src) (((u_int32_t)(src) & 0x00000030U) >> 4) +#define RXTX2__BW_ST__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000030U) +#define RXTX2__BW_ST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000030U) | (((u_int32_t)(src) <<\ + 4) & 0x00000030U) +#define RXTX2__BW_ST__VERIFY(src) (!((((u_int32_t)(src) << 4) & ~0x00000030U))) + +/* macros for field BW_ST_ovr */ +#define RXTX2__BW_ST_OVR__SHIFT 6 +#define RXTX2__BW_ST_OVR__WIDTH 1 +#define RXTX2__BW_ST_OVR__MASK 0x00000040U +#define RXTX2__BW_ST_OVR__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define RXTX2__BW_ST_OVR__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) +#define RXTX2__BW_ST_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RXTX2__BW_ST_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RXTX2__BW_ST_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RXTX2__BW_ST_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field txon */ +#define RXTX2__TXON__SHIFT 7 +#define RXTX2__TXON__WIDTH 1 +#define RXTX2__TXON__MASK 0x00000080U +#define RXTX2__TXON__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define RXTX2__TXON__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) +#define RXTX2__TXON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RXTX2__TXON__VERIFY(src) (!((((u_int32_t)(src) << 7) & ~0x00000080U))) +#define RXTX2__TXON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RXTX2__TXON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field txon_ovr */ +#define RXTX2__TXON_OVR__SHIFT 8 +#define RXTX2__TXON_OVR__WIDTH 1 +#define RXTX2__TXON_OVR__MASK 0x00000100U +#define RXTX2__TXON_OVR__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define RXTX2__TXON_OVR__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) +#define RXTX2__TXON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RXTX2__TXON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RXTX2__TXON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RXTX2__TXON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field paon */ +#define RXTX2__PAON__SHIFT 9 +#define RXTX2__PAON__WIDTH 1 +#define RXTX2__PAON__MASK 0x00000200U +#define RXTX2__PAON__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define RXTX2__PAON__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) +#define RXTX2__PAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define RXTX2__PAON__VERIFY(src) (!((((u_int32_t)(src) << 9) & ~0x00000200U))) +#define RXTX2__PAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define RXTX2__PAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field paon_ovr */ +#define RXTX2__PAON_OVR__SHIFT 10 +#define RXTX2__PAON_OVR__WIDTH 1 +#define RXTX2__PAON_OVR__MASK 0x00000400U +#define RXTX2__PAON_OVR__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define RXTX2__PAON_OVR__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) +#define RXTX2__PAON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RXTX2__PAON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RXTX2__PAON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RXTX2__PAON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field rxon */ +#define RXTX2__RXON__SHIFT 11 +#define RXTX2__RXON__WIDTH 1 +#define RXTX2__RXON__MASK 0x00000800U +#define RXTX2__RXON__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define RXTX2__RXON__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define RXTX2__RXON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define RXTX2__RXON__VERIFY(src) (!((((u_int32_t)(src) << 11) & ~0x00000800U))) +#define RXTX2__RXON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define RXTX2__RXON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field rxon_ovr */ +#define RXTX2__RXON_OVR__SHIFT 12 +#define RXTX2__RXON_OVR__WIDTH 1 +#define RXTX2__RXON_OVR__MASK 0x00001000U +#define RXTX2__RXON_OVR__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) +#define RXTX2__RXON_OVR__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) +#define RXTX2__RXON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define RXTX2__RXON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define RXTX2__RXON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define RXTX2__RXON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field agcon */ +#define RXTX2__AGCON__SHIFT 13 +#define RXTX2__AGCON__WIDTH 1 +#define RXTX2__AGCON__MASK 0x00002000U +#define RXTX2__AGCON__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) +#define RXTX2__AGCON__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U) +#define RXTX2__AGCON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RXTX2__AGCON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RXTX2__AGCON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RXTX2__AGCON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field agcon_ovr */ +#define RXTX2__AGCON_OVR__SHIFT 14 +#define RXTX2__AGCON_OVR__WIDTH 1 +#define RXTX2__AGCON_OVR__MASK 0x00004000U +#define RXTX2__AGCON_OVR__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) +#define RXTX2__AGCON_OVR__WRITE(src) (((u_int32_t)(src) << 14) & 0x00004000U) +#define RXTX2__AGCON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RXTX2__AGCON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RXTX2__AGCON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RXTX2__AGCON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field txmod */ +#define RXTX2__TXMOD__SHIFT 15 +#define RXTX2__TXMOD__WIDTH 3 +#define RXTX2__TXMOD__MASK 0x00038000U +#define RXTX2__TXMOD__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) +#define RXTX2__TXMOD__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) +#define RXTX2__TXMOD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define RXTX2__TXMOD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field txmod_ovr */ +#define RXTX2__TXMOD_OVR__SHIFT 18 +#define RXTX2__TXMOD_OVR__WIDTH 1 +#define RXTX2__TXMOD_OVR__MASK 0x00040000U +#define RXTX2__TXMOD_OVR__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define RXTX2__TXMOD_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define RXTX2__TXMOD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define RXTX2__TXMOD_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define RXTX2__TXMOD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define RXTX2__TXMOD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field rx1db_biquad */ +#define RXTX2__RX1DB_BIQUAD__SHIFT 19 +#define RXTX2__RX1DB_BIQUAD__WIDTH 3 +#define RXTX2__RX1DB_BIQUAD__MASK 0x00380000U +#define RXTX2__RX1DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00380000U) >> 19) +#define RXTX2__RX1DB_BIQUAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 19) & 0x00380000U) +#define RXTX2__RX1DB_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00380000U) | (((u_int32_t)(src) <<\ + 19) & 0x00380000U) +#define RXTX2__RX1DB_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00380000U))) + +/* macros for field rx6db_biquad */ +#define RXTX2__RX6DB_BIQUAD__SHIFT 22 +#define RXTX2__RX6DB_BIQUAD__WIDTH 2 +#define RXTX2__RX6DB_BIQUAD__MASK 0x00c00000U +#define RXTX2__RX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00c00000U) >> 22) +#define RXTX2__RX6DB_BIQUAD__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00c00000U) +#define RXTX2__RX6DB_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00c00000U) | (((u_int32_t)(src) <<\ + 22) & 0x00c00000U) +#define RXTX2__RX6DB_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00c00000U))) + +/* macros for field mxrgain */ +#define RXTX2__MXRGAIN__SHIFT 24 +#define RXTX2__MXRGAIN__WIDTH 2 +#define RXTX2__MXRGAIN__MASK 0x03000000U +#define RXTX2__MXRGAIN__READ(src) (((u_int32_t)(src) & 0x03000000U) >> 24) +#define RXTX2__MXRGAIN__WRITE(src) (((u_int32_t)(src) << 24) & 0x03000000U) +#define RXTX2__MXRGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03000000U) | (((u_int32_t)(src) <<\ + 24) & 0x03000000U) +#define RXTX2__MXRGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x03000000U))) + +/* macros for field vgagain */ +#define RXTX2__VGAGAIN__SHIFT 26 +#define RXTX2__VGAGAIN__WIDTH 3 +#define RXTX2__VGAGAIN__MASK 0x1c000000U +#define RXTX2__VGAGAIN__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) +#define RXTX2__VGAGAIN__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) +#define RXTX2__VGAGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x1c000000U) +#define RXTX2__VGAGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x1c000000U))) + +/* macros for field lnagain */ +#define RXTX2__LNAGAIN__SHIFT 29 +#define RXTX2__LNAGAIN__WIDTH 3 +#define RXTX2__LNAGAIN__MASK 0xe0000000U +#define RXTX2__LNAGAIN__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define RXTX2__LNAGAIN__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define RXTX2__LNAGAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define RXTX2__LNAGAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define RXTX2__TYPE u_int32_t +#define RXTX2__READ 0xffffffffU +#define RXTX2__WRITE 0xffffffffU + +#endif /* __RXTX2_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_RXTX2 */ +#define INST_RADIO65_REG_MAP__CH0_RXTX2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXTX3 */ +#ifndef __RXTX3_MACRO__ +#define __RXTX3_MACRO__ + +/* macros for field xlnabias_pwd */ +#define RXTX3__XLNABIAS_PWD__SHIFT 0 +#define RXTX3__XLNABIAS_PWD__WIDTH 1 +#define RXTX3__XLNABIAS_PWD__MASK 0x00000001U +#define RXTX3__XLNABIAS_PWD__READ(src) (u_int32_t)(src) & 0x00000001U +#define RXTX3__XLNABIAS_PWD__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define RXTX3__XLNABIAS_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RXTX3__XLNABIAS_PWD__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define RXTX3__XLNABIAS_PWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RXTX3__XLNABIAS_PWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field xlnaon */ +#define RXTX3__XLNAON__SHIFT 1 +#define RXTX3__XLNAON__WIDTH 1 +#define RXTX3__XLNAON__MASK 0x00000002U +#define RXTX3__XLNAON__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define RXTX3__XLNAON__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define RXTX3__XLNAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RXTX3__XLNAON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RXTX3__XLNAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RXTX3__XLNAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field xlnaon_ovr */ +#define RXTX3__XLNAON_OVR__SHIFT 2 +#define RXTX3__XLNAON_OVR__WIDTH 1 +#define RXTX3__XLNAON_OVR__MASK 0x00000004U +#define RXTX3__XLNAON_OVR__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define RXTX3__XLNAON_OVR__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define RXTX3__XLNAON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RXTX3__XLNAON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RXTX3__XLNAON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RXTX3__XLNAON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field dacFullScale */ +#define RXTX3__DACFULLSCALE__SHIFT 3 +#define RXTX3__DACFULLSCALE__WIDTH 1 +#define RXTX3__DACFULLSCALE__MASK 0x00000008U +#define RXTX3__DACFULLSCALE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define RXTX3__DACFULLSCALE__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define RXTX3__DACFULLSCALE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RXTX3__DACFULLSCALE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RXTX3__DACFULLSCALE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RXTX3__DACFULLSCALE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field dacrstb */ +#define RXTX3__DACRSTB__SHIFT 4 +#define RXTX3__DACRSTB__WIDTH 1 +#define RXTX3__DACRSTB__MASK 0x00000010U +#define RXTX3__DACRSTB__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) +#define RXTX3__DACRSTB__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) +#define RXTX3__DACRSTB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RXTX3__DACRSTB__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RXTX3__DACRSTB__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RXTX3__DACRSTB__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field addacloopback */ +#define RXTX3__ADDACLOOPBACK__SHIFT 5 +#define RXTX3__ADDACLOOPBACK__WIDTH 1 +#define RXTX3__ADDACLOOPBACK__MASK 0x00000020U +#define RXTX3__ADDACLOOPBACK__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define RXTX3__ADDACLOOPBACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RXTX3__ADDACLOOPBACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RXTX3__ADDACLOOPBACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RXTX3__ADDACLOOPBACK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RXTX3__ADDACLOOPBACK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field adcshort */ +#define RXTX3__ADCSHORT__SHIFT 6 +#define RXTX3__ADCSHORT__WIDTH 1 +#define RXTX3__ADCSHORT__MASK 0x00000040U +#define RXTX3__ADCSHORT__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define RXTX3__ADCSHORT__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) +#define RXTX3__ADCSHORT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RXTX3__ADCSHORT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RXTX3__ADCSHORT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RXTX3__ADCSHORT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field dacpwd */ +#define RXTX3__DACPWD__SHIFT 7 +#define RXTX3__DACPWD__WIDTH 1 +#define RXTX3__DACPWD__MASK 0x00000080U +#define RXTX3__DACPWD__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define RXTX3__DACPWD__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) +#define RXTX3__DACPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RXTX3__DACPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RXTX3__DACPWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RXTX3__DACPWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field dacpwd_ovr */ +#define RXTX3__DACPWD_OVR__SHIFT 8 +#define RXTX3__DACPWD_OVR__WIDTH 1 +#define RXTX3__DACPWD_OVR__MASK 0x00000100U +#define RXTX3__DACPWD_OVR__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define RXTX3__DACPWD_OVR__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) +#define RXTX3__DACPWD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RXTX3__DACPWD_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RXTX3__DACPWD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RXTX3__DACPWD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field adcpwd */ +#define RXTX3__ADCPWD__SHIFT 9 +#define RXTX3__ADCPWD__WIDTH 1 +#define RXTX3__ADCPWD__MASK 0x00000200U +#define RXTX3__ADCPWD__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define RXTX3__ADCPWD__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) +#define RXTX3__ADCPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define RXTX3__ADCPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define RXTX3__ADCPWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define RXTX3__ADCPWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field adcpwd_ovr */ +#define RXTX3__ADCPWD_OVR__SHIFT 10 +#define RXTX3__ADCPWD_OVR__WIDTH 1 +#define RXTX3__ADCPWD_OVR__MASK 0x00000400U +#define RXTX3__ADCPWD_OVR__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define RXTX3__ADCPWD_OVR__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) +#define RXTX3__ADCPWD_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RXTX3__ADCPWD_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RXTX3__ADCPWD_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RXTX3__ADCPWD_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field agc_caldac */ +#define RXTX3__AGC_CALDAC__SHIFT 11 +#define RXTX3__AGC_CALDAC__WIDTH 6 +#define RXTX3__AGC_CALDAC__MASK 0x0001f800U +#define RXTX3__AGC_CALDAC__READ(src) (((u_int32_t)(src) & 0x0001f800U) >> 11) +#define RXTX3__AGC_CALDAC__WRITE(src) (((u_int32_t)(src) << 11) & 0x0001f800U) +#define RXTX3__AGC_CALDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0001f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0001f800U) +#define RXTX3__AGC_CALDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0001f800U))) + +/* macros for field agc_cal */ +#define RXTX3__AGC_CAL__SHIFT 17 +#define RXTX3__AGC_CAL__WIDTH 1 +#define RXTX3__AGC_CAL__MASK 0x00020000U +#define RXTX3__AGC_CAL__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17) +#define RXTX3__AGC_CAL__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U) +#define RXTX3__AGC_CAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define RXTX3__AGC_CAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define RXTX3__AGC_CAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define RXTX3__AGC_CAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field agc_cal_ovr */ +#define RXTX3__AGC_CAL_OVR__SHIFT 18 +#define RXTX3__AGC_CAL_OVR__WIDTH 1 +#define RXTX3__AGC_CAL_OVR__MASK 0x00040000U +#define RXTX3__AGC_CAL_OVR__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define RXTX3__AGC_CAL_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define RXTX3__AGC_CAL_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define RXTX3__AGC_CAL_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define RXTX3__AGC_CAL_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define RXTX3__AGC_CAL_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field LOforcedon */ +#define RXTX3__LOFORCEDON__SHIFT 19 +#define RXTX3__LOFORCEDON__WIDTH 1 +#define RXTX3__LOFORCEDON__MASK 0x00080000U +#define RXTX3__LOFORCEDON__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) +#define RXTX3__LOFORCEDON__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) +#define RXTX3__LOFORCEDON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define RXTX3__LOFORCEDON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define RXTX3__LOFORCEDON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define RXTX3__LOFORCEDON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field calresidue */ +#define RXTX3__CALRESIDUE__SHIFT 20 +#define RXTX3__CALRESIDUE__WIDTH 1 +#define RXTX3__CALRESIDUE__MASK 0x00100000U +#define RXTX3__CALRESIDUE__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define RXTX3__CALRESIDUE__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) +#define RXTX3__CALRESIDUE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define RXTX3__CALRESIDUE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define RXTX3__CALRESIDUE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define RXTX3__CALRESIDUE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field calresidue_ovr */ +#define RXTX3__CALRESIDUE_OVR__SHIFT 21 +#define RXTX3__CALRESIDUE_OVR__WIDTH 1 +#define RXTX3__CALRESIDUE_OVR__MASK 0x00200000U +#define RXTX3__CALRESIDUE_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define RXTX3__CALRESIDUE_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define RXTX3__CALRESIDUE_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define RXTX3__CALRESIDUE_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define RXTX3__CALRESIDUE_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define RXTX3__CALRESIDUE_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field calfc */ +#define RXTX3__CALFC__SHIFT 22 +#define RXTX3__CALFC__WIDTH 1 +#define RXTX3__CALFC__MASK 0x00400000U +#define RXTX3__CALFC__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22) +#define RXTX3__CALFC__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U) +#define RXTX3__CALFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define RXTX3__CALFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define RXTX3__CALFC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define RXTX3__CALFC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field calfc_ovr */ +#define RXTX3__CALFC_OVR__SHIFT 23 +#define RXTX3__CALFC_OVR__WIDTH 1 +#define RXTX3__CALFC_OVR__MASK 0x00800000U +#define RXTX3__CALFC_OVR__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) +#define RXTX3__CALFC_OVR__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) +#define RXTX3__CALFC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RXTX3__CALFC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RXTX3__CALFC_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RXTX3__CALFC_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field caltx */ +#define RXTX3__CALTX__SHIFT 24 +#define RXTX3__CALTX__WIDTH 1 +#define RXTX3__CALTX__MASK 0x01000000U +#define RXTX3__CALTX__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define RXTX3__CALTX__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U) +#define RXTX3__CALTX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RXTX3__CALTX__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RXTX3__CALTX__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RXTX3__CALTX__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field caltx_ovr */ +#define RXTX3__CALTX_OVR__SHIFT 25 +#define RXTX3__CALTX_OVR__WIDTH 1 +#define RXTX3__CALTX_OVR__MASK 0x02000000U +#define RXTX3__CALTX_OVR__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) +#define RXTX3__CALTX_OVR__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U) +#define RXTX3__CALTX_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RXTX3__CALTX_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RXTX3__CALTX_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RXTX3__CALTX_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field caltxshift */ +#define RXTX3__CALTXSHIFT__SHIFT 26 +#define RXTX3__CALTXSHIFT__WIDTH 1 +#define RXTX3__CALTXSHIFT__MASK 0x04000000U +#define RXTX3__CALTXSHIFT__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) +#define RXTX3__CALTXSHIFT__WRITE(src) (((u_int32_t)(src) << 26) & 0x04000000U) +#define RXTX3__CALTXSHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RXTX3__CALTXSHIFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RXTX3__CALTXSHIFT__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RXTX3__CALTXSHIFT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field caltxshift_ovr */ +#define RXTX3__CALTXSHIFT_OVR__SHIFT 27 +#define RXTX3__CALTXSHIFT_OVR__WIDTH 1 +#define RXTX3__CALTXSHIFT_OVR__MASK 0x08000000U +#define RXTX3__CALTXSHIFT_OVR__READ(src) \ + (((u_int32_t)(src)\ + & 0x08000000U) >> 27) +#define RXTX3__CALTXSHIFT_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RXTX3__CALTXSHIFT_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RXTX3__CALTXSHIFT_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RXTX3__CALTXSHIFT_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RXTX3__CALTXSHIFT_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field calpa */ +#define RXTX3__CALPA__SHIFT 28 +#define RXTX3__CALPA__WIDTH 1 +#define RXTX3__CALPA__MASK 0x10000000U +#define RXTX3__CALPA__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define RXTX3__CALPA__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define RXTX3__CALPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RXTX3__CALPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RXTX3__CALPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RXTX3__CALPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field calpa_ovr */ +#define RXTX3__CALPA_OVR__SHIFT 29 +#define RXTX3__CALPA_OVR__WIDTH 1 +#define RXTX3__CALPA_OVR__MASK 0x20000000U +#define RXTX3__CALPA_OVR__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define RXTX3__CALPA_OVR__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define RXTX3__CALPA_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RXTX3__CALPA_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RXTX3__CALPA_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RXTX3__CALPA_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field spuron */ +#define RXTX3__SPURON__SHIFT 30 +#define RXTX3__SPURON__WIDTH 1 +#define RXTX3__SPURON__MASK 0x40000000U +#define RXTX3__SPURON__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define RXTX3__SPURON__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define RXTX3__SPURON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define RXTX3__SPURON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define RXTX3__SPURON__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define RXTX3__SPURON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field PAL_lockedEn */ +#define RXTX3__PAL_LOCKEDEN__SHIFT 31 +#define RXTX3__PAL_LOCKEDEN__WIDTH 1 +#define RXTX3__PAL_LOCKEDEN__MASK 0x80000000U +#define RXTX3__PAL_LOCKEDEN__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define RXTX3__PAL_LOCKEDEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define RXTX3__PAL_LOCKEDEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define RXTX3__PAL_LOCKEDEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define RXTX3__PAL_LOCKEDEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define RXTX3__PAL_LOCKEDEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define RXTX3__TYPE u_int32_t +#define RXTX3__READ 0xffffffffU +#define RXTX3__WRITE 0xffffffffU + +#endif /* __RXTX3_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_RXTX3 */ +#define INST_RADIO65_REG_MAP__CH0_RXTX3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::RXTX4 */ +#ifndef __RXTX4_MACRO__ +#define __RXTX4_MACRO__ + +/* macros for field SPARE4 */ +#define RXTX4__SPARE4__SHIFT 0 +#define RXTX4__SPARE4__WIDTH 21 +#define RXTX4__SPARE4__MASK 0x001fffffU +#define RXTX4__SPARE4__READ(src) (u_int32_t)(src) & 0x001fffffU +#define RXTX4__SPARE4__WRITE(src) ((u_int32_t)(src) & 0x001fffffU) +#define RXTX4__SPARE4__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001fffffU) | ((u_int32_t)(src) &\ + 0x001fffffU) +#define RXTX4__SPARE4__VERIFY(src) (!(((u_int32_t)(src) & ~0x001fffffU))) + +/* macros for field obdb2G_ssctrl */ +#define RXTX4__OBDB2G_SSCTRL__SHIFT 21 +#define RXTX4__OBDB2G_SSCTRL__WIDTH 1 +#define RXTX4__OBDB2G_SSCTRL__MASK 0x00200000U +#define RXTX4__OBDB2G_SSCTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00200000U) >> 21) +#define RXTX4__OBDB2G_SSCTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 21) & 0x00200000U) +#define RXTX4__OBDB2G_SSCTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define RXTX4__OBDB2G_SSCTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define RXTX4__OBDB2G_SSCTRL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define RXTX4__OBDB2G_SSCTRL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field obdb5G_ssctrl */ +#define RXTX4__OBDB5G_SSCTRL__SHIFT 22 +#define RXTX4__OBDB5G_SSCTRL__WIDTH 1 +#define RXTX4__OBDB5G_SSCTRL__MASK 0x00400000U +#define RXTX4__OBDB5G_SSCTRL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00400000U) >> 22) +#define RXTX4__OBDB5G_SSCTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 22) & 0x00400000U) +#define RXTX4__OBDB5G_SSCTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define RXTX4__OBDB5G_SSCTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define RXTX4__OBDB5G_SSCTRL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define RXTX4__OBDB5G_SSCTRL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field testiq_on */ +#define RXTX4__TESTIQ_ON__SHIFT 23 +#define RXTX4__TESTIQ_ON__WIDTH 1 +#define RXTX4__TESTIQ_ON__MASK 0x00800000U +#define RXTX4__TESTIQ_ON__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) +#define RXTX4__TESTIQ_ON__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) +#define RXTX4__TESTIQ_ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define RXTX4__TESTIQ_ON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define RXTX4__TESTIQ_ON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define RXTX4__TESTIQ_ON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field testiq_bufen */ +#define RXTX4__TESTIQ_BUFEN__SHIFT 24 +#define RXTX4__TESTIQ_BUFEN__WIDTH 1 +#define RXTX4__TESTIQ_BUFEN__MASK 0x01000000U +#define RXTX4__TESTIQ_BUFEN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define RXTX4__TESTIQ_BUFEN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define RXTX4__TESTIQ_BUFEN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define RXTX4__TESTIQ_BUFEN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define RXTX4__TESTIQ_BUFEN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define RXTX4__TESTIQ_BUFEN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field testiq_rsel */ +#define RXTX4__TESTIQ_RSEL__SHIFT 25 +#define RXTX4__TESTIQ_RSEL__WIDTH 1 +#define RXTX4__TESTIQ_RSEL__MASK 0x02000000U +#define RXTX4__TESTIQ_RSEL__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) +#define RXTX4__TESTIQ_RSEL__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U) +#define RXTX4__TESTIQ_RSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define RXTX4__TESTIQ_RSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define RXTX4__TESTIQ_RSEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define RXTX4__TESTIQ_RSEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field turboADC */ +#define RXTX4__TURBOADC__SHIFT 26 +#define RXTX4__TURBOADC__WIDTH 1 +#define RXTX4__TURBOADC__MASK 0x04000000U +#define RXTX4__TURBOADC__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) +#define RXTX4__TURBOADC__WRITE(src) (((u_int32_t)(src) << 26) & 0x04000000U) +#define RXTX4__TURBOADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define RXTX4__TURBOADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define RXTX4__TURBOADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define RXTX4__TURBOADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field turboADC_ovr */ +#define RXTX4__TURBOADC_OVR__SHIFT 27 +#define RXTX4__TURBOADC_OVR__WIDTH 1 +#define RXTX4__TURBOADC_OVR__MASK 0x08000000U +#define RXTX4__TURBOADC_OVR__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) +#define RXTX4__TURBOADC_OVR__WRITE(src) \ + (((u_int32_t)(src)\ + << 27) & 0x08000000U) +#define RXTX4__TURBOADC_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define RXTX4__TURBOADC_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define RXTX4__TURBOADC_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define RXTX4__TURBOADC_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field thermOn */ +#define RXTX4__THERMON__SHIFT 28 +#define RXTX4__THERMON__WIDTH 1 +#define RXTX4__THERMON__MASK 0x10000000U +#define RXTX4__THERMON__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define RXTX4__THERMON__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define RXTX4__THERMON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define RXTX4__THERMON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define RXTX4__THERMON__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define RXTX4__THERMON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field thermOn_ovr */ +#define RXTX4__THERMON_OVR__SHIFT 29 +#define RXTX4__THERMON_OVR__WIDTH 1 +#define RXTX4__THERMON_OVR__MASK 0x20000000U +#define RXTX4__THERMON_OVR__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define RXTX4__THERMON_OVR__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define RXTX4__THERMON_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define RXTX4__THERMON_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define RXTX4__THERMON_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define RXTX4__THERMON_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field xlna_strength */ +#define RXTX4__XLNA_STRENGTH__SHIFT 30 +#define RXTX4__XLNA_STRENGTH__WIDTH 2 +#define RXTX4__XLNA_STRENGTH__MASK 0xc0000000U +#define RXTX4__XLNA_STRENGTH__READ(src) \ + (((u_int32_t)(src)\ + & 0xc0000000U) >> 30) +#define RXTX4__XLNA_STRENGTH__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0xc0000000U) +#define RXTX4__XLNA_STRENGTH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define RXTX4__XLNA_STRENGTH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define RXTX4__TYPE u_int32_t +#define RXTX4__READ 0xffffffffU +#define RXTX4__WRITE 0xffffffffU + +#endif /* __RXTX4_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_RXTX4 */ +#define INST_RADIO65_REG_MAP__CH0_RXTX4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BB1 */ +#ifndef __BB1_MACRO__ +#define __BB1_MACRO__ + +/* macros for field I2V_CURR2X */ +#define BB1__I2V_CURR2X__SHIFT 0 +#define BB1__I2V_CURR2X__WIDTH 1 +#define BB1__I2V_CURR2X__MASK 0x00000001U +#define BB1__I2V_CURR2X__READ(src) (u_int32_t)(src) & 0x00000001U +#define BB1__I2V_CURR2X__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define BB1__I2V_CURR2X__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define BB1__I2V_CURR2X__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define BB1__I2V_CURR2X__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define BB1__I2V_CURR2X__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ENABLE_LOQ */ +#define BB1__ENABLE_LOQ__SHIFT 1 +#define BB1__ENABLE_LOQ__WIDTH 1 +#define BB1__ENABLE_LOQ__MASK 0x00000002U +#define BB1__ENABLE_LOQ__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define BB1__ENABLE_LOQ__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define BB1__ENABLE_LOQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define BB1__ENABLE_LOQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define BB1__ENABLE_LOQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define BB1__ENABLE_LOQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field FORCE_LOQ */ +#define BB1__FORCE_LOQ__SHIFT 2 +#define BB1__FORCE_LOQ__WIDTH 1 +#define BB1__FORCE_LOQ__MASK 0x00000004U +#define BB1__FORCE_LOQ__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define BB1__FORCE_LOQ__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define BB1__FORCE_LOQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define BB1__FORCE_LOQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define BB1__FORCE_LOQ__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define BB1__FORCE_LOQ__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field ENABLE_NOTCH */ +#define BB1__ENABLE_NOTCH__SHIFT 3 +#define BB1__ENABLE_NOTCH__WIDTH 1 +#define BB1__ENABLE_NOTCH__MASK 0x00000008U +#define BB1__ENABLE_NOTCH__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define BB1__ENABLE_NOTCH__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define BB1__ENABLE_NOTCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define BB1__ENABLE_NOTCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define BB1__ENABLE_NOTCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define BB1__ENABLE_NOTCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field FORCE_NOTCH */ +#define BB1__FORCE_NOTCH__SHIFT 4 +#define BB1__FORCE_NOTCH__WIDTH 1 +#define BB1__FORCE_NOTCH__MASK 0x00000010U +#define BB1__FORCE_NOTCH__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) +#define BB1__FORCE_NOTCH__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) +#define BB1__FORCE_NOTCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define BB1__FORCE_NOTCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define BB1__FORCE_NOTCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define BB1__FORCE_NOTCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field ENABLE_BIQUAD */ +#define BB1__ENABLE_BIQUAD__SHIFT 5 +#define BB1__ENABLE_BIQUAD__WIDTH 1 +#define BB1__ENABLE_BIQUAD__MASK 0x00000020U +#define BB1__ENABLE_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define BB1__ENABLE_BIQUAD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) +#define BB1__ENABLE_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define BB1__ENABLE_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define BB1__ENABLE_BIQUAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define BB1__ENABLE_BIQUAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field FORCE_BIQUAD */ +#define BB1__FORCE_BIQUAD__SHIFT 6 +#define BB1__FORCE_BIQUAD__WIDTH 1 +#define BB1__FORCE_BIQUAD__MASK 0x00000040U +#define BB1__FORCE_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define BB1__FORCE_BIQUAD__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) +#define BB1__FORCE_BIQUAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define BB1__FORCE_BIQUAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define BB1__FORCE_BIQUAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define BB1__FORCE_BIQUAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field ENABLE_OSDAC */ +#define BB1__ENABLE_OSDAC__SHIFT 7 +#define BB1__ENABLE_OSDAC__WIDTH 1 +#define BB1__ENABLE_OSDAC__MASK 0x00000080U +#define BB1__ENABLE_OSDAC__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define BB1__ENABLE_OSDAC__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) +#define BB1__ENABLE_OSDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define BB1__ENABLE_OSDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define BB1__ENABLE_OSDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define BB1__ENABLE_OSDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field FORCE_OSDAC */ +#define BB1__FORCE_OSDAC__SHIFT 8 +#define BB1__FORCE_OSDAC__WIDTH 1 +#define BB1__FORCE_OSDAC__MASK 0x00000100U +#define BB1__FORCE_OSDAC__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define BB1__FORCE_OSDAC__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) +#define BB1__FORCE_OSDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define BB1__FORCE_OSDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define BB1__FORCE_OSDAC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define BB1__FORCE_OSDAC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field ENABLE_V2I */ +#define BB1__ENABLE_V2I__SHIFT 9 +#define BB1__ENABLE_V2I__WIDTH 1 +#define BB1__ENABLE_V2I__MASK 0x00000200U +#define BB1__ENABLE_V2I__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define BB1__ENABLE_V2I__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) +#define BB1__ENABLE_V2I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define BB1__ENABLE_V2I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define BB1__ENABLE_V2I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define BB1__ENABLE_V2I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field FORCE_V2I */ +#define BB1__FORCE_V2I__SHIFT 10 +#define BB1__FORCE_V2I__WIDTH 1 +#define BB1__FORCE_V2I__MASK 0x00000400U +#define BB1__FORCE_V2I__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define BB1__FORCE_V2I__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) +#define BB1__FORCE_V2I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define BB1__FORCE_V2I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define BB1__FORCE_V2I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define BB1__FORCE_V2I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field ENABLE_I2V */ +#define BB1__ENABLE_I2V__SHIFT 11 +#define BB1__ENABLE_I2V__WIDTH 1 +#define BB1__ENABLE_I2V__MASK 0x00000800U +#define BB1__ENABLE_I2V__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define BB1__ENABLE_I2V__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define BB1__ENABLE_I2V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define BB1__ENABLE_I2V__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define BB1__ENABLE_I2V__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define BB1__ENABLE_I2V__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field FORCE_I2V */ +#define BB1__FORCE_I2V__SHIFT 12 +#define BB1__FORCE_I2V__WIDTH 1 +#define BB1__FORCE_I2V__MASK 0x00001000U +#define BB1__FORCE_I2V__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) +#define BB1__FORCE_I2V__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) +#define BB1__FORCE_I2V__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define BB1__FORCE_I2V__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define BB1__FORCE_I2V__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define BB1__FORCE_I2V__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field CMSEL */ +#define BB1__CMSEL__SHIFT 13 +#define BB1__CMSEL__WIDTH 3 +#define BB1__CMSEL__MASK 0x0000e000U +#define BB1__CMSEL__READ(src) (((u_int32_t)(src) & 0x0000e000U) >> 13) +#define BB1__CMSEL__WRITE(src) (((u_int32_t)(src) << 13) & 0x0000e000U) +#define BB1__CMSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define BB1__CMSEL__VERIFY(src) (!((((u_int32_t)(src) << 13) & ~0x0000e000U))) + +/* macros for field ATBSEL */ +#define BB1__ATBSEL__SHIFT 16 +#define BB1__ATBSEL__WIDTH 2 +#define BB1__ATBSEL__MASK 0x00030000U +#define BB1__ATBSEL__READ(src) (((u_int32_t)(src) & 0x00030000U) >> 16) +#define BB1__ATBSEL__WRITE(src) (((u_int32_t)(src) << 16) & 0x00030000U) +#define BB1__ATBSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00030000U) | (((u_int32_t)(src) <<\ + 16) & 0x00030000U) +#define BB1__ATBSEL__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x00030000U))) + +/* macros for field PD_OSDAC_CALTX_CALPA */ +#define BB1__PD_OSDAC_CALTX_CALPA__SHIFT 18 +#define BB1__PD_OSDAC_CALTX_CALPA__WIDTH 1 +#define BB1__PD_OSDAC_CALTX_CALPA__MASK 0x00040000U +#define BB1__PD_OSDAC_CALTX_CALPA__READ(src) \ + (((u_int32_t)(src)\ + & 0x00040000U) >> 18) +#define BB1__PD_OSDAC_CALTX_CALPA__WRITE(src) \ + (((u_int32_t)(src)\ + << 18) & 0x00040000U) +#define BB1__PD_OSDAC_CALTX_CALPA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define BB1__PD_OSDAC_CALTX_CALPA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define BB1__PD_OSDAC_CALTX_CALPA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define BB1__PD_OSDAC_CALTX_CALPA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field OFSTCORRI2VQ */ +#define BB1__OFSTCORRI2VQ__SHIFT 19 +#define BB1__OFSTCORRI2VQ__WIDTH 5 +#define BB1__OFSTCORRI2VQ__MASK 0x00f80000U +#define BB1__OFSTCORRI2VQ__READ(src) (((u_int32_t)(src) & 0x00f80000U) >> 19) +#define BB1__OFSTCORRI2VQ__WRITE(src) (((u_int32_t)(src) << 19) & 0x00f80000U) +#define BB1__OFSTCORRI2VQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00f80000U) | (((u_int32_t)(src) <<\ + 19) & 0x00f80000U) +#define BB1__OFSTCORRI2VQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00f80000U))) + +/* macros for field OFSTCORRI2VI */ +#define BB1__OFSTCORRI2VI__SHIFT 24 +#define BB1__OFSTCORRI2VI__WIDTH 5 +#define BB1__OFSTCORRI2VI__MASK 0x1f000000U +#define BB1__OFSTCORRI2VI__READ(src) (((u_int32_t)(src) & 0x1f000000U) >> 24) +#define BB1__OFSTCORRI2VI__WRITE(src) (((u_int32_t)(src) << 24) & 0x1f000000U) +#define BB1__OFSTCORRI2VI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x1f000000U) +#define BB1__OFSTCORRI2VI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x1f000000U))) + +/* macros for field LOCALOFFSET */ +#define BB1__LOCALOFFSET__SHIFT 29 +#define BB1__LOCALOFFSET__WIDTH 1 +#define BB1__LOCALOFFSET__MASK 0x20000000U +#define BB1__LOCALOFFSET__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define BB1__LOCALOFFSET__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define BB1__LOCALOFFSET__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define BB1__LOCALOFFSET__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define BB1__LOCALOFFSET__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define BB1__LOCALOFFSET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field RANGE_OSDAC */ +#define BB1__RANGE_OSDAC__SHIFT 30 +#define BB1__RANGE_OSDAC__WIDTH 2 +#define BB1__RANGE_OSDAC__MASK 0xc0000000U +#define BB1__RANGE_OSDAC__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) +#define BB1__RANGE_OSDAC__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U) +#define BB1__RANGE_OSDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define BB1__RANGE_OSDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define BB1__TYPE u_int32_t +#define BB1__READ 0xffffffffU +#define BB1__WRITE 0xffffffffU + +#endif /* __BB1_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_BB1 */ +#define INST_RADIO65_REG_MAP__CH0_BB1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BB2 */ +#ifndef __BB2_MACRO__ +#define __BB2_MACRO__ + +/* macros for field SPARE */ +#define BB2__SPARE__SHIFT 0 +#define BB2__SPARE__WIDTH 4 +#define BB2__SPARE__MASK 0x0000000fU +#define BB2__SPARE__READ(src) (u_int32_t)(src) & 0x0000000fU +#define BB2__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define BB2__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define BB2__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) + +/* macros for field MXR_HIGHGAINMASK */ +#define BB2__MXR_HIGHGAINMASK__SHIFT 4 +#define BB2__MXR_HIGHGAINMASK__WIDTH 4 +#define BB2__MXR_HIGHGAINMASK__MASK 0x000000f0U +#define BB2__MXR_HIGHGAINMASK__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define BB2__MXR_HIGHGAINMASK__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define BB2__MXR_HIGHGAINMASK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define BB2__MXR_HIGHGAINMASK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) + +/* macros for field SEL_TEST */ +#define BB2__SEL_TEST__SHIFT 8 +#define BB2__SEL_TEST__WIDTH 2 +#define BB2__SEL_TEST__MASK 0x00000300U +#define BB2__SEL_TEST__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8) +#define BB2__SEL_TEST__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000300U) +#define BB2__SEL_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define BB2__SEL_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field RCFILTER_CAP */ +#define BB2__RCFILTER_CAP__SHIFT 10 +#define BB2__RCFILTER_CAP__WIDTH 5 +#define BB2__RCFILTER_CAP__MASK 0x00007c00U +#define BB2__RCFILTER_CAP__READ(src) (((u_int32_t)(src) & 0x00007c00U) >> 10) +#define BB2__RCFILTER_CAP__WRITE(src) (((u_int32_t)(src) << 10) & 0x00007c00U) +#define BB2__RCFILTER_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007c00U) | (((u_int32_t)(src) <<\ + 10) & 0x00007c00U) +#define BB2__RCFILTER_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00007c00U))) + +/* macros for field OVERRIDE_RCFILTER_CAP */ +#define BB2__OVERRIDE_RCFILTER_CAP__SHIFT 15 +#define BB2__OVERRIDE_RCFILTER_CAP__WIDTH 1 +#define BB2__OVERRIDE_RCFILTER_CAP__MASK 0x00008000U +#define BB2__OVERRIDE_RCFILTER_CAP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define BB2__OVERRIDE_RCFILTER_CAP__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define BB2__OVERRIDE_RCFILTER_CAP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define BB2__OVERRIDE_RCFILTER_CAP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define BB2__OVERRIDE_RCFILTER_CAP__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define BB2__OVERRIDE_RCFILTER_CAP__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field FNOTCH */ +#define BB2__FNOTCH__SHIFT 16 +#define BB2__FNOTCH__WIDTH 4 +#define BB2__FNOTCH__MASK 0x000f0000U +#define BB2__FNOTCH__READ(src) (((u_int32_t)(src) & 0x000f0000U) >> 16) +#define BB2__FNOTCH__WRITE(src) (((u_int32_t)(src) << 16) & 0x000f0000U) +#define BB2__FNOTCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define BB2__FNOTCH__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x000f0000U))) + +/* macros for field OVERRIDE_FNOTCH */ +#define BB2__OVERRIDE_FNOTCH__SHIFT 20 +#define BB2__OVERRIDE_FNOTCH__WIDTH 1 +#define BB2__OVERRIDE_FNOTCH__MASK 0x00100000U +#define BB2__OVERRIDE_FNOTCH__READ(src) \ + (((u_int32_t)(src)\ + & 0x00100000U) >> 20) +#define BB2__OVERRIDE_FNOTCH__WRITE(src) \ + (((u_int32_t)(src)\ + << 20) & 0x00100000U) +#define BB2__OVERRIDE_FNOTCH__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define BB2__OVERRIDE_FNOTCH__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define BB2__OVERRIDE_FNOTCH__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define BB2__OVERRIDE_FNOTCH__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field FILTERFC */ +#define BB2__FILTERFC__SHIFT 21 +#define BB2__FILTERFC__WIDTH 5 +#define BB2__FILTERFC__MASK 0x03e00000U +#define BB2__FILTERFC__READ(src) (((u_int32_t)(src) & 0x03e00000U) >> 21) +#define BB2__FILTERFC__WRITE(src) (((u_int32_t)(src) << 21) & 0x03e00000U) +#define BB2__FILTERFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x03e00000U) +#define BB2__FILTERFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x03e00000U))) + +/* macros for field OVERRIDE_FILTERFC */ +#define BB2__OVERRIDE_FILTERFC__SHIFT 26 +#define BB2__OVERRIDE_FILTERFC__WIDTH 1 +#define BB2__OVERRIDE_FILTERFC__MASK 0x04000000U +#define BB2__OVERRIDE_FILTERFC__READ(src) \ + (((u_int32_t)(src)\ + & 0x04000000U) >> 26) +#define BB2__OVERRIDE_FILTERFC__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define BB2__OVERRIDE_FILTERFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define BB2__OVERRIDE_FILTERFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define BB2__OVERRIDE_FILTERFC__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define BB2__OVERRIDE_FILTERFC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field I2V2RXOUT_EN */ +#define BB2__I2V2RXOUT_EN__SHIFT 27 +#define BB2__I2V2RXOUT_EN__WIDTH 1 +#define BB2__I2V2RXOUT_EN__MASK 0x08000000U +#define BB2__I2V2RXOUT_EN__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) +#define BB2__I2V2RXOUT_EN__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U) +#define BB2__I2V2RXOUT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define BB2__I2V2RXOUT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define BB2__I2V2RXOUT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define BB2__I2V2RXOUT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field BQ2RXOUT_EN */ +#define BB2__BQ2RXOUT_EN__SHIFT 28 +#define BB2__BQ2RXOUT_EN__WIDTH 1 +#define BB2__BQ2RXOUT_EN__MASK 0x10000000U +#define BB2__BQ2RXOUT_EN__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define BB2__BQ2RXOUT_EN__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define BB2__BQ2RXOUT_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define BB2__BQ2RXOUT_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define BB2__BQ2RXOUT_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define BB2__BQ2RXOUT_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field RXIN2I2V_EN */ +#define BB2__RXIN2I2V_EN__SHIFT 29 +#define BB2__RXIN2I2V_EN__WIDTH 1 +#define BB2__RXIN2I2V_EN__MASK 0x20000000U +#define BB2__RXIN2I2V_EN__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define BB2__RXIN2I2V_EN__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define BB2__RXIN2I2V_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define BB2__RXIN2I2V_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define BB2__RXIN2I2V_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define BB2__RXIN2I2V_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field RXIN2BQ_EN */ +#define BB2__RXIN2BQ_EN__SHIFT 30 +#define BB2__RXIN2BQ_EN__WIDTH 1 +#define BB2__RXIN2BQ_EN__MASK 0x40000000U +#define BB2__RXIN2BQ_EN__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define BB2__RXIN2BQ_EN__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define BB2__RXIN2BQ_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define BB2__RXIN2BQ_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define BB2__RXIN2BQ_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define BB2__RXIN2BQ_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field SWITCH_OVERRIDE */ +#define BB2__SWITCH_OVERRIDE__SHIFT 31 +#define BB2__SWITCH_OVERRIDE__WIDTH 1 +#define BB2__SWITCH_OVERRIDE__MASK 0x80000000U +#define BB2__SWITCH_OVERRIDE__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define BB2__SWITCH_OVERRIDE__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define BB2__SWITCH_OVERRIDE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define BB2__SWITCH_OVERRIDE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define BB2__SWITCH_OVERRIDE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define BB2__SWITCH_OVERRIDE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define BB2__TYPE u_int32_t +#define BB2__READ 0xffffffffU +#define BB2__WRITE 0xffffffffU + +#endif /* __BB2_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_BB2 */ +#define INST_RADIO65_REG_MAP__CH0_BB2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::BB3 */ +#ifndef __BB3_MACRO__ +#define __BB3_MACRO__ + +/* macros for field SPARE */ +#define BB3__SPARE__SHIFT 0 +#define BB3__SPARE__WIDTH 8 +#define BB3__SPARE__MASK 0x000000ffU +#define BB3__SPARE__READ(src) (u_int32_t)(src) & 0x000000ffU +#define BB3__SPARE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) +#define BB3__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000ffU) | ((u_int32_t)(src) &\ + 0x000000ffU) +#define BB3__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) + +/* macros for field SEL_OFST_READBK */ +#define BB3__SEL_OFST_READBK__SHIFT 8 +#define BB3__SEL_OFST_READBK__WIDTH 2 +#define BB3__SEL_OFST_READBK__MASK 0x00000300U +#define BB3__SEL_OFST_READBK__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8) +#define BB3__SEL_OFST_READBK__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000300U) +#define BB3__SEL_OFST_READBK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000300U) | (((u_int32_t)(src) <<\ + 8) & 0x00000300U) +#define BB3__SEL_OFST_READBK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000300U))) + +/* macros for field OVERRIDE_RXONLY_FILTERFC */ +#define BB3__OVERRIDE_RXONLY_FILTERFC__SHIFT 10 +#define BB3__OVERRIDE_RXONLY_FILTERFC__WIDTH 1 +#define BB3__OVERRIDE_RXONLY_FILTERFC__MASK 0x00000400U +#define BB3__OVERRIDE_RXONLY_FILTERFC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define BB3__OVERRIDE_RXONLY_FILTERFC__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define BB3__OVERRIDE_RXONLY_FILTERFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define BB3__OVERRIDE_RXONLY_FILTERFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define BB3__OVERRIDE_RXONLY_FILTERFC__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define BB3__OVERRIDE_RXONLY_FILTERFC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field RXONLY_FILTERFC */ +#define BB3__RXONLY_FILTERFC__SHIFT 11 +#define BB3__RXONLY_FILTERFC__WIDTH 5 +#define BB3__RXONLY_FILTERFC__MASK 0x0000f800U +#define BB3__RXONLY_FILTERFC__READ(src) \ + (((u_int32_t)(src)\ + & 0x0000f800U) >> 11) +#define BB3__RXONLY_FILTERFC__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x0000f800U) +#define BB3__RXONLY_FILTERFC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000f800U) | (((u_int32_t)(src) <<\ + 11) & 0x0000f800U) +#define BB3__RXONLY_FILTERFC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x0000f800U))) + +/* macros for field FILTERFC */ +#define BB3__FILTERFC__SHIFT 16 +#define BB3__FILTERFC__WIDTH 5 +#define BB3__FILTERFC__MASK 0x001f0000U +#define BB3__FILTERFC__READ(src) (((u_int32_t)(src) & 0x001f0000U) >> 16) + +/* macros for field OFSTCORRI2VQ */ +#define BB3__OFSTCORRI2VQ__SHIFT 21 +#define BB3__OFSTCORRI2VQ__WIDTH 5 +#define BB3__OFSTCORRI2VQ__MASK 0x03e00000U +#define BB3__OFSTCORRI2VQ__READ(src) (((u_int32_t)(src) & 0x03e00000U) >> 21) + +/* macros for field OFSTCORRI2VI */ +#define BB3__OFSTCORRI2VI__SHIFT 26 +#define BB3__OFSTCORRI2VI__WIDTH 5 +#define BB3__OFSTCORRI2VI__MASK 0x7c000000U +#define BB3__OFSTCORRI2VI__READ(src) (((u_int32_t)(src) & 0x7c000000U) >> 26) + +/* macros for field EN_TXBBCONSTCUR */ +#define BB3__EN_TXBBCONSTCUR__SHIFT 31 +#define BB3__EN_TXBBCONSTCUR__WIDTH 1 +#define BB3__EN_TXBBCONSTCUR__MASK 0x80000000U +#define BB3__EN_TXBBCONSTCUR__READ(src) \ + (((u_int32_t)(src)\ + & 0x80000000U) >> 31) +#define BB3__EN_TXBBCONSTCUR__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define BB3__EN_TXBBCONSTCUR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define BB3__EN_TXBBCONSTCUR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define BB3__EN_TXBBCONSTCUR__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define BB3__EN_TXBBCONSTCUR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define BB3__TYPE u_int32_t +#define BB3__READ 0xffffffffU +#define BB3__WRITE 0xffffffffU + +#endif /* __BB3_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_BB3 */ +#define INST_RADIO65_REG_MAP__CH0_BB3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DPLL */ +#ifndef __DPLL_MACRO__ +#define __DPLL_MACRO__ + +/* macros for field nfrac */ +#define DPLL__NFRAC__SHIFT 0 +#define DPLL__NFRAC__WIDTH 18 +#define DPLL__NFRAC__MASK 0x0003ffffU +#define DPLL__NFRAC__READ(src) (u_int32_t)(src) & 0x0003ffffU +#define DPLL__NFRAC__WRITE(src) ((u_int32_t)(src) & 0x0003ffffU) +#define DPLL__NFRAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0003ffffU) | ((u_int32_t)(src) &\ + 0x0003ffffU) +#define DPLL__NFRAC__VERIFY(src) (!(((u_int32_t)(src) & ~0x0003ffffU))) + +/* macros for field nint */ +#define DPLL__NINT__SHIFT 18 +#define DPLL__NINT__WIDTH 9 +#define DPLL__NINT__MASK 0x07fc0000U +#define DPLL__NINT__READ(src) (((u_int32_t)(src) & 0x07fc0000U) >> 18) +#define DPLL__NINT__WRITE(src) (((u_int32_t)(src) << 18) & 0x07fc0000U) +#define DPLL__NINT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07fc0000U) | (((u_int32_t)(src) <<\ + 18) & 0x07fc0000U) +#define DPLL__NINT__VERIFY(src) (!((((u_int32_t)(src) << 18) & ~0x07fc0000U))) + +/* macros for field refdiv */ +#define DPLL__REFDIV__SHIFT 27 +#define DPLL__REFDIV__WIDTH 5 +#define DPLL__REFDIV__MASK 0xf8000000U +#define DPLL__REFDIV__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) +#define DPLL__REFDIV__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) +#define DPLL__REFDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xf8000000U) | (((u_int32_t)(src) <<\ + 27) & 0xf8000000U) +#define DPLL__REFDIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0xf8000000U))) +#define DPLL__TYPE u_int32_t +#define DPLL__READ 0xffffffffU +#define DPLL__WRITE 0xffffffffU + +#endif /* __DPLL_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_BB_PLL */ +#define INST_RADIO65_REG_MAP__CH0_BB_PLL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DPLL2 */ +#ifndef __DPLL2_MACRO__ +#define __DPLL2_MACRO__ + +/* macros for field testinMSB */ +#define DPLL2__TESTINMSB__SHIFT 0 +#define DPLL2__TESTINMSB__WIDTH 7 +#define DPLL2__TESTINMSB__MASK 0x0000007fU +#define DPLL2__TESTINMSB__READ(src) (u_int32_t)(src) & 0x0000007fU +#define DPLL2__TESTINMSB__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) +#define DPLL2__TESTINMSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define DPLL2__TESTINMSB__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU))) + +/* macros for field delta */ +#define DPLL2__DELTA__SHIFT 7 +#define DPLL2__DELTA__WIDTH 6 +#define DPLL2__DELTA__MASK 0x00001f80U +#define DPLL2__DELTA__READ(src) (((u_int32_t)(src) & 0x00001f80U) >> 7) +#define DPLL2__DELTA__WRITE(src) (((u_int32_t)(src) << 7) & 0x00001f80U) +#define DPLL2__DELTA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f80U) | (((u_int32_t)(src) <<\ + 7) & 0x00001f80U) +#define DPLL2__DELTA__VERIFY(src) (!((((u_int32_t)(src) << 7) & ~0x00001f80U))) + +/* macros for field outdiv */ +#define DPLL2__OUTDIV__SHIFT 13 +#define DPLL2__OUTDIV__WIDTH 3 +#define DPLL2__OUTDIV__MASK 0x0000e000U +#define DPLL2__OUTDIV__READ(src) (((u_int32_t)(src) & 0x0000e000U) >> 13) +#define DPLL2__OUTDIV__WRITE(src) (((u_int32_t)(src) << 13) & 0x0000e000U) +#define DPLL2__OUTDIV__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000e000U) | (((u_int32_t)(src) <<\ + 13) & 0x0000e000U) +#define DPLL2__OUTDIV__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x0000e000U))) + +/* macros for field pll_pwd */ +#define DPLL2__PLL_PWD__SHIFT 16 +#define DPLL2__PLL_PWD__WIDTH 1 +#define DPLL2__PLL_PWD__MASK 0x00010000U +#define DPLL2__PLL_PWD__READ(src) (((u_int32_t)(src) & 0x00010000U) >> 16) +#define DPLL2__PLL_PWD__WRITE(src) (((u_int32_t)(src) << 16) & 0x00010000U) +#define DPLL2__PLL_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define DPLL2__PLL_PWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define DPLL2__PLL_PWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define DPLL2__PLL_PWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) + +/* macros for field sel_1sdm */ +#define DPLL2__SEL_1SDM__SHIFT 17 +#define DPLL2__SEL_1SDM__WIDTH 1 +#define DPLL2__SEL_1SDM__MASK 0x00020000U +#define DPLL2__SEL_1SDM__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17) +#define DPLL2__SEL_1SDM__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U) +#define DPLL2__SEL_1SDM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00020000U) | (((u_int32_t)(src) <<\ + 17) & 0x00020000U) +#define DPLL2__SEL_1SDM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00020000U))) +#define DPLL2__SEL_1SDM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(1) << 17) +#define DPLL2__SEL_1SDM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00020000U) | ((u_int32_t)(0) << 17) + +/* macros for field en_negtrig */ +#define DPLL2__EN_NEGTRIG__SHIFT 18 +#define DPLL2__EN_NEGTRIG__WIDTH 1 +#define DPLL2__EN_NEGTRIG__MASK 0x00040000U +#define DPLL2__EN_NEGTRIG__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define DPLL2__EN_NEGTRIG__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define DPLL2__EN_NEGTRIG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define DPLL2__EN_NEGTRIG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define DPLL2__EN_NEGTRIG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define DPLL2__EN_NEGTRIG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field kd */ +#define DPLL2__KD__SHIFT 19 +#define DPLL2__KD__WIDTH 7 +#define DPLL2__KD__MASK 0x03f80000U +#define DPLL2__KD__READ(src) (((u_int32_t)(src) & 0x03f80000U) >> 19) +#define DPLL2__KD__WRITE(src) (((u_int32_t)(src) << 19) & 0x03f80000U) +#define DPLL2__KD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03f80000U) | (((u_int32_t)(src) <<\ + 19) & 0x03f80000U) +#define DPLL2__KD__VERIFY(src) (!((((u_int32_t)(src) << 19) & ~0x03f80000U))) + +/* macros for field ki */ +#define DPLL2__KI__SHIFT 26 +#define DPLL2__KI__WIDTH 4 +#define DPLL2__KI__MASK 0x3c000000U +#define DPLL2__KI__READ(src) (((u_int32_t)(src) & 0x3c000000U) >> 26) +#define DPLL2__KI__WRITE(src) (((u_int32_t)(src) << 26) & 0x3c000000U) +#define DPLL2__KI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x3c000000U) +#define DPLL2__KI__VERIFY(src) (!((((u_int32_t)(src) << 26) & ~0x3c000000U))) + +/* macros for field local_pll */ +#define DPLL2__LOCAL_PLL__SHIFT 30 +#define DPLL2__LOCAL_PLL__WIDTH 1 +#define DPLL2__LOCAL_PLL__MASK 0x40000000U +#define DPLL2__LOCAL_PLL__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define DPLL2__LOCAL_PLL__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define DPLL2__LOCAL_PLL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define DPLL2__LOCAL_PLL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define DPLL2__LOCAL_PLL__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define DPLL2__LOCAL_PLL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field range */ +#define DPLL2__RANGE__SHIFT 31 +#define DPLL2__RANGE__WIDTH 1 +#define DPLL2__RANGE__MASK 0x80000000U +#define DPLL2__RANGE__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define DPLL2__RANGE__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) +#define DPLL2__RANGE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define DPLL2__RANGE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define DPLL2__RANGE__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define DPLL2__RANGE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define DPLL2__TYPE u_int32_t +#define DPLL2__READ 0xffffffffU +#define DPLL2__WRITE 0xffffffffU + +#endif /* __DPLL2_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_BB_PLL2 */ +#define INST_RADIO65_REG_MAP__CH0_BB_PLL2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DPLL3 */ +#ifndef __DPLL3_MACRO__ +#define __DPLL3_MACRO__ + +/* macros for field testinLSB */ +#define DPLL3__TESTINLSB__SHIFT 0 +#define DPLL3__TESTINLSB__WIDTH 3 +#define DPLL3__TESTINLSB__MASK 0x00000007U +#define DPLL3__TESTINLSB__READ(src) (u_int32_t)(src) & 0x00000007U +#define DPLL3__TESTINLSB__WRITE(src) ((u_int32_t)(src) & 0x00000007U) +#define DPLL3__TESTINLSB__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000007U) | ((u_int32_t)(src) &\ + 0x00000007U) +#define DPLL3__TESTINLSB__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) + +/* macros for field sqsum_dvc */ +#define DPLL3__SQSUM_DVC__SHIFT 3 +#define DPLL3__SQSUM_DVC__WIDTH 20 +#define DPLL3__SQSUM_DVC__MASK 0x007ffff8U +#define DPLL3__SQSUM_DVC__READ(src) (((u_int32_t)(src) & 0x007ffff8U) >> 3) + +/* macros for field phase_shift */ +#define DPLL3__PHASE_SHIFT__SHIFT 23 +#define DPLL3__PHASE_SHIFT__WIDTH 7 +#define DPLL3__PHASE_SHIFT__MASK 0x3f800000U +#define DPLL3__PHASE_SHIFT__READ(src) (((u_int32_t)(src) & 0x3f800000U) >> 23) +#define DPLL3__PHASE_SHIFT__WRITE(src) (((u_int32_t)(src) << 23) & 0x3f800000U) +#define DPLL3__PHASE_SHIFT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f800000U) | (((u_int32_t)(src) <<\ + 23) & 0x3f800000U) +#define DPLL3__PHASE_SHIFT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x3f800000U))) + +/* macros for field do_meas */ +#define DPLL3__DO_MEAS__SHIFT 30 +#define DPLL3__DO_MEAS__WIDTH 1 +#define DPLL3__DO_MEAS__MASK 0x40000000U +#define DPLL3__DO_MEAS__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define DPLL3__DO_MEAS__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) +#define DPLL3__DO_MEAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define DPLL3__DO_MEAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define DPLL3__DO_MEAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define DPLL3__DO_MEAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field meas_at_txon */ +#define DPLL3__MEAS_AT_TXON__SHIFT 31 +#define DPLL3__MEAS_AT_TXON__WIDTH 1 +#define DPLL3__MEAS_AT_TXON__MASK 0x80000000U +#define DPLL3__MEAS_AT_TXON__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define DPLL3__MEAS_AT_TXON__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define DPLL3__MEAS_AT_TXON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define DPLL3__MEAS_AT_TXON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define DPLL3__MEAS_AT_TXON__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define DPLL3__MEAS_AT_TXON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define DPLL3__TYPE u_int32_t +#define DPLL3__READ 0xffffffffU +#define DPLL3__WRITE 0xffffffffU + +#endif /* __DPLL3_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_BB_PLL3 */ +#define INST_RADIO65_REG_MAP__CH0_BB_PLL3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::DPLL4 */ +#ifndef __DPLL4_MACRO__ +#define __DPLL4_MACRO__ + +/* macros for field SPARE */ +#define DPLL4__SPARE__SHIFT 0 +#define DPLL4__SPARE__WIDTH 1 +#define DPLL4__SPARE__MASK 0x00000001U +#define DPLL4__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U +#define DPLL4__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define DPLL4__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define DPLL4__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define DPLL4__SPARE__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1) +#define DPLL4__SPARE__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0) + +/* macros for field sel_count */ +#define DPLL4__SEL_COUNT__SHIFT 1 +#define DPLL4__SEL_COUNT__WIDTH 1 +#define DPLL4__SEL_COUNT__MASK 0x00000002U +#define DPLL4__SEL_COUNT__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define DPLL4__SEL_COUNT__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define DPLL4__SEL_COUNT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define DPLL4__SEL_COUNT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define DPLL4__SEL_COUNT__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define DPLL4__SEL_COUNT__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field reset_test */ +#define DPLL4__RESET_TEST__SHIFT 2 +#define DPLL4__RESET_TEST__WIDTH 1 +#define DPLL4__RESET_TEST__MASK 0x00000004U +#define DPLL4__RESET_TEST__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define DPLL4__RESET_TEST__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define DPLL4__RESET_TEST__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define DPLL4__RESET_TEST__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define DPLL4__RESET_TEST__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define DPLL4__RESET_TEST__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field meas_done */ +#define DPLL4__MEAS_DONE__SHIFT 3 +#define DPLL4__MEAS_DONE__WIDTH 1 +#define DPLL4__MEAS_DONE__MASK 0x00000008U +#define DPLL4__MEAS_DONE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define DPLL4__MEAS_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define DPLL4__MEAS_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field vc_meas0 */ +#define DPLL4__VC_MEAS0__SHIFT 4 +#define DPLL4__VC_MEAS0__WIDTH 17 +#define DPLL4__VC_MEAS0__MASK 0x001ffff0U +#define DPLL4__VC_MEAS0__READ(src) (((u_int32_t)(src) & 0x001ffff0U) >> 4) + +/* macros for field mean_dvc */ +#define DPLL4__MEAN_DVC__SHIFT 21 +#define DPLL4__MEAN_DVC__WIDTH 11 +#define DPLL4__MEAN_DVC__MASK 0xffe00000U +#define DPLL4__MEAN_DVC__READ(src) (((u_int32_t)(src) & 0xffe00000U) >> 21) +#define DPLL4__TYPE u_int32_t +#define DPLL4__READ 0xffffffffU +#define DPLL4__WRITE 0xffffffffU + +#endif /* __DPLL4_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_BB_PLL4 */ +#define INST_RADIO65_REG_MAP__CH0_BB_PLL4__NUM 1 + +/* macros for radio65_reg_map.ch0_CPU_PLL */ +#define INST_RADIO65_REG_MAP__CH0_CPU_PLL__NUM 1 + +/* macros for radio65_reg_map.ch0_CPU_PLL2 */ +#define INST_RADIO65_REG_MAP__CH0_CPU_PLL2__NUM 1 + +/* macros for radio65_reg_map.ch0_CPU_PLL3 */ +#define INST_RADIO65_REG_MAP__CH0_CPU_PLL3__NUM 1 + +/* macros for radio65_reg_map.ch0_CPU_PLL4 */ +#define INST_RADIO65_REG_MAP__CH0_CPU_PLL4__NUM 1 + +/* macros for radio65_reg_map.ch0_AUDIO_PLL */ +#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL__NUM 1 + +/* macros for radio65_reg_map.ch0_AUDIO_PLL2 */ +#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL2__NUM 1 + +/* macros for radio65_reg_map.ch0_AUDIO_PLL3 */ +#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL3__NUM 1 + +/* macros for radio65_reg_map.ch0_AUDIO_PLL4 */ +#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL4__NUM 1 + +/* macros for radio65_reg_map.ch0_DDR_PLL */ +#define INST_RADIO65_REG_MAP__CH0_DDR_PLL__NUM 1 + +/* macros for radio65_reg_map.ch0_DDR_PLL2 */ +#define INST_RADIO65_REG_MAP__CH0_DDR_PLL2__NUM 1 + +/* macros for radio65_reg_map.ch0_DDR_PLL3 */ +#define INST_RADIO65_REG_MAP__CH0_DDR_PLL3__NUM 1 + +/* macros for radio65_reg_map.ch0_DDR_PLL4 */ +#define INST_RADIO65_REG_MAP__CH0_DDR_PLL4__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TOP */ +#ifndef __TOP_MACRO__ +#define __TOP_MACRO__ + +/* macros for field sel_tempsensor */ +#define TOP__SEL_TEMPSENSOR__SHIFT 0 +#define TOP__SEL_TEMPSENSOR__WIDTH 1 +#define TOP__SEL_TEMPSENSOR__MASK 0x00000001U +#define TOP__SEL_TEMPSENSOR__READ(src) (u_int32_t)(src) & 0x00000001U +#define TOP__SEL_TEMPSENSOR__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TOP__SEL_TEMPSENSOR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TOP__SEL_TEMPSENSOR__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) +#define TOP__SEL_TEMPSENSOR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TOP__SEL_TEMPSENSOR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field spare */ +#define TOP__SPARE__SHIFT 1 +#define TOP__SPARE__WIDTH 1 +#define TOP__SPARE__MASK 0x00000002U +#define TOP__SPARE__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define TOP__SPARE__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define TOP__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define TOP__SPARE__VERIFY(src) (!((((u_int32_t)(src) << 1) & ~0x00000002U))) +#define TOP__SPARE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TOP__SPARE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field clk107_en */ +#define TOP__CLK107_EN__SHIFT 2 +#define TOP__CLK107_EN__WIDTH 1 +#define TOP__CLK107_EN__MASK 0x00000004U +#define TOP__CLK107_EN__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define TOP__CLK107_EN__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define TOP__CLK107_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define TOP__CLK107_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define TOP__CLK107_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TOP__CLK107_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field pwdv2i */ +#define TOP__PWDV2I__SHIFT 3 +#define TOP__PWDV2I__WIDTH 1 +#define TOP__PWDV2I__MASK 0x00000008U +#define TOP__PWDV2I__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define TOP__PWDV2I__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define TOP__PWDV2I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TOP__PWDV2I__VERIFY(src) (!((((u_int32_t)(src) << 3) & ~0x00000008U))) +#define TOP__PWDV2I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TOP__PWDV2I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field pwdbias */ +#define TOP__PWDBIAS__SHIFT 4 +#define TOP__PWDBIAS__WIDTH 1 +#define TOP__PWDBIAS__MASK 0x00000010U +#define TOP__PWDBIAS__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) +#define TOP__PWDBIAS__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) +#define TOP__PWDBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define TOP__PWDBIAS__VERIFY(src) (!((((u_int32_t)(src) << 4) & ~0x00000010U))) +#define TOP__PWDBIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define TOP__PWDBIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field xpabias_bypass */ +#define TOP__XPABIAS_BYPASS__SHIFT 5 +#define TOP__XPABIAS_BYPASS__WIDTH 1 +#define TOP__XPABIAS_BYPASS__MASK 0x00000020U +#define TOP__XPABIAS_BYPASS__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define TOP__XPABIAS_BYPASS__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) +#define TOP__XPABIAS_BYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define TOP__XPABIAS_BYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define TOP__XPABIAS_BYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define TOP__XPABIAS_BYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field xpabiaslvl */ +#define TOP__XPABIASLVL__SHIFT 6 +#define TOP__XPABIASLVL__WIDTH 4 +#define TOP__XPABIASLVL__MASK 0x000003c0U +#define TOP__XPABIASLVL__READ(src) (((u_int32_t)(src) & 0x000003c0U) >> 6) +#define TOP__XPABIASLVL__WRITE(src) (((u_int32_t)(src) << 6) & 0x000003c0U) +#define TOP__XPABIASLVL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000003c0U) +#define TOP__XPABIASLVL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000003c0U))) + +/* macros for field xparegulator_en */ +#define TOP__XPAREGULATOR_EN__SHIFT 10 +#define TOP__XPAREGULATOR_EN__WIDTH 1 +#define TOP__XPAREGULATOR_EN__MASK 0x00000400U +#define TOP__XPAREGULATOR_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define TOP__XPAREGULATOR_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define TOP__XPAREGULATOR_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define TOP__XPAREGULATOR_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define TOP__XPAREGULATOR_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define TOP__XPAREGULATOR_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field xpashort2gnd */ +#define TOP__XPASHORT2GND__SHIFT 11 +#define TOP__XPASHORT2GND__WIDTH 1 +#define TOP__XPASHORT2GND__MASK 0x00000800U +#define TOP__XPASHORT2GND__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define TOP__XPASHORT2GND__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define TOP__XPASHORT2GND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define TOP__XPASHORT2GND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define TOP__XPASHORT2GND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define TOP__XPASHORT2GND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field xpa5on */ +#define TOP__XPA5ON__SHIFT 12 +#define TOP__XPA5ON__WIDTH 3 +#define TOP__XPA5ON__MASK 0x00007000U +#define TOP__XPA5ON__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12) +#define TOP__XPA5ON__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U) +#define TOP__XPA5ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define TOP__XPA5ON__VERIFY(src) (!((((u_int32_t)(src) << 12) & ~0x00007000U))) + +/* macros for field xpa2on */ +#define TOP__XPA2ON__SHIFT 15 +#define TOP__XPA2ON__WIDTH 3 +#define TOP__XPA2ON__MASK 0x00038000U +#define TOP__XPA2ON__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) +#define TOP__XPA2ON__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) +#define TOP__XPA2ON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define TOP__XPA2ON__VERIFY(src) (!((((u_int32_t)(src) << 15) & ~0x00038000U))) + +/* macros for field local_xpaon */ +#define TOP__LOCAL_XPAON__SHIFT 18 +#define TOP__LOCAL_XPAON__WIDTH 1 +#define TOP__LOCAL_XPAON__MASK 0x00040000U +#define TOP__LOCAL_XPAON__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) +#define TOP__LOCAL_XPAON__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) +#define TOP__LOCAL_XPAON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00040000U) | (((u_int32_t)(src) <<\ + 18) & 0x00040000U) +#define TOP__LOCAL_XPAON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x00040000U))) +#define TOP__LOCAL_XPAON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(1) << 18) +#define TOP__LOCAL_XPAON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00040000U) | ((u_int32_t)(0) << 18) + +/* macros for field pad2gnd */ +#define TOP__PAD2GND__SHIFT 19 +#define TOP__PAD2GND__WIDTH 1 +#define TOP__PAD2GND__MASK 0x00080000U +#define TOP__PAD2GND__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) +#define TOP__PAD2GND__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) +#define TOP__PAD2GND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00080000U) | (((u_int32_t)(src) <<\ + 19) & 0x00080000U) +#define TOP__PAD2GND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 19) & ~0x00080000U))) +#define TOP__PAD2GND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(1) << 19) +#define TOP__PAD2GND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00080000U) | ((u_int32_t)(0) << 19) + +/* macros for field intH2pad */ +#define TOP__INTH2PAD__SHIFT 20 +#define TOP__INTH2PAD__WIDTH 1 +#define TOP__INTH2PAD__MASK 0x00100000U +#define TOP__INTH2PAD__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) +#define TOP__INTH2PAD__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) +#define TOP__INTH2PAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00100000U) | (((u_int32_t)(src) <<\ + 20) & 0x00100000U) +#define TOP__INTH2PAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 20) & ~0x00100000U))) +#define TOP__INTH2PAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(1) << 20) +#define TOP__INTH2PAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00100000U) | ((u_int32_t)(0) << 20) + +/* macros for field intH2gnd */ +#define TOP__INTH2GND__SHIFT 21 +#define TOP__INTH2GND__WIDTH 1 +#define TOP__INTH2GND__MASK 0x00200000U +#define TOP__INTH2GND__READ(src) (((u_int32_t)(src) & 0x00200000U) >> 21) +#define TOP__INTH2GND__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U) +#define TOP__INTH2GND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00200000U) | (((u_int32_t)(src) <<\ + 21) & 0x00200000U) +#define TOP__INTH2GND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00200000U))) +#define TOP__INTH2GND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(1) << 21) +#define TOP__INTH2GND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00200000U) | ((u_int32_t)(0) << 21) + +/* macros for field int2pad */ +#define TOP__INT2PAD__SHIFT 22 +#define TOP__INT2PAD__WIDTH 1 +#define TOP__INT2PAD__MASK 0x00400000U +#define TOP__INT2PAD__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22) +#define TOP__INT2PAD__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U) +#define TOP__INT2PAD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00400000U) | (((u_int32_t)(src) <<\ + 22) & 0x00400000U) +#define TOP__INT2PAD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 22) & ~0x00400000U))) +#define TOP__INT2PAD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(1) << 22) +#define TOP__INT2PAD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00400000U) | ((u_int32_t)(0) << 22) + +/* macros for field int2gnd */ +#define TOP__INT2GND__SHIFT 23 +#define TOP__INT2GND__WIDTH 1 +#define TOP__INT2GND__MASK 0x00800000U +#define TOP__INT2GND__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) +#define TOP__INT2GND__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) +#define TOP__INT2GND__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00800000U) | (((u_int32_t)(src) <<\ + 23) & 0x00800000U) +#define TOP__INT2GND__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 23) & ~0x00800000U))) +#define TOP__INT2GND__SET(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(1) << 23) +#define TOP__INT2GND__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00800000U) | ((u_int32_t)(0) << 23) + +/* macros for field enBTclk */ +#define TOP__ENBTCLK__SHIFT 24 +#define TOP__ENBTCLK__WIDTH 1 +#define TOP__ENBTCLK__MASK 0x01000000U +#define TOP__ENBTCLK__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) +#define TOP__ENBTCLK__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U) +#define TOP__ENBTCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TOP__ENBTCLK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TOP__ENBTCLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TOP__ENBTCLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field pwdPALclk */ +#define TOP__PWDPALCLK__SHIFT 25 +#define TOP__PWDPALCLK__WIDTH 1 +#define TOP__PWDPALCLK__MASK 0x02000000U +#define TOP__PWDPALCLK__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) +#define TOP__PWDPALCLK__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U) +#define TOP__PWDPALCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define TOP__PWDPALCLK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define TOP__PWDPALCLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define TOP__PWDPALCLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field inv_clk320_adc */ +#define TOP__INV_CLK320_ADC__SHIFT 26 +#define TOP__INV_CLK320_ADC__WIDTH 1 +#define TOP__INV_CLK320_ADC__MASK 0x04000000U +#define TOP__INV_CLK320_ADC__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) +#define TOP__INV_CLK320_ADC__WRITE(src) \ + (((u_int32_t)(src)\ + << 26) & 0x04000000U) +#define TOP__INV_CLK320_ADC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x04000000U) | (((u_int32_t)(src) <<\ + 26) & 0x04000000U) +#define TOP__INV_CLK320_ADC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x04000000U))) +#define TOP__INV_CLK320_ADC__SET(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(1) << 26) +#define TOP__INV_CLK320_ADC__CLR(dst) \ + (dst) = ((dst) &\ + ~0x04000000U) | ((u_int32_t)(0) << 26) + +/* macros for field flip_refclk40 */ +#define TOP__FLIP_REFCLK40__SHIFT 27 +#define TOP__FLIP_REFCLK40__WIDTH 1 +#define TOP__FLIP_REFCLK40__MASK 0x08000000U +#define TOP__FLIP_REFCLK40__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) +#define TOP__FLIP_REFCLK40__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U) +#define TOP__FLIP_REFCLK40__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x08000000U) | (((u_int32_t)(src) <<\ + 27) & 0x08000000U) +#define TOP__FLIP_REFCLK40__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 27) & ~0x08000000U))) +#define TOP__FLIP_REFCLK40__SET(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(1) << 27) +#define TOP__FLIP_REFCLK40__CLR(dst) \ + (dst) = ((dst) &\ + ~0x08000000U) | ((u_int32_t)(0) << 27) + +/* macros for field flip_pllclk320 */ +#define TOP__FLIP_PLLCLK320__SHIFT 28 +#define TOP__FLIP_PLLCLK320__WIDTH 1 +#define TOP__FLIP_PLLCLK320__MASK 0x10000000U +#define TOP__FLIP_PLLCLK320__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define TOP__FLIP_PLLCLK320__WRITE(src) \ + (((u_int32_t)(src)\ + << 28) & 0x10000000U) +#define TOP__FLIP_PLLCLK320__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TOP__FLIP_PLLCLK320__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TOP__FLIP_PLLCLK320__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TOP__FLIP_PLLCLK320__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field flip_pllclk160 */ +#define TOP__FLIP_PLLCLK160__SHIFT 29 +#define TOP__FLIP_PLLCLK160__WIDTH 1 +#define TOP__FLIP_PLLCLK160__MASK 0x20000000U +#define TOP__FLIP_PLLCLK160__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define TOP__FLIP_PLLCLK160__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define TOP__FLIP_PLLCLK160__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define TOP__FLIP_PLLCLK160__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define TOP__FLIP_PLLCLK160__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define TOP__FLIP_PLLCLK160__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field clk_sel */ +#define TOP__CLK_SEL__SHIFT 30 +#define TOP__CLK_SEL__WIDTH 2 +#define TOP__CLK_SEL__MASK 0xc0000000U +#define TOP__CLK_SEL__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) +#define TOP__CLK_SEL__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U) +#define TOP__CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xc0000000U) | (((u_int32_t)(src) <<\ + 30) & 0xc0000000U) +#define TOP__CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0xc0000000U))) +#define TOP__TYPE u_int32_t +#define TOP__READ 0xffffffffU +#define TOP__WRITE 0xffffffffU + +#endif /* __TOP_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_TOP */ +#define INST_RADIO65_REG_MAP__CH0_TOP__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TOP2 */ +#ifndef __TOP2_MACRO__ +#define __TOP2_MACRO__ + +/* macros for field rst_warm_int_l */ +#define TOP2__RST_WARM_INT_L__SHIFT 0 +#define TOP2__RST_WARM_INT_L__WIDTH 1 +#define TOP2__RST_WARM_INT_L__MASK 0x00000001U +#define TOP2__RST_WARM_INT_L__READ(src) (u_int32_t)(src) & 0x00000001U +#define TOP2__RST_WARM_INT_L__WRITE(src) ((u_int32_t)(src) & 0x00000001U) +#define TOP2__RST_WARM_INT_L__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define TOP2__RST_WARM_INT_L__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define TOP2__RST_WARM_INT_L__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define TOP2__RST_WARM_INT_L__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field rst_warm_ovr */ +#define TOP2__RST_WARM_OVR__SHIFT 1 +#define TOP2__RST_WARM_OVR__WIDTH 1 +#define TOP2__RST_WARM_OVR__MASK 0x00000002U +#define TOP2__RST_WARM_OVR__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) +#define TOP2__RST_WARM_OVR__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) +#define TOP2__RST_WARM_OVR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define TOP2__RST_WARM_OVR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define TOP2__RST_WARM_OVR__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define TOP2__RST_WARM_OVR__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field global_clk_en */ +#define TOP2__GLOBAL_CLK_EN__SHIFT 2 +#define TOP2__GLOBAL_CLK_EN__WIDTH 1 +#define TOP2__GLOBAL_CLK_EN__MASK 0x00000004U +#define TOP2__GLOBAL_CLK_EN__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) +#define TOP2__GLOBAL_CLK_EN__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) +#define TOP2__GLOBAL_CLK_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define TOP2__GLOBAL_CLK_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define TOP2__GLOBAL_CLK_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define TOP2__GLOBAL_CLK_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field local_clkmoda */ +#define TOP2__LOCAL_CLKMODA__SHIFT 3 +#define TOP2__LOCAL_CLKMODA__WIDTH 1 +#define TOP2__LOCAL_CLKMODA__MASK 0x00000008U +#define TOP2__LOCAL_CLKMODA__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) +#define TOP2__LOCAL_CLKMODA__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) +#define TOP2__LOCAL_CLKMODA__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define TOP2__LOCAL_CLKMODA__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define TOP2__LOCAL_CLKMODA__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define TOP2__LOCAL_CLKMODA__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field pllbypass */ +#define TOP2__PLLBYPASS__SHIFT 4 +#define TOP2__PLLBYPASS__WIDTH 1 +#define TOP2__PLLBYPASS__MASK 0x00000010U +#define TOP2__PLLBYPASS__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) +#define TOP2__PLLBYPASS__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) +#define TOP2__PLLBYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define TOP2__PLLBYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define TOP2__PLLBYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define TOP2__PLLBYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field local_pllbypass */ +#define TOP2__LOCAL_PLLBYPASS__SHIFT 5 +#define TOP2__LOCAL_PLLBYPASS__WIDTH 1 +#define TOP2__LOCAL_PLLBYPASS__MASK 0x00000020U +#define TOP2__LOCAL_PLLBYPASS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define TOP2__LOCAL_PLLBYPASS__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define TOP2__LOCAL_PLLBYPASS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define TOP2__LOCAL_PLLBYPASS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define TOP2__LOCAL_PLLBYPASS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define TOP2__LOCAL_PLLBYPASS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field testtxiq_enbypass_b */ +#define TOP2__TESTTXIQ_ENBYPASS_B__SHIFT 6 +#define TOP2__TESTTXIQ_ENBYPASS_B__WIDTH 3 +#define TOP2__TESTTXIQ_ENBYPASS_B__MASK 0x000001c0U +#define TOP2__TESTTXIQ_ENBYPASS_B__READ(src) \ + (((u_int32_t)(src)\ + & 0x000001c0U) >> 6) +#define TOP2__TESTTXIQ_ENBYPASS_B__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x000001c0U) +#define TOP2__TESTTXIQ_ENBYPASS_B__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000001c0U) | (((u_int32_t)(src) <<\ + 6) & 0x000001c0U) +#define TOP2__TESTTXIQ_ENBYPASS_B__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x000001c0U))) + +/* macros for field testtxiq_rctrl */ +#define TOP2__TESTTXIQ_RCTRL__SHIFT 9 +#define TOP2__TESTTXIQ_RCTRL__WIDTH 3 +#define TOP2__TESTTXIQ_RCTRL__MASK 0x00000e00U +#define TOP2__TESTTXIQ_RCTRL__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) +#define TOP2__TESTTXIQ_RCTRL__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000e00U) +#define TOP2__TESTTXIQ_RCTRL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000e00U) | (((u_int32_t)(src) <<\ + 9) & 0x00000e00U) +#define TOP2__TESTTXIQ_RCTRL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000e00U))) + +/* macros for field testtxiq_enloopback */ +#define TOP2__TESTTXIQ_ENLOOPBACK__SHIFT 12 +#define TOP2__TESTTXIQ_ENLOOPBACK__WIDTH 3 +#define TOP2__TESTTXIQ_ENLOOPBACK__MASK 0x00007000U +#define TOP2__TESTTXIQ_ENLOOPBACK__READ(src) \ + (((u_int32_t)(src)\ + & 0x00007000U) >> 12) +#define TOP2__TESTTXIQ_ENLOOPBACK__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00007000U) +#define TOP2__TESTTXIQ_ENLOOPBACK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00007000U) | (((u_int32_t)(src) <<\ + 12) & 0x00007000U) +#define TOP2__TESTTXIQ_ENLOOPBACK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00007000U))) + +/* macros for field testtxiq_pwd */ +#define TOP2__TESTTXIQ_PWD__SHIFT 15 +#define TOP2__TESTTXIQ_PWD__WIDTH 3 +#define TOP2__TESTTXIQ_PWD__MASK 0x00038000U +#define TOP2__TESTTXIQ_PWD__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) +#define TOP2__TESTTXIQ_PWD__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) +#define TOP2__TESTTXIQ_PWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00038000U) | (((u_int32_t)(src) <<\ + 15) & 0x00038000U) +#define TOP2__TESTTXIQ_PWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00038000U))) + +/* macros for field dacpwd */ +#define TOP2__DACPWD__SHIFT 18 +#define TOP2__DACPWD__WIDTH 3 +#define TOP2__DACPWD__MASK 0x001c0000U +#define TOP2__DACPWD__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18) +#define TOP2__DACPWD__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U) +#define TOP2__DACPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001c0000U) | (((u_int32_t)(src) <<\ + 18) & 0x001c0000U) +#define TOP2__DACPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 18) & ~0x001c0000U))) + +/* macros for field adcpwd */ +#define TOP2__ADCPWD__SHIFT 21 +#define TOP2__ADCPWD__WIDTH 3 +#define TOP2__ADCPWD__MASK 0x00e00000U +#define TOP2__ADCPWD__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21) +#define TOP2__ADCPWD__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U) +#define TOP2__ADCPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00e00000U) | (((u_int32_t)(src) <<\ + 21) & 0x00e00000U) +#define TOP2__ADCPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 21) & ~0x00e00000U))) + +/* macros for field local_addacpwd */ +#define TOP2__LOCAL_ADDACPWD__SHIFT 24 +#define TOP2__LOCAL_ADDACPWD__WIDTH 1 +#define TOP2__LOCAL_ADDACPWD__MASK 0x01000000U +#define TOP2__LOCAL_ADDACPWD__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define TOP2__LOCAL_ADDACPWD__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define TOP2__LOCAL_ADDACPWD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define TOP2__LOCAL_ADDACPWD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define TOP2__LOCAL_ADDACPWD__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define TOP2__LOCAL_ADDACPWD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field adc_clk_sel */ +#define TOP2__ADC_CLK_SEL__SHIFT 25 +#define TOP2__ADC_CLK_SEL__WIDTH 4 +#define TOP2__ADC_CLK_SEL__MASK 0x1e000000U +#define TOP2__ADC_CLK_SEL__READ(src) (((u_int32_t)(src) & 0x1e000000U) >> 25) +#define TOP2__ADC_CLK_SEL__WRITE(src) (((u_int32_t)(src) << 25) & 0x1e000000U) +#define TOP2__ADC_CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1e000000U) | (((u_int32_t)(src) <<\ + 25) & 0x1e000000U) +#define TOP2__ADC_CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x1e000000U))) + +/* macros for field dac_clk_sel */ +#define TOP2__DAC_CLK_SEL__SHIFT 29 +#define TOP2__DAC_CLK_SEL__WIDTH 3 +#define TOP2__DAC_CLK_SEL__MASK 0xe0000000U +#define TOP2__DAC_CLK_SEL__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) +#define TOP2__DAC_CLK_SEL__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) +#define TOP2__DAC_CLK_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xe0000000U) | (((u_int32_t)(src) <<\ + 29) & 0xe0000000U) +#define TOP2__DAC_CLK_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0xe0000000U))) +#define TOP2__TYPE u_int32_t +#define TOP2__READ 0xffffffffU +#define TOP2__WRITE 0xffffffffU + +#endif /* __TOP2_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_TOP2 */ +#define INST_RADIO65_REG_MAP__CH0_TOP2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::TOP3 */ +#ifndef __TOP3_MACRO__ +#define __TOP3_MACRO__ + +/* macros for field spare */ +#define TOP3__SPARE__SHIFT 0 +#define TOP3__SPARE__WIDTH 16 +#define TOP3__SPARE__MASK 0x0000ffffU +#define TOP3__SPARE__READ(src) (u_int32_t)(src) & 0x0000ffffU +#define TOP3__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) +#define TOP3__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000ffffU) | ((u_int32_t)(src) &\ + 0x0000ffffU) +#define TOP3__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU))) + +/* macros for field rbias_out */ +#define TOP3__RBIAS_OUT__SHIFT 16 +#define TOP3__RBIAS_OUT__WIDTH 6 +#define TOP3__RBIAS_OUT__MASK 0x003f0000U +#define TOP3__RBIAS_OUT__READ(src) (((u_int32_t)(src) & 0x003f0000U) >> 16) + +/* macros for field rbias */ +#define TOP3__RBIAS__SHIFT 22 +#define TOP3__RBIAS__WIDTH 6 +#define TOP3__RBIAS__MASK 0x0fc00000U +#define TOP3__RBIAS__READ(src) (((u_int32_t)(src) & 0x0fc00000U) >> 22) +#define TOP3__RBIAS__WRITE(src) (((u_int32_t)(src) << 22) & 0x0fc00000U) +#define TOP3__RBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0fc00000U) | (((u_int32_t)(src) <<\ + 22) & 0x0fc00000U) +#define TOP3__RBIAS__VERIFY(src) (!((((u_int32_t)(src) << 22) & ~0x0fc00000U))) + +/* macros for field localrbias */ +#define TOP3__LOCALRBIAS__SHIFT 28 +#define TOP3__LOCALRBIAS__WIDTH 1 +#define TOP3__LOCALRBIAS__MASK 0x10000000U +#define TOP3__LOCALRBIAS__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define TOP3__LOCALRBIAS__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define TOP3__LOCALRBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define TOP3__LOCALRBIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define TOP3__LOCALRBIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define TOP3__LOCALRBIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field bbpll_atbvreg */ +#define TOP3__BBPLL_ATBVREG__SHIFT 29 +#define TOP3__BBPLL_ATBVREG__WIDTH 1 +#define TOP3__BBPLL_ATBVREG__MASK 0x20000000U +#define TOP3__BBPLL_ATBVREG__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define TOP3__BBPLL_ATBVREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 29) & 0x20000000U) +#define TOP3__BBPLL_ATBVREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define TOP3__BBPLL_ATBVREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define TOP3__BBPLL_ATBVREG__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define TOP3__BBPLL_ATBVREG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field bbpll_selvreg */ +#define TOP3__BBPLL_SELVREG__SHIFT 30 +#define TOP3__BBPLL_SELVREG__WIDTH 1 +#define TOP3__BBPLL_SELVREG__MASK 0x40000000U +#define TOP3__BBPLL_SELVREG__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) +#define TOP3__BBPLL_SELVREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define TOP3__BBPLL_SELVREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define TOP3__BBPLL_SELVREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define TOP3__BBPLL_SELVREG__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define TOP3__BBPLL_SELVREG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field bbpll_pwdvreg */ +#define TOP3__BBPLL_PWDVREG__SHIFT 31 +#define TOP3__BBPLL_PWDVREG__WIDTH 1 +#define TOP3__BBPLL_PWDVREG__MASK 0x80000000U +#define TOP3__BBPLL_PWDVREG__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define TOP3__BBPLL_PWDVREG__WRITE(src) \ + (((u_int32_t)(src)\ + << 31) & 0x80000000U) +#define TOP3__BBPLL_PWDVREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define TOP3__BBPLL_PWDVREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define TOP3__BBPLL_PWDVREG__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define TOP3__BBPLL_PWDVREG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define TOP3__TYPE u_int32_t +#define TOP3__READ 0xffffffffU +#define TOP3__WRITE 0xffffffffU + +#endif /* __TOP3_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_TOP3 */ +#define INST_RADIO65_REG_MAP__CH0_TOP3__NUM 1 + +/* macros for BlueprintGlobalNameSpace::THERM */ +#ifndef __THERM_MACRO__ +#define __THERM_MACRO__ + +/* macros for field spare */ +#define THERM__SPARE__SHIFT 0 +#define THERM__SPARE__WIDTH 6 +#define THERM__SPARE__MASK 0x0000003fU +#define THERM__SPARE__READ(src) (u_int32_t)(src) & 0x0000003fU +#define THERM__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) +#define THERM__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000003fU) | ((u_int32_t)(src) &\ + 0x0000003fU) +#define THERM__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000003fU))) + +/* macros for field rst_warm_l_therm */ +#define THERM__RST_WARM_L_THERM__SHIFT 6 +#define THERM__RST_WARM_L_THERM__WIDTH 1 +#define THERM__RST_WARM_L_THERM__MASK 0x00000040U +#define THERM__RST_WARM_L_THERM__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define THERM__RST_WARM_L_THERM__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define THERM__RST_WARM_L_THERM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define THERM__RST_WARM_L_THERM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define THERM__RST_WARM_L_THERM__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define THERM__RST_WARM_L_THERM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field sar_adc_done */ +#define THERM__SAR_ADC_DONE__SHIFT 7 +#define THERM__SAR_ADC_DONE__WIDTH 1 +#define THERM__SAR_ADC_DONE__MASK 0x00000080U +#define THERM__SAR_ADC_DONE__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define THERM__SAR_ADC_DONE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define THERM__SAR_ADC_DONE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field sar_adc_out */ +#define THERM__SAR_ADC_OUT__SHIFT 8 +#define THERM__SAR_ADC_OUT__WIDTH 8 +#define THERM__SAR_ADC_OUT__MASK 0x0000ff00U +#define THERM__SAR_ADC_OUT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) + +/* macros for field sar_dactest_code */ +#define THERM__SAR_DACTEST_CODE__SHIFT 16 +#define THERM__SAR_DACTEST_CODE__WIDTH 8 +#define THERM__SAR_DACTEST_CODE__MASK 0x00ff0000U +#define THERM__SAR_DACTEST_CODE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define THERM__SAR_DACTEST_CODE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define THERM__SAR_DACTEST_CODE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define THERM__SAR_DACTEST_CODE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field sar_dactest_en */ +#define THERM__SAR_DACTEST_EN__SHIFT 24 +#define THERM__SAR_DACTEST_EN__WIDTH 1 +#define THERM__SAR_DACTEST_EN__MASK 0x01000000U +#define THERM__SAR_DACTEST_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x01000000U) >> 24) +#define THERM__SAR_DACTEST_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x01000000U) +#define THERM__SAR_DACTEST_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x01000000U) | (((u_int32_t)(src) <<\ + 24) & 0x01000000U) +#define THERM__SAR_DACTEST_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x01000000U))) +#define THERM__SAR_DACTEST_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(1) << 24) +#define THERM__SAR_DACTEST_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x01000000U) | ((u_int32_t)(0) << 24) + +/* macros for field sar_adccal_en */ +#define THERM__SAR_ADCCAL_EN__SHIFT 25 +#define THERM__SAR_ADCCAL_EN__WIDTH 1 +#define THERM__SAR_ADCCAL_EN__MASK 0x02000000U +#define THERM__SAR_ADCCAL_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x02000000U) >> 25) +#define THERM__SAR_ADCCAL_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 25) & 0x02000000U) +#define THERM__SAR_ADCCAL_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x02000000U) | (((u_int32_t)(src) <<\ + 25) & 0x02000000U) +#define THERM__SAR_ADCCAL_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 25) & ~0x02000000U))) +#define THERM__SAR_ADCCAL_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(1) << 25) +#define THERM__SAR_ADCCAL_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x02000000U) | ((u_int32_t)(0) << 25) + +/* macros for field thermsel */ +#define THERM__THERMSEL__SHIFT 26 +#define THERM__THERMSEL__WIDTH 2 +#define THERM__THERMSEL__MASK 0x0c000000U +#define THERM__THERMSEL__READ(src) (((u_int32_t)(src) & 0x0c000000U) >> 26) +#define THERM__THERMSEL__WRITE(src) (((u_int32_t)(src) << 26) & 0x0c000000U) +#define THERM__THERMSEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0c000000U) | (((u_int32_t)(src) <<\ + 26) & 0x0c000000U) +#define THERM__THERMSEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 26) & ~0x0c000000U))) + +/* macros for field sar_slow_en */ +#define THERM__SAR_SLOW_EN__SHIFT 28 +#define THERM__SAR_SLOW_EN__WIDTH 1 +#define THERM__SAR_SLOW_EN__MASK 0x10000000U +#define THERM__SAR_SLOW_EN__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) +#define THERM__SAR_SLOW_EN__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) +#define THERM__SAR_SLOW_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x10000000U) | (((u_int32_t)(src) <<\ + 28) & 0x10000000U) +#define THERM__SAR_SLOW_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 28) & ~0x10000000U))) +#define THERM__SAR_SLOW_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(1) << 28) +#define THERM__SAR_SLOW_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x10000000U) | ((u_int32_t)(0) << 28) + +/* macros for field thermstart */ +#define THERM__THERMSTART__SHIFT 29 +#define THERM__THERMSTART__WIDTH 1 +#define THERM__THERMSTART__MASK 0x20000000U +#define THERM__THERMSTART__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) +#define THERM__THERMSTART__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) +#define THERM__THERMSTART__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x20000000U) | (((u_int32_t)(src) <<\ + 29) & 0x20000000U) +#define THERM__THERMSTART__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 29) & ~0x20000000U))) +#define THERM__THERMSTART__SET(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(1) << 29) +#define THERM__THERMSTART__CLR(dst) \ + (dst) = ((dst) &\ + ~0x20000000U) | ((u_int32_t)(0) << 29) + +/* macros for field sar_autopwd_en */ +#define THERM__SAR_AUTOPWD_EN__SHIFT 30 +#define THERM__SAR_AUTOPWD_EN__WIDTH 1 +#define THERM__SAR_AUTOPWD_EN__MASK 0x40000000U +#define THERM__SAR_AUTOPWD_EN__READ(src) \ + (((u_int32_t)(src)\ + & 0x40000000U) >> 30) +#define THERM__SAR_AUTOPWD_EN__WRITE(src) \ + (((u_int32_t)(src)\ + << 30) & 0x40000000U) +#define THERM__SAR_AUTOPWD_EN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x40000000U) | (((u_int32_t)(src) <<\ + 30) & 0x40000000U) +#define THERM__SAR_AUTOPWD_EN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 30) & ~0x40000000U))) +#define THERM__SAR_AUTOPWD_EN__SET(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(1) << 30) +#define THERM__SAR_AUTOPWD_EN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x40000000U) | ((u_int32_t)(0) << 30) + +/* macros for field local_therm */ +#define THERM__LOCAL_THERM__SHIFT 31 +#define THERM__LOCAL_THERM__WIDTH 1 +#define THERM__LOCAL_THERM__MASK 0x80000000U +#define THERM__LOCAL_THERM__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define THERM__LOCAL_THERM__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) +#define THERM__LOCAL_THERM__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x80000000U) | (((u_int32_t)(src) <<\ + 31) & 0x80000000U) +#define THERM__LOCAL_THERM__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 31) & ~0x80000000U))) +#define THERM__LOCAL_THERM__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define THERM__LOCAL_THERM__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define THERM__TYPE u_int32_t +#define THERM__READ 0xffffffffU +#define THERM__WRITE 0xffffffffU + +#endif /* __THERM_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_THERM */ +#define INST_RADIO65_REG_MAP__CH0_THERM__NUM 1 + +/* macros for BlueprintGlobalNameSpace::XTAL */ +#ifndef __XTAL_MACRO__ +#define __XTAL_MACRO__ + +/* macros for field SPARE */ +#define XTAL__SPARE__SHIFT 0 +#define XTAL__SPARE__WIDTH 4 +#define XTAL__SPARE__MASK 0x0000000fU +#define XTAL__SPARE__READ(src) (u_int32_t)(src) & 0x0000000fU +#define XTAL__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) +#define XTAL__SPARE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define XTAL__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) + +/* macros for field swregclk_edge_sel */ +#define XTAL__SWREGCLK_EDGE_SEL__SHIFT 4 +#define XTAL__SWREGCLK_EDGE_SEL__WIDTH 1 +#define XTAL__SWREGCLK_EDGE_SEL__MASK 0x00000010U +#define XTAL__SWREGCLK_EDGE_SEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define XTAL__SWREGCLK_EDGE_SEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define XTAL__SWREGCLK_EDGE_SEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define XTAL__SWREGCLK_EDGE_SEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define XTAL__SWREGCLK_EDGE_SEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define XTAL__SWREGCLK_EDGE_SEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field pwd_swregclk */ +#define XTAL__PWD_SWREGCLK__SHIFT 5 +#define XTAL__PWD_SWREGCLK__WIDTH 1 +#define XTAL__PWD_SWREGCLK__MASK 0x00000020U +#define XTAL__PWD_SWREGCLK__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) +#define XTAL__PWD_SWREGCLK__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) +#define XTAL__PWD_SWREGCLK__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define XTAL__PWD_SWREGCLK__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define XTAL__PWD_SWREGCLK__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define XTAL__PWD_SWREGCLK__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field local_xtal */ +#define XTAL__LOCAL_XTAL__SHIFT 6 +#define XTAL__LOCAL_XTAL__WIDTH 1 +#define XTAL__LOCAL_XTAL__MASK 0x00000040U +#define XTAL__LOCAL_XTAL__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) +#define XTAL__LOCAL_XTAL__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) +#define XTAL__LOCAL_XTAL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define XTAL__LOCAL_XTAL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define XTAL__LOCAL_XTAL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define XTAL__LOCAL_XTAL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field xtal_pwdclkin */ +#define XTAL__XTAL_PWDCLKIN__SHIFT 7 +#define XTAL__XTAL_PWDCLKIN__WIDTH 1 +#define XTAL__XTAL_PWDCLKIN__MASK 0x00000080U +#define XTAL__XTAL_PWDCLKIN__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) +#define XTAL__XTAL_PWDCLKIN__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) +#define XTAL__XTAL_PWDCLKIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define XTAL__XTAL_PWDCLKIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define XTAL__XTAL_PWDCLKIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define XTAL__XTAL_PWDCLKIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field xtal_oscon */ +#define XTAL__XTAL_OSCON__SHIFT 8 +#define XTAL__XTAL_OSCON__WIDTH 1 +#define XTAL__XTAL_OSCON__MASK 0x00000100U +#define XTAL__XTAL_OSCON__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) +#define XTAL__XTAL_OSCON__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) +#define XTAL__XTAL_OSCON__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define XTAL__XTAL_OSCON__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define XTAL__XTAL_OSCON__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define XTAL__XTAL_OSCON__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field xtal_atbvreg */ +#define XTAL__XTAL_ATBVREG__SHIFT 9 +#define XTAL__XTAL_ATBVREG__WIDTH 1 +#define XTAL__XTAL_ATBVREG__MASK 0x00000200U +#define XTAL__XTAL_ATBVREG__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) +#define XTAL__XTAL_ATBVREG__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) +#define XTAL__XTAL_ATBVREG__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define XTAL__XTAL_ATBVREG__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define XTAL__XTAL_ATBVREG__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define XTAL__XTAL_ATBVREG__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field xtal_Lbias2x */ +#define XTAL__XTAL_LBIAS2X__SHIFT 10 +#define XTAL__XTAL_LBIAS2X__WIDTH 1 +#define XTAL__XTAL_LBIAS2X__MASK 0x00000400U +#define XTAL__XTAL_LBIAS2X__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) +#define XTAL__XTAL_LBIAS2X__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) +#define XTAL__XTAL_LBIAS2X__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define XTAL__XTAL_LBIAS2X__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define XTAL__XTAL_LBIAS2X__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define XTAL__XTAL_LBIAS2X__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field xtal_bias2x */ +#define XTAL__XTAL_BIAS2X__SHIFT 11 +#define XTAL__XTAL_BIAS2X__WIDTH 1 +#define XTAL__XTAL_BIAS2X__MASK 0x00000800U +#define XTAL__XTAL_BIAS2X__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) +#define XTAL__XTAL_BIAS2X__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) +#define XTAL__XTAL_BIAS2X__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define XTAL__XTAL_BIAS2X__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define XTAL__XTAL_BIAS2X__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define XTAL__XTAL_BIAS2X__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field xtal_pwdclkD */ +#define XTAL__XTAL_PWDCLKD__SHIFT 12 +#define XTAL__XTAL_PWDCLKD__WIDTH 1 +#define XTAL__XTAL_PWDCLKD__MASK 0x00001000U +#define XTAL__XTAL_PWDCLKD__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) +#define XTAL__XTAL_PWDCLKD__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) +#define XTAL__XTAL_PWDCLKD__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define XTAL__XTAL_PWDCLKD__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define XTAL__XTAL_PWDCLKD__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define XTAL__XTAL_PWDCLKD__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field xtal_localbias */ +#define XTAL__XTAL_LOCALBIAS__SHIFT 13 +#define XTAL__XTAL_LOCALBIAS__WIDTH 1 +#define XTAL__XTAL_LOCALBIAS__MASK 0x00002000U +#define XTAL__XTAL_LOCALBIAS__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define XTAL__XTAL_LOCALBIAS__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define XTAL__XTAL_LOCALBIAS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define XTAL__XTAL_LOCALBIAS__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define XTAL__XTAL_LOCALBIAS__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define XTAL__XTAL_LOCALBIAS__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field xtal_shortXin */ +#define XTAL__XTAL_SHORTXIN__SHIFT 14 +#define XTAL__XTAL_SHORTXIN__WIDTH 1 +#define XTAL__XTAL_SHORTXIN__MASK 0x00004000U +#define XTAL__XTAL_SHORTXIN__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) +#define XTAL__XTAL_SHORTXIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define XTAL__XTAL_SHORTXIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define XTAL__XTAL_SHORTXIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define XTAL__XTAL_SHORTXIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define XTAL__XTAL_SHORTXIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field xtal_drvstr */ +#define XTAL__XTAL_DRVSTR__SHIFT 15 +#define XTAL__XTAL_DRVSTR__WIDTH 2 +#define XTAL__XTAL_DRVSTR__MASK 0x00018000U +#define XTAL__XTAL_DRVSTR__READ(src) (((u_int32_t)(src) & 0x00018000U) >> 15) +#define XTAL__XTAL_DRVSTR__WRITE(src) (((u_int32_t)(src) << 15) & 0x00018000U) +#define XTAL__XTAL_DRVSTR__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00018000U) | (((u_int32_t)(src) <<\ + 15) & 0x00018000U) +#define XTAL__XTAL_DRVSTR__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00018000U))) + +/* macros for field xtal_capoutdac */ +#define XTAL__XTAL_CAPOUTDAC__SHIFT 17 +#define XTAL__XTAL_CAPOUTDAC__WIDTH 7 +#define XTAL__XTAL_CAPOUTDAC__MASK 0x00fe0000U +#define XTAL__XTAL_CAPOUTDAC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00fe0000U) >> 17) +#define XTAL__XTAL_CAPOUTDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 17) & 0x00fe0000U) +#define XTAL__XTAL_CAPOUTDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00fe0000U) | (((u_int32_t)(src) <<\ + 17) & 0x00fe0000U) +#define XTAL__XTAL_CAPOUTDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 17) & ~0x00fe0000U))) + +/* macros for field xtal_capindac */ +#define XTAL__XTAL_CAPINDAC__SHIFT 24 +#define XTAL__XTAL_CAPINDAC__WIDTH 7 +#define XTAL__XTAL_CAPINDAC__MASK 0x7f000000U +#define XTAL__XTAL_CAPINDAC__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24) +#define XTAL__XTAL_CAPINDAC__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define XTAL__XTAL_CAPINDAC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define XTAL__XTAL_CAPINDAC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) + +/* macros for field tcxodet */ +#define XTAL__TCXODET__SHIFT 31 +#define XTAL__TCXODET__WIDTH 1 +#define XTAL__TCXODET__MASK 0x80000000U +#define XTAL__TCXODET__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) +#define XTAL__TCXODET__SET(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(1) << 31) +#define XTAL__TCXODET__CLR(dst) \ + (dst) = ((dst) &\ + ~0x80000000U) | ((u_int32_t)(0) << 31) +#define XTAL__TYPE u_int32_t +#define XTAL__READ 0xffffffffU +#define XTAL__WRITE 0xffffffffU + +#endif /* __XTAL_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_XTAL */ +#define INST_RADIO65_REG_MAP__CH0_XTAL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rbist_cntrl_type */ +#ifndef __RBIST_CNTRL_TYPE_MACRO__ +#define __RBIST_CNTRL_TYPE_MACRO__ + +/* macros for field ate_tonegen_dc_enable */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__SHIFT 0 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__MASK 0x00000001U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__READ(src) \ + (u_int32_t)(src)\ + & 0x00000001U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000001U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000001U) | ((u_int32_t)(src) &\ + 0x00000001U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000001U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(1) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000001U) | (u_int32_t)(0) + +/* macros for field ate_tonegen_tone0_enable */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__SHIFT 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__MASK 0x00000002U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000002U) >> 1) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 1) & 0x00000002U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000002U) | (((u_int32_t)(src) <<\ + 1) & 0x00000002U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 1) & ~0x00000002U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(1) << 1) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000002U) | ((u_int32_t)(0) << 1) + +/* macros for field ate_tonegen_tone1_enable */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__SHIFT 2 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__MASK 0x00000004U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000004U) >> 2) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 2) & 0x00000004U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000004U) | (((u_int32_t)(src) <<\ + 2) & 0x00000004U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 2) & ~0x00000004U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(1) << 2) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000004U) | ((u_int32_t)(0) << 2) + +/* macros for field ate_tonegen_lftone0_enable */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__SHIFT 3 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__MASK 0x00000008U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000008U) >> 3) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 3) & 0x00000008U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000008U) | (((u_int32_t)(src) <<\ + 3) & 0x00000008U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 3) & ~0x00000008U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(1) << 3) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000008U) | ((u_int32_t)(0) << 3) + +/* macros for field ate_tonegen_linramp_enable_i */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__SHIFT 4 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__MASK 0x00000010U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field ate_tonegen_linramp_enable_q */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__SHIFT 5 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__MASK 0x00000020U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000020U) >> 5) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 5) & 0x00000020U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000020U) | (((u_int32_t)(src) <<\ + 5) & 0x00000020U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 5) & ~0x00000020U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(1) << 5) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000020U) | ((u_int32_t)(0) << 5) + +/* macros for field ate_tonegen_prbs_enable_i */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__SHIFT 6 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__MASK 0x00000040U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000040U) >> 6) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__WRITE(src) \ + (((u_int32_t)(src)\ + << 6) & 0x00000040U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000040U) | (((u_int32_t)(src) <<\ + 6) & 0x00000040U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 6) & ~0x00000040U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(1) << 6) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000040U) | ((u_int32_t)(0) << 6) + +/* macros for field ate_tonegen_prbs_enable_q */ +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__SHIFT 7 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__MASK 0x00000080U +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000080U) >> 7) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 7) & 0x00000080U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000080U) | (((u_int32_t)(src) <<\ + 7) & 0x00000080U) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 7) & ~0x00000080U))) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(1) << 7) +#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000080U) | ((u_int32_t)(0) << 7) + +/* macros for field ate_cmac_dc_write_to_cancel */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__SHIFT 8 +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__MASK 0x00000100U +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000100U) >> 8) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000100U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000100U) | (((u_int32_t)(src) <<\ + 8) & 0x00000100U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000100U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(1) << 8) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000100U) | ((u_int32_t)(0) << 8) + +/* macros for field ate_cmac_dc_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__SHIFT 9 +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__MASK 0x00000200U +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000200U) >> 9) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 9) & 0x00000200U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000200U) | (((u_int32_t)(src) <<\ + 9) & 0x00000200U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 9) & ~0x00000200U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(1) << 9) +#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000200U) | ((u_int32_t)(0) << 9) + +/* macros for field ate_cmac_corr_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__SHIFT 10 +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__MASK 0x00000400U +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000400U) >> 10) +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 10) & 0x00000400U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000400U) | (((u_int32_t)(src) <<\ + 10) & 0x00000400U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 10) & ~0x00000400U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(1) << 10) +#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000400U) | ((u_int32_t)(0) << 10) + +/* macros for field ate_cmac_power_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__SHIFT 11 +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__MASK 0x00000800U +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000800U) >> 11) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 11) & 0x00000800U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000800U) | (((u_int32_t)(src) <<\ + 11) & 0x00000800U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 11) & ~0x00000800U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(1) << 11) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000800U) | ((u_int32_t)(0) << 11) + +/* macros for field ate_cmac_iq_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__SHIFT 12 +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__MASK 0x00001000U +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001000U) >> 12) +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x00001000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001000U) | (((u_int32_t)(src) <<\ + 12) & 0x00001000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x00001000U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(1) << 12) +#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00001000U) | ((u_int32_t)(0) << 12) + +/* macros for field ate_cmac_i2q2_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__SHIFT 13 +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__MASK 0x00002000U +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00002000U) >> 13) +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 13) & 0x00002000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00002000U) | (((u_int32_t)(src) <<\ + 13) & 0x00002000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 13) & ~0x00002000U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(1) << 13) +#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00002000U) | ((u_int32_t)(0) << 13) + +/* macros for field ate_cmac_power_hpf_enable */ +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__SHIFT 14 +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__MASK 0x00004000U +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00004000U) >> 14) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 14) & 0x00004000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00004000U) | (((u_int32_t)(src) <<\ + 14) & 0x00004000U) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 14) & ~0x00004000U))) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(1) << 14) +#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00004000U) | ((u_int32_t)(0) << 14) + +/* macros for field ate_rxdac_calibrate */ +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__SHIFT 15 +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__MASK 0x00008000U +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00008000U) >> 15) +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__WRITE(src) \ + (((u_int32_t)(src)\ + << 15) & 0x00008000U) +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00008000U) | (((u_int32_t)(src) <<\ + 15) & 0x00008000U) +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 15) & ~0x00008000U))) +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(1) << 15) +#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00008000U) | ((u_int32_t)(0) << 15) + +/* macros for field ate_rbist_enable */ +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__SHIFT 16 +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__WIDTH 1 +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__MASK 0x00010000U +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__READ(src) \ + (((u_int32_t)(src)\ + & 0x00010000U) >> 16) +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00010000U) +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00010000U) | (((u_int32_t)(src) <<\ + 16) & 0x00010000U) +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00010000U))) +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__SET(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(1) << 16) +#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00010000U) | ((u_int32_t)(0) << 16) +#define RBIST_CNTRL_TYPE__TYPE u_int32_t +#define RBIST_CNTRL_TYPE__READ 0x0001ffffU +#define RBIST_CNTRL_TYPE__WRITE 0x0001ffffU + +#endif /* __RBIST_CNTRL_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_rbist_cntrl */ +#define INST_RADIO65_REG_MAP__CH0_RBIST_CNTRL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_dc_offset_type */ +#ifndef __TX_DC_OFFSET_TYPE_MACRO__ +#define __TX_DC_OFFSET_TYPE_MACRO__ + +/* macros for field ate_tonegen_dc_i */ +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__SHIFT 0 +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__WIDTH 11 +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__MASK 0x000007ffU +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__READ(src) \ + (u_int32_t)(src)\ + & 0x000007ffU +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000007ffU) +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000007ffU))) + +/* macros for field ate_tonegen_dc_q */ +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__SHIFT 16 +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__WIDTH 11 +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__MASK 0x07ff0000U +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x07ff0000U) >> 16) +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x07ff0000U) +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x07ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x07ff0000U) +#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x07ff0000U))) +#define TX_DC_OFFSET_TYPE__TYPE u_int32_t +#define TX_DC_OFFSET_TYPE__READ 0x07ff07ffU +#define TX_DC_OFFSET_TYPE__WRITE 0x07ff07ffU + +#endif /* __TX_DC_OFFSET_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_tx_dc_offset */ +#define INST_RADIO65_REG_MAP__CH0_TX_DC_OFFSET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_tonegen_type */ +#ifndef __TX_TONEGEN_TYPE_MACRO__ +#define __TX_TONEGEN_TYPE_MACRO__ + +/* macros for field ate_tonegen_tone_freq */ +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__SHIFT 0 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__WIDTH 7 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__MASK 0x0000007fU +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__READ(src) \ + (u_int32_t)(src)\ + & 0x0000007fU +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000007fU) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000007fU) | ((u_int32_t)(src) &\ + 0x0000007fU) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000007fU))) + +/* macros for field ate_tonegen_tone_A_exp */ +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__SHIFT 8 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__WIDTH 4 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__MASK 0x00000f00U +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000f00U) >> 8) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00000f00U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00000f00U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00000f00U))) + +/* macros for field ate_tonegen_tone_A_man */ +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__SHIFT 16 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__WIDTH 8 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__MASK 0x00ff0000U +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00ff0000U) >> 16) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x00ff0000U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x00ff0000U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x00ff0000U))) + +/* macros for field ate_tonegen_tone_tau_k */ +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__SHIFT 24 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__WIDTH 7 +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__MASK 0x7f000000U +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__READ(src) \ + (((u_int32_t)(src)\ + & 0x7f000000U) >> 24) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x7f000000U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x7f000000U) +#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x7f000000U))) +#define TX_TONEGEN_TYPE__TYPE u_int32_t +#define TX_TONEGEN_TYPE__READ 0x7fff0f7fU +#define TX_TONEGEN_TYPE__WRITE 0x7fff0f7fU + +#endif /* __TX_TONEGEN_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_tx_tonegen0 */ +#define INST_RADIO65_REG_MAP__CH0_TX_TONEGEN0__NUM 1 + +/* macros for radio65_reg_map.ch0_tx_tonegen1 */ +#define INST_RADIO65_REG_MAP__CH0_TX_TONEGEN1__NUM 1 + +/* macros for radio65_reg_map.ch0_tx_lftonegen0 */ +#define INST_RADIO65_REG_MAP__CH0_TX_LFTONEGEN0__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_linear_ramp_type */ +#ifndef __TX_LINEAR_RAMP_TYPE_MACRO__ +#define __TX_LINEAR_RAMP_TYPE_MACRO__ + +/* macros for field ate_tonegen_linramp_init */ +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__SHIFT 0 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__WIDTH 11 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__MASK 0x000007ffU +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__READ(src) \ + (u_int32_t)(src)\ + & 0x000007ffU +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000007ffU) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000007ffU) | ((u_int32_t)(src) &\ + 0x000007ffU) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000007ffU))) + +/* macros for field ate_tonegen_linramp_dwell */ +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__SHIFT 12 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__WIDTH 10 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__MASK 0x003ff000U +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__READ(src) \ + (((u_int32_t)(src)\ + & 0x003ff000U) >> 12) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__WRITE(src) \ + (((u_int32_t)(src)\ + << 12) & 0x003ff000U) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x003ff000U) | (((u_int32_t)(src) <<\ + 12) & 0x003ff000U) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 12) & ~0x003ff000U))) + +/* macros for field ate_tonegen_linramp_step */ +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__SHIFT 24 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__WIDTH 6 +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__MASK 0x3f000000U +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__READ(src) \ + (((u_int32_t)(src)\ + & 0x3f000000U) >> 24) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x3f000000U) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x3f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x3f000000U) +#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x3f000000U))) +#define TX_LINEAR_RAMP_TYPE__TYPE u_int32_t +#define TX_LINEAR_RAMP_TYPE__READ 0x3f3ff7ffU +#define TX_LINEAR_RAMP_TYPE__WRITE 0x3f3ff7ffU + +#endif /* __TX_LINEAR_RAMP_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_tx_linear_ramp_i */ +#define INST_RADIO65_REG_MAP__CH0_TX_LINEAR_RAMP_I__NUM 1 + +/* macros for radio65_reg_map.ch0_tx_linear_ramp_q */ +#define INST_RADIO65_REG_MAP__CH0_TX_LINEAR_RAMP_Q__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_prbs_mag_type */ +#ifndef __TX_PRBS_MAG_TYPE_MACRO__ +#define __TX_PRBS_MAG_TYPE_MACRO__ + +/* macros for field ate_tonegen_prbs_magnitude_i */ +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__SHIFT 0 +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__WIDTH 10 +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__MASK 0x000003ffU +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field ate_tonegen_prbs_magnitude_q */ +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__SHIFT 16 +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__WIDTH 10 +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__MASK 0x03ff0000U +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x03ff0000U) >> 16) +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x03ff0000U) +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x03ff0000U) +#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define TX_PRBS_MAG_TYPE__TYPE u_int32_t +#define TX_PRBS_MAG_TYPE__READ 0x03ff03ffU +#define TX_PRBS_MAG_TYPE__WRITE 0x03ff03ffU + +#endif /* __TX_PRBS_MAG_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_tx_prbs_mag */ +#define INST_RADIO65_REG_MAP__CH0_TX_PRBS_MAG__NUM 1 + +/* macros for BlueprintGlobalNameSpace::tx_prbs_seed_type */ +#ifndef __TX_PRBS_SEED_TYPE_MACRO__ +#define __TX_PRBS_SEED_TYPE_MACRO__ + +/* macros for field ate_tonegen_prbs_seed */ +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__SHIFT 0 +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__WIDTH 31 +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__MASK 0x7fffffffU +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__READ(src) \ + (u_int32_t)(src)\ + & 0x7fffffffU +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x7fffffffU) +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x7fffffffU) | ((u_int32_t)(src) &\ + 0x7fffffffU) +#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x7fffffffU))) +#define TX_PRBS_SEED_TYPE__TYPE u_int32_t +#define TX_PRBS_SEED_TYPE__READ 0x7fffffffU +#define TX_PRBS_SEED_TYPE__WRITE 0x7fffffffU + +#endif /* __TX_PRBS_SEED_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_tx_prbs_seed_i */ +#define INST_RADIO65_REG_MAP__CH0_TX_PRBS_SEED_I__NUM 1 + +/* macros for radio65_reg_map.ch0_tx_prbs_seed_q */ +#define INST_RADIO65_REG_MAP__CH0_TX_PRBS_SEED_Q__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_dc_cancel_type */ +#ifndef __CMAC_DC_CANCEL_TYPE_MACRO__ +#define __CMAC_DC_CANCEL_TYPE_MACRO__ + +/* macros for field ate_cmac_dc_cancel_i */ +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__SHIFT 0 +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__WIDTH 10 +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__MASK 0x000003ffU +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__READ(src) \ + (u_int32_t)(src)\ + & 0x000003ffU +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x000003ffU) +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000003ffU) | ((u_int32_t)(src) &\ + 0x000003ffU) +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x000003ffU))) + +/* macros for field ate_cmac_dc_cancel_q */ +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__SHIFT 16 +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__WIDTH 10 +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__MASK 0x03ff0000U +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__READ(src) \ + (((u_int32_t)(src)\ + & 0x03ff0000U) >> 16) +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x03ff0000U) +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x03ff0000U) | (((u_int32_t)(src) <<\ + 16) & 0x03ff0000U) +#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x03ff0000U))) +#define CMAC_DC_CANCEL_TYPE__TYPE u_int32_t +#define CMAC_DC_CANCEL_TYPE__READ 0x03ff03ffU +#define CMAC_DC_CANCEL_TYPE__WRITE 0x03ff03ffU + +#endif /* __CMAC_DC_CANCEL_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_cmac_dc_cancel */ +#define INST_RADIO65_REG_MAP__CH0_CMAC_DC_CANCEL__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_dc_offset_type */ +#ifndef __CMAC_DC_OFFSET_TYPE_MACRO__ +#define __CMAC_DC_OFFSET_TYPE_MACRO__ + +/* macros for field ate_cmac_dc_cycles */ +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__SHIFT 0 +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__WIDTH 4 +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__MASK 0x0000000fU +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define CMAC_DC_OFFSET_TYPE__TYPE u_int32_t +#define CMAC_DC_OFFSET_TYPE__READ 0x0000000fU +#define CMAC_DC_OFFSET_TYPE__WRITE 0x0000000fU + +#endif /* __CMAC_DC_OFFSET_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_cmac_dc_offset */ +#define INST_RADIO65_REG_MAP__CH0_CMAC_DC_OFFSET__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_corr_type */ +#ifndef __CMAC_CORR_TYPE_MACRO__ +#define __CMAC_CORR_TYPE_MACRO__ + +/* macros for field ate_cmac_corr_cycles */ +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__SHIFT 0 +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__WIDTH 5 +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__MASK 0x0000001fU +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field ate_cmac_corr_freq */ +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__SHIFT 8 +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__WIDTH 6 +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__MASK 0x00003f00U +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) +#define CMAC_CORR_TYPE__TYPE u_int32_t +#define CMAC_CORR_TYPE__READ 0x00003f1fU +#define CMAC_CORR_TYPE__WRITE 0x00003f1fU + +#endif /* __CMAC_CORR_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_cmac_corr */ +#define INST_RADIO65_REG_MAP__CH0_CMAC_CORR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_power_type */ +#ifndef __CMAC_POWER_TYPE_MACRO__ +#define __CMAC_POWER_TYPE_MACRO__ + +/* macros for field ate_cmac_power_cycles */ +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__SHIFT 0 +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__WIDTH 4 +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__MASK 0x0000000fU +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define CMAC_POWER_TYPE__TYPE u_int32_t +#define CMAC_POWER_TYPE__READ 0x0000000fU +#define CMAC_POWER_TYPE__WRITE 0x0000000fU + +#endif /* __CMAC_POWER_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_cmac_power */ +#define INST_RADIO65_REG_MAP__CH0_CMAC_POWER__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_cross_corr_type */ +#ifndef __CMAC_CROSS_CORR_TYPE_MACRO__ +#define __CMAC_CROSS_CORR_TYPE_MACRO__ + +/* macros for field ate_cmac_iq_cycles */ +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__SHIFT 0 +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__WIDTH 4 +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__MASK 0x0000000fU +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define CMAC_CROSS_CORR_TYPE__TYPE u_int32_t +#define CMAC_CROSS_CORR_TYPE__READ 0x0000000fU +#define CMAC_CROSS_CORR_TYPE__WRITE 0x0000000fU + +#endif /* __CMAC_CROSS_CORR_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_cmac_cross_corr */ +#define INST_RADIO65_REG_MAP__CH0_CMAC_CROSS_CORR__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_i2q2_type */ +#ifndef __CMAC_I2Q2_TYPE_MACRO__ +#define __CMAC_I2Q2_TYPE_MACRO__ + +/* macros for field ate_cmac_i2q2_cycles */ +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__SHIFT 0 +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__WIDTH 4 +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__MASK 0x0000000fU +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) +#define CMAC_I2Q2_TYPE__TYPE u_int32_t +#define CMAC_I2Q2_TYPE__READ 0x0000000fU +#define CMAC_I2Q2_TYPE__WRITE 0x0000000fU + +#endif /* __CMAC_I2Q2_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_cmac_i2q2 */ +#define INST_RADIO65_REG_MAP__CH0_CMAC_I2Q2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_power_hpf_type */ +#ifndef __CMAC_POWER_HPF_TYPE_MACRO__ +#define __CMAC_POWER_HPF_TYPE_MACRO__ + +/* macros for field ate_cmac_power_hpf_cycles */ +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__SHIFT 0 +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__WIDTH 4 +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__MASK 0x0000000fU +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__READ(src) \ + (u_int32_t)(src)\ + & 0x0000000fU +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000000fU) +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000000fU) | ((u_int32_t)(src) &\ + 0x0000000fU) +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000000fU))) + +/* macros for field ate_cmac_power_hpf_wait */ +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__SHIFT 4 +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__WIDTH 4 +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__MASK 0x000000f0U +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x000000f0U) >> 4) +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x000000f0U) +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000000f0U) | (((u_int32_t)(src) <<\ + 4) & 0x000000f0U) +#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x000000f0U))) +#define CMAC_POWER_HPF_TYPE__TYPE u_int32_t +#define CMAC_POWER_HPF_TYPE__READ 0x000000ffU +#define CMAC_POWER_HPF_TYPE__WRITE 0x000000ffU + +#endif /* __CMAC_POWER_HPF_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_cmac_power_hpf */ +#define INST_RADIO65_REG_MAP__CH0_CMAC_POWER_HPF__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rxdac_set1_type */ +#ifndef __RXDAC_SET1_TYPE_MACRO__ +#define __RXDAC_SET1_TYPE_MACRO__ + +/* macros for field ate_rxdac_mux */ +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__SHIFT 0 +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__WIDTH 2 +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__MASK 0x00000003U +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__READ(src) \ + (u_int32_t)(src)\ + & 0x00000003U +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x00000003U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000003U) | ((u_int32_t)(src) &\ + 0x00000003U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x00000003U))) + +/* macros for field ate_rxdac_hi_gain */ +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__SHIFT 4 +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__WIDTH 1 +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__MASK 0x00000010U +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__READ(src) \ + (((u_int32_t)(src)\ + & 0x00000010U) >> 4) +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__WRITE(src) \ + (((u_int32_t)(src)\ + << 4) & 0x00000010U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00000010U) | (((u_int32_t)(src) <<\ + 4) & 0x00000010U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 4) & ~0x00000010U))) +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__SET(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(1) << 4) +#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__CLR(dst) \ + (dst) = ((dst) &\ + ~0x00000010U) | ((u_int32_t)(0) << 4) + +/* macros for field ate_rxdac_cal_wait */ +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__SHIFT 8 +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__WIDTH 6 +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__MASK 0x00003f00U +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__READ(src) \ + (((u_int32_t)(src)\ + & 0x00003f00U) >> 8) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00003f00U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00003f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00003f00U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00003f00U))) + +/* macros for field ate_rxdac_cal_measure_time */ +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__SHIFT 16 +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__WIDTH 4 +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__MASK 0x000f0000U +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__READ(src) \ + (((u_int32_t)(src)\ + & 0x000f0000U) >> 16) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x000f0000U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x000f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x000f0000U) +#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x000f0000U))) +#define RXDAC_SET1_TYPE__TYPE u_int32_t +#define RXDAC_SET1_TYPE__READ 0x000f3f13U +#define RXDAC_SET1_TYPE__WRITE 0x000f3f13U + +#endif /* __RXDAC_SET1_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_rxdac_set1 */ +#define INST_RADIO65_REG_MAP__CH0_RXDAC_SET1__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rxdac_set2_type */ +#ifndef __RXDAC_SET2_TYPE_MACRO__ +#define __RXDAC_SET2_TYPE_MACRO__ + +/* macros for field ate_rxdac_i_hi */ +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__SHIFT 0 +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__WIDTH 5 +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__MASK 0x0000001fU +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field ate_rxdac_q_hi */ +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__SHIFT 8 +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__WIDTH 5 +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__MASK 0x00001f00U +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) + +/* macros for field ate_rxdac_i_low */ +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__SHIFT 16 +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__WIDTH 5 +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__MASK 0x001f0000U +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x001f0000U) >> 16) +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 16) & 0x001f0000U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x001f0000U) | (((u_int32_t)(src) <<\ + 16) & 0x001f0000U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 16) & ~0x001f0000U))) + +/* macros for field ate_rxdac_q_low */ +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__SHIFT 24 +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__WIDTH 5 +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__MASK 0x1f000000U +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__READ(src) \ + (((u_int32_t)(src)\ + & 0x1f000000U) >> 24) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__WRITE(src) \ + (((u_int32_t)(src)\ + << 24) & 0x1f000000U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x1f000000U) | (((u_int32_t)(src) <<\ + 24) & 0x1f000000U) +#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 24) & ~0x1f000000U))) +#define RXDAC_SET2_TYPE__TYPE u_int32_t +#define RXDAC_SET2_TYPE__READ 0x1f1f1f1fU +#define RXDAC_SET2_TYPE__WRITE 0x1f1f1f1fU + +#endif /* __RXDAC_SET2_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_rxdac_set2 */ +#define INST_RADIO65_REG_MAP__CH0_RXDAC_SET2__NUM 1 + +/* macros for BlueprintGlobalNameSpace::rxdac_long_shift_type */ +#ifndef __RXDAC_LONG_SHIFT_TYPE_MACRO__ +#define __RXDAC_LONG_SHIFT_TYPE_MACRO__ + +/* macros for field ate_rxdac_i_static */ +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__SHIFT 0 +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__WIDTH 5 +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__MASK 0x0000001fU +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__READ(src) \ + (u_int32_t)(src)\ + & 0x0000001fU +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__WRITE(src) \ + ((u_int32_t)(src)\ + & 0x0000001fU) +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x0000001fU) | ((u_int32_t)(src) &\ + 0x0000001fU) +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0x0000001fU))) + +/* macros for field ate_rxdac_q_static */ +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__SHIFT 8 +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__WIDTH 5 +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__MASK 0x00001f00U +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__READ(src) \ + (((u_int32_t)(src)\ + & 0x00001f00U) >> 8) +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__WRITE(src) \ + (((u_int32_t)(src)\ + << 8) & 0x00001f00U) +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0x00001f00U) | (((u_int32_t)(src) <<\ + 8) & 0x00001f00U) +#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__VERIFY(src) \ + (!((((u_int32_t)(src)\ + << 8) & ~0x00001f00U))) +#define RXDAC_LONG_SHIFT_TYPE__TYPE u_int32_t +#define RXDAC_LONG_SHIFT_TYPE__READ 0x00001f1fU +#define RXDAC_LONG_SHIFT_TYPE__WRITE 0x00001f1fU + +#endif /* __RXDAC_LONG_SHIFT_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_rxdac_long_shift */ +#define INST_RADIO65_REG_MAP__CH0_RXDAC_LONG_SHIFT__NUM 1 + +/* macros for BlueprintGlobalNameSpace::cmac_results_type */ +#ifndef __CMAC_RESULTS_TYPE_MACRO__ +#define __CMAC_RESULTS_TYPE_MACRO__ + +/* macros for field ate_cmac_results */ +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__SHIFT 0 +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__WIDTH 32 +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__MASK 0xffffffffU +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__READ(src) \ + (u_int32_t)(src)\ + & 0xffffffffU +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__WRITE(src) \ + ((u_int32_t)(src)\ + & 0xffffffffU) +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__MODIFY(dst, src) \ + (dst) = ((dst) &\ + ~0xffffffffU) | ((u_int32_t)(src) &\ + 0xffffffffU) +#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__VERIFY(src) \ + (!(((u_int32_t)(src)\ + & ~0xffffffffU))) +#define CMAC_RESULTS_TYPE__TYPE u_int32_t +#define CMAC_RESULTS_TYPE__READ 0xffffffffU +#define CMAC_RESULTS_TYPE__WRITE 0xffffffffU + +#endif /* __CMAC_RESULTS_TYPE_MACRO__ */ + + +/* macros for radio65_reg_map.ch0_cmac_results_i */ +#define INST_RADIO65_REG_MAP__CH0_CMAC_RESULTS_I__NUM 1 + +/* macros for radio65_reg_map.ch0_cmac_results_q */ +#define INST_RADIO65_REG_MAP__CH0_CMAC_RESULTS_Q__NUM 1 + +/* macros for radio65_reg_map.ch1_RXRF_BIAS1 */ +#define INST_RADIO65_REG_MAP__CH1_RXRF_BIAS1__NUM 1 + +/* macros for radio65_reg_map.ch1_RXRF_BIAS2 */ +#define INST_RADIO65_REG_MAP__CH1_RXRF_BIAS2__NUM 1 + +/* macros for radio65_reg_map.ch1_RXRF_GAINSTAGES */ +#define INST_RADIO65_REG_MAP__CH1_RXRF_GAINSTAGES__NUM 1 + +/* macros for radio65_reg_map.ch1_RXRF_AGC */ +#define INST_RADIO65_REG_MAP__CH1_RXRF_AGC__NUM 1 + +/* macros for radio65_reg_map.ch1_TXRF1 */ +#define INST_RADIO65_REG_MAP__CH1_TXRF1__NUM 1 + +/* macros for radio65_reg_map.ch1_TXRF2 */ +#define INST_RADIO65_REG_MAP__CH1_TXRF2__NUM 1 + +/* macros for radio65_reg_map.ch1_TXRF3 */ +#define INST_RADIO65_REG_MAP__CH1_TXRF3__NUM 1 + +/* macros for radio65_reg_map.ch1_TXRF4 */ +#define INST_RADIO65_REG_MAP__CH1_TXRF4__NUM 1 + +/* macros for radio65_reg_map.ch1_TXRF5 */ +#define INST_RADIO65_REG_MAP__CH1_TXRF5__NUM 1 + +/* macros for radio65_reg_map.ch1_TXRF6 */ +#define INST_RADIO65_REG_MAP__CH1_TXRF6__NUM 1 + +/* macros for radio65_reg_map.ch1_RXTX1 */ +#define INST_RADIO65_REG_MAP__CH1_RXTX1__NUM 1 + +/* macros for radio65_reg_map.ch1_RXTX2 */ +#define INST_RADIO65_REG_MAP__CH1_RXTX2__NUM 1 + +/* macros for radio65_reg_map.ch1_RXTX3 */ +#define INST_RADIO65_REG_MAP__CH1_RXTX3__NUM 1 + +/* macros for radio65_reg_map.ch1_RXTX4 */ +#define INST_RADIO65_REG_MAP__CH1_RXTX4__NUM 1 + +/* macros for radio65_reg_map.ch1_BB1 */ +#define INST_RADIO65_REG_MAP__CH1_BB1__NUM 1 + +/* macros for radio65_reg_map.ch1_BB2 */ +#define INST_RADIO65_REG_MAP__CH1_BB2__NUM 1 + +/* macros for radio65_reg_map.ch1_BB3 */ +#define INST_RADIO65_REG_MAP__CH1_BB3__NUM 1 + +/* macros for radio65_reg_map.ch1_rbist_cntrl */ +#define INST_RADIO65_REG_MAP__CH1_RBIST_CNTRL__NUM 1 + +/* macros for radio65_reg_map.ch1_tx_dc_offset */ +#define INST_RADIO65_REG_MAP__CH1_TX_DC_OFFSET__NUM 1 + +/* macros for radio65_reg_map.ch1_tx_tonegen0 */ +#define INST_RADIO65_REG_MAP__CH1_TX_TONEGEN0__NUM 1 + +/* macros for radio65_reg_map.ch1_tx_tonegen1 */ +#define INST_RADIO65_REG_MAP__CH1_TX_TONEGEN1__NUM 1 + +/* macros for radio65_reg_map.ch1_tx_lftonegen0 */ +#define INST_RADIO65_REG_MAP__CH1_TX_LFTONEGEN0__NUM 1 + +/* macros for radio65_reg_map.ch1_tx_linear_ramp_i */ +#define INST_RADIO65_REG_MAP__CH1_TX_LINEAR_RAMP_I__NUM 1 + +/* macros for radio65_reg_map.ch1_tx_linear_ramp_q */ +#define INST_RADIO65_REG_MAP__CH1_TX_LINEAR_RAMP_Q__NUM 1 + +/* macros for radio65_reg_map.ch1_tx_prbs_mag */ +#define INST_RADIO65_REG_MAP__CH1_TX_PRBS_MAG__NUM 1 + +/* macros for radio65_reg_map.ch1_tx_prbs_seed_i */ +#define INST_RADIO65_REG_MAP__CH1_TX_PRBS_SEED_I__NUM 1 + +/* macros for radio65_reg_map.ch1_tx_prbs_seed_q */ +#define INST_RADIO65_REG_MAP__CH1_TX_PRBS_SEED_Q__NUM 1 + +/* macros for radio65_reg_map.ch1_cmac_dc_cancel */ +#define INST_RADIO65_REG_MAP__CH1_CMAC_DC_CANCEL__NUM 1 + +/* macros for radio65_reg_map.ch1_cmac_dc_offset */ +#define INST_RADIO65_REG_MAP__CH1_CMAC_DC_OFFSET__NUM 1 + +/* macros for radio65_reg_map.ch1_cmac_corr */ +#define INST_RADIO65_REG_MAP__CH1_CMAC_CORR__NUM 1 + +/* macros for radio65_reg_map.ch1_cmac_power */ +#define INST_RADIO65_REG_MAP__CH1_CMAC_POWER__NUM 1 + +/* macros for radio65_reg_map.ch1_cmac_cross_corr */ +#define INST_RADIO65_REG_MAP__CH1_CMAC_CROSS_CORR__NUM 1 + +/* macros for radio65_reg_map.ch1_cmac_i2q2 */ +#define INST_RADIO65_REG_MAP__CH1_CMAC_I2Q2__NUM 1 + +/* macros for radio65_reg_map.ch1_cmac_power_hpf */ +#define INST_RADIO65_REG_MAP__CH1_CMAC_POWER_HPF__NUM 1 + +/* macros for radio65_reg_map.ch1_rxdac_set1 */ +#define INST_RADIO65_REG_MAP__CH1_RXDAC_SET1__NUM 1 + +/* macros for radio65_reg_map.ch1_rxdac_set2 */ +#define INST_RADIO65_REG_MAP__CH1_RXDAC_SET2__NUM 1 + +/* macros for radio65_reg_map.ch1_rxdac_long_shift */ +#define INST_RADIO65_REG_MAP__CH1_RXDAC_LONG_SHIFT__NUM 1 + +/* macros for radio65_reg_map.ch1_cmac_results_i */ +#define INST_RADIO65_REG_MAP__CH1_CMAC_RESULTS_I__NUM 1 + +/* macros for radio65_reg_map.ch1_cmac_results_q */ +#define INST_RADIO65_REG_MAP__CH1_CMAC_RESULTS_Q__NUM 1 + +/* macros for radio65_reg_map.ch2_RXRF_BIAS1 */ +#define INST_RADIO65_REG_MAP__CH2_RXRF_BIAS1__NUM 1 + +/* macros for radio65_reg_map.ch2_RXRF_BIAS2 */ +#define INST_RADIO65_REG_MAP__CH2_RXRF_BIAS2__NUM 1 + +/* macros for radio65_reg_map.ch2_RXRF_GAINSTAGES */ +#define INST_RADIO65_REG_MAP__CH2_RXRF_GAINSTAGES__NUM 1 + +/* macros for radio65_reg_map.ch2_RXRF_AGC */ +#define INST_RADIO65_REG_MAP__CH2_RXRF_AGC__NUM 1 + +/* macros for radio65_reg_map.ch2_TXRF1 */ +#define INST_RADIO65_REG_MAP__CH2_TXRF1__NUM 1 + +/* macros for radio65_reg_map.ch2_TXRF2 */ +#define INST_RADIO65_REG_MAP__CH2_TXRF2__NUM 1 + +/* macros for radio65_reg_map.ch2_TXRF3 */ +#define INST_RADIO65_REG_MAP__CH2_TXRF3__NUM 1 + +/* macros for radio65_reg_map.ch2_TXRF4 */ +#define INST_RADIO65_REG_MAP__CH2_TXRF4__NUM 1 + +/* macros for radio65_reg_map.ch2_TXRF5 */ +#define INST_RADIO65_REG_MAP__CH2_TXRF5__NUM 1 + +/* macros for radio65_reg_map.ch2_TXRF6 */ +#define INST_RADIO65_REG_MAP__CH2_TXRF6__NUM 1 + +/* macros for radio65_reg_map.ch2_RXTX1 */ +#define INST_RADIO65_REG_MAP__CH2_RXTX1__NUM 1 + +/* macros for radio65_reg_map.ch2_RXTX2 */ +#define INST_RADIO65_REG_MAP__CH2_RXTX2__NUM 1 + +/* macros for radio65_reg_map.ch2_RXTX3 */ +#define INST_RADIO65_REG_MAP__CH2_RXTX3__NUM 1 + +/* macros for radio65_reg_map.ch2_RXTX4 */ +#define INST_RADIO65_REG_MAP__CH2_RXTX4__NUM 1 + +/* macros for radio65_reg_map.ch2_BB1 */ +#define INST_RADIO65_REG_MAP__CH2_BB1__NUM 1 + +/* macros for radio65_reg_map.ch2_BB2 */ +#define INST_RADIO65_REG_MAP__CH2_BB2__NUM 1 + +/* macros for radio65_reg_map.ch2_BB3 */ +#define INST_RADIO65_REG_MAP__CH2_BB3__NUM 1 + +/* macros for radio65_reg_map.ch2_rbist_cntrl */ +#define INST_RADIO65_REG_MAP__CH2_RBIST_CNTRL__NUM 1 + +/* macros for radio65_reg_map.ch2_tx_dc_offset */ +#define INST_RADIO65_REG_MAP__CH2_TX_DC_OFFSET__NUM 1 + +/* macros for radio65_reg_map.ch2_tx_tonegen0 */ +#define INST_RADIO65_REG_MAP__CH2_TX_TONEGEN0__NUM 1 + +/* macros for radio65_reg_map.ch2_tx_tonegen1 */ +#define INST_RADIO65_REG_MAP__CH2_TX_TONEGEN1__NUM 1 + +/* macros for radio65_reg_map.ch2_tx_lftonegen0 */ +#define INST_RADIO65_REG_MAP__CH2_TX_LFTONEGEN0__NUM 1 + +/* macros for radio65_reg_map.ch2_tx_linear_ramp_i */ +#define INST_RADIO65_REG_MAP__CH2_TX_LINEAR_RAMP_I__NUM 1 + +/* macros for radio65_reg_map.ch2_tx_linear_ramp_q */ +#define INST_RADIO65_REG_MAP__CH2_TX_LINEAR_RAMP_Q__NUM 1 + +/* macros for radio65_reg_map.ch2_tx_prbs_mag */ +#define INST_RADIO65_REG_MAP__CH2_TX_PRBS_MAG__NUM 1 + +/* macros for radio65_reg_map.ch2_tx_prbs_seed_i */ +#define INST_RADIO65_REG_MAP__CH2_TX_PRBS_SEED_I__NUM 1 + +/* macros for radio65_reg_map.ch2_tx_prbs_seed_q */ +#define INST_RADIO65_REG_MAP__CH2_TX_PRBS_SEED_Q__NUM 1 + +/* macros for radio65_reg_map.ch2_cmac_dc_cancel */ +#define INST_RADIO65_REG_MAP__CH2_CMAC_DC_CANCEL__NUM 1 + +/* macros for radio65_reg_map.ch2_cmac_dc_offset */ +#define INST_RADIO65_REG_MAP__CH2_CMAC_DC_OFFSET__NUM 1 + +/* macros for radio65_reg_map.ch2_cmac_corr */ +#define INST_RADIO65_REG_MAP__CH2_CMAC_CORR__NUM 1 + +/* macros for radio65_reg_map.ch2_cmac_power */ +#define INST_RADIO65_REG_MAP__CH2_CMAC_POWER__NUM 1 + +/* macros for radio65_reg_map.ch2_cmac_cross_corr */ +#define INST_RADIO65_REG_MAP__CH2_CMAC_CROSS_CORR__NUM 1 + +/* macros for radio65_reg_map.ch2_cmac_i2q2 */ +#define INST_RADIO65_REG_MAP__CH2_CMAC_I2Q2__NUM 1 + +/* macros for radio65_reg_map.ch2_cmac_power_hpf */ +#define INST_RADIO65_REG_MAP__CH2_CMAC_POWER_HPF__NUM 1 + +/* macros for radio65_reg_map.ch2_rxdac_set1 */ +#define INST_RADIO65_REG_MAP__CH2_RXDAC_SET1__NUM 1 + +/* macros for radio65_reg_map.ch2_rxdac_set2 */ +#define INST_RADIO65_REG_MAP__CH2_RXDAC_SET2__NUM 1 + +/* macros for radio65_reg_map.ch2_rxdac_long_shift */ +#define INST_RADIO65_REG_MAP__CH2_RXDAC_LONG_SHIFT__NUM 1 + +/* macros for radio65_reg_map.ch2_cmac_results_i */ +#define INST_RADIO65_REG_MAP__CH2_CMAC_RESULTS_I__NUM 1 + +/* macros for radio65_reg_map.ch2_cmac_results_q */ +#define INST_RADIO65_REG_MAP__CH2_CMAC_RESULTS_Q__NUM 1 +#define RFILE_INST_MAC_DMA_REG_MAP__NUM 1 +#define RFILE_INST_MAC_QCU_REG_MAP__NUM 1 +#define RFILE_INST_MAC_DCU_REG_MAP__NUM 1 +#define RFILE_INST_RTC_REG_MAP__NUM 1 +#define RFILE_INST_RTC_SYNC_REG_MAP__NUM 1 +#define RFILE_INST_MAC_PCU_REG_MAP__NUM 1 +#define RFILE_INST_BB_REG_MAP__NUM 1 +#define RFILE_INST_MAC_PCU_BUF_REG_MAP__NUM 1 +#define RFILE_INST_SVD_REG_MAP__NUM 1 +#define RFILE_INST_RADIO65_REG_MAP__NUM 1 + +#define SCORPION_REG_MAP__VERSION \ + "/cad/local/lib/perl/Pinfo.pm\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_radio_reg.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.pm\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/bb/blueprint/bb_reg_map.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/rtc/rtc_reg.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/svd/svd_reg.rdl\n\ + /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/wmac_wrap/rtc_sync_reg.rdl" +#endif /* __REG_SCORPION_REG_MAP_MACRO_H__ */ diff --git a/hal/ar9300/sources b/hal/ar9300/sources new file mode 100644 index 000000000000..e560b0bfb0cc --- /dev/null +++ b/hal/ar9300/sources @@ -0,0 +1,81 @@ +# +# SOURCES file for ar9300 module +# + +HAL_TOP=.. + +!IFDEF TOP_HAL_DIR +TOP=$(HAL_TOP)\$(TOP_HAL_DIR) +!ELSE +# The default is to assume the relative position of HAL in the Fusion tree. +TOP=$(HAL_TOP)\..\..\.. +!ENDIF + +INC=$(TOP)\include +ASF=$(TOP)\asf +ADF=$(TOP)\adf + +!IFDEF BUILD_UMAC +INC_MP=$(TOP)\os\win_nwf\include +!ELSE +INC_MP=$(INC)\winvista +!ENDIF + +!include $(INC_MP)\sources.inc + +TARGETNAME=ath_hal_ar9300 +TARGETPATH=$(TOP)\lib +TARGETTYPE=LIBRARY + +INCLUDES= $(INCLUDES) \ + $(HAL_TOP); \ + $(INC); \ + $(INC_MP); \ + $(ASF)\include; \ + $(ADF)\include\os; \ + $(ADF)\include\net; \ + $(ADF)\include\nbuf; \ + $(ADF)\os\win_nwf; \ + $(ADF)\net\win_nwf; \ + $(ADF)\nbuf\win_nwf; \ + $(SDXROOT)\net\inc; \ + $(DDK_INC_PATH) + +HAL_OSDEP_INCLUDES=$(HAL_TOP)\winvista; + +INCLUDES=$(HAL_OSDEP_INCLUDES) $(INCLUDES) + +!IF "$(DDKBUILDENV)"=="chk" +C_DEFINES=$(C_DEFINES) -DAH_DEBUG=1 +!ENDIF + +C_DEFINES=$(C_DEFINES) -DAH_SUPPORT_WRITE_EEPROM -DATH_SLOW_ANT_DIV=1 -DATH_BT_COEX + +SOURCES=$(SOURCES) \ + ar9300_radio.c \ + ar9300_gpio.c \ + ar9300_radar.c \ + ar9300_xmit.c \ + ar9300_xmit_ds.c \ + ar9300_interrupts.c \ + ar9300_recv.c \ + ar9300_recv_ds.c \ + ar9300_ani.c \ + ar9300_keycache.c \ + ar9300_attach.c \ + ar9300_misc.c \ + ar9300_beacon.c \ + ar9300_phy.c \ + ar9300_eeprom.c \ + ar9300_power.c \ + ar9300_reset.c \ + ar9300_timer.c \ + ar9300_spectral.c \ + ar9300_txbf.c \ + ar9300_raw_adc_capture.c \ + ar9300_txbf_cal.c \ + ar9300_paprd.c \ + ar9300_sim.c \ + ar9300_mci.c \ + ar9300_rtt.c \ + ar9300_aic.c diff --git a/hal/ar9300/wasp_reg_map.h b/hal/ar9300/wasp_reg_map.h new file mode 100644 index 000000000000..2cc1c483786a --- /dev/null +++ b/hal/ar9300/wasp_reg_map.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __REG_WASP_REG_MAP_H__ + +struct host_intf_reg_ar9340 { + volatile char pad__0[0x4000]; /* 0x0 - 0x4000 */ + volatile u_int32_t HOST_INTF_RESET_CONTROL; /* 0x4000 - 0x4004 */ + volatile u_int32_t HOST_INTF_PM_CTRL; /* 0x4004 - 0x4008 */ + volatile u_int32_t HOST_INTF_TIMEOUT; /* 0x4008 - 0x400c */ + volatile u_int32_t HOST_INTF_SREV; /* 0x400c - 0x4010 */ + volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE; /* 0x4010 - 0x4014 */ + volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE; /* 0x4014 - 0x4018 */ + volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK; /* 0x4018 - 0x401c */ + volatile u_int32_t HOST_INTF_INTR_SYNC_MASK; /* 0x401c - 0x4020 */ + volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE; /* 0x4020 - 0x4024 */ + volatile u_int32_t HOST_INTF_INTR_ASYNC_ENABLE; /* 0x4024 - 0x4028 */ + volatile u_int32_t HOST_INTF_GPIO_OUT; /* 0x4028 - 0x402c */ + volatile u_int32_t HOST_INTF_GPIO_IN; /* 0x402c - 0x4030 */ + volatile u_int32_t HOST_INTF_GPIO_OE; /* 0x4030 - 0x4034 */ + volatile u_int32_t HOST_INTF_GPIO_OE1; /* 0x4034 - 0x4038 */ + volatile u_int32_t HOST_INTF_GPIO_INTR_POLAR; /* 0x4038 - 0x403c */ + volatile u_int32_t HOST_INTF_GPIO_INPUT_VALUE; /* 0x403c - 0x4040 */ + volatile u_int32_t HOST_INTF_GPIO_INPUT_MUX1; /* 0x4040 - 0x4044 */ + volatile u_int32_t HOST_INTF_GPIO_INPUT_MUX2; /* 0x4044 - 0x4048 */ + volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX1; /* 0x4048 - 0x404c */ + volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX2; /* 0x404c - 0x4050 */ + volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX3; /* 0x4050 - 0x4054 */ + volatile u_int32_t HOST_INTF_GPIO_INPUT_STATE; /* 0x4054 - 0x4058 */ + volatile u_int32_t HOST_INTF_CLKRUN; /* 0x4058 - 0x405c */ + volatile u_int32_t HOST_INTF_OBS_CTRL; /* 0x405c - 0x4060 */ + volatile u_int32_t HOST_INTF_RFSILENT; /* 0x4060 - 0x4064 */ + volatile char pad__3[0x10]; /* 0x4064 - 0x4074 */ + volatile u_int32_t HOST_INTF_MISC; /* 0x4074 - 0x4078 */ + volatile u_int32_t HOST_INTF_MAC_TDMA_CCA_CNTL; /* 0x4078 - 0x407c */ + volatile u_int32_t HOST_INTF_MAC_TXAPSYNC; /* 0x407c - 0x4080 */ + volatile u_int32_t HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR; + /* 0x4080 - 0x4084 */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_CAUSE; + /* 0x4084 - 0x4088 */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_ENABLE; + /* 0x4088 - 0x408c */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_MASK; + /* 0x408c - 0x4090 */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_MASK; + /* 0x4090 - 0x4094 */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE; + /* 0x4094 - 0x4098 */ + volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE; + /* 0x4098 - 0x409c */ + volatile u_int32_t HOST_INTF_AXI_BYTE_SWAP; /* 0x409c - 0x40a0 */ + volatile char pad__4[0x20]; /* 0x40a4 - 0x40c4 */ + volatile u_int32_t HOST_INTF_WORK_AROUND; /* 0x40c4 - 0x40c8 */ + volatile u_int32_t HOST_INTF_EEPROM_STS; /* 0x40c8 - 0x40cc */ + volatile u_int32_t HOST_INTF_PCIE_MSI; /* 0x40d8 - 0x40dc */ +}; + +#endif /* __REG_WASP_REG_MAP_H__ */ -- cgit v1.2.3